2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
49 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct atmel_pdc_regs pdc_tx_reg = {
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
61 static struct atmel_pdc_regs pdc_rx_reg = {
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
69 * SSC & PDC status bits for transmit and receive.
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .ssc_error = SSC_BIT(SR_OVRUN),
77 .pdc_enable = ATMEL_PDC_TXTEN,
78 .pdc_disable = ATMEL_PDC_TXTDIS,
81 static struct atmel_ssc_mask ssc_rx_mask = {
82 .ssc_enable = SSC_BIT(CR_RXEN),
83 .ssc_disable = SSC_BIT(CR_RXDIS),
84 .ssc_endx = SSC_BIT(SR_ENDRX),
85 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
86 .ssc_error = SSC_BIT(SR_OVRUN),
87 .pdc_enable = ATMEL_PDC_RXTEN,
88 .pdc_disable = ATMEL_PDC_RXTDIS,
95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
97 .name = "SSC0 PCM out",
102 .name = "SSC0 PCM in",
104 .mask = &ssc_rx_mask,
107 .name = "SSC1 PCM out",
109 .mask = &ssc_tx_mask,
112 .name = "SSC1 PCM in",
114 .mask = &ssc_rx_mask,
117 .name = "SSC2 PCM out",
119 .mask = &ssc_tx_mask,
122 .name = "SSC2 PCM in",
124 .mask = &ssc_rx_mask,
129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133 .dir_mask = SSC_DIR_MASK_UNUSED,
138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139 .dir_mask = SSC_DIR_MASK_UNUSED,
144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145 .dir_mask = SSC_DIR_MASK_UNUSED,
152 * SSC interrupt handler. Passes PDC interrupts to the DMA
153 * interrupt handler in the PCM driver.
155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
157 struct atmel_ssc_info *ssc_p = dev_id;
158 struct atmel_pcm_dma_params *dma_params;
160 u32 ssc_substream_mask;
163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
167 * Loop through the substreams attached to this SSC. If
168 * a DMA-related interrupt occurred on that substream, call
169 * the DMA interrupt handler function, if one has been
170 * registered in the dma_params structure by the PCM driver.
172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173 dma_params = ssc_p->dma_params[i];
175 if ((dma_params != NULL) &&
176 (dma_params->dma_intr_handler != NULL)) {
177 ssc_substream_mask = (dma_params->mask->ssc_endx |
178 dma_params->mask->ssc_endbuf);
179 if (ssc_sr & ssc_substream_mask) {
180 dma_params->dma_intr_handler(ssc_sr,
191 * When the bit clock is input, limit the maximum rate according to the
192 * Serial Clock Ratio Considerations section from the SSC documentation:
194 * The Transmitter and the Receiver can be programmed to operate
195 * with the clock signals provided on either the TK or RK pins.
196 * This allows the SSC to support many slave-mode data transfers.
197 * In this case, the maximum clock speed allowed on the RK pin is:
198 * - Peripheral clock divided by 2 if Receiver Frame Synchro is input
199 * - Peripheral clock divided by 3 if Receiver Frame Synchro is output
200 * In addition, the maximum clock speed allowed on the TK pin is:
201 * - Peripheral clock divided by 6 if Transmit Frame Synchro is input
202 * - Peripheral clock divided by 2 if Transmit Frame Synchro is output
204 * When the bit clock is output, limit the rate according to the
205 * SSC divider restrictions.
207 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
208 struct snd_pcm_hw_rule *rule)
210 struct atmel_ssc_info *ssc_p = rule->private;
211 struct ssc_device *ssc = ssc_p->ssc;
212 struct snd_interval *i = hw_param_interval(params, rule->var);
213 struct snd_interval t;
214 struct snd_ratnum r = {
219 unsigned int num = 0, den = 0;
224 frame_size = snd_soc_params_to_frame_size(params);
228 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
229 case SND_SOC_DAIFMT_CBM_CFS:
230 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE)
231 && ssc->clk_from_rk_pin)
232 /* Receiver Frame Synchro (i.e. capture)
233 * is output (format is _CFS) and the RK pin
234 * is used for input (format is _CBM_).
239 case SND_SOC_DAIFMT_CBM_CFM:
240 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK)
241 && !ssc->clk_from_rk_pin)
242 /* Transmit Frame Synchro (i.e. playback)
243 * is input (format is _CFM) and the TK pin
244 * is used for input (format _CBM_ but not
251 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
252 case SND_SOC_DAIFMT_CBS_CFS:
253 r.num = ssc_p->mck_rate / mck_div / frame_size;
255 ret = snd_interval_ratnum(i, 1, &r, &num, &den);
256 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) {
257 params->rate_num = num;
258 params->rate_den = den;
262 case SND_SOC_DAIFMT_CBM_CFS:
263 case SND_SOC_DAIFMT_CBM_CFM:
265 t.max = ssc_p->mck_rate / mck_div / frame_size;
266 t.openmin = t.openmax = 0;
268 ret = snd_interval_refine(i, &t);
279 /*-------------------------------------------------------------------------*\
281 \*-------------------------------------------------------------------------*/
283 * Startup. Only that one substream allowed in each direction.
285 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai)
288 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
289 struct atmel_pcm_dma_params *dma_params;
293 pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n",
294 ssc_readl(ssc_p->ssc->regs, SR));
296 /* Enable PMC peripheral clock for this SSC */
297 pr_debug("atmel_ssc_dai: Starting clock\n");
298 clk_enable(ssc_p->ssc->clk);
299 ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
301 /* Reset the SSC unless initialized to keep it in a clean state */
302 if (!ssc_p->initialized)
303 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
305 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
307 dir_mask = SSC_DIR_MASK_PLAYBACK;
310 dir_mask = SSC_DIR_MASK_CAPTURE;
313 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
314 SNDRV_PCM_HW_PARAM_RATE,
315 atmel_ssc_hw_rule_rate,
317 SNDRV_PCM_HW_PARAM_FRAME_BITS,
318 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
320 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret);
324 dma_params = &ssc_dma_params[dai->id][dir];
325 dma_params->ssc = ssc_p->ssc;
326 dma_params->substream = substream;
328 ssc_p->dma_params[dir] = dma_params;
330 snd_soc_dai_set_dma_data(dai, substream, dma_params);
332 spin_lock_irq(&ssc_p->lock);
333 if (ssc_p->dir_mask & dir_mask) {
334 spin_unlock_irq(&ssc_p->lock);
337 ssc_p->dir_mask |= dir_mask;
338 spin_unlock_irq(&ssc_p->lock);
344 * Shutdown. Clear DMA parameters and shutdown the SSC if there
345 * are no other substreams open.
347 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
348 struct snd_soc_dai *dai)
350 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
351 struct atmel_pcm_dma_params *dma_params;
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
359 dma_params = ssc_p->dma_params[dir];
361 if (dma_params != NULL) {
362 dma_params->ssc = NULL;
363 dma_params->substream = NULL;
364 ssc_p->dma_params[dir] = NULL;
369 spin_lock_irq(&ssc_p->lock);
370 ssc_p->dir_mask &= ~dir_mask;
371 if (!ssc_p->dir_mask) {
372 if (ssc_p->initialized) {
373 free_irq(ssc_p->ssc->irq, ssc_p);
374 ssc_p->initialized = 0;
378 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
379 /* Clear the SSC dividers */
380 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
382 spin_unlock_irq(&ssc_p->lock);
384 /* Shutdown the SSC clock. */
385 pr_debug("atmel_ssc_dai: Stopping clock\n");
386 clk_disable(ssc_p->ssc->clk);
391 * Record the DAI format for use in hw_params().
393 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
396 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
403 * Record SSC clock dividers for use in hw_params().
405 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
408 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
411 case ATMEL_SSC_CMR_DIV:
413 * The same master clock divider is used for both
414 * transmit and receive, so if a value has already
415 * been set, it must match this value.
417 if (ssc_p->dir_mask !=
418 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
419 ssc_p->cmr_div = div;
420 else if (ssc_p->cmr_div == 0)
421 ssc_p->cmr_div = div;
423 if (div != ssc_p->cmr_div)
427 case ATMEL_SSC_TCMR_PERIOD:
428 ssc_p->tcmr_period = div;
431 case ATMEL_SSC_RCMR_PERIOD:
432 ssc_p->rcmr_period = div;
445 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
446 struct snd_pcm_hw_params *params,
447 struct snd_soc_dai *dai)
450 struct atmel_ssc_info *ssc_p = &ssc_info[id];
451 struct ssc_device *ssc = ssc_p->ssc;
452 struct atmel_pcm_dma_params *dma_params;
453 int dir, channels, bits;
454 u32 tfmr, rfmr, tcmr, rcmr;
456 int fslen, fslen_ext;
459 * Currently, there is only one set of dma params for
460 * each direction. If more are added, this code will
461 * have to be changed to select the proper set.
463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
468 dma_params = ssc_p->dma_params[dir];
470 channels = params_channels(params);
473 * Determine sample size in bits and the PDC increment.
475 switch (params_format(params)) {
476 case SNDRV_PCM_FORMAT_S8:
478 dma_params->pdc_xfer_size = 1;
480 case SNDRV_PCM_FORMAT_S16_LE:
482 dma_params->pdc_xfer_size = 2;
484 case SNDRV_PCM_FORMAT_S24_LE:
486 dma_params->pdc_xfer_size = 4;
488 case SNDRV_PCM_FORMAT_S32_LE:
490 dma_params->pdc_xfer_size = 4;
493 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
498 * Compute SSC register settings.
500 switch (ssc_p->daifmt
501 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
503 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
505 * I2S format, SSC provides BCLK and LRC clocks.
507 * The SSC transmit and receive clocks are generated
508 * from the MCK divider, and the BCLK signal
509 * is output on the SSC TK line.
512 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
514 "sample size %d is too large for SSC device\n",
519 fslen_ext = (bits - 1) / 16;
520 fslen = (bits - 1) % 16;
522 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
523 | SSC_BF(RCMR_STTDLY, START_DELAY)
524 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
525 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
526 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
527 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
529 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
530 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
531 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
532 | SSC_BF(RFMR_FSLEN, fslen)
533 | SSC_BF(RFMR_DATNB, (channels - 1))
535 | SSC_BF(RFMR_LOOP, 0)
536 | SSC_BF(RFMR_DATLEN, (bits - 1));
538 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
539 | SSC_BF(TCMR_STTDLY, START_DELAY)
540 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
541 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
542 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
543 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
545 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
546 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
547 | SSC_BF(TFMR_FSDEN, 0)
548 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
549 | SSC_BF(TFMR_FSLEN, fslen)
550 | SSC_BF(TFMR_DATNB, (channels - 1))
552 | SSC_BF(TFMR_DATDEF, 0)
553 | SSC_BF(TFMR_DATLEN, (bits - 1));
556 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
557 /* I2S format, CODEC supplies BCLK and LRC clocks. */
558 rcmr = SSC_BF(RCMR_PERIOD, 0)
559 | SSC_BF(RCMR_STTDLY, START_DELAY)
560 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
561 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
562 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
563 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
564 SSC_CKS_PIN : SSC_CKS_CLOCK);
566 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
567 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
568 | SSC_BF(RFMR_FSLEN, 0)
569 | SSC_BF(RFMR_DATNB, (channels - 1))
571 | SSC_BF(RFMR_LOOP, 0)
572 | SSC_BF(RFMR_DATLEN, (bits - 1));
574 tcmr = SSC_BF(TCMR_PERIOD, 0)
575 | SSC_BF(TCMR_STTDLY, START_DELAY)
576 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
577 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
578 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
579 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
580 SSC_CKS_CLOCK : SSC_CKS_PIN);
582 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
583 | SSC_BF(TFMR_FSDEN, 0)
584 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
585 | SSC_BF(TFMR_FSLEN, 0)
586 | SSC_BF(TFMR_DATNB, (channels - 1))
588 | SSC_BF(TFMR_DATDEF, 0)
589 | SSC_BF(TFMR_DATLEN, (bits - 1));
592 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
593 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
594 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
596 "sample size %d is too large for SSC device\n",
601 fslen_ext = (bits - 1) / 16;
602 fslen = (bits - 1) % 16;
604 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
605 | SSC_BF(RCMR_STTDLY, START_DELAY)
606 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
607 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
608 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
609 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
610 SSC_CKS_PIN : SSC_CKS_CLOCK);
612 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
613 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
614 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
615 | SSC_BF(RFMR_FSLEN, fslen)
616 | SSC_BF(RFMR_DATNB, (channels - 1))
618 | SSC_BF(RFMR_LOOP, 0)
619 | SSC_BF(RFMR_DATLEN, (bits - 1));
621 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
622 | SSC_BF(TCMR_STTDLY, START_DELAY)
623 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
624 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
625 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
626 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
627 SSC_CKS_CLOCK : SSC_CKS_PIN);
629 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
630 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
631 | SSC_BF(TFMR_FSDEN, 0)
632 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
633 | SSC_BF(TFMR_FSLEN, fslen)
634 | SSC_BF(TFMR_DATNB, (channels - 1))
636 | SSC_BF(TFMR_DATDEF, 0)
637 | SSC_BF(TFMR_DATLEN, (bits - 1));
640 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
642 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
644 * The SSC transmit and receive clocks are generated from the
645 * MCK divider, and the BCLK signal is output
646 * on the SSC TK line.
648 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
649 | SSC_BF(RCMR_STTDLY, 1)
650 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
651 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
652 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
653 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
655 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
656 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
657 | SSC_BF(RFMR_FSLEN, 0)
658 | SSC_BF(RFMR_DATNB, (channels - 1))
660 | SSC_BF(RFMR_LOOP, 0)
661 | SSC_BF(RFMR_DATLEN, (bits - 1));
663 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
664 | SSC_BF(TCMR_STTDLY, 1)
665 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
666 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
667 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
668 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
670 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
671 | SSC_BF(TFMR_FSDEN, 0)
672 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
673 | SSC_BF(TFMR_FSLEN, 0)
674 | SSC_BF(TFMR_DATNB, (channels - 1))
676 | SSC_BF(TFMR_DATDEF, 0)
677 | SSC_BF(TFMR_DATLEN, (bits - 1));
680 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
682 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
684 * Data is transferred on first BCLK after LRC pulse rising
685 * edge.If stereo, the right channel data is contiguous with
686 * the left channel data.
688 rcmr = SSC_BF(RCMR_PERIOD, 0)
689 | SSC_BF(RCMR_STTDLY, START_DELAY)
690 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
691 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
692 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
693 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
694 SSC_CKS_PIN : SSC_CKS_CLOCK);
696 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
697 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
698 | SSC_BF(RFMR_FSLEN, 0)
699 | SSC_BF(RFMR_DATNB, (channels - 1))
701 | SSC_BF(RFMR_LOOP, 0)
702 | SSC_BF(RFMR_DATLEN, (bits - 1));
704 tcmr = SSC_BF(TCMR_PERIOD, 0)
705 | SSC_BF(TCMR_STTDLY, START_DELAY)
706 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
707 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
708 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
709 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
710 SSC_CKS_CLOCK : SSC_CKS_PIN);
712 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
713 | SSC_BF(TFMR_FSDEN, 0)
714 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
715 | SSC_BF(TFMR_FSLEN, 0)
716 | SSC_BF(TFMR_DATNB, (channels - 1))
718 | SSC_BF(TFMR_DATDEF, 0)
719 | SSC_BF(TFMR_DATLEN, (bits - 1));
723 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
727 pr_debug("atmel_ssc_hw_params: "
728 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
729 rcmr, rfmr, tcmr, tfmr);
731 if (!ssc_p->initialized) {
732 if (!ssc_p->ssc->pdata->use_dma) {
733 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
734 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
735 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
736 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
738 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
739 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
740 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
741 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
744 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
748 "atmel_ssc_dai: request_irq failure\n");
749 pr_debug("Atmel_ssc_dai: Stoping clock\n");
750 clk_disable(ssc_p->ssc->clk);
754 ssc_p->initialized = 1;
757 /* set SSC clock mode register */
758 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
760 /* set receive clock mode and format */
761 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
762 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
764 /* set transmit clock mode and format */
765 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
766 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
768 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
773 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
774 struct snd_soc_dai *dai)
776 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
777 struct atmel_pcm_dma_params *dma_params;
780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
785 dma_params = ssc_p->dma_params[dir];
787 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
788 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
790 pr_debug("%s enabled SSC_SR=0x%08x\n",
791 dir ? "receive" : "transmit",
792 ssc_readl(ssc_p->ssc->regs, SR));
796 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
797 int cmd, struct snd_soc_dai *dai)
799 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
800 struct atmel_pcm_dma_params *dma_params;
803 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
808 dma_params = ssc_p->dma_params[dir];
811 case SNDRV_PCM_TRIGGER_START:
812 case SNDRV_PCM_TRIGGER_RESUME:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
817 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
825 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
827 struct atmel_ssc_info *ssc_p;
829 if (!cpu_dai->active)
832 ssc_p = &ssc_info[cpu_dai->id];
834 /* Save the status register before disabling transmit and receive */
835 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
836 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
838 /* Save the current interrupt mask, then disable unmasked interrupts */
839 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
840 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
842 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
843 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
844 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
845 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
846 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
853 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
855 struct atmel_ssc_info *ssc_p;
858 if (!cpu_dai->active)
861 ssc_p = &ssc_info[cpu_dai->id];
863 /* restore SSC register settings */
864 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
865 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
866 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
867 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
868 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
870 /* re-enable interrupts */
871 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
873 /* Re-enable receive and transmit as appropriate */
876 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
878 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
879 ssc_writel(ssc_p->ssc->regs, CR, cr);
883 #else /* CONFIG_PM */
884 # define atmel_ssc_suspend NULL
885 # define atmel_ssc_resume NULL
886 #endif /* CONFIG_PM */
888 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
889 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
891 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
892 .startup = atmel_ssc_startup,
893 .shutdown = atmel_ssc_shutdown,
894 .prepare = atmel_ssc_prepare,
895 .trigger = atmel_ssc_trigger,
896 .hw_params = atmel_ssc_hw_params,
897 .set_fmt = atmel_ssc_set_dai_fmt,
898 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
901 static struct snd_soc_dai_driver atmel_ssc_dai = {
902 .suspend = atmel_ssc_suspend,
903 .resume = atmel_ssc_resume,
907 .rates = SNDRV_PCM_RATE_CONTINUOUS,
910 .formats = ATMEL_SSC_FORMATS,},
914 .rates = SNDRV_PCM_RATE_CONTINUOUS,
917 .formats = ATMEL_SSC_FORMATS,},
918 .ops = &atmel_ssc_dai_ops,
921 static const struct snd_soc_component_driver atmel_ssc_component = {
925 static int asoc_ssc_init(struct device *dev)
927 struct platform_device *pdev = to_platform_device(dev);
928 struct ssc_device *ssc = platform_get_drvdata(pdev);
931 ret = snd_soc_register_component(dev, &atmel_ssc_component,
934 dev_err(dev, "Could not register DAI: %d\n", ret);
938 if (ssc->pdata->use_dma)
939 ret = atmel_pcm_dma_platform_register(dev);
941 ret = atmel_pcm_pdc_platform_register(dev);
944 dev_err(dev, "Could not register PCM: %d\n", ret);
945 goto err_unregister_dai;
951 snd_soc_unregister_component(dev);
956 static void asoc_ssc_exit(struct device *dev)
958 struct platform_device *pdev = to_platform_device(dev);
959 struct ssc_device *ssc = platform_get_drvdata(pdev);
961 if (ssc->pdata->use_dma)
962 atmel_pcm_dma_platform_unregister(dev);
964 atmel_pcm_pdc_platform_unregister(dev);
966 snd_soc_unregister_component(dev);
970 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
972 int atmel_ssc_set_audio(int ssc_id)
974 struct ssc_device *ssc;
977 /* If we can grab the SSC briefly to parent the DAI device off it */
978 ssc = ssc_request(ssc_id);
980 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
984 ssc_info[ssc_id].ssc = ssc;
987 ret = asoc_ssc_init(&ssc->pdev->dev);
991 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
993 void atmel_ssc_put_audio(int ssc_id)
995 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
997 asoc_ssc_exit(&ssc->pdev->dev);
1000 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
1002 /* Module information */
1003 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
1004 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
1005 MODULE_LICENSE("GPL");