1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel I2S controller
5 * Copyright (C) 2015 Atmel Corporation
7 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/mfd/syscon.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
24 #include <sound/dmaengine_pcm.h>
26 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8
29 * ---- I2S Controller Register map ----
31 #define ATMEL_I2SC_CR 0x0000 /* Control Register */
32 #define ATMEL_I2SC_MR 0x0004 /* Mode Register */
33 #define ATMEL_I2SC_SR 0x0008 /* Status Register */
34 #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */
35 #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */
36 #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */
37 #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */
38 #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */
39 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */
40 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */
41 #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */
44 * ---- Control Register (Write-only) ----
46 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */
47 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
50 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */
51 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */
52 #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */
55 * ---- Mode Register (Read/Write) ----
57 #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0)
58 #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0)
59 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
61 #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2)
62 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2)
63 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2)
64 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2)
65 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2)
66 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2)
67 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2)
68 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2)
69 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
71 #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6)
72 #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6)
73 #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */
74 #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6)
75 #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6)
77 /* Left audio samples duplicated to right audio channel */
78 #define ATMEL_I2SC_MR_RXMONO BIT(8)
80 /* Receiver uses one DMA channel ... */
81 #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9)
82 #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */
83 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */
85 /* I2SDO output of I2SC is internally connected to I2SDI input */
86 #define ATMEL_I2SC_MR_RXLOOP BIT(10)
88 /* Left audio samples duplicated to right audio channel */
89 #define ATMEL_I2SC_MR_TXMONO BIT(12)
91 /* Transmitter uses one DMA channel ... */
92 #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13)
93 #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */
94 #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */
96 /* x sample transmitted when underrun */
97 #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14)
98 #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */
99 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */
101 /* Audio Clock to I2SC Master Clock ratio */
102 #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16)
103 #define ATMEL_I2SC_MR_IMCKDIV(div) \
104 (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
106 /* Master Clock to fs ratio */
107 #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24)
108 #define ATMEL_I2SC_MR_IMCKFS(fs) \
109 (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
111 /* Master Clock mode */
112 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)
113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
114 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30)
115 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
116 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30)
119 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
120 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
121 #define ATMEL_I2SC_MR_IWS BIT(31)
124 * ---- Status Registers ----
126 #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */
127 #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */
128 #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */
130 #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */
131 #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */
132 #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */
134 /* Receive Overrun Channel */
135 #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8)
136 #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8))
138 /* Transmit Underrun Channel */
139 #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20)
140 #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20))
143 * ---- Interrupt Enable/Disable/Mask Registers ----
145 #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY
146 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR
147 #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY
148 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR
150 static const struct regmap_config atmel_i2s_regmap_config = {
154 .max_register = ATMEL_I2SC_VERSION,
157 struct atmel_i2s_gck_param {
164 #define I2S_MCK_12M288 12288000UL
165 #define I2S_MCK_11M2896 11289600UL
167 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
168 static const struct atmel_i2s_gck_param gck_params[] = {
169 /* mck = 12.288MHz */
170 { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */
171 { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */
172 { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */
173 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
174 { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */
175 { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */
176 { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */
177 {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */
179 /* mck = 11.2896MHz */
180 { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */
181 { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */
182 { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */
183 { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */
184 {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */
187 struct atmel_i2s_dev;
189 struct atmel_i2s_caps {
190 int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
193 struct atmel_i2s_dev {
195 struct regmap *regmap;
198 struct snd_dmaengine_dai_dma_data playback;
199 struct snd_dmaengine_dai_dma_data capture;
201 const struct atmel_i2s_gck_param *gck_param;
202 const struct atmel_i2s_caps *caps;
206 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
208 struct atmel_i2s_dev *dev = dev_id;
209 unsigned int sr, imr, pending, ch, mask;
210 irqreturn_t ret = IRQ_NONE;
212 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
213 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
219 if (pending & ATMEL_I2SC_INT_RXOR) {
220 mask = ATMEL_I2SC_SR_RXOR;
222 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
223 if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
224 mask |= ATMEL_I2SC_SR_RXORCH(ch);
226 "RX overrun on channel %d\n", ch);
229 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
233 if (pending & ATMEL_I2SC_INT_TXUR) {
234 mask = ATMEL_I2SC_SR_TXUR;
236 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
237 if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
238 mask |= ATMEL_I2SC_SR_TXURCH(ch);
240 "TX underrun on channel %d\n", ch);
243 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
250 #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000
252 #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
253 SNDRV_PCM_FMTBIT_S16_LE | \
254 SNDRV_PCM_FMTBIT_S18_3LE | \
255 SNDRV_PCM_FMTBIT_S20_3LE | \
256 SNDRV_PCM_FMTBIT_S24_3LE | \
257 SNDRV_PCM_FMTBIT_S24_LE | \
258 SNDRV_PCM_FMTBIT_S32_LE)
260 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
262 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
268 static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
269 struct snd_soc_dai *dai)
271 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
272 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
273 unsigned int rhr, sr = 0;
276 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
277 if (sr & ATMEL_I2SC_SR_RXRDY) {
279 * The RX Ready flag should not be set. However if here,
280 * we flush (read) the Receive Holding Register to start
281 * from a clean state.
283 dev_dbg(dev->dev, "RXRDY is set\n");
284 regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
291 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
296 dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
301 * Find the best possible settings to generate the I2S Master Clock
302 * from the PLL Audio.
304 dev->gck_param = NULL;
306 for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
307 const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
308 int val = abs(fs - gck_param->fs);
312 dev->gck_param = gck_param;
319 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
320 struct snd_pcm_hw_params *params,
321 struct snd_soc_dai *dai)
323 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
324 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
325 unsigned int mr = 0, mr_mask;
328 mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK |
329 ATMEL_I2SC_MR_DATALENGTH_MASK;
331 mr_mask |= ATMEL_I2SC_MR_TXMONO;
333 mr_mask |= ATMEL_I2SC_MR_RXMONO;
335 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
336 case SND_SOC_DAIFMT_I2S:
337 mr |= ATMEL_I2SC_MR_FORMAT_I2S;
341 dev_err(dev->dev, "unsupported bus format\n");
345 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
346 case SND_SOC_DAIFMT_CBS_CFS:
347 /* codec is slave, so cpu is master */
348 mr |= ATMEL_I2SC_MR_MODE_MASTER;
349 ret = atmel_i2s_get_gck_param(dev, params_rate(params));
354 case SND_SOC_DAIFMT_CBM_CFM:
355 /* codec is master, so cpu is slave */
356 mr |= ATMEL_I2SC_MR_MODE_SLAVE;
357 dev->gck_param = NULL;
361 dev_err(dev->dev, "unsupported master/slave mode\n");
365 switch (params_channels(params)) {
368 mr |= ATMEL_I2SC_MR_TXMONO;
370 mr |= ATMEL_I2SC_MR_RXMONO;
375 dev_err(dev->dev, "unsupported number of audio channels\n");
379 switch (params_format(params)) {
380 case SNDRV_PCM_FORMAT_S8:
381 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
384 case SNDRV_PCM_FORMAT_S16_LE:
385 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
388 case SNDRV_PCM_FORMAT_S18_3LE:
389 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
392 case SNDRV_PCM_FORMAT_S20_3LE:
393 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
396 case SNDRV_PCM_FORMAT_S24_3LE:
397 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
400 case SNDRV_PCM_FORMAT_S24_LE:
401 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
404 case SNDRV_PCM_FORMAT_S32_LE:
405 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
409 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
413 return regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
416 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
419 unsigned int mr, mr_mask;
420 unsigned long gclk_rate;
424 mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
425 ATMEL_I2SC_MR_IMCKFS_MASK |
426 ATMEL_I2SC_MR_IMCKMODE_MASK);
429 /* Disable the I2S Master Clock generator. */
430 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
431 ATMEL_I2SC_CR_CKDIS);
435 /* Reset the I2S Master Clock generator settings. */
436 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
441 /* Disable/unprepare the PMC generated clock. */
442 clk_disable_unprepare(dev->gclk);
450 gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
452 ret = clk_set_rate(dev->gclk, gclk_rate);
456 ret = clk_prepare_enable(dev->gclk);
460 /* Update the Mode Register to generate the I2S Master Clock. */
461 mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
462 mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
463 mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
464 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
468 /* Finally enable the I2S Master Clock generator. */
469 return regmap_write(dev->regmap, ATMEL_I2SC_CR,
473 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
474 struct snd_soc_dai *dai)
476 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
477 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
478 bool is_master, mck_enabled;
483 case SNDRV_PCM_TRIGGER_START:
484 case SNDRV_PCM_TRIGGER_RESUME:
485 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
486 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
489 case SNDRV_PCM_TRIGGER_STOP:
490 case SNDRV_PCM_TRIGGER_SUSPEND:
491 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
492 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
499 /* Read the Mode Register to retrieve the master/slave state. */
500 err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
503 is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
505 /* If master starts, enable the audio clock. */
506 if (is_master && mck_enabled) {
507 if (!dev->clk_use_no) {
508 err = atmel_i2s_switch_mck_generator(dev, true);
515 err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
519 /* If master stops, disable the audio clock. */
520 if (is_master && !mck_enabled) {
521 if (dev->clk_use_no == 1) {
522 err = atmel_i2s_switch_mck_generator(dev, false);
532 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
533 .prepare = atmel_i2s_prepare,
534 .trigger = atmel_i2s_trigger,
535 .hw_params = atmel_i2s_hw_params,
536 .set_fmt = atmel_i2s_set_dai_fmt,
539 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
541 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
543 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
547 static struct snd_soc_dai_driver atmel_i2s_dai = {
548 .probe = atmel_i2s_dai_probe,
552 .rates = ATMEL_I2S_RATES,
553 .formats = ATMEL_I2S_FORMATS,
558 .rates = ATMEL_I2S_RATES,
559 .formats = ATMEL_I2S_FORMATS,
561 .ops = &atmel_i2s_dai_ops,
562 .symmetric_rates = 1,
565 static const struct snd_soc_component_driver atmel_i2s_component = {
569 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
570 struct device_node *np)
578 /* muxclk is optional, so we return error for probe defer only */
579 muxclk = devm_clk_get(dev->dev, "muxclk");
580 if (IS_ERR(muxclk)) {
581 err = PTR_ERR(muxclk);
582 if (err == -EPROBE_DEFER)
583 return -EPROBE_DEFER;
585 "failed to get the I2S clock control: %d\n", err);
589 return clk_set_parent(muxclk, dev->gclk);
592 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
593 .mck_init = atmel_i2s_sama5d2_mck_init,
596 static const struct of_device_id atmel_i2s_dt_ids[] = {
598 .compatible = "atmel,sama5d2-i2s",
599 .data = (void *)&atmel_i2s_sama5d2_caps,
605 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
607 static int atmel_i2s_probe(struct platform_device *pdev)
609 struct device_node *np = pdev->dev.of_node;
610 const struct of_device_id *match;
611 struct atmel_i2s_dev *dev;
612 struct resource *mem;
613 struct regmap *regmap;
617 unsigned int pcm_flags = 0;
618 unsigned int version;
620 /* Get memory for driver data. */
621 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
625 /* Get hardware capabilities. */
626 match = of_match_node(atmel_i2s_dt_ids, np);
628 dev->caps = match->data;
630 /* Map I/O registers. */
631 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 base = devm_ioremap_resource(&pdev->dev, mem);
634 return PTR_ERR(base);
636 regmap = devm_regmap_init_mmio(&pdev->dev, base,
637 &atmel_i2s_regmap_config);
639 return PTR_ERR(regmap);
642 irq = platform_get_irq(pdev, 0);
646 err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
647 dev_name(&pdev->dev), dev);
651 /* Get the peripheral clock. */
652 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
653 if (IS_ERR(dev->pclk)) {
654 err = PTR_ERR(dev->pclk);
656 "failed to get the peripheral clock: %d\n", err);
660 /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */
661 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
662 if (IS_ERR(dev->gclk)) {
663 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
664 return -EPROBE_DEFER;
665 /* Master Mode not supported */
668 dev->dev = &pdev->dev;
669 dev->regmap = regmap;
670 platform_set_drvdata(pdev, dev);
672 /* Do hardware specific settings to initialize I2S_MCK generator */
673 if (dev->caps && dev->caps->mck_init) {
674 err = dev->caps->mck_init(dev, np);
679 /* Enable the peripheral clock. */
680 err = clk_prepare_enable(dev->pclk);
684 /* Get IP version. */
685 regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
686 dev_info(&pdev->dev, "hw version: %#x\n", version);
688 /* Enable error interrupts. */
689 regmap_write(dev->regmap, ATMEL_I2SC_IER,
690 ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
692 err = devm_snd_soc_register_component(&pdev->dev,
693 &atmel_i2s_component,
696 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
697 clk_disable_unprepare(dev->pclk);
701 /* Prepare DMA config. */
702 dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
703 dev->playback.maxburst = 1;
704 dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
705 dev->capture.maxburst = 1;
707 if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
708 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
709 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
711 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
712 clk_disable_unprepare(dev->pclk);
719 static int atmel_i2s_remove(struct platform_device *pdev)
721 struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
723 clk_disable_unprepare(dev->pclk);
728 static struct platform_driver atmel_i2s_driver = {
731 .of_match_table = of_match_ptr(atmel_i2s_dt_ids),
733 .probe = atmel_i2s_probe,
734 .remove = atmel_i2s_remove,
736 module_platform_driver(atmel_i2s_driver);
738 MODULE_DESCRIPTION("Atmel I2S Controller driver");
739 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
740 MODULE_LICENSE("GPL v2");