1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
49 #define HDSP_MAX_CHANNELS 26
50 #define HDSP_MAX_DS_CHANNELS 14
51 #define HDSP_MAX_QS_CHANNELS 8
52 #define DIGIFACE_SS_CHANNELS 26
53 #define DIGIFACE_DS_CHANNELS 14
54 #define MULTIFACE_SS_CHANNELS 18
55 #define MULTIFACE_DS_CHANNELS 14
56 #define H9652_SS_CHANNELS 26
57 #define H9652_DS_CHANNELS 14
58 /* This does not include possible Analog Extension Boards
59 AEBs are detected at card initialization
61 #define H9632_SS_CHANNELS 12
62 #define H9632_DS_CHANNELS 8
63 #define H9632_QS_CHANNELS 4
64 #define RPM_CHANNELS 6
66 /* Write registers. These are defined as byte-offsets from the iobase value.
68 #define HDSP_resetPointer 0
69 #define HDSP_freqReg 0
70 #define HDSP_outputBufferAddress 32
71 #define HDSP_inputBufferAddress 36
72 #define HDSP_controlRegister 64
73 #define HDSP_interruptConfirmation 96
74 #define HDSP_outputEnable 128
75 #define HDSP_control2Reg 256
76 #define HDSP_midiDataOut0 352
77 #define HDSP_midiDataOut1 356
78 #define HDSP_fifoData 368
79 #define HDSP_inputEnable 384
81 /* Read registers. These are defined as byte-offsets from the iobase value
84 #define HDSP_statusRegister 0
85 #define HDSP_timecode 128
86 #define HDSP_status2Register 192
87 #define HDSP_midiDataIn0 360
88 #define HDSP_midiDataIn1 364
89 #define HDSP_midiStatusOut0 384
90 #define HDSP_midiStatusOut1 388
91 #define HDSP_midiStatusIn0 392
92 #define HDSP_midiStatusIn1 396
93 #define HDSP_fifoStatus 400
95 /* the meters are regular i/o-mapped registers, but offset
96 considerably from the rest. the peak registers are reset
97 when read; the least-significant 4 bits are full-scale counters;
98 the actual peak value is in the most-significant 24 bits.
101 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
102 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
103 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
104 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
105 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
108 /* This is for H9652 cards
109 Peak values are read downward from the base
110 Rms values are read upward
111 There are rms values for the outputs too
112 26*3 values are read in ss mode
113 14*3 in ds mode, with no gap between values
115 #define HDSP_9652_peakBase 7164
116 #define HDSP_9652_rmsBase 4096
118 /* c.f. the hdsp_9632_meters_t struct */
119 #define HDSP_9632_metersBase 4096
121 #define HDSP_IO_EXTENT 7168
123 /* control2 register bits */
125 #define HDSP_TMS 0x01
126 #define HDSP_TCK 0x02
127 #define HDSP_TDI 0x04
128 #define HDSP_JTAG 0x08
129 #define HDSP_PWDN 0x10
130 #define HDSP_PROGRAM 0x020
131 #define HDSP_CONFIG_MODE_0 0x040
132 #define HDSP_CONFIG_MODE_1 0x080
133 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
134 #define HDSP_BIGENDIAN_MODE 0x200
135 #define HDSP_RD_MULTIPLE 0x400
136 #define HDSP_9652_ENABLE_MIXER 0x800
137 #define HDSP_S200 0x800
138 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
139 #define HDSP_CYCLIC_MODE 0x1000
140 #define HDSP_TDO 0x10000000
142 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
143 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
145 /* Control Register bits */
147 #define HDSP_Start (1<<0) /* start engine */
148 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
149 #define HDSP_Latency1 (1<<2) /* [ see above ] */
150 #define HDSP_Latency2 (1<<3) /* [ see above ] */
151 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
152 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
153 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
154 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
155 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
156 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
157 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
158 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
159 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
160 #define HDSP_SyncRef2 (1<<13)
161 #define HDSP_SPDIFInputSelect0 (1<<14)
162 #define HDSP_SPDIFInputSelect1 (1<<15)
163 #define HDSP_SyncRef0 (1<<16)
164 #define HDSP_SyncRef1 (1<<17)
165 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
166 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
167 #define HDSP_Midi0InterruptEnable (1<<22)
168 #define HDSP_Midi1InterruptEnable (1<<23)
169 #define HDSP_LineOut (1<<24)
170 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
171 #define HDSP_ADGain1 (1<<26)
172 #define HDSP_DAGain0 (1<<27)
173 #define HDSP_DAGain1 (1<<28)
174 #define HDSP_PhoneGain0 (1<<29)
175 #define HDSP_PhoneGain1 (1<<30)
176 #define HDSP_QuadSpeed (1<<31)
178 /* RPM uses some of the registers for special purposes */
179 #define HDSP_RPM_Inp12 0x04A00
180 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
181 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
182 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
183 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
184 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
186 #define HDSP_RPM_Inp34 0x32000
187 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
188 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
189 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
190 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
191 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
193 #define HDSP_RPM_Bypass 0x01000
195 #define HDSP_RPM_Disconnect 0x00001
197 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
198 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
199 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
200 #define HDSP_ADGainLowGain 0
202 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
203 #define HDSP_DAGainHighGain HDSP_DAGainMask
204 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
205 #define HDSP_DAGainMinus10dBV 0
207 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
208 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
209 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
210 #define HDSP_PhoneGainMinus12dB 0
212 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
213 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
215 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
216 #define HDSP_SPDIFInputADAT1 0
217 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
218 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
219 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
221 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
222 #define HDSP_SyncRef_ADAT1 0
223 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
224 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
225 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
226 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
227 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
229 /* Sample Clock Sources */
231 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
232 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
233 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
234 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
235 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
236 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
237 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
238 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
239 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
240 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
242 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
244 #define HDSP_SYNC_FROM_WORD 0
245 #define HDSP_SYNC_FROM_SPDIF 1
246 #define HDSP_SYNC_FROM_ADAT1 2
247 #define HDSP_SYNC_FROM_ADAT_SYNC 3
248 #define HDSP_SYNC_FROM_ADAT2 4
249 #define HDSP_SYNC_FROM_ADAT3 5
251 /* SyncCheck status */
253 #define HDSP_SYNC_CHECK_NO_LOCK 0
254 #define HDSP_SYNC_CHECK_LOCK 1
255 #define HDSP_SYNC_CHECK_SYNC 2
257 /* AutoSync references - used by "autosync_ref" control switch */
259 #define HDSP_AUTOSYNC_FROM_WORD 0
260 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
261 #define HDSP_AUTOSYNC_FROM_SPDIF 2
262 #define HDSP_AUTOSYNC_FROM_NONE 3
263 #define HDSP_AUTOSYNC_FROM_ADAT1 4
264 #define HDSP_AUTOSYNC_FROM_ADAT2 5
265 #define HDSP_AUTOSYNC_FROM_ADAT3 6
267 /* Possible sources of S/PDIF input */
269 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
270 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
271 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
272 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
274 #define HDSP_Frequency32KHz HDSP_Frequency0
275 #define HDSP_Frequency44_1KHz HDSP_Frequency1
276 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
277 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
278 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
279 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
280 /* For H9632 cards */
281 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
282 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
283 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
284 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
285 return 104857600000000 / rate; // 100 MHz
286 return 110100480000000 / rate; // 105 MHz
288 #define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */
290 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
291 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
293 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
294 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
296 /* Status Register bits */
298 #define HDSP_audioIRQPending (1<<0)
299 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
300 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
301 #define HDSP_Lock1 (1<<2)
302 #define HDSP_Lock0 (1<<3)
303 #define HDSP_SPDIFSync (1<<4)
304 #define HDSP_TimecodeLock (1<<5)
305 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
306 #define HDSP_Sync2 (1<<16)
307 #define HDSP_Sync1 (1<<17)
308 #define HDSP_Sync0 (1<<18)
309 #define HDSP_DoubleSpeedStatus (1<<19)
310 #define HDSP_ConfigError (1<<20)
311 #define HDSP_DllError (1<<21)
312 #define HDSP_spdifFrequency0 (1<<22)
313 #define HDSP_spdifFrequency1 (1<<23)
314 #define HDSP_spdifFrequency2 (1<<24)
315 #define HDSP_SPDIFErrorFlag (1<<25)
316 #define HDSP_BufferID (1<<26)
317 #define HDSP_TimecodeSync (1<<27)
318 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
319 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
320 #define HDSP_midi0IRQPending (1<<30)
321 #define HDSP_midi1IRQPending (1<<31)
323 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
324 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
325 HDSP_spdifFrequency1|\
326 HDSP_spdifFrequency2|\
327 HDSP_spdifFrequency3)
329 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
330 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
331 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
333 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
334 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
335 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
337 /* This is for H9632 cards */
338 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
339 HDSP_spdifFrequency1|\
340 HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
342 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
344 /* Status2 Register bits */
346 #define HDSP_version0 (1<<0)
347 #define HDSP_version1 (1<<1)
348 #define HDSP_version2 (1<<2)
349 #define HDSP_wc_lock (1<<3)
350 #define HDSP_wc_sync (1<<4)
351 #define HDSP_inp_freq0 (1<<5)
352 #define HDSP_inp_freq1 (1<<6)
353 #define HDSP_inp_freq2 (1<<7)
354 #define HDSP_SelSyncRef0 (1<<8)
355 #define HDSP_SelSyncRef1 (1<<9)
356 #define HDSP_SelSyncRef2 (1<<10)
358 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
360 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
361 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
362 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
363 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
364 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
365 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
366 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
367 /* FIXME : more values for 9632 cards ? */
369 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
370 #define HDSP_SelSyncRef_ADAT1 0
371 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
372 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
373 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
374 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
375 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
377 /* Card state flags */
379 #define HDSP_InitializationComplete (1<<0)
380 #define HDSP_FirmwareLoaded (1<<1)
381 #define HDSP_FirmwareCached (1<<2)
383 /* FIFO wait times, defined in terms of 1/10ths of msecs */
385 #define HDSP_LONG_WAIT 5000
386 #define HDSP_SHORT_WAIT 30
388 #define UNITY_GAIN 32768
389 #define MINUS_INFINITY_GAIN 0
391 /* the size of a substream (1 mono data stream) */
393 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
394 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
396 /* the size of the area we need to allocate for DMA transfers. the
397 size is the same regardless of the number of channels - the
398 Multiface still uses the same memory area.
400 Note that we allocate 1 more channel than is apparently needed
401 because the h/w seems to write 1 byte beyond the end of the last
405 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
406 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
408 #define HDSP_FIRMWARE_SIZE (24413 * 4)
410 struct hdsp_9632_meters {
412 u32 playback_peak[16];
416 u32 input_rms_low[16];
417 u32 playback_rms_low[16];
418 u32 output_rms_low[16];
420 u32 input_rms_high[16];
421 u32 playback_rms_high[16];
422 u32 output_rms_high[16];
423 u32 xxx_rms_high[16];
429 struct snd_rawmidi *rmidi;
430 struct snd_rawmidi_substream *input;
431 struct snd_rawmidi_substream *output;
432 signed char istimer; /* timer in use */
433 struct timer_list timer;
440 struct snd_pcm_substream *capture_substream;
441 struct snd_pcm_substream *playback_substream;
442 struct hdsp_midi midi[2];
443 struct work_struct midi_work;
446 u32 control_register; /* cached value */
447 u32 control2_register; /* cached value */
449 u32 creg_spdif_stream;
450 int clock_source_locked;
451 char *card_name; /* digiface/multiface/rpm */
452 enum HDSP_IO_Type io_type; /* ditto, but for code use */
453 unsigned short firmware_rev;
454 unsigned short state; /* stores state bits */
455 const struct firmware *firmware;
457 size_t period_bytes; /* guess what this is */
458 unsigned char max_channels;
459 unsigned char qs_in_channels; /* quad speed mode for H9632 */
460 unsigned char ds_in_channels;
461 unsigned char ss_in_channels; /* different for multiface/digiface */
462 unsigned char qs_out_channels;
463 unsigned char ds_out_channels;
464 unsigned char ss_out_channels;
465 u32 io_loopback; /* output loopback channel states*/
467 /* DMA buffers; those are copied instances from the original snd_dma_buf
468 * objects (which are managed via devres) for the address alignments
470 struct snd_dma_buffer capture_dma_buf;
471 struct snd_dma_buffer playback_dma_buf;
472 unsigned char *capture_buffer; /* suitably aligned address */
473 unsigned char *playback_buffer; /* suitably aligned address */
478 int system_sample_rate;
479 const signed char *channel_map;
483 void __iomem *iobase;
484 struct snd_card *card;
486 struct snd_hwdep *hwdep;
488 struct snd_kcontrol *spdif_ctl;
489 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
490 unsigned int dds_value; /* last value written to freq register */
493 /* These tables map the ALSA channels 1..N to the channels that we
494 need to use in order to find the relevant channel buffer. RME
495 refer to this kind of mapping as between "the ADAT channel and
496 the DMA channel." We index it using the logical audio channel,
497 and the value is the DMA channel (i.e. channel buffer number)
498 where the data for that channel can be read/written from/to.
501 static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
502 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
503 18, 19, 20, 21, 22, 23, 24, 25
506 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
508 0, 1, 2, 3, 4, 5, 6, 7,
510 16, 17, 18, 19, 20, 21, 22, 23,
513 -1, -1, -1, -1, -1, -1, -1, -1
516 static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = {
517 /* ADAT channels are remapped */
518 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
519 /* channels 12 and 13 are S/PDIF */
521 /* others don't exist */
522 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
525 static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
527 0, 1, 2, 3, 4, 5, 6, 7,
532 /* AO4S-192 and AI4S-192 extension boards */
534 /* others don't exist */
535 -1, -1, -1, -1, -1, -1, -1, -1,
539 static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
546 /* AO4S-192 and AI4S-192 extension boards */
548 /* others don't exist */
549 -1, -1, -1, -1, -1, -1, -1, -1,
550 -1, -1, -1, -1, -1, -1
553 static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
554 /* ADAT is disabled in this mode */
559 /* AO4S-192 and AI4S-192 extension boards */
561 /* others don't exist */
562 -1, -1, -1, -1, -1, -1, -1, -1,
563 -1, -1, -1, -1, -1, -1, -1, -1,
567 static struct snd_dma_buffer *
568 snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
570 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
573 static const struct pci_device_id snd_hdsp_ids[] = {
575 .vendor = PCI_VENDOR_ID_XILINX,
576 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
577 .subvendor = PCI_ANY_ID,
578 .subdevice = PCI_ANY_ID,
579 }, /* RME Hammerfall-DSP */
583 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
586 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
587 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
588 static int snd_hdsp_enable_io (struct hdsp *hdsp);
589 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
590 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
591 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
592 static int hdsp_autosync_ref(struct hdsp *hdsp);
593 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
594 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
596 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
598 switch (hdsp->io_type) {
603 if (hdsp->firmware_rev == 0xa)
604 return (64 * out) + (32 + (in));
606 return (52 * out) + (26 + (in));
608 return (32 * out) + (16 + (in));
610 return (52 * out) + (26 + (in));
614 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
616 switch (hdsp->io_type) {
621 if (hdsp->firmware_rev == 0xa)
622 return (64 * out) + in;
624 return (52 * out) + in;
626 return (32 * out) + in;
628 return (52 * out) + in;
632 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
634 writel(val, hdsp->iobase + reg);
637 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
639 return readl (hdsp->iobase + reg);
642 static int hdsp_check_for_iobox (struct hdsp *hdsp)
646 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
647 for (i = 0; i < 500; i++) {
648 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
651 dev_dbg(hdsp->card->dev,
652 "IO box found after %d ms\n",
659 dev_err(hdsp->card->dev, "no IO box connected!\n");
660 hdsp->state &= ~HDSP_FirmwareLoaded;
664 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
669 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
672 for (i = 0; i != loops; ++i) {
673 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
676 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
682 dev_info(hdsp->card->dev, "no IO box connected!\n");
683 hdsp->state &= ~HDSP_FirmwareLoaded;
687 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
693 if (hdsp->fw_uploaded)
694 cache = hdsp->fw_uploaded;
698 cache = (u32 *)hdsp->firmware->data;
703 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
705 dev_info(hdsp->card->dev, "loading firmware\n");
707 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
708 hdsp_write (hdsp, HDSP_fifoData, 0);
710 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
711 dev_info(hdsp->card->dev,
712 "timeout waiting for download preparation\n");
713 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
717 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
719 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
720 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
721 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
722 dev_info(hdsp->card->dev,
723 "timeout during firmware loading\n");
724 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
729 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
730 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
733 #ifdef SNDRV_BIG_ENDIAN
734 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
736 hdsp->control2_register = 0;
738 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
739 dev_info(hdsp->card->dev, "finished firmware loading\n");
742 if (hdsp->state & HDSP_InitializationComplete) {
743 dev_info(hdsp->card->dev,
744 "firmware loaded from cache, restoring defaults\n");
745 spin_lock_irqsave(&hdsp->lock, flags);
746 snd_hdsp_set_defaults(hdsp);
747 spin_unlock_irqrestore(&hdsp->lock, flags);
750 hdsp->state |= HDSP_FirmwareLoaded;
755 static int hdsp_get_iobox_version (struct hdsp *hdsp)
757 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
759 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
760 hdsp_write(hdsp, HDSP_fifoData, 0);
762 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
763 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
764 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
767 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
768 hdsp_write (hdsp, HDSP_fifoData, 0);
769 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
772 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
773 hdsp_write(hdsp, HDSP_fifoData, 0);
774 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
775 hdsp->io_type = Digiface;
776 dev_info(hdsp->card->dev, "Digiface found\n");
780 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
781 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
782 hdsp_write(hdsp, HDSP_fifoData, 0);
783 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
786 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
788 hdsp_write(hdsp, HDSP_fifoData, 0);
789 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
793 dev_info(hdsp->card->dev, "RPM found\n");
796 /* firmware was already loaded, get iobox type */
797 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
799 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
800 hdsp->io_type = Multiface;
802 hdsp->io_type = Digiface;
807 hdsp->io_type = Multiface;
808 dev_info(hdsp->card->dev, "Multiface found\n");
813 static int hdsp_request_fw_loader(struct hdsp *hdsp);
815 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
817 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
819 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
820 hdsp->state &= ~HDSP_FirmwareLoaded;
821 if (! load_on_demand)
823 dev_err(hdsp->card->dev, "firmware not present.\n");
824 /* try to load firmware */
825 if (! (hdsp->state & HDSP_FirmwareCached)) {
826 if (! hdsp_request_fw_loader(hdsp))
828 dev_err(hdsp->card->dev,
829 "No firmware loaded nor cached, please upload firmware.\n");
832 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
833 dev_err(hdsp->card->dev,
834 "Firmware loading from cache failed, please upload manually.\n");
842 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
846 /* the fifoStatus registers reports on how many words
847 are available in the command FIFO.
850 for (i = 0; i < timeout; i++) {
852 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
855 /* not very friendly, but we only do this during a firmware
856 load and changing the mixer, so we just put up with it.
862 dev_warn(hdsp->card->dev,
863 "wait for FIFO status <= %d failed after %d iterations\n",
868 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
870 if (addr >= HDSP_MATRIX_MIXER_SIZE)
873 return hdsp->mixer_matrix[addr];
876 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
880 if (addr >= HDSP_MATRIX_MIXER_SIZE)
883 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
885 /* from martin bjornsen:
887 "You can only write dwords to the
888 mixer memory which contain two
889 mixer values in the low and high
890 word. So if you want to change
891 value 0 you have to read value 1
892 from the cache and write both to
893 the first dword in the mixer
897 if (hdsp->io_type == H9632 && addr >= 512)
900 if (hdsp->io_type == H9652 && addr >= 1352)
903 hdsp->mixer_matrix[addr] = data;
906 /* `addr' addresses a 16-bit wide address, but
907 the address space accessed via hdsp_write
908 uses byte offsets. put another way, addr
909 varies from 0 to 1351, but to access the
910 corresponding memory location, we need
911 to access 0 to 2703 ...
915 hdsp_write (hdsp, 4096 + (ad*4),
916 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
917 hdsp->mixer_matrix[addr&0x7fe]);
923 ad = (addr << 16) + data;
925 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
928 hdsp_write (hdsp, HDSP_fifoData, ad);
929 hdsp->mixer_matrix[addr] = data;
936 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
941 spin_lock_irqsave(&hdsp->lock, flags);
942 if ((hdsp->playback_pid != hdsp->capture_pid) &&
943 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
945 spin_unlock_irqrestore(&hdsp->lock, flags);
949 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
951 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
952 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
954 /* For the 9632, the mask is different */
955 if (hdsp->io_type == H9632)
956 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
958 if (status & HDSP_SPDIFErrorFlag)
962 case HDSP_spdifFrequency32KHz: return 32000;
963 case HDSP_spdifFrequency44_1KHz: return 44100;
964 case HDSP_spdifFrequency48KHz: return 48000;
965 case HDSP_spdifFrequency64KHz: return 64000;
966 case HDSP_spdifFrequency88_2KHz: return 88200;
967 case HDSP_spdifFrequency96KHz: return 96000;
968 case HDSP_spdifFrequency128KHz:
969 if (hdsp->io_type == H9632) return 128000;
971 case HDSP_spdifFrequency176_4KHz:
972 if (hdsp->io_type == H9632) return 176400;
974 case HDSP_spdifFrequency192KHz:
975 if (hdsp->io_type == H9632) return 192000;
980 dev_warn(hdsp->card->dev,
981 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
986 static int hdsp_external_sample_rate(struct hdsp *hdsp)
988 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
989 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
991 /* For the 9632 card, there seems to be no bit for indicating external
992 * sample rate greater than 96kHz. The card reports the corresponding
993 * single speed. So the best means seems to get spdif rate when
994 * autosync reference is spdif */
995 if (hdsp->io_type == H9632 &&
996 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
997 return hdsp_spdif_sample_rate(hdsp);
1000 case HDSP_systemFrequency32: return 32000;
1001 case HDSP_systemFrequency44_1: return 44100;
1002 case HDSP_systemFrequency48: return 48000;
1003 case HDSP_systemFrequency64: return 64000;
1004 case HDSP_systemFrequency88_2: return 88200;
1005 case HDSP_systemFrequency96: return 96000;
1011 static void hdsp_compute_period_size(struct hdsp *hdsp)
1013 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1016 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1020 position = hdsp_read(hdsp, HDSP_statusRegister);
1022 if (!hdsp->precise_ptr)
1023 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1025 position &= HDSP_BufferPositionMask;
1027 position &= (hdsp->period_bytes/2) - 1;
1031 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1033 hdsp_write (hdsp, HDSP_resetPointer, 0);
1034 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1035 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1036 * requires (?) to write again DDS value after a reset pointer
1037 * (at least, it works like this) */
1038 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1041 static void hdsp_start_audio(struct hdsp *s)
1043 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1044 hdsp_write(s, HDSP_controlRegister, s->control_register);
1047 static void hdsp_stop_audio(struct hdsp *s)
1049 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1050 hdsp_write(s, HDSP_controlRegister, s->control_register);
1053 static void hdsp_silence_playback(struct hdsp *hdsp)
1055 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1058 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1062 spin_lock_irq(&s->lock);
1071 s->control_register &= ~HDSP_LatencyMask;
1072 s->control_register |= hdsp_encode_latency(n);
1074 hdsp_write(s, HDSP_controlRegister, s->control_register);
1076 hdsp_compute_period_size(s);
1078 spin_unlock_irq(&s->lock);
1083 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1089 else if (rate >= 56000)
1093 n = div_u64(n, rate);
1094 /* n should be less than 2^32 for being written to FREQ register */
1095 snd_BUG_ON(n >> 32);
1096 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1097 value to write it after a reset */
1098 hdsp->dds_value = n;
1099 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1102 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1104 int reject_if_open = 0;
1108 /* ASSUMPTION: hdsp->lock is either held, or
1109 there is no need for it (e.g. during module
1113 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1114 if (called_internally) {
1115 /* request from ctl or card initialization */
1116 dev_err(hdsp->card->dev,
1117 "device is not running as a clock master: cannot set sample rate.\n");
1120 /* hw_param request while in AutoSync mode */
1121 int external_freq = hdsp_external_sample_rate(hdsp);
1122 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1124 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1125 dev_info(hdsp->card->dev,
1126 "Detected ADAT in double speed mode\n");
1127 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1128 dev_info(hdsp->card->dev,
1129 "Detected ADAT in quad speed mode\n");
1130 else if (rate != external_freq) {
1131 dev_info(hdsp->card->dev,
1132 "No AutoSync source for requested rate\n");
1138 current_rate = hdsp->system_sample_rate;
1140 /* Changing from a "single speed" to a "double speed" rate is
1141 not allowed if any substreams are open. This is because
1142 such a change causes a shift in the location of
1143 the DMA buffers and a reduction in the number of available
1146 Note that a similar but essentially insoluble problem
1147 exists for externally-driven rate changes. All we can do
1148 is to flag rate changes in the read/write routines. */
1150 if (rate > 96000 && hdsp->io_type != H9632)
1155 if (current_rate > 48000)
1157 rate_bits = HDSP_Frequency32KHz;
1160 if (current_rate > 48000)
1162 rate_bits = HDSP_Frequency44_1KHz;
1165 if (current_rate > 48000)
1167 rate_bits = HDSP_Frequency48KHz;
1170 if (current_rate <= 48000 || current_rate > 96000)
1172 rate_bits = HDSP_Frequency64KHz;
1175 if (current_rate <= 48000 || current_rate > 96000)
1177 rate_bits = HDSP_Frequency88_2KHz;
1180 if (current_rate <= 48000 || current_rate > 96000)
1182 rate_bits = HDSP_Frequency96KHz;
1185 if (current_rate < 128000)
1187 rate_bits = HDSP_Frequency128KHz;
1190 if (current_rate < 128000)
1192 rate_bits = HDSP_Frequency176_4KHz;
1195 if (current_rate < 128000)
1197 rate_bits = HDSP_Frequency192KHz;
1203 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1204 dev_warn(hdsp->card->dev,
1205 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1207 hdsp->playback_pid);
1211 hdsp->control_register &= ~HDSP_FrequencyMask;
1212 hdsp->control_register |= rate_bits;
1213 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1215 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1216 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1217 hdsp_set_dds_value(hdsp, rate);
1219 if (rate >= 128000) {
1220 hdsp->channel_map = channel_map_H9632_qs;
1221 } else if (rate > 48000) {
1222 if (hdsp->io_type == H9632)
1223 hdsp->channel_map = channel_map_H9632_ds;
1225 hdsp->channel_map = channel_map_ds;
1227 switch (hdsp->io_type) {
1230 hdsp->channel_map = channel_map_mf_ss;
1234 hdsp->channel_map = channel_map_df_ss;
1237 hdsp->channel_map = channel_map_H9632_ss;
1240 /* should never happen */
1245 hdsp->system_sample_rate = rate;
1250 /*----------------------------------------------------------------------------
1252 ----------------------------------------------------------------------------*/
1254 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1256 /* the hardware already does the relevant bit-mask with 0xff */
1258 return hdsp_read(hdsp, HDSP_midiDataIn1);
1260 return hdsp_read(hdsp, HDSP_midiDataIn0);
1263 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1265 /* the hardware already does the relevant bit-mask with 0xff */
1267 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1269 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1272 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1275 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1277 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1280 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1282 int fifo_bytes_used;
1285 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1287 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1289 if (fifo_bytes_used < 128)
1290 return 128 - fifo_bytes_used;
1295 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1297 while (snd_hdsp_midi_input_available (hdsp, id))
1298 snd_hdsp_midi_read_byte (hdsp, id);
1301 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1303 unsigned long flags;
1307 unsigned char buf[128];
1309 /* Output is not interrupt driven */
1311 spin_lock_irqsave (&hmidi->lock, flags);
1312 if (hmidi->output) {
1313 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1314 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
1315 if (n_pending > 0) {
1316 if (n_pending > (int)sizeof (buf))
1317 n_pending = sizeof (buf);
1319 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
1321 for (i = 0; i < to_write; ++i)
1322 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1327 spin_unlock_irqrestore (&hmidi->lock, flags);
1331 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1333 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1334 unsigned long flags;
1338 spin_lock_irqsave (&hmidi->lock, flags);
1339 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
1340 if (n_pending > 0) {
1342 if (n_pending > (int)sizeof (buf))
1343 n_pending = sizeof (buf);
1344 for (i = 0; i < n_pending; ++i)
1345 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1347 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1349 /* flush the MIDI input FIFO */
1351 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1356 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1358 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1359 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1360 spin_unlock_irqrestore (&hmidi->lock, flags);
1361 return snd_hdsp_midi_output_write (hmidi);
1364 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1367 struct hdsp_midi *hmidi;
1368 unsigned long flags;
1371 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1373 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1374 spin_lock_irqsave (&hdsp->lock, flags);
1376 if (!(hdsp->control_register & ie)) {
1377 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1378 hdsp->control_register |= ie;
1381 hdsp->control_register &= ~ie;
1384 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1385 spin_unlock_irqrestore (&hdsp->lock, flags);
1388 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1390 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1391 unsigned long flags;
1393 snd_hdsp_midi_output_write(hmidi);
1394 spin_lock_irqsave (&hmidi->lock, flags);
1396 /* this does not bump hmidi->istimer, because the
1397 kernel automatically removed the timer when it
1398 expired, and we are now adding it back, thus
1399 leaving istimer wherever it was set before.
1403 mod_timer(&hmidi->timer, 1 + jiffies);
1405 spin_unlock_irqrestore (&hmidi->lock, flags);
1408 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1410 struct hdsp_midi *hmidi;
1411 unsigned long flags;
1413 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1414 spin_lock_irqsave (&hmidi->lock, flags);
1416 if (!hmidi->istimer) {
1417 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1419 mod_timer(&hmidi->timer, 1 + jiffies);
1423 if (hmidi->istimer && --hmidi->istimer <= 0)
1424 del_timer (&hmidi->timer);
1426 spin_unlock_irqrestore (&hmidi->lock, flags);
1428 snd_hdsp_midi_output_write(hmidi);
1431 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1433 struct hdsp_midi *hmidi;
1435 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1436 spin_lock_irq (&hmidi->lock);
1437 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1438 hmidi->input = substream;
1439 spin_unlock_irq (&hmidi->lock);
1444 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1446 struct hdsp_midi *hmidi;
1448 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1449 spin_lock_irq (&hmidi->lock);
1450 hmidi->output = substream;
1451 spin_unlock_irq (&hmidi->lock);
1456 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1458 struct hdsp_midi *hmidi;
1460 snd_hdsp_midi_input_trigger (substream, 0);
1462 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1463 spin_lock_irq (&hmidi->lock);
1464 hmidi->input = NULL;
1465 spin_unlock_irq (&hmidi->lock);
1470 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1472 struct hdsp_midi *hmidi;
1474 snd_hdsp_midi_output_trigger (substream, 0);
1476 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1477 spin_lock_irq (&hmidi->lock);
1478 hmidi->output = NULL;
1479 spin_unlock_irq (&hmidi->lock);
1484 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1486 .open = snd_hdsp_midi_output_open,
1487 .close = snd_hdsp_midi_output_close,
1488 .trigger = snd_hdsp_midi_output_trigger,
1491 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1493 .open = snd_hdsp_midi_input_open,
1494 .close = snd_hdsp_midi_input_close,
1495 .trigger = snd_hdsp_midi_input_trigger,
1498 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1502 hdsp->midi[id].id = id;
1503 hdsp->midi[id].rmidi = NULL;
1504 hdsp->midi[id].input = NULL;
1505 hdsp->midi[id].output = NULL;
1506 hdsp->midi[id].hdsp = hdsp;
1507 hdsp->midi[id].istimer = 0;
1508 hdsp->midi[id].pending = 0;
1509 spin_lock_init (&hdsp->midi[id].lock);
1511 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1512 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1515 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1516 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1518 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1519 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1521 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1522 SNDRV_RAWMIDI_INFO_INPUT |
1523 SNDRV_RAWMIDI_INFO_DUPLEX;
1528 /*-----------------------------------------------------------------------------
1530 ----------------------------------------------------------------------------*/
1532 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1535 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1536 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1537 if (val & HDSP_SPDIFProfessional)
1538 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1540 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1544 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1546 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1547 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1548 if (val & HDSP_SPDIFProfessional)
1549 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1551 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1554 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1556 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1561 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1563 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1565 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1569 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1571 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1575 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1576 spin_lock_irq(&hdsp->lock);
1577 change = val != hdsp->creg_spdif;
1578 hdsp->creg_spdif = val;
1579 spin_unlock_irq(&hdsp->lock);
1583 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1585 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1592 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1594 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1598 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1600 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1604 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1605 spin_lock_irq(&hdsp->lock);
1606 change = val != hdsp->creg_spdif_stream;
1607 hdsp->creg_spdif_stream = val;
1608 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1609 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1610 spin_unlock_irq(&hdsp->lock);
1614 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1616 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1621 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1623 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1627 #define HDSP_SPDIF_IN(xname, xindex) \
1628 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1631 .info = snd_hdsp_info_spdif_in, \
1632 .get = snd_hdsp_get_spdif_in, \
1633 .put = snd_hdsp_put_spdif_in }
1635 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1637 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1640 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1642 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1643 hdsp->control_register |= hdsp_encode_spdif_in(in);
1644 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1648 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1650 static const char * const texts[4] = {
1651 "Optical", "Coaxial", "Internal", "AES"
1653 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1655 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1659 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1661 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1663 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1667 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1669 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1673 if (!snd_hdsp_use_is_exclusive(hdsp))
1675 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1676 spin_lock_irq(&hdsp->lock);
1677 change = val != hdsp_spdif_in(hdsp);
1679 hdsp_set_spdif_input(hdsp, val);
1680 spin_unlock_irq(&hdsp->lock);
1684 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1685 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1687 .private_value = xindex, \
1688 .info = snd_hdsp_info_toggle_setting, \
1689 .get = snd_hdsp_get_toggle_setting, \
1690 .put = snd_hdsp_put_toggle_setting \
1693 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1695 return (hdsp->control_register & regmask) ? 1 : 0;
1698 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1701 hdsp->control_register |= regmask;
1703 hdsp->control_register &= ~regmask;
1704 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1709 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1711 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1712 struct snd_ctl_elem_value *ucontrol)
1714 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1715 u32 regmask = kcontrol->private_value;
1717 spin_lock_irq(&hdsp->lock);
1718 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1719 spin_unlock_irq(&hdsp->lock);
1723 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1724 struct snd_ctl_elem_value *ucontrol)
1726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1727 u32 regmask = kcontrol->private_value;
1731 if (!snd_hdsp_use_is_exclusive(hdsp))
1733 val = ucontrol->value.integer.value[0] & 1;
1734 spin_lock_irq(&hdsp->lock);
1735 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1737 hdsp_set_toggle_setting(hdsp, regmask, val);
1738 spin_unlock_irq(&hdsp->lock);
1742 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1743 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1746 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1747 .info = snd_hdsp_info_spdif_sample_rate, \
1748 .get = snd_hdsp_get_spdif_sample_rate \
1751 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1753 static const char * const texts[] = {
1754 "32000", "44100", "48000", "64000", "88200", "96000",
1755 "None", "128000", "176400", "192000"
1757 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1759 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1763 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1765 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1767 switch (hdsp_spdif_sample_rate(hdsp)) {
1769 ucontrol->value.enumerated.item[0] = 0;
1772 ucontrol->value.enumerated.item[0] = 1;
1775 ucontrol->value.enumerated.item[0] = 2;
1778 ucontrol->value.enumerated.item[0] = 3;
1781 ucontrol->value.enumerated.item[0] = 4;
1784 ucontrol->value.enumerated.item[0] = 5;
1787 ucontrol->value.enumerated.item[0] = 7;
1790 ucontrol->value.enumerated.item[0] = 8;
1793 ucontrol->value.enumerated.item[0] = 9;
1796 ucontrol->value.enumerated.item[0] = 6;
1801 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1802 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1805 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1806 .info = snd_hdsp_info_system_sample_rate, \
1807 .get = snd_hdsp_get_system_sample_rate \
1810 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1812 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1817 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1819 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1821 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1825 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1826 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1829 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1830 .info = snd_hdsp_info_autosync_sample_rate, \
1831 .get = snd_hdsp_get_autosync_sample_rate \
1834 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1836 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1837 static const char * const texts[] = {
1838 "32000", "44100", "48000", "64000", "88200", "96000",
1839 "None", "128000", "176400", "192000"
1842 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1846 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1848 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1850 switch (hdsp_external_sample_rate(hdsp)) {
1852 ucontrol->value.enumerated.item[0] = 0;
1855 ucontrol->value.enumerated.item[0] = 1;
1858 ucontrol->value.enumerated.item[0] = 2;
1861 ucontrol->value.enumerated.item[0] = 3;
1864 ucontrol->value.enumerated.item[0] = 4;
1867 ucontrol->value.enumerated.item[0] = 5;
1870 ucontrol->value.enumerated.item[0] = 7;
1873 ucontrol->value.enumerated.item[0] = 8;
1876 ucontrol->value.enumerated.item[0] = 9;
1879 ucontrol->value.enumerated.item[0] = 6;
1884 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1885 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1888 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1889 .info = snd_hdsp_info_system_clock_mode, \
1890 .get = snd_hdsp_get_system_clock_mode \
1893 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1895 if (hdsp->control_register & HDSP_ClockModeMaster)
1897 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1902 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1904 static const char * const texts[] = {"Master", "Slave" };
1906 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1909 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1911 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1913 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1917 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1918 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1921 .info = snd_hdsp_info_clock_source, \
1922 .get = snd_hdsp_get_clock_source, \
1923 .put = snd_hdsp_put_clock_source \
1926 static int hdsp_clock_source(struct hdsp *hdsp)
1928 if (hdsp->control_register & HDSP_ClockModeMaster) {
1929 switch (hdsp->system_sample_rate) {
1956 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1960 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1961 if (hdsp_external_sample_rate(hdsp) != 0) {
1962 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1963 hdsp->control_register &= ~HDSP_ClockModeMaster;
1964 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1969 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1972 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1975 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1978 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1981 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1984 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1987 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1990 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1993 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
1999 hdsp->control_register |= HDSP_ClockModeMaster;
2000 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2001 hdsp_set_rate(hdsp, rate, 1);
2005 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2007 static const char * const texts[] = {
2008 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2009 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2010 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2011 "Internal 192.0 KHz"
2013 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2015 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2019 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2021 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2023 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2027 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2029 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2033 if (!snd_hdsp_use_is_exclusive(hdsp))
2035 val = ucontrol->value.enumerated.item[0];
2036 if (val < 0) val = 0;
2037 if (hdsp->io_type == H9632) {
2044 spin_lock_irq(&hdsp->lock);
2045 if (val != hdsp_clock_source(hdsp))
2046 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2049 spin_unlock_irq(&hdsp->lock);
2053 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2055 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2057 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2059 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2063 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2065 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2068 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2070 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2074 #define HDSP_DA_GAIN(xname, xindex) \
2075 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2078 .info = snd_hdsp_info_da_gain, \
2079 .get = snd_hdsp_get_da_gain, \
2080 .put = snd_hdsp_put_da_gain \
2083 static int hdsp_da_gain(struct hdsp *hdsp)
2085 switch (hdsp->control_register & HDSP_DAGainMask) {
2086 case HDSP_DAGainHighGain:
2088 case HDSP_DAGainPlus4dBu:
2090 case HDSP_DAGainMinus10dBV:
2097 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2099 hdsp->control_register &= ~HDSP_DAGainMask;
2102 hdsp->control_register |= HDSP_DAGainHighGain;
2105 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2108 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2114 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2118 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2120 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2122 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2125 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2127 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2129 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2133 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2135 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2139 if (!snd_hdsp_use_is_exclusive(hdsp))
2141 val = ucontrol->value.enumerated.item[0];
2142 if (val < 0) val = 0;
2143 if (val > 2) val = 2;
2144 spin_lock_irq(&hdsp->lock);
2145 if (val != hdsp_da_gain(hdsp))
2146 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2149 spin_unlock_irq(&hdsp->lock);
2153 #define HDSP_AD_GAIN(xname, xindex) \
2154 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2157 .info = snd_hdsp_info_ad_gain, \
2158 .get = snd_hdsp_get_ad_gain, \
2159 .put = snd_hdsp_put_ad_gain \
2162 static int hdsp_ad_gain(struct hdsp *hdsp)
2164 switch (hdsp->control_register & HDSP_ADGainMask) {
2165 case HDSP_ADGainMinus10dBV:
2167 case HDSP_ADGainPlus4dBu:
2169 case HDSP_ADGainLowGain:
2176 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2178 hdsp->control_register &= ~HDSP_ADGainMask;
2181 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2184 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2187 hdsp->control_register |= HDSP_ADGainLowGain;
2193 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2197 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2199 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2201 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2204 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2206 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2208 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2212 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2214 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2218 if (!snd_hdsp_use_is_exclusive(hdsp))
2220 val = ucontrol->value.enumerated.item[0];
2221 if (val < 0) val = 0;
2222 if (val > 2) val = 2;
2223 spin_lock_irq(&hdsp->lock);
2224 if (val != hdsp_ad_gain(hdsp))
2225 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2228 spin_unlock_irq(&hdsp->lock);
2232 #define HDSP_PHONE_GAIN(xname, xindex) \
2233 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2236 .info = snd_hdsp_info_phone_gain, \
2237 .get = snd_hdsp_get_phone_gain, \
2238 .put = snd_hdsp_put_phone_gain \
2241 static int hdsp_phone_gain(struct hdsp *hdsp)
2243 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2244 case HDSP_PhoneGain0dB:
2246 case HDSP_PhoneGainMinus6dB:
2248 case HDSP_PhoneGainMinus12dB:
2255 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2257 hdsp->control_register &= ~HDSP_PhoneGainMask;
2260 hdsp->control_register |= HDSP_PhoneGain0dB;
2263 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2266 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2272 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2276 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2278 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2280 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2283 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2285 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2287 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2291 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2293 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2297 if (!snd_hdsp_use_is_exclusive(hdsp))
2299 val = ucontrol->value.enumerated.item[0];
2300 if (val < 0) val = 0;
2301 if (val > 2) val = 2;
2302 spin_lock_irq(&hdsp->lock);
2303 if (val != hdsp_phone_gain(hdsp))
2304 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2307 spin_unlock_irq(&hdsp->lock);
2311 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2312 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2315 .info = snd_hdsp_info_pref_sync_ref, \
2316 .get = snd_hdsp_get_pref_sync_ref, \
2317 .put = snd_hdsp_put_pref_sync_ref \
2320 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2322 /* Notice that this looks at the requested sync source,
2323 not the one actually in use.
2326 switch (hdsp->control_register & HDSP_SyncRefMask) {
2327 case HDSP_SyncRef_ADAT1:
2328 return HDSP_SYNC_FROM_ADAT1;
2329 case HDSP_SyncRef_ADAT2:
2330 return HDSP_SYNC_FROM_ADAT2;
2331 case HDSP_SyncRef_ADAT3:
2332 return HDSP_SYNC_FROM_ADAT3;
2333 case HDSP_SyncRef_SPDIF:
2334 return HDSP_SYNC_FROM_SPDIF;
2335 case HDSP_SyncRef_WORD:
2336 return HDSP_SYNC_FROM_WORD;
2337 case HDSP_SyncRef_ADAT_SYNC:
2338 return HDSP_SYNC_FROM_ADAT_SYNC;
2340 return HDSP_SYNC_FROM_WORD;
2345 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2347 hdsp->control_register &= ~HDSP_SyncRefMask;
2349 case HDSP_SYNC_FROM_ADAT1:
2350 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2352 case HDSP_SYNC_FROM_ADAT2:
2353 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2355 case HDSP_SYNC_FROM_ADAT3:
2356 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2358 case HDSP_SYNC_FROM_SPDIF:
2359 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2361 case HDSP_SYNC_FROM_WORD:
2362 hdsp->control_register |= HDSP_SyncRef_WORD;
2364 case HDSP_SYNC_FROM_ADAT_SYNC:
2365 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2370 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2374 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2376 static const char * const texts[] = {
2377 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2379 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2382 switch (hdsp->io_type) {
2397 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2400 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2402 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2404 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2408 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2410 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2414 if (!snd_hdsp_use_is_exclusive(hdsp))
2417 switch (hdsp->io_type) {
2432 val = ucontrol->value.enumerated.item[0] % max;
2433 spin_lock_irq(&hdsp->lock);
2434 change = (int)val != hdsp_pref_sync_ref(hdsp);
2435 hdsp_set_pref_sync_ref(hdsp, val);
2436 spin_unlock_irq(&hdsp->lock);
2440 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2441 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2444 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2445 .info = snd_hdsp_info_autosync_ref, \
2446 .get = snd_hdsp_get_autosync_ref, \
2449 static int hdsp_autosync_ref(struct hdsp *hdsp)
2451 /* This looks at the autosync selected sync reference */
2452 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2454 switch (status2 & HDSP_SelSyncRefMask) {
2455 case HDSP_SelSyncRef_WORD:
2456 return HDSP_AUTOSYNC_FROM_WORD;
2457 case HDSP_SelSyncRef_ADAT_SYNC:
2458 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2459 case HDSP_SelSyncRef_SPDIF:
2460 return HDSP_AUTOSYNC_FROM_SPDIF;
2461 case HDSP_SelSyncRefMask:
2462 return HDSP_AUTOSYNC_FROM_NONE;
2463 case HDSP_SelSyncRef_ADAT1:
2464 return HDSP_AUTOSYNC_FROM_ADAT1;
2465 case HDSP_SelSyncRef_ADAT2:
2466 return HDSP_AUTOSYNC_FROM_ADAT2;
2467 case HDSP_SelSyncRef_ADAT3:
2468 return HDSP_AUTOSYNC_FROM_ADAT3;
2470 return HDSP_AUTOSYNC_FROM_WORD;
2475 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2477 static const char * const texts[] = {
2478 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2481 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2484 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2486 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2488 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2492 #define HDSP_PRECISE_POINTER(xname, xindex) \
2493 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2496 .info = snd_hdsp_info_precise_pointer, \
2497 .get = snd_hdsp_get_precise_pointer, \
2498 .put = snd_hdsp_put_precise_pointer \
2501 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2504 hdsp->precise_ptr = 1;
2506 hdsp->precise_ptr = 0;
2510 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2512 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2514 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2516 spin_lock_irq(&hdsp->lock);
2517 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2518 spin_unlock_irq(&hdsp->lock);
2522 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2524 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2528 if (!snd_hdsp_use_is_exclusive(hdsp))
2530 val = ucontrol->value.integer.value[0] & 1;
2531 spin_lock_irq(&hdsp->lock);
2532 change = (int)val != hdsp->precise_ptr;
2533 hdsp_set_precise_pointer(hdsp, val);
2534 spin_unlock_irq(&hdsp->lock);
2538 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2539 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2542 .info = snd_hdsp_info_use_midi_work, \
2543 .get = snd_hdsp_get_use_midi_work, \
2544 .put = snd_hdsp_put_use_midi_work \
2547 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2550 hdsp->use_midi_work = 1;
2552 hdsp->use_midi_work = 0;
2556 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2558 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2560 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2562 spin_lock_irq(&hdsp->lock);
2563 ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2564 spin_unlock_irq(&hdsp->lock);
2568 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2574 if (!snd_hdsp_use_is_exclusive(hdsp))
2576 val = ucontrol->value.integer.value[0] & 1;
2577 spin_lock_irq(&hdsp->lock);
2578 change = (int)val != hdsp->use_midi_work;
2579 hdsp_set_use_midi_work(hdsp, val);
2580 spin_unlock_irq(&hdsp->lock);
2584 #define HDSP_MIXER(xname, xindex) \
2585 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2589 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2590 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2591 .info = snd_hdsp_info_mixer, \
2592 .get = snd_hdsp_get_mixer, \
2593 .put = snd_hdsp_put_mixer \
2596 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2598 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2600 uinfo->value.integer.min = 0;
2601 uinfo->value.integer.max = 65536;
2602 uinfo->value.integer.step = 1;
2606 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2608 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2613 source = ucontrol->value.integer.value[0];
2614 destination = ucontrol->value.integer.value[1];
2616 if (source >= hdsp->max_channels)
2617 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2619 addr = hdsp_input_to_output_key(hdsp,source, destination);
2621 spin_lock_irq(&hdsp->lock);
2622 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2623 spin_unlock_irq(&hdsp->lock);
2627 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2629 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2636 if (!snd_hdsp_use_is_exclusive(hdsp))
2639 source = ucontrol->value.integer.value[0];
2640 destination = ucontrol->value.integer.value[1];
2642 if (source >= hdsp->max_channels)
2643 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2645 addr = hdsp_input_to_output_key(hdsp,source, destination);
2647 gain = ucontrol->value.integer.value[2];
2649 spin_lock_irq(&hdsp->lock);
2650 change = gain != hdsp_read_gain(hdsp, addr);
2652 hdsp_write_gain(hdsp, addr, gain);
2653 spin_unlock_irq(&hdsp->lock);
2657 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2658 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2661 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2662 .info = snd_hdsp_info_sync_check, \
2663 .get = snd_hdsp_get_wc_sync_check \
2666 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2668 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2670 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2673 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2675 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2676 if (status2 & HDSP_wc_lock) {
2677 if (status2 & HDSP_wc_sync)
2686 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2688 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2690 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2694 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2695 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2698 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2699 .info = snd_hdsp_info_sync_check, \
2700 .get = snd_hdsp_get_spdif_sync_check \
2703 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2705 int status = hdsp_read(hdsp, HDSP_statusRegister);
2706 if (status & HDSP_SPDIFErrorFlag)
2709 if (status & HDSP_SPDIFSync)
2717 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2719 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2721 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2725 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2726 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2729 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2730 .info = snd_hdsp_info_sync_check, \
2731 .get = snd_hdsp_get_adatsync_sync_check \
2734 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2736 int status = hdsp_read(hdsp, HDSP_statusRegister);
2737 if (status & HDSP_TimecodeLock) {
2738 if (status & HDSP_TimecodeSync)
2746 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2748 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2750 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2754 #define HDSP_ADAT_SYNC_CHECK \
2755 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2756 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2757 .info = snd_hdsp_info_sync_check, \
2758 .get = snd_hdsp_get_adat_sync_check \
2761 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2763 int status = hdsp_read(hdsp, HDSP_statusRegister);
2765 if (status & (HDSP_Lock0>>idx)) {
2766 if (status & (HDSP_Sync0>>idx))
2774 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2777 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2779 offset = ucontrol->id.index - 1;
2780 if (snd_BUG_ON(offset < 0))
2783 switch (hdsp->io_type) {
2798 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2802 #define HDSP_DDS_OFFSET(xname, xindex) \
2803 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2806 .info = snd_hdsp_info_dds_offset, \
2807 .get = snd_hdsp_get_dds_offset, \
2808 .put = snd_hdsp_put_dds_offset \
2811 static int hdsp_dds_offset(struct hdsp *hdsp)
2814 unsigned int dds_value = hdsp->dds_value;
2815 int system_sample_rate = hdsp->system_sample_rate;
2822 * dds_value = n / rate
2823 * rate = n / dds_value
2825 n = div_u64(n, dds_value);
2826 if (system_sample_rate >= 112000)
2828 else if (system_sample_rate >= 56000)
2830 return ((int)n) - system_sample_rate;
2833 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2835 int rate = hdsp->system_sample_rate + offset_hz;
2836 hdsp_set_dds_value(hdsp, rate);
2840 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2842 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2844 uinfo->value.integer.min = -5000;
2845 uinfo->value.integer.max = 5000;
2849 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2851 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2853 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2857 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2859 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2863 if (!snd_hdsp_use_is_exclusive(hdsp))
2865 val = ucontrol->value.integer.value[0];
2866 spin_lock_irq(&hdsp->lock);
2867 if (val != hdsp_dds_offset(hdsp))
2868 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2871 spin_unlock_irq(&hdsp->lock);
2875 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2876 HDSP_DA_GAIN("DA Gain", 0),
2877 HDSP_AD_GAIN("AD Gain", 0),
2878 HDSP_PHONE_GAIN("Phones Gain", 0),
2879 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2880 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2883 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2885 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2886 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2887 .info = snd_hdsp_control_spdif_info,
2888 .get = snd_hdsp_control_spdif_get,
2889 .put = snd_hdsp_control_spdif_put,
2892 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2893 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2894 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2895 .info = snd_hdsp_control_spdif_stream_info,
2896 .get = snd_hdsp_control_spdif_stream_get,
2897 .put = snd_hdsp_control_spdif_stream_put,
2900 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2901 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2902 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2903 .info = snd_hdsp_control_spdif_mask_info,
2904 .get = snd_hdsp_control_spdif_mask_get,
2905 .private_value = IEC958_AES0_NONAUDIO |
2906 IEC958_AES0_PROFESSIONAL |
2907 IEC958_AES0_CON_EMPHASIS,
2910 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2911 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2912 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2913 .info = snd_hdsp_control_spdif_mask_info,
2914 .get = snd_hdsp_control_spdif_mask_get,
2915 .private_value = IEC958_AES0_NONAUDIO |
2916 IEC958_AES0_PROFESSIONAL |
2917 IEC958_AES0_PRO_EMPHASIS,
2919 HDSP_MIXER("Mixer", 0),
2920 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2921 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2922 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2923 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2924 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2925 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2926 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2928 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2929 .name = "Sample Clock Source Locking",
2930 .info = snd_hdsp_info_clock_source_lock,
2931 .get = snd_hdsp_get_clock_source_lock,
2932 .put = snd_hdsp_put_clock_source_lock,
2934 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2935 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2936 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2937 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2938 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2939 /* 'External Rate' complies with the alsa control naming scheme */
2940 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2941 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2942 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2943 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2944 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2945 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2946 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2950 static int hdsp_rpm_input12(struct hdsp *hdsp)
2952 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2953 case HDSP_RPM_Inp12_Phon_6dB:
2955 case HDSP_RPM_Inp12_Phon_n6dB:
2957 case HDSP_RPM_Inp12_Line_0dB:
2959 case HDSP_RPM_Inp12_Line_n6dB:
2966 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2968 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2970 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2975 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2977 hdsp->control_register &= ~HDSP_RPM_Inp12;
2980 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2985 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2988 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2991 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2997 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3002 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3004 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3008 if (!snd_hdsp_use_is_exclusive(hdsp))
3010 val = ucontrol->value.enumerated.item[0];
3015 spin_lock_irq(&hdsp->lock);
3016 if (val != hdsp_rpm_input12(hdsp))
3017 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3020 spin_unlock_irq(&hdsp->lock);
3025 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3027 static const char * const texts[] = {
3028 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3031 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3035 static int hdsp_rpm_input34(struct hdsp *hdsp)
3037 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3038 case HDSP_RPM_Inp34_Phon_6dB:
3040 case HDSP_RPM_Inp34_Phon_n6dB:
3042 case HDSP_RPM_Inp34_Line_0dB:
3044 case HDSP_RPM_Inp34_Line_n6dB:
3051 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3053 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3055 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3060 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3062 hdsp->control_register &= ~HDSP_RPM_Inp34;
3065 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3070 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3073 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3076 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3082 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3087 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3089 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3093 if (!snd_hdsp_use_is_exclusive(hdsp))
3095 val = ucontrol->value.enumerated.item[0];
3100 spin_lock_irq(&hdsp->lock);
3101 if (val != hdsp_rpm_input34(hdsp))
3102 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3105 spin_unlock_irq(&hdsp->lock);
3110 /* RPM Bypass switch */
3111 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3113 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3117 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3119 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3121 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3126 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3129 hdsp->control_register |= HDSP_RPM_Bypass;
3131 hdsp->control_register &= ~HDSP_RPM_Bypass;
3132 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3137 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3139 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3143 if (!snd_hdsp_use_is_exclusive(hdsp))
3145 val = ucontrol->value.integer.value[0] & 1;
3146 spin_lock_irq(&hdsp->lock);
3147 change = (int)val != hdsp_rpm_bypass(hdsp);
3148 hdsp_set_rpm_bypass(hdsp, val);
3149 spin_unlock_irq(&hdsp->lock);
3154 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3156 static const char * const texts[] = {"On", "Off"};
3158 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3162 /* RPM Disconnect switch */
3163 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3165 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3169 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3171 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3173 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3178 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3181 hdsp->control_register |= HDSP_RPM_Disconnect;
3183 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3184 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3189 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3191 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3195 if (!snd_hdsp_use_is_exclusive(hdsp))
3197 val = ucontrol->value.integer.value[0] & 1;
3198 spin_lock_irq(&hdsp->lock);
3199 change = (int)val != hdsp_rpm_disconnect(hdsp);
3200 hdsp_set_rpm_disconnect(hdsp, val);
3201 spin_unlock_irq(&hdsp->lock);
3205 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3207 static const char * const texts[] = {"On", "Off"};
3209 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3212 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3214 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3215 .name = "RPM Bypass",
3216 .get = snd_hdsp_get_rpm_bypass,
3217 .put = snd_hdsp_put_rpm_bypass,
3218 .info = snd_hdsp_info_rpm_bypass
3221 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222 .name = "RPM Disconnect",
3223 .get = snd_hdsp_get_rpm_disconnect,
3224 .put = snd_hdsp_put_rpm_disconnect,
3225 .info = snd_hdsp_info_rpm_disconnect
3228 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229 .name = "Input 1/2",
3230 .get = snd_hdsp_get_rpm_input12,
3231 .put = snd_hdsp_put_rpm_input12,
3232 .info = snd_hdsp_info_rpm_input
3235 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236 .name = "Input 3/4",
3237 .get = snd_hdsp_get_rpm_input34,
3238 .put = snd_hdsp_put_rpm_input34,
3239 .info = snd_hdsp_info_rpm_input
3241 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3242 HDSP_MIXER("Mixer", 0)
3245 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3246 HDSP_TOGGLE_SETTING("Analog Extension Board",
3247 HDSP_AnalogExtensionBoard);
3248 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3251 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3253 return hdsp->io_loopback & (1 << channel);
3256 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3258 if (hdsp_loopback_get(hdsp, channel) == enable)
3261 hdsp->io_loopback ^= (1 << channel);
3263 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3268 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3269 struct snd_ctl_elem_value *const ucontrol)
3271 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3272 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3274 if (channel >= hdsp->max_channels)
3277 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3282 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3283 struct snd_ctl_elem_value *const ucontrol)
3285 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3286 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3287 const bool enable = ucontrol->value.integer.value[0] & 1;
3289 if (channel >= hdsp->max_channels)
3292 return hdsp_loopback_set(hdsp, channel, enable);
3295 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3296 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3297 .name = "Output Loopback",
3298 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3299 .info = snd_ctl_boolean_mono_info,
3300 .get = snd_hdsp_loopback_get,
3301 .put = snd_hdsp_loopback_put
3304 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3308 struct snd_kcontrol *kctl;
3310 if (hdsp->io_type == RPM) {
3311 /* RPM Bypass, Disconnect and Input switches */
3312 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3313 err = snd_ctl_add(card, snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3320 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3321 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);
3322 err = snd_ctl_add(card, kctl);
3325 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3326 hdsp->spdif_ctl = kctl;
3329 /* ADAT SyncCheck status */
3330 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3331 snd_hdsp_adat_sync_check.index = 1;
3332 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3333 err = snd_ctl_add(card, kctl);
3336 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3337 for (idx = 1; idx < 3; ++idx) {
3338 snd_hdsp_adat_sync_check.index = idx+1;
3339 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3340 err = snd_ctl_add(card, kctl);
3346 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3347 if (hdsp->io_type == H9632) {
3348 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3349 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);
3350 err = snd_ctl_add(card, kctl);
3356 /* Output loopback controls for H9632 cards */
3357 if (hdsp->io_type == H9632) {
3358 snd_hdsp_loopback_control.count = hdsp->max_channels;
3359 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3362 err = snd_ctl_add(card, kctl);
3367 /* AEB control for H96xx card */
3368 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3369 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);
3370 err = snd_ctl_add(card, kctl);
3378 /*------------------------------------------------------------
3380 ------------------------------------------------------------*/
3383 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3385 struct hdsp *hdsp = entry->private_data;
3386 unsigned int status;
3387 unsigned int status2;
3388 char *pref_sync_ref;
3390 char *system_clock_mode;
3394 status = hdsp_read(hdsp, HDSP_statusRegister);
3395 status2 = hdsp_read(hdsp, HDSP_status2Register);
3397 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3398 hdsp->card->number + 1);
3399 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3400 hdsp->capture_buffer, hdsp->playback_buffer);
3401 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3402 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3403 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3404 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3405 hdsp->control2_register);
3406 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3407 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3409 if (hdsp_check_for_iobox(hdsp)) {
3410 snd_iprintf(buffer, "No I/O box connected.\n"
3411 "Please connect one and upload firmware.\n");
3415 if (hdsp_check_for_firmware(hdsp, 0)) {
3416 if (hdsp->state & HDSP_FirmwareCached) {
3417 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3418 snd_iprintf(buffer, "Firmware loading from "
3420 "please upload manually.\n");
3426 err = hdsp_request_fw_loader(hdsp);
3429 "No firmware loaded nor cached, "
3430 "please upload firmware.\n");
3436 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3437 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3438 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3439 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3440 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3441 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3443 snd_iprintf(buffer, "\n");
3445 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3447 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3448 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3449 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3450 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3452 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3454 snd_iprintf(buffer, "\n");
3456 switch (hdsp_clock_source(hdsp)) {
3457 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3458 clock_source = "AutoSync";
3460 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3461 clock_source = "Internal 32 kHz";
3463 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3464 clock_source = "Internal 44.1 kHz";
3466 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3467 clock_source = "Internal 48 kHz";
3469 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3470 clock_source = "Internal 64 kHz";
3472 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3473 clock_source = "Internal 88.2 kHz";
3475 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3476 clock_source = "Internal 96 kHz";
3478 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3479 clock_source = "Internal 128 kHz";
3481 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3482 clock_source = "Internal 176.4 kHz";
3484 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3485 clock_source = "Internal 192 kHz";
3488 clock_source = "Error";
3490 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3492 if (hdsp_system_clock_mode(hdsp))
3493 system_clock_mode = "Slave";
3495 system_clock_mode = "Master";
3497 switch (hdsp_pref_sync_ref (hdsp)) {
3498 case HDSP_SYNC_FROM_WORD:
3499 pref_sync_ref = "Word Clock";
3501 case HDSP_SYNC_FROM_ADAT_SYNC:
3502 pref_sync_ref = "ADAT Sync";
3504 case HDSP_SYNC_FROM_SPDIF:
3505 pref_sync_ref = "SPDIF";
3507 case HDSP_SYNC_FROM_ADAT1:
3508 pref_sync_ref = "ADAT1";
3510 case HDSP_SYNC_FROM_ADAT2:
3511 pref_sync_ref = "ADAT2";
3513 case HDSP_SYNC_FROM_ADAT3:
3514 pref_sync_ref = "ADAT3";
3517 pref_sync_ref = "Word Clock";
3520 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3522 switch (hdsp_autosync_ref (hdsp)) {
3523 case HDSP_AUTOSYNC_FROM_WORD:
3524 autosync_ref = "Word Clock";
3526 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3527 autosync_ref = "ADAT Sync";
3529 case HDSP_AUTOSYNC_FROM_SPDIF:
3530 autosync_ref = "SPDIF";
3532 case HDSP_AUTOSYNC_FROM_NONE:
3533 autosync_ref = "None";
3535 case HDSP_AUTOSYNC_FROM_ADAT1:
3536 autosync_ref = "ADAT1";
3538 case HDSP_AUTOSYNC_FROM_ADAT2:
3539 autosync_ref = "ADAT2";
3541 case HDSP_AUTOSYNC_FROM_ADAT3:
3542 autosync_ref = "ADAT3";
3545 autosync_ref = "---";
3548 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3550 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3552 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3554 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3555 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3557 snd_iprintf(buffer, "\n");
3559 if (hdsp->io_type != RPM) {
3560 switch (hdsp_spdif_in(hdsp)) {
3561 case HDSP_SPDIFIN_OPTICAL:
3562 snd_iprintf(buffer, "IEC958 input: Optical\n");
3564 case HDSP_SPDIFIN_COAXIAL:
3565 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3567 case HDSP_SPDIFIN_INTERNAL:
3568 snd_iprintf(buffer, "IEC958 input: Internal\n");
3570 case HDSP_SPDIFIN_AES:
3571 snd_iprintf(buffer, "IEC958 input: AES\n");
3574 snd_iprintf(buffer, "IEC958 input: ???\n");
3579 if (RPM == hdsp->io_type) {
3580 if (hdsp->control_register & HDSP_RPM_Bypass)
3581 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3583 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3584 if (hdsp->control_register & HDSP_RPM_Disconnect)
3585 snd_iprintf(buffer, "RPM disconnected\n");
3587 snd_iprintf(buffer, "RPM connected\n");
3589 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3590 case HDSP_RPM_Inp12_Phon_6dB:
3591 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3593 case HDSP_RPM_Inp12_Phon_0dB:
3594 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3596 case HDSP_RPM_Inp12_Phon_n6dB:
3597 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3599 case HDSP_RPM_Inp12_Line_0dB:
3600 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3602 case HDSP_RPM_Inp12_Line_n6dB:
3603 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3606 snd_iprintf(buffer, "Input 1/2: ???\n");
3609 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3610 case HDSP_RPM_Inp34_Phon_6dB:
3611 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3613 case HDSP_RPM_Inp34_Phon_0dB:
3614 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3616 case HDSP_RPM_Inp34_Phon_n6dB:
3617 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3619 case HDSP_RPM_Inp34_Line_0dB:
3620 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3622 case HDSP_RPM_Inp34_Line_n6dB:
3623 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3626 snd_iprintf(buffer, "Input 3/4: ???\n");
3630 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3631 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3633 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3635 if (hdsp->control_register & HDSP_SPDIFProfessional)
3636 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3638 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3640 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3641 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3643 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3645 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3646 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3648 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3649 x = hdsp_spdif_sample_rate(hdsp);
3651 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3653 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3655 snd_iprintf(buffer, "\n");
3658 x = status & HDSP_Sync0;
3659 if (status & HDSP_Lock0)
3660 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3662 snd_iprintf(buffer, "ADAT1: No Lock\n");
3664 switch (hdsp->io_type) {
3667 x = status & HDSP_Sync1;
3668 if (status & HDSP_Lock1)
3669 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3671 snd_iprintf(buffer, "ADAT2: No Lock\n");
3672 x = status & HDSP_Sync2;
3673 if (status & HDSP_Lock2)
3674 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3676 snd_iprintf(buffer, "ADAT3: No Lock\n");
3683 x = status & HDSP_SPDIFSync;
3684 if (status & HDSP_SPDIFErrorFlag)
3685 snd_iprintf (buffer, "SPDIF: No Lock\n");
3687 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3689 x = status2 & HDSP_wc_sync;
3690 if (status2 & HDSP_wc_lock)
3691 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3693 snd_iprintf (buffer, "Word Clock: No Lock\n");
3695 x = status & HDSP_TimecodeSync;
3696 if (status & HDSP_TimecodeLock)
3697 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3699 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3701 snd_iprintf(buffer, "\n");
3703 /* Informations about H9632 specific controls */
3704 if (hdsp->io_type == H9632) {
3707 switch (hdsp_ad_gain(hdsp)) {
3718 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3720 switch (hdsp_da_gain(hdsp)) {
3731 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3733 switch (hdsp_phone_gain(hdsp)) {
3744 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3746 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3747 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3750 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3751 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3753 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3754 snd_iprintf(buffer, "\n");
3759 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3761 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3764 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3766 struct snd_dma_buffer *capture_dma, *playback_dma;
3768 capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3769 playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3770 if (!capture_dma || !playback_dma) {
3771 dev_err(hdsp->card->dev,
3772 "%s: no buffers available\n", hdsp->card_name);
3776 /* copy to the own data for alignment */
3777 hdsp->capture_dma_buf = *capture_dma;
3778 hdsp->playback_dma_buf = *playback_dma;
3780 /* Align to bus-space 64K boundary */
3781 hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
3782 hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
3784 /* Tell the card where it is */
3785 hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr);
3786 hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr);
3788 hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr;
3789 hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr;
3790 hdsp->capture_buffer = hdsp->capture_dma_buf.area;
3791 hdsp->playback_buffer = hdsp->playback_dma_buf.area;
3796 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3800 /* ASSUMPTION: hdsp->lock is either held, or
3801 there is no need to hold it (e.g. during module
3807 SPDIF Input via Coax
3809 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3810 which implies 2 4096 sample, 32Kbyte periods).
3814 hdsp->control_register = HDSP_ClockModeMaster |
3815 HDSP_SPDIFInputCoaxial |
3816 hdsp_encode_latency(7) |
3820 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3822 #ifdef SNDRV_BIG_ENDIAN
3823 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3825 hdsp->control2_register = 0;
3827 if (hdsp->io_type == H9652)
3828 snd_hdsp_9652_enable_mixer (hdsp);
3830 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3832 hdsp_reset_hw_pointer(hdsp);
3833 hdsp_compute_period_size(hdsp);
3835 /* silence everything */
3837 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3838 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3840 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3841 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3845 /* H9632 specific defaults */
3846 if (hdsp->io_type == H9632) {
3847 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3848 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3851 /* set a default rate so that the channel map is set up.
3854 hdsp_set_rate(hdsp, 48000, 1);
3859 static void hdsp_midi_work(struct work_struct *work)
3861 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3863 if (hdsp->midi[0].pending)
3864 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3865 if (hdsp->midi[1].pending)
3866 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3869 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3871 struct hdsp *hdsp = (struct hdsp *) dev_id;
3872 unsigned int status;
3876 unsigned int midi0status;
3877 unsigned int midi1status;
3880 status = hdsp_read(hdsp, HDSP_statusRegister);
3882 audio = status & HDSP_audioIRQPending;
3883 midi0 = status & HDSP_midi0IRQPending;
3884 midi1 = status & HDSP_midi1IRQPending;
3886 if (!audio && !midi0 && !midi1)
3889 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3891 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3892 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3894 if (!(hdsp->state & HDSP_InitializationComplete))
3898 if (hdsp->capture_substream)
3899 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3901 if (hdsp->playback_substream)
3902 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3905 if (midi0 && midi0status) {
3906 if (hdsp->use_midi_work) {
3907 /* we disable interrupts for this input until processing is done */
3908 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3909 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3910 hdsp->midi[0].pending = 1;
3913 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3916 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3917 if (hdsp->use_midi_work) {
3918 /* we disable interrupts for this input until processing is done */
3919 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3920 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3921 hdsp->midi[1].pending = 1;
3924 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3927 if (hdsp->use_midi_work && schedule)
3928 queue_work(system_highpri_wq, &hdsp->midi_work);
3932 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3934 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935 return hdsp_hw_pointer(hdsp);
3938 static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3945 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3948 mapped_channel = hdsp->channel_map[channel];
3949 if (mapped_channel < 0)
3952 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3953 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3955 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3958 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3959 int channel, unsigned long pos,
3960 struct iov_iter *src, unsigned long count)
3962 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3963 signed char *channel_buf;
3965 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3968 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3969 if (snd_BUG_ON(!channel_buf))
3971 if (copy_from_iter(channel_buf + pos, count, src) != count)
3976 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3977 int channel, unsigned long pos,
3978 struct iov_iter *dst, unsigned long count)
3980 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3981 signed char *channel_buf;
3983 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3986 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3987 if (snd_BUG_ON(!channel_buf))
3989 if (copy_to_iter(channel_buf + pos, count, dst) != count)
3994 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3995 int channel, unsigned long pos,
3996 unsigned long count)
3998 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3999 signed char *channel_buf;
4001 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4002 if (snd_BUG_ON(!channel_buf))
4004 memset(channel_buf + pos, 0, count);
4008 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4010 struct snd_pcm_runtime *runtime = substream->runtime;
4011 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4012 struct snd_pcm_substream *other;
4013 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4014 other = hdsp->capture_substream;
4016 other = hdsp->playback_substream;
4018 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4020 runtime->status->hw_ptr = 0;
4022 struct snd_pcm_substream *s;
4023 struct snd_pcm_runtime *oruntime = other->runtime;
4024 snd_pcm_group_for_each_entry(s, substream) {
4026 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4034 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4035 struct snd_pcm_hw_params *params)
4037 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4042 if (hdsp_check_for_iobox (hdsp))
4045 if (hdsp_check_for_firmware(hdsp, 1))
4048 spin_lock_irq(&hdsp->lock);
4050 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4051 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4052 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4053 this_pid = hdsp->playback_pid;
4054 other_pid = hdsp->capture_pid;
4056 this_pid = hdsp->capture_pid;
4057 other_pid = hdsp->playback_pid;
4060 if ((other_pid > 0) && (this_pid != other_pid)) {
4062 /* The other stream is open, and not by the same
4063 task as this one. Make sure that the parameters
4064 that matter are the same.
4067 if (params_rate(params) != hdsp->system_sample_rate) {
4068 spin_unlock_irq(&hdsp->lock);
4069 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4073 if (params_period_size(params) != hdsp->period_bytes / 4) {
4074 spin_unlock_irq(&hdsp->lock);
4075 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4081 spin_unlock_irq(&hdsp->lock);
4085 spin_unlock_irq(&hdsp->lock);
4088 /* how to make sure that the rate matches an externally-set one ?
4091 spin_lock_irq(&hdsp->lock);
4092 if (! hdsp->clock_source_locked) {
4093 err = hdsp_set_rate(hdsp, params_rate(params), 0);
4095 spin_unlock_irq(&hdsp->lock);
4096 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4100 spin_unlock_irq(&hdsp->lock);
4102 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));
4104 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4111 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4112 struct snd_pcm_channel_info *info)
4114 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4115 unsigned int channel = info->channel;
4117 if (snd_BUG_ON(channel >= hdsp->max_channels))
4119 channel = array_index_nospec(channel, hdsp->max_channels);
4121 if (hdsp->channel_map[channel] < 0)
4124 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4130 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4131 unsigned int cmd, void *arg)
4134 case SNDRV_PCM_IOCTL1_RESET:
4135 return snd_hdsp_reset(substream);
4136 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4137 return snd_hdsp_channel_info(substream, arg);
4142 return snd_pcm_lib_ioctl(substream, cmd, arg);
4145 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4147 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4148 struct snd_pcm_substream *other;
4151 if (hdsp_check_for_iobox (hdsp))
4154 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4157 spin_lock(&hdsp->lock);
4158 running = hdsp->running;
4160 case SNDRV_PCM_TRIGGER_START:
4161 running |= 1 << substream->stream;
4163 case SNDRV_PCM_TRIGGER_STOP:
4164 running &= ~(1 << substream->stream);
4168 spin_unlock(&hdsp->lock);
4171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4172 other = hdsp->capture_substream;
4174 other = hdsp->playback_substream;
4177 struct snd_pcm_substream *s;
4178 snd_pcm_group_for_each_entry(s, substream) {
4180 snd_pcm_trigger_done(s, substream);
4181 if (cmd == SNDRV_PCM_TRIGGER_START)
4182 running |= 1 << s->stream;
4184 running &= ~(1 << s->stream);
4188 if (cmd == SNDRV_PCM_TRIGGER_START) {
4189 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4190 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4191 hdsp_silence_playback(hdsp);
4194 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4195 hdsp_silence_playback(hdsp);
4198 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4199 hdsp_silence_playback(hdsp);
4202 snd_pcm_trigger_done(substream, substream);
4203 if (!hdsp->running && running)
4204 hdsp_start_audio(hdsp);
4205 else if (hdsp->running && !running)
4206 hdsp_stop_audio(hdsp);
4207 hdsp->running = running;
4208 spin_unlock(&hdsp->lock);
4213 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4215 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4218 if (hdsp_check_for_iobox (hdsp))
4221 if (hdsp_check_for_firmware(hdsp, 1))
4224 spin_lock_irq(&hdsp->lock);
4226 hdsp_reset_hw_pointer(hdsp);
4227 spin_unlock_irq(&hdsp->lock);
4231 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4233 .info = (SNDRV_PCM_INFO_MMAP |
4234 SNDRV_PCM_INFO_MMAP_VALID |
4235 SNDRV_PCM_INFO_NONINTERLEAVED |
4236 SNDRV_PCM_INFO_SYNC_START |
4237 SNDRV_PCM_INFO_DOUBLE),
4238 #ifdef SNDRV_BIG_ENDIAN
4239 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4241 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4243 .rates = (SNDRV_PCM_RATE_32000 |
4244 SNDRV_PCM_RATE_44100 |
4245 SNDRV_PCM_RATE_48000 |
4246 SNDRV_PCM_RATE_64000 |
4247 SNDRV_PCM_RATE_88200 |
4248 SNDRV_PCM_RATE_96000),
4252 .channels_max = HDSP_MAX_CHANNELS,
4253 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4254 .period_bytes_min = (64 * 4) * 10,
4255 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4261 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4263 .info = (SNDRV_PCM_INFO_MMAP |
4264 SNDRV_PCM_INFO_MMAP_VALID |
4265 SNDRV_PCM_INFO_NONINTERLEAVED |
4266 SNDRV_PCM_INFO_SYNC_START),
4267 #ifdef SNDRV_BIG_ENDIAN
4268 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4270 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4272 .rates = (SNDRV_PCM_RATE_32000 |
4273 SNDRV_PCM_RATE_44100 |
4274 SNDRV_PCM_RATE_48000 |
4275 SNDRV_PCM_RATE_64000 |
4276 SNDRV_PCM_RATE_88200 |
4277 SNDRV_PCM_RATE_96000),
4281 .channels_max = HDSP_MAX_CHANNELS,
4282 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4283 .period_bytes_min = (64 * 4) * 10,
4284 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4290 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4292 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4293 .count = ARRAY_SIZE(hdsp_period_sizes),
4294 .list = hdsp_period_sizes,
4298 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4300 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4301 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4302 .list = hdsp_9632_sample_rates,
4306 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4307 struct snd_pcm_hw_rule *rule)
4309 struct hdsp *hdsp = rule->private;
4310 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4311 if (hdsp->io_type == H9632) {
4312 unsigned int list[3];
4313 list[0] = hdsp->qs_in_channels;
4314 list[1] = hdsp->ds_in_channels;
4315 list[2] = hdsp->ss_in_channels;
4316 return snd_interval_list(c, 3, list, 0);
4318 unsigned int list[2];
4319 list[0] = hdsp->ds_in_channels;
4320 list[1] = hdsp->ss_in_channels;
4321 return snd_interval_list(c, 2, list, 0);
4325 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4326 struct snd_pcm_hw_rule *rule)
4328 unsigned int list[3];
4329 struct hdsp *hdsp = rule->private;
4330 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4331 if (hdsp->io_type == H9632) {
4332 list[0] = hdsp->qs_out_channels;
4333 list[1] = hdsp->ds_out_channels;
4334 list[2] = hdsp->ss_out_channels;
4335 return snd_interval_list(c, 3, list, 0);
4337 list[0] = hdsp->ds_out_channels;
4338 list[1] = hdsp->ss_out_channels;
4340 return snd_interval_list(c, 2, list, 0);
4343 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4344 struct snd_pcm_hw_rule *rule)
4346 struct hdsp *hdsp = rule->private;
4347 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4348 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4349 if (r->min > 96000 && hdsp->io_type == H9632) {
4350 struct snd_interval t = {
4351 .min = hdsp->qs_in_channels,
4352 .max = hdsp->qs_in_channels,
4355 return snd_interval_refine(c, &t);
4356 } else if (r->min > 48000 && r->max <= 96000) {
4357 struct snd_interval t = {
4358 .min = hdsp->ds_in_channels,
4359 .max = hdsp->ds_in_channels,
4362 return snd_interval_refine(c, &t);
4363 } else if (r->max < 64000) {
4364 struct snd_interval t = {
4365 .min = hdsp->ss_in_channels,
4366 .max = hdsp->ss_in_channels,
4369 return snd_interval_refine(c, &t);
4374 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4375 struct snd_pcm_hw_rule *rule)
4377 struct hdsp *hdsp = rule->private;
4378 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4379 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4380 if (r->min > 96000 && hdsp->io_type == H9632) {
4381 struct snd_interval t = {
4382 .min = hdsp->qs_out_channels,
4383 .max = hdsp->qs_out_channels,
4386 return snd_interval_refine(c, &t);
4387 } else if (r->min > 48000 && r->max <= 96000) {
4388 struct snd_interval t = {
4389 .min = hdsp->ds_out_channels,
4390 .max = hdsp->ds_out_channels,
4393 return snd_interval_refine(c, &t);
4394 } else if (r->max < 64000) {
4395 struct snd_interval t = {
4396 .min = hdsp->ss_out_channels,
4397 .max = hdsp->ss_out_channels,
4400 return snd_interval_refine(c, &t);
4405 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4406 struct snd_pcm_hw_rule *rule)
4408 struct hdsp *hdsp = rule->private;
4409 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4410 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4411 if (c->min >= hdsp->ss_out_channels) {
4412 struct snd_interval t = {
4417 return snd_interval_refine(r, &t);
4418 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4419 struct snd_interval t = {
4424 return snd_interval_refine(r, &t);
4425 } else if (c->max <= hdsp->ds_out_channels) {
4426 struct snd_interval t = {
4431 return snd_interval_refine(r, &t);
4436 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4437 struct snd_pcm_hw_rule *rule)
4439 struct hdsp *hdsp = rule->private;
4440 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4441 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4442 if (c->min >= hdsp->ss_in_channels) {
4443 struct snd_interval t = {
4448 return snd_interval_refine(r, &t);
4449 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4450 struct snd_interval t = {
4455 return snd_interval_refine(r, &t);
4456 } else if (c->max <= hdsp->ds_in_channels) {
4457 struct snd_interval t = {
4462 return snd_interval_refine(r, &t);
4467 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4469 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4470 struct snd_pcm_runtime *runtime = substream->runtime;
4472 if (hdsp_check_for_iobox (hdsp))
4475 if (hdsp_check_for_firmware(hdsp, 1))
4478 spin_lock_irq(&hdsp->lock);
4480 snd_pcm_set_sync(substream);
4482 runtime->hw = snd_hdsp_playback_subinfo;
4483 snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf);
4485 hdsp->playback_pid = current->pid;
4486 hdsp->playback_substream = substream;
4488 spin_unlock_irq(&hdsp->lock);
4490 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4491 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4492 if (hdsp->clock_source_locked) {
4493 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4494 } else if (hdsp->io_type == H9632) {
4495 runtime->hw.rate_max = 192000;
4496 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4497 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4499 if (hdsp->io_type == H9632) {
4500 runtime->hw.channels_min = hdsp->qs_out_channels;
4501 runtime->hw.channels_max = hdsp->ss_out_channels;
4504 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4505 snd_hdsp_hw_rule_out_channels, hdsp,
4506 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4507 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4508 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4509 SNDRV_PCM_HW_PARAM_RATE, -1);
4510 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4511 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4512 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4514 if (RPM != hdsp->io_type) {
4515 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4516 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4517 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4518 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4523 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4525 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4527 spin_lock_irq(&hdsp->lock);
4529 hdsp->playback_pid = -1;
4530 hdsp->playback_substream = NULL;
4532 spin_unlock_irq(&hdsp->lock);
4534 if (RPM != hdsp->io_type) {
4535 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4536 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4537 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4543 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4545 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4546 struct snd_pcm_runtime *runtime = substream->runtime;
4548 if (hdsp_check_for_iobox (hdsp))
4551 if (hdsp_check_for_firmware(hdsp, 1))
4554 spin_lock_irq(&hdsp->lock);
4556 snd_pcm_set_sync(substream);
4558 runtime->hw = snd_hdsp_capture_subinfo;
4559 snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf);
4561 hdsp->capture_pid = current->pid;
4562 hdsp->capture_substream = substream;
4564 spin_unlock_irq(&hdsp->lock);
4566 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4567 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4568 if (hdsp->io_type == H9632) {
4569 runtime->hw.channels_min = hdsp->qs_in_channels;
4570 runtime->hw.channels_max = hdsp->ss_in_channels;
4571 runtime->hw.rate_max = 192000;
4572 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4573 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4575 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4576 snd_hdsp_hw_rule_in_channels, hdsp,
4577 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4578 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4579 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4580 SNDRV_PCM_HW_PARAM_RATE, -1);
4581 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4582 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4583 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4587 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4589 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4591 spin_lock_irq(&hdsp->lock);
4593 hdsp->capture_pid = -1;
4594 hdsp->capture_substream = NULL;
4596 spin_unlock_irq(&hdsp->lock);
4600 /* helper functions for copying meter values */
4601 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4603 u32 val = readl(src);
4604 return copy_to_user(dest, &val, 4);
4607 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4609 u32 rms_low, rms_high;
4611 rms_low = readl(src_low);
4612 rms_high = readl(src_high);
4613 rms = ((u64)rms_high << 32) | rms_low;
4614 return copy_to_user(dest, &rms, 8);
4617 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4619 u32 rms_low, rms_high;
4621 rms_low = readl(src_low) & 0xffffff00;
4622 rms_high = readl(src_high) & 0xffffff00;
4623 rms = ((u64)rms_high << 32) | rms_low;
4624 return copy_to_user(dest, &rms, 8);
4627 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4629 int doublespeed = 0;
4630 int i, j, channels, ofs;
4632 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4634 channels = doublespeed ? 14 : 26;
4635 for (i = 0, j = 0; i < 26; ++i) {
4636 if (doublespeed && (i & 4))
4638 ofs = HDSP_9652_peakBase - j * 4;
4639 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4641 ofs -= channels * 4;
4642 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4644 ofs -= channels * 4;
4645 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4647 ofs = HDSP_9652_rmsBase + j * 8;
4648 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4649 hdsp->iobase + ofs + 4))
4651 ofs += channels * 8;
4652 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4653 hdsp->iobase + ofs + 4))
4655 ofs += channels * 8;
4656 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4657 hdsp->iobase + ofs + 4))
4664 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4667 struct hdsp_9632_meters __iomem *m;
4668 int doublespeed = 0;
4670 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4672 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4673 for (i = 0, j = 0; i < 16; ++i, ++j) {
4674 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4676 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4678 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4680 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4681 &m->input_rms_high[j]))
4683 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4684 &m->playback_rms_high[j]))
4686 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4687 &m->output_rms_high[j]))
4689 if (doublespeed && i == 3) i += 4;
4694 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4698 for (i = 0; i < 26; i++) {
4699 if (copy_u32_le(&peak_rms->playback_peaks[i],
4700 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4702 if (copy_u32_le(&peak_rms->input_peaks[i],
4703 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4706 for (i = 0; i < 28; i++) {
4707 if (copy_u32_le(&peak_rms->output_peaks[i],
4708 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4711 for (i = 0; i < 26; ++i) {
4712 if (copy_u64_le(&peak_rms->playback_rms[i],
4713 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4714 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4716 if (copy_u64_le(&peak_rms->input_rms[i],
4717 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4718 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4724 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4726 struct hdsp *hdsp = hw->private_data;
4727 void __user *argp = (void __user *)arg;
4731 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4732 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4734 err = hdsp_check_for_iobox(hdsp);
4738 err = hdsp_check_for_firmware(hdsp, 1);
4742 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4743 dev_err(hdsp->card->dev,
4744 "firmware needs to be uploaded to the card.\n");
4748 switch (hdsp->io_type) {
4750 return hdsp_9652_get_peak(hdsp, peak_rms);
4752 return hdsp_9632_get_peak(hdsp, peak_rms);
4754 return hdsp_get_peak(hdsp, peak_rms);
4757 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4758 struct hdsp_config_info info;
4759 unsigned long flags;
4762 err = hdsp_check_for_iobox(hdsp);
4766 err = hdsp_check_for_firmware(hdsp, 1);
4770 memset(&info, 0, sizeof(info));
4771 spin_lock_irqsave(&hdsp->lock, flags);
4772 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4773 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4774 if (hdsp->io_type != H9632)
4775 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4776 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4777 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4778 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4779 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4780 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4781 HDSP_SPDIFOpticalOut);
4782 info.spdif_professional = (unsigned char)
4783 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4784 info.spdif_emphasis = (unsigned char)
4785 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4786 info.spdif_nonaudio = (unsigned char)
4787 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4788 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4789 info.system_sample_rate = hdsp->system_sample_rate;
4790 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4791 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4792 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4793 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4794 info.line_out = (unsigned char)
4795 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4796 if (hdsp->io_type == H9632) {
4797 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4798 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4799 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4800 info.xlr_breakout_cable =
4801 (unsigned char)hdsp_toggle_setting(hdsp,
4802 HDSP_XLRBreakoutCable);
4804 } else if (hdsp->io_type == RPM) {
4805 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4806 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4808 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4809 info.analog_extension_board =
4810 (unsigned char)hdsp_toggle_setting(hdsp,
4811 HDSP_AnalogExtensionBoard);
4812 spin_unlock_irqrestore(&hdsp->lock, flags);
4813 if (copy_to_user(argp, &info, sizeof(info)))
4817 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4818 struct hdsp_9632_aeb h9632_aeb;
4820 if (hdsp->io_type != H9632) return -EINVAL;
4821 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4822 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4823 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4827 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4828 struct hdsp_version hdsp_version;
4831 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4832 if (hdsp->io_type == Undefined) {
4833 err = hdsp_get_iobox_version(hdsp);
4837 memset(&hdsp_version, 0, sizeof(hdsp_version));
4838 hdsp_version.io_type = hdsp->io_type;
4839 hdsp_version.firmware_rev = hdsp->firmware_rev;
4840 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))
4844 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4845 struct hdsp_firmware firmware;
4846 u32 __user *firmware_data;
4849 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4850 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4851 if (hdsp->io_type == Undefined) return -EINVAL;
4853 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4856 dev_info(hdsp->card->dev,
4857 "initializing firmware upload\n");
4858 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4860 firmware_data = (u32 __user *)firmware.firmware_data;
4862 if (hdsp_check_for_iobox (hdsp))
4865 if (!hdsp->fw_uploaded) {
4866 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4867 if (!hdsp->fw_uploaded)
4871 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4872 HDSP_FIRMWARE_SIZE)) {
4873 vfree(hdsp->fw_uploaded);
4874 hdsp->fw_uploaded = NULL;
4878 hdsp->state |= HDSP_FirmwareCached;
4880 err = snd_hdsp_load_firmware_from_cache(hdsp);
4884 if (!(hdsp->state & HDSP_InitializationComplete)) {
4885 err = snd_hdsp_enable_io(hdsp);
4889 snd_hdsp_initialize_channels(hdsp);
4890 snd_hdsp_initialize_midi_flush(hdsp);
4892 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
4894 dev_err(hdsp->card->dev,
4895 "error creating alsa devices\n");
4901 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4902 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4903 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4913 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4914 .open = snd_hdsp_playback_open,
4915 .close = snd_hdsp_playback_release,
4916 .ioctl = snd_hdsp_ioctl,
4917 .hw_params = snd_hdsp_hw_params,
4918 .prepare = snd_hdsp_prepare,
4919 .trigger = snd_hdsp_trigger,
4920 .pointer = snd_hdsp_hw_pointer,
4921 .copy = snd_hdsp_playback_copy,
4922 .fill_silence = snd_hdsp_hw_silence,
4925 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4926 .open = snd_hdsp_capture_open,
4927 .close = snd_hdsp_capture_release,
4928 .ioctl = snd_hdsp_ioctl,
4929 .hw_params = snd_hdsp_hw_params,
4930 .prepare = snd_hdsp_prepare,
4931 .trigger = snd_hdsp_trigger,
4932 .pointer = snd_hdsp_hw_pointer,
4933 .copy = snd_hdsp_capture_copy,
4936 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4938 struct snd_hwdep *hw;
4941 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);
4946 hw->private_data = hdsp;
4947 strcpy(hw->name, "HDSP hwdep interface");
4949 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4950 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4955 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4957 struct snd_pcm *pcm;
4960 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);
4965 pcm->private_data = hdsp;
4966 strcpy(pcm->name, hdsp->card_name);
4968 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4969 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4971 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4976 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4978 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4979 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4982 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4986 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4987 dev_err(hdsp->card->dev,
4988 "enable_io fifo_wait failed\n");
4992 for (i = 0; i < hdsp->max_channels; ++i) {
4993 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4994 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5000 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5002 int status, aebi_channels, aebo_channels, i;
5004 switch (hdsp->io_type) {
5006 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5007 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5008 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5012 hdsp->card_name = "RME Hammerfall HDSP 9652";
5013 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5014 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5018 status = hdsp_read(hdsp, HDSP_statusRegister);
5019 /* HDSP_AEBx bits are low when AEB are connected */
5020 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5021 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5022 hdsp->card_name = "RME Hammerfall HDSP 9632";
5023 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5024 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5025 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5026 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5027 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5028 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5029 /* Disable loopback of output channels, as the set function
5030 * only sets on a change we fake all bits (channels) as enabled.
5032 hdsp->io_loopback = 0xffffffff;
5033 for (i = 0; i < hdsp->max_channels; ++i)
5034 hdsp_loopback_set(hdsp, i, false);
5038 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5039 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5040 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5044 hdsp->card_name = "RME Hammerfall DSP + RPM";
5045 hdsp->ss_in_channels = RPM_CHANNELS-1;
5046 hdsp->ss_out_channels = RPM_CHANNELS;
5047 hdsp->ds_in_channels = RPM_CHANNELS-1;
5048 hdsp->ds_out_channels = RPM_CHANNELS;
5052 /* should never get here */
5057 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5059 snd_hdsp_flush_midi_input (hdsp, 0);
5060 snd_hdsp_flush_midi_input (hdsp, 1);
5063 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5067 err = snd_hdsp_create_pcm(card, hdsp);
5070 "Error creating pcm interface\n");
5075 err = snd_hdsp_create_midi(card, hdsp, 0);
5078 "Error creating first midi interface\n");
5082 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5083 err = snd_hdsp_create_midi(card, hdsp, 1);
5086 "Error creating second midi interface\n");
5091 err = snd_hdsp_create_controls(card, hdsp);
5094 "Error creating ctl interface\n");
5098 snd_hdsp_proc_init(hdsp);
5100 hdsp->system_sample_rate = -1;
5101 hdsp->playback_pid = -1;
5102 hdsp->capture_pid = -1;
5103 hdsp->capture_substream = NULL;
5104 hdsp->playback_substream = NULL;
5106 err = snd_hdsp_set_defaults(hdsp);
5109 "Error setting default values\n");
5113 if (!(hdsp->state & HDSP_InitializationComplete)) {
5114 strcpy(card->shortname, "Hammerfall DSP");
5115 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5116 hdsp->port, hdsp->irq);
5118 err = snd_card_register(card);
5121 "error registering card\n");
5124 hdsp->state |= HDSP_InitializationComplete;
5130 /* load firmware via hotplug fw loader */
5131 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5134 const struct firmware *fw;
5137 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5139 if (hdsp->io_type == Undefined) {
5140 err = hdsp_get_iobox_version(hdsp);
5143 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5147 /* caution: max length of firmware filename is 30! */
5148 switch (hdsp->io_type) {
5150 fwfile = "/*(DEBLOBBED)*/";
5153 if (hdsp->firmware_rev == 0xa)
5154 fwfile = "/*(DEBLOBBED)*/";
5156 fwfile = "/*(DEBLOBBED)*/";
5159 if (hdsp->firmware_rev == 0xa)
5160 fwfile = "/*(DEBLOBBED)*/";
5162 fwfile = "/*(DEBLOBBED)*/";
5165 dev_err(hdsp->card->dev,
5166 "invalid io_type %d\n", hdsp->io_type);
5170 if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5171 dev_err(hdsp->card->dev,
5172 "cannot load firmware %s\n", fwfile);
5175 if (fw->size < HDSP_FIRMWARE_SIZE) {
5176 dev_err(hdsp->card->dev,
5177 "too short firmware size %d (expected %d)\n",
5178 (int)fw->size, HDSP_FIRMWARE_SIZE);
5179 release_firmware(fw);
5183 hdsp->firmware = fw;
5185 hdsp->state |= HDSP_FirmwareCached;
5187 err = snd_hdsp_load_firmware_from_cache(hdsp);
5191 if (!(hdsp->state & HDSP_InitializationComplete)) {
5192 err = snd_hdsp_enable_io(hdsp);
5196 err = snd_hdsp_create_hwdep(hdsp->card, hdsp);
5198 dev_err(hdsp->card->dev,
5199 "error creating hwdep device\n");
5202 snd_hdsp_initialize_channels(hdsp);
5203 snd_hdsp_initialize_midi_flush(hdsp);
5204 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
5206 dev_err(hdsp->card->dev,
5207 "error creating alsa devices\n");
5214 static int snd_hdsp_create(struct snd_card *card,
5217 struct pci_dev *pci = hdsp->pci;
5224 hdsp->midi[0].rmidi = NULL;
5225 hdsp->midi[1].rmidi = NULL;
5226 hdsp->midi[0].input = NULL;
5227 hdsp->midi[1].input = NULL;
5228 hdsp->midi[0].output = NULL;
5229 hdsp->midi[1].output = NULL;
5230 hdsp->midi[0].pending = 0;
5231 hdsp->midi[1].pending = 0;
5232 spin_lock_init(&hdsp->midi[0].lock);
5233 spin_lock_init(&hdsp->midi[1].lock);
5234 hdsp->iobase = NULL;
5235 hdsp->control_register = 0;
5236 hdsp->control2_register = 0;
5237 hdsp->io_type = Undefined;
5238 hdsp->max_channels = 26;
5242 spin_lock_init(&hdsp->lock);
5244 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5246 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5247 hdsp->firmware_rev &= 0xff;
5249 /* From Martin Bjoernsen :
5250 "It is important that the card's latency timer register in
5251 the PCI configuration space is set to a value much larger
5252 than 0 by the computer's BIOS or the driver.
5253 The windows driver always sets this 8 bit register [...]
5254 to its maximum 255 to avoid problems with some computers."
5256 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5258 strcpy(card->driver, "H-DSP");
5259 strcpy(card->mixername, "Xilinx FPGA");
5261 if (hdsp->firmware_rev < 0xa)
5263 else if (hdsp->firmware_rev < 0x64)
5264 hdsp->card_name = "RME Hammerfall DSP";
5265 else if (hdsp->firmware_rev < 0x96) {
5266 hdsp->card_name = "RME HDSP 9652";
5269 hdsp->card_name = "RME HDSP 9632";
5270 hdsp->max_channels = 16;
5274 err = pcim_enable_device(pci);
5278 pci_set_master(hdsp->pci);
5280 err = pci_request_regions(pci, "hdsp");
5283 hdsp->port = pci_resource_start(pci, 0);
5284 hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);
5285 if (!hdsp->iobase) {
5286 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5287 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5291 if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,
5292 IRQF_SHARED, KBUILD_MODNAME, hdsp)) {
5293 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5297 hdsp->irq = pci->irq;
5298 card->sync_irq = hdsp->irq;
5299 hdsp->precise_ptr = 0;
5300 hdsp->use_midi_work = 1;
5301 hdsp->dds_value = 0;
5303 err = snd_hdsp_initialize_memory(hdsp);
5307 if (!is_9652 && !is_9632) {
5308 /* we wait a maximum of 10 seconds to let freshly
5309 * inserted cardbus cards do their hardware init */
5310 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5315 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5316 err = hdsp_request_fw_loader(hdsp);
5318 /* we don't fail as this can happen
5319 if userspace is not ready for
5322 dev_err(hdsp->card->dev,
5323 "couldn't get firmware from userspace. try using hdsploader\n");
5325 /* init is complete, we return */
5327 /* we defer initialization */
5328 dev_info(hdsp->card->dev,
5329 "card initialization pending : waiting for firmware\n");
5330 err = snd_hdsp_create_hwdep(card, hdsp);
5335 dev_info(hdsp->card->dev,
5336 "Firmware already present, initializing card.\n");
5337 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5338 hdsp->io_type = RPM;
5339 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5340 hdsp->io_type = Multiface;
5342 hdsp->io_type = Digiface;
5346 err = snd_hdsp_enable_io(hdsp);
5351 hdsp->io_type = H9652;
5354 hdsp->io_type = H9632;
5356 err = snd_hdsp_create_hwdep(card, hdsp);
5360 snd_hdsp_initialize_channels(hdsp);
5361 snd_hdsp_initialize_midi_flush(hdsp);
5363 hdsp->state |= HDSP_FirmwareLoaded;
5365 err = snd_hdsp_create_alsa_devices(card, hdsp);
5372 static void snd_hdsp_card_free(struct snd_card *card)
5374 struct hdsp *hdsp = card->private_data;
5377 /* stop the audio, and cancel all interrupts */
5378 cancel_work_sync(&hdsp->midi_work);
5379 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5380 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5383 release_firmware(hdsp->firmware);
5384 vfree(hdsp->fw_uploaded);
5387 static int snd_hdsp_probe(struct pci_dev *pci,
5388 const struct pci_device_id *pci_id)
5392 struct snd_card *card;
5395 if (dev >= SNDRV_CARDS)
5402 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5403 sizeof(struct hdsp), &card);
5407 hdsp = card->private_data;
5408 card->private_free = snd_hdsp_card_free;
5411 err = snd_hdsp_create(card, hdsp);
5415 strcpy(card->shortname, "Hammerfall DSP");
5416 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5417 hdsp->port, hdsp->irq);
5418 err = snd_card_register(card);
5421 pci_set_drvdata(pci, card);
5426 snd_card_free(card);
5430 static struct pci_driver hdsp_driver = {
5431 .name = KBUILD_MODNAME,
5432 .id_table = snd_hdsp_ids,
5433 .probe = snd_hdsp_probe,
5436 module_pci_driver(hdsp_driver);