2 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 * Copyright (c) 2002 Paul Davis
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
33 #include <linux/nospec.h>
35 #include <sound/core.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/info.h>
39 #include <sound/asoundef.h>
40 #include <sound/rawmidi.h>
41 #include <sound/hwdep.h>
42 #include <sound/initval.h>
43 #include <sound/hdsp.h>
45 #include <asm/byteorder.h>
46 #include <asm/current.h>
48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
52 module_param_array(index, int, NULL, 0444);
53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
54 module_param_array(id, charp, NULL, 0444);
55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
56 module_param_array(enable, bool, NULL, 0444);
57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
59 MODULE_DESCRIPTION("RME Hammerfall DSP");
60 MODULE_LICENSE("GPL");
61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
66 #define HDSP_MAX_CHANNELS 26
67 #define HDSP_MAX_DS_CHANNELS 14
68 #define HDSP_MAX_QS_CHANNELS 8
69 #define DIGIFACE_SS_CHANNELS 26
70 #define DIGIFACE_DS_CHANNELS 14
71 #define MULTIFACE_SS_CHANNELS 18
72 #define MULTIFACE_DS_CHANNELS 14
73 #define H9652_SS_CHANNELS 26
74 #define H9652_DS_CHANNELS 14
75 /* This does not include possible Analog Extension Boards
76 AEBs are detected at card initialization
78 #define H9632_SS_CHANNELS 12
79 #define H9632_DS_CHANNELS 8
80 #define H9632_QS_CHANNELS 4
81 #define RPM_CHANNELS 6
83 /* Write registers. These are defined as byte-offsets from the iobase value.
85 #define HDSP_resetPointer 0
86 #define HDSP_freqReg 0
87 #define HDSP_outputBufferAddress 32
88 #define HDSP_inputBufferAddress 36
89 #define HDSP_controlRegister 64
90 #define HDSP_interruptConfirmation 96
91 #define HDSP_outputEnable 128
92 #define HDSP_control2Reg 256
93 #define HDSP_midiDataOut0 352
94 #define HDSP_midiDataOut1 356
95 #define HDSP_fifoData 368
96 #define HDSP_inputEnable 384
98 /* Read registers. These are defined as byte-offsets from the iobase value
101 #define HDSP_statusRegister 0
102 #define HDSP_timecode 128
103 #define HDSP_status2Register 192
104 #define HDSP_midiDataIn0 360
105 #define HDSP_midiDataIn1 364
106 #define HDSP_midiStatusOut0 384
107 #define HDSP_midiStatusOut1 388
108 #define HDSP_midiStatusIn0 392
109 #define HDSP_midiStatusIn1 396
110 #define HDSP_fifoStatus 400
112 /* the meters are regular i/o-mapped registers, but offset
113 considerably from the rest. the peak registers are reset
114 when read; the least-significant 4 bits are full-scale counters;
115 the actual peak value is in the most-significant 24 bits.
118 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
119 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
120 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
121 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
122 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
125 /* This is for H9652 cards
126 Peak values are read downward from the base
127 Rms values are read upward
128 There are rms values for the outputs too
129 26*3 values are read in ss mode
130 14*3 in ds mode, with no gap between values
132 #define HDSP_9652_peakBase 7164
133 #define HDSP_9652_rmsBase 4096
135 /* c.f. the hdsp_9632_meters_t struct */
136 #define HDSP_9632_metersBase 4096
138 #define HDSP_IO_EXTENT 7168
140 /* control2 register bits */
142 #define HDSP_TMS 0x01
143 #define HDSP_TCK 0x02
144 #define HDSP_TDI 0x04
145 #define HDSP_JTAG 0x08
146 #define HDSP_PWDN 0x10
147 #define HDSP_PROGRAM 0x020
148 #define HDSP_CONFIG_MODE_0 0x040
149 #define HDSP_CONFIG_MODE_1 0x080
150 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
151 #define HDSP_BIGENDIAN_MODE 0x200
152 #define HDSP_RD_MULTIPLE 0x400
153 #define HDSP_9652_ENABLE_MIXER 0x800
154 #define HDSP_S200 0x800
155 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
156 #define HDSP_CYCLIC_MODE 0x1000
157 #define HDSP_TDO 0x10000000
159 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
160 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
162 /* Control Register bits */
164 #define HDSP_Start (1<<0) /* start engine */
165 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
166 #define HDSP_Latency1 (1<<2) /* [ see above ] */
167 #define HDSP_Latency2 (1<<3) /* [ see above ] */
168 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
169 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
170 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
171 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
172 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
173 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
174 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
175 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
176 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
177 #define HDSP_SyncRef2 (1<<13)
178 #define HDSP_SPDIFInputSelect0 (1<<14)
179 #define HDSP_SPDIFInputSelect1 (1<<15)
180 #define HDSP_SyncRef0 (1<<16)
181 #define HDSP_SyncRef1 (1<<17)
182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
183 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
184 #define HDSP_Midi0InterruptEnable (1<<22)
185 #define HDSP_Midi1InterruptEnable (1<<23)
186 #define HDSP_LineOut (1<<24)
187 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
188 #define HDSP_ADGain1 (1<<26)
189 #define HDSP_DAGain0 (1<<27)
190 #define HDSP_DAGain1 (1<<28)
191 #define HDSP_PhoneGain0 (1<<29)
192 #define HDSP_PhoneGain1 (1<<30)
193 #define HDSP_QuadSpeed (1<<31)
195 /* RPM uses some of the registers for special purposes */
196 #define HDSP_RPM_Inp12 0x04A00
197 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
198 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
199 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
200 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
201 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
203 #define HDSP_RPM_Inp34 0x32000
204 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
205 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
206 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
207 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
208 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
210 #define HDSP_RPM_Bypass 0x01000
212 #define HDSP_RPM_Disconnect 0x00001
214 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
215 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
216 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
217 #define HDSP_ADGainLowGain 0
219 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
220 #define HDSP_DAGainHighGain HDSP_DAGainMask
221 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
222 #define HDSP_DAGainMinus10dBV 0
224 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
225 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
226 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
227 #define HDSP_PhoneGainMinus12dB 0
229 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
230 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
232 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
233 #define HDSP_SPDIFInputADAT1 0
234 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
235 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
238 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
239 #define HDSP_SyncRef_ADAT1 0
240 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
241 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
242 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
243 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
244 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
246 /* Sample Clock Sources */
248 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
249 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
250 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
251 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
252 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
253 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
254 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
255 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
256 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
257 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
259 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
261 #define HDSP_SYNC_FROM_WORD 0
262 #define HDSP_SYNC_FROM_SPDIF 1
263 #define HDSP_SYNC_FROM_ADAT1 2
264 #define HDSP_SYNC_FROM_ADAT_SYNC 3
265 #define HDSP_SYNC_FROM_ADAT2 4
266 #define HDSP_SYNC_FROM_ADAT3 5
268 /* SyncCheck status */
270 #define HDSP_SYNC_CHECK_NO_LOCK 0
271 #define HDSP_SYNC_CHECK_LOCK 1
272 #define HDSP_SYNC_CHECK_SYNC 2
274 /* AutoSync references - used by "autosync_ref" control switch */
276 #define HDSP_AUTOSYNC_FROM_WORD 0
277 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
278 #define HDSP_AUTOSYNC_FROM_SPDIF 2
279 #define HDSP_AUTOSYNC_FROM_NONE 3
280 #define HDSP_AUTOSYNC_FROM_ADAT1 4
281 #define HDSP_AUTOSYNC_FROM_ADAT2 5
282 #define HDSP_AUTOSYNC_FROM_ADAT3 6
284 /* Possible sources of S/PDIF input */
286 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
287 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
288 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
289 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
291 #define HDSP_Frequency32KHz HDSP_Frequency0
292 #define HDSP_Frequency44_1KHz HDSP_Frequency1
293 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
294 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
295 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
296 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
297 /* For H9632 cards */
298 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
299 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
300 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
301 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
302 return 104857600000000 / rate; // 100 MHz
303 return 110100480000000 / rate; // 105 MHz
305 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
307 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
308 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
310 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
311 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
313 /* Status Register bits */
315 #define HDSP_audioIRQPending (1<<0)
316 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
317 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
318 #define HDSP_Lock1 (1<<2)
319 #define HDSP_Lock0 (1<<3)
320 #define HDSP_SPDIFSync (1<<4)
321 #define HDSP_TimecodeLock (1<<5)
322 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
323 #define HDSP_Sync2 (1<<16)
324 #define HDSP_Sync1 (1<<17)
325 #define HDSP_Sync0 (1<<18)
326 #define HDSP_DoubleSpeedStatus (1<<19)
327 #define HDSP_ConfigError (1<<20)
328 #define HDSP_DllError (1<<21)
329 #define HDSP_spdifFrequency0 (1<<22)
330 #define HDSP_spdifFrequency1 (1<<23)
331 #define HDSP_spdifFrequency2 (1<<24)
332 #define HDSP_SPDIFErrorFlag (1<<25)
333 #define HDSP_BufferID (1<<26)
334 #define HDSP_TimecodeSync (1<<27)
335 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
336 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
337 #define HDSP_midi0IRQPending (1<<30)
338 #define HDSP_midi1IRQPending (1<<31)
340 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
342 HDSP_spdifFrequency1|\
343 HDSP_spdifFrequency2|\
344 HDSP_spdifFrequency3)
346 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
347 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
348 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
350 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
351 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
352 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
354 /* This is for H9632 cards */
355 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
356 HDSP_spdifFrequency1|\
357 HDSP_spdifFrequency2)
358 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
359 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
361 /* Status2 Register bits */
363 #define HDSP_version0 (1<<0)
364 #define HDSP_version1 (1<<1)
365 #define HDSP_version2 (1<<2)
366 #define HDSP_wc_lock (1<<3)
367 #define HDSP_wc_sync (1<<4)
368 #define HDSP_inp_freq0 (1<<5)
369 #define HDSP_inp_freq1 (1<<6)
370 #define HDSP_inp_freq2 (1<<7)
371 #define HDSP_SelSyncRef0 (1<<8)
372 #define HDSP_SelSyncRef1 (1<<9)
373 #define HDSP_SelSyncRef2 (1<<10)
375 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
377 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
378 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
379 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
380 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
381 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
382 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
383 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
384 /* FIXME : more values for 9632 cards ? */
386 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
387 #define HDSP_SelSyncRef_ADAT1 0
388 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
389 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
390 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
391 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
392 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
394 /* Card state flags */
396 #define HDSP_InitializationComplete (1<<0)
397 #define HDSP_FirmwareLoaded (1<<1)
398 #define HDSP_FirmwareCached (1<<2)
400 /* FIFO wait times, defined in terms of 1/10ths of msecs */
402 #define HDSP_LONG_WAIT 5000
403 #define HDSP_SHORT_WAIT 30
405 #define UNITY_GAIN 32768
406 #define MINUS_INFINITY_GAIN 0
408 /* the size of a substream (1 mono data stream) */
410 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
411 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
413 /* the size of the area we need to allocate for DMA transfers. the
414 size is the same regardless of the number of channels - the
415 Multiface still uses the same memory area.
417 Note that we allocate 1 more channel than is apparently needed
418 because the h/w seems to write 1 byte beyond the end of the last
422 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
423 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
425 #define HDSP_FIRMWARE_SIZE (24413 * 4)
427 struct hdsp_9632_meters {
429 u32 playback_peak[16];
433 u32 input_rms_low[16];
434 u32 playback_rms_low[16];
435 u32 output_rms_low[16];
437 u32 input_rms_high[16];
438 u32 playback_rms_high[16];
439 u32 output_rms_high[16];
440 u32 xxx_rms_high[16];
446 struct snd_rawmidi *rmidi;
447 struct snd_rawmidi_substream *input;
448 struct snd_rawmidi_substream *output;
449 char istimer; /* timer in use */
450 struct timer_list timer;
457 struct snd_pcm_substream *capture_substream;
458 struct snd_pcm_substream *playback_substream;
459 struct hdsp_midi midi[2];
460 struct tasklet_struct midi_tasklet;
461 int use_midi_tasklet;
463 u32 control_register; /* cached value */
464 u32 control2_register; /* cached value */
466 u32 creg_spdif_stream;
467 int clock_source_locked;
468 char *card_name; /* digiface/multiface/rpm */
469 enum HDSP_IO_Type io_type; /* ditto, but for code use */
470 unsigned short firmware_rev;
471 unsigned short state; /* stores state bits */
472 const struct firmware *firmware;
474 size_t period_bytes; /* guess what this is */
475 unsigned char max_channels;
476 unsigned char qs_in_channels; /* quad speed mode for H9632 */
477 unsigned char ds_in_channels;
478 unsigned char ss_in_channels; /* different for multiface/digiface */
479 unsigned char qs_out_channels;
480 unsigned char ds_out_channels;
481 unsigned char ss_out_channels;
483 struct snd_dma_buffer capture_dma_buf;
484 struct snd_dma_buffer playback_dma_buf;
485 unsigned char *capture_buffer; /* suitably aligned address */
486 unsigned char *playback_buffer; /* suitably aligned address */
491 int system_sample_rate;
496 void __iomem *iobase;
497 struct snd_card *card;
499 struct snd_hwdep *hwdep;
501 struct snd_kcontrol *spdif_ctl;
502 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
503 unsigned int dds_value; /* last value written to freq register */
506 /* These tables map the ALSA channels 1..N to the channels that we
507 need to use in order to find the relevant channel buffer. RME
508 refer to this kind of mapping as between "the ADAT channel and
509 the DMA channel." We index it using the logical audio channel,
510 and the value is the DMA channel (i.e. channel buffer number)
511 where the data for that channel can be read/written from/to.
514 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
515 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
516 18, 19, 20, 21, 22, 23, 24, 25
519 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
521 0, 1, 2, 3, 4, 5, 6, 7,
523 16, 17, 18, 19, 20, 21, 22, 23,
526 -1, -1, -1, -1, -1, -1, -1, -1
529 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
530 /* ADAT channels are remapped */
531 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
532 /* channels 12 and 13 are S/PDIF */
534 /* others don't exist */
535 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
538 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
540 0, 1, 2, 3, 4, 5, 6, 7,
545 /* AO4S-192 and AI4S-192 extension boards */
547 /* others don't exist */
548 -1, -1, -1, -1, -1, -1, -1, -1,
552 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
559 /* AO4S-192 and AI4S-192 extension boards */
561 /* others don't exist */
562 -1, -1, -1, -1, -1, -1, -1, -1,
563 -1, -1, -1, -1, -1, -1
566 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
567 /* ADAT is disabled in this mode */
572 /* AO4S-192 and AI4S-192 extension boards */
574 /* others don't exist */
575 -1, -1, -1, -1, -1, -1, -1, -1,
576 -1, -1, -1, -1, -1, -1, -1, -1,
580 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
582 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
583 dmab->dev.dev = snd_dma_pci_data(pci);
584 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
590 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
593 snd_dma_free_pages(dmab);
597 static const struct pci_device_id snd_hdsp_ids[] = {
599 .vendor = PCI_VENDOR_ID_XILINX,
600 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
601 .subvendor = PCI_ANY_ID,
602 .subdevice = PCI_ANY_ID,
603 }, /* RME Hammerfall-DSP */
607 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
610 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
611 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
612 static int snd_hdsp_enable_io (struct hdsp *hdsp);
613 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
614 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
615 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
616 static int hdsp_autosync_ref(struct hdsp *hdsp);
617 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
618 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
620 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
622 switch (hdsp->io_type) {
627 if (hdsp->firmware_rev == 0xa)
628 return (64 * out) + (32 + (in));
630 return (52 * out) + (26 + (in));
632 return (32 * out) + (16 + (in));
634 return (52 * out) + (26 + (in));
638 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
640 switch (hdsp->io_type) {
645 if (hdsp->firmware_rev == 0xa)
646 return (64 * out) + in;
648 return (52 * out) + in;
650 return (32 * out) + in;
652 return (52 * out) + in;
656 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
658 writel(val, hdsp->iobase + reg);
661 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
663 return readl (hdsp->iobase + reg);
666 static int hdsp_check_for_iobox (struct hdsp *hdsp)
670 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
671 for (i = 0; i < 500; i++) {
672 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
675 dev_dbg(hdsp->card->dev,
676 "IO box found after %d ms\n",
683 dev_err(hdsp->card->dev, "no IO box connected!\n");
684 hdsp->state &= ~HDSP_FirmwareLoaded;
688 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
693 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
696 for (i = 0; i != loops; ++i) {
697 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
700 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
706 dev_info(hdsp->card->dev, "no IO box connected!\n");
707 hdsp->state &= ~HDSP_FirmwareLoaded;
711 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
717 if (hdsp->fw_uploaded)
718 cache = hdsp->fw_uploaded;
722 cache = (u32 *)hdsp->firmware->data;
727 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
729 dev_info(hdsp->card->dev, "loading firmware\n");
731 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
732 hdsp_write (hdsp, HDSP_fifoData, 0);
734 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
735 dev_info(hdsp->card->dev,
736 "timeout waiting for download preparation\n");
737 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
741 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
743 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
744 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
745 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
746 dev_info(hdsp->card->dev,
747 "timeout during firmware loading\n");
748 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
753 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
754 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
757 #ifdef SNDRV_BIG_ENDIAN
758 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
760 hdsp->control2_register = 0;
762 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
763 dev_info(hdsp->card->dev, "finished firmware loading\n");
766 if (hdsp->state & HDSP_InitializationComplete) {
767 dev_info(hdsp->card->dev,
768 "firmware loaded from cache, restoring defaults\n");
769 spin_lock_irqsave(&hdsp->lock, flags);
770 snd_hdsp_set_defaults(hdsp);
771 spin_unlock_irqrestore(&hdsp->lock, flags);
774 hdsp->state |= HDSP_FirmwareLoaded;
779 static int hdsp_get_iobox_version (struct hdsp *hdsp)
781 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
783 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
784 hdsp_write(hdsp, HDSP_fifoData, 0);
786 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
792 hdsp_write (hdsp, HDSP_fifoData, 0);
793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
797 hdsp_write(hdsp, HDSP_fifoData, 0);
798 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
799 hdsp->io_type = Digiface;
800 dev_info(hdsp->card->dev, "Digiface found\n");
804 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
805 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
806 hdsp_write(hdsp, HDSP_fifoData, 0);
807 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
810 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
811 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
812 hdsp_write(hdsp, HDSP_fifoData, 0);
813 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
817 dev_info(hdsp->card->dev, "RPM found\n");
820 /* firmware was already loaded, get iobox type */
821 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
823 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
824 hdsp->io_type = Multiface;
826 hdsp->io_type = Digiface;
831 hdsp->io_type = Multiface;
832 dev_info(hdsp->card->dev, "Multiface found\n");
837 static int hdsp_request_fw_loader(struct hdsp *hdsp);
839 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
841 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
843 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
844 hdsp->state &= ~HDSP_FirmwareLoaded;
845 if (! load_on_demand)
847 dev_err(hdsp->card->dev, "firmware not present.\n");
848 /* try to load firmware */
849 if (! (hdsp->state & HDSP_FirmwareCached)) {
850 if (! hdsp_request_fw_loader(hdsp))
852 dev_err(hdsp->card->dev,
853 "No firmware loaded nor cached, please upload firmware.\n");
856 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
857 dev_err(hdsp->card->dev,
858 "Firmware loading from cache failed, please upload manually.\n");
866 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
870 /* the fifoStatus registers reports on how many words
871 are available in the command FIFO.
874 for (i = 0; i < timeout; i++) {
876 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
879 /* not very friendly, but we only do this during a firmware
880 load and changing the mixer, so we just put up with it.
886 dev_warn(hdsp->card->dev,
887 "wait for FIFO status <= %d failed after %d iterations\n",
892 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
894 if (addr >= HDSP_MATRIX_MIXER_SIZE)
897 return hdsp->mixer_matrix[addr];
900 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
904 if (addr >= HDSP_MATRIX_MIXER_SIZE)
907 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
909 /* from martin bjornsen:
911 "You can only write dwords to the
912 mixer memory which contain two
913 mixer values in the low and high
914 word. So if you want to change
915 value 0 you have to read value 1
916 from the cache and write both to
917 the first dword in the mixer
921 if (hdsp->io_type == H9632 && addr >= 512)
924 if (hdsp->io_type == H9652 && addr >= 1352)
927 hdsp->mixer_matrix[addr] = data;
930 /* `addr' addresses a 16-bit wide address, but
931 the address space accessed via hdsp_write
932 uses byte offsets. put another way, addr
933 varies from 0 to 1351, but to access the
934 corresponding memory location, we need
935 to access 0 to 2703 ...
939 hdsp_write (hdsp, 4096 + (ad*4),
940 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
941 hdsp->mixer_matrix[addr&0x7fe]);
947 ad = (addr << 16) + data;
949 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
952 hdsp_write (hdsp, HDSP_fifoData, ad);
953 hdsp->mixer_matrix[addr] = data;
960 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
965 spin_lock_irqsave(&hdsp->lock, flags);
966 if ((hdsp->playback_pid != hdsp->capture_pid) &&
967 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
969 spin_unlock_irqrestore(&hdsp->lock, flags);
973 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
975 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
976 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
978 /* For the 9632, the mask is different */
979 if (hdsp->io_type == H9632)
980 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
982 if (status & HDSP_SPDIFErrorFlag)
986 case HDSP_spdifFrequency32KHz: return 32000;
987 case HDSP_spdifFrequency44_1KHz: return 44100;
988 case HDSP_spdifFrequency48KHz: return 48000;
989 case HDSP_spdifFrequency64KHz: return 64000;
990 case HDSP_spdifFrequency88_2KHz: return 88200;
991 case HDSP_spdifFrequency96KHz: return 96000;
992 case HDSP_spdifFrequency128KHz:
993 if (hdsp->io_type == H9632) return 128000;
995 case HDSP_spdifFrequency176_4KHz:
996 if (hdsp->io_type == H9632) return 176400;
998 case HDSP_spdifFrequency192KHz:
999 if (hdsp->io_type == H9632) return 192000;
1004 dev_warn(hdsp->card->dev,
1005 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1010 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1012 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1013 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1015 /* For the 9632 card, there seems to be no bit for indicating external
1016 * sample rate greater than 96kHz. The card reports the corresponding
1017 * single speed. So the best means seems to get spdif rate when
1018 * autosync reference is spdif */
1019 if (hdsp->io_type == H9632 &&
1020 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1021 return hdsp_spdif_sample_rate(hdsp);
1023 switch (rate_bits) {
1024 case HDSP_systemFrequency32: return 32000;
1025 case HDSP_systemFrequency44_1: return 44100;
1026 case HDSP_systemFrequency48: return 48000;
1027 case HDSP_systemFrequency64: return 64000;
1028 case HDSP_systemFrequency88_2: return 88200;
1029 case HDSP_systemFrequency96: return 96000;
1035 static void hdsp_compute_period_size(struct hdsp *hdsp)
1037 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1040 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1044 position = hdsp_read(hdsp, HDSP_statusRegister);
1046 if (!hdsp->precise_ptr)
1047 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1049 position &= HDSP_BufferPositionMask;
1051 position &= (hdsp->period_bytes/2) - 1;
1055 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1057 hdsp_write (hdsp, HDSP_resetPointer, 0);
1058 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1059 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1060 * requires (?) to write again DDS value after a reset pointer
1061 * (at least, it works like this) */
1062 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1065 static void hdsp_start_audio(struct hdsp *s)
1067 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1068 hdsp_write(s, HDSP_controlRegister, s->control_register);
1071 static void hdsp_stop_audio(struct hdsp *s)
1073 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1074 hdsp_write(s, HDSP_controlRegister, s->control_register);
1077 static void hdsp_silence_playback(struct hdsp *hdsp)
1079 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1082 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1086 spin_lock_irq(&s->lock);
1095 s->control_register &= ~HDSP_LatencyMask;
1096 s->control_register |= hdsp_encode_latency(n);
1098 hdsp_write(s, HDSP_controlRegister, s->control_register);
1100 hdsp_compute_period_size(s);
1102 spin_unlock_irq(&s->lock);
1107 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1113 else if (rate >= 56000)
1117 n = div_u64(n, rate);
1118 /* n should be less than 2^32 for being written to FREQ register */
1119 snd_BUG_ON(n >> 32);
1120 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1121 value to write it after a reset */
1122 hdsp->dds_value = n;
1123 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1126 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1128 int reject_if_open = 0;
1132 /* ASSUMPTION: hdsp->lock is either held, or
1133 there is no need for it (e.g. during module
1137 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1138 if (called_internally) {
1139 /* request from ctl or card initialization */
1140 dev_err(hdsp->card->dev,
1141 "device is not running as a clock master: cannot set sample rate.\n");
1144 /* hw_param request while in AutoSync mode */
1145 int external_freq = hdsp_external_sample_rate(hdsp);
1146 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1148 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1149 dev_info(hdsp->card->dev,
1150 "Detected ADAT in double speed mode\n");
1151 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1152 dev_info(hdsp->card->dev,
1153 "Detected ADAT in quad speed mode\n");
1154 else if (rate != external_freq) {
1155 dev_info(hdsp->card->dev,
1156 "No AutoSync source for requested rate\n");
1162 current_rate = hdsp->system_sample_rate;
1164 /* Changing from a "single speed" to a "double speed" rate is
1165 not allowed if any substreams are open. This is because
1166 such a change causes a shift in the location of
1167 the DMA buffers and a reduction in the number of available
1170 Note that a similar but essentially insoluble problem
1171 exists for externally-driven rate changes. All we can do
1172 is to flag rate changes in the read/write routines. */
1174 if (rate > 96000 && hdsp->io_type != H9632)
1179 if (current_rate > 48000)
1181 rate_bits = HDSP_Frequency32KHz;
1184 if (current_rate > 48000)
1186 rate_bits = HDSP_Frequency44_1KHz;
1189 if (current_rate > 48000)
1191 rate_bits = HDSP_Frequency48KHz;
1194 if (current_rate <= 48000 || current_rate > 96000)
1196 rate_bits = HDSP_Frequency64KHz;
1199 if (current_rate <= 48000 || current_rate > 96000)
1201 rate_bits = HDSP_Frequency88_2KHz;
1204 if (current_rate <= 48000 || current_rate > 96000)
1206 rate_bits = HDSP_Frequency96KHz;
1209 if (current_rate < 128000)
1211 rate_bits = HDSP_Frequency128KHz;
1214 if (current_rate < 128000)
1216 rate_bits = HDSP_Frequency176_4KHz;
1219 if (current_rate < 128000)
1221 rate_bits = HDSP_Frequency192KHz;
1227 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1228 dev_warn(hdsp->card->dev,
1229 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1231 hdsp->playback_pid);
1235 hdsp->control_register &= ~HDSP_FrequencyMask;
1236 hdsp->control_register |= rate_bits;
1237 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1239 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1240 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1241 hdsp_set_dds_value(hdsp, rate);
1243 if (rate >= 128000) {
1244 hdsp->channel_map = channel_map_H9632_qs;
1245 } else if (rate > 48000) {
1246 if (hdsp->io_type == H9632)
1247 hdsp->channel_map = channel_map_H9632_ds;
1249 hdsp->channel_map = channel_map_ds;
1251 switch (hdsp->io_type) {
1254 hdsp->channel_map = channel_map_mf_ss;
1258 hdsp->channel_map = channel_map_df_ss;
1261 hdsp->channel_map = channel_map_H9632_ss;
1264 /* should never happen */
1269 hdsp->system_sample_rate = rate;
1274 /*----------------------------------------------------------------------------
1276 ----------------------------------------------------------------------------*/
1278 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1280 /* the hardware already does the relevant bit-mask with 0xff */
1282 return hdsp_read(hdsp, HDSP_midiDataIn1);
1284 return hdsp_read(hdsp, HDSP_midiDataIn0);
1287 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1289 /* the hardware already does the relevant bit-mask with 0xff */
1291 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1293 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1296 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1299 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1301 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1304 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1306 int fifo_bytes_used;
1309 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1311 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1313 if (fifo_bytes_used < 128)
1314 return 128 - fifo_bytes_used;
1319 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1321 while (snd_hdsp_midi_input_available (hdsp, id))
1322 snd_hdsp_midi_read_byte (hdsp, id);
1325 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1327 unsigned long flags;
1331 unsigned char buf[128];
1333 /* Output is not interrupt driven */
1335 spin_lock_irqsave (&hmidi->lock, flags);
1336 if (hmidi->output) {
1337 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1338 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1339 if (n_pending > (int)sizeof (buf))
1340 n_pending = sizeof (buf);
1342 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1343 for (i = 0; i < to_write; ++i)
1344 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1349 spin_unlock_irqrestore (&hmidi->lock, flags);
1353 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1355 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1356 unsigned long flags;
1360 spin_lock_irqsave (&hmidi->lock, flags);
1361 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1363 if (n_pending > (int)sizeof (buf))
1364 n_pending = sizeof (buf);
1365 for (i = 0; i < n_pending; ++i)
1366 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1368 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1370 /* flush the MIDI input FIFO */
1372 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1377 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1379 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1380 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1381 spin_unlock_irqrestore (&hmidi->lock, flags);
1382 return snd_hdsp_midi_output_write (hmidi);
1385 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1388 struct hdsp_midi *hmidi;
1389 unsigned long flags;
1392 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1394 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1395 spin_lock_irqsave (&hdsp->lock, flags);
1397 if (!(hdsp->control_register & ie)) {
1398 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1399 hdsp->control_register |= ie;
1402 hdsp->control_register &= ~ie;
1403 tasklet_kill(&hdsp->midi_tasklet);
1406 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1407 spin_unlock_irqrestore (&hdsp->lock, flags);
1410 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1412 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1413 unsigned long flags;
1415 snd_hdsp_midi_output_write(hmidi);
1416 spin_lock_irqsave (&hmidi->lock, flags);
1418 /* this does not bump hmidi->istimer, because the
1419 kernel automatically removed the timer when it
1420 expired, and we are now adding it back, thus
1421 leaving istimer wherever it was set before.
1425 mod_timer(&hmidi->timer, 1 + jiffies);
1427 spin_unlock_irqrestore (&hmidi->lock, flags);
1430 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1432 struct hdsp_midi *hmidi;
1433 unsigned long flags;
1435 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1436 spin_lock_irqsave (&hmidi->lock, flags);
1438 if (!hmidi->istimer) {
1439 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1441 mod_timer(&hmidi->timer, 1 + jiffies);
1445 if (hmidi->istimer && --hmidi->istimer <= 0)
1446 del_timer (&hmidi->timer);
1448 spin_unlock_irqrestore (&hmidi->lock, flags);
1450 snd_hdsp_midi_output_write(hmidi);
1453 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1455 struct hdsp_midi *hmidi;
1457 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1458 spin_lock_irq (&hmidi->lock);
1459 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1460 hmidi->input = substream;
1461 spin_unlock_irq (&hmidi->lock);
1466 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1468 struct hdsp_midi *hmidi;
1470 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1471 spin_lock_irq (&hmidi->lock);
1472 hmidi->output = substream;
1473 spin_unlock_irq (&hmidi->lock);
1478 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1480 struct hdsp_midi *hmidi;
1482 snd_hdsp_midi_input_trigger (substream, 0);
1484 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1485 spin_lock_irq (&hmidi->lock);
1486 hmidi->input = NULL;
1487 spin_unlock_irq (&hmidi->lock);
1492 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1494 struct hdsp_midi *hmidi;
1496 snd_hdsp_midi_output_trigger (substream, 0);
1498 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1499 spin_lock_irq (&hmidi->lock);
1500 hmidi->output = NULL;
1501 spin_unlock_irq (&hmidi->lock);
1506 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1508 .open = snd_hdsp_midi_output_open,
1509 .close = snd_hdsp_midi_output_close,
1510 .trigger = snd_hdsp_midi_output_trigger,
1513 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1515 .open = snd_hdsp_midi_input_open,
1516 .close = snd_hdsp_midi_input_close,
1517 .trigger = snd_hdsp_midi_input_trigger,
1520 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1524 hdsp->midi[id].id = id;
1525 hdsp->midi[id].rmidi = NULL;
1526 hdsp->midi[id].input = NULL;
1527 hdsp->midi[id].output = NULL;
1528 hdsp->midi[id].hdsp = hdsp;
1529 hdsp->midi[id].istimer = 0;
1530 hdsp->midi[id].pending = 0;
1531 spin_lock_init (&hdsp->midi[id].lock);
1533 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1534 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1537 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1538 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1540 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1541 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1543 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1544 SNDRV_RAWMIDI_INFO_INPUT |
1545 SNDRV_RAWMIDI_INFO_DUPLEX;
1550 /*-----------------------------------------------------------------------------
1552 ----------------------------------------------------------------------------*/
1554 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1557 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1558 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1559 if (val & HDSP_SPDIFProfessional)
1560 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1562 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1566 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1568 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1569 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1570 if (val & HDSP_SPDIFProfessional)
1571 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1573 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1576 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1578 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1583 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1585 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1587 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1591 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1593 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1598 spin_lock_irq(&hdsp->lock);
1599 change = val != hdsp->creg_spdif;
1600 hdsp->creg_spdif = val;
1601 spin_unlock_irq(&hdsp->lock);
1605 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1607 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1612 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1614 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1616 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1620 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1622 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1626 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1627 spin_lock_irq(&hdsp->lock);
1628 change = val != hdsp->creg_spdif_stream;
1629 hdsp->creg_spdif_stream = val;
1630 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1631 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1632 spin_unlock_irq(&hdsp->lock);
1636 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1638 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1643 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1645 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1649 #define HDSP_SPDIF_IN(xname, xindex) \
1650 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1653 .info = snd_hdsp_info_spdif_in, \
1654 .get = snd_hdsp_get_spdif_in, \
1655 .put = snd_hdsp_put_spdif_in }
1657 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1659 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1662 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1664 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1665 hdsp->control_register |= hdsp_encode_spdif_in(in);
1666 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1670 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1672 static const char * const texts[4] = {
1673 "Optical", "Coaxial", "Internal", "AES"
1675 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1677 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1681 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1683 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1685 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1689 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1691 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1695 if (!snd_hdsp_use_is_exclusive(hdsp))
1697 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1698 spin_lock_irq(&hdsp->lock);
1699 change = val != hdsp_spdif_in(hdsp);
1701 hdsp_set_spdif_input(hdsp, val);
1702 spin_unlock_irq(&hdsp->lock);
1706 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1707 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1709 .private_value = xindex, \
1710 .info = snd_hdsp_info_toggle_setting, \
1711 .get = snd_hdsp_get_toggle_setting, \
1712 .put = snd_hdsp_put_toggle_setting \
1715 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1717 return (hdsp->control_register & regmask) ? 1 : 0;
1720 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1723 hdsp->control_register |= regmask;
1725 hdsp->control_register &= ~regmask;
1726 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1731 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1733 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1734 struct snd_ctl_elem_value *ucontrol)
1736 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1737 u32 regmask = kcontrol->private_value;
1739 spin_lock_irq(&hdsp->lock);
1740 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1741 spin_unlock_irq(&hdsp->lock);
1745 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1746 struct snd_ctl_elem_value *ucontrol)
1748 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1749 u32 regmask = kcontrol->private_value;
1753 if (!snd_hdsp_use_is_exclusive(hdsp))
1755 val = ucontrol->value.integer.value[0] & 1;
1756 spin_lock_irq(&hdsp->lock);
1757 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1759 hdsp_set_toggle_setting(hdsp, regmask, val);
1760 spin_unlock_irq(&hdsp->lock);
1764 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1765 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1768 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1769 .info = snd_hdsp_info_spdif_sample_rate, \
1770 .get = snd_hdsp_get_spdif_sample_rate \
1773 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1775 static const char * const texts[] = {
1776 "32000", "44100", "48000", "64000", "88200", "96000",
1777 "None", "128000", "176400", "192000"
1779 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1781 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1785 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1787 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1789 switch (hdsp_spdif_sample_rate(hdsp)) {
1791 ucontrol->value.enumerated.item[0] = 0;
1794 ucontrol->value.enumerated.item[0] = 1;
1797 ucontrol->value.enumerated.item[0] = 2;
1800 ucontrol->value.enumerated.item[0] = 3;
1803 ucontrol->value.enumerated.item[0] = 4;
1806 ucontrol->value.enumerated.item[0] = 5;
1809 ucontrol->value.enumerated.item[0] = 7;
1812 ucontrol->value.enumerated.item[0] = 8;
1815 ucontrol->value.enumerated.item[0] = 9;
1818 ucontrol->value.enumerated.item[0] = 6;
1823 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1824 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1827 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1828 .info = snd_hdsp_info_system_sample_rate, \
1829 .get = snd_hdsp_get_system_sample_rate \
1832 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1834 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1839 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1841 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1843 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1847 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1848 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1851 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1852 .info = snd_hdsp_info_autosync_sample_rate, \
1853 .get = snd_hdsp_get_autosync_sample_rate \
1856 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1858 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1859 static const char * const texts[] = {
1860 "32000", "44100", "48000", "64000", "88200", "96000",
1861 "None", "128000", "176400", "192000"
1864 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1868 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1870 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1872 switch (hdsp_external_sample_rate(hdsp)) {
1874 ucontrol->value.enumerated.item[0] = 0;
1877 ucontrol->value.enumerated.item[0] = 1;
1880 ucontrol->value.enumerated.item[0] = 2;
1883 ucontrol->value.enumerated.item[0] = 3;
1886 ucontrol->value.enumerated.item[0] = 4;
1889 ucontrol->value.enumerated.item[0] = 5;
1892 ucontrol->value.enumerated.item[0] = 7;
1895 ucontrol->value.enumerated.item[0] = 8;
1898 ucontrol->value.enumerated.item[0] = 9;
1901 ucontrol->value.enumerated.item[0] = 6;
1906 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1907 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1910 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1911 .info = snd_hdsp_info_system_clock_mode, \
1912 .get = snd_hdsp_get_system_clock_mode \
1915 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1917 if (hdsp->control_register & HDSP_ClockModeMaster)
1919 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1924 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1926 static const char * const texts[] = {"Master", "Slave" };
1928 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1931 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1933 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1935 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1939 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1940 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1943 .info = snd_hdsp_info_clock_source, \
1944 .get = snd_hdsp_get_clock_source, \
1945 .put = snd_hdsp_put_clock_source \
1948 static int hdsp_clock_source(struct hdsp *hdsp)
1950 if (hdsp->control_register & HDSP_ClockModeMaster) {
1951 switch (hdsp->system_sample_rate) {
1978 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1982 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1983 if (hdsp_external_sample_rate(hdsp) != 0) {
1984 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1985 hdsp->control_register &= ~HDSP_ClockModeMaster;
1986 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1991 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1994 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1997 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2000 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2003 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2006 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2009 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2012 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2015 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2021 hdsp->control_register |= HDSP_ClockModeMaster;
2022 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2023 hdsp_set_rate(hdsp, rate, 1);
2027 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2029 static const char * const texts[] = {
2030 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2031 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2032 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2033 "Internal 192.0 KHz"
2035 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2037 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2041 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2043 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2045 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2049 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2051 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2055 if (!snd_hdsp_use_is_exclusive(hdsp))
2057 val = ucontrol->value.enumerated.item[0];
2058 if (val < 0) val = 0;
2059 if (hdsp->io_type == H9632) {
2066 spin_lock_irq(&hdsp->lock);
2067 if (val != hdsp_clock_source(hdsp))
2068 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2071 spin_unlock_irq(&hdsp->lock);
2075 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2077 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2079 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2081 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2085 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2087 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2090 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2092 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2096 #define HDSP_DA_GAIN(xname, xindex) \
2097 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2100 .info = snd_hdsp_info_da_gain, \
2101 .get = snd_hdsp_get_da_gain, \
2102 .put = snd_hdsp_put_da_gain \
2105 static int hdsp_da_gain(struct hdsp *hdsp)
2107 switch (hdsp->control_register & HDSP_DAGainMask) {
2108 case HDSP_DAGainHighGain:
2110 case HDSP_DAGainPlus4dBu:
2112 case HDSP_DAGainMinus10dBV:
2119 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2121 hdsp->control_register &= ~HDSP_DAGainMask;
2124 hdsp->control_register |= HDSP_DAGainHighGain;
2127 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2130 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2136 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2140 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2142 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2144 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2147 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2149 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2151 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2155 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2157 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2161 if (!snd_hdsp_use_is_exclusive(hdsp))
2163 val = ucontrol->value.enumerated.item[0];
2164 if (val < 0) val = 0;
2165 if (val > 2) val = 2;
2166 spin_lock_irq(&hdsp->lock);
2167 if (val != hdsp_da_gain(hdsp))
2168 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2171 spin_unlock_irq(&hdsp->lock);
2175 #define HDSP_AD_GAIN(xname, xindex) \
2176 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2179 .info = snd_hdsp_info_ad_gain, \
2180 .get = snd_hdsp_get_ad_gain, \
2181 .put = snd_hdsp_put_ad_gain \
2184 static int hdsp_ad_gain(struct hdsp *hdsp)
2186 switch (hdsp->control_register & HDSP_ADGainMask) {
2187 case HDSP_ADGainMinus10dBV:
2189 case HDSP_ADGainPlus4dBu:
2191 case HDSP_ADGainLowGain:
2198 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2200 hdsp->control_register &= ~HDSP_ADGainMask;
2203 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2206 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2209 hdsp->control_register |= HDSP_ADGainLowGain;
2215 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2219 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2221 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2223 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2226 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2228 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2230 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2234 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2236 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2240 if (!snd_hdsp_use_is_exclusive(hdsp))
2242 val = ucontrol->value.enumerated.item[0];
2243 if (val < 0) val = 0;
2244 if (val > 2) val = 2;
2245 spin_lock_irq(&hdsp->lock);
2246 if (val != hdsp_ad_gain(hdsp))
2247 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2250 spin_unlock_irq(&hdsp->lock);
2254 #define HDSP_PHONE_GAIN(xname, xindex) \
2255 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2258 .info = snd_hdsp_info_phone_gain, \
2259 .get = snd_hdsp_get_phone_gain, \
2260 .put = snd_hdsp_put_phone_gain \
2263 static int hdsp_phone_gain(struct hdsp *hdsp)
2265 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2266 case HDSP_PhoneGain0dB:
2268 case HDSP_PhoneGainMinus6dB:
2270 case HDSP_PhoneGainMinus12dB:
2277 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2279 hdsp->control_register &= ~HDSP_PhoneGainMask;
2282 hdsp->control_register |= HDSP_PhoneGain0dB;
2285 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2288 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2294 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2298 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2300 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2302 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2305 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2307 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2309 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2313 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2315 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2319 if (!snd_hdsp_use_is_exclusive(hdsp))
2321 val = ucontrol->value.enumerated.item[0];
2322 if (val < 0) val = 0;
2323 if (val > 2) val = 2;
2324 spin_lock_irq(&hdsp->lock);
2325 if (val != hdsp_phone_gain(hdsp))
2326 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2329 spin_unlock_irq(&hdsp->lock);
2333 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2334 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2337 .info = snd_hdsp_info_pref_sync_ref, \
2338 .get = snd_hdsp_get_pref_sync_ref, \
2339 .put = snd_hdsp_put_pref_sync_ref \
2342 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2344 /* Notice that this looks at the requested sync source,
2345 not the one actually in use.
2348 switch (hdsp->control_register & HDSP_SyncRefMask) {
2349 case HDSP_SyncRef_ADAT1:
2350 return HDSP_SYNC_FROM_ADAT1;
2351 case HDSP_SyncRef_ADAT2:
2352 return HDSP_SYNC_FROM_ADAT2;
2353 case HDSP_SyncRef_ADAT3:
2354 return HDSP_SYNC_FROM_ADAT3;
2355 case HDSP_SyncRef_SPDIF:
2356 return HDSP_SYNC_FROM_SPDIF;
2357 case HDSP_SyncRef_WORD:
2358 return HDSP_SYNC_FROM_WORD;
2359 case HDSP_SyncRef_ADAT_SYNC:
2360 return HDSP_SYNC_FROM_ADAT_SYNC;
2362 return HDSP_SYNC_FROM_WORD;
2367 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2369 hdsp->control_register &= ~HDSP_SyncRefMask;
2371 case HDSP_SYNC_FROM_ADAT1:
2372 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2374 case HDSP_SYNC_FROM_ADAT2:
2375 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2377 case HDSP_SYNC_FROM_ADAT3:
2378 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2380 case HDSP_SYNC_FROM_SPDIF:
2381 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2383 case HDSP_SYNC_FROM_WORD:
2384 hdsp->control_register |= HDSP_SyncRef_WORD;
2386 case HDSP_SYNC_FROM_ADAT_SYNC:
2387 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2392 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2396 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2398 static const char * const texts[] = {
2399 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2401 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2404 switch (hdsp->io_type) {
2419 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2422 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2424 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2426 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2430 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2432 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2436 if (!snd_hdsp_use_is_exclusive(hdsp))
2439 switch (hdsp->io_type) {
2454 val = ucontrol->value.enumerated.item[0] % max;
2455 spin_lock_irq(&hdsp->lock);
2456 change = (int)val != hdsp_pref_sync_ref(hdsp);
2457 hdsp_set_pref_sync_ref(hdsp, val);
2458 spin_unlock_irq(&hdsp->lock);
2462 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2463 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2466 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2467 .info = snd_hdsp_info_autosync_ref, \
2468 .get = snd_hdsp_get_autosync_ref, \
2471 static int hdsp_autosync_ref(struct hdsp *hdsp)
2473 /* This looks at the autosync selected sync reference */
2474 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2476 switch (status2 & HDSP_SelSyncRefMask) {
2477 case HDSP_SelSyncRef_WORD:
2478 return HDSP_AUTOSYNC_FROM_WORD;
2479 case HDSP_SelSyncRef_ADAT_SYNC:
2480 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2481 case HDSP_SelSyncRef_SPDIF:
2482 return HDSP_AUTOSYNC_FROM_SPDIF;
2483 case HDSP_SelSyncRefMask:
2484 return HDSP_AUTOSYNC_FROM_NONE;
2485 case HDSP_SelSyncRef_ADAT1:
2486 return HDSP_AUTOSYNC_FROM_ADAT1;
2487 case HDSP_SelSyncRef_ADAT2:
2488 return HDSP_AUTOSYNC_FROM_ADAT2;
2489 case HDSP_SelSyncRef_ADAT3:
2490 return HDSP_AUTOSYNC_FROM_ADAT3;
2492 return HDSP_AUTOSYNC_FROM_WORD;
2497 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2499 static const char * const texts[] = {
2500 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2503 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2506 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2508 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2510 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2514 #define HDSP_PRECISE_POINTER(xname, xindex) \
2515 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2518 .info = snd_hdsp_info_precise_pointer, \
2519 .get = snd_hdsp_get_precise_pointer, \
2520 .put = snd_hdsp_put_precise_pointer \
2523 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2526 hdsp->precise_ptr = 1;
2528 hdsp->precise_ptr = 0;
2532 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2534 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2536 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2538 spin_lock_irq(&hdsp->lock);
2539 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2540 spin_unlock_irq(&hdsp->lock);
2544 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2546 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2550 if (!snd_hdsp_use_is_exclusive(hdsp))
2552 val = ucontrol->value.integer.value[0] & 1;
2553 spin_lock_irq(&hdsp->lock);
2554 change = (int)val != hdsp->precise_ptr;
2555 hdsp_set_precise_pointer(hdsp, val);
2556 spin_unlock_irq(&hdsp->lock);
2560 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2561 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2564 .info = snd_hdsp_info_use_midi_tasklet, \
2565 .get = snd_hdsp_get_use_midi_tasklet, \
2566 .put = snd_hdsp_put_use_midi_tasklet \
2569 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2572 hdsp->use_midi_tasklet = 1;
2574 hdsp->use_midi_tasklet = 0;
2578 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2580 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2582 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2584 spin_lock_irq(&hdsp->lock);
2585 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2586 spin_unlock_irq(&hdsp->lock);
2590 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2592 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2596 if (!snd_hdsp_use_is_exclusive(hdsp))
2598 val = ucontrol->value.integer.value[0] & 1;
2599 spin_lock_irq(&hdsp->lock);
2600 change = (int)val != hdsp->use_midi_tasklet;
2601 hdsp_set_use_midi_tasklet(hdsp, val);
2602 spin_unlock_irq(&hdsp->lock);
2606 #define HDSP_MIXER(xname, xindex) \
2607 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2611 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2612 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2613 .info = snd_hdsp_info_mixer, \
2614 .get = snd_hdsp_get_mixer, \
2615 .put = snd_hdsp_put_mixer \
2618 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2620 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2622 uinfo->value.integer.min = 0;
2623 uinfo->value.integer.max = 65536;
2624 uinfo->value.integer.step = 1;
2628 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2630 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2635 source = ucontrol->value.integer.value[0];
2636 destination = ucontrol->value.integer.value[1];
2638 if (source >= hdsp->max_channels)
2639 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2641 addr = hdsp_input_to_output_key(hdsp,source, destination);
2643 spin_lock_irq(&hdsp->lock);
2644 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2645 spin_unlock_irq(&hdsp->lock);
2649 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2651 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2658 if (!snd_hdsp_use_is_exclusive(hdsp))
2661 source = ucontrol->value.integer.value[0];
2662 destination = ucontrol->value.integer.value[1];
2664 if (source >= hdsp->max_channels)
2665 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2667 addr = hdsp_input_to_output_key(hdsp,source, destination);
2669 gain = ucontrol->value.integer.value[2];
2671 spin_lock_irq(&hdsp->lock);
2672 change = gain != hdsp_read_gain(hdsp, addr);
2674 hdsp_write_gain(hdsp, addr, gain);
2675 spin_unlock_irq(&hdsp->lock);
2679 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2680 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2683 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2684 .info = snd_hdsp_info_sync_check, \
2685 .get = snd_hdsp_get_wc_sync_check \
2688 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2690 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2692 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2695 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2697 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2698 if (status2 & HDSP_wc_lock) {
2699 if (status2 & HDSP_wc_sync)
2708 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2710 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2712 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2716 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2717 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2720 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2721 .info = snd_hdsp_info_sync_check, \
2722 .get = snd_hdsp_get_spdif_sync_check \
2725 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2727 int status = hdsp_read(hdsp, HDSP_statusRegister);
2728 if (status & HDSP_SPDIFErrorFlag)
2731 if (status & HDSP_SPDIFSync)
2739 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2741 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2743 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2747 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2748 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2751 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2752 .info = snd_hdsp_info_sync_check, \
2753 .get = snd_hdsp_get_adatsync_sync_check \
2756 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2758 int status = hdsp_read(hdsp, HDSP_statusRegister);
2759 if (status & HDSP_TimecodeLock) {
2760 if (status & HDSP_TimecodeSync)
2768 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2770 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2772 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2776 #define HDSP_ADAT_SYNC_CHECK \
2777 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2778 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2779 .info = snd_hdsp_info_sync_check, \
2780 .get = snd_hdsp_get_adat_sync_check \
2783 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2785 int status = hdsp_read(hdsp, HDSP_statusRegister);
2787 if (status & (HDSP_Lock0>>idx)) {
2788 if (status & (HDSP_Sync0>>idx))
2796 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2799 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2801 offset = ucontrol->id.index - 1;
2802 if (snd_BUG_ON(offset < 0))
2805 switch (hdsp->io_type) {
2820 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2824 #define HDSP_DDS_OFFSET(xname, xindex) \
2825 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2828 .info = snd_hdsp_info_dds_offset, \
2829 .get = snd_hdsp_get_dds_offset, \
2830 .put = snd_hdsp_put_dds_offset \
2833 static int hdsp_dds_offset(struct hdsp *hdsp)
2836 unsigned int dds_value = hdsp->dds_value;
2837 int system_sample_rate = hdsp->system_sample_rate;
2844 * dds_value = n / rate
2845 * rate = n / dds_value
2847 n = div_u64(n, dds_value);
2848 if (system_sample_rate >= 112000)
2850 else if (system_sample_rate >= 56000)
2852 return ((int)n) - system_sample_rate;
2855 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2857 int rate = hdsp->system_sample_rate + offset_hz;
2858 hdsp_set_dds_value(hdsp, rate);
2862 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2864 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2866 uinfo->value.integer.min = -5000;
2867 uinfo->value.integer.max = 5000;
2871 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2873 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2875 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2879 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2881 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2885 if (!snd_hdsp_use_is_exclusive(hdsp))
2887 val = ucontrol->value.integer.value[0];
2888 spin_lock_irq(&hdsp->lock);
2889 if (val != hdsp_dds_offset(hdsp))
2890 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2893 spin_unlock_irq(&hdsp->lock);
2897 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2898 HDSP_DA_GAIN("DA Gain", 0),
2899 HDSP_AD_GAIN("AD Gain", 0),
2900 HDSP_PHONE_GAIN("Phones Gain", 0),
2901 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2902 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2905 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2907 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2908 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2909 .info = snd_hdsp_control_spdif_info,
2910 .get = snd_hdsp_control_spdif_get,
2911 .put = snd_hdsp_control_spdif_put,
2914 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2915 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2916 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2917 .info = snd_hdsp_control_spdif_stream_info,
2918 .get = snd_hdsp_control_spdif_stream_get,
2919 .put = snd_hdsp_control_spdif_stream_put,
2922 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2923 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2924 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2925 .info = snd_hdsp_control_spdif_mask_info,
2926 .get = snd_hdsp_control_spdif_mask_get,
2927 .private_value = IEC958_AES0_NONAUDIO |
2928 IEC958_AES0_PROFESSIONAL |
2929 IEC958_AES0_CON_EMPHASIS,
2932 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2933 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2934 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2935 .info = snd_hdsp_control_spdif_mask_info,
2936 .get = snd_hdsp_control_spdif_mask_get,
2937 .private_value = IEC958_AES0_NONAUDIO |
2938 IEC958_AES0_PROFESSIONAL |
2939 IEC958_AES0_PRO_EMPHASIS,
2941 HDSP_MIXER("Mixer", 0),
2942 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2943 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2944 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2945 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2946 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2947 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2948 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2950 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2951 .name = "Sample Clock Source Locking",
2952 .info = snd_hdsp_info_clock_source_lock,
2953 .get = snd_hdsp_get_clock_source_lock,
2954 .put = snd_hdsp_put_clock_source_lock,
2956 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2957 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2958 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2959 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2960 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2961 /* 'External Rate' complies with the alsa control naming scheme */
2962 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2963 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2964 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2965 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2966 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2967 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2968 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2972 static int hdsp_rpm_input12(struct hdsp *hdsp)
2974 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2975 case HDSP_RPM_Inp12_Phon_6dB:
2977 case HDSP_RPM_Inp12_Phon_n6dB:
2979 case HDSP_RPM_Inp12_Line_0dB:
2981 case HDSP_RPM_Inp12_Line_n6dB:
2988 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2990 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2992 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2997 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2999 hdsp->control_register &= ~HDSP_RPM_Inp12;
3002 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3007 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3010 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3013 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3019 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3024 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3026 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3030 if (!snd_hdsp_use_is_exclusive(hdsp))
3032 val = ucontrol->value.enumerated.item[0];
3037 spin_lock_irq(&hdsp->lock);
3038 if (val != hdsp_rpm_input12(hdsp))
3039 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3042 spin_unlock_irq(&hdsp->lock);
3047 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3049 static const char * const texts[] = {
3050 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3053 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3057 static int hdsp_rpm_input34(struct hdsp *hdsp)
3059 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3060 case HDSP_RPM_Inp34_Phon_6dB:
3062 case HDSP_RPM_Inp34_Phon_n6dB:
3064 case HDSP_RPM_Inp34_Line_0dB:
3066 case HDSP_RPM_Inp34_Line_n6dB:
3073 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3075 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3077 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3082 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3084 hdsp->control_register &= ~HDSP_RPM_Inp34;
3087 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3092 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3095 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3098 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3104 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3109 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3111 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3115 if (!snd_hdsp_use_is_exclusive(hdsp))
3117 val = ucontrol->value.enumerated.item[0];
3122 spin_lock_irq(&hdsp->lock);
3123 if (val != hdsp_rpm_input34(hdsp))
3124 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3127 spin_unlock_irq(&hdsp->lock);
3132 /* RPM Bypass switch */
3133 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3135 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3139 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3141 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3143 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3148 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3151 hdsp->control_register |= HDSP_RPM_Bypass;
3153 hdsp->control_register &= ~HDSP_RPM_Bypass;
3154 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3159 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3161 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3165 if (!snd_hdsp_use_is_exclusive(hdsp))
3167 val = ucontrol->value.integer.value[0] & 1;
3168 spin_lock_irq(&hdsp->lock);
3169 change = (int)val != hdsp_rpm_bypass(hdsp);
3170 hdsp_set_rpm_bypass(hdsp, val);
3171 spin_unlock_irq(&hdsp->lock);
3176 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3178 static const char * const texts[] = {"On", "Off"};
3180 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3184 /* RPM Disconnect switch */
3185 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3187 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3191 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3193 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3195 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3200 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3203 hdsp->control_register |= HDSP_RPM_Disconnect;
3205 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3206 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3211 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3213 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3217 if (!snd_hdsp_use_is_exclusive(hdsp))
3219 val = ucontrol->value.integer.value[0] & 1;
3220 spin_lock_irq(&hdsp->lock);
3221 change = (int)val != hdsp_rpm_disconnect(hdsp);
3222 hdsp_set_rpm_disconnect(hdsp, val);
3223 spin_unlock_irq(&hdsp->lock);
3227 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3229 static const char * const texts[] = {"On", "Off"};
3231 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3234 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3236 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3237 .name = "RPM Bypass",
3238 .get = snd_hdsp_get_rpm_bypass,
3239 .put = snd_hdsp_put_rpm_bypass,
3240 .info = snd_hdsp_info_rpm_bypass
3243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3244 .name = "RPM Disconnect",
3245 .get = snd_hdsp_get_rpm_disconnect,
3246 .put = snd_hdsp_put_rpm_disconnect,
3247 .info = snd_hdsp_info_rpm_disconnect
3250 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3251 .name = "Input 1/2",
3252 .get = snd_hdsp_get_rpm_input12,
3253 .put = snd_hdsp_put_rpm_input12,
3254 .info = snd_hdsp_info_rpm_input
3257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3258 .name = "Input 3/4",
3259 .get = snd_hdsp_get_rpm_input34,
3260 .put = snd_hdsp_put_rpm_input34,
3261 .info = snd_hdsp_info_rpm_input
3263 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3264 HDSP_MIXER("Mixer", 0)
3267 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3268 HDSP_TOGGLE_SETTING("Analog Extension Board",
3269 HDSP_AnalogExtensionBoard);
3270 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3272 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3276 struct snd_kcontrol *kctl;
3278 if (hdsp->io_type == RPM) {
3279 /* RPM Bypass, Disconnect and Input switches */
3280 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3281 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3288 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3289 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3291 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3292 hdsp->spdif_ctl = kctl;
3295 /* ADAT SyncCheck status */
3296 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3297 snd_hdsp_adat_sync_check.index = 1;
3298 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3300 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3301 for (idx = 1; idx < 3; ++idx) {
3302 snd_hdsp_adat_sync_check.index = idx+1;
3303 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3308 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3309 if (hdsp->io_type == H9632) {
3310 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3311 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3316 /* AEB control for H96xx card */
3317 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3318 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3325 /*------------------------------------------------------------
3327 ------------------------------------------------------------*/
3330 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3332 struct hdsp *hdsp = entry->private_data;
3333 unsigned int status;
3334 unsigned int status2;
3335 char *pref_sync_ref;
3337 char *system_clock_mode;
3341 status = hdsp_read(hdsp, HDSP_statusRegister);
3342 status2 = hdsp_read(hdsp, HDSP_status2Register);
3344 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3345 hdsp->card->number + 1);
3346 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3347 hdsp->capture_buffer, hdsp->playback_buffer);
3348 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3349 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3350 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3351 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3352 hdsp->control2_register);
3353 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3354 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3356 if (hdsp_check_for_iobox(hdsp)) {
3357 snd_iprintf(buffer, "No I/O box connected.\n"
3358 "Please connect one and upload firmware.\n");
3362 if (hdsp_check_for_firmware(hdsp, 0)) {
3363 if (hdsp->state & HDSP_FirmwareCached) {
3364 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3365 snd_iprintf(buffer, "Firmware loading from "
3367 "please upload manually.\n");
3372 err = hdsp_request_fw_loader(hdsp);
3375 "No firmware loaded nor cached, "
3376 "please upload firmware.\n");
3382 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3383 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3384 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3385 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3386 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3387 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3389 snd_iprintf(buffer, "\n");
3391 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3393 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3394 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3395 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3396 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3398 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3400 snd_iprintf(buffer, "\n");
3402 switch (hdsp_clock_source(hdsp)) {
3403 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3404 clock_source = "AutoSync";
3406 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3407 clock_source = "Internal 32 kHz";
3409 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3410 clock_source = "Internal 44.1 kHz";
3412 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3413 clock_source = "Internal 48 kHz";
3415 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3416 clock_source = "Internal 64 kHz";
3418 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3419 clock_source = "Internal 88.2 kHz";
3421 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3422 clock_source = "Internal 96 kHz";
3424 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3425 clock_source = "Internal 128 kHz";
3427 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3428 clock_source = "Internal 176.4 kHz";
3430 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3431 clock_source = "Internal 192 kHz";
3434 clock_source = "Error";
3436 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3438 if (hdsp_system_clock_mode(hdsp))
3439 system_clock_mode = "Slave";
3441 system_clock_mode = "Master";
3443 switch (hdsp_pref_sync_ref (hdsp)) {
3444 case HDSP_SYNC_FROM_WORD:
3445 pref_sync_ref = "Word Clock";
3447 case HDSP_SYNC_FROM_ADAT_SYNC:
3448 pref_sync_ref = "ADAT Sync";
3450 case HDSP_SYNC_FROM_SPDIF:
3451 pref_sync_ref = "SPDIF";
3453 case HDSP_SYNC_FROM_ADAT1:
3454 pref_sync_ref = "ADAT1";
3456 case HDSP_SYNC_FROM_ADAT2:
3457 pref_sync_ref = "ADAT2";
3459 case HDSP_SYNC_FROM_ADAT3:
3460 pref_sync_ref = "ADAT3";
3463 pref_sync_ref = "Word Clock";
3466 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3468 switch (hdsp_autosync_ref (hdsp)) {
3469 case HDSP_AUTOSYNC_FROM_WORD:
3470 autosync_ref = "Word Clock";
3472 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3473 autosync_ref = "ADAT Sync";
3475 case HDSP_AUTOSYNC_FROM_SPDIF:
3476 autosync_ref = "SPDIF";
3478 case HDSP_AUTOSYNC_FROM_NONE:
3479 autosync_ref = "None";
3481 case HDSP_AUTOSYNC_FROM_ADAT1:
3482 autosync_ref = "ADAT1";
3484 case HDSP_AUTOSYNC_FROM_ADAT2:
3485 autosync_ref = "ADAT2";
3487 case HDSP_AUTOSYNC_FROM_ADAT3:
3488 autosync_ref = "ADAT3";
3491 autosync_ref = "---";
3494 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3496 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3498 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3500 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3501 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3503 snd_iprintf(buffer, "\n");
3505 if (hdsp->io_type != RPM) {
3506 switch (hdsp_spdif_in(hdsp)) {
3507 case HDSP_SPDIFIN_OPTICAL:
3508 snd_iprintf(buffer, "IEC958 input: Optical\n");
3510 case HDSP_SPDIFIN_COAXIAL:
3511 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3513 case HDSP_SPDIFIN_INTERNAL:
3514 snd_iprintf(buffer, "IEC958 input: Internal\n");
3516 case HDSP_SPDIFIN_AES:
3517 snd_iprintf(buffer, "IEC958 input: AES\n");
3520 snd_iprintf(buffer, "IEC958 input: ???\n");
3525 if (RPM == hdsp->io_type) {
3526 if (hdsp->control_register & HDSP_RPM_Bypass)
3527 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3529 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3530 if (hdsp->control_register & HDSP_RPM_Disconnect)
3531 snd_iprintf(buffer, "RPM disconnected\n");
3533 snd_iprintf(buffer, "RPM connected\n");
3535 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3536 case HDSP_RPM_Inp12_Phon_6dB:
3537 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3539 case HDSP_RPM_Inp12_Phon_0dB:
3540 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3542 case HDSP_RPM_Inp12_Phon_n6dB:
3543 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3545 case HDSP_RPM_Inp12_Line_0dB:
3546 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3548 case HDSP_RPM_Inp12_Line_n6dB:
3549 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3552 snd_iprintf(buffer, "Input 1/2: ???\n");
3555 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3556 case HDSP_RPM_Inp34_Phon_6dB:
3557 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3559 case HDSP_RPM_Inp34_Phon_0dB:
3560 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3562 case HDSP_RPM_Inp34_Phon_n6dB:
3563 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3565 case HDSP_RPM_Inp34_Line_0dB:
3566 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3568 case HDSP_RPM_Inp34_Line_n6dB:
3569 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3572 snd_iprintf(buffer, "Input 3/4: ???\n");
3576 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3577 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3579 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3581 if (hdsp->control_register & HDSP_SPDIFProfessional)
3582 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3584 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3586 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3587 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3589 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3591 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3592 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3594 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3595 x = hdsp_spdif_sample_rate(hdsp);
3597 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3599 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3601 snd_iprintf(buffer, "\n");
3604 x = status & HDSP_Sync0;
3605 if (status & HDSP_Lock0)
3606 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3608 snd_iprintf(buffer, "ADAT1: No Lock\n");
3610 switch (hdsp->io_type) {
3613 x = status & HDSP_Sync1;
3614 if (status & HDSP_Lock1)
3615 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3617 snd_iprintf(buffer, "ADAT2: No Lock\n");
3618 x = status & HDSP_Sync2;
3619 if (status & HDSP_Lock2)
3620 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3622 snd_iprintf(buffer, "ADAT3: No Lock\n");
3629 x = status & HDSP_SPDIFSync;
3630 if (status & HDSP_SPDIFErrorFlag)
3631 snd_iprintf (buffer, "SPDIF: No Lock\n");
3633 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3635 x = status2 & HDSP_wc_sync;
3636 if (status2 & HDSP_wc_lock)
3637 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3639 snd_iprintf (buffer, "Word Clock: No Lock\n");
3641 x = status & HDSP_TimecodeSync;
3642 if (status & HDSP_TimecodeLock)
3643 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3645 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3647 snd_iprintf(buffer, "\n");
3649 /* Informations about H9632 specific controls */
3650 if (hdsp->io_type == H9632) {
3653 switch (hdsp_ad_gain(hdsp)) {
3664 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3666 switch (hdsp_da_gain(hdsp)) {
3677 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3679 switch (hdsp_phone_gain(hdsp)) {
3690 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3692 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3693 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3696 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3697 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3699 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3700 snd_iprintf(buffer, "\n");
3705 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3707 struct snd_info_entry *entry;
3709 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3710 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3713 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3715 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3716 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3719 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3721 unsigned long pb_bus, cb_bus;
3723 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3724 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3725 if (hdsp->capture_dma_buf.area)
3726 snd_dma_free_pages(&hdsp->capture_dma_buf);
3727 dev_err(hdsp->card->dev,
3728 "%s: no buffers available\n", hdsp->card_name);
3732 /* Align to bus-space 64K boundary */
3734 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3735 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3737 /* Tell the card where it is */
3739 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3740 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3742 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3743 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3748 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3752 /* ASSUMPTION: hdsp->lock is either held, or
3753 there is no need to hold it (e.g. during module
3759 SPDIF Input via Coax
3761 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3762 which implies 2 4096 sample, 32Kbyte periods).
3766 hdsp->control_register = HDSP_ClockModeMaster |
3767 HDSP_SPDIFInputCoaxial |
3768 hdsp_encode_latency(7) |
3772 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3774 #ifdef SNDRV_BIG_ENDIAN
3775 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3777 hdsp->control2_register = 0;
3779 if (hdsp->io_type == H9652)
3780 snd_hdsp_9652_enable_mixer (hdsp);
3782 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3784 hdsp_reset_hw_pointer(hdsp);
3785 hdsp_compute_period_size(hdsp);
3787 /* silence everything */
3789 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3790 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3792 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3793 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3797 /* H9632 specific defaults */
3798 if (hdsp->io_type == H9632) {
3799 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3800 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3803 /* set a default rate so that the channel map is set up.
3806 hdsp_set_rate(hdsp, 48000, 1);
3811 static void hdsp_midi_tasklet(unsigned long arg)
3813 struct hdsp *hdsp = (struct hdsp *)arg;
3815 if (hdsp->midi[0].pending)
3816 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3817 if (hdsp->midi[1].pending)
3818 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3821 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3823 struct hdsp *hdsp = (struct hdsp *) dev_id;
3824 unsigned int status;
3828 unsigned int midi0status;
3829 unsigned int midi1status;
3832 status = hdsp_read(hdsp, HDSP_statusRegister);
3834 audio = status & HDSP_audioIRQPending;
3835 midi0 = status & HDSP_midi0IRQPending;
3836 midi1 = status & HDSP_midi1IRQPending;
3838 if (!audio && !midi0 && !midi1)
3841 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3843 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3844 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3846 if (!(hdsp->state & HDSP_InitializationComplete))
3850 if (hdsp->capture_substream)
3851 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3853 if (hdsp->playback_substream)
3854 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3857 if (midi0 && midi0status) {
3858 if (hdsp->use_midi_tasklet) {
3859 /* we disable interrupts for this input until processing is done */
3860 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3861 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3862 hdsp->midi[0].pending = 1;
3865 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3868 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3869 if (hdsp->use_midi_tasklet) {
3870 /* we disable interrupts for this input until processing is done */
3871 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3872 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3873 hdsp->midi[1].pending = 1;
3876 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3879 if (hdsp->use_midi_tasklet && schedule)
3880 tasklet_schedule(&hdsp->midi_tasklet);
3884 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3886 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3887 return hdsp_hw_pointer(hdsp);
3890 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3897 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3900 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3903 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3904 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3906 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3909 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3910 int channel, unsigned long pos,
3911 void __user *src, unsigned long count)
3913 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3916 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3919 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3920 if (snd_BUG_ON(!channel_buf))
3922 if (copy_from_user(channel_buf + pos, src, count))
3927 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3928 int channel, unsigned long pos,
3929 void *src, unsigned long count)
3931 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3934 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3935 if (snd_BUG_ON(!channel_buf))
3937 memcpy(channel_buf + pos, src, count);
3941 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3942 int channel, unsigned long pos,
3943 void __user *dst, unsigned long count)
3945 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3948 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3951 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3952 if (snd_BUG_ON(!channel_buf))
3954 if (copy_to_user(dst, channel_buf + pos, count))
3959 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3960 int channel, unsigned long pos,
3961 void *dst, unsigned long count)
3963 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3966 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3967 if (snd_BUG_ON(!channel_buf))
3969 memcpy(dst, channel_buf + pos, count);
3973 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3974 int channel, unsigned long pos,
3975 unsigned long count)
3977 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3980 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3981 if (snd_BUG_ON(!channel_buf))
3983 memset(channel_buf + pos, 0, count);
3987 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3989 struct snd_pcm_runtime *runtime = substream->runtime;
3990 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3991 struct snd_pcm_substream *other;
3992 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3993 other = hdsp->capture_substream;
3995 other = hdsp->playback_substream;
3997 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3999 runtime->status->hw_ptr = 0;
4001 struct snd_pcm_substream *s;
4002 struct snd_pcm_runtime *oruntime = other->runtime;
4003 snd_pcm_group_for_each_entry(s, substream) {
4005 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4013 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4014 struct snd_pcm_hw_params *params)
4016 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4021 if (hdsp_check_for_iobox (hdsp))
4024 if (hdsp_check_for_firmware(hdsp, 1))
4027 spin_lock_irq(&hdsp->lock);
4029 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4030 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4031 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4032 this_pid = hdsp->playback_pid;
4033 other_pid = hdsp->capture_pid;
4035 this_pid = hdsp->capture_pid;
4036 other_pid = hdsp->playback_pid;
4039 if ((other_pid > 0) && (this_pid != other_pid)) {
4041 /* The other stream is open, and not by the same
4042 task as this one. Make sure that the parameters
4043 that matter are the same.
4046 if (params_rate(params) != hdsp->system_sample_rate) {
4047 spin_unlock_irq(&hdsp->lock);
4048 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4052 if (params_period_size(params) != hdsp->period_bytes / 4) {
4053 spin_unlock_irq(&hdsp->lock);
4054 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4060 spin_unlock_irq(&hdsp->lock);
4064 spin_unlock_irq(&hdsp->lock);
4067 /* how to make sure that the rate matches an externally-set one ?
4070 spin_lock_irq(&hdsp->lock);
4071 if (! hdsp->clock_source_locked) {
4072 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4073 spin_unlock_irq(&hdsp->lock);
4074 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4078 spin_unlock_irq(&hdsp->lock);
4080 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4081 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4088 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4089 struct snd_pcm_channel_info *info)
4091 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4092 unsigned int channel = info->channel;
4094 if (snd_BUG_ON(channel >= hdsp->max_channels))
4096 channel = array_index_nospec(channel, hdsp->max_channels);
4098 if (hdsp->channel_map[channel] < 0)
4101 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4107 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4108 unsigned int cmd, void *arg)
4111 case SNDRV_PCM_IOCTL1_RESET:
4112 return snd_hdsp_reset(substream);
4113 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4114 return snd_hdsp_channel_info(substream, arg);
4119 return snd_pcm_lib_ioctl(substream, cmd, arg);
4122 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4124 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4125 struct snd_pcm_substream *other;
4128 if (hdsp_check_for_iobox (hdsp))
4131 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4134 spin_lock(&hdsp->lock);
4135 running = hdsp->running;
4137 case SNDRV_PCM_TRIGGER_START:
4138 running |= 1 << substream->stream;
4140 case SNDRV_PCM_TRIGGER_STOP:
4141 running &= ~(1 << substream->stream);
4145 spin_unlock(&hdsp->lock);
4148 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4149 other = hdsp->capture_substream;
4151 other = hdsp->playback_substream;
4154 struct snd_pcm_substream *s;
4155 snd_pcm_group_for_each_entry(s, substream) {
4157 snd_pcm_trigger_done(s, substream);
4158 if (cmd == SNDRV_PCM_TRIGGER_START)
4159 running |= 1 << s->stream;
4161 running &= ~(1 << s->stream);
4165 if (cmd == SNDRV_PCM_TRIGGER_START) {
4166 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4167 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4168 hdsp_silence_playback(hdsp);
4171 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4172 hdsp_silence_playback(hdsp);
4175 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4176 hdsp_silence_playback(hdsp);
4179 snd_pcm_trigger_done(substream, substream);
4180 if (!hdsp->running && running)
4181 hdsp_start_audio(hdsp);
4182 else if (hdsp->running && !running)
4183 hdsp_stop_audio(hdsp);
4184 hdsp->running = running;
4185 spin_unlock(&hdsp->lock);
4190 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4192 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4195 if (hdsp_check_for_iobox (hdsp))
4198 if (hdsp_check_for_firmware(hdsp, 1))
4201 spin_lock_irq(&hdsp->lock);
4203 hdsp_reset_hw_pointer(hdsp);
4204 spin_unlock_irq(&hdsp->lock);
4208 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4210 .info = (SNDRV_PCM_INFO_MMAP |
4211 SNDRV_PCM_INFO_MMAP_VALID |
4212 SNDRV_PCM_INFO_NONINTERLEAVED |
4213 SNDRV_PCM_INFO_SYNC_START |
4214 SNDRV_PCM_INFO_DOUBLE),
4215 #ifdef SNDRV_BIG_ENDIAN
4216 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4218 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4220 .rates = (SNDRV_PCM_RATE_32000 |
4221 SNDRV_PCM_RATE_44100 |
4222 SNDRV_PCM_RATE_48000 |
4223 SNDRV_PCM_RATE_64000 |
4224 SNDRV_PCM_RATE_88200 |
4225 SNDRV_PCM_RATE_96000),
4229 .channels_max = HDSP_MAX_CHANNELS,
4230 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4231 .period_bytes_min = (64 * 4) * 10,
4232 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4238 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4240 .info = (SNDRV_PCM_INFO_MMAP |
4241 SNDRV_PCM_INFO_MMAP_VALID |
4242 SNDRV_PCM_INFO_NONINTERLEAVED |
4243 SNDRV_PCM_INFO_SYNC_START),
4244 #ifdef SNDRV_BIG_ENDIAN
4245 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4247 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4249 .rates = (SNDRV_PCM_RATE_32000 |
4250 SNDRV_PCM_RATE_44100 |
4251 SNDRV_PCM_RATE_48000 |
4252 SNDRV_PCM_RATE_64000 |
4253 SNDRV_PCM_RATE_88200 |
4254 SNDRV_PCM_RATE_96000),
4258 .channels_max = HDSP_MAX_CHANNELS,
4259 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4260 .period_bytes_min = (64 * 4) * 10,
4261 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4267 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4269 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4270 .count = ARRAY_SIZE(hdsp_period_sizes),
4271 .list = hdsp_period_sizes,
4275 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4277 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4278 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4279 .list = hdsp_9632_sample_rates,
4283 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4284 struct snd_pcm_hw_rule *rule)
4286 struct hdsp *hdsp = rule->private;
4287 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4288 if (hdsp->io_type == H9632) {
4289 unsigned int list[3];
4290 list[0] = hdsp->qs_in_channels;
4291 list[1] = hdsp->ds_in_channels;
4292 list[2] = hdsp->ss_in_channels;
4293 return snd_interval_list(c, 3, list, 0);
4295 unsigned int list[2];
4296 list[0] = hdsp->ds_in_channels;
4297 list[1] = hdsp->ss_in_channels;
4298 return snd_interval_list(c, 2, list, 0);
4302 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4303 struct snd_pcm_hw_rule *rule)
4305 unsigned int list[3];
4306 struct hdsp *hdsp = rule->private;
4307 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308 if (hdsp->io_type == H9632) {
4309 list[0] = hdsp->qs_out_channels;
4310 list[1] = hdsp->ds_out_channels;
4311 list[2] = hdsp->ss_out_channels;
4312 return snd_interval_list(c, 3, list, 0);
4314 list[0] = hdsp->ds_out_channels;
4315 list[1] = hdsp->ss_out_channels;
4317 return snd_interval_list(c, 2, list, 0);
4320 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4321 struct snd_pcm_hw_rule *rule)
4323 struct hdsp *hdsp = rule->private;
4324 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4325 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4326 if (r->min > 96000 && hdsp->io_type == H9632) {
4327 struct snd_interval t = {
4328 .min = hdsp->qs_in_channels,
4329 .max = hdsp->qs_in_channels,
4332 return snd_interval_refine(c, &t);
4333 } else if (r->min > 48000 && r->max <= 96000) {
4334 struct snd_interval t = {
4335 .min = hdsp->ds_in_channels,
4336 .max = hdsp->ds_in_channels,
4339 return snd_interval_refine(c, &t);
4340 } else if (r->max < 64000) {
4341 struct snd_interval t = {
4342 .min = hdsp->ss_in_channels,
4343 .max = hdsp->ss_in_channels,
4346 return snd_interval_refine(c, &t);
4351 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4352 struct snd_pcm_hw_rule *rule)
4354 struct hdsp *hdsp = rule->private;
4355 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4356 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4357 if (r->min > 96000 && hdsp->io_type == H9632) {
4358 struct snd_interval t = {
4359 .min = hdsp->qs_out_channels,
4360 .max = hdsp->qs_out_channels,
4363 return snd_interval_refine(c, &t);
4364 } else if (r->min > 48000 && r->max <= 96000) {
4365 struct snd_interval t = {
4366 .min = hdsp->ds_out_channels,
4367 .max = hdsp->ds_out_channels,
4370 return snd_interval_refine(c, &t);
4371 } else if (r->max < 64000) {
4372 struct snd_interval t = {
4373 .min = hdsp->ss_out_channels,
4374 .max = hdsp->ss_out_channels,
4377 return snd_interval_refine(c, &t);
4382 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4383 struct snd_pcm_hw_rule *rule)
4385 struct hdsp *hdsp = rule->private;
4386 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4387 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4388 if (c->min >= hdsp->ss_out_channels) {
4389 struct snd_interval t = {
4394 return snd_interval_refine(r, &t);
4395 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4396 struct snd_interval t = {
4401 return snd_interval_refine(r, &t);
4402 } else if (c->max <= hdsp->ds_out_channels) {
4403 struct snd_interval t = {
4408 return snd_interval_refine(r, &t);
4413 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4414 struct snd_pcm_hw_rule *rule)
4416 struct hdsp *hdsp = rule->private;
4417 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4418 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4419 if (c->min >= hdsp->ss_in_channels) {
4420 struct snd_interval t = {
4425 return snd_interval_refine(r, &t);
4426 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4427 struct snd_interval t = {
4432 return snd_interval_refine(r, &t);
4433 } else if (c->max <= hdsp->ds_in_channels) {
4434 struct snd_interval t = {
4439 return snd_interval_refine(r, &t);
4444 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4446 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4447 struct snd_pcm_runtime *runtime = substream->runtime;
4449 if (hdsp_check_for_iobox (hdsp))
4452 if (hdsp_check_for_firmware(hdsp, 1))
4455 spin_lock_irq(&hdsp->lock);
4457 snd_pcm_set_sync(substream);
4459 runtime->hw = snd_hdsp_playback_subinfo;
4460 runtime->dma_area = hdsp->playback_buffer;
4461 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4463 hdsp->playback_pid = current->pid;
4464 hdsp->playback_substream = substream;
4466 spin_unlock_irq(&hdsp->lock);
4468 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4469 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4470 if (hdsp->clock_source_locked) {
4471 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4472 } else if (hdsp->io_type == H9632) {
4473 runtime->hw.rate_max = 192000;
4474 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4475 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4477 if (hdsp->io_type == H9632) {
4478 runtime->hw.channels_min = hdsp->qs_out_channels;
4479 runtime->hw.channels_max = hdsp->ss_out_channels;
4482 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4483 snd_hdsp_hw_rule_out_channels, hdsp,
4484 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4485 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4486 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4487 SNDRV_PCM_HW_PARAM_RATE, -1);
4488 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4489 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4490 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4492 if (RPM != hdsp->io_type) {
4493 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4494 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4495 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4496 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4501 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4503 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4505 spin_lock_irq(&hdsp->lock);
4507 hdsp->playback_pid = -1;
4508 hdsp->playback_substream = NULL;
4510 spin_unlock_irq(&hdsp->lock);
4512 if (RPM != hdsp->io_type) {
4513 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4514 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4515 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4521 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4523 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4524 struct snd_pcm_runtime *runtime = substream->runtime;
4526 if (hdsp_check_for_iobox (hdsp))
4529 if (hdsp_check_for_firmware(hdsp, 1))
4532 spin_lock_irq(&hdsp->lock);
4534 snd_pcm_set_sync(substream);
4536 runtime->hw = snd_hdsp_capture_subinfo;
4537 runtime->dma_area = hdsp->capture_buffer;
4538 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4540 hdsp->capture_pid = current->pid;
4541 hdsp->capture_substream = substream;
4543 spin_unlock_irq(&hdsp->lock);
4545 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4546 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4547 if (hdsp->io_type == H9632) {
4548 runtime->hw.channels_min = hdsp->qs_in_channels;
4549 runtime->hw.channels_max = hdsp->ss_in_channels;
4550 runtime->hw.rate_max = 192000;
4551 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4552 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4554 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4555 snd_hdsp_hw_rule_in_channels, hdsp,
4556 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4557 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4558 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4559 SNDRV_PCM_HW_PARAM_RATE, -1);
4560 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4561 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4562 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4566 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4568 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4570 spin_lock_irq(&hdsp->lock);
4572 hdsp->capture_pid = -1;
4573 hdsp->capture_substream = NULL;
4575 spin_unlock_irq(&hdsp->lock);
4579 /* helper functions for copying meter values */
4580 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4582 u32 val = readl(src);
4583 return copy_to_user(dest, &val, 4);
4586 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4588 u32 rms_low, rms_high;
4590 rms_low = readl(src_low);
4591 rms_high = readl(src_high);
4592 rms = ((u64)rms_high << 32) | rms_low;
4593 return copy_to_user(dest, &rms, 8);
4596 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4598 u32 rms_low, rms_high;
4600 rms_low = readl(src_low) & 0xffffff00;
4601 rms_high = readl(src_high) & 0xffffff00;
4602 rms = ((u64)rms_high << 32) | rms_low;
4603 return copy_to_user(dest, &rms, 8);
4606 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4608 int doublespeed = 0;
4609 int i, j, channels, ofs;
4611 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4613 channels = doublespeed ? 14 : 26;
4614 for (i = 0, j = 0; i < 26; ++i) {
4615 if (doublespeed && (i & 4))
4617 ofs = HDSP_9652_peakBase - j * 4;
4618 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4620 ofs -= channels * 4;
4621 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4623 ofs -= channels * 4;
4624 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4626 ofs = HDSP_9652_rmsBase + j * 8;
4627 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4628 hdsp->iobase + ofs + 4))
4630 ofs += channels * 8;
4631 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4632 hdsp->iobase + ofs + 4))
4634 ofs += channels * 8;
4635 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4636 hdsp->iobase + ofs + 4))
4643 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4646 struct hdsp_9632_meters __iomem *m;
4647 int doublespeed = 0;
4649 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4651 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4652 for (i = 0, j = 0; i < 16; ++i, ++j) {
4653 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4655 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4657 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4659 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4660 &m->input_rms_high[j]))
4662 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4663 &m->playback_rms_high[j]))
4665 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4666 &m->output_rms_high[j]))
4668 if (doublespeed && i == 3) i += 4;
4673 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4677 for (i = 0; i < 26; i++) {
4678 if (copy_u32_le(&peak_rms->playback_peaks[i],
4679 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4681 if (copy_u32_le(&peak_rms->input_peaks[i],
4682 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4685 for (i = 0; i < 28; i++) {
4686 if (copy_u32_le(&peak_rms->output_peaks[i],
4687 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4690 for (i = 0; i < 26; ++i) {
4691 if (copy_u64_le(&peak_rms->playback_rms[i],
4692 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4693 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4695 if (copy_u64_le(&peak_rms->input_rms[i],
4696 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4697 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4703 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4705 struct hdsp *hdsp = hw->private_data;
4706 void __user *argp = (void __user *)arg;
4710 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4711 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4713 err = hdsp_check_for_iobox(hdsp);
4717 err = hdsp_check_for_firmware(hdsp, 1);
4721 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4722 dev_err(hdsp->card->dev,
4723 "firmware needs to be uploaded to the card.\n");
4727 switch (hdsp->io_type) {
4729 return hdsp_9652_get_peak(hdsp, peak_rms);
4731 return hdsp_9632_get_peak(hdsp, peak_rms);
4733 return hdsp_get_peak(hdsp, peak_rms);
4736 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4737 struct hdsp_config_info info;
4738 unsigned long flags;
4741 err = hdsp_check_for_iobox(hdsp);
4745 err = hdsp_check_for_firmware(hdsp, 1);
4749 memset(&info, 0, sizeof(info));
4750 spin_lock_irqsave(&hdsp->lock, flags);
4751 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4752 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4753 if (hdsp->io_type != H9632)
4754 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4755 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4756 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4757 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4758 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4759 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4760 HDSP_SPDIFOpticalOut);
4761 info.spdif_professional = (unsigned char)
4762 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4763 info.spdif_emphasis = (unsigned char)
4764 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4765 info.spdif_nonaudio = (unsigned char)
4766 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4767 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4768 info.system_sample_rate = hdsp->system_sample_rate;
4769 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4770 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4771 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4772 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4773 info.line_out = (unsigned char)
4774 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4775 if (hdsp->io_type == H9632) {
4776 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4777 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4778 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4779 info.xlr_breakout_cable =
4780 (unsigned char)hdsp_toggle_setting(hdsp,
4781 HDSP_XLRBreakoutCable);
4783 } else if (hdsp->io_type == RPM) {
4784 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4785 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4787 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4788 info.analog_extension_board =
4789 (unsigned char)hdsp_toggle_setting(hdsp,
4790 HDSP_AnalogExtensionBoard);
4791 spin_unlock_irqrestore(&hdsp->lock, flags);
4792 if (copy_to_user(argp, &info, sizeof(info)))
4796 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4797 struct hdsp_9632_aeb h9632_aeb;
4799 if (hdsp->io_type != H9632) return -EINVAL;
4800 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4801 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4802 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4806 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4807 struct hdsp_version hdsp_version;
4810 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4811 if (hdsp->io_type == Undefined) {
4812 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4815 memset(&hdsp_version, 0, sizeof(hdsp_version));
4816 hdsp_version.io_type = hdsp->io_type;
4817 hdsp_version.firmware_rev = hdsp->firmware_rev;
4818 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4822 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4823 struct hdsp_firmware __user *firmware;
4824 u32 __user *firmware_data;
4827 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4828 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4829 if (hdsp->io_type == Undefined) return -EINVAL;
4831 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4834 dev_info(hdsp->card->dev,
4835 "initializing firmware upload\n");
4836 firmware = (struct hdsp_firmware __user *)argp;
4838 if (get_user(firmware_data, &firmware->firmware_data))
4841 if (hdsp_check_for_iobox (hdsp))
4844 if (!hdsp->fw_uploaded) {
4845 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4846 if (!hdsp->fw_uploaded)
4850 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4851 HDSP_FIRMWARE_SIZE)) {
4852 vfree(hdsp->fw_uploaded);
4853 hdsp->fw_uploaded = NULL;
4857 hdsp->state |= HDSP_FirmwareCached;
4859 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4862 if (!(hdsp->state & HDSP_InitializationComplete)) {
4863 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4866 snd_hdsp_initialize_channels(hdsp);
4867 snd_hdsp_initialize_midi_flush(hdsp);
4869 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4870 dev_err(hdsp->card->dev,
4871 "error creating alsa devices\n");
4877 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4878 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4879 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4889 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4890 .open = snd_hdsp_playback_open,
4891 .close = snd_hdsp_playback_release,
4892 .ioctl = snd_hdsp_ioctl,
4893 .hw_params = snd_hdsp_hw_params,
4894 .prepare = snd_hdsp_prepare,
4895 .trigger = snd_hdsp_trigger,
4896 .pointer = snd_hdsp_hw_pointer,
4897 .copy_user = snd_hdsp_playback_copy,
4898 .copy_kernel = snd_hdsp_playback_copy_kernel,
4899 .fill_silence = snd_hdsp_hw_silence,
4902 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4903 .open = snd_hdsp_capture_open,
4904 .close = snd_hdsp_capture_release,
4905 .ioctl = snd_hdsp_ioctl,
4906 .hw_params = snd_hdsp_hw_params,
4907 .prepare = snd_hdsp_prepare,
4908 .trigger = snd_hdsp_trigger,
4909 .pointer = snd_hdsp_hw_pointer,
4910 .copy_user = snd_hdsp_capture_copy,
4911 .copy_kernel = snd_hdsp_capture_copy_kernel,
4914 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4916 struct snd_hwdep *hw;
4919 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4923 hw->private_data = hdsp;
4924 strcpy(hw->name, "HDSP hwdep interface");
4926 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4927 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4932 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4934 struct snd_pcm *pcm;
4937 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4941 pcm->private_data = hdsp;
4942 strcpy(pcm->name, hdsp->card_name);
4944 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4945 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4947 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4952 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4954 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4955 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4958 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4962 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4963 dev_err(hdsp->card->dev,
4964 "enable_io fifo_wait failed\n");
4968 for (i = 0; i < hdsp->max_channels; ++i) {
4969 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4970 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4976 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4978 int status, aebi_channels, aebo_channels;
4980 switch (hdsp->io_type) {
4982 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4983 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4984 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4988 hdsp->card_name = "RME Hammerfall HDSP 9652";
4989 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4990 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4994 status = hdsp_read(hdsp, HDSP_statusRegister);
4995 /* HDSP_AEBx bits are low when AEB are connected */
4996 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4997 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4998 hdsp->card_name = "RME Hammerfall HDSP 9632";
4999 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5000 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5001 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5002 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5003 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5004 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5008 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5009 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5010 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5014 hdsp->card_name = "RME Hammerfall DSP + RPM";
5015 hdsp->ss_in_channels = RPM_CHANNELS-1;
5016 hdsp->ss_out_channels = RPM_CHANNELS;
5017 hdsp->ds_in_channels = RPM_CHANNELS-1;
5018 hdsp->ds_out_channels = RPM_CHANNELS;
5022 /* should never get here */
5027 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5029 snd_hdsp_flush_midi_input (hdsp, 0);
5030 snd_hdsp_flush_midi_input (hdsp, 1);
5033 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5037 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5039 "Error creating pcm interface\n");
5044 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5046 "Error creating first midi interface\n");
5050 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5051 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5053 "Error creating second midi interface\n");
5058 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5060 "Error creating ctl interface\n");
5064 snd_hdsp_proc_init(hdsp);
5066 hdsp->system_sample_rate = -1;
5067 hdsp->playback_pid = -1;
5068 hdsp->capture_pid = -1;
5069 hdsp->capture_substream = NULL;
5070 hdsp->playback_substream = NULL;
5072 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5074 "Error setting default values\n");
5078 if (!(hdsp->state & HDSP_InitializationComplete)) {
5079 strcpy(card->shortname, "Hammerfall DSP");
5080 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5081 hdsp->port, hdsp->irq);
5083 if ((err = snd_card_register(card)) < 0) {
5085 "error registering card\n");
5088 hdsp->state |= HDSP_InitializationComplete;
5094 /* load firmware via hotplug fw loader */
5095 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5098 const struct firmware *fw;
5101 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5103 if (hdsp->io_type == Undefined) {
5104 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5106 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5110 /* caution: max length of firmware filename is 30! */
5111 switch (hdsp->io_type) {
5113 fwfile = "/*(DEBLOBBED)*/";
5116 if (hdsp->firmware_rev == 0xa)
5117 fwfile = "/*(DEBLOBBED)*/";
5119 fwfile = "/*(DEBLOBBED)*/";
5122 if (hdsp->firmware_rev == 0xa)
5123 fwfile = "/*(DEBLOBBED)*/";
5125 fwfile = "/*(DEBLOBBED)*/";
5128 dev_err(hdsp->card->dev,
5129 "invalid io_type %d\n", hdsp->io_type);
5133 if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5134 dev_err(hdsp->card->dev,
5135 "cannot load firmware %s\n", fwfile);
5138 if (fw->size < HDSP_FIRMWARE_SIZE) {
5139 dev_err(hdsp->card->dev,
5140 "too short firmware size %d (expected %d)\n",
5141 (int)fw->size, HDSP_FIRMWARE_SIZE);
5142 release_firmware(fw);
5146 hdsp->firmware = fw;
5148 hdsp->state |= HDSP_FirmwareCached;
5150 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5153 if (!(hdsp->state & HDSP_InitializationComplete)) {
5154 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5157 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5158 dev_err(hdsp->card->dev,
5159 "error creating hwdep device\n");
5162 snd_hdsp_initialize_channels(hdsp);
5163 snd_hdsp_initialize_midi_flush(hdsp);
5164 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5165 dev_err(hdsp->card->dev,
5166 "error creating alsa devices\n");
5173 static int snd_hdsp_create(struct snd_card *card,
5176 struct pci_dev *pci = hdsp->pci;
5183 hdsp->midi[0].rmidi = NULL;
5184 hdsp->midi[1].rmidi = NULL;
5185 hdsp->midi[0].input = NULL;
5186 hdsp->midi[1].input = NULL;
5187 hdsp->midi[0].output = NULL;
5188 hdsp->midi[1].output = NULL;
5189 hdsp->midi[0].pending = 0;
5190 hdsp->midi[1].pending = 0;
5191 spin_lock_init(&hdsp->midi[0].lock);
5192 spin_lock_init(&hdsp->midi[1].lock);
5193 hdsp->iobase = NULL;
5194 hdsp->control_register = 0;
5195 hdsp->control2_register = 0;
5196 hdsp->io_type = Undefined;
5197 hdsp->max_channels = 26;
5201 spin_lock_init(&hdsp->lock);
5203 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5205 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5206 hdsp->firmware_rev &= 0xff;
5208 /* From Martin Bjoernsen :
5209 "It is important that the card's latency timer register in
5210 the PCI configuration space is set to a value much larger
5211 than 0 by the computer's BIOS or the driver.
5212 The windows driver always sets this 8 bit register [...]
5213 to its maximum 255 to avoid problems with some computers."
5215 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5217 strcpy(card->driver, "H-DSP");
5218 strcpy(card->mixername, "Xilinx FPGA");
5220 if (hdsp->firmware_rev < 0xa)
5222 else if (hdsp->firmware_rev < 0x64)
5223 hdsp->card_name = "RME Hammerfall DSP";
5224 else if (hdsp->firmware_rev < 0x96) {
5225 hdsp->card_name = "RME HDSP 9652";
5228 hdsp->card_name = "RME HDSP 9632";
5229 hdsp->max_channels = 16;
5233 if ((err = pci_enable_device(pci)) < 0)
5236 pci_set_master(hdsp->pci);
5238 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5240 hdsp->port = pci_resource_start(pci, 0);
5241 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5242 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5243 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5247 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5248 KBUILD_MODNAME, hdsp)) {
5249 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5253 hdsp->irq = pci->irq;
5254 hdsp->precise_ptr = 0;
5255 hdsp->use_midi_tasklet = 1;
5256 hdsp->dds_value = 0;
5258 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5261 if (!is_9652 && !is_9632) {
5262 /* we wait a maximum of 10 seconds to let freshly
5263 * inserted cardbus cards do their hardware init */
5264 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5269 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5270 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5271 /* we don't fail as this can happen
5272 if userspace is not ready for
5275 dev_err(hdsp->card->dev,
5276 "couldn't get firmware from userspace. try using hdsploader\n");
5278 /* init is complete, we return */
5280 /* we defer initialization */
5281 dev_info(hdsp->card->dev,
5282 "card initialization pending : waiting for firmware\n");
5283 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5287 dev_info(hdsp->card->dev,
5288 "Firmware already present, initializing card.\n");
5289 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5290 hdsp->io_type = RPM;
5291 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5292 hdsp->io_type = Multiface;
5294 hdsp->io_type = Digiface;
5298 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5302 hdsp->io_type = H9652;
5305 hdsp->io_type = H9632;
5307 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5310 snd_hdsp_initialize_channels(hdsp);
5311 snd_hdsp_initialize_midi_flush(hdsp);
5313 hdsp->state |= HDSP_FirmwareLoaded;
5315 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5321 static int snd_hdsp_free(struct hdsp *hdsp)
5324 /* stop the audio, and cancel all interrupts */
5325 tasklet_kill(&hdsp->midi_tasklet);
5326 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5327 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5331 free_irq(hdsp->irq, (void *)hdsp);
5333 snd_hdsp_free_buffers(hdsp);
5335 release_firmware(hdsp->firmware);
5336 vfree(hdsp->fw_uploaded);
5337 iounmap(hdsp->iobase);
5340 pci_release_regions(hdsp->pci);
5342 if (pci_is_enabled(hdsp->pci))
5343 pci_disable_device(hdsp->pci);
5347 static void snd_hdsp_card_free(struct snd_card *card)
5349 struct hdsp *hdsp = card->private_data;
5352 snd_hdsp_free(hdsp);
5355 static int snd_hdsp_probe(struct pci_dev *pci,
5356 const struct pci_device_id *pci_id)
5360 struct snd_card *card;
5363 if (dev >= SNDRV_CARDS)
5370 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5371 sizeof(struct hdsp), &card);
5375 hdsp = card->private_data;
5376 card->private_free = snd_hdsp_card_free;
5379 err = snd_hdsp_create(card, hdsp);
5383 strcpy(card->shortname, "Hammerfall DSP");
5384 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5385 hdsp->port, hdsp->irq);
5386 err = snd_card_register(card);
5389 snd_card_free(card);
5392 pci_set_drvdata(pci, card);
5397 static void snd_hdsp_remove(struct pci_dev *pci)
5399 snd_card_free(pci_get_drvdata(pci));
5402 static struct pci_driver hdsp_driver = {
5403 .name = KBUILD_MODNAME,
5404 .id_table = snd_hdsp_ids,
5405 .probe = snd_hdsp_probe,
5406 .remove = snd_hdsp_remove,
5409 module_pci_driver(hdsp_driver);