sound/pci/rme9652/hdsp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   4  *
   5  *      Copyright (c) 2002  Paul Davis
   6  *                          Marcus Andersson
   7  *                          Thomas Charbonnel
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/pci.h>
  14 #include <linux/firmware.h>
  15 #include <linux/module.h>
  16 #include <linux/math64.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/io.h>
  19 #include <linux/nospec.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/control.h>
  23 #include <sound/pcm.h>
  24 #include <sound/info.h>
  25 #include <sound/asoundef.h>
  26 #include <sound/rawmidi.h>
  27 #include <sound/hwdep.h>
  28 #include <sound/initval.h>
  29 #include <sound/hdsp.h>
  30
  31 #include <asm/byteorder.h>
  32 #include <asm/current.h>
  33
  34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  37
  38 module_param_array(index, int, NULL, 0444);
  39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  40 module_param_array(id, charp, NULL, 0444);
  41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  42 module_param_array(enable, bool, NULL, 0444);
  43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  45 MODULE_DESCRIPTION("RME Hammerfall DSP");
  46 MODULE_LICENSE("GPL");
  47 /*(DEBLOBBED)*/
  48
  49 #define HDSP_MAX_CHANNELS        26
  50 #define HDSP_MAX_DS_CHANNELS     14
  51 #define HDSP_MAX_QS_CHANNELS     8
  52 #define DIGIFACE_SS_CHANNELS     26
  53 #define DIGIFACE_DS_CHANNELS     14
  54 #define MULTIFACE_SS_CHANNELS    18
  55 #define MULTIFACE_DS_CHANNELS    14
  56 #define H9652_SS_CHANNELS        26
  57 #define H9652_DS_CHANNELS        14
  58 /* This does not include possible Analog Extension Boards
  59    AEBs are detected at card initialization
  60 */
  61 #define H9632_SS_CHANNELS        12
  62 #define H9632_DS_CHANNELS        8
  63 #define H9632_QS_CHANNELS        4
  64 #define RPM_CHANNELS             6
  65
  66 /* Write registers. These are defined as byte-offsets from the iobase value.
  67  */
  68 #define HDSP_resetPointer               0
  69 #define HDSP_freqReg                    0
  70 #define HDSP_outputBufferAddress        32
  71 #define HDSP_inputBufferAddress         36
  72 #define HDSP_controlRegister            64
  73 #define HDSP_interruptConfirmation      96
  74 #define HDSP_outputEnable               128
  75 #define HDSP_control2Reg                256
  76 #define HDSP_midiDataOut0               352
  77 #define HDSP_midiDataOut1               356
  78 #define HDSP_fifoData                   368
  79 #define HDSP_inputEnable                384
  80
  81 /* Read registers. These are defined as byte-offsets from the iobase value
  82  */
  83
  84 #define HDSP_statusRegister    0
  85 #define HDSP_timecode        128
  86 #define HDSP_status2Register 192
  87 #define HDSP_midiDataIn0     360
  88 #define HDSP_midiDataIn1     364
  89 #define HDSP_midiStatusOut0  384
  90 #define HDSP_midiStatusOut1  388
  91 #define HDSP_midiStatusIn0   392
  92 #define HDSP_midiStatusIn1   396
  93 #define HDSP_fifoStatus      400
  94
  95 /* the meters are regular i/o-mapped registers, but offset
  96    considerably from the rest. the peak registers are reset
  97    when read; the least-significant 4 bits are full-scale counters;
  98    the actual peak value is in the most-significant 24 bits.
  99 */
 100
 101 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 102 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 103 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 104 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 105 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 106
 107
 108 /* This is for H9652 cards
 109    Peak values are read downward from the base
 110    Rms values are read upward
 111    There are rms values for the outputs too
 112    26*3 values are read in ss mode
 113    14*3 in ds mode, with no gap between values
 114 */
 115 #define HDSP_9652_peakBase      7164
 116 #define HDSP_9652_rmsBase       4096
 117
 118 /* c.f. the hdsp_9632_meters_t struct */
 119 #define HDSP_9632_metersBase    4096
 120
 121 #define HDSP_IO_EXTENT     7168
 122
 123 /* control2 register bits */
 124
 125 #define HDSP_TMS                0x01
 126 #define HDSP_TCK                0x02
 127 #define HDSP_TDI                0x04
 128 #define HDSP_JTAG               0x08
 129 #define HDSP_PWDN               0x10
 130 #define HDSP_PROGRAM            0x020
 131 #define HDSP_CONFIG_MODE_0      0x040
 132 #define HDSP_CONFIG_MODE_1      0x080
 133 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 134 #define HDSP_BIGENDIAN_MODE     0x200
 135 #define HDSP_RD_MULTIPLE        0x400
 136 #define HDSP_9652_ENABLE_MIXER  0x800
 137 #define HDSP_S200               0x800
 138 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 139 #define HDSP_CYCLIC_MODE        0x1000
 140 #define HDSP_TDO                0x10000000
 141
 142 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 143 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 144
 145 /* Control Register bits */
 146
 147 #define HDSP_Start                (1<<0)  /* start engine */
 148 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 149 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 150 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 151 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 152 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 153 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 154 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 155 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 156 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 157 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 158 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 159 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 160 #define HDSP_SyncRef2             (1<<13)
 161 #define HDSP_SPDIFInputSelect0    (1<<14)
 162 #define HDSP_SPDIFInputSelect1    (1<<15)
 163 #define HDSP_SyncRef0             (1<<16)
 164 #define HDSP_SyncRef1             (1<<17)
 165 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 166 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 167 #define HDSP_Midi0InterruptEnable (1<<22)
 168 #define HDSP_Midi1InterruptEnable (1<<23)
 169 #define HDSP_LineOut              (1<<24)
 170 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 171 #define HDSP_ADGain1              (1<<26)
 172 #define HDSP_DAGain0              (1<<27)
 173 #define HDSP_DAGain1              (1<<28)
 174 #define HDSP_PhoneGain0           (1<<29)
 175 #define HDSP_PhoneGain1           (1<<30)
 176 #define HDSP_QuadSpeed            (1<<31)
 177
 178 /* RPM uses some of the registers for special purposes */
 179 #define HDSP_RPM_Inp12            0x04A00
 180 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 181 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 182 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 183 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 184 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 185
 186 #define HDSP_RPM_Inp34            0x32000
 187 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 188 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 189 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 190 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 191 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 192
 193 #define HDSP_RPM_Bypass           0x01000
 194
 195 #define HDSP_RPM_Disconnect       0x00001
 196
 197 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 198 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 199 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 200 #define HDSP_ADGainLowGain     0
 201
 202 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 203 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 204 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 205 #define HDSP_DAGainMinus10dBV    0
 206
 207 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 208 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 209 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 210 #define HDSP_PhoneGainMinus12dB  0
 211
 212 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 213 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 214
 215 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 216 #define HDSP_SPDIFInputADAT1    0
 217 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 218 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 219 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 220
 221 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 222 #define HDSP_SyncRef_ADAT1       0
 223 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 224 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 225 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 226 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 227 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 228
 229 /* Sample Clock Sources */
 230
 231 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 232 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 233 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 234 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 235 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 236 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 240 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 241
 242 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 243
 244 #define HDSP_SYNC_FROM_WORD      0
 245 #define HDSP_SYNC_FROM_SPDIF     1
 246 #define HDSP_SYNC_FROM_ADAT1     2
 247 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 248 #define HDSP_SYNC_FROM_ADAT2     4
 249 #define HDSP_SYNC_FROM_ADAT3     5
 250
 251 /* SyncCheck status */
 252
 253 #define HDSP_SYNC_CHECK_NO_LOCK 0
 254 #define HDSP_SYNC_CHECK_LOCK    1
 255 #define HDSP_SYNC_CHECK_SYNC    2
 256
 257 /* AutoSync references - used by "autosync_ref" control switch */
 258
 259 #define HDSP_AUTOSYNC_FROM_WORD      0
 260 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 261 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 262 #define HDSP_AUTOSYNC_FROM_NONE      3
 263 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 264 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 265 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 266
 267 /* Possible sources of S/PDIF input */
 268
 269 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 270 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 271 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 272 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 273
 274 #define HDSP_Frequency32KHz    HDSP_Frequency0
 275 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 276 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 277 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 278 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 279 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 280 /* For H9632 cards */
 281 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 282 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 283 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 284 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 285         return 104857600000000 / rate; // 100 MHz
 286         return 110100480000000 / rate; // 105 MHz
 287 */
 288 #define DDS_NUMERATOR 104857600000000ULL  /*  =  2^20 * 10^8 */
 289
 290 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 291 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 292
 293 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 294 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 295
 296 /* Status Register bits */
 297
 298 #define HDSP_audioIRQPending    (1<<0)
 299 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 300 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 301 #define HDSP_Lock1              (1<<2)
 302 #define HDSP_Lock0              (1<<3)
 303 #define HDSP_SPDIFSync          (1<<4)
 304 #define HDSP_TimecodeLock       (1<<5)
 305 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 306 #define HDSP_Sync2              (1<<16)
 307 #define HDSP_Sync1              (1<<17)
 308 #define HDSP_Sync0              (1<<18)
 309 #define HDSP_DoubleSpeedStatus  (1<<19)
 310 #define HDSP_ConfigError        (1<<20)
 311 #define HDSP_DllError           (1<<21)
 312 #define HDSP_spdifFrequency0    (1<<22)
 313 #define HDSP_spdifFrequency1    (1<<23)
 314 #define HDSP_spdifFrequency2    (1<<24)
 315 #define HDSP_SPDIFErrorFlag     (1<<25)
 316 #define HDSP_BufferID           (1<<26)
 317 #define HDSP_TimecodeSync       (1<<27)
 318 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 319 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 320 #define HDSP_midi0IRQPending    (1<<30)
 321 #define HDSP_midi1IRQPending    (1<<31)
 322
 323 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 324 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 325                                       HDSP_spdifFrequency1|\
 326                                       HDSP_spdifFrequency2|\
 327                                       HDSP_spdifFrequency3)
 328
 329 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 330 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 331 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 332
 333 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 334 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 335 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 336
 337 /* This is for H9632 cards */
 338 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 339                                      HDSP_spdifFrequency1|\
 340                                      HDSP_spdifFrequency2)
 341 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 342 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 343
 344 /* Status2 Register bits */
 345
 346 #define HDSP_version0     (1<<0)
 347 #define HDSP_version1     (1<<1)
 348 #define HDSP_version2     (1<<2)
 349 #define HDSP_wc_lock      (1<<3)
 350 #define HDSP_wc_sync      (1<<4)
 351 #define HDSP_inp_freq0    (1<<5)
 352 #define HDSP_inp_freq1    (1<<6)
 353 #define HDSP_inp_freq2    (1<<7)
 354 #define HDSP_SelSyncRef0  (1<<8)
 355 #define HDSP_SelSyncRef1  (1<<9)
 356 #define HDSP_SelSyncRef2  (1<<10)
 357
 358 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 359
 360 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 361 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 362 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 363 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 364 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 365 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 366 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 367 /* FIXME : more values for 9632 cards ? */
 368
 369 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 370 #define HDSP_SelSyncRef_ADAT1      0
 371 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 372 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 373 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 374 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 375 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 376
 377 /* Card state flags */
 378
 379 #define HDSP_InitializationComplete  (1<<0)
 380 #define HDSP_FirmwareLoaded          (1<<1)
 381 #define HDSP_FirmwareCached          (1<<2)
 382
 383 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 384
 385 #define HDSP_LONG_WAIT   5000
 386 #define HDSP_SHORT_WAIT  30
 387
 388 #define UNITY_GAIN                       32768
 389 #define MINUS_INFINITY_GAIN              0
 390
 391 /* the size of a substream (1 mono data stream) */
 392
 393 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 394 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 395
 396 /* the size of the area we need to allocate for DMA transfers. the
 397    size is the same regardless of the number of channels - the
 398    Multiface still uses the same memory area.
 399
 400    Note that we allocate 1 more channel than is apparently needed
 401    because the h/w seems to write 1 byte beyond the end of the last
 402    page. Sigh.
 403 */
 404
 405 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 406 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 407
 408 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 409
 410 struct hdsp_9632_meters {
 411     u32 input_peak[16];
 412     u32 playback_peak[16];
 413     u32 output_peak[16];
 414     u32 xxx_peak[16];
 415     u32 padding[64];
 416     u32 input_rms_low[16];
 417     u32 playback_rms_low[16];
 418     u32 output_rms_low[16];
 419     u32 xxx_rms_low[16];
 420     u32 input_rms_high[16];
 421     u32 playback_rms_high[16];
 422     u32 output_rms_high[16];
 423     u32 xxx_rms_high[16];
 424 };
 425
 426 struct hdsp_midi {
 427     struct hdsp             *hdsp;
 428     int                      id;
 429     struct snd_rawmidi           *rmidi;
 430     struct snd_rawmidi_substream *input;
 431     struct snd_rawmidi_substream *output;
 432     signed char              istimer; /* timer in use */
 433     struct timer_list        timer;
 434     spinlock_t               lock;
 435     int                      pending;
 436 };
 437
 438 struct hdsp {
 439         spinlock_t            lock;
 440         struct snd_pcm_substream *capture_substream;
 441         struct snd_pcm_substream *playback_substream;
 442         struct hdsp_midi      midi[2];
 443         struct work_struct    midi_work;
 444         int                   use_midi_work;
 445         int                   precise_ptr;
 446         u32                   control_register;      /* cached value */
 447         u32                   control2_register;     /* cached value */
 448         u32                   creg_spdif;
 449         u32                   creg_spdif_stream;
 450         int                   clock_source_locked;
 451         char                 *card_name;         /* digiface/multiface/rpm */
 452         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 453         unsigned short        firmware_rev;
 454         unsigned short        state;                 /* stores state bits */
 455         const struct firmware *firmware;
 456         u32                  *fw_uploaded;
 457         size_t                period_bytes;          /* guess what this is */
 458         unsigned char         max_channels;
 459         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 460         unsigned char         ds_in_channels;
 461         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 462         unsigned char         qs_out_channels;
 463         unsigned char         ds_out_channels;
 464         unsigned char         ss_out_channels;
 465         u32                   io_loopback;          /* output loopback channel states*/
 466
 467         /* DMA buffers; those are copied instances from the original snd_dma_buf
 468          * objects (which are managed via devres) for the address alignments
 469          */
 470         struct snd_dma_buffer capture_dma_buf;
 471         struct snd_dma_buffer playback_dma_buf;
 472         unsigned char        *capture_buffer;       /* suitably aligned address */
 473         unsigned char        *playback_buffer;      /* suitably aligned address */
 474
 475         pid_t                 capture_pid;
 476         pid_t                 playback_pid;
 477         int                   running;
 478         int                   system_sample_rate;
 479         const signed char    *channel_map;
 480         int                   dev;
 481         int                   irq;
 482         unsigned long         port;
 483         void __iomem         *iobase;
 484         struct snd_card *card;
 485         struct snd_pcm *pcm;
 486         struct snd_hwdep          *hwdep;
 487         struct pci_dev       *pci;
 488         struct snd_kcontrol *spdif_ctl;
 489         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 490         unsigned int          dds_value; /* last value written to freq register */
 491 };
 492
 493 /* These tables map the ALSA channels 1..N to the channels that we
 494    need to use in order to find the relevant channel buffer. RME
 495    refer to this kind of mapping as between "the ADAT channel and
 496    the DMA channel." We index it using the logical audio channel,
 497    and the value is the DMA channel (i.e. channel buffer number)
 498    where the data for that channel can be read/written from/to.
 499 */
 500
 501 static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 502         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 503         18, 19, 20, 21, 22, 23, 24, 25
 504 };
 505
 506 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 507         /* Analog */
 508         0, 1, 2, 3, 4, 5, 6, 7,
 509         /* ADAT 2 */
 510         16, 17, 18, 19, 20, 21, 22, 23,
 511         /* SPDIF */
 512         24, 25,
 513         -1, -1, -1, -1, -1, -1, -1, -1
 514 };
 515
 516 static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = {
 517         /* ADAT channels are remapped */
 518         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 519         /* channels 12 and 13 are S/PDIF */
 520         24, 25,
 521         /* others don't exist */
 522         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 523 };
 524
 525 static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 526         /* ADAT channels */
 527         0, 1, 2, 3, 4, 5, 6, 7,
 528         /* SPDIF */
 529         8, 9,
 530         /* Analog */
 531         10, 11,
 532         /* AO4S-192 and AI4S-192 extension boards */
 533         12, 13, 14, 15,
 534         /* others don't exist */
 535         -1, -1, -1, -1, -1, -1, -1, -1,
 536         -1, -1
 537 };
 538
 539 static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 540         /* ADAT */
 541         1, 3, 5, 7,
 542         /* SPDIF */
 543         8, 9,
 544         /* Analog */
 545         10, 11,
 546         /* AO4S-192 and AI4S-192 extension boards */
 547         12, 13, 14, 15,
 548         /* others don't exist */
 549         -1, -1, -1, -1, -1, -1, -1, -1,
 550         -1, -1, -1, -1, -1, -1
 551 };
 552
 553 static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 554         /* ADAT is disabled in this mode */
 555         /* SPDIF */
 556         8, 9,
 557         /* Analog */
 558         10, 11,
 559         /* AO4S-192 and AI4S-192 extension boards */
 560         12, 13, 14, 15,
 561         /* others don't exist */
 562         -1, -1, -1, -1, -1, -1, -1, -1,
 563         -1, -1, -1, -1, -1, -1, -1, -1,
 564         -1, -1
 565 };
 566
 567 static struct snd_dma_buffer *
 568 snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
 569 {
 570         return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
 571 }
 572
 573 static const struct pci_device_id snd_hdsp_ids[] = {
 574         {
 575                 .vendor = PCI_VENDOR_ID_XILINX,
 576                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 577                 .subvendor = PCI_ANY_ID,
 578                 .subdevice = PCI_ANY_ID,
 579         }, /* RME Hammerfall-DSP */
 580         { 0, },
 581 };
 582
 583 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 584
 585 /* prototypes */
 586 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 587 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 588 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 589 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 590 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 591 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 592 static int hdsp_autosync_ref(struct hdsp *hdsp);
 593 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 594 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 595
 596 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 597 {
 598         switch (hdsp->io_type) {
 599         case Multiface:
 600         case Digiface:
 601         case RPM:
 602         default:
 603                 if (hdsp->firmware_rev == 0xa)
 604                         return (64 * out) + (32 + (in));
 605                 else
 606                         return (52 * out) + (26 + (in));
 607         case H9632:
 608                 return (32 * out) + (16 + (in));
 609         case H9652:
 610                 return (52 * out) + (26 + (in));
 611         }
 612 }
 613
 614 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 615 {
 616         switch (hdsp->io_type) {
 617         case Multiface:
 618         case Digiface:
 619         case RPM:
 620         default:
 621                 if (hdsp->firmware_rev == 0xa)
 622                         return (64 * out) + in;
 623                 else
 624                         return (52 * out) + in;
 625         case H9632:
 626                 return (32 * out) + in;
 627         case H9652:
 628                 return (52 * out) + in;
 629         }
 630 }
 631
 632 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 633 {
 634         writel(val, hdsp->iobase + reg);
 635 }
 636
 637 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 638 {
 639         return readl (hdsp->iobase + reg);
 640 }
 641
 642 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 643 {
 644         int i;
 645
 646         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 647         for (i = 0; i < 500; i++) {
 648                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 649                                         HDSP_ConfigError)) {
 650                         if (i) {
 651                                 dev_dbg(hdsp->card->dev,
 652                                         "IO box found after %d ms\n",
 653                                                 (20 * i));
 654                         }
 655                         return 0;
 656                 }
 657                 msleep(20);
 658         }
 659         dev_err(hdsp->card->dev, "no IO box connected!\n");
 660         hdsp->state &= ~HDSP_FirmwareLoaded;
 661         return -EIO;
 662 }
 663
 664 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 665                                unsigned int delay)
 666 {
 667         unsigned int i;
 668
 669         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 670                 return 0;
 671
 672         for (i = 0; i != loops; ++i) {
 673                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 674                         msleep(delay);
 675                 else {
 676                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 677                                    i * delay);
 678                         return 0;
 679                 }
 680         }
 681
 682         dev_info(hdsp->card->dev, "no IO box connected!\n");
 683         hdsp->state &= ~HDSP_FirmwareLoaded;
 684         return -EIO;
 685 }
 686
 687 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 688
 689         int i;
 690         unsigned long flags;
 691         const u32 *cache;
 692
 693         if (hdsp->fw_uploaded)
 694                 cache = hdsp->fw_uploaded;
 695         else {
 696                 if (!hdsp->firmware)
 697                         return -ENODEV;
 698                 cache = (u32 *)hdsp->firmware->data;
 699                 if (!cache)
 700                         return -ENODEV;
 701         }
 702
 703         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 704
 705                 dev_info(hdsp->card->dev, "loading firmware\n");
 706
 707                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 708                 hdsp_write (hdsp, HDSP_fifoData, 0);
 709
 710                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 711                         dev_info(hdsp->card->dev,
 712                                  "timeout waiting for download preparation\n");
 713                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 714                         return -EIO;
 715                 }
 716
 717                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 718
 719                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 720                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 721                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 722                                 dev_info(hdsp->card->dev,
 723                                          "timeout during firmware loading\n");
 724                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 725                                 return -EIO;
 726                         }
 727                 }
 728
 729                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 730                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 731
 732                 ssleep(3);
 733 #ifdef SNDRV_BIG_ENDIAN
 734                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 735 #else
 736                 hdsp->control2_register = 0;
 737 #endif
 738                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 739                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 740
 741         }
 742         if (hdsp->state & HDSP_InitializationComplete) {
 743                 dev_info(hdsp->card->dev,
 744                          "firmware loaded from cache, restoring defaults\n");
 745                 spin_lock_irqsave(&hdsp->lock, flags);
 746                 snd_hdsp_set_defaults(hdsp);
 747                 spin_unlock_irqrestore(&hdsp->lock, flags);
 748         }
 749
 750         hdsp->state |= HDSP_FirmwareLoaded;
 751
 752         return 0;
 753 }
 754
 755 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 756 {
 757         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 758
 759                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 760                 hdsp_write(hdsp, HDSP_fifoData, 0);
 761
 762                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 763                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 764                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 765                 }
 766
 767                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 768                 hdsp_write (hdsp, HDSP_fifoData, 0);
 769                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 770                         goto set_multi;
 771
 772                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 773                 hdsp_write(hdsp, HDSP_fifoData, 0);
 774                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 775                         hdsp->io_type = Digiface;
 776                         dev_info(hdsp->card->dev, "Digiface found\n");
 777                         return 0;
 778                 }
 779
 780                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 781                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 782                 hdsp_write(hdsp, HDSP_fifoData, 0);
 783                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 784                         goto set_multi;
 785
 786                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 787                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 788                 hdsp_write(hdsp, HDSP_fifoData, 0);
 789                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 790                         goto set_multi;
 791
 792                 hdsp->io_type = RPM;
 793                 dev_info(hdsp->card->dev, "RPM found\n");
 794                 return 0;
 795         } else {
 796                 /* firmware was already loaded, get iobox type */
 797                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 798                         hdsp->io_type = RPM;
 799                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 800                         hdsp->io_type = Multiface;
 801                 else
 802                         hdsp->io_type = Digiface;
 803         }
 804         return 0;
 805
 806 set_multi:
 807         hdsp->io_type = Multiface;
 808         dev_info(hdsp->card->dev, "Multiface found\n");
 809         return 0;
 810 }
 811
 812
 813 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 814
 815 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 816 {
 817         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 818                 return 0;
 819         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 820                 hdsp->state &= ~HDSP_FirmwareLoaded;
 821                 if (! load_on_demand)
 822                         return -EIO;
 823                 dev_err(hdsp->card->dev, "firmware not present.\n");
 824                 /* try to load firmware */
 825                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 826                         if (! hdsp_request_fw_loader(hdsp))
 827                                 return 0;
 828                         dev_err(hdsp->card->dev,
 829                                    "No firmware loaded nor cached, please upload firmware.\n");
 830                         return -EIO;
 831                 }
 832                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 833                         dev_err(hdsp->card->dev,
 834                                    "Firmware loading from cache failed, please upload manually.\n");
 835                         return -EIO;
 836                 }
 837         }
 838         return 0;
 839 }
 840
 841
 842 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 843 {
 844         int i;
 845
 846         /* the fifoStatus registers reports on how many words
 847            are available in the command FIFO.
 848         */
 849
 850         for (i = 0; i < timeout; i++) {
 851
 852                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 853                         return 0;
 854
 855                 /* not very friendly, but we only do this during a firmware
 856                    load and changing the mixer, so we just put up with it.
 857                 */
 858
 859                 udelay (100);
 860         }
 861
 862         dev_warn(hdsp->card->dev,
 863                  "wait for FIFO status <= %d failed after %d iterations\n",
 864                     count, timeout);
 865         return -1;
 866 }
 867
 868 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 869 {
 870         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 871                 return 0;
 872
 873         return hdsp->mixer_matrix[addr];
 874 }
 875
 876 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 877 {
 878         unsigned int ad;
 879
 880         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 881                 return -1;
 882
 883         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 884
 885                 /* from martin bjornsen:
 886
 887                    "You can only write dwords to the
 888                    mixer memory which contain two
 889                    mixer values in the low and high
 890                    word. So if you want to change
 891                    value 0 you have to read value 1
 892                    from the cache and write both to
 893                    the first dword in the mixer
 894                    memory."
 895                 */
 896
 897                 if (hdsp->io_type == H9632 && addr >= 512)
 898                         return 0;
 899
 900                 if (hdsp->io_type == H9652 && addr >= 1352)
 901                         return 0;
 902
 903                 hdsp->mixer_matrix[addr] = data;
 904
 905
 906                 /* `addr' addresses a 16-bit wide address, but
 907                    the address space accessed via hdsp_write
 908                    uses byte offsets. put another way, addr
 909                    varies from 0 to 1351, but to access the
 910                    corresponding memory location, we need
 911                    to access 0 to 2703 ...
 912                 */
 913                 ad = addr/2;
 914
 915                 hdsp_write (hdsp, 4096 + (ad*4),
 916                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 917                             hdsp->mixer_matrix[addr&0x7fe]);
 918
 919                 return 0;
 920
 921         } else {
 922
 923                 ad = (addr << 16) + data;
 924
 925                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 926                         return -1;
 927
 928                 hdsp_write (hdsp, HDSP_fifoData, ad);
 929                 hdsp->mixer_matrix[addr] = data;
 930
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 937 {
 938         unsigned long flags;
 939         int ret = 1;
 940
 941         spin_lock_irqsave(&hdsp->lock, flags);
 942         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 943             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 944                 ret = 0;
 945         spin_unlock_irqrestore(&hdsp->lock, flags);
 946         return ret;
 947 }
 948
 949 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 950 {
 951         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 952         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 953
 954         /* For the 9632, the mask is different */
 955         if (hdsp->io_type == H9632)
 956                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 957
 958         if (status & HDSP_SPDIFErrorFlag)
 959                 return 0;
 960
 961         switch (rate_bits) {
 962         case HDSP_spdifFrequency32KHz: return 32000;
 963         case HDSP_spdifFrequency44_1KHz: return 44100;
 964         case HDSP_spdifFrequency48KHz: return 48000;
 965         case HDSP_spdifFrequency64KHz: return 64000;
 966         case HDSP_spdifFrequency88_2KHz: return 88200;
 967         case HDSP_spdifFrequency96KHz: return 96000;
 968         case HDSP_spdifFrequency128KHz:
 969                 if (hdsp->io_type == H9632) return 128000;
 970                 break;
 971         case HDSP_spdifFrequency176_4KHz:
 972                 if (hdsp->io_type == H9632) return 176400;
 973                 break;
 974         case HDSP_spdifFrequency192KHz:
 975                 if (hdsp->io_type == H9632) return 192000;
 976                 break;
 977         default:
 978                 break;
 979         }
 980         dev_warn(hdsp->card->dev,
 981                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
 982                  rate_bits, status);
 983         return 0;
 984 }
 985
 986 static int hdsp_external_sample_rate(struct hdsp *hdsp)
 987 {
 988         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 989         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 990
 991         /* For the 9632 card, there seems to be no bit for indicating external
 992          * sample rate greater than 96kHz. The card reports the corresponding
 993          * single speed. So the best means seems to get spdif rate when
 994          * autosync reference is spdif */
 995         if (hdsp->io_type == H9632 &&
 996             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
 997                  return hdsp_spdif_sample_rate(hdsp);
 998
 999         switch (rate_bits) {
1000         case HDSP_systemFrequency32:   return 32000;
1001         case HDSP_systemFrequency44_1: return 44100;
1002         case HDSP_systemFrequency48:   return 48000;
1003         case HDSP_systemFrequency64:   return 64000;
1004         case HDSP_systemFrequency88_2: return 88200;
1005         case HDSP_systemFrequency96:   return 96000;
1006         default:
1007                 return 0;
1008         }
1009 }
1010
1011 static void hdsp_compute_period_size(struct hdsp *hdsp)
1012 {
1013         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1014 }
1015
1016 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1017 {
1018         int position;
1019
1020         position = hdsp_read(hdsp, HDSP_statusRegister);
1021
1022         if (!hdsp->precise_ptr)
1023                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1024
1025         position &= HDSP_BufferPositionMask;
1026         position /= 4;
1027         position &= (hdsp->period_bytes/2) - 1;
1028         return position;
1029 }
1030
1031 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1032 {
1033         hdsp_write (hdsp, HDSP_resetPointer, 0);
1034         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1035                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1036                  * requires (?) to write again DDS value after a reset pointer
1037                  * (at least, it works like this) */
1038                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1039 }
1040
1041 static void hdsp_start_audio(struct hdsp *s)
1042 {
1043         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1044         hdsp_write(s, HDSP_controlRegister, s->control_register);
1045 }
1046
1047 static void hdsp_stop_audio(struct hdsp *s)
1048 {
1049         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1050         hdsp_write(s, HDSP_controlRegister, s->control_register);
1051 }
1052
1053 static void hdsp_silence_playback(struct hdsp *hdsp)
1054 {
1055         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1056 }
1057
1058 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1059 {
1060         int n;
1061
1062         spin_lock_irq(&s->lock);
1063
1064         frames >>= 7;
1065         n = 0;
1066         while (frames) {
1067                 n++;
1068                 frames >>= 1;
1069         }
1070
1071         s->control_register &= ~HDSP_LatencyMask;
1072         s->control_register |= hdsp_encode_latency(n);
1073
1074         hdsp_write(s, HDSP_controlRegister, s->control_register);
1075
1076         hdsp_compute_period_size(s);
1077
1078         spin_unlock_irq(&s->lock);
1079
1080         return 0;
1081 }
1082
1083 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1084 {
1085         u64 n;
1086
1087         if (rate >= 112000)
1088                 rate /= 4;
1089         else if (rate >= 56000)
1090                 rate /= 2;
1091
1092         n = DDS_NUMERATOR;
1093         n = div_u64(n, rate);
1094         /* n should be less than 2^32 for being written to FREQ register */
1095         snd_BUG_ON(n >> 32);
1096         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1097            value to write it after a reset */
1098         hdsp->dds_value = n;
1099         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1100 }
1101
1102 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1103 {
1104         int reject_if_open = 0;
1105         int current_rate;
1106         int rate_bits;
1107
1108         /* ASSUMPTION: hdsp->lock is either held, or
1109            there is no need for it (e.g. during module
1110            initialization).
1111         */
1112
1113         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1114                 if (called_internally) {
1115                         /* request from ctl or card initialization */
1116                         dev_err(hdsp->card->dev,
1117                                 "device is not running as a clock master: cannot set sample rate.\n");
1118                         return -1;
1119                 } else {
1120                         /* hw_param request while in AutoSync mode */
1121                         int external_freq = hdsp_external_sample_rate(hdsp);
1122                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1123
1124                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1125                                 dev_info(hdsp->card->dev,
1126                                          "Detected ADAT in double speed mode\n");
1127                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1128                                 dev_info(hdsp->card->dev,
1129                                          "Detected ADAT in quad speed mode\n");
1130                         else if (rate != external_freq) {
1131                                 dev_info(hdsp->card->dev,
1132                                          "No AutoSync source for requested rate\n");
1133                                 return -1;
1134                         }
1135                 }
1136         }
1137
1138         current_rate = hdsp->system_sample_rate;
1139
1140         /* Changing from a "single speed" to a "double speed" rate is
1141            not allowed if any substreams are open. This is because
1142            such a change causes a shift in the location of
1143            the DMA buffers and a reduction in the number of available
1144            buffers.
1145
1146            Note that a similar but essentially insoluble problem
1147            exists for externally-driven rate changes. All we can do
1148            is to flag rate changes in the read/write routines.  */
1149
1150         if (rate > 96000 && hdsp->io_type != H9632)
1151                 return -EINVAL;
1152
1153         switch (rate) {
1154         case 32000:
1155                 if (current_rate > 48000)
1156                         reject_if_open = 1;
1157                 rate_bits = HDSP_Frequency32KHz;
1158                 break;
1159         case 44100:
1160                 if (current_rate > 48000)
1161                         reject_if_open = 1;
1162                 rate_bits = HDSP_Frequency44_1KHz;
1163                 break;
1164         case 48000:
1165                 if (current_rate > 48000)
1166                         reject_if_open = 1;
1167                 rate_bits = HDSP_Frequency48KHz;
1168                 break;
1169         case 64000:
1170                 if (current_rate <= 48000 || current_rate > 96000)
1171                         reject_if_open = 1;
1172                 rate_bits = HDSP_Frequency64KHz;
1173                 break;
1174         case 88200:
1175                 if (current_rate <= 48000 || current_rate > 96000)
1176                         reject_if_open = 1;
1177                 rate_bits = HDSP_Frequency88_2KHz;
1178                 break;
1179         case 96000:
1180                 if (current_rate <= 48000 || current_rate > 96000)
1181                         reject_if_open = 1;
1182                 rate_bits = HDSP_Frequency96KHz;
1183                 break;
1184         case 128000:
1185                 if (current_rate < 128000)
1186                         reject_if_open = 1;
1187                 rate_bits = HDSP_Frequency128KHz;
1188                 break;
1189         case 176400:
1190                 if (current_rate < 128000)
1191                         reject_if_open = 1;
1192                 rate_bits = HDSP_Frequency176_4KHz;
1193                 break;
1194         case 192000:
1195                 if (current_rate < 128000)
1196                         reject_if_open = 1;
1197                 rate_bits = HDSP_Frequency192KHz;
1198                 break;
1199         default:
1200                 return -EINVAL;
1201         }
1202
1203         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1204                 dev_warn(hdsp->card->dev,
1205                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1206                             hdsp->capture_pid,
1207                             hdsp->playback_pid);
1208                 return -EBUSY;
1209         }
1210
1211         hdsp->control_register &= ~HDSP_FrequencyMask;
1212         hdsp->control_register |= rate_bits;
1213         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1214
1215         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1216         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1217                 hdsp_set_dds_value(hdsp, rate);
1218
1219         if (rate >= 128000) {
1220                 hdsp->channel_map = channel_map_H9632_qs;
1221         } else if (rate > 48000) {
1222                 if (hdsp->io_type == H9632)
1223                         hdsp->channel_map = channel_map_H9632_ds;
1224                 else
1225                         hdsp->channel_map = channel_map_ds;
1226         } else {
1227                 switch (hdsp->io_type) {
1228                 case RPM:
1229                 case Multiface:
1230                         hdsp->channel_map = channel_map_mf_ss;
1231                         break;
1232                 case Digiface:
1233                 case H9652:
1234                         hdsp->channel_map = channel_map_df_ss;
1235                         break;
1236                 case H9632:
1237                         hdsp->channel_map = channel_map_H9632_ss;
1238                         break;
1239                 default:
1240                         /* should never happen */
1241                         break;
1242                 }
1243         }
1244
1245         hdsp->system_sample_rate = rate;
1246
1247         return 0;
1248 }
1249
1250 /*----------------------------------------------------------------------------
1251    MIDI
1252   ----------------------------------------------------------------------------*/
1253
1254 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1255 {
1256         /* the hardware already does the relevant bit-mask with 0xff */
1257         if (id)
1258                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1259         else
1260                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1261 }
1262
1263 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1264 {
1265         /* the hardware already does the relevant bit-mask with 0xff */
1266         if (id)
1267                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1268         else
1269                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1270 }
1271
1272 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1273 {
1274         if (id)
1275                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1276         else
1277                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1278 }
1279
1280 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1281 {
1282         int fifo_bytes_used;
1283
1284         if (id)
1285                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1286         else
1287                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1288
1289         if (fifo_bytes_used < 128)
1290                 return  128 - fifo_bytes_used;
1291         else
1292                 return 0;
1293 }
1294
1295 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1296 {
1297         while (snd_hdsp_midi_input_available (hdsp, id))
1298                 snd_hdsp_midi_read_byte (hdsp, id);
1299 }
1300
1301 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1302 {
1303         unsigned long flags;
1304         int n_pending;
1305         int to_write;
1306         int i;
1307         unsigned char buf[128];
1308
1309         /* Output is not interrupt driven */
1310
1311         spin_lock_irqsave (&hmidi->lock, flags);
1312         if (hmidi->output) {
1313                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1314                         n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
1315                         if (n_pending > 0) {
1316                                 if (n_pending > (int)sizeof (buf))
1317                                         n_pending = sizeof (buf);
1318
1319                                 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
1320                                 if (to_write > 0) {
1321                                         for (i = 0; i < to_write; ++i)
1322                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1323                                 }
1324                         }
1325                 }
1326         }
1327         spin_unlock_irqrestore (&hmidi->lock, flags);
1328         return 0;
1329 }
1330
1331 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1332 {
1333         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1334         unsigned long flags;
1335         int n_pending;
1336         int i;
1337
1338         spin_lock_irqsave (&hmidi->lock, flags);
1339         n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
1340         if (n_pending > 0) {
1341                 if (hmidi->input) {
1342                         if (n_pending > (int)sizeof (buf))
1343                                 n_pending = sizeof (buf);
1344                         for (i = 0; i < n_pending; ++i)
1345                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1346                         if (n_pending)
1347                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1348                 } else {
1349                         /* flush the MIDI input FIFO */
1350                         while (--n_pending)
1351                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1352                 }
1353         }
1354         hmidi->pending = 0;
1355         if (hmidi->id)
1356                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1357         else
1358                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1359         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1360         spin_unlock_irqrestore (&hmidi->lock, flags);
1361         return snd_hdsp_midi_output_write (hmidi);
1362 }
1363
1364 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1365 {
1366         struct hdsp *hdsp;
1367         struct hdsp_midi *hmidi;
1368         unsigned long flags;
1369         u32 ie;
1370
1371         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1372         hdsp = hmidi->hdsp;
1373         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1374         spin_lock_irqsave (&hdsp->lock, flags);
1375         if (up) {
1376                 if (!(hdsp->control_register & ie)) {
1377                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1378                         hdsp->control_register |= ie;
1379                 }
1380         } else {
1381                 hdsp->control_register &= ~ie;
1382         }
1383
1384         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1385         spin_unlock_irqrestore (&hdsp->lock, flags);
1386 }
1387
1388 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1389 {
1390         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1391         unsigned long flags;
1392
1393         snd_hdsp_midi_output_write(hmidi);
1394         spin_lock_irqsave (&hmidi->lock, flags);
1395
1396         /* this does not bump hmidi->istimer, because the
1397            kernel automatically removed the timer when it
1398            expired, and we are now adding it back, thus
1399            leaving istimer wherever it was set before.
1400         */
1401
1402         if (hmidi->istimer)
1403                 mod_timer(&hmidi->timer, 1 + jiffies);
1404
1405         spin_unlock_irqrestore (&hmidi->lock, flags);
1406 }
1407
1408 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1409 {
1410         struct hdsp_midi *hmidi;
1411         unsigned long flags;
1412
1413         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1414         spin_lock_irqsave (&hmidi->lock, flags);
1415         if (up) {
1416                 if (!hmidi->istimer) {
1417                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1418                                     0);
1419                         mod_timer(&hmidi->timer, 1 + jiffies);
1420                         hmidi->istimer++;
1421                 }
1422         } else {
1423                 if (hmidi->istimer && --hmidi->istimer <= 0)
1424                         del_timer (&hmidi->timer);
1425         }
1426         spin_unlock_irqrestore (&hmidi->lock, flags);
1427         if (up)
1428                 snd_hdsp_midi_output_write(hmidi);
1429 }
1430
1431 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1432 {
1433         struct hdsp_midi *hmidi;
1434
1435         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1436         spin_lock_irq (&hmidi->lock);
1437         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1438         hmidi->input = substream;
1439         spin_unlock_irq (&hmidi->lock);
1440
1441         return 0;
1442 }
1443
1444 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1445 {
1446         struct hdsp_midi *hmidi;
1447
1448         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1449         spin_lock_irq (&hmidi->lock);
1450         hmidi->output = substream;
1451         spin_unlock_irq (&hmidi->lock);
1452
1453         return 0;
1454 }
1455
1456 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1457 {
1458         struct hdsp_midi *hmidi;
1459
1460         snd_hdsp_midi_input_trigger (substream, 0);
1461
1462         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1463         spin_lock_irq (&hmidi->lock);
1464         hmidi->input = NULL;
1465         spin_unlock_irq (&hmidi->lock);
1466
1467         return 0;
1468 }
1469
1470 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1471 {
1472         struct hdsp_midi *hmidi;
1473
1474         snd_hdsp_midi_output_trigger (substream, 0);
1475
1476         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1477         spin_lock_irq (&hmidi->lock);
1478         hmidi->output = NULL;
1479         spin_unlock_irq (&hmidi->lock);
1480
1481         return 0;
1482 }
1483
1484 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1485 {
1486         .open =         snd_hdsp_midi_output_open,
1487         .close =        snd_hdsp_midi_output_close,
1488         .trigger =      snd_hdsp_midi_output_trigger,
1489 };
1490
1491 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1492 {
1493         .open =         snd_hdsp_midi_input_open,
1494         .close =        snd_hdsp_midi_input_close,
1495         .trigger =      snd_hdsp_midi_input_trigger,
1496 };
1497
1498 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1499 {
1500         char buf[40];
1501
1502         hdsp->midi[id].id = id;
1503         hdsp->midi[id].rmidi = NULL;
1504         hdsp->midi[id].input = NULL;
1505         hdsp->midi[id].output = NULL;
1506         hdsp->midi[id].hdsp = hdsp;
1507         hdsp->midi[id].istimer = 0;
1508         hdsp->midi[id].pending = 0;
1509         spin_lock_init (&hdsp->midi[id].lock);
1510
1511         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1512         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1513                 return -1;
1514
1515         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1516         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1517
1518         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1519         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1520
1521         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1522                 SNDRV_RAWMIDI_INFO_INPUT |
1523                 SNDRV_RAWMIDI_INFO_DUPLEX;
1524
1525         return 0;
1526 }
1527
1528 /*-----------------------------------------------------------------------------
1529   Control Interface
1530   ----------------------------------------------------------------------------*/
1531
1532 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1533 {
1534         u32 val = 0;
1535         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1536         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1537         if (val & HDSP_SPDIFProfessional)
1538                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1539         else
1540                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1541         return val;
1542 }
1543
1544 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1545 {
1546         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1547                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1548         if (val & HDSP_SPDIFProfessional)
1549                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1550         else
1551                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1552 }
1553
1554 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1555 {
1556         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1557         uinfo->count = 1;
1558         return 0;
1559 }
1560
1561 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1562 {
1563         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1564
1565         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1566         return 0;
1567 }
1568
1569 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1570 {
1571         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1572         int change;
1573         u32 val;
1574
1575         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1576         spin_lock_irq(&hdsp->lock);
1577         change = val != hdsp->creg_spdif;
1578         hdsp->creg_spdif = val;
1579         spin_unlock_irq(&hdsp->lock);
1580         return change;
1581 }
1582
1583 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1584 {
1585         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1586         uinfo->count = 1;
1587         return 0;
1588 }
1589
1590 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1591 {
1592         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1593
1594         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1595         return 0;
1596 }
1597
1598 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1599 {
1600         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601         int change;
1602         u32 val;
1603
1604         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1605         spin_lock_irq(&hdsp->lock);
1606         change = val != hdsp->creg_spdif_stream;
1607         hdsp->creg_spdif_stream = val;
1608         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1609         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1610         spin_unlock_irq(&hdsp->lock);
1611         return change;
1612 }
1613
1614 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1615 {
1616         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1617         uinfo->count = 1;
1618         return 0;
1619 }
1620
1621 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1622 {
1623         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1624         return 0;
1625 }
1626
1627 #define HDSP_SPDIF_IN(xname, xindex) \
1628 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1629   .name = xname, \
1630   .index = xindex, \
1631   .info = snd_hdsp_info_spdif_in, \
1632   .get = snd_hdsp_get_spdif_in, \
1633   .put = snd_hdsp_put_spdif_in }
1634
1635 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1636 {
1637         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1638 }
1639
1640 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1641 {
1642         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1643         hdsp->control_register |= hdsp_encode_spdif_in(in);
1644         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1645         return 0;
1646 }
1647
1648 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1649 {
1650         static const char * const texts[4] = {
1651                 "Optical", "Coaxial", "Internal", "AES"
1652         };
1653         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1654
1655         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1656                                  texts);
1657 }
1658
1659 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1660 {
1661         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1662
1663         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1664         return 0;
1665 }
1666
1667 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1668 {
1669         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1670         int change;
1671         unsigned int val;
1672
1673         if (!snd_hdsp_use_is_exclusive(hdsp))
1674                 return -EBUSY;
1675         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1676         spin_lock_irq(&hdsp->lock);
1677         change = val != hdsp_spdif_in(hdsp);
1678         if (change)
1679                 hdsp_set_spdif_input(hdsp, val);
1680         spin_unlock_irq(&hdsp->lock);
1681         return change;
1682 }
1683
1684 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1685 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1686         .name = xname, \
1687         .private_value = xindex, \
1688         .info = snd_hdsp_info_toggle_setting, \
1689         .get = snd_hdsp_get_toggle_setting, \
1690         .put = snd_hdsp_put_toggle_setting \
1691 }
1692
1693 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1694 {
1695         return (hdsp->control_register & regmask) ? 1 : 0;
1696 }
1697
1698 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1699 {
1700         if (out)
1701                 hdsp->control_register |= regmask;
1702         else
1703                 hdsp->control_register &= ~regmask;
1704         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1705
1706         return 0;
1707 }
1708
1709 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1710
1711 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1712                 struct snd_ctl_elem_value *ucontrol)
1713 {
1714         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1715         u32 regmask = kcontrol->private_value;
1716
1717         spin_lock_irq(&hdsp->lock);
1718         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1719         spin_unlock_irq(&hdsp->lock);
1720         return 0;
1721 }
1722
1723 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1724                 struct snd_ctl_elem_value *ucontrol)
1725 {
1726         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1727         u32 regmask = kcontrol->private_value;
1728         int change;
1729         unsigned int val;
1730
1731         if (!snd_hdsp_use_is_exclusive(hdsp))
1732                 return -EBUSY;
1733         val = ucontrol->value.integer.value[0] & 1;
1734         spin_lock_irq(&hdsp->lock);
1735         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1736         if (change)
1737                 hdsp_set_toggle_setting(hdsp, regmask, val);
1738         spin_unlock_irq(&hdsp->lock);
1739         return change;
1740 }
1741
1742 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1743 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1744   .name = xname, \
1745   .index = xindex, \
1746   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1747   .info = snd_hdsp_info_spdif_sample_rate, \
1748   .get = snd_hdsp_get_spdif_sample_rate \
1749 }
1750
1751 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1752 {
1753         static const char * const texts[] = {
1754                 "32000", "44100", "48000", "64000", "88200", "96000",
1755                 "None", "128000", "176400", "192000"
1756         };
1757         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1758
1759         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1760                                  texts);
1761 }
1762
1763 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1764 {
1765         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1766
1767         switch (hdsp_spdif_sample_rate(hdsp)) {
1768         case 32000:
1769                 ucontrol->value.enumerated.item[0] = 0;
1770                 break;
1771         case 44100:
1772                 ucontrol->value.enumerated.item[0] = 1;
1773                 break;
1774         case 48000:
1775                 ucontrol->value.enumerated.item[0] = 2;
1776                 break;
1777         case 64000:
1778                 ucontrol->value.enumerated.item[0] = 3;
1779                 break;
1780         case 88200:
1781                 ucontrol->value.enumerated.item[0] = 4;
1782                 break;
1783         case 96000:
1784                 ucontrol->value.enumerated.item[0] = 5;
1785                 break;
1786         case 128000:
1787                 ucontrol->value.enumerated.item[0] = 7;
1788                 break;
1789         case 176400:
1790                 ucontrol->value.enumerated.item[0] = 8;
1791                 break;
1792         case 192000:
1793                 ucontrol->value.enumerated.item[0] = 9;
1794                 break;
1795         default:
1796                 ucontrol->value.enumerated.item[0] = 6;
1797         }
1798         return 0;
1799 }
1800
1801 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1802 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1803   .name = xname, \
1804   .index = xindex, \
1805   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1806   .info = snd_hdsp_info_system_sample_rate, \
1807   .get = snd_hdsp_get_system_sample_rate \
1808 }
1809
1810 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1811 {
1812         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1813         uinfo->count = 1;
1814         return 0;
1815 }
1816
1817 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1818 {
1819         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1820
1821         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1822         return 0;
1823 }
1824
1825 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1826 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1827   .name = xname, \
1828   .index = xindex, \
1829   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1830   .info = snd_hdsp_info_autosync_sample_rate, \
1831   .get = snd_hdsp_get_autosync_sample_rate \
1832 }
1833
1834 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1835 {
1836         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1837         static const char * const texts[] = {
1838                 "32000", "44100", "48000", "64000", "88200", "96000",
1839                 "None", "128000", "176400", "192000"
1840         };
1841
1842         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1843                                  texts);
1844 }
1845
1846 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1847 {
1848         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1849
1850         switch (hdsp_external_sample_rate(hdsp)) {
1851         case 32000:
1852                 ucontrol->value.enumerated.item[0] = 0;
1853                 break;
1854         case 44100:
1855                 ucontrol->value.enumerated.item[0] = 1;
1856                 break;
1857         case 48000:
1858                 ucontrol->value.enumerated.item[0] = 2;
1859                 break;
1860         case 64000:
1861                 ucontrol->value.enumerated.item[0] = 3;
1862                 break;
1863         case 88200:
1864                 ucontrol->value.enumerated.item[0] = 4;
1865                 break;
1866         case 96000:
1867                 ucontrol->value.enumerated.item[0] = 5;
1868                 break;
1869         case 128000:
1870                 ucontrol->value.enumerated.item[0] = 7;
1871                 break;
1872         case 176400:
1873                 ucontrol->value.enumerated.item[0] = 8;
1874                 break;
1875         case 192000:
1876                 ucontrol->value.enumerated.item[0] = 9;
1877                 break;
1878         default:
1879                 ucontrol->value.enumerated.item[0] = 6;
1880         }
1881         return 0;
1882 }
1883
1884 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1885 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1886   .name = xname, \
1887   .index = xindex, \
1888   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1889   .info = snd_hdsp_info_system_clock_mode, \
1890   .get = snd_hdsp_get_system_clock_mode \
1891 }
1892
1893 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1894 {
1895         if (hdsp->control_register & HDSP_ClockModeMaster)
1896                 return 0;
1897         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1898                         return 0;
1899         return 1;
1900 }
1901
1902 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1903 {
1904         static const char * const texts[] = {"Master", "Slave" };
1905
1906         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1907 }
1908
1909 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1910 {
1911         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1912
1913         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1914         return 0;
1915 }
1916
1917 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1918 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1919   .name = xname, \
1920   .index = xindex, \
1921   .info = snd_hdsp_info_clock_source, \
1922   .get = snd_hdsp_get_clock_source, \
1923   .put = snd_hdsp_put_clock_source \
1924 }
1925
1926 static int hdsp_clock_source(struct hdsp *hdsp)
1927 {
1928         if (hdsp->control_register & HDSP_ClockModeMaster) {
1929                 switch (hdsp->system_sample_rate) {
1930                 case 32000:
1931                         return 1;
1932                 case 44100:
1933                         return 2;
1934                 case 48000:
1935                         return 3;
1936                 case 64000:
1937                         return 4;
1938                 case 88200:
1939                         return 5;
1940                 case 96000:
1941                         return 6;
1942                 case 128000:
1943                         return 7;
1944                 case 176400:
1945                         return 8;
1946                 case 192000:
1947                         return 9;
1948                 default:
1949                         return 3;
1950                 }
1951         } else {
1952                 return 0;
1953         }
1954 }
1955
1956 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1957 {
1958         int rate;
1959         switch (mode) {
1960         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1961                 if (hdsp_external_sample_rate(hdsp) != 0) {
1962                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1963                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1964                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1965                         return 0;
1966                     }
1967                 }
1968                 return -1;
1969         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1970                 rate = 32000;
1971                 break;
1972         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1973                 rate = 44100;
1974                 break;
1975         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1976                 rate = 48000;
1977                 break;
1978         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1979                 rate = 64000;
1980                 break;
1981         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1982                 rate = 88200;
1983                 break;
1984         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1985                 rate = 96000;
1986                 break;
1987         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1988                 rate = 128000;
1989                 break;
1990         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1991                 rate = 176400;
1992                 break;
1993         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
1994                 rate = 192000;
1995                 break;
1996         default:
1997                 rate = 48000;
1998         }
1999         hdsp->control_register |= HDSP_ClockModeMaster;
2000         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2001         hdsp_set_rate(hdsp, rate, 1);
2002         return 0;
2003 }
2004
2005 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2006 {
2007         static const char * const texts[] = {
2008                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2009                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2010                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2011                 "Internal 192.0 KHz"
2012         };
2013         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2014
2015         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2016                                  texts);
2017 }
2018
2019 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2020 {
2021         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2022
2023         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2024         return 0;
2025 }
2026
2027 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2028 {
2029         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2030         int change;
2031         int val;
2032
2033         if (!snd_hdsp_use_is_exclusive(hdsp))
2034                 return -EBUSY;
2035         val = ucontrol->value.enumerated.item[0];
2036         if (val < 0) val = 0;
2037         if (hdsp->io_type == H9632) {
2038                 if (val > 9)
2039                         val = 9;
2040         } else {
2041                 if (val > 6)
2042                         val = 6;
2043         }
2044         spin_lock_irq(&hdsp->lock);
2045         if (val != hdsp_clock_source(hdsp))
2046                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2047         else
2048                 change = 0;
2049         spin_unlock_irq(&hdsp->lock);
2050         return change;
2051 }
2052
2053 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2054
2055 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2056 {
2057         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2058
2059         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2060         return 0;
2061 }
2062
2063 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2064 {
2065         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2066         int change;
2067
2068         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2069         if (change)
2070                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2071         return change;
2072 }
2073
2074 #define HDSP_DA_GAIN(xname, xindex) \
2075 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2076   .name = xname, \
2077   .index = xindex, \
2078   .info = snd_hdsp_info_da_gain, \
2079   .get = snd_hdsp_get_da_gain, \
2080   .put = snd_hdsp_put_da_gain \
2081 }
2082
2083 static int hdsp_da_gain(struct hdsp *hdsp)
2084 {
2085         switch (hdsp->control_register & HDSP_DAGainMask) {
2086         case HDSP_DAGainHighGain:
2087                 return 0;
2088         case HDSP_DAGainPlus4dBu:
2089                 return 1;
2090         case HDSP_DAGainMinus10dBV:
2091                 return 2;
2092         default:
2093                 return 1;
2094         }
2095 }
2096
2097 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2098 {
2099         hdsp->control_register &= ~HDSP_DAGainMask;
2100         switch (mode) {
2101         case 0:
2102                 hdsp->control_register |= HDSP_DAGainHighGain;
2103                 break;
2104         case 1:
2105                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2106                 break;
2107         case 2:
2108                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2109                 break;
2110         default:
2111                 return -1;
2112
2113         }
2114         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2115         return 0;
2116 }
2117
2118 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2119 {
2120         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2121
2122         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2123 }
2124
2125 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2126 {
2127         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2128
2129         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2130         return 0;
2131 }
2132
2133 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2134 {
2135         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2136         int change;
2137         int val;
2138
2139         if (!snd_hdsp_use_is_exclusive(hdsp))
2140                 return -EBUSY;
2141         val = ucontrol->value.enumerated.item[0];
2142         if (val < 0) val = 0;
2143         if (val > 2) val = 2;
2144         spin_lock_irq(&hdsp->lock);
2145         if (val != hdsp_da_gain(hdsp))
2146                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2147         else
2148                 change = 0;
2149         spin_unlock_irq(&hdsp->lock);
2150         return change;
2151 }
2152
2153 #define HDSP_AD_GAIN(xname, xindex) \
2154 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2155   .name = xname, \
2156   .index = xindex, \
2157   .info = snd_hdsp_info_ad_gain, \
2158   .get = snd_hdsp_get_ad_gain, \
2159   .put = snd_hdsp_put_ad_gain \
2160 }
2161
2162 static int hdsp_ad_gain(struct hdsp *hdsp)
2163 {
2164         switch (hdsp->control_register & HDSP_ADGainMask) {
2165         case HDSP_ADGainMinus10dBV:
2166                 return 0;
2167         case HDSP_ADGainPlus4dBu:
2168                 return 1;
2169         case HDSP_ADGainLowGain:
2170                 return 2;
2171         default:
2172                 return 1;
2173         }
2174 }
2175
2176 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2177 {
2178         hdsp->control_register &= ~HDSP_ADGainMask;
2179         switch (mode) {
2180         case 0:
2181                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2182                 break;
2183         case 1:
2184                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2185                 break;
2186         case 2:
2187                 hdsp->control_register |= HDSP_ADGainLowGain;
2188                 break;
2189         default:
2190                 return -1;
2191
2192         }
2193         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2194         return 0;
2195 }
2196
2197 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2198 {
2199         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2200
2201         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2202 }
2203
2204 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2205 {
2206         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2207
2208         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2209         return 0;
2210 }
2211
2212 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2213 {
2214         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2215         int change;
2216         int val;
2217
2218         if (!snd_hdsp_use_is_exclusive(hdsp))
2219                 return -EBUSY;
2220         val = ucontrol->value.enumerated.item[0];
2221         if (val < 0) val = 0;
2222         if (val > 2) val = 2;
2223         spin_lock_irq(&hdsp->lock);
2224         if (val != hdsp_ad_gain(hdsp))
2225                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2226         else
2227                 change = 0;
2228         spin_unlock_irq(&hdsp->lock);
2229         return change;
2230 }
2231
2232 #define HDSP_PHONE_GAIN(xname, xindex) \
2233 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2234   .name = xname, \
2235   .index = xindex, \
2236   .info = snd_hdsp_info_phone_gain, \
2237   .get = snd_hdsp_get_phone_gain, \
2238   .put = snd_hdsp_put_phone_gain \
2239 }
2240
2241 static int hdsp_phone_gain(struct hdsp *hdsp)
2242 {
2243         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2244         case HDSP_PhoneGain0dB:
2245                 return 0;
2246         case HDSP_PhoneGainMinus6dB:
2247                 return 1;
2248         case HDSP_PhoneGainMinus12dB:
2249                 return 2;
2250         default:
2251                 return 0;
2252         }
2253 }
2254
2255 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2256 {
2257         hdsp->control_register &= ~HDSP_PhoneGainMask;
2258         switch (mode) {
2259         case 0:
2260                 hdsp->control_register |= HDSP_PhoneGain0dB;
2261                 break;
2262         case 1:
2263                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2264                 break;
2265         case 2:
2266                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2267                 break;
2268         default:
2269                 return -1;
2270
2271         }
2272         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2273         return 0;
2274 }
2275
2276 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2277 {
2278         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2279
2280         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2281 }
2282
2283 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2284 {
2285         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2286
2287         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2288         return 0;
2289 }
2290
2291 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2292 {
2293         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2294         int change;
2295         int val;
2296
2297         if (!snd_hdsp_use_is_exclusive(hdsp))
2298                 return -EBUSY;
2299         val = ucontrol->value.enumerated.item[0];
2300         if (val < 0) val = 0;
2301         if (val > 2) val = 2;
2302         spin_lock_irq(&hdsp->lock);
2303         if (val != hdsp_phone_gain(hdsp))
2304                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2305         else
2306                 change = 0;
2307         spin_unlock_irq(&hdsp->lock);
2308         return change;
2309 }
2310
2311 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2312 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2313   .name = xname, \
2314   .index = xindex, \
2315   .info = snd_hdsp_info_pref_sync_ref, \
2316   .get = snd_hdsp_get_pref_sync_ref, \
2317   .put = snd_hdsp_put_pref_sync_ref \
2318 }
2319
2320 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2321 {
2322         /* Notice that this looks at the requested sync source,
2323            not the one actually in use.
2324         */
2325
2326         switch (hdsp->control_register & HDSP_SyncRefMask) {
2327         case HDSP_SyncRef_ADAT1:
2328                 return HDSP_SYNC_FROM_ADAT1;
2329         case HDSP_SyncRef_ADAT2:
2330                 return HDSP_SYNC_FROM_ADAT2;
2331         case HDSP_SyncRef_ADAT3:
2332                 return HDSP_SYNC_FROM_ADAT3;
2333         case HDSP_SyncRef_SPDIF:
2334                 return HDSP_SYNC_FROM_SPDIF;
2335         case HDSP_SyncRef_WORD:
2336                 return HDSP_SYNC_FROM_WORD;
2337         case HDSP_SyncRef_ADAT_SYNC:
2338                 return HDSP_SYNC_FROM_ADAT_SYNC;
2339         default:
2340                 return HDSP_SYNC_FROM_WORD;
2341         }
2342         return 0;
2343 }
2344
2345 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2346 {
2347         hdsp->control_register &= ~HDSP_SyncRefMask;
2348         switch (pref) {
2349         case HDSP_SYNC_FROM_ADAT1:
2350                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2351                 break;
2352         case HDSP_SYNC_FROM_ADAT2:
2353                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2354                 break;
2355         case HDSP_SYNC_FROM_ADAT3:
2356                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2357                 break;
2358         case HDSP_SYNC_FROM_SPDIF:
2359                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2360                 break;
2361         case HDSP_SYNC_FROM_WORD:
2362                 hdsp->control_register |= HDSP_SyncRef_WORD;
2363                 break;
2364         case HDSP_SYNC_FROM_ADAT_SYNC:
2365                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2366                 break;
2367         default:
2368                 return -1;
2369         }
2370         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2371         return 0;
2372 }
2373
2374 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2375 {
2376         static const char * const texts[] = {
2377                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2378         };
2379         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2380         int num_items;
2381
2382         switch (hdsp->io_type) {
2383         case Digiface:
2384         case H9652:
2385                 num_items = 6;
2386                 break;
2387         case Multiface:
2388                 num_items = 4;
2389                 break;
2390         case H9632:
2391                 num_items = 3;
2392                 break;
2393         default:
2394                 return -EINVAL;
2395         }
2396
2397         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2398 }
2399
2400 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2401 {
2402         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2403
2404         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2405         return 0;
2406 }
2407
2408 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2409 {
2410         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2411         int change, max;
2412         unsigned int val;
2413
2414         if (!snd_hdsp_use_is_exclusive(hdsp))
2415                 return -EBUSY;
2416
2417         switch (hdsp->io_type) {
2418         case Digiface:
2419         case H9652:
2420                 max = 6;
2421                 break;
2422         case Multiface:
2423                 max = 4;
2424                 break;
2425         case H9632:
2426                 max = 3;
2427                 break;
2428         default:
2429                 return -EIO;
2430         }
2431
2432         val = ucontrol->value.enumerated.item[0] % max;
2433         spin_lock_irq(&hdsp->lock);
2434         change = (int)val != hdsp_pref_sync_ref(hdsp);
2435         hdsp_set_pref_sync_ref(hdsp, val);
2436         spin_unlock_irq(&hdsp->lock);
2437         return change;
2438 }
2439
2440 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2441 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2442   .name = xname, \
2443   .index = xindex, \
2444   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2445   .info = snd_hdsp_info_autosync_ref, \
2446   .get = snd_hdsp_get_autosync_ref, \
2447 }
2448
2449 static int hdsp_autosync_ref(struct hdsp *hdsp)
2450 {
2451         /* This looks at the autosync selected sync reference */
2452         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2453
2454         switch (status2 & HDSP_SelSyncRefMask) {
2455         case HDSP_SelSyncRef_WORD:
2456                 return HDSP_AUTOSYNC_FROM_WORD;
2457         case HDSP_SelSyncRef_ADAT_SYNC:
2458                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2459         case HDSP_SelSyncRef_SPDIF:
2460                 return HDSP_AUTOSYNC_FROM_SPDIF;
2461         case HDSP_SelSyncRefMask:
2462                 return HDSP_AUTOSYNC_FROM_NONE;
2463         case HDSP_SelSyncRef_ADAT1:
2464                 return HDSP_AUTOSYNC_FROM_ADAT1;
2465         case HDSP_SelSyncRef_ADAT2:
2466                 return HDSP_AUTOSYNC_FROM_ADAT2;
2467         case HDSP_SelSyncRef_ADAT3:
2468                 return HDSP_AUTOSYNC_FROM_ADAT3;
2469         default:
2470                 return HDSP_AUTOSYNC_FROM_WORD;
2471         }
2472         return 0;
2473 }
2474
2475 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2476 {
2477         static const char * const texts[] = {
2478                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2479         };
2480
2481         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2482 }
2483
2484 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2485 {
2486         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2487
2488         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2489         return 0;
2490 }
2491
2492 #define HDSP_PRECISE_POINTER(xname, xindex) \
2493 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2494   .name = xname, \
2495   .index = xindex, \
2496   .info = snd_hdsp_info_precise_pointer, \
2497   .get = snd_hdsp_get_precise_pointer, \
2498   .put = snd_hdsp_put_precise_pointer \
2499 }
2500
2501 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2502 {
2503         if (precise)
2504                 hdsp->precise_ptr = 1;
2505         else
2506                 hdsp->precise_ptr = 0;
2507         return 0;
2508 }
2509
2510 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2511
2512 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2513 {
2514         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2515
2516         spin_lock_irq(&hdsp->lock);
2517         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2518         spin_unlock_irq(&hdsp->lock);
2519         return 0;
2520 }
2521
2522 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2523 {
2524         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2525         int change;
2526         unsigned int val;
2527
2528         if (!snd_hdsp_use_is_exclusive(hdsp))
2529                 return -EBUSY;
2530         val = ucontrol->value.integer.value[0] & 1;
2531         spin_lock_irq(&hdsp->lock);
2532         change = (int)val != hdsp->precise_ptr;
2533         hdsp_set_precise_pointer(hdsp, val);
2534         spin_unlock_irq(&hdsp->lock);
2535         return change;
2536 }
2537
2538 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2539 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2540   .name = xname, \
2541   .index = xindex, \
2542   .info = snd_hdsp_info_use_midi_work, \
2543   .get = snd_hdsp_get_use_midi_work, \
2544   .put = snd_hdsp_put_use_midi_work \
2545 }
2546
2547 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2548 {
2549         if (use_work)
2550                 hdsp->use_midi_work = 1;
2551         else
2552                 hdsp->use_midi_work = 0;
2553         return 0;
2554 }
2555
2556 #define snd_hdsp_info_use_midi_work             snd_ctl_boolean_mono_info
2557
2558 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2559 {
2560         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2561
2562         spin_lock_irq(&hdsp->lock);
2563         ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2564         spin_unlock_irq(&hdsp->lock);
2565         return 0;
2566 }
2567
2568 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2569 {
2570         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2571         int change;
2572         unsigned int val;
2573
2574         if (!snd_hdsp_use_is_exclusive(hdsp))
2575                 return -EBUSY;
2576         val = ucontrol->value.integer.value[0] & 1;
2577         spin_lock_irq(&hdsp->lock);
2578         change = (int)val != hdsp->use_midi_work;
2579         hdsp_set_use_midi_work(hdsp, val);
2580         spin_unlock_irq(&hdsp->lock);
2581         return change;
2582 }
2583
2584 #define HDSP_MIXER(xname, xindex) \
2585 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2586   .name = xname, \
2587   .index = xindex, \
2588   .device = 0, \
2589   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2590                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2591   .info = snd_hdsp_info_mixer, \
2592   .get = snd_hdsp_get_mixer, \
2593   .put = snd_hdsp_put_mixer \
2594 }
2595
2596 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2597 {
2598         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2599         uinfo->count = 3;
2600         uinfo->value.integer.min = 0;
2601         uinfo->value.integer.max = 65536;
2602         uinfo->value.integer.step = 1;
2603         return 0;
2604 }
2605
2606 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2607 {
2608         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2609         int source;
2610         int destination;
2611         int addr;
2612
2613         source = ucontrol->value.integer.value[0];
2614         destination = ucontrol->value.integer.value[1];
2615
2616         if (source >= hdsp->max_channels)
2617                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2618         else
2619                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2620
2621         spin_lock_irq(&hdsp->lock);
2622         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2623         spin_unlock_irq(&hdsp->lock);
2624         return 0;
2625 }
2626
2627 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2628 {
2629         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2630         int change;
2631         int source;
2632         int destination;
2633         int gain;
2634         int addr;
2635
2636         if (!snd_hdsp_use_is_exclusive(hdsp))
2637                 return -EBUSY;
2638
2639         source = ucontrol->value.integer.value[0];
2640         destination = ucontrol->value.integer.value[1];
2641
2642         if (source >= hdsp->max_channels)
2643                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2644         else
2645                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2646
2647         gain = ucontrol->value.integer.value[2];
2648
2649         spin_lock_irq(&hdsp->lock);
2650         change = gain != hdsp_read_gain(hdsp, addr);
2651         if (change)
2652                 hdsp_write_gain(hdsp, addr, gain);
2653         spin_unlock_irq(&hdsp->lock);
2654         return change;
2655 }
2656
2657 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2658 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2659   .name = xname, \
2660   .index = xindex, \
2661   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2662   .info = snd_hdsp_info_sync_check, \
2663   .get = snd_hdsp_get_wc_sync_check \
2664 }
2665
2666 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2667 {
2668         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2669
2670         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2671 }
2672
2673 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2674 {
2675         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2676         if (status2 & HDSP_wc_lock) {
2677                 if (status2 & HDSP_wc_sync)
2678                         return 2;
2679                 else
2680                          return 1;
2681         } else
2682                 return 0;
2683         return 0;
2684 }
2685
2686 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2687 {
2688         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2689
2690         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2691         return 0;
2692 }
2693
2694 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2695 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2696   .name = xname, \
2697   .index = xindex, \
2698   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2699   .info = snd_hdsp_info_sync_check, \
2700   .get = snd_hdsp_get_spdif_sync_check \
2701 }
2702
2703 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2704 {
2705         int status = hdsp_read(hdsp, HDSP_statusRegister);
2706         if (status & HDSP_SPDIFErrorFlag)
2707                 return 0;
2708         else {
2709                 if (status & HDSP_SPDIFSync)
2710                         return 2;
2711                 else
2712                         return 1;
2713         }
2714         return 0;
2715 }
2716
2717 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2718 {
2719         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2720
2721         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2722         return 0;
2723 }
2724
2725 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2726 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2727   .name = xname, \
2728   .index = xindex, \
2729   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2730   .info = snd_hdsp_info_sync_check, \
2731   .get = snd_hdsp_get_adatsync_sync_check \
2732 }
2733
2734 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2735 {
2736         int status = hdsp_read(hdsp, HDSP_statusRegister);
2737         if (status & HDSP_TimecodeLock) {
2738                 if (status & HDSP_TimecodeSync)
2739                         return 2;
2740                 else
2741                         return 1;
2742         } else
2743                 return 0;
2744 }
2745
2746 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2747 {
2748         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2749
2750         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2751         return 0;
2752 }
2753
2754 #define HDSP_ADAT_SYNC_CHECK \
2755 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2756   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2757   .info = snd_hdsp_info_sync_check, \
2758   .get = snd_hdsp_get_adat_sync_check \
2759 }
2760
2761 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2762 {
2763         int status = hdsp_read(hdsp, HDSP_statusRegister);
2764
2765         if (status & (HDSP_Lock0>>idx)) {
2766                 if (status & (HDSP_Sync0>>idx))
2767                         return 2;
2768                 else
2769                         return 1;
2770         } else
2771                 return 0;
2772 }
2773
2774 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2775 {
2776         int offset;
2777         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2778
2779         offset = ucontrol->id.index - 1;
2780         if (snd_BUG_ON(offset < 0))
2781                 return -EINVAL;
2782
2783         switch (hdsp->io_type) {
2784         case Digiface:
2785         case H9652:
2786                 if (offset >= 3)
2787                         return -EINVAL;
2788                 break;
2789         case Multiface:
2790         case H9632:
2791                 if (offset >= 1)
2792                         return -EINVAL;
2793                 break;
2794         default:
2795                 return -EIO;
2796         }
2797
2798         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2799         return 0;
2800 }
2801
2802 #define HDSP_DDS_OFFSET(xname, xindex) \
2803 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2804   .name = xname, \
2805   .index = xindex, \
2806   .info = snd_hdsp_info_dds_offset, \
2807   .get = snd_hdsp_get_dds_offset, \
2808   .put = snd_hdsp_put_dds_offset \
2809 }
2810
2811 static int hdsp_dds_offset(struct hdsp *hdsp)
2812 {
2813         u64 n;
2814         unsigned int dds_value = hdsp->dds_value;
2815         int system_sample_rate = hdsp->system_sample_rate;
2816
2817         if (!dds_value)
2818                 return 0;
2819
2820         n = DDS_NUMERATOR;
2821         /*
2822          * dds_value = n / rate
2823          * rate = n / dds_value
2824          */
2825         n = div_u64(n, dds_value);
2826         if (system_sample_rate >= 112000)
2827                 n *= 4;
2828         else if (system_sample_rate >= 56000)
2829                 n *= 2;
2830         return ((int)n) - system_sample_rate;
2831 }
2832
2833 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2834 {
2835         int rate = hdsp->system_sample_rate + offset_hz;
2836         hdsp_set_dds_value(hdsp, rate);
2837         return 0;
2838 }
2839
2840 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2841 {
2842         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2843         uinfo->count = 1;
2844         uinfo->value.integer.min = -5000;
2845         uinfo->value.integer.max = 5000;
2846         return 0;
2847 }
2848
2849 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2850 {
2851         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2852
2853         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2854         return 0;
2855 }
2856
2857 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2858 {
2859         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2860         int change;
2861         int val;
2862
2863         if (!snd_hdsp_use_is_exclusive(hdsp))
2864                 return -EBUSY;
2865         val = ucontrol->value.integer.value[0];
2866         spin_lock_irq(&hdsp->lock);
2867         if (val != hdsp_dds_offset(hdsp))
2868                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2869         else
2870                 change = 0;
2871         spin_unlock_irq(&hdsp->lock);
2872         return change;
2873 }
2874
2875 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2876 HDSP_DA_GAIN("DA Gain", 0),
2877 HDSP_AD_GAIN("AD Gain", 0),
2878 HDSP_PHONE_GAIN("Phones Gain", 0),
2879 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2880 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2881 };
2882
2883 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2884 {
2885         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2886         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2887         .info =         snd_hdsp_control_spdif_info,
2888         .get =          snd_hdsp_control_spdif_get,
2889         .put =          snd_hdsp_control_spdif_put,
2890 },
2891 {
2892         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2893         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2894         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2895         .info =         snd_hdsp_control_spdif_stream_info,
2896         .get =          snd_hdsp_control_spdif_stream_get,
2897         .put =          snd_hdsp_control_spdif_stream_put,
2898 },
2899 {
2900         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2901         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2902         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2903         .info =         snd_hdsp_control_spdif_mask_info,
2904         .get =          snd_hdsp_control_spdif_mask_get,
2905         .private_value = IEC958_AES0_NONAUDIO |
2906                          IEC958_AES0_PROFESSIONAL |
2907                          IEC958_AES0_CON_EMPHASIS,
2908 },
2909 {
2910         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2911         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2912         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2913         .info =         snd_hdsp_control_spdif_mask_info,
2914         .get =          snd_hdsp_control_spdif_mask_get,
2915         .private_value = IEC958_AES0_NONAUDIO |
2916                          IEC958_AES0_PROFESSIONAL |
2917                          IEC958_AES0_PRO_EMPHASIS,
2918 },
2919 HDSP_MIXER("Mixer", 0),
2920 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2921 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2922 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2923 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2924 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2925 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2926 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2927 {
2928         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2929         .name = "Sample Clock Source Locking",
2930         .info = snd_hdsp_info_clock_source_lock,
2931         .get = snd_hdsp_get_clock_source_lock,
2932         .put = snd_hdsp_put_clock_source_lock,
2933 },
2934 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2935 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2936 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2937 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2938 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2939 /* 'External Rate' complies with the alsa control naming scheme */
2940 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2941 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2942 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2943 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2944 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2945 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2946 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2947 };
2948
2949
2950 static int hdsp_rpm_input12(struct hdsp *hdsp)
2951 {
2952         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2953         case HDSP_RPM_Inp12_Phon_6dB:
2954                 return 0;
2955         case HDSP_RPM_Inp12_Phon_n6dB:
2956                 return 2;
2957         case HDSP_RPM_Inp12_Line_0dB:
2958                 return 3;
2959         case HDSP_RPM_Inp12_Line_n6dB:
2960                 return 4;
2961         }
2962         return 1;
2963 }
2964
2965
2966 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2967 {
2968         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2969
2970         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2971         return 0;
2972 }
2973
2974
2975 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2976 {
2977         hdsp->control_register &= ~HDSP_RPM_Inp12;
2978         switch (mode) {
2979         case 0:
2980                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2981                 break;
2982         case 1:
2983                 break;
2984         case 2:
2985                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2986                 break;
2987         case 3:
2988                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2989                 break;
2990         case 4:
2991                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2992                 break;
2993         default:
2994                 return -1;
2995         }
2996
2997         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2998         return 0;
2999 }
3000
3001
3002 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3003 {
3004         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3005         int change;
3006         int val;
3007
3008         if (!snd_hdsp_use_is_exclusive(hdsp))
3009                 return -EBUSY;
3010         val = ucontrol->value.enumerated.item[0];
3011         if (val < 0)
3012                 val = 0;
3013         if (val > 4)
3014                 val = 4;
3015         spin_lock_irq(&hdsp->lock);
3016         if (val != hdsp_rpm_input12(hdsp))
3017                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3018         else
3019                 change = 0;
3020         spin_unlock_irq(&hdsp->lock);
3021         return change;
3022 }
3023
3024
3025 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3026 {
3027         static const char * const texts[] = {
3028                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3029         };
3030
3031         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3032 }
3033
3034
3035 static int hdsp_rpm_input34(struct hdsp *hdsp)
3036 {
3037         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3038         case HDSP_RPM_Inp34_Phon_6dB:
3039                 return 0;
3040         case HDSP_RPM_Inp34_Phon_n6dB:
3041                 return 2;
3042         case HDSP_RPM_Inp34_Line_0dB:
3043                 return 3;
3044         case HDSP_RPM_Inp34_Line_n6dB:
3045                 return 4;
3046         }
3047         return 1;
3048 }
3049
3050
3051 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3052 {
3053         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3054
3055         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3056         return 0;
3057 }
3058
3059
3060 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3061 {
3062         hdsp->control_register &= ~HDSP_RPM_Inp34;
3063         switch (mode) {
3064         case 0:
3065                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3066                 break;
3067         case 1:
3068                 break;
3069         case 2:
3070                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3071                 break;
3072         case 3:
3073                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3074                 break;
3075         case 4:
3076                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3077                 break;
3078         default:
3079                 return -1;
3080         }
3081
3082         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3083         return 0;
3084 }
3085
3086
3087 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3088 {
3089         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3090         int change;
3091         int val;
3092
3093         if (!snd_hdsp_use_is_exclusive(hdsp))
3094                 return -EBUSY;
3095         val = ucontrol->value.enumerated.item[0];
3096         if (val < 0)
3097                 val = 0;
3098         if (val > 4)
3099                 val = 4;
3100         spin_lock_irq(&hdsp->lock);
3101         if (val != hdsp_rpm_input34(hdsp))
3102                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3103         else
3104                 change = 0;
3105         spin_unlock_irq(&hdsp->lock);
3106         return change;
3107 }
3108
3109
3110 /* RPM Bypass switch */
3111 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3112 {
3113         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3114 }
3115
3116
3117 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3118 {
3119         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3120
3121         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3122         return 0;
3123 }
3124
3125
3126 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3127 {
3128         if (on)
3129                 hdsp->control_register |= HDSP_RPM_Bypass;
3130         else
3131                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3132         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3133         return 0;
3134 }
3135
3136
3137 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3138 {
3139         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3140         int change;
3141         unsigned int val;
3142
3143         if (!snd_hdsp_use_is_exclusive(hdsp))
3144                 return -EBUSY;
3145         val = ucontrol->value.integer.value[0] & 1;
3146         spin_lock_irq(&hdsp->lock);
3147         change = (int)val != hdsp_rpm_bypass(hdsp);
3148         hdsp_set_rpm_bypass(hdsp, val);
3149         spin_unlock_irq(&hdsp->lock);
3150         return change;
3151 }
3152
3153
3154 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3155 {
3156         static const char * const texts[] = {"On", "Off"};
3157
3158         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3159 }
3160
3161
3162 /* RPM Disconnect switch */
3163 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3164 {
3165         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3166 }
3167
3168
3169 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3170 {
3171         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3172
3173         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3174         return 0;
3175 }
3176
3177
3178 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3179 {
3180         if (on)
3181                 hdsp->control_register |= HDSP_RPM_Disconnect;
3182         else
3183                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3184         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3185         return 0;
3186 }
3187
3188
3189 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3190 {
3191         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3192         int change;
3193         unsigned int val;
3194
3195         if (!snd_hdsp_use_is_exclusive(hdsp))
3196                 return -EBUSY;
3197         val = ucontrol->value.integer.value[0] & 1;
3198         spin_lock_irq(&hdsp->lock);
3199         change = (int)val != hdsp_rpm_disconnect(hdsp);
3200         hdsp_set_rpm_disconnect(hdsp, val);
3201         spin_unlock_irq(&hdsp->lock);
3202         return change;
3203 }
3204
3205 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3206 {
3207         static const char * const texts[] = {"On", "Off"};
3208
3209         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3210 }
3211
3212 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3213         {
3214                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3215                 .name = "RPM Bypass",
3216                 .get = snd_hdsp_get_rpm_bypass,
3217                 .put = snd_hdsp_put_rpm_bypass,
3218                 .info = snd_hdsp_info_rpm_bypass
3219         },
3220         {
3221                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222                 .name = "RPM Disconnect",
3223                 .get = snd_hdsp_get_rpm_disconnect,
3224                 .put = snd_hdsp_put_rpm_disconnect,
3225                 .info = snd_hdsp_info_rpm_disconnect
3226         },
3227         {
3228                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229                 .name = "Input 1/2",
3230                 .get = snd_hdsp_get_rpm_input12,
3231                 .put = snd_hdsp_put_rpm_input12,
3232                 .info = snd_hdsp_info_rpm_input
3233         },
3234         {
3235                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236                 .name = "Input 3/4",
3237                 .get = snd_hdsp_get_rpm_input34,
3238                 .put = snd_hdsp_put_rpm_input34,
3239                 .info = snd_hdsp_info_rpm_input
3240         },
3241         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3242         HDSP_MIXER("Mixer", 0)
3243 };
3244
3245 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3246         HDSP_TOGGLE_SETTING("Analog Extension Board",
3247                         HDSP_AnalogExtensionBoard);
3248 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3249
3250
3251 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3252 {
3253         return hdsp->io_loopback & (1 << channel);
3254 }
3255
3256 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3257 {
3258         if (hdsp_loopback_get(hdsp, channel) == enable)
3259                 return 0;
3260
3261         hdsp->io_loopback ^= (1 << channel);
3262
3263         hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3264
3265         return 1;
3266 }
3267
3268 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3269                                  struct snd_ctl_elem_value *const ucontrol)
3270 {
3271         struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3272         const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3273
3274         if (channel >= hdsp->max_channels)
3275                 return -ENOENT;
3276
3277         ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3278
3279         return 0;
3280 }
3281
3282 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3283                                  struct snd_ctl_elem_value *const ucontrol)
3284 {
3285         struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3286         const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3287         const bool enable = ucontrol->value.integer.value[0] & 1;
3288
3289         if (channel >= hdsp->max_channels)
3290                 return -ENOENT;
3291
3292         return hdsp_loopback_set(hdsp, channel, enable);
3293 }
3294
3295 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3296         .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3297         .name = "Output Loopback",
3298         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3299         .info = snd_ctl_boolean_mono_info,
3300         .get = snd_hdsp_loopback_get,
3301         .put = snd_hdsp_loopback_put
3302 };
3303
3304 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3305 {
3306         unsigned int idx;
3307         int err;
3308         struct snd_kcontrol *kctl;
3309
3310         if (hdsp->io_type == RPM) {
3311                 /* RPM Bypass, Disconnect and Input switches */
3312                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3313                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3314                         if (err < 0)
3315                                 return err;
3316                 }
3317                 return 0;
3318         }
3319
3320         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3321                 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);
3322                 err = snd_ctl_add(card, kctl);
3323                 if (err < 0)
3324                         return err;
3325                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3326                         hdsp->spdif_ctl = kctl;
3327         }
3328
3329         /* ADAT SyncCheck status */
3330         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3331         snd_hdsp_adat_sync_check.index = 1;
3332         kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3333         err = snd_ctl_add(card, kctl);
3334         if (err < 0)
3335                 return err;
3336         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3337                 for (idx = 1; idx < 3; ++idx) {
3338                         snd_hdsp_adat_sync_check.index = idx+1;
3339                         kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3340                         err = snd_ctl_add(card, kctl);
3341                         if (err < 0)
3342                                 return err;
3343                 }
3344         }
3345
3346         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3347         if (hdsp->io_type == H9632) {
3348                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3349                         kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);
3350                         err = snd_ctl_add(card, kctl);
3351                         if (err < 0)
3352                                 return err;
3353                 }
3354         }
3355
3356         /* Output loopback controls for H9632 cards */
3357         if (hdsp->io_type == H9632) {
3358                 snd_hdsp_loopback_control.count = hdsp->max_channels;
3359                 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3360                 if (kctl == NULL)
3361                         return -ENOMEM;
3362                 err = snd_ctl_add(card, kctl);
3363                 if (err < 0)
3364                         return err;
3365         }
3366
3367         /* AEB control for H96xx card */
3368         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3369                 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);
3370                 err = snd_ctl_add(card, kctl);
3371                 if (err < 0)
3372                         return err;
3373         }
3374
3375         return 0;
3376 }
3377
3378 /*------------------------------------------------------------
3379    /proc interface
3380  ------------------------------------------------------------*/
3381
3382 static void
3383 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3384 {
3385         struct hdsp *hdsp = entry->private_data;
3386         unsigned int status;
3387         unsigned int status2;
3388         char *pref_sync_ref;
3389         char *autosync_ref;
3390         char *system_clock_mode;
3391         char *clock_source;
3392         int x;
3393
3394         status = hdsp_read(hdsp, HDSP_statusRegister);
3395         status2 = hdsp_read(hdsp, HDSP_status2Register);
3396
3397         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3398                     hdsp->card->number + 1);
3399         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3400                     hdsp->capture_buffer, hdsp->playback_buffer);
3401         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3402                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3403         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3404         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3405                     hdsp->control2_register);
3406         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3407         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3408
3409         if (hdsp_check_for_iobox(hdsp)) {
3410                 snd_iprintf(buffer, "No I/O box connected.\n"
3411                             "Please connect one and upload firmware.\n");
3412                 return;
3413         }
3414
3415         if (hdsp_check_for_firmware(hdsp, 0)) {
3416                 if (hdsp->state & HDSP_FirmwareCached) {
3417                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3418                                 snd_iprintf(buffer, "Firmware loading from "
3419                                             "cache failed, "
3420                                             "please upload manually.\n");
3421                                 return;
3422                         }
3423                 } else {
3424                         int err;
3425
3426                         err = hdsp_request_fw_loader(hdsp);
3427                         if (err < 0) {
3428                                 snd_iprintf(buffer,
3429                                             "No firmware loaded nor cached, "
3430                                             "please upload firmware.\n");
3431                                 return;
3432                         }
3433                 }
3434         }
3435
3436         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3437         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3438         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3439         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3440         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3441         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3442
3443         snd_iprintf(buffer, "\n");
3444
3445         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3446
3447         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3448         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3449         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3450         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3451
3452         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3453
3454         snd_iprintf(buffer, "\n");
3455
3456         switch (hdsp_clock_source(hdsp)) {
3457         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3458                 clock_source = "AutoSync";
3459                 break;
3460         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3461                 clock_source = "Internal 32 kHz";
3462                 break;
3463         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3464                 clock_source = "Internal 44.1 kHz";
3465                 break;
3466         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3467                 clock_source = "Internal 48 kHz";
3468                 break;
3469         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3470                 clock_source = "Internal 64 kHz";
3471                 break;
3472         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3473                 clock_source = "Internal 88.2 kHz";
3474                 break;
3475         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3476                 clock_source = "Internal 96 kHz";
3477                 break;
3478         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3479                 clock_source = "Internal 128 kHz";
3480                 break;
3481         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3482                 clock_source = "Internal 176.4 kHz";
3483                 break;
3484                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3485                 clock_source = "Internal 192 kHz";
3486                 break;
3487         default:
3488                 clock_source = "Error";
3489         }
3490         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3491
3492         if (hdsp_system_clock_mode(hdsp))
3493                 system_clock_mode = "Slave";
3494         else
3495                 system_clock_mode = "Master";
3496
3497         switch (hdsp_pref_sync_ref (hdsp)) {
3498         case HDSP_SYNC_FROM_WORD:
3499                 pref_sync_ref = "Word Clock";
3500                 break;
3501         case HDSP_SYNC_FROM_ADAT_SYNC:
3502                 pref_sync_ref = "ADAT Sync";
3503                 break;
3504         case HDSP_SYNC_FROM_SPDIF:
3505                 pref_sync_ref = "SPDIF";
3506                 break;
3507         case HDSP_SYNC_FROM_ADAT1:
3508                 pref_sync_ref = "ADAT1";
3509                 break;
3510         case HDSP_SYNC_FROM_ADAT2:
3511                 pref_sync_ref = "ADAT2";
3512                 break;
3513         case HDSP_SYNC_FROM_ADAT3:
3514                 pref_sync_ref = "ADAT3";
3515                 break;
3516         default:
3517                 pref_sync_ref = "Word Clock";
3518                 break;
3519         }
3520         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3521
3522         switch (hdsp_autosync_ref (hdsp)) {
3523         case HDSP_AUTOSYNC_FROM_WORD:
3524                 autosync_ref = "Word Clock";
3525                 break;
3526         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3527                 autosync_ref = "ADAT Sync";
3528                 break;
3529         case HDSP_AUTOSYNC_FROM_SPDIF:
3530                 autosync_ref = "SPDIF";
3531                 break;
3532         case HDSP_AUTOSYNC_FROM_NONE:
3533                 autosync_ref = "None";
3534                 break;
3535         case HDSP_AUTOSYNC_FROM_ADAT1:
3536                 autosync_ref = "ADAT1";
3537                 break;
3538         case HDSP_AUTOSYNC_FROM_ADAT2:
3539                 autosync_ref = "ADAT2";
3540                 break;
3541         case HDSP_AUTOSYNC_FROM_ADAT3:
3542                 autosync_ref = "ADAT3";
3543                 break;
3544         default:
3545                 autosync_ref = "---";
3546                 break;
3547         }
3548         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3549
3550         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3551
3552         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3553
3554         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3555         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3556
3557         snd_iprintf(buffer, "\n");
3558
3559         if (hdsp->io_type != RPM) {
3560                 switch (hdsp_spdif_in(hdsp)) {
3561                 case HDSP_SPDIFIN_OPTICAL:
3562                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3563                         break;
3564                 case HDSP_SPDIFIN_COAXIAL:
3565                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3566                         break;
3567                 case HDSP_SPDIFIN_INTERNAL:
3568                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3569                         break;
3570                 case HDSP_SPDIFIN_AES:
3571                         snd_iprintf(buffer, "IEC958 input: AES\n");
3572                         break;
3573                 default:
3574                         snd_iprintf(buffer, "IEC958 input: ???\n");
3575                         break;
3576                 }
3577         }
3578
3579         if (RPM == hdsp->io_type) {
3580                 if (hdsp->control_register & HDSP_RPM_Bypass)
3581                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3582                 else
3583                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3584                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3585                         snd_iprintf(buffer, "RPM disconnected\n");
3586                 else
3587                         snd_iprintf(buffer, "RPM connected\n");
3588
3589                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3590                 case HDSP_RPM_Inp12_Phon_6dB:
3591                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3592                         break;
3593                 case HDSP_RPM_Inp12_Phon_0dB:
3594                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3595                         break;
3596                 case HDSP_RPM_Inp12_Phon_n6dB:
3597                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3598                         break;
3599                 case HDSP_RPM_Inp12_Line_0dB:
3600                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3601                         break;
3602                 case HDSP_RPM_Inp12_Line_n6dB:
3603                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3604                         break;
3605                 default:
3606                         snd_iprintf(buffer, "Input 1/2: ???\n");
3607                 }
3608
3609                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3610                 case HDSP_RPM_Inp34_Phon_6dB:
3611                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3612                         break;
3613                 case HDSP_RPM_Inp34_Phon_0dB:
3614                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3615                         break;
3616                 case HDSP_RPM_Inp34_Phon_n6dB:
3617                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3618                         break;
3619                 case HDSP_RPM_Inp34_Line_0dB:
3620                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3621                         break;
3622                 case HDSP_RPM_Inp34_Line_n6dB:
3623                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3624                         break;
3625                 default:
3626                         snd_iprintf(buffer, "Input 3/4: ???\n");
3627                 }
3628
3629         } else {
3630                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3631                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3632                 else
3633                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3634
3635                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3636                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3637                 else
3638                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3639
3640                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3641                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3642                 else
3643                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3644
3645                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3646                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3647                 else
3648                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3649                 x = hdsp_spdif_sample_rate(hdsp);
3650                 if (x != 0)
3651                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3652                 else
3653                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3654         }
3655         snd_iprintf(buffer, "\n");
3656
3657         /* Sync Check */
3658         x = status & HDSP_Sync0;
3659         if (status & HDSP_Lock0)
3660                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3661         else
3662                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3663
3664         switch (hdsp->io_type) {
3665         case Digiface:
3666         case H9652:
3667                 x = status & HDSP_Sync1;
3668                 if (status & HDSP_Lock1)
3669                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3670                 else
3671                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3672                 x = status & HDSP_Sync2;
3673                 if (status & HDSP_Lock2)
3674                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3675                 else
3676                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3677                 break;
3678         default:
3679                 /* relax */
3680                 break;
3681         }
3682
3683         x = status & HDSP_SPDIFSync;
3684         if (status & HDSP_SPDIFErrorFlag)
3685                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3686         else
3687                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3688
3689         x = status2 & HDSP_wc_sync;
3690         if (status2 & HDSP_wc_lock)
3691                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3692         else
3693                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3694
3695         x = status & HDSP_TimecodeSync;
3696         if (status & HDSP_TimecodeLock)
3697                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3698         else
3699                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3700
3701         snd_iprintf(buffer, "\n");
3702
3703         /* Informations about H9632 specific controls */
3704         if (hdsp->io_type == H9632) {
3705                 char *tmp;
3706
3707                 switch (hdsp_ad_gain(hdsp)) {
3708                 case 0:
3709                         tmp = "-10 dBV";
3710                         break;
3711                 case 1:
3712                         tmp = "+4 dBu";
3713                         break;
3714                 default:
3715                         tmp = "Lo Gain";
3716                         break;
3717                 }
3718                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3719
3720                 switch (hdsp_da_gain(hdsp)) {
3721                 case 0:
3722                         tmp = "Hi Gain";
3723                         break;
3724                 case 1:
3725                         tmp = "+4 dBu";
3726                         break;
3727                 default:
3728                         tmp = "-10 dBV";
3729                         break;
3730                 }
3731                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3732
3733                 switch (hdsp_phone_gain(hdsp)) {
3734                 case 0:
3735                         tmp = "0 dB";
3736                         break;
3737                 case 1:
3738                         tmp = "-6 dB";
3739                         break;
3740                 default:
3741                         tmp = "-12 dB";
3742                         break;
3743                 }
3744                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3745
3746                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3747                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3748                         "yes" : "no");
3749
3750                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3751                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3752                 else
3753                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3754                 snd_iprintf(buffer, "\n");
3755         }
3756
3757 }
3758
3759 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3760 {
3761         snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3762 }
3763
3764 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3765 {
3766         struct snd_dma_buffer *capture_dma, *playback_dma;
3767
3768         capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3769         playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3770         if (!capture_dma || !playback_dma) {
3771                 dev_err(hdsp->card->dev,
3772                         "%s: no buffers available\n", hdsp->card_name);
3773                 return -ENOMEM;
3774         }
3775
3776         /* copy to the own data for alignment */
3777         hdsp->capture_dma_buf = *capture_dma;
3778         hdsp->playback_dma_buf = *playback_dma;
3779
3780         /* Align to bus-space 64K boundary */
3781         hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
3782         hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
3783
3784         /* Tell the card where it is */
3785         hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr);
3786         hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr);
3787
3788         hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr;
3789         hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr;
3790         hdsp->capture_buffer = hdsp->capture_dma_buf.area;
3791         hdsp->playback_buffer = hdsp->playback_dma_buf.area;
3792
3793         return 0;
3794 }
3795
3796 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3797 {
3798         unsigned int i;
3799
3800         /* ASSUMPTION: hdsp->lock is either held, or
3801            there is no need to hold it (e.g. during module
3802            initialization).
3803          */
3804
3805         /* set defaults:
3806
3807            SPDIF Input via Coax
3808            Master clock mode
3809            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3810                             which implies 2 4096 sample, 32Kbyte periods).
3811            Enable line out.
3812          */
3813
3814         hdsp->control_register = HDSP_ClockModeMaster |
3815                                  HDSP_SPDIFInputCoaxial |
3816                                  hdsp_encode_latency(7) |
3817                                  HDSP_LineOut;
3818
3819
3820         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3821
3822 #ifdef SNDRV_BIG_ENDIAN
3823         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3824 #else
3825         hdsp->control2_register = 0;
3826 #endif
3827         if (hdsp->io_type == H9652)
3828                 snd_hdsp_9652_enable_mixer (hdsp);
3829         else
3830                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3831
3832         hdsp_reset_hw_pointer(hdsp);
3833         hdsp_compute_period_size(hdsp);
3834
3835         /* silence everything */
3836
3837         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3838                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3839
3840         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3841                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3842                         return -EIO;
3843         }
3844
3845         /* H9632 specific defaults */
3846         if (hdsp->io_type == H9632) {
3847                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3848                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3849         }
3850
3851         /* set a default rate so that the channel map is set up.
3852          */
3853
3854         hdsp_set_rate(hdsp, 48000, 1);
3855
3856         return 0;
3857 }
3858
3859 static void hdsp_midi_work(struct work_struct *work)
3860 {
3861         struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3862
3863         if (hdsp->midi[0].pending)
3864                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3865         if (hdsp->midi[1].pending)
3866                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3867 }
3868
3869 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3870 {
3871         struct hdsp *hdsp = (struct hdsp *) dev_id;
3872         unsigned int status;
3873         int audio;
3874         int midi0;
3875         int midi1;
3876         unsigned int midi0status;
3877         unsigned int midi1status;
3878         int schedule = 0;
3879
3880         status = hdsp_read(hdsp, HDSP_statusRegister);
3881
3882         audio = status & HDSP_audioIRQPending;
3883         midi0 = status & HDSP_midi0IRQPending;
3884         midi1 = status & HDSP_midi1IRQPending;
3885
3886         if (!audio && !midi0 && !midi1)
3887                 return IRQ_NONE;
3888
3889         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3890
3891         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3892         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3893
3894         if (!(hdsp->state & HDSP_InitializationComplete))
3895                 return IRQ_HANDLED;
3896
3897         if (audio) {
3898                 if (hdsp->capture_substream)
3899                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3900
3901                 if (hdsp->playback_substream)
3902                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3903         }
3904
3905         if (midi0 && midi0status) {
3906                 if (hdsp->use_midi_work) {
3907                         /* we disable interrupts for this input until processing is done */
3908                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3909                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3910                         hdsp->midi[0].pending = 1;
3911                         schedule = 1;
3912                 } else {
3913                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3914                 }
3915         }
3916         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3917                 if (hdsp->use_midi_work) {
3918                         /* we disable interrupts for this input until processing is done */
3919                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3920                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3921                         hdsp->midi[1].pending = 1;
3922                         schedule = 1;
3923                 } else {
3924                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3925                 }
3926         }
3927         if (hdsp->use_midi_work && schedule)
3928                 queue_work(system_highpri_wq, &hdsp->midi_work);
3929         return IRQ_HANDLED;
3930 }
3931
3932 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3933 {
3934         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935         return hdsp_hw_pointer(hdsp);
3936 }
3937
3938 static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3939                                              int stream,
3940                                              int channel)
3941
3942 {
3943         int mapped_channel;
3944
3945         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3946                 return NULL;
3947
3948         mapped_channel = hdsp->channel_map[channel];
3949         if (mapped_channel < 0)
3950                 return NULL;
3951
3952         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3953                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3954         else
3955                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3956 }
3957
3958 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3959                                   int channel, unsigned long pos,
3960                                   void __user *src, unsigned long count)
3961 {
3962         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3963         signed char *channel_buf;
3964
3965         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3966                 return -EINVAL;
3967
3968         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3969         if (snd_BUG_ON(!channel_buf))
3970                 return -EIO;
3971         if (copy_from_user(channel_buf + pos, src, count))
3972                 return -EFAULT;
3973         return 0;
3974 }
3975
3976 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3977                                          int channel, unsigned long pos,
3978                                          void *src, unsigned long count)
3979 {
3980         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3981         signed char *channel_buf;
3982
3983         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3984         if (snd_BUG_ON(!channel_buf))
3985                 return -EIO;
3986         memcpy(channel_buf + pos, src, count);
3987         return 0;
3988 }
3989
3990 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3991                                  int channel, unsigned long pos,
3992                                  void __user *dst, unsigned long count)
3993 {
3994         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3995         signed char *channel_buf;
3996
3997         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3998                 return -EINVAL;
3999
4000         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4001         if (snd_BUG_ON(!channel_buf))
4002                 return -EIO;
4003         if (copy_to_user(dst, channel_buf + pos, count))
4004                 return -EFAULT;
4005         return 0;
4006 }
4007
4008 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
4009                                         int channel, unsigned long pos,
4010                                         void *dst, unsigned long count)
4011 {
4012         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4013         signed char *channel_buf;
4014
4015         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
4016         if (snd_BUG_ON(!channel_buf))
4017                 return -EIO;
4018         memcpy(dst, channel_buf + pos, count);
4019         return 0;
4020 }
4021
4022 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
4023                                int channel, unsigned long pos,
4024                                unsigned long count)
4025 {
4026         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4027         signed char *channel_buf;
4028
4029         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4030         if (snd_BUG_ON(!channel_buf))
4031                 return -EIO;
4032         memset(channel_buf + pos, 0, count);
4033         return 0;
4034 }
4035
4036 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4037 {
4038         struct snd_pcm_runtime *runtime = substream->runtime;
4039         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4040         struct snd_pcm_substream *other;
4041         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4042                 other = hdsp->capture_substream;
4043         else
4044                 other = hdsp->playback_substream;
4045         if (hdsp->running)
4046                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4047         else
4048                 runtime->status->hw_ptr = 0;
4049         if (other) {
4050                 struct snd_pcm_substream *s;
4051                 struct snd_pcm_runtime *oruntime = other->runtime;
4052                 snd_pcm_group_for_each_entry(s, substream) {
4053                         if (s == other) {
4054                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4055                                 break;
4056                         }
4057                 }
4058         }
4059         return 0;
4060 }
4061
4062 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4063                                  struct snd_pcm_hw_params *params)
4064 {
4065         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4066         int err;
4067         pid_t this_pid;
4068         pid_t other_pid;
4069
4070         if (hdsp_check_for_iobox (hdsp))
4071                 return -EIO;
4072
4073         if (hdsp_check_for_firmware(hdsp, 1))
4074                 return -EIO;
4075
4076         spin_lock_irq(&hdsp->lock);
4077
4078         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4079                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4080                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4081                 this_pid = hdsp->playback_pid;
4082                 other_pid = hdsp->capture_pid;
4083         } else {
4084                 this_pid = hdsp->capture_pid;
4085                 other_pid = hdsp->playback_pid;
4086         }
4087
4088         if ((other_pid > 0) && (this_pid != other_pid)) {
4089
4090                 /* The other stream is open, and not by the same
4091                    task as this one. Make sure that the parameters
4092                    that matter are the same.
4093                  */
4094
4095                 if (params_rate(params) != hdsp->system_sample_rate) {
4096                         spin_unlock_irq(&hdsp->lock);
4097                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4098                         return -EBUSY;
4099                 }
4100
4101                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4102                         spin_unlock_irq(&hdsp->lock);
4103                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4104                         return -EBUSY;
4105                 }
4106
4107                 /* We're fine. */
4108
4109                 spin_unlock_irq(&hdsp->lock);
4110                 return 0;
4111
4112         } else {
4113                 spin_unlock_irq(&hdsp->lock);
4114         }
4115
4116         /* how to make sure that the rate matches an externally-set one ?
4117          */
4118
4119         spin_lock_irq(&hdsp->lock);
4120         if (! hdsp->clock_source_locked) {
4121                 err = hdsp_set_rate(hdsp, params_rate(params), 0);
4122                 if (err < 0) {
4123                         spin_unlock_irq(&hdsp->lock);
4124                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4125                         return err;
4126                 }
4127         }
4128         spin_unlock_irq(&hdsp->lock);
4129
4130         err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));
4131         if (err < 0) {
4132                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4133                 return err;
4134         }
4135
4136         return 0;
4137 }
4138
4139 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4140                                     struct snd_pcm_channel_info *info)
4141 {
4142         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4143         unsigned int channel = info->channel;
4144
4145         if (snd_BUG_ON(channel >= hdsp->max_channels))
4146                 return -EINVAL;
4147         channel = array_index_nospec(channel, hdsp->max_channels);
4148
4149         if (hdsp->channel_map[channel] < 0)
4150                 return -EINVAL;
4151
4152         info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4153         info->first = 0;
4154         info->step = 32;
4155         return 0;
4156 }
4157
4158 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4159                              unsigned int cmd, void *arg)
4160 {
4161         switch (cmd) {
4162         case SNDRV_PCM_IOCTL1_RESET:
4163                 return snd_hdsp_reset(substream);
4164         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4165                 return snd_hdsp_channel_info(substream, arg);
4166         default:
4167                 break;
4168         }
4169
4170         return snd_pcm_lib_ioctl(substream, cmd, arg);
4171 }
4172
4173 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4174 {
4175         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4176         struct snd_pcm_substream *other;
4177         int running;
4178
4179         if (hdsp_check_for_iobox (hdsp))
4180                 return -EIO;
4181
4182         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4183                 return -EIO;
4184
4185         spin_lock(&hdsp->lock);
4186         running = hdsp->running;
4187         switch (cmd) {
4188         case SNDRV_PCM_TRIGGER_START:
4189                 running |= 1 << substream->stream;
4190                 break;
4191         case SNDRV_PCM_TRIGGER_STOP:
4192                 running &= ~(1 << substream->stream);
4193                 break;
4194         default:
4195                 snd_BUG();
4196                 spin_unlock(&hdsp->lock);
4197                 return -EINVAL;
4198         }
4199         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4200                 other = hdsp->capture_substream;
4201         else
4202                 other = hdsp->playback_substream;
4203
4204         if (other) {
4205                 struct snd_pcm_substream *s;
4206                 snd_pcm_group_for_each_entry(s, substream) {
4207                         if (s == other) {
4208                                 snd_pcm_trigger_done(s, substream);
4209                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4210                                         running |= 1 << s->stream;
4211                                 else
4212                                         running &= ~(1 << s->stream);
4213                                 goto _ok;
4214                         }
4215                 }
4216                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4217                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4218                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4219                                 hdsp_silence_playback(hdsp);
4220                 } else {
4221                         if (running &&
4222                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4223                                 hdsp_silence_playback(hdsp);
4224                 }
4225         } else {
4226                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4227                                 hdsp_silence_playback(hdsp);
4228         }
4229  _ok:
4230         snd_pcm_trigger_done(substream, substream);
4231         if (!hdsp->running && running)
4232                 hdsp_start_audio(hdsp);
4233         else if (hdsp->running && !running)
4234                 hdsp_stop_audio(hdsp);
4235         hdsp->running = running;
4236         spin_unlock(&hdsp->lock);
4237
4238         return 0;
4239 }
4240
4241 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4242 {
4243         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4244         int result = 0;
4245
4246         if (hdsp_check_for_iobox (hdsp))
4247                 return -EIO;
4248
4249         if (hdsp_check_for_firmware(hdsp, 1))
4250                 return -EIO;
4251
4252         spin_lock_irq(&hdsp->lock);
4253         if (!hdsp->running)
4254                 hdsp_reset_hw_pointer(hdsp);
4255         spin_unlock_irq(&hdsp->lock);
4256         return result;
4257 }
4258
4259 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4260 {
4261         .info =                 (SNDRV_PCM_INFO_MMAP |
4262                                  SNDRV_PCM_INFO_MMAP_VALID |
4263                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4264                                  SNDRV_PCM_INFO_SYNC_START |
4265                                  SNDRV_PCM_INFO_DOUBLE),
4266 #ifdef SNDRV_BIG_ENDIAN
4267         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4268 #else
4269         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4270 #endif
4271         .rates =                (SNDRV_PCM_RATE_32000 |
4272                                  SNDRV_PCM_RATE_44100 |
4273                                  SNDRV_PCM_RATE_48000 |
4274                                  SNDRV_PCM_RATE_64000 |
4275                                  SNDRV_PCM_RATE_88200 |
4276                                  SNDRV_PCM_RATE_96000),
4277         .rate_min =             32000,
4278         .rate_max =             96000,
4279         .channels_min =         6,
4280         .channels_max =         HDSP_MAX_CHANNELS,
4281         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4282         .period_bytes_min =     (64 * 4) * 10,
4283         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4284         .periods_min =          2,
4285         .periods_max =          2,
4286         .fifo_size =            0
4287 };
4288
4289 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4290 {
4291         .info =                 (SNDRV_PCM_INFO_MMAP |
4292                                  SNDRV_PCM_INFO_MMAP_VALID |
4293                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4294                                  SNDRV_PCM_INFO_SYNC_START),
4295 #ifdef SNDRV_BIG_ENDIAN
4296         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4297 #else
4298         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4299 #endif
4300         .rates =                (SNDRV_PCM_RATE_32000 |
4301                                  SNDRV_PCM_RATE_44100 |
4302                                  SNDRV_PCM_RATE_48000 |
4303                                  SNDRV_PCM_RATE_64000 |
4304                                  SNDRV_PCM_RATE_88200 |
4305                                  SNDRV_PCM_RATE_96000),
4306         .rate_min =             32000,
4307         .rate_max =             96000,
4308         .channels_min =         5,
4309         .channels_max =         HDSP_MAX_CHANNELS,
4310         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4311         .period_bytes_min =     (64 * 4) * 10,
4312         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4313         .periods_min =          2,
4314         .periods_max =          2,
4315         .fifo_size =            0
4316 };
4317
4318 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4319
4320 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4321         .count = ARRAY_SIZE(hdsp_period_sizes),
4322         .list = hdsp_period_sizes,
4323         .mask = 0
4324 };
4325
4326 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4327
4328 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4329         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4330         .list = hdsp_9632_sample_rates,
4331         .mask = 0
4332 };
4333
4334 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4335                                         struct snd_pcm_hw_rule *rule)
4336 {
4337         struct hdsp *hdsp = rule->private;
4338         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339         if (hdsp->io_type == H9632) {
4340                 unsigned int list[3];
4341                 list[0] = hdsp->qs_in_channels;
4342                 list[1] = hdsp->ds_in_channels;
4343                 list[2] = hdsp->ss_in_channels;
4344                 return snd_interval_list(c, 3, list, 0);
4345         } else {
4346                 unsigned int list[2];
4347                 list[0] = hdsp->ds_in_channels;
4348                 list[1] = hdsp->ss_in_channels;
4349                 return snd_interval_list(c, 2, list, 0);
4350         }
4351 }
4352
4353 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4354                                         struct snd_pcm_hw_rule *rule)
4355 {
4356         unsigned int list[3];
4357         struct hdsp *hdsp = rule->private;
4358         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4359         if (hdsp->io_type == H9632) {
4360                 list[0] = hdsp->qs_out_channels;
4361                 list[1] = hdsp->ds_out_channels;
4362                 list[2] = hdsp->ss_out_channels;
4363                 return snd_interval_list(c, 3, list, 0);
4364         } else {
4365                 list[0] = hdsp->ds_out_channels;
4366                 list[1] = hdsp->ss_out_channels;
4367         }
4368         return snd_interval_list(c, 2, list, 0);
4369 }
4370
4371 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4372                                              struct snd_pcm_hw_rule *rule)
4373 {
4374         struct hdsp *hdsp = rule->private;
4375         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4376         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4377         if (r->min > 96000 && hdsp->io_type == H9632) {
4378                 struct snd_interval t = {
4379                         .min = hdsp->qs_in_channels,
4380                         .max = hdsp->qs_in_channels,
4381                         .integer = 1,
4382                 };
4383                 return snd_interval_refine(c, &t);
4384         } else if (r->min > 48000 && r->max <= 96000) {
4385                 struct snd_interval t = {
4386                         .min = hdsp->ds_in_channels,
4387                         .max = hdsp->ds_in_channels,
4388                         .integer = 1,
4389                 };
4390                 return snd_interval_refine(c, &t);
4391         } else if (r->max < 64000) {
4392                 struct snd_interval t = {
4393                         .min = hdsp->ss_in_channels,
4394                         .max = hdsp->ss_in_channels,
4395                         .integer = 1,
4396                 };
4397                 return snd_interval_refine(c, &t);
4398         }
4399         return 0;
4400 }
4401
4402 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4403                                              struct snd_pcm_hw_rule *rule)
4404 {
4405         struct hdsp *hdsp = rule->private;
4406         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4407         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4408         if (r->min > 96000 && hdsp->io_type == H9632) {
4409                 struct snd_interval t = {
4410                         .min = hdsp->qs_out_channels,
4411                         .max = hdsp->qs_out_channels,
4412                         .integer = 1,
4413                 };
4414                 return snd_interval_refine(c, &t);
4415         } else if (r->min > 48000 && r->max <= 96000) {
4416                 struct snd_interval t = {
4417                         .min = hdsp->ds_out_channels,
4418                         .max = hdsp->ds_out_channels,
4419                         .integer = 1,
4420                 };
4421                 return snd_interval_refine(c, &t);
4422         } else if (r->max < 64000) {
4423                 struct snd_interval t = {
4424                         .min = hdsp->ss_out_channels,
4425                         .max = hdsp->ss_out_channels,
4426                         .integer = 1,
4427                 };
4428                 return snd_interval_refine(c, &t);
4429         }
4430         return 0;
4431 }
4432
4433 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4434                                              struct snd_pcm_hw_rule *rule)
4435 {
4436         struct hdsp *hdsp = rule->private;
4437         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4438         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4439         if (c->min >= hdsp->ss_out_channels) {
4440                 struct snd_interval t = {
4441                         .min = 32000,
4442                         .max = 48000,
4443                         .integer = 1,
4444                 };
4445                 return snd_interval_refine(r, &t);
4446         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4447                 struct snd_interval t = {
4448                         .min = 128000,
4449                         .max = 192000,
4450                         .integer = 1,
4451                 };
4452                 return snd_interval_refine(r, &t);
4453         } else if (c->max <= hdsp->ds_out_channels) {
4454                 struct snd_interval t = {
4455                         .min = 64000,
4456                         .max = 96000,
4457                         .integer = 1,
4458                 };
4459                 return snd_interval_refine(r, &t);
4460         }
4461         return 0;
4462 }
4463
4464 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4465                                              struct snd_pcm_hw_rule *rule)
4466 {
4467         struct hdsp *hdsp = rule->private;
4468         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4469         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4470         if (c->min >= hdsp->ss_in_channels) {
4471                 struct snd_interval t = {
4472                         .min = 32000,
4473                         .max = 48000,
4474                         .integer = 1,
4475                 };
4476                 return snd_interval_refine(r, &t);
4477         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4478                 struct snd_interval t = {
4479                         .min = 128000,
4480                         .max = 192000,
4481                         .integer = 1,
4482                 };
4483                 return snd_interval_refine(r, &t);
4484         } else if (c->max <= hdsp->ds_in_channels) {
4485                 struct snd_interval t = {
4486                         .min = 64000,
4487                         .max = 96000,
4488                         .integer = 1,
4489                 };
4490                 return snd_interval_refine(r, &t);
4491         }
4492         return 0;
4493 }
4494
4495 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4496 {
4497         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4498         struct snd_pcm_runtime *runtime = substream->runtime;
4499
4500         if (hdsp_check_for_iobox (hdsp))
4501                 return -EIO;
4502
4503         if (hdsp_check_for_firmware(hdsp, 1))
4504                 return -EIO;
4505
4506         spin_lock_irq(&hdsp->lock);
4507
4508         snd_pcm_set_sync(substream);
4509
4510         runtime->hw = snd_hdsp_playback_subinfo;
4511         snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf);
4512
4513         hdsp->playback_pid = current->pid;
4514         hdsp->playback_substream = substream;
4515
4516         spin_unlock_irq(&hdsp->lock);
4517
4518         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4519         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4520         if (hdsp->clock_source_locked) {
4521                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4522         } else if (hdsp->io_type == H9632) {
4523                 runtime->hw.rate_max = 192000;
4524                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4525                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4526         }
4527         if (hdsp->io_type == H9632) {
4528                 runtime->hw.channels_min = hdsp->qs_out_channels;
4529                 runtime->hw.channels_max = hdsp->ss_out_channels;
4530         }
4531
4532         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4533                              snd_hdsp_hw_rule_out_channels, hdsp,
4534                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4535         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4536                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4537                              SNDRV_PCM_HW_PARAM_RATE, -1);
4538         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4539                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4540                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4541
4542         if (RPM != hdsp->io_type) {
4543                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4544                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4545                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4546                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4547         }
4548         return 0;
4549 }
4550
4551 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4552 {
4553         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4554
4555         spin_lock_irq(&hdsp->lock);
4556
4557         hdsp->playback_pid = -1;
4558         hdsp->playback_substream = NULL;
4559
4560         spin_unlock_irq(&hdsp->lock);
4561
4562         if (RPM != hdsp->io_type) {
4563                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4564                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4565                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4566         }
4567         return 0;
4568 }
4569
4570
4571 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4572 {
4573         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4574         struct snd_pcm_runtime *runtime = substream->runtime;
4575
4576         if (hdsp_check_for_iobox (hdsp))
4577                 return -EIO;
4578
4579         if (hdsp_check_for_firmware(hdsp, 1))
4580                 return -EIO;
4581
4582         spin_lock_irq(&hdsp->lock);
4583
4584         snd_pcm_set_sync(substream);
4585
4586         runtime->hw = snd_hdsp_capture_subinfo;
4587         snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf);
4588
4589         hdsp->capture_pid = current->pid;
4590         hdsp->capture_substream = substream;
4591
4592         spin_unlock_irq(&hdsp->lock);
4593
4594         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4595         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4596         if (hdsp->io_type == H9632) {
4597                 runtime->hw.channels_min = hdsp->qs_in_channels;
4598                 runtime->hw.channels_max = hdsp->ss_in_channels;
4599                 runtime->hw.rate_max = 192000;
4600                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4601                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4602         }
4603         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4604                              snd_hdsp_hw_rule_in_channels, hdsp,
4605                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4606         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4607                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4608                              SNDRV_PCM_HW_PARAM_RATE, -1);
4609         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4610                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4611                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4612         return 0;
4613 }
4614
4615 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4616 {
4617         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4618
4619         spin_lock_irq(&hdsp->lock);
4620
4621         hdsp->capture_pid = -1;
4622         hdsp->capture_substream = NULL;
4623
4624         spin_unlock_irq(&hdsp->lock);
4625         return 0;
4626 }
4627
4628 /* helper functions for copying meter values */
4629 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4630 {
4631         u32 val = readl(src);
4632         return copy_to_user(dest, &val, 4);
4633 }
4634
4635 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4636 {
4637         u32 rms_low, rms_high;
4638         u64 rms;
4639         rms_low = readl(src_low);
4640         rms_high = readl(src_high);
4641         rms = ((u64)rms_high << 32) | rms_low;
4642         return copy_to_user(dest, &rms, 8);
4643 }
4644
4645 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4646 {
4647         u32 rms_low, rms_high;
4648         u64 rms;
4649         rms_low = readl(src_low) & 0xffffff00;
4650         rms_high = readl(src_high) & 0xffffff00;
4651         rms = ((u64)rms_high << 32) | rms_low;
4652         return copy_to_user(dest, &rms, 8);
4653 }
4654
4655 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4656 {
4657         int doublespeed = 0;
4658         int i, j, channels, ofs;
4659
4660         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4661                 doublespeed = 1;
4662         channels = doublespeed ? 14 : 26;
4663         for (i = 0, j = 0; i < 26; ++i) {
4664                 if (doublespeed && (i & 4))
4665                         continue;
4666                 ofs = HDSP_9652_peakBase - j * 4;
4667                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4668                         return -EFAULT;
4669                 ofs -= channels * 4;
4670                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4671                         return -EFAULT;
4672                 ofs -= channels * 4;
4673                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4674                         return -EFAULT;
4675                 ofs = HDSP_9652_rmsBase + j * 8;
4676                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4677                                 hdsp->iobase + ofs + 4))
4678                         return -EFAULT;
4679                 ofs += channels * 8;
4680                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4681                                 hdsp->iobase + ofs + 4))
4682                         return -EFAULT;
4683                 ofs += channels * 8;
4684                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4685                                 hdsp->iobase + ofs + 4))
4686                         return -EFAULT;
4687                 j++;
4688         }
4689         return 0;
4690 }
4691
4692 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4693 {
4694         int i, j;
4695         struct hdsp_9632_meters __iomem *m;
4696         int doublespeed = 0;
4697
4698         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4699                 doublespeed = 1;
4700         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4701         for (i = 0, j = 0; i < 16; ++i, ++j) {
4702                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4703                         return -EFAULT;
4704                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4705                         return -EFAULT;
4706                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4707                         return -EFAULT;
4708                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4709                                 &m->input_rms_high[j]))
4710                         return -EFAULT;
4711                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4712                                 &m->playback_rms_high[j]))
4713                         return -EFAULT;
4714                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4715                                 &m->output_rms_high[j]))
4716                         return -EFAULT;
4717                 if (doublespeed && i == 3) i += 4;
4718         }
4719         return 0;
4720 }
4721
4722 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4723 {
4724         int i;
4725
4726         for (i = 0; i < 26; i++) {
4727                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4728                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4729                         return -EFAULT;
4730                 if (copy_u32_le(&peak_rms->input_peaks[i],
4731                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4732                         return -EFAULT;
4733         }
4734         for (i = 0; i < 28; i++) {
4735                 if (copy_u32_le(&peak_rms->output_peaks[i],
4736                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4737                         return -EFAULT;
4738         }
4739         for (i = 0; i < 26; ++i) {
4740                 if (copy_u64_le(&peak_rms->playback_rms[i],
4741                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4742                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4743                         return -EFAULT;
4744                 if (copy_u64_le(&peak_rms->input_rms[i],
4745                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4746                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4747                         return -EFAULT;
4748         }
4749         return 0;
4750 }
4751
4752 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4753 {
4754         struct hdsp *hdsp = hw->private_data;
4755         void __user *argp = (void __user *)arg;
4756         int err;
4757
4758         switch (cmd) {
4759         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4760                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4761
4762                 err = hdsp_check_for_iobox(hdsp);
4763                 if (err < 0)
4764                         return err;
4765
4766                 err = hdsp_check_for_firmware(hdsp, 1);
4767                 if (err < 0)
4768                         return err;
4769
4770                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4771                         dev_err(hdsp->card->dev,
4772                                 "firmware needs to be uploaded to the card.\n");
4773                         return -EINVAL;
4774                 }
4775
4776                 switch (hdsp->io_type) {
4777                 case H9652:
4778                         return hdsp_9652_get_peak(hdsp, peak_rms);
4779                 case H9632:
4780                         return hdsp_9632_get_peak(hdsp, peak_rms);
4781                 default:
4782                         return hdsp_get_peak(hdsp, peak_rms);
4783                 }
4784         }
4785         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4786                 struct hdsp_config_info info;
4787                 unsigned long flags;
4788                 int i;
4789
4790                 err = hdsp_check_for_iobox(hdsp);
4791                 if (err < 0)
4792                         return err;
4793
4794                 err = hdsp_check_for_firmware(hdsp, 1);
4795                 if (err < 0)
4796                         return err;
4797
4798                 memset(&info, 0, sizeof(info));
4799                 spin_lock_irqsave(&hdsp->lock, flags);
4800                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4801                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4802                 if (hdsp->io_type != H9632)
4803                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4804                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4805                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4806                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4807                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4808                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4809                                 HDSP_SPDIFOpticalOut);
4810                 info.spdif_professional = (unsigned char)
4811                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4812                 info.spdif_emphasis = (unsigned char)
4813                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4814                 info.spdif_nonaudio = (unsigned char)
4815                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4816                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4817                 info.system_sample_rate = hdsp->system_sample_rate;
4818                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4819                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4820                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4821                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4822                 info.line_out = (unsigned char)
4823                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4824                 if (hdsp->io_type == H9632) {
4825                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4826                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4827                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4828                         info.xlr_breakout_cable =
4829                                 (unsigned char)hdsp_toggle_setting(hdsp,
4830                                         HDSP_XLRBreakoutCable);
4831
4832                 } else if (hdsp->io_type == RPM) {
4833                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4834                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4835                 }
4836                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4837                         info.analog_extension_board =
4838                                 (unsigned char)hdsp_toggle_setting(hdsp,
4839                                             HDSP_AnalogExtensionBoard);
4840                 spin_unlock_irqrestore(&hdsp->lock, flags);
4841                 if (copy_to_user(argp, &info, sizeof(info)))
4842                         return -EFAULT;
4843                 break;
4844         }
4845         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4846                 struct hdsp_9632_aeb h9632_aeb;
4847
4848                 if (hdsp->io_type != H9632) return -EINVAL;
4849                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4850                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4851                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4852                         return -EFAULT;
4853                 break;
4854         }
4855         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4856                 struct hdsp_version hdsp_version;
4857                 int err;
4858
4859                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4860                 if (hdsp->io_type == Undefined) {
4861                         err = hdsp_get_iobox_version(hdsp);
4862                         if (err < 0)
4863                                 return err;
4864                 }
4865                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4866                 hdsp_version.io_type = hdsp->io_type;
4867                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4868                 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))
4869                         return -EFAULT;
4870                 break;
4871         }
4872         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4873                 struct hdsp_firmware firmware;
4874                 u32 __user *firmware_data;
4875                 int err;
4876
4877                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4878                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4879                 if (hdsp->io_type == Undefined) return -EINVAL;
4880
4881                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4882                         return -EBUSY;
4883
4884                 dev_info(hdsp->card->dev,
4885                          "initializing firmware upload\n");
4886                 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4887                         return -EFAULT;
4888                 firmware_data = (u32 __user *)firmware.firmware_data;
4889
4890                 if (hdsp_check_for_iobox (hdsp))
4891                         return -EIO;
4892
4893                 if (!hdsp->fw_uploaded) {
4894                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4895                         if (!hdsp->fw_uploaded)
4896                                 return -ENOMEM;
4897                 }
4898
4899                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4900                                    HDSP_FIRMWARE_SIZE)) {
4901                         vfree(hdsp->fw_uploaded);
4902                         hdsp->fw_uploaded = NULL;
4903                         return -EFAULT;
4904                 }
4905
4906                 hdsp->state |= HDSP_FirmwareCached;
4907
4908                 err = snd_hdsp_load_firmware_from_cache(hdsp);
4909                 if (err < 0)
4910                         return err;
4911
4912                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4913                         err = snd_hdsp_enable_io(hdsp);
4914                         if (err < 0)
4915                                 return err;
4916
4917                         snd_hdsp_initialize_channels(hdsp);
4918                         snd_hdsp_initialize_midi_flush(hdsp);
4919
4920                         err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
4921                         if (err < 0) {
4922                                 dev_err(hdsp->card->dev,
4923                                         "error creating alsa devices\n");
4924                                 return err;
4925                         }
4926                 }
4927                 break;
4928         }
4929         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4930                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4931                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4932                         return -EFAULT;
4933                 break;
4934         }
4935         default:
4936                 return -EINVAL;
4937         }
4938         return 0;
4939 }
4940
4941 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4942         .open =         snd_hdsp_playback_open,
4943         .close =        snd_hdsp_playback_release,
4944         .ioctl =        snd_hdsp_ioctl,
4945         .hw_params =    snd_hdsp_hw_params,
4946         .prepare =      snd_hdsp_prepare,
4947         .trigger =      snd_hdsp_trigger,
4948         .pointer =      snd_hdsp_hw_pointer,
4949         .copy_user =    snd_hdsp_playback_copy,
4950         .copy_kernel =  snd_hdsp_playback_copy_kernel,
4951         .fill_silence = snd_hdsp_hw_silence,
4952 };
4953
4954 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4955         .open =         snd_hdsp_capture_open,
4956         .close =        snd_hdsp_capture_release,
4957         .ioctl =        snd_hdsp_ioctl,
4958         .hw_params =    snd_hdsp_hw_params,
4959         .prepare =      snd_hdsp_prepare,
4960         .trigger =      snd_hdsp_trigger,
4961         .pointer =      snd_hdsp_hw_pointer,
4962         .copy_user =    snd_hdsp_capture_copy,
4963         .copy_kernel =  snd_hdsp_capture_copy_kernel,
4964 };
4965
4966 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4967 {
4968         struct snd_hwdep *hw;
4969         int err;
4970
4971         err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);
4972         if (err < 0)
4973                 return err;
4974
4975         hdsp->hwdep = hw;
4976         hw->private_data = hdsp;
4977         strcpy(hw->name, "HDSP hwdep interface");
4978
4979         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4980         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4981
4982         return 0;
4983 }
4984
4985 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4986 {
4987         struct snd_pcm *pcm;
4988         int err;
4989
4990         err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);
4991         if (err < 0)
4992                 return err;
4993
4994         hdsp->pcm = pcm;
4995         pcm->private_data = hdsp;
4996         strcpy(pcm->name, hdsp->card_name);
4997
4998         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4999         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
5000
5001         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
5002
5003         return 0;
5004 }
5005
5006 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
5007 {
5008         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
5009         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5010 }
5011
5012 static int snd_hdsp_enable_io (struct hdsp *hdsp)
5013 {
5014         int i;
5015
5016         if (hdsp_fifo_wait (hdsp, 0, 100)) {
5017                 dev_err(hdsp->card->dev,
5018                         "enable_io fifo_wait failed\n");
5019                 return -EIO;
5020         }
5021
5022         for (i = 0; i < hdsp->max_channels; ++i) {
5023                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5024                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5025         }
5026
5027         return 0;
5028 }
5029
5030 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5031 {
5032         int status, aebi_channels, aebo_channels, i;
5033
5034         switch (hdsp->io_type) {
5035         case Digiface:
5036                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5037                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5038                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5039                 break;
5040
5041         case H9652:
5042                 hdsp->card_name = "RME Hammerfall HDSP 9652";
5043                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5044                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5045                 break;
5046
5047         case H9632:
5048                 status = hdsp_read(hdsp, HDSP_statusRegister);
5049                 /* HDSP_AEBx bits are low when AEB are connected */
5050                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5051                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5052                 hdsp->card_name = "RME Hammerfall HDSP 9632";
5053                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5054                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5055                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5056                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5057                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5058                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5059                 /* Disable loopback of output channels, as the set function
5060                  * only sets on a change we fake all bits (channels) as enabled.
5061                  */
5062                 hdsp->io_loopback = 0xffffffff;
5063                 for (i = 0; i < hdsp->max_channels; ++i)
5064                         hdsp_loopback_set(hdsp, i, false);
5065                 break;
5066
5067         case Multiface:
5068                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5069                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5070                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5071                 break;
5072
5073         case RPM:
5074                 hdsp->card_name = "RME Hammerfall DSP + RPM";
5075                 hdsp->ss_in_channels = RPM_CHANNELS-1;
5076                 hdsp->ss_out_channels = RPM_CHANNELS;
5077                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5078                 hdsp->ds_out_channels = RPM_CHANNELS;
5079                 break;
5080
5081         default:
5082                 /* should never get here */
5083                 break;
5084         }
5085 }
5086
5087 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5088 {
5089         snd_hdsp_flush_midi_input (hdsp, 0);
5090         snd_hdsp_flush_midi_input (hdsp, 1);
5091 }
5092
5093 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5094 {
5095         int err;
5096
5097         err = snd_hdsp_create_pcm(card, hdsp);
5098         if (err < 0) {
5099                 dev_err(card->dev,
5100                         "Error creating pcm interface\n");
5101                 return err;
5102         }
5103
5104
5105         err = snd_hdsp_create_midi(card, hdsp, 0);
5106         if (err < 0) {
5107                 dev_err(card->dev,
5108                         "Error creating first midi interface\n");
5109                 return err;
5110         }
5111
5112         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5113                 err = snd_hdsp_create_midi(card, hdsp, 1);
5114                 if (err < 0) {
5115                         dev_err(card->dev,
5116                                 "Error creating second midi interface\n");
5117                         return err;
5118                 }
5119         }
5120
5121         err = snd_hdsp_create_controls(card, hdsp);
5122         if (err < 0) {
5123                 dev_err(card->dev,
5124                         "Error creating ctl interface\n");
5125                 return err;
5126         }
5127
5128         snd_hdsp_proc_init(hdsp);
5129
5130         hdsp->system_sample_rate = -1;
5131         hdsp->playback_pid = -1;
5132         hdsp->capture_pid = -1;
5133         hdsp->capture_substream = NULL;
5134         hdsp->playback_substream = NULL;
5135
5136         err = snd_hdsp_set_defaults(hdsp);
5137         if (err < 0) {
5138                 dev_err(card->dev,
5139                         "Error setting default values\n");
5140                 return err;
5141         }
5142
5143         if (!(hdsp->state & HDSP_InitializationComplete)) {
5144                 strcpy(card->shortname, "Hammerfall DSP");
5145                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5146                         hdsp->port, hdsp->irq);
5147
5148                 err = snd_card_register(card);
5149                 if (err < 0) {
5150                         dev_err(card->dev,
5151                                 "error registering card\n");
5152                         return err;
5153                 }
5154                 hdsp->state |= HDSP_InitializationComplete;
5155         }
5156
5157         return 0;
5158 }
5159
5160 /* load firmware via hotplug fw loader */
5161 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5162 {
5163         const char *fwfile;
5164         const struct firmware *fw;
5165         int err;
5166
5167         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5168                 return 0;
5169         if (hdsp->io_type == Undefined) {
5170                 err = hdsp_get_iobox_version(hdsp);
5171                 if (err < 0)
5172                         return err;
5173                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5174                         return 0;
5175         }
5176
5177         /* caution: max length of firmware filename is 30! */
5178         switch (hdsp->io_type) {
5179         case RPM:
5180                 fwfile = "/*(DEBLOBBED)*/";
5181                 break;
5182         case Multiface:
5183                 if (hdsp->firmware_rev == 0xa)
5184                         fwfile = "/*(DEBLOBBED)*/";
5185                 else
5186                         fwfile = "/*(DEBLOBBED)*/";
5187                 break;
5188         case Digiface:
5189                 if (hdsp->firmware_rev == 0xa)
5190                         fwfile = "/*(DEBLOBBED)*/";
5191                 else
5192                         fwfile = "/*(DEBLOBBED)*/";
5193                 break;
5194         default:
5195                 dev_err(hdsp->card->dev,
5196                         "invalid io_type %d\n", hdsp->io_type);
5197                 return -EINVAL;
5198         }
5199
5200         if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5201                 dev_err(hdsp->card->dev,
5202                         "cannot load firmware %s\n", fwfile);
5203                 return -ENOENT;
5204         }
5205         if (fw->size < HDSP_FIRMWARE_SIZE) {
5206                 dev_err(hdsp->card->dev,
5207                         "too short firmware size %d (expected %d)\n",
5208                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5209                 release_firmware(fw);
5210                 return -EINVAL;
5211         }
5212
5213         hdsp->firmware = fw;
5214
5215         hdsp->state |= HDSP_FirmwareCached;
5216
5217         err = snd_hdsp_load_firmware_from_cache(hdsp);
5218         if (err < 0)
5219                 return err;
5220
5221         if (!(hdsp->state & HDSP_InitializationComplete)) {
5222                 err = snd_hdsp_enable_io(hdsp);
5223                 if (err < 0)
5224                         return err;
5225
5226                 err = snd_hdsp_create_hwdep(hdsp->card, hdsp);
5227                 if (err < 0) {
5228                         dev_err(hdsp->card->dev,
5229                                 "error creating hwdep device\n");
5230                         return err;
5231                 }
5232                 snd_hdsp_initialize_channels(hdsp);
5233                 snd_hdsp_initialize_midi_flush(hdsp);
5234                 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
5235                 if (err < 0) {
5236                         dev_err(hdsp->card->dev,
5237                                 "error creating alsa devices\n");
5238                         return err;
5239                 }
5240         }
5241         return 0;
5242 }
5243
5244 static int snd_hdsp_create(struct snd_card *card,
5245                            struct hdsp *hdsp)
5246 {
5247         struct pci_dev *pci = hdsp->pci;
5248         int err;
5249         int is_9652 = 0;
5250         int is_9632 = 0;
5251
5252         hdsp->irq = -1;
5253         hdsp->state = 0;
5254         hdsp->midi[0].rmidi = NULL;
5255         hdsp->midi[1].rmidi = NULL;
5256         hdsp->midi[0].input = NULL;
5257         hdsp->midi[1].input = NULL;
5258         hdsp->midi[0].output = NULL;
5259         hdsp->midi[1].output = NULL;
5260         hdsp->midi[0].pending = 0;
5261         hdsp->midi[1].pending = 0;
5262         spin_lock_init(&hdsp->midi[0].lock);
5263         spin_lock_init(&hdsp->midi[1].lock);
5264         hdsp->iobase = NULL;
5265         hdsp->control_register = 0;
5266         hdsp->control2_register = 0;
5267         hdsp->io_type = Undefined;
5268         hdsp->max_channels = 26;
5269
5270         hdsp->card = card;
5271
5272         spin_lock_init(&hdsp->lock);
5273
5274         INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5275
5276         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5277         hdsp->firmware_rev &= 0xff;
5278
5279         /* From Martin Bjoernsen :
5280             "It is important that the card's latency timer register in
5281             the PCI configuration space is set to a value much larger
5282             than 0 by the computer's BIOS or the driver.
5283             The windows driver always sets this 8 bit register [...]
5284             to its maximum 255 to avoid problems with some computers."
5285         */
5286         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5287
5288         strcpy(card->driver, "H-DSP");
5289         strcpy(card->mixername, "Xilinx FPGA");
5290
5291         if (hdsp->firmware_rev < 0xa)
5292                 return -ENODEV;
5293         else if (hdsp->firmware_rev < 0x64)
5294                 hdsp->card_name = "RME Hammerfall DSP";
5295         else if (hdsp->firmware_rev < 0x96) {
5296                 hdsp->card_name = "RME HDSP 9652";
5297                 is_9652 = 1;
5298         } else {
5299                 hdsp->card_name = "RME HDSP 9632";
5300                 hdsp->max_channels = 16;
5301                 is_9632 = 1;
5302         }
5303
5304         err = pcim_enable_device(pci);
5305         if (err < 0)
5306                 return err;
5307
5308         pci_set_master(hdsp->pci);
5309
5310         err = pci_request_regions(pci, "hdsp");
5311         if (err < 0)
5312                 return err;
5313         hdsp->port = pci_resource_start(pci, 0);
5314         hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);
5315         if (!hdsp->iobase) {
5316                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5317                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5318                 return -EBUSY;
5319         }
5320
5321         if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,
5322                              IRQF_SHARED, KBUILD_MODNAME, hdsp)) {
5323                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5324                 return -EBUSY;
5325         }
5326
5327         hdsp->irq = pci->irq;
5328         card->sync_irq = hdsp->irq;
5329         hdsp->precise_ptr = 0;
5330         hdsp->use_midi_work = 1;
5331         hdsp->dds_value = 0;
5332
5333         err = snd_hdsp_initialize_memory(hdsp);
5334         if (err < 0)
5335                 return err;
5336
5337         if (!is_9652 && !is_9632) {
5338                 /* we wait a maximum of 10 seconds to let freshly
5339                  * inserted cardbus cards do their hardware init */
5340                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5341
5342                 if (err < 0)
5343                         return err;
5344
5345                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5346                         err = hdsp_request_fw_loader(hdsp);
5347                         if (err < 0)
5348                                 /* we don't fail as this can happen
5349                                    if userspace is not ready for
5350                                    firmware upload
5351                                 */
5352                                 dev_err(hdsp->card->dev,
5353                                         "couldn't get firmware from userspace. try using hdsploader\n");
5354                         else
5355                                 /* init is complete, we return */
5356                                 return 0;
5357                         /* we defer initialization */
5358                         dev_info(hdsp->card->dev,
5359                                  "card initialization pending : waiting for firmware\n");
5360                         err = snd_hdsp_create_hwdep(card, hdsp);
5361                         if (err < 0)
5362                                 return err;
5363                         return 0;
5364                 } else {
5365                         dev_info(hdsp->card->dev,
5366                                  "Firmware already present, initializing card.\n");
5367                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5368                                 hdsp->io_type = RPM;
5369                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5370                                 hdsp->io_type = Multiface;
5371                         else
5372                                 hdsp->io_type = Digiface;
5373                 }
5374         }
5375
5376         err = snd_hdsp_enable_io(hdsp);
5377         if (err)
5378                 return err;
5379
5380         if (is_9652)
5381                 hdsp->io_type = H9652;
5382
5383         if (is_9632)
5384                 hdsp->io_type = H9632;
5385
5386         err = snd_hdsp_create_hwdep(card, hdsp);
5387         if (err < 0)
5388                 return err;
5389
5390         snd_hdsp_initialize_channels(hdsp);
5391         snd_hdsp_initialize_midi_flush(hdsp);
5392
5393         hdsp->state |= HDSP_FirmwareLoaded;
5394
5395         err = snd_hdsp_create_alsa_devices(card, hdsp);
5396         if (err < 0)
5397                 return err;
5398
5399         return 0;
5400 }
5401
5402 static void snd_hdsp_card_free(struct snd_card *card)
5403 {
5404         struct hdsp *hdsp = card->private_data;
5405
5406         if (hdsp->port) {
5407                 /* stop the audio, and cancel all interrupts */
5408                 cancel_work_sync(&hdsp->midi_work);
5409                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5410                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5411         }
5412
5413         release_firmware(hdsp->firmware);
5414         vfree(hdsp->fw_uploaded);
5415 }
5416
5417 static int snd_hdsp_probe(struct pci_dev *pci,
5418                           const struct pci_device_id *pci_id)
5419 {
5420         static int dev;
5421         struct hdsp *hdsp;
5422         struct snd_card *card;
5423         int err;
5424
5425         if (dev >= SNDRV_CARDS)
5426                 return -ENODEV;
5427         if (!enable[dev]) {
5428                 dev++;
5429                 return -ENOENT;
5430         }
5431
5432         err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5433                                 sizeof(struct hdsp), &card);
5434         if (err < 0)
5435                 return err;
5436
5437         hdsp = card->private_data;
5438         card->private_free = snd_hdsp_card_free;
5439         hdsp->dev = dev;
5440         hdsp->pci = pci;
5441         err = snd_hdsp_create(card, hdsp);
5442         if (err)
5443                 goto error;
5444
5445         strcpy(card->shortname, "Hammerfall DSP");
5446         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5447                 hdsp->port, hdsp->irq);
5448         err = snd_card_register(card);
5449         if (err)
5450                 goto error;
5451         pci_set_drvdata(pci, card);
5452         dev++;
5453         return 0;
5454
5455  error:
5456         snd_card_free(card);
5457         return err;
5458 }
5459
5460 static struct pci_driver hdsp_driver = {
5461         .name =     KBUILD_MODNAME,
5462         .id_table = snd_hdsp_ids,
5463         .probe =    snd_hdsp_probe,
5464 };
5465
5466 module_pci_driver(hdsp_driver);