2 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 * Copyright (c) 2002 Paul Davis
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
33 #include <linux/nospec.h>
35 #include <sound/core.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/info.h>
39 #include <sound/asoundef.h>
40 #include <sound/rawmidi.h>
41 #include <sound/hwdep.h>
42 #include <sound/initval.h>
43 #include <sound/hdsp.h>
45 #include <asm/byteorder.h>
46 #include <asm/current.h>
48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
52 module_param_array(index, int, NULL, 0444);
53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
54 module_param_array(id, charp, NULL, 0444);
55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
56 module_param_array(enable, bool, NULL, 0444);
57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
59 MODULE_DESCRIPTION("RME Hammerfall DSP");
60 MODULE_LICENSE("GPL");
61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
66 #define HDSP_MAX_CHANNELS 26
67 #define HDSP_MAX_DS_CHANNELS 14
68 #define HDSP_MAX_QS_CHANNELS 8
69 #define DIGIFACE_SS_CHANNELS 26
70 #define DIGIFACE_DS_CHANNELS 14
71 #define MULTIFACE_SS_CHANNELS 18
72 #define MULTIFACE_DS_CHANNELS 14
73 #define H9652_SS_CHANNELS 26
74 #define H9652_DS_CHANNELS 14
75 /* This does not include possible Analog Extension Boards
76 AEBs are detected at card initialization
78 #define H9632_SS_CHANNELS 12
79 #define H9632_DS_CHANNELS 8
80 #define H9632_QS_CHANNELS 4
81 #define RPM_CHANNELS 6
83 /* Write registers. These are defined as byte-offsets from the iobase value.
85 #define HDSP_resetPointer 0
86 #define HDSP_freqReg 0
87 #define HDSP_outputBufferAddress 32
88 #define HDSP_inputBufferAddress 36
89 #define HDSP_controlRegister 64
90 #define HDSP_interruptConfirmation 96
91 #define HDSP_outputEnable 128
92 #define HDSP_control2Reg 256
93 #define HDSP_midiDataOut0 352
94 #define HDSP_midiDataOut1 356
95 #define HDSP_fifoData 368
96 #define HDSP_inputEnable 384
98 /* Read registers. These are defined as byte-offsets from the iobase value
101 #define HDSP_statusRegister 0
102 #define HDSP_timecode 128
103 #define HDSP_status2Register 192
104 #define HDSP_midiDataIn0 360
105 #define HDSP_midiDataIn1 364
106 #define HDSP_midiStatusOut0 384
107 #define HDSP_midiStatusOut1 388
108 #define HDSP_midiStatusIn0 392
109 #define HDSP_midiStatusIn1 396
110 #define HDSP_fifoStatus 400
112 /* the meters are regular i/o-mapped registers, but offset
113 considerably from the rest. the peak registers are reset
114 when read; the least-significant 4 bits are full-scale counters;
115 the actual peak value is in the most-significant 24 bits.
118 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
119 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
120 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
121 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
122 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
125 /* This is for H9652 cards
126 Peak values are read downward from the base
127 Rms values are read upward
128 There are rms values for the outputs too
129 26*3 values are read in ss mode
130 14*3 in ds mode, with no gap between values
132 #define HDSP_9652_peakBase 7164
133 #define HDSP_9652_rmsBase 4096
135 /* c.f. the hdsp_9632_meters_t struct */
136 #define HDSP_9632_metersBase 4096
138 #define HDSP_IO_EXTENT 7168
140 /* control2 register bits */
142 #define HDSP_TMS 0x01
143 #define HDSP_TCK 0x02
144 #define HDSP_TDI 0x04
145 #define HDSP_JTAG 0x08
146 #define HDSP_PWDN 0x10
147 #define HDSP_PROGRAM 0x020
148 #define HDSP_CONFIG_MODE_0 0x040
149 #define HDSP_CONFIG_MODE_1 0x080
150 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
151 #define HDSP_BIGENDIAN_MODE 0x200
152 #define HDSP_RD_MULTIPLE 0x400
153 #define HDSP_9652_ENABLE_MIXER 0x800
154 #define HDSP_S200 0x800
155 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
156 #define HDSP_CYCLIC_MODE 0x1000
157 #define HDSP_TDO 0x10000000
159 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
160 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
162 /* Control Register bits */
164 #define HDSP_Start (1<<0) /* start engine */
165 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
166 #define HDSP_Latency1 (1<<2) /* [ see above ] */
167 #define HDSP_Latency2 (1<<3) /* [ see above ] */
168 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
169 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
170 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
171 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
172 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
173 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
174 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
175 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
176 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
177 #define HDSP_SyncRef2 (1<<13)
178 #define HDSP_SPDIFInputSelect0 (1<<14)
179 #define HDSP_SPDIFInputSelect1 (1<<15)
180 #define HDSP_SyncRef0 (1<<16)
181 #define HDSP_SyncRef1 (1<<17)
182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
183 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
184 #define HDSP_Midi0InterruptEnable (1<<22)
185 #define HDSP_Midi1InterruptEnable (1<<23)
186 #define HDSP_LineOut (1<<24)
187 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
188 #define HDSP_ADGain1 (1<<26)
189 #define HDSP_DAGain0 (1<<27)
190 #define HDSP_DAGain1 (1<<28)
191 #define HDSP_PhoneGain0 (1<<29)
192 #define HDSP_PhoneGain1 (1<<30)
193 #define HDSP_QuadSpeed (1<<31)
195 /* RPM uses some of the registers for special purposes */
196 #define HDSP_RPM_Inp12 0x04A00
197 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
198 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
199 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
200 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
201 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
203 #define HDSP_RPM_Inp34 0x32000
204 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
205 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
206 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
207 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
208 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
210 #define HDSP_RPM_Bypass 0x01000
212 #define HDSP_RPM_Disconnect 0x00001
214 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
215 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
216 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
217 #define HDSP_ADGainLowGain 0
219 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
220 #define HDSP_DAGainHighGain HDSP_DAGainMask
221 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
222 #define HDSP_DAGainMinus10dBV 0
224 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
225 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
226 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
227 #define HDSP_PhoneGainMinus12dB 0
229 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
230 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
232 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
233 #define HDSP_SPDIFInputADAT1 0
234 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
235 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
238 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
239 #define HDSP_SyncRef_ADAT1 0
240 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
241 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
242 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
243 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
244 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
246 /* Sample Clock Sources */
248 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
249 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
250 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
251 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
252 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
253 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
254 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
255 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
256 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
257 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
259 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
261 #define HDSP_SYNC_FROM_WORD 0
262 #define HDSP_SYNC_FROM_SPDIF 1
263 #define HDSP_SYNC_FROM_ADAT1 2
264 #define HDSP_SYNC_FROM_ADAT_SYNC 3
265 #define HDSP_SYNC_FROM_ADAT2 4
266 #define HDSP_SYNC_FROM_ADAT3 5
268 /* SyncCheck status */
270 #define HDSP_SYNC_CHECK_NO_LOCK 0
271 #define HDSP_SYNC_CHECK_LOCK 1
272 #define HDSP_SYNC_CHECK_SYNC 2
274 /* AutoSync references - used by "autosync_ref" control switch */
276 #define HDSP_AUTOSYNC_FROM_WORD 0
277 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
278 #define HDSP_AUTOSYNC_FROM_SPDIF 2
279 #define HDSP_AUTOSYNC_FROM_NONE 3
280 #define HDSP_AUTOSYNC_FROM_ADAT1 4
281 #define HDSP_AUTOSYNC_FROM_ADAT2 5
282 #define HDSP_AUTOSYNC_FROM_ADAT3 6
284 /* Possible sources of S/PDIF input */
286 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
287 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
288 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
289 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
291 #define HDSP_Frequency32KHz HDSP_Frequency0
292 #define HDSP_Frequency44_1KHz HDSP_Frequency1
293 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
294 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
295 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
296 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
297 /* For H9632 cards */
298 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
299 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
300 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
301 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
302 return 104857600000000 / rate; // 100 MHz
303 return 110100480000000 / rate; // 105 MHz
305 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
307 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
308 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
310 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
311 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
313 /* Status Register bits */
315 #define HDSP_audioIRQPending (1<<0)
316 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
317 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
318 #define HDSP_Lock1 (1<<2)
319 #define HDSP_Lock0 (1<<3)
320 #define HDSP_SPDIFSync (1<<4)
321 #define HDSP_TimecodeLock (1<<5)
322 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
323 #define HDSP_Sync2 (1<<16)
324 #define HDSP_Sync1 (1<<17)
325 #define HDSP_Sync0 (1<<18)
326 #define HDSP_DoubleSpeedStatus (1<<19)
327 #define HDSP_ConfigError (1<<20)
328 #define HDSP_DllError (1<<21)
329 #define HDSP_spdifFrequency0 (1<<22)
330 #define HDSP_spdifFrequency1 (1<<23)
331 #define HDSP_spdifFrequency2 (1<<24)
332 #define HDSP_SPDIFErrorFlag (1<<25)
333 #define HDSP_BufferID (1<<26)
334 #define HDSP_TimecodeSync (1<<27)
335 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
336 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
337 #define HDSP_midi0IRQPending (1<<30)
338 #define HDSP_midi1IRQPending (1<<31)
340 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
342 HDSP_spdifFrequency1|\
343 HDSP_spdifFrequency2|\
344 HDSP_spdifFrequency3)
346 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
347 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
348 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
350 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
351 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
352 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
354 /* This is for H9632 cards */
355 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
356 HDSP_spdifFrequency1|\
357 HDSP_spdifFrequency2)
358 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
359 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
361 /* Status2 Register bits */
363 #define HDSP_version0 (1<<0)
364 #define HDSP_version1 (1<<1)
365 #define HDSP_version2 (1<<2)
366 #define HDSP_wc_lock (1<<3)
367 #define HDSP_wc_sync (1<<4)
368 #define HDSP_inp_freq0 (1<<5)
369 #define HDSP_inp_freq1 (1<<6)
370 #define HDSP_inp_freq2 (1<<7)
371 #define HDSP_SelSyncRef0 (1<<8)
372 #define HDSP_SelSyncRef1 (1<<9)
373 #define HDSP_SelSyncRef2 (1<<10)
375 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
377 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
378 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
379 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
380 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
381 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
382 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
383 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
384 /* FIXME : more values for 9632 cards ? */
386 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
387 #define HDSP_SelSyncRef_ADAT1 0
388 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
389 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
390 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
391 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
392 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
394 /* Card state flags */
396 #define HDSP_InitializationComplete (1<<0)
397 #define HDSP_FirmwareLoaded (1<<1)
398 #define HDSP_FirmwareCached (1<<2)
400 /* FIFO wait times, defined in terms of 1/10ths of msecs */
402 #define HDSP_LONG_WAIT 5000
403 #define HDSP_SHORT_WAIT 30
405 #define UNITY_GAIN 32768
406 #define MINUS_INFINITY_GAIN 0
408 /* the size of a substream (1 mono data stream) */
410 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
411 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
413 /* the size of the area we need to allocate for DMA transfers. the
414 size is the same regardless of the number of channels - the
415 Multiface still uses the same memory area.
417 Note that we allocate 1 more channel than is apparently needed
418 because the h/w seems to write 1 byte beyond the end of the last
422 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
423 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
425 #define HDSP_FIRMWARE_SIZE (24413 * 4)
427 struct hdsp_9632_meters {
429 u32 playback_peak[16];
433 u32 input_rms_low[16];
434 u32 playback_rms_low[16];
435 u32 output_rms_low[16];
437 u32 input_rms_high[16];
438 u32 playback_rms_high[16];
439 u32 output_rms_high[16];
440 u32 xxx_rms_high[16];
446 struct snd_rawmidi *rmidi;
447 struct snd_rawmidi_substream *input;
448 struct snd_rawmidi_substream *output;
449 char istimer; /* timer in use */
450 struct timer_list timer;
457 struct snd_pcm_substream *capture_substream;
458 struct snd_pcm_substream *playback_substream;
459 struct hdsp_midi midi[2];
460 struct tasklet_struct midi_tasklet;
461 int use_midi_tasklet;
463 u32 control_register; /* cached value */
464 u32 control2_register; /* cached value */
466 u32 creg_spdif_stream;
467 int clock_source_locked;
468 char *card_name; /* digiface/multiface/rpm */
469 enum HDSP_IO_Type io_type; /* ditto, but for code use */
470 unsigned short firmware_rev;
471 unsigned short state; /* stores state bits */
472 const struct firmware *firmware;
474 size_t period_bytes; /* guess what this is */
475 unsigned char max_channels;
476 unsigned char qs_in_channels; /* quad speed mode for H9632 */
477 unsigned char ds_in_channels;
478 unsigned char ss_in_channels; /* different for multiface/digiface */
479 unsigned char qs_out_channels;
480 unsigned char ds_out_channels;
481 unsigned char ss_out_channels;
483 struct snd_dma_buffer capture_dma_buf;
484 struct snd_dma_buffer playback_dma_buf;
485 unsigned char *capture_buffer; /* suitably aligned address */
486 unsigned char *playback_buffer; /* suitably aligned address */
491 int system_sample_rate;
496 void __iomem *iobase;
497 struct snd_card *card;
499 struct snd_hwdep *hwdep;
501 struct snd_kcontrol *spdif_ctl;
502 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
503 unsigned int dds_value; /* last value written to freq register */
506 /* These tables map the ALSA channels 1..N to the channels that we
507 need to use in order to find the relevant channel buffer. RME
508 refer to this kind of mapping as between "the ADAT channel and
509 the DMA channel." We index it using the logical audio channel,
510 and the value is the DMA channel (i.e. channel buffer number)
511 where the data for that channel can be read/written from/to.
514 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
515 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
516 18, 19, 20, 21, 22, 23, 24, 25
519 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
521 0, 1, 2, 3, 4, 5, 6, 7,
523 16, 17, 18, 19, 20, 21, 22, 23,
526 -1, -1, -1, -1, -1, -1, -1, -1
529 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
530 /* ADAT channels are remapped */
531 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
532 /* channels 12 and 13 are S/PDIF */
534 /* others don't exist */
535 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
538 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
540 0, 1, 2, 3, 4, 5, 6, 7,
545 /* AO4S-192 and AI4S-192 extension boards */
547 /* others don't exist */
548 -1, -1, -1, -1, -1, -1, -1, -1,
552 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
559 /* AO4S-192 and AI4S-192 extension boards */
561 /* others don't exist */
562 -1, -1, -1, -1, -1, -1, -1, -1,
563 -1, -1, -1, -1, -1, -1
566 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
567 /* ADAT is disabled in this mode */
572 /* AO4S-192 and AI4S-192 extension boards */
574 /* others don't exist */
575 -1, -1, -1, -1, -1, -1, -1, -1,
576 -1, -1, -1, -1, -1, -1, -1, -1,
580 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
582 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
583 dmab->dev.dev = snd_dma_pci_data(pci);
584 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
590 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
593 snd_dma_free_pages(dmab);
597 static const struct pci_device_id snd_hdsp_ids[] = {
599 .vendor = PCI_VENDOR_ID_XILINX,
600 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
601 .subvendor = PCI_ANY_ID,
602 .subdevice = PCI_ANY_ID,
603 }, /* RME Hammerfall-DSP */
607 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
610 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
611 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
612 static int snd_hdsp_enable_io (struct hdsp *hdsp);
613 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
614 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
615 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
616 static int hdsp_autosync_ref(struct hdsp *hdsp);
617 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
618 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
620 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
622 switch (hdsp->io_type) {
627 if (hdsp->firmware_rev == 0xa)
628 return (64 * out) + (32 + (in));
630 return (52 * out) + (26 + (in));
632 return (32 * out) + (16 + (in));
634 return (52 * out) + (26 + (in));
638 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
640 switch (hdsp->io_type) {
645 if (hdsp->firmware_rev == 0xa)
646 return (64 * out) + in;
648 return (52 * out) + in;
650 return (32 * out) + in;
652 return (52 * out) + in;
656 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
658 writel(val, hdsp->iobase + reg);
661 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
663 return readl (hdsp->iobase + reg);
666 static int hdsp_check_for_iobox (struct hdsp *hdsp)
670 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
671 for (i = 0; i < 500; i++) {
672 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
675 dev_dbg(hdsp->card->dev,
676 "IO box found after %d ms\n",
683 dev_err(hdsp->card->dev, "no IO box connected!\n");
684 hdsp->state &= ~HDSP_FirmwareLoaded;
688 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
693 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
696 for (i = 0; i != loops; ++i) {
697 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
700 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
706 dev_info(hdsp->card->dev, "no IO box connected!\n");
707 hdsp->state &= ~HDSP_FirmwareLoaded;
711 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
717 if (hdsp->fw_uploaded)
718 cache = hdsp->fw_uploaded;
722 cache = (u32 *)hdsp->firmware->data;
727 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
729 dev_info(hdsp->card->dev, "loading firmware\n");
731 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
732 hdsp_write (hdsp, HDSP_fifoData, 0);
734 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
735 dev_info(hdsp->card->dev,
736 "timeout waiting for download preparation\n");
737 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
741 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
743 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
744 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
745 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
746 dev_info(hdsp->card->dev,
747 "timeout during firmware loading\n");
748 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
753 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
754 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
757 #ifdef SNDRV_BIG_ENDIAN
758 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
760 hdsp->control2_register = 0;
762 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
763 dev_info(hdsp->card->dev, "finished firmware loading\n");
766 if (hdsp->state & HDSP_InitializationComplete) {
767 dev_info(hdsp->card->dev,
768 "firmware loaded from cache, restoring defaults\n");
769 spin_lock_irqsave(&hdsp->lock, flags);
770 snd_hdsp_set_defaults(hdsp);
771 spin_unlock_irqrestore(&hdsp->lock, flags);
774 hdsp->state |= HDSP_FirmwareLoaded;
779 static int hdsp_get_iobox_version (struct hdsp *hdsp)
781 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
783 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
784 hdsp_write(hdsp, HDSP_fifoData, 0);
786 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
792 hdsp_write (hdsp, HDSP_fifoData, 0);
793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
794 hdsp->io_type = Multiface;
795 dev_info(hdsp->card->dev, "Multiface found\n");
799 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
800 hdsp_write(hdsp, HDSP_fifoData, 0);
801 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
802 hdsp->io_type = Digiface;
803 dev_info(hdsp->card->dev, "Digiface found\n");
807 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
808 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
809 hdsp_write(hdsp, HDSP_fifoData, 0);
810 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
811 hdsp->io_type = Multiface;
812 dev_info(hdsp->card->dev, "Multiface found\n");
816 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
817 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
818 hdsp_write(hdsp, HDSP_fifoData, 0);
819 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
820 hdsp->io_type = Multiface;
821 dev_info(hdsp->card->dev, "Multiface found\n");
826 dev_info(hdsp->card->dev, "RPM found\n");
829 /* firmware was already loaded, get iobox type */
830 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
832 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
833 hdsp->io_type = Multiface;
835 hdsp->io_type = Digiface;
841 static int hdsp_request_fw_loader(struct hdsp *hdsp);
843 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
845 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
847 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
848 hdsp->state &= ~HDSP_FirmwareLoaded;
849 if (! load_on_demand)
851 dev_err(hdsp->card->dev, "firmware not present.\n");
852 /* try to load firmware */
853 if (! (hdsp->state & HDSP_FirmwareCached)) {
854 if (! hdsp_request_fw_loader(hdsp))
856 dev_err(hdsp->card->dev,
857 "No firmware loaded nor cached, please upload firmware.\n");
860 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
861 dev_err(hdsp->card->dev,
862 "Firmware loading from cache failed, please upload manually.\n");
870 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
874 /* the fifoStatus registers reports on how many words
875 are available in the command FIFO.
878 for (i = 0; i < timeout; i++) {
880 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
883 /* not very friendly, but we only do this during a firmware
884 load and changing the mixer, so we just put up with it.
890 dev_warn(hdsp->card->dev,
891 "wait for FIFO status <= %d failed after %d iterations\n",
896 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
898 if (addr >= HDSP_MATRIX_MIXER_SIZE)
901 return hdsp->mixer_matrix[addr];
904 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
908 if (addr >= HDSP_MATRIX_MIXER_SIZE)
911 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
913 /* from martin bjornsen:
915 "You can only write dwords to the
916 mixer memory which contain two
917 mixer values in the low and high
918 word. So if you want to change
919 value 0 you have to read value 1
920 from the cache and write both to
921 the first dword in the mixer
925 if (hdsp->io_type == H9632 && addr >= 512)
928 if (hdsp->io_type == H9652 && addr >= 1352)
931 hdsp->mixer_matrix[addr] = data;
934 /* `addr' addresses a 16-bit wide address, but
935 the address space accessed via hdsp_write
936 uses byte offsets. put another way, addr
937 varies from 0 to 1351, but to access the
938 corresponding memory location, we need
939 to access 0 to 2703 ...
943 hdsp_write (hdsp, 4096 + (ad*4),
944 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
945 hdsp->mixer_matrix[addr&0x7fe]);
951 ad = (addr << 16) + data;
953 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
956 hdsp_write (hdsp, HDSP_fifoData, ad);
957 hdsp->mixer_matrix[addr] = data;
964 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
969 spin_lock_irqsave(&hdsp->lock, flags);
970 if ((hdsp->playback_pid != hdsp->capture_pid) &&
971 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
973 spin_unlock_irqrestore(&hdsp->lock, flags);
977 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
979 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
980 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
982 /* For the 9632, the mask is different */
983 if (hdsp->io_type == H9632)
984 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
986 if (status & HDSP_SPDIFErrorFlag)
990 case HDSP_spdifFrequency32KHz: return 32000;
991 case HDSP_spdifFrequency44_1KHz: return 44100;
992 case HDSP_spdifFrequency48KHz: return 48000;
993 case HDSP_spdifFrequency64KHz: return 64000;
994 case HDSP_spdifFrequency88_2KHz: return 88200;
995 case HDSP_spdifFrequency96KHz: return 96000;
996 case HDSP_spdifFrequency128KHz:
997 if (hdsp->io_type == H9632) return 128000;
999 case HDSP_spdifFrequency176_4KHz:
1000 if (hdsp->io_type == H9632) return 176400;
1002 case HDSP_spdifFrequency192KHz:
1003 if (hdsp->io_type == H9632) return 192000;
1008 dev_warn(hdsp->card->dev,
1009 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1014 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1016 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1017 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1019 /* For the 9632 card, there seems to be no bit for indicating external
1020 * sample rate greater than 96kHz. The card reports the corresponding
1021 * single speed. So the best means seems to get spdif rate when
1022 * autosync reference is spdif */
1023 if (hdsp->io_type == H9632 &&
1024 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1025 return hdsp_spdif_sample_rate(hdsp);
1027 switch (rate_bits) {
1028 case HDSP_systemFrequency32: return 32000;
1029 case HDSP_systemFrequency44_1: return 44100;
1030 case HDSP_systemFrequency48: return 48000;
1031 case HDSP_systemFrequency64: return 64000;
1032 case HDSP_systemFrequency88_2: return 88200;
1033 case HDSP_systemFrequency96: return 96000;
1039 static void hdsp_compute_period_size(struct hdsp *hdsp)
1041 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1044 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1048 position = hdsp_read(hdsp, HDSP_statusRegister);
1050 if (!hdsp->precise_ptr)
1051 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1053 position &= HDSP_BufferPositionMask;
1055 position &= (hdsp->period_bytes/2) - 1;
1059 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1061 hdsp_write (hdsp, HDSP_resetPointer, 0);
1062 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1063 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1064 * requires (?) to write again DDS value after a reset pointer
1065 * (at least, it works like this) */
1066 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1069 static void hdsp_start_audio(struct hdsp *s)
1071 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1072 hdsp_write(s, HDSP_controlRegister, s->control_register);
1075 static void hdsp_stop_audio(struct hdsp *s)
1077 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1078 hdsp_write(s, HDSP_controlRegister, s->control_register);
1081 static void hdsp_silence_playback(struct hdsp *hdsp)
1083 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1086 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1090 spin_lock_irq(&s->lock);
1099 s->control_register &= ~HDSP_LatencyMask;
1100 s->control_register |= hdsp_encode_latency(n);
1102 hdsp_write(s, HDSP_controlRegister, s->control_register);
1104 hdsp_compute_period_size(s);
1106 spin_unlock_irq(&s->lock);
1111 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1117 else if (rate >= 56000)
1121 n = div_u64(n, rate);
1122 /* n should be less than 2^32 for being written to FREQ register */
1123 snd_BUG_ON(n >> 32);
1124 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1125 value to write it after a reset */
1126 hdsp->dds_value = n;
1127 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1130 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1132 int reject_if_open = 0;
1136 /* ASSUMPTION: hdsp->lock is either held, or
1137 there is no need for it (e.g. during module
1141 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1142 if (called_internally) {
1143 /* request from ctl or card initialization */
1144 dev_err(hdsp->card->dev,
1145 "device is not running as a clock master: cannot set sample rate.\n");
1148 /* hw_param request while in AutoSync mode */
1149 int external_freq = hdsp_external_sample_rate(hdsp);
1150 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1152 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1153 dev_info(hdsp->card->dev,
1154 "Detected ADAT in double speed mode\n");
1155 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156 dev_info(hdsp->card->dev,
1157 "Detected ADAT in quad speed mode\n");
1158 else if (rate != external_freq) {
1159 dev_info(hdsp->card->dev,
1160 "No AutoSync source for requested rate\n");
1166 current_rate = hdsp->system_sample_rate;
1168 /* Changing from a "single speed" to a "double speed" rate is
1169 not allowed if any substreams are open. This is because
1170 such a change causes a shift in the location of
1171 the DMA buffers and a reduction in the number of available
1174 Note that a similar but essentially insoluble problem
1175 exists for externally-driven rate changes. All we can do
1176 is to flag rate changes in the read/write routines. */
1178 if (rate > 96000 && hdsp->io_type != H9632)
1183 if (current_rate > 48000)
1185 rate_bits = HDSP_Frequency32KHz;
1188 if (current_rate > 48000)
1190 rate_bits = HDSP_Frequency44_1KHz;
1193 if (current_rate > 48000)
1195 rate_bits = HDSP_Frequency48KHz;
1198 if (current_rate <= 48000 || current_rate > 96000)
1200 rate_bits = HDSP_Frequency64KHz;
1203 if (current_rate <= 48000 || current_rate > 96000)
1205 rate_bits = HDSP_Frequency88_2KHz;
1208 if (current_rate <= 48000 || current_rate > 96000)
1210 rate_bits = HDSP_Frequency96KHz;
1213 if (current_rate < 128000)
1215 rate_bits = HDSP_Frequency128KHz;
1218 if (current_rate < 128000)
1220 rate_bits = HDSP_Frequency176_4KHz;
1223 if (current_rate < 128000)
1225 rate_bits = HDSP_Frequency192KHz;
1231 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1232 dev_warn(hdsp->card->dev,
1233 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1235 hdsp->playback_pid);
1239 hdsp->control_register &= ~HDSP_FrequencyMask;
1240 hdsp->control_register |= rate_bits;
1241 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1243 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1244 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1245 hdsp_set_dds_value(hdsp, rate);
1247 if (rate >= 128000) {
1248 hdsp->channel_map = channel_map_H9632_qs;
1249 } else if (rate > 48000) {
1250 if (hdsp->io_type == H9632)
1251 hdsp->channel_map = channel_map_H9632_ds;
1253 hdsp->channel_map = channel_map_ds;
1255 switch (hdsp->io_type) {
1258 hdsp->channel_map = channel_map_mf_ss;
1262 hdsp->channel_map = channel_map_df_ss;
1265 hdsp->channel_map = channel_map_H9632_ss;
1268 /* should never happen */
1273 hdsp->system_sample_rate = rate;
1278 /*----------------------------------------------------------------------------
1280 ----------------------------------------------------------------------------*/
1282 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1284 /* the hardware already does the relevant bit-mask with 0xff */
1286 return hdsp_read(hdsp, HDSP_midiDataIn1);
1288 return hdsp_read(hdsp, HDSP_midiDataIn0);
1291 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1293 /* the hardware already does the relevant bit-mask with 0xff */
1295 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1297 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1300 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1303 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1305 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1308 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1310 int fifo_bytes_used;
1313 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1315 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1317 if (fifo_bytes_used < 128)
1318 return 128 - fifo_bytes_used;
1323 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1325 while (snd_hdsp_midi_input_available (hdsp, id))
1326 snd_hdsp_midi_read_byte (hdsp, id);
1329 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1331 unsigned long flags;
1335 unsigned char buf[128];
1337 /* Output is not interrupt driven */
1339 spin_lock_irqsave (&hmidi->lock, flags);
1340 if (hmidi->output) {
1341 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1342 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1343 if (n_pending > (int)sizeof (buf))
1344 n_pending = sizeof (buf);
1346 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1347 for (i = 0; i < to_write; ++i)
1348 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1353 spin_unlock_irqrestore (&hmidi->lock, flags);
1357 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1359 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1360 unsigned long flags;
1364 spin_lock_irqsave (&hmidi->lock, flags);
1365 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1367 if (n_pending > (int)sizeof (buf))
1368 n_pending = sizeof (buf);
1369 for (i = 0; i < n_pending; ++i)
1370 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1372 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1374 /* flush the MIDI input FIFO */
1376 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1381 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1383 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1384 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1385 spin_unlock_irqrestore (&hmidi->lock, flags);
1386 return snd_hdsp_midi_output_write (hmidi);
1389 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1392 struct hdsp_midi *hmidi;
1393 unsigned long flags;
1396 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1398 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1399 spin_lock_irqsave (&hdsp->lock, flags);
1401 if (!(hdsp->control_register & ie)) {
1402 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1403 hdsp->control_register |= ie;
1406 hdsp->control_register &= ~ie;
1407 tasklet_kill(&hdsp->midi_tasklet);
1410 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1411 spin_unlock_irqrestore (&hdsp->lock, flags);
1414 static void snd_hdsp_midi_output_timer(unsigned long data)
1416 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1417 unsigned long flags;
1419 snd_hdsp_midi_output_write(hmidi);
1420 spin_lock_irqsave (&hmidi->lock, flags);
1422 /* this does not bump hmidi->istimer, because the
1423 kernel automatically removed the timer when it
1424 expired, and we are now adding it back, thus
1425 leaving istimer wherever it was set before.
1429 mod_timer(&hmidi->timer, 1 + jiffies);
1431 spin_unlock_irqrestore (&hmidi->lock, flags);
1434 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1436 struct hdsp_midi *hmidi;
1437 unsigned long flags;
1439 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440 spin_lock_irqsave (&hmidi->lock, flags);
1442 if (!hmidi->istimer) {
1443 setup_timer(&hmidi->timer, snd_hdsp_midi_output_timer,
1444 (unsigned long) hmidi);
1445 mod_timer(&hmidi->timer, 1 + jiffies);
1449 if (hmidi->istimer && --hmidi->istimer <= 0)
1450 del_timer (&hmidi->timer);
1452 spin_unlock_irqrestore (&hmidi->lock, flags);
1454 snd_hdsp_midi_output_write(hmidi);
1457 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1459 struct hdsp_midi *hmidi;
1461 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1462 spin_lock_irq (&hmidi->lock);
1463 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1464 hmidi->input = substream;
1465 spin_unlock_irq (&hmidi->lock);
1470 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1472 struct hdsp_midi *hmidi;
1474 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1475 spin_lock_irq (&hmidi->lock);
1476 hmidi->output = substream;
1477 spin_unlock_irq (&hmidi->lock);
1482 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1484 struct hdsp_midi *hmidi;
1486 snd_hdsp_midi_input_trigger (substream, 0);
1488 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1489 spin_lock_irq (&hmidi->lock);
1490 hmidi->input = NULL;
1491 spin_unlock_irq (&hmidi->lock);
1496 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1498 struct hdsp_midi *hmidi;
1500 snd_hdsp_midi_output_trigger (substream, 0);
1502 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1503 spin_lock_irq (&hmidi->lock);
1504 hmidi->output = NULL;
1505 spin_unlock_irq (&hmidi->lock);
1510 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1512 .open = snd_hdsp_midi_output_open,
1513 .close = snd_hdsp_midi_output_close,
1514 .trigger = snd_hdsp_midi_output_trigger,
1517 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1519 .open = snd_hdsp_midi_input_open,
1520 .close = snd_hdsp_midi_input_close,
1521 .trigger = snd_hdsp_midi_input_trigger,
1524 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1528 hdsp->midi[id].id = id;
1529 hdsp->midi[id].rmidi = NULL;
1530 hdsp->midi[id].input = NULL;
1531 hdsp->midi[id].output = NULL;
1532 hdsp->midi[id].hdsp = hdsp;
1533 hdsp->midi[id].istimer = 0;
1534 hdsp->midi[id].pending = 0;
1535 spin_lock_init (&hdsp->midi[id].lock);
1537 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1538 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1541 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1542 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1544 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1545 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1547 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1548 SNDRV_RAWMIDI_INFO_INPUT |
1549 SNDRV_RAWMIDI_INFO_DUPLEX;
1554 /*-----------------------------------------------------------------------------
1556 ----------------------------------------------------------------------------*/
1558 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1561 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1562 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1563 if (val & HDSP_SPDIFProfessional)
1564 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1566 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1570 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1572 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1573 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1574 if (val & HDSP_SPDIFProfessional)
1575 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1577 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1580 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1582 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1587 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1589 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1591 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1595 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1597 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1602 spin_lock_irq(&hdsp->lock);
1603 change = val != hdsp->creg_spdif;
1604 hdsp->creg_spdif = val;
1605 spin_unlock_irq(&hdsp->lock);
1609 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1611 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1616 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1618 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1620 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1624 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1626 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1630 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1631 spin_lock_irq(&hdsp->lock);
1632 change = val != hdsp->creg_spdif_stream;
1633 hdsp->creg_spdif_stream = val;
1634 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1635 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1636 spin_unlock_irq(&hdsp->lock);
1640 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1642 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1647 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1649 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1653 #define HDSP_SPDIF_IN(xname, xindex) \
1654 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1657 .info = snd_hdsp_info_spdif_in, \
1658 .get = snd_hdsp_get_spdif_in, \
1659 .put = snd_hdsp_put_spdif_in }
1661 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1663 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1666 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1668 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1669 hdsp->control_register |= hdsp_encode_spdif_in(in);
1670 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1674 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1676 static const char * const texts[4] = {
1677 "Optical", "Coaxial", "Internal", "AES"
1679 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1681 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1685 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1687 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1689 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1693 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1699 if (!snd_hdsp_use_is_exclusive(hdsp))
1701 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1702 spin_lock_irq(&hdsp->lock);
1703 change = val != hdsp_spdif_in(hdsp);
1705 hdsp_set_spdif_input(hdsp, val);
1706 spin_unlock_irq(&hdsp->lock);
1710 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1711 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1713 .private_value = xindex, \
1714 .info = snd_hdsp_info_toggle_setting, \
1715 .get = snd_hdsp_get_toggle_setting, \
1716 .put = snd_hdsp_put_toggle_setting \
1719 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1721 return (hdsp->control_register & regmask) ? 1 : 0;
1724 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1727 hdsp->control_register |= regmask;
1729 hdsp->control_register &= ~regmask;
1730 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1735 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1737 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1738 struct snd_ctl_elem_value *ucontrol)
1740 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1741 u32 regmask = kcontrol->private_value;
1743 spin_lock_irq(&hdsp->lock);
1744 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1745 spin_unlock_irq(&hdsp->lock);
1749 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1750 struct snd_ctl_elem_value *ucontrol)
1752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1753 u32 regmask = kcontrol->private_value;
1757 if (!snd_hdsp_use_is_exclusive(hdsp))
1759 val = ucontrol->value.integer.value[0] & 1;
1760 spin_lock_irq(&hdsp->lock);
1761 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1763 hdsp_set_toggle_setting(hdsp, regmask, val);
1764 spin_unlock_irq(&hdsp->lock);
1768 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1772 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1773 .info = snd_hdsp_info_spdif_sample_rate, \
1774 .get = snd_hdsp_get_spdif_sample_rate \
1777 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1779 static const char * const texts[] = {
1780 "32000", "44100", "48000", "64000", "88200", "96000",
1781 "None", "128000", "176400", "192000"
1783 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1785 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1789 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1791 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1793 switch (hdsp_spdif_sample_rate(hdsp)) {
1795 ucontrol->value.enumerated.item[0] = 0;
1798 ucontrol->value.enumerated.item[0] = 1;
1801 ucontrol->value.enumerated.item[0] = 2;
1804 ucontrol->value.enumerated.item[0] = 3;
1807 ucontrol->value.enumerated.item[0] = 4;
1810 ucontrol->value.enumerated.item[0] = 5;
1813 ucontrol->value.enumerated.item[0] = 7;
1816 ucontrol->value.enumerated.item[0] = 8;
1819 ucontrol->value.enumerated.item[0] = 9;
1822 ucontrol->value.enumerated.item[0] = 6;
1827 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1828 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1831 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1832 .info = snd_hdsp_info_system_sample_rate, \
1833 .get = snd_hdsp_get_system_sample_rate \
1836 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1838 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1843 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1845 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1847 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1851 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1852 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1855 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1856 .info = snd_hdsp_info_autosync_sample_rate, \
1857 .get = snd_hdsp_get_autosync_sample_rate \
1860 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1862 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1863 static const char * const texts[] = {
1864 "32000", "44100", "48000", "64000", "88200", "96000",
1865 "None", "128000", "176400", "192000"
1868 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1872 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1874 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1876 switch (hdsp_external_sample_rate(hdsp)) {
1878 ucontrol->value.enumerated.item[0] = 0;
1881 ucontrol->value.enumerated.item[0] = 1;
1884 ucontrol->value.enumerated.item[0] = 2;
1887 ucontrol->value.enumerated.item[0] = 3;
1890 ucontrol->value.enumerated.item[0] = 4;
1893 ucontrol->value.enumerated.item[0] = 5;
1896 ucontrol->value.enumerated.item[0] = 7;
1899 ucontrol->value.enumerated.item[0] = 8;
1902 ucontrol->value.enumerated.item[0] = 9;
1905 ucontrol->value.enumerated.item[0] = 6;
1910 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1911 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1914 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1915 .info = snd_hdsp_info_system_clock_mode, \
1916 .get = snd_hdsp_get_system_clock_mode \
1919 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1921 if (hdsp->control_register & HDSP_ClockModeMaster)
1923 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1928 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1930 static const char * const texts[] = {"Master", "Slave" };
1932 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1935 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1937 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1939 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1943 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1947 .info = snd_hdsp_info_clock_source, \
1948 .get = snd_hdsp_get_clock_source, \
1949 .put = snd_hdsp_put_clock_source \
1952 static int hdsp_clock_source(struct hdsp *hdsp)
1954 if (hdsp->control_register & HDSP_ClockModeMaster) {
1955 switch (hdsp->system_sample_rate) {
1982 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1986 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1987 if (hdsp_external_sample_rate(hdsp) != 0) {
1988 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1989 hdsp->control_register &= ~HDSP_ClockModeMaster;
1990 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1995 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1998 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2001 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2004 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2007 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2010 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2013 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2016 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2019 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2025 hdsp->control_register |= HDSP_ClockModeMaster;
2026 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2027 hdsp_set_rate(hdsp, rate, 1);
2031 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2033 static const char * const texts[] = {
2034 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2035 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2036 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2037 "Internal 192.0 KHz"
2039 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2041 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2045 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2047 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2049 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2053 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2055 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2059 if (!snd_hdsp_use_is_exclusive(hdsp))
2061 val = ucontrol->value.enumerated.item[0];
2062 if (val < 0) val = 0;
2063 if (hdsp->io_type == H9632) {
2070 spin_lock_irq(&hdsp->lock);
2071 if (val != hdsp_clock_source(hdsp))
2072 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2075 spin_unlock_irq(&hdsp->lock);
2079 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2081 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2083 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2085 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2089 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2091 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2094 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2096 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2100 #define HDSP_DA_GAIN(xname, xindex) \
2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2104 .info = snd_hdsp_info_da_gain, \
2105 .get = snd_hdsp_get_da_gain, \
2106 .put = snd_hdsp_put_da_gain \
2109 static int hdsp_da_gain(struct hdsp *hdsp)
2111 switch (hdsp->control_register & HDSP_DAGainMask) {
2112 case HDSP_DAGainHighGain:
2114 case HDSP_DAGainPlus4dBu:
2116 case HDSP_DAGainMinus10dBV:
2123 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2125 hdsp->control_register &= ~HDSP_DAGainMask;
2128 hdsp->control_register |= HDSP_DAGainHighGain;
2131 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2134 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2140 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2144 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2146 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2148 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2151 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2153 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2155 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2159 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2161 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2165 if (!snd_hdsp_use_is_exclusive(hdsp))
2167 val = ucontrol->value.enumerated.item[0];
2168 if (val < 0) val = 0;
2169 if (val > 2) val = 2;
2170 spin_lock_irq(&hdsp->lock);
2171 if (val != hdsp_da_gain(hdsp))
2172 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2175 spin_unlock_irq(&hdsp->lock);
2179 #define HDSP_AD_GAIN(xname, xindex) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2183 .info = snd_hdsp_info_ad_gain, \
2184 .get = snd_hdsp_get_ad_gain, \
2185 .put = snd_hdsp_put_ad_gain \
2188 static int hdsp_ad_gain(struct hdsp *hdsp)
2190 switch (hdsp->control_register & HDSP_ADGainMask) {
2191 case HDSP_ADGainMinus10dBV:
2193 case HDSP_ADGainPlus4dBu:
2195 case HDSP_ADGainLowGain:
2202 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2204 hdsp->control_register &= ~HDSP_ADGainMask;
2207 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2210 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2213 hdsp->control_register |= HDSP_ADGainLowGain;
2219 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2223 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2225 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2227 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2230 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2232 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2234 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2238 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2240 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2244 if (!snd_hdsp_use_is_exclusive(hdsp))
2246 val = ucontrol->value.enumerated.item[0];
2247 if (val < 0) val = 0;
2248 if (val > 2) val = 2;
2249 spin_lock_irq(&hdsp->lock);
2250 if (val != hdsp_ad_gain(hdsp))
2251 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2254 spin_unlock_irq(&hdsp->lock);
2258 #define HDSP_PHONE_GAIN(xname, xindex) \
2259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2262 .info = snd_hdsp_info_phone_gain, \
2263 .get = snd_hdsp_get_phone_gain, \
2264 .put = snd_hdsp_put_phone_gain \
2267 static int hdsp_phone_gain(struct hdsp *hdsp)
2269 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2270 case HDSP_PhoneGain0dB:
2272 case HDSP_PhoneGainMinus6dB:
2274 case HDSP_PhoneGainMinus12dB:
2281 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2283 hdsp->control_register &= ~HDSP_PhoneGainMask;
2286 hdsp->control_register |= HDSP_PhoneGain0dB;
2289 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2292 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2298 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2302 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2304 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2306 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2309 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2311 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2313 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2317 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2319 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2323 if (!snd_hdsp_use_is_exclusive(hdsp))
2325 val = ucontrol->value.enumerated.item[0];
2326 if (val < 0) val = 0;
2327 if (val > 2) val = 2;
2328 spin_lock_irq(&hdsp->lock);
2329 if (val != hdsp_phone_gain(hdsp))
2330 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2333 spin_unlock_irq(&hdsp->lock);
2337 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2338 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2341 .info = snd_hdsp_info_pref_sync_ref, \
2342 .get = snd_hdsp_get_pref_sync_ref, \
2343 .put = snd_hdsp_put_pref_sync_ref \
2346 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2348 /* Notice that this looks at the requested sync source,
2349 not the one actually in use.
2352 switch (hdsp->control_register & HDSP_SyncRefMask) {
2353 case HDSP_SyncRef_ADAT1:
2354 return HDSP_SYNC_FROM_ADAT1;
2355 case HDSP_SyncRef_ADAT2:
2356 return HDSP_SYNC_FROM_ADAT2;
2357 case HDSP_SyncRef_ADAT3:
2358 return HDSP_SYNC_FROM_ADAT3;
2359 case HDSP_SyncRef_SPDIF:
2360 return HDSP_SYNC_FROM_SPDIF;
2361 case HDSP_SyncRef_WORD:
2362 return HDSP_SYNC_FROM_WORD;
2363 case HDSP_SyncRef_ADAT_SYNC:
2364 return HDSP_SYNC_FROM_ADAT_SYNC;
2366 return HDSP_SYNC_FROM_WORD;
2371 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2373 hdsp->control_register &= ~HDSP_SyncRefMask;
2375 case HDSP_SYNC_FROM_ADAT1:
2376 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2378 case HDSP_SYNC_FROM_ADAT2:
2379 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2381 case HDSP_SYNC_FROM_ADAT3:
2382 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2384 case HDSP_SYNC_FROM_SPDIF:
2385 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2387 case HDSP_SYNC_FROM_WORD:
2388 hdsp->control_register |= HDSP_SyncRef_WORD;
2390 case HDSP_SYNC_FROM_ADAT_SYNC:
2391 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2396 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2400 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2402 static const char * const texts[] = {
2403 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2405 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2408 switch (hdsp->io_type) {
2423 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2426 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2428 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2430 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2434 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2436 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2440 if (!snd_hdsp_use_is_exclusive(hdsp))
2443 switch (hdsp->io_type) {
2458 val = ucontrol->value.enumerated.item[0] % max;
2459 spin_lock_irq(&hdsp->lock);
2460 change = (int)val != hdsp_pref_sync_ref(hdsp);
2461 hdsp_set_pref_sync_ref(hdsp, val);
2462 spin_unlock_irq(&hdsp->lock);
2466 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2470 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2471 .info = snd_hdsp_info_autosync_ref, \
2472 .get = snd_hdsp_get_autosync_ref, \
2475 static int hdsp_autosync_ref(struct hdsp *hdsp)
2477 /* This looks at the autosync selected sync reference */
2478 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2480 switch (status2 & HDSP_SelSyncRefMask) {
2481 case HDSP_SelSyncRef_WORD:
2482 return HDSP_AUTOSYNC_FROM_WORD;
2483 case HDSP_SelSyncRef_ADAT_SYNC:
2484 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2485 case HDSP_SelSyncRef_SPDIF:
2486 return HDSP_AUTOSYNC_FROM_SPDIF;
2487 case HDSP_SelSyncRefMask:
2488 return HDSP_AUTOSYNC_FROM_NONE;
2489 case HDSP_SelSyncRef_ADAT1:
2490 return HDSP_AUTOSYNC_FROM_ADAT1;
2491 case HDSP_SelSyncRef_ADAT2:
2492 return HDSP_AUTOSYNC_FROM_ADAT2;
2493 case HDSP_SelSyncRef_ADAT3:
2494 return HDSP_AUTOSYNC_FROM_ADAT3;
2496 return HDSP_AUTOSYNC_FROM_WORD;
2501 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2503 static const char * const texts[] = {
2504 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2507 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2510 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2512 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2514 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2518 #define HDSP_PRECISE_POINTER(xname, xindex) \
2519 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2522 .info = snd_hdsp_info_precise_pointer, \
2523 .get = snd_hdsp_get_precise_pointer, \
2524 .put = snd_hdsp_put_precise_pointer \
2527 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2530 hdsp->precise_ptr = 1;
2532 hdsp->precise_ptr = 0;
2536 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2538 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2540 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2542 spin_lock_irq(&hdsp->lock);
2543 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2544 spin_unlock_irq(&hdsp->lock);
2548 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2550 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2554 if (!snd_hdsp_use_is_exclusive(hdsp))
2556 val = ucontrol->value.integer.value[0] & 1;
2557 spin_lock_irq(&hdsp->lock);
2558 change = (int)val != hdsp->precise_ptr;
2559 hdsp_set_precise_pointer(hdsp, val);
2560 spin_unlock_irq(&hdsp->lock);
2564 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2565 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2568 .info = snd_hdsp_info_use_midi_tasklet, \
2569 .get = snd_hdsp_get_use_midi_tasklet, \
2570 .put = snd_hdsp_put_use_midi_tasklet \
2573 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2576 hdsp->use_midi_tasklet = 1;
2578 hdsp->use_midi_tasklet = 0;
2582 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2584 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2586 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2588 spin_lock_irq(&hdsp->lock);
2589 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2590 spin_unlock_irq(&hdsp->lock);
2594 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2596 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2600 if (!snd_hdsp_use_is_exclusive(hdsp))
2602 val = ucontrol->value.integer.value[0] & 1;
2603 spin_lock_irq(&hdsp->lock);
2604 change = (int)val != hdsp->use_midi_tasklet;
2605 hdsp_set_use_midi_tasklet(hdsp, val);
2606 spin_unlock_irq(&hdsp->lock);
2610 #define HDSP_MIXER(xname, xindex) \
2611 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2615 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2616 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2617 .info = snd_hdsp_info_mixer, \
2618 .get = snd_hdsp_get_mixer, \
2619 .put = snd_hdsp_put_mixer \
2622 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2624 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2626 uinfo->value.integer.min = 0;
2627 uinfo->value.integer.max = 65536;
2628 uinfo->value.integer.step = 1;
2632 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2634 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2639 source = ucontrol->value.integer.value[0];
2640 destination = ucontrol->value.integer.value[1];
2642 if (source >= hdsp->max_channels)
2643 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2645 addr = hdsp_input_to_output_key(hdsp,source, destination);
2647 spin_lock_irq(&hdsp->lock);
2648 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2649 spin_unlock_irq(&hdsp->lock);
2653 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2655 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2662 if (!snd_hdsp_use_is_exclusive(hdsp))
2665 source = ucontrol->value.integer.value[0];
2666 destination = ucontrol->value.integer.value[1];
2668 if (source >= hdsp->max_channels)
2669 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2671 addr = hdsp_input_to_output_key(hdsp,source, destination);
2673 gain = ucontrol->value.integer.value[2];
2675 spin_lock_irq(&hdsp->lock);
2676 change = gain != hdsp_read_gain(hdsp, addr);
2678 hdsp_write_gain(hdsp, addr, gain);
2679 spin_unlock_irq(&hdsp->lock);
2683 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2687 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2688 .info = snd_hdsp_info_sync_check, \
2689 .get = snd_hdsp_get_wc_sync_check \
2692 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2694 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2696 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2699 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2701 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2702 if (status2 & HDSP_wc_lock) {
2703 if (status2 & HDSP_wc_sync)
2712 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2714 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2716 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2720 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2721 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2724 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2725 .info = snd_hdsp_info_sync_check, \
2726 .get = snd_hdsp_get_spdif_sync_check \
2729 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2731 int status = hdsp_read(hdsp, HDSP_statusRegister);
2732 if (status & HDSP_SPDIFErrorFlag)
2735 if (status & HDSP_SPDIFSync)
2743 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2745 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2747 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2751 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2752 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2755 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2756 .info = snd_hdsp_info_sync_check, \
2757 .get = snd_hdsp_get_adatsync_sync_check \
2760 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2762 int status = hdsp_read(hdsp, HDSP_statusRegister);
2763 if (status & HDSP_TimecodeLock) {
2764 if (status & HDSP_TimecodeSync)
2772 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2774 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2776 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2780 #define HDSP_ADAT_SYNC_CHECK \
2781 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2782 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2783 .info = snd_hdsp_info_sync_check, \
2784 .get = snd_hdsp_get_adat_sync_check \
2787 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2789 int status = hdsp_read(hdsp, HDSP_statusRegister);
2791 if (status & (HDSP_Lock0>>idx)) {
2792 if (status & (HDSP_Sync0>>idx))
2800 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2805 offset = ucontrol->id.index - 1;
2806 if (snd_BUG_ON(offset < 0))
2809 switch (hdsp->io_type) {
2824 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2828 #define HDSP_DDS_OFFSET(xname, xindex) \
2829 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2832 .info = snd_hdsp_info_dds_offset, \
2833 .get = snd_hdsp_get_dds_offset, \
2834 .put = snd_hdsp_put_dds_offset \
2837 static int hdsp_dds_offset(struct hdsp *hdsp)
2840 unsigned int dds_value = hdsp->dds_value;
2841 int system_sample_rate = hdsp->system_sample_rate;
2848 * dds_value = n / rate
2849 * rate = n / dds_value
2851 n = div_u64(n, dds_value);
2852 if (system_sample_rate >= 112000)
2854 else if (system_sample_rate >= 56000)
2856 return ((int)n) - system_sample_rate;
2859 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2861 int rate = hdsp->system_sample_rate + offset_hz;
2862 hdsp_set_dds_value(hdsp, rate);
2866 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2868 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2870 uinfo->value.integer.min = -5000;
2871 uinfo->value.integer.max = 5000;
2875 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2877 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2879 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2883 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2885 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2889 if (!snd_hdsp_use_is_exclusive(hdsp))
2891 val = ucontrol->value.integer.value[0];
2892 spin_lock_irq(&hdsp->lock);
2893 if (val != hdsp_dds_offset(hdsp))
2894 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2897 spin_unlock_irq(&hdsp->lock);
2901 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2902 HDSP_DA_GAIN("DA Gain", 0),
2903 HDSP_AD_GAIN("AD Gain", 0),
2904 HDSP_PHONE_GAIN("Phones Gain", 0),
2905 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2906 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2909 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2911 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2912 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2913 .info = snd_hdsp_control_spdif_info,
2914 .get = snd_hdsp_control_spdif_get,
2915 .put = snd_hdsp_control_spdif_put,
2918 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2919 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2920 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2921 .info = snd_hdsp_control_spdif_stream_info,
2922 .get = snd_hdsp_control_spdif_stream_get,
2923 .put = snd_hdsp_control_spdif_stream_put,
2926 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2927 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2928 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2929 .info = snd_hdsp_control_spdif_mask_info,
2930 .get = snd_hdsp_control_spdif_mask_get,
2931 .private_value = IEC958_AES0_NONAUDIO |
2932 IEC958_AES0_PROFESSIONAL |
2933 IEC958_AES0_CON_EMPHASIS,
2936 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2937 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2938 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2939 .info = snd_hdsp_control_spdif_mask_info,
2940 .get = snd_hdsp_control_spdif_mask_get,
2941 .private_value = IEC958_AES0_NONAUDIO |
2942 IEC958_AES0_PROFESSIONAL |
2943 IEC958_AES0_PRO_EMPHASIS,
2945 HDSP_MIXER("Mixer", 0),
2946 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2947 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2948 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2949 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2950 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2951 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2952 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2954 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2955 .name = "Sample Clock Source Locking",
2956 .info = snd_hdsp_info_clock_source_lock,
2957 .get = snd_hdsp_get_clock_source_lock,
2958 .put = snd_hdsp_put_clock_source_lock,
2960 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2961 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2962 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2963 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2964 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2965 /* 'External Rate' complies with the alsa control naming scheme */
2966 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2967 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2968 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2969 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2970 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2971 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2972 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2976 static int hdsp_rpm_input12(struct hdsp *hdsp)
2978 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2979 case HDSP_RPM_Inp12_Phon_6dB:
2981 case HDSP_RPM_Inp12_Phon_n6dB:
2983 case HDSP_RPM_Inp12_Line_0dB:
2985 case HDSP_RPM_Inp12_Line_n6dB:
2992 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2994 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2996 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3001 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3003 hdsp->control_register &= ~HDSP_RPM_Inp12;
3006 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3011 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3014 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3017 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3023 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3028 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3030 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3034 if (!snd_hdsp_use_is_exclusive(hdsp))
3036 val = ucontrol->value.enumerated.item[0];
3041 spin_lock_irq(&hdsp->lock);
3042 if (val != hdsp_rpm_input12(hdsp))
3043 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3046 spin_unlock_irq(&hdsp->lock);
3051 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3053 static const char * const texts[] = {
3054 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3057 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3061 static int hdsp_rpm_input34(struct hdsp *hdsp)
3063 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3064 case HDSP_RPM_Inp34_Phon_6dB:
3066 case HDSP_RPM_Inp34_Phon_n6dB:
3068 case HDSP_RPM_Inp34_Line_0dB:
3070 case HDSP_RPM_Inp34_Line_n6dB:
3077 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3079 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3081 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3086 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3088 hdsp->control_register &= ~HDSP_RPM_Inp34;
3091 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3096 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3099 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3102 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3108 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3113 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3115 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3119 if (!snd_hdsp_use_is_exclusive(hdsp))
3121 val = ucontrol->value.enumerated.item[0];
3126 spin_lock_irq(&hdsp->lock);
3127 if (val != hdsp_rpm_input34(hdsp))
3128 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3131 spin_unlock_irq(&hdsp->lock);
3136 /* RPM Bypass switch */
3137 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3139 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3143 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3145 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3147 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3152 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3155 hdsp->control_register |= HDSP_RPM_Bypass;
3157 hdsp->control_register &= ~HDSP_RPM_Bypass;
3158 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3163 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3165 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3169 if (!snd_hdsp_use_is_exclusive(hdsp))
3171 val = ucontrol->value.integer.value[0] & 1;
3172 spin_lock_irq(&hdsp->lock);
3173 change = (int)val != hdsp_rpm_bypass(hdsp);
3174 hdsp_set_rpm_bypass(hdsp, val);
3175 spin_unlock_irq(&hdsp->lock);
3180 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3182 static const char * const texts[] = {"On", "Off"};
3184 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3188 /* RPM Disconnect switch */
3189 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3191 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3195 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3197 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3199 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3204 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3207 hdsp->control_register |= HDSP_RPM_Disconnect;
3209 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3210 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3215 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3217 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3221 if (!snd_hdsp_use_is_exclusive(hdsp))
3223 val = ucontrol->value.integer.value[0] & 1;
3224 spin_lock_irq(&hdsp->lock);
3225 change = (int)val != hdsp_rpm_disconnect(hdsp);
3226 hdsp_set_rpm_disconnect(hdsp, val);
3227 spin_unlock_irq(&hdsp->lock);
3231 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3233 static const char * const texts[] = {"On", "Off"};
3235 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3238 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3240 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3241 .name = "RPM Bypass",
3242 .get = snd_hdsp_get_rpm_bypass,
3243 .put = snd_hdsp_put_rpm_bypass,
3244 .info = snd_hdsp_info_rpm_bypass
3247 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3248 .name = "RPM Disconnect",
3249 .get = snd_hdsp_get_rpm_disconnect,
3250 .put = snd_hdsp_put_rpm_disconnect,
3251 .info = snd_hdsp_info_rpm_disconnect
3254 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3255 .name = "Input 1/2",
3256 .get = snd_hdsp_get_rpm_input12,
3257 .put = snd_hdsp_put_rpm_input12,
3258 .info = snd_hdsp_info_rpm_input
3261 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3262 .name = "Input 3/4",
3263 .get = snd_hdsp_get_rpm_input34,
3264 .put = snd_hdsp_put_rpm_input34,
3265 .info = snd_hdsp_info_rpm_input
3267 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3268 HDSP_MIXER("Mixer", 0)
3271 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3272 HDSP_TOGGLE_SETTING("Analog Extension Board",
3273 HDSP_AnalogExtensionBoard);
3274 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3276 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3280 struct snd_kcontrol *kctl;
3282 if (hdsp->io_type == RPM) {
3283 /* RPM Bypass, Disconnect and Input switches */
3284 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3285 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3292 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3293 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3295 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3296 hdsp->spdif_ctl = kctl;
3299 /* ADAT SyncCheck status */
3300 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3301 snd_hdsp_adat_sync_check.index = 1;
3302 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3304 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3305 for (idx = 1; idx < 3; ++idx) {
3306 snd_hdsp_adat_sync_check.index = idx+1;
3307 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3312 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3313 if (hdsp->io_type == H9632) {
3314 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3315 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3320 /* AEB control for H96xx card */
3321 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3322 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3329 /*------------------------------------------------------------
3331 ------------------------------------------------------------*/
3334 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3336 struct hdsp *hdsp = entry->private_data;
3337 unsigned int status;
3338 unsigned int status2;
3339 char *pref_sync_ref;
3341 char *system_clock_mode;
3345 status = hdsp_read(hdsp, HDSP_statusRegister);
3346 status2 = hdsp_read(hdsp, HDSP_status2Register);
3348 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3349 hdsp->card->number + 1);
3350 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3351 hdsp->capture_buffer, hdsp->playback_buffer);
3352 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3353 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3354 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3355 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3356 hdsp->control2_register);
3357 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3358 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3360 if (hdsp_check_for_iobox(hdsp)) {
3361 snd_iprintf(buffer, "No I/O box connected.\n"
3362 "Please connect one and upload firmware.\n");
3366 if (hdsp_check_for_firmware(hdsp, 0)) {
3367 if (hdsp->state & HDSP_FirmwareCached) {
3368 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3369 snd_iprintf(buffer, "Firmware loading from "
3371 "please upload manually.\n");
3376 err = hdsp_request_fw_loader(hdsp);
3379 "No firmware loaded nor cached, "
3380 "please upload firmware.\n");
3386 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3387 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3388 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3389 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3390 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3391 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3393 snd_iprintf(buffer, "\n");
3395 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3397 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3398 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3399 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3400 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3402 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3404 snd_iprintf(buffer, "\n");
3406 switch (hdsp_clock_source(hdsp)) {
3407 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3408 clock_source = "AutoSync";
3410 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3411 clock_source = "Internal 32 kHz";
3413 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3414 clock_source = "Internal 44.1 kHz";
3416 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3417 clock_source = "Internal 48 kHz";
3419 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3420 clock_source = "Internal 64 kHz";
3422 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3423 clock_source = "Internal 88.2 kHz";
3425 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3426 clock_source = "Internal 96 kHz";
3428 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3429 clock_source = "Internal 128 kHz";
3431 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3432 clock_source = "Internal 176.4 kHz";
3434 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3435 clock_source = "Internal 192 kHz";
3438 clock_source = "Error";
3440 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3442 if (hdsp_system_clock_mode(hdsp))
3443 system_clock_mode = "Slave";
3445 system_clock_mode = "Master";
3447 switch (hdsp_pref_sync_ref (hdsp)) {
3448 case HDSP_SYNC_FROM_WORD:
3449 pref_sync_ref = "Word Clock";
3451 case HDSP_SYNC_FROM_ADAT_SYNC:
3452 pref_sync_ref = "ADAT Sync";
3454 case HDSP_SYNC_FROM_SPDIF:
3455 pref_sync_ref = "SPDIF";
3457 case HDSP_SYNC_FROM_ADAT1:
3458 pref_sync_ref = "ADAT1";
3460 case HDSP_SYNC_FROM_ADAT2:
3461 pref_sync_ref = "ADAT2";
3463 case HDSP_SYNC_FROM_ADAT3:
3464 pref_sync_ref = "ADAT3";
3467 pref_sync_ref = "Word Clock";
3470 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3472 switch (hdsp_autosync_ref (hdsp)) {
3473 case HDSP_AUTOSYNC_FROM_WORD:
3474 autosync_ref = "Word Clock";
3476 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3477 autosync_ref = "ADAT Sync";
3479 case HDSP_AUTOSYNC_FROM_SPDIF:
3480 autosync_ref = "SPDIF";
3482 case HDSP_AUTOSYNC_FROM_NONE:
3483 autosync_ref = "None";
3485 case HDSP_AUTOSYNC_FROM_ADAT1:
3486 autosync_ref = "ADAT1";
3488 case HDSP_AUTOSYNC_FROM_ADAT2:
3489 autosync_ref = "ADAT2";
3491 case HDSP_AUTOSYNC_FROM_ADAT3:
3492 autosync_ref = "ADAT3";
3495 autosync_ref = "---";
3498 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3500 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3502 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3504 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3505 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3507 snd_iprintf(buffer, "\n");
3509 if (hdsp->io_type != RPM) {
3510 switch (hdsp_spdif_in(hdsp)) {
3511 case HDSP_SPDIFIN_OPTICAL:
3512 snd_iprintf(buffer, "IEC958 input: Optical\n");
3514 case HDSP_SPDIFIN_COAXIAL:
3515 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3517 case HDSP_SPDIFIN_INTERNAL:
3518 snd_iprintf(buffer, "IEC958 input: Internal\n");
3520 case HDSP_SPDIFIN_AES:
3521 snd_iprintf(buffer, "IEC958 input: AES\n");
3524 snd_iprintf(buffer, "IEC958 input: ???\n");
3529 if (RPM == hdsp->io_type) {
3530 if (hdsp->control_register & HDSP_RPM_Bypass)
3531 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3533 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3534 if (hdsp->control_register & HDSP_RPM_Disconnect)
3535 snd_iprintf(buffer, "RPM disconnected\n");
3537 snd_iprintf(buffer, "RPM connected\n");
3539 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3540 case HDSP_RPM_Inp12_Phon_6dB:
3541 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3543 case HDSP_RPM_Inp12_Phon_0dB:
3544 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3546 case HDSP_RPM_Inp12_Phon_n6dB:
3547 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3549 case HDSP_RPM_Inp12_Line_0dB:
3550 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3552 case HDSP_RPM_Inp12_Line_n6dB:
3553 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3556 snd_iprintf(buffer, "Input 1/2: ???\n");
3559 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3560 case HDSP_RPM_Inp34_Phon_6dB:
3561 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3563 case HDSP_RPM_Inp34_Phon_0dB:
3564 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3566 case HDSP_RPM_Inp34_Phon_n6dB:
3567 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3569 case HDSP_RPM_Inp34_Line_0dB:
3570 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3572 case HDSP_RPM_Inp34_Line_n6dB:
3573 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3576 snd_iprintf(buffer, "Input 3/4: ???\n");
3580 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3581 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3583 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3585 if (hdsp->control_register & HDSP_SPDIFProfessional)
3586 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3588 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3590 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3591 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3593 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3595 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3596 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3598 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3599 x = hdsp_spdif_sample_rate(hdsp);
3601 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3603 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3605 snd_iprintf(buffer, "\n");
3608 x = status & HDSP_Sync0;
3609 if (status & HDSP_Lock0)
3610 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3612 snd_iprintf(buffer, "ADAT1: No Lock\n");
3614 switch (hdsp->io_type) {
3617 x = status & HDSP_Sync1;
3618 if (status & HDSP_Lock1)
3619 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3621 snd_iprintf(buffer, "ADAT2: No Lock\n");
3622 x = status & HDSP_Sync2;
3623 if (status & HDSP_Lock2)
3624 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3626 snd_iprintf(buffer, "ADAT3: No Lock\n");
3633 x = status & HDSP_SPDIFSync;
3634 if (status & HDSP_SPDIFErrorFlag)
3635 snd_iprintf (buffer, "SPDIF: No Lock\n");
3637 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3639 x = status2 & HDSP_wc_sync;
3640 if (status2 & HDSP_wc_lock)
3641 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3643 snd_iprintf (buffer, "Word Clock: No Lock\n");
3645 x = status & HDSP_TimecodeSync;
3646 if (status & HDSP_TimecodeLock)
3647 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3649 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3651 snd_iprintf(buffer, "\n");
3653 /* Informations about H9632 specific controls */
3654 if (hdsp->io_type == H9632) {
3657 switch (hdsp_ad_gain(hdsp)) {
3668 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3670 switch (hdsp_da_gain(hdsp)) {
3681 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3683 switch (hdsp_phone_gain(hdsp)) {
3694 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3696 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3697 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3700 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3701 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3703 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3704 snd_iprintf(buffer, "\n");
3709 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3711 struct snd_info_entry *entry;
3713 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3714 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3717 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3719 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3720 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3723 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3725 unsigned long pb_bus, cb_bus;
3727 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3728 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3729 if (hdsp->capture_dma_buf.area)
3730 snd_dma_free_pages(&hdsp->capture_dma_buf);
3731 dev_err(hdsp->card->dev,
3732 "%s: no buffers available\n", hdsp->card_name);
3736 /* Align to bus-space 64K boundary */
3738 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3739 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3741 /* Tell the card where it is */
3743 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3744 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3746 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3747 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3752 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3756 /* ASSUMPTION: hdsp->lock is either held, or
3757 there is no need to hold it (e.g. during module
3763 SPDIF Input via Coax
3765 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3766 which implies 2 4096 sample, 32Kbyte periods).
3770 hdsp->control_register = HDSP_ClockModeMaster |
3771 HDSP_SPDIFInputCoaxial |
3772 hdsp_encode_latency(7) |
3776 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3778 #ifdef SNDRV_BIG_ENDIAN
3779 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3781 hdsp->control2_register = 0;
3783 if (hdsp->io_type == H9652)
3784 snd_hdsp_9652_enable_mixer (hdsp);
3786 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3788 hdsp_reset_hw_pointer(hdsp);
3789 hdsp_compute_period_size(hdsp);
3791 /* silence everything */
3793 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3794 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3796 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3797 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3801 /* H9632 specific defaults */
3802 if (hdsp->io_type == H9632) {
3803 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3804 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3807 /* set a default rate so that the channel map is set up.
3810 hdsp_set_rate(hdsp, 48000, 1);
3815 static void hdsp_midi_tasklet(unsigned long arg)
3817 struct hdsp *hdsp = (struct hdsp *)arg;
3819 if (hdsp->midi[0].pending)
3820 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3821 if (hdsp->midi[1].pending)
3822 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3825 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3827 struct hdsp *hdsp = (struct hdsp *) dev_id;
3828 unsigned int status;
3832 unsigned int midi0status;
3833 unsigned int midi1status;
3836 status = hdsp_read(hdsp, HDSP_statusRegister);
3838 audio = status & HDSP_audioIRQPending;
3839 midi0 = status & HDSP_midi0IRQPending;
3840 midi1 = status & HDSP_midi1IRQPending;
3842 if (!audio && !midi0 && !midi1)
3845 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3847 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3848 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3850 if (!(hdsp->state & HDSP_InitializationComplete))
3854 if (hdsp->capture_substream)
3855 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3857 if (hdsp->playback_substream)
3858 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3861 if (midi0 && midi0status) {
3862 if (hdsp->use_midi_tasklet) {
3863 /* we disable interrupts for this input until processing is done */
3864 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3865 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3866 hdsp->midi[0].pending = 1;
3869 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3872 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3873 if (hdsp->use_midi_tasklet) {
3874 /* we disable interrupts for this input until processing is done */
3875 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3876 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3877 hdsp->midi[1].pending = 1;
3880 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3883 if (hdsp->use_midi_tasklet && schedule)
3884 tasklet_schedule(&hdsp->midi_tasklet);
3888 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3890 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3891 return hdsp_hw_pointer(hdsp);
3894 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3901 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3904 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3907 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3908 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3910 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3913 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3914 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3916 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3919 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3922 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3923 if (snd_BUG_ON(!channel_buf))
3925 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3930 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3931 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3933 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3936 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3939 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3940 if (snd_BUG_ON(!channel_buf))
3942 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3947 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3948 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3950 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3953 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3954 if (snd_BUG_ON(!channel_buf))
3956 memset(channel_buf + pos * 4, 0, count * 4);
3960 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3962 struct snd_pcm_runtime *runtime = substream->runtime;
3963 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3964 struct snd_pcm_substream *other;
3965 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3966 other = hdsp->capture_substream;
3968 other = hdsp->playback_substream;
3970 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3972 runtime->status->hw_ptr = 0;
3974 struct snd_pcm_substream *s;
3975 struct snd_pcm_runtime *oruntime = other->runtime;
3976 snd_pcm_group_for_each_entry(s, substream) {
3978 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3986 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3987 struct snd_pcm_hw_params *params)
3989 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3994 if (hdsp_check_for_iobox (hdsp))
3997 if (hdsp_check_for_firmware(hdsp, 1))
4000 spin_lock_irq(&hdsp->lock);
4002 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4003 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4005 this_pid = hdsp->playback_pid;
4006 other_pid = hdsp->capture_pid;
4008 this_pid = hdsp->capture_pid;
4009 other_pid = hdsp->playback_pid;
4012 if ((other_pid > 0) && (this_pid != other_pid)) {
4014 /* The other stream is open, and not by the same
4015 task as this one. Make sure that the parameters
4016 that matter are the same.
4019 if (params_rate(params) != hdsp->system_sample_rate) {
4020 spin_unlock_irq(&hdsp->lock);
4021 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4025 if (params_period_size(params) != hdsp->period_bytes / 4) {
4026 spin_unlock_irq(&hdsp->lock);
4027 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4033 spin_unlock_irq(&hdsp->lock);
4037 spin_unlock_irq(&hdsp->lock);
4040 /* how to make sure that the rate matches an externally-set one ?
4043 spin_lock_irq(&hdsp->lock);
4044 if (! hdsp->clock_source_locked) {
4045 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4046 spin_unlock_irq(&hdsp->lock);
4047 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4051 spin_unlock_irq(&hdsp->lock);
4053 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4054 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4061 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4062 struct snd_pcm_channel_info *info)
4064 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4065 unsigned int channel = info->channel;
4067 if (snd_BUG_ON(channel >= hdsp->max_channels))
4069 channel = array_index_nospec(channel, hdsp->max_channels);
4071 if (hdsp->channel_map[channel] < 0)
4074 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4080 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4081 unsigned int cmd, void *arg)
4084 case SNDRV_PCM_IOCTL1_RESET:
4085 return snd_hdsp_reset(substream);
4086 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4087 return snd_hdsp_channel_info(substream, arg);
4092 return snd_pcm_lib_ioctl(substream, cmd, arg);
4095 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4097 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4098 struct snd_pcm_substream *other;
4101 if (hdsp_check_for_iobox (hdsp))
4104 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4107 spin_lock(&hdsp->lock);
4108 running = hdsp->running;
4110 case SNDRV_PCM_TRIGGER_START:
4111 running |= 1 << substream->stream;
4113 case SNDRV_PCM_TRIGGER_STOP:
4114 running &= ~(1 << substream->stream);
4118 spin_unlock(&hdsp->lock);
4121 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4122 other = hdsp->capture_substream;
4124 other = hdsp->playback_substream;
4127 struct snd_pcm_substream *s;
4128 snd_pcm_group_for_each_entry(s, substream) {
4130 snd_pcm_trigger_done(s, substream);
4131 if (cmd == SNDRV_PCM_TRIGGER_START)
4132 running |= 1 << s->stream;
4134 running &= ~(1 << s->stream);
4138 if (cmd == SNDRV_PCM_TRIGGER_START) {
4139 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4140 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4141 hdsp_silence_playback(hdsp);
4144 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4145 hdsp_silence_playback(hdsp);
4148 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4149 hdsp_silence_playback(hdsp);
4152 snd_pcm_trigger_done(substream, substream);
4153 if (!hdsp->running && running)
4154 hdsp_start_audio(hdsp);
4155 else if (hdsp->running && !running)
4156 hdsp_stop_audio(hdsp);
4157 hdsp->running = running;
4158 spin_unlock(&hdsp->lock);
4163 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4165 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4168 if (hdsp_check_for_iobox (hdsp))
4171 if (hdsp_check_for_firmware(hdsp, 1))
4174 spin_lock_irq(&hdsp->lock);
4176 hdsp_reset_hw_pointer(hdsp);
4177 spin_unlock_irq(&hdsp->lock);
4181 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4183 .info = (SNDRV_PCM_INFO_MMAP |
4184 SNDRV_PCM_INFO_MMAP_VALID |
4185 SNDRV_PCM_INFO_NONINTERLEAVED |
4186 SNDRV_PCM_INFO_SYNC_START |
4187 SNDRV_PCM_INFO_DOUBLE),
4188 #ifdef SNDRV_BIG_ENDIAN
4189 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4191 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4193 .rates = (SNDRV_PCM_RATE_32000 |
4194 SNDRV_PCM_RATE_44100 |
4195 SNDRV_PCM_RATE_48000 |
4196 SNDRV_PCM_RATE_64000 |
4197 SNDRV_PCM_RATE_88200 |
4198 SNDRV_PCM_RATE_96000),
4202 .channels_max = HDSP_MAX_CHANNELS,
4203 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4204 .period_bytes_min = (64 * 4) * 10,
4205 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4211 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4213 .info = (SNDRV_PCM_INFO_MMAP |
4214 SNDRV_PCM_INFO_MMAP_VALID |
4215 SNDRV_PCM_INFO_NONINTERLEAVED |
4216 SNDRV_PCM_INFO_SYNC_START),
4217 #ifdef SNDRV_BIG_ENDIAN
4218 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4220 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4222 .rates = (SNDRV_PCM_RATE_32000 |
4223 SNDRV_PCM_RATE_44100 |
4224 SNDRV_PCM_RATE_48000 |
4225 SNDRV_PCM_RATE_64000 |
4226 SNDRV_PCM_RATE_88200 |
4227 SNDRV_PCM_RATE_96000),
4231 .channels_max = HDSP_MAX_CHANNELS,
4232 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4233 .period_bytes_min = (64 * 4) * 10,
4234 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4240 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4242 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4243 .count = ARRAY_SIZE(hdsp_period_sizes),
4244 .list = hdsp_period_sizes,
4248 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4250 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4251 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4252 .list = hdsp_9632_sample_rates,
4256 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4257 struct snd_pcm_hw_rule *rule)
4259 struct hdsp *hdsp = rule->private;
4260 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4261 if (hdsp->io_type == H9632) {
4262 unsigned int list[3];
4263 list[0] = hdsp->qs_in_channels;
4264 list[1] = hdsp->ds_in_channels;
4265 list[2] = hdsp->ss_in_channels;
4266 return snd_interval_list(c, 3, list, 0);
4268 unsigned int list[2];
4269 list[0] = hdsp->ds_in_channels;
4270 list[1] = hdsp->ss_in_channels;
4271 return snd_interval_list(c, 2, list, 0);
4275 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4276 struct snd_pcm_hw_rule *rule)
4278 unsigned int list[3];
4279 struct hdsp *hdsp = rule->private;
4280 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4281 if (hdsp->io_type == H9632) {
4282 list[0] = hdsp->qs_out_channels;
4283 list[1] = hdsp->ds_out_channels;
4284 list[2] = hdsp->ss_out_channels;
4285 return snd_interval_list(c, 3, list, 0);
4287 list[0] = hdsp->ds_out_channels;
4288 list[1] = hdsp->ss_out_channels;
4290 return snd_interval_list(c, 2, list, 0);
4293 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4294 struct snd_pcm_hw_rule *rule)
4296 struct hdsp *hdsp = rule->private;
4297 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4298 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4299 if (r->min > 96000 && hdsp->io_type == H9632) {
4300 struct snd_interval t = {
4301 .min = hdsp->qs_in_channels,
4302 .max = hdsp->qs_in_channels,
4305 return snd_interval_refine(c, &t);
4306 } else if (r->min > 48000 && r->max <= 96000) {
4307 struct snd_interval t = {
4308 .min = hdsp->ds_in_channels,
4309 .max = hdsp->ds_in_channels,
4312 return snd_interval_refine(c, &t);
4313 } else if (r->max < 64000) {
4314 struct snd_interval t = {
4315 .min = hdsp->ss_in_channels,
4316 .max = hdsp->ss_in_channels,
4319 return snd_interval_refine(c, &t);
4324 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4325 struct snd_pcm_hw_rule *rule)
4327 struct hdsp *hdsp = rule->private;
4328 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4329 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4330 if (r->min > 96000 && hdsp->io_type == H9632) {
4331 struct snd_interval t = {
4332 .min = hdsp->qs_out_channels,
4333 .max = hdsp->qs_out_channels,
4336 return snd_interval_refine(c, &t);
4337 } else if (r->min > 48000 && r->max <= 96000) {
4338 struct snd_interval t = {
4339 .min = hdsp->ds_out_channels,
4340 .max = hdsp->ds_out_channels,
4343 return snd_interval_refine(c, &t);
4344 } else if (r->max < 64000) {
4345 struct snd_interval t = {
4346 .min = hdsp->ss_out_channels,
4347 .max = hdsp->ss_out_channels,
4350 return snd_interval_refine(c, &t);
4355 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4356 struct snd_pcm_hw_rule *rule)
4358 struct hdsp *hdsp = rule->private;
4359 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4360 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4361 if (c->min >= hdsp->ss_out_channels) {
4362 struct snd_interval t = {
4367 return snd_interval_refine(r, &t);
4368 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4369 struct snd_interval t = {
4374 return snd_interval_refine(r, &t);
4375 } else if (c->max <= hdsp->ds_out_channels) {
4376 struct snd_interval t = {
4381 return snd_interval_refine(r, &t);
4386 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4387 struct snd_pcm_hw_rule *rule)
4389 struct hdsp *hdsp = rule->private;
4390 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4391 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4392 if (c->min >= hdsp->ss_in_channels) {
4393 struct snd_interval t = {
4398 return snd_interval_refine(r, &t);
4399 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4400 struct snd_interval t = {
4405 return snd_interval_refine(r, &t);
4406 } else if (c->max <= hdsp->ds_in_channels) {
4407 struct snd_interval t = {
4412 return snd_interval_refine(r, &t);
4417 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4419 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4420 struct snd_pcm_runtime *runtime = substream->runtime;
4422 if (hdsp_check_for_iobox (hdsp))
4425 if (hdsp_check_for_firmware(hdsp, 1))
4428 spin_lock_irq(&hdsp->lock);
4430 snd_pcm_set_sync(substream);
4432 runtime->hw = snd_hdsp_playback_subinfo;
4433 runtime->dma_area = hdsp->playback_buffer;
4434 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4436 hdsp->playback_pid = current->pid;
4437 hdsp->playback_substream = substream;
4439 spin_unlock_irq(&hdsp->lock);
4441 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4442 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4443 if (hdsp->clock_source_locked) {
4444 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4445 } else if (hdsp->io_type == H9632) {
4446 runtime->hw.rate_max = 192000;
4447 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4448 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4450 if (hdsp->io_type == H9632) {
4451 runtime->hw.channels_min = hdsp->qs_out_channels;
4452 runtime->hw.channels_max = hdsp->ss_out_channels;
4455 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4456 snd_hdsp_hw_rule_out_channels, hdsp,
4457 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4458 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4459 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4460 SNDRV_PCM_HW_PARAM_RATE, -1);
4461 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4462 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4463 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4465 if (RPM != hdsp->io_type) {
4466 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4467 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4468 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4469 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4474 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4476 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4478 spin_lock_irq(&hdsp->lock);
4480 hdsp->playback_pid = -1;
4481 hdsp->playback_substream = NULL;
4483 spin_unlock_irq(&hdsp->lock);
4485 if (RPM != hdsp->io_type) {
4486 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4487 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4488 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4494 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4496 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4497 struct snd_pcm_runtime *runtime = substream->runtime;
4499 if (hdsp_check_for_iobox (hdsp))
4502 if (hdsp_check_for_firmware(hdsp, 1))
4505 spin_lock_irq(&hdsp->lock);
4507 snd_pcm_set_sync(substream);
4509 runtime->hw = snd_hdsp_capture_subinfo;
4510 runtime->dma_area = hdsp->capture_buffer;
4511 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4513 hdsp->capture_pid = current->pid;
4514 hdsp->capture_substream = substream;
4516 spin_unlock_irq(&hdsp->lock);
4518 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4519 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4520 if (hdsp->io_type == H9632) {
4521 runtime->hw.channels_min = hdsp->qs_in_channels;
4522 runtime->hw.channels_max = hdsp->ss_in_channels;
4523 runtime->hw.rate_max = 192000;
4524 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4525 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4527 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4528 snd_hdsp_hw_rule_in_channels, hdsp,
4529 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4530 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4531 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4532 SNDRV_PCM_HW_PARAM_RATE, -1);
4533 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4534 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4535 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4539 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4541 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4543 spin_lock_irq(&hdsp->lock);
4545 hdsp->capture_pid = -1;
4546 hdsp->capture_substream = NULL;
4548 spin_unlock_irq(&hdsp->lock);
4552 /* helper functions for copying meter values */
4553 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4555 u32 val = readl(src);
4556 return copy_to_user(dest, &val, 4);
4559 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4561 u32 rms_low, rms_high;
4563 rms_low = readl(src_low);
4564 rms_high = readl(src_high);
4565 rms = ((u64)rms_high << 32) | rms_low;
4566 return copy_to_user(dest, &rms, 8);
4569 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4571 u32 rms_low, rms_high;
4573 rms_low = readl(src_low) & 0xffffff00;
4574 rms_high = readl(src_high) & 0xffffff00;
4575 rms = ((u64)rms_high << 32) | rms_low;
4576 return copy_to_user(dest, &rms, 8);
4579 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4581 int doublespeed = 0;
4582 int i, j, channels, ofs;
4584 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4586 channels = doublespeed ? 14 : 26;
4587 for (i = 0, j = 0; i < 26; ++i) {
4588 if (doublespeed && (i & 4))
4590 ofs = HDSP_9652_peakBase - j * 4;
4591 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4593 ofs -= channels * 4;
4594 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4596 ofs -= channels * 4;
4597 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4599 ofs = HDSP_9652_rmsBase + j * 8;
4600 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4601 hdsp->iobase + ofs + 4))
4603 ofs += channels * 8;
4604 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4605 hdsp->iobase + ofs + 4))
4607 ofs += channels * 8;
4608 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4609 hdsp->iobase + ofs + 4))
4616 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4619 struct hdsp_9632_meters __iomem *m;
4620 int doublespeed = 0;
4622 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4624 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4625 for (i = 0, j = 0; i < 16; ++i, ++j) {
4626 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4628 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4630 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4632 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4633 &m->input_rms_high[j]))
4635 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4636 &m->playback_rms_high[j]))
4638 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4639 &m->output_rms_high[j]))
4641 if (doublespeed && i == 3) i += 4;
4646 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4650 for (i = 0; i < 26; i++) {
4651 if (copy_u32_le(&peak_rms->playback_peaks[i],
4652 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4654 if (copy_u32_le(&peak_rms->input_peaks[i],
4655 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4658 for (i = 0; i < 28; i++) {
4659 if (copy_u32_le(&peak_rms->output_peaks[i],
4660 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4663 for (i = 0; i < 26; ++i) {
4664 if (copy_u64_le(&peak_rms->playback_rms[i],
4665 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4666 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4668 if (copy_u64_le(&peak_rms->input_rms[i],
4669 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4670 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4676 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4678 struct hdsp *hdsp = hw->private_data;
4679 void __user *argp = (void __user *)arg;
4683 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4684 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4686 err = hdsp_check_for_iobox(hdsp);
4690 err = hdsp_check_for_firmware(hdsp, 1);
4694 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4695 dev_err(hdsp->card->dev,
4696 "firmware needs to be uploaded to the card.\n");
4700 switch (hdsp->io_type) {
4702 return hdsp_9652_get_peak(hdsp, peak_rms);
4704 return hdsp_9632_get_peak(hdsp, peak_rms);
4706 return hdsp_get_peak(hdsp, peak_rms);
4709 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4710 struct hdsp_config_info info;
4711 unsigned long flags;
4714 err = hdsp_check_for_iobox(hdsp);
4718 err = hdsp_check_for_firmware(hdsp, 1);
4722 memset(&info, 0, sizeof(info));
4723 spin_lock_irqsave(&hdsp->lock, flags);
4724 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4725 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4726 if (hdsp->io_type != H9632)
4727 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4728 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4729 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4730 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4731 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4732 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4733 HDSP_SPDIFOpticalOut);
4734 info.spdif_professional = (unsigned char)
4735 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4736 info.spdif_emphasis = (unsigned char)
4737 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4738 info.spdif_nonaudio = (unsigned char)
4739 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4740 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4741 info.system_sample_rate = hdsp->system_sample_rate;
4742 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4743 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4744 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4745 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4746 info.line_out = (unsigned char)
4747 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4748 if (hdsp->io_type == H9632) {
4749 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4750 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4751 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4752 info.xlr_breakout_cable =
4753 (unsigned char)hdsp_toggle_setting(hdsp,
4754 HDSP_XLRBreakoutCable);
4756 } else if (hdsp->io_type == RPM) {
4757 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4758 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4760 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4761 info.analog_extension_board =
4762 (unsigned char)hdsp_toggle_setting(hdsp,
4763 HDSP_AnalogExtensionBoard);
4764 spin_unlock_irqrestore(&hdsp->lock, flags);
4765 if (copy_to_user(argp, &info, sizeof(info)))
4769 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4770 struct hdsp_9632_aeb h9632_aeb;
4772 if (hdsp->io_type != H9632) return -EINVAL;
4773 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4774 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4775 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4779 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4780 struct hdsp_version hdsp_version;
4783 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4784 if (hdsp->io_type == Undefined) {
4785 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4788 memset(&hdsp_version, 0, sizeof(hdsp_version));
4789 hdsp_version.io_type = hdsp->io_type;
4790 hdsp_version.firmware_rev = hdsp->firmware_rev;
4791 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4795 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4796 struct hdsp_firmware __user *firmware;
4797 u32 __user *firmware_data;
4800 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4801 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4802 if (hdsp->io_type == Undefined) return -EINVAL;
4804 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4807 dev_info(hdsp->card->dev,
4808 "initializing firmware upload\n");
4809 firmware = (struct hdsp_firmware __user *)argp;
4811 if (get_user(firmware_data, &firmware->firmware_data))
4814 if (hdsp_check_for_iobox (hdsp))
4817 if (!hdsp->fw_uploaded) {
4818 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4819 if (!hdsp->fw_uploaded)
4823 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4824 HDSP_FIRMWARE_SIZE)) {
4825 vfree(hdsp->fw_uploaded);
4826 hdsp->fw_uploaded = NULL;
4830 hdsp->state |= HDSP_FirmwareCached;
4832 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4835 if (!(hdsp->state & HDSP_InitializationComplete)) {
4836 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4839 snd_hdsp_initialize_channels(hdsp);
4840 snd_hdsp_initialize_midi_flush(hdsp);
4842 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4843 dev_err(hdsp->card->dev,
4844 "error creating alsa devices\n");
4850 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4851 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4852 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4862 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4863 .open = snd_hdsp_playback_open,
4864 .close = snd_hdsp_playback_release,
4865 .ioctl = snd_hdsp_ioctl,
4866 .hw_params = snd_hdsp_hw_params,
4867 .prepare = snd_hdsp_prepare,
4868 .trigger = snd_hdsp_trigger,
4869 .pointer = snd_hdsp_hw_pointer,
4870 .copy = snd_hdsp_playback_copy,
4871 .silence = snd_hdsp_hw_silence,
4874 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4875 .open = snd_hdsp_capture_open,
4876 .close = snd_hdsp_capture_release,
4877 .ioctl = snd_hdsp_ioctl,
4878 .hw_params = snd_hdsp_hw_params,
4879 .prepare = snd_hdsp_prepare,
4880 .trigger = snd_hdsp_trigger,
4881 .pointer = snd_hdsp_hw_pointer,
4882 .copy = snd_hdsp_capture_copy,
4885 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4887 struct snd_hwdep *hw;
4890 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4894 hw->private_data = hdsp;
4895 strcpy(hw->name, "HDSP hwdep interface");
4897 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4898 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4903 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4905 struct snd_pcm *pcm;
4908 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4912 pcm->private_data = hdsp;
4913 strcpy(pcm->name, hdsp->card_name);
4915 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4916 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4918 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4923 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4925 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4926 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4929 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4933 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4934 dev_err(hdsp->card->dev,
4935 "enable_io fifo_wait failed\n");
4939 for (i = 0; i < hdsp->max_channels; ++i) {
4940 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4941 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4947 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4949 int status, aebi_channels, aebo_channels;
4951 switch (hdsp->io_type) {
4953 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4954 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4955 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4959 hdsp->card_name = "RME Hammerfall HDSP 9652";
4960 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4961 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4965 status = hdsp_read(hdsp, HDSP_statusRegister);
4966 /* HDSP_AEBx bits are low when AEB are connected */
4967 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4968 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4969 hdsp->card_name = "RME Hammerfall HDSP 9632";
4970 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4971 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4972 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4973 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4974 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4975 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4979 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4980 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4981 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4985 hdsp->card_name = "RME Hammerfall DSP + RPM";
4986 hdsp->ss_in_channels = RPM_CHANNELS-1;
4987 hdsp->ss_out_channels = RPM_CHANNELS;
4988 hdsp->ds_in_channels = RPM_CHANNELS-1;
4989 hdsp->ds_out_channels = RPM_CHANNELS;
4993 /* should never get here */
4998 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5000 snd_hdsp_flush_midi_input (hdsp, 0);
5001 snd_hdsp_flush_midi_input (hdsp, 1);
5004 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5008 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5010 "Error creating pcm interface\n");
5015 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5017 "Error creating first midi interface\n");
5021 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5022 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5024 "Error creating second midi interface\n");
5029 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5031 "Error creating ctl interface\n");
5035 snd_hdsp_proc_init(hdsp);
5037 hdsp->system_sample_rate = -1;
5038 hdsp->playback_pid = -1;
5039 hdsp->capture_pid = -1;
5040 hdsp->capture_substream = NULL;
5041 hdsp->playback_substream = NULL;
5043 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5045 "Error setting default values\n");
5049 if (!(hdsp->state & HDSP_InitializationComplete)) {
5050 strcpy(card->shortname, "Hammerfall DSP");
5051 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5052 hdsp->port, hdsp->irq);
5054 if ((err = snd_card_register(card)) < 0) {
5056 "error registering card\n");
5059 hdsp->state |= HDSP_InitializationComplete;
5065 /* load firmware via hotplug fw loader */
5066 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5069 const struct firmware *fw;
5072 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5074 if (hdsp->io_type == Undefined) {
5075 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5077 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5081 /* caution: max length of firmware filename is 30! */
5082 switch (hdsp->io_type) {
5084 fwfile = "/*(DEBLOBBED)*/";
5087 if (hdsp->firmware_rev == 0xa)
5088 fwfile = "/*(DEBLOBBED)*/";
5090 fwfile = "/*(DEBLOBBED)*/";
5093 if (hdsp->firmware_rev == 0xa)
5094 fwfile = "/*(DEBLOBBED)*/";
5096 fwfile = "/*(DEBLOBBED)*/";
5099 dev_err(hdsp->card->dev,
5100 "invalid io_type %d\n", hdsp->io_type);
5104 if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5105 dev_err(hdsp->card->dev,
5106 "cannot load firmware %s\n", fwfile);
5109 if (fw->size < HDSP_FIRMWARE_SIZE) {
5110 dev_err(hdsp->card->dev,
5111 "too short firmware size %d (expected %d)\n",
5112 (int)fw->size, HDSP_FIRMWARE_SIZE);
5113 release_firmware(fw);
5117 hdsp->firmware = fw;
5119 hdsp->state |= HDSP_FirmwareCached;
5121 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5124 if (!(hdsp->state & HDSP_InitializationComplete)) {
5125 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5128 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5129 dev_err(hdsp->card->dev,
5130 "error creating hwdep device\n");
5133 snd_hdsp_initialize_channels(hdsp);
5134 snd_hdsp_initialize_midi_flush(hdsp);
5135 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5136 dev_err(hdsp->card->dev,
5137 "error creating alsa devices\n");
5144 static int snd_hdsp_create(struct snd_card *card,
5147 struct pci_dev *pci = hdsp->pci;
5154 hdsp->midi[0].rmidi = NULL;
5155 hdsp->midi[1].rmidi = NULL;
5156 hdsp->midi[0].input = NULL;
5157 hdsp->midi[1].input = NULL;
5158 hdsp->midi[0].output = NULL;
5159 hdsp->midi[1].output = NULL;
5160 hdsp->midi[0].pending = 0;
5161 hdsp->midi[1].pending = 0;
5162 spin_lock_init(&hdsp->midi[0].lock);
5163 spin_lock_init(&hdsp->midi[1].lock);
5164 hdsp->iobase = NULL;
5165 hdsp->control_register = 0;
5166 hdsp->control2_register = 0;
5167 hdsp->io_type = Undefined;
5168 hdsp->max_channels = 26;
5172 spin_lock_init(&hdsp->lock);
5174 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5176 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5177 hdsp->firmware_rev &= 0xff;
5179 /* From Martin Bjoernsen :
5180 "It is important that the card's latency timer register in
5181 the PCI configuration space is set to a value much larger
5182 than 0 by the computer's BIOS or the driver.
5183 The windows driver always sets this 8 bit register [...]
5184 to its maximum 255 to avoid problems with some computers."
5186 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5188 strcpy(card->driver, "H-DSP");
5189 strcpy(card->mixername, "Xilinx FPGA");
5191 if (hdsp->firmware_rev < 0xa)
5193 else if (hdsp->firmware_rev < 0x64)
5194 hdsp->card_name = "RME Hammerfall DSP";
5195 else if (hdsp->firmware_rev < 0x96) {
5196 hdsp->card_name = "RME HDSP 9652";
5199 hdsp->card_name = "RME HDSP 9632";
5200 hdsp->max_channels = 16;
5204 if ((err = pci_enable_device(pci)) < 0)
5207 pci_set_master(hdsp->pci);
5209 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5211 hdsp->port = pci_resource_start(pci, 0);
5212 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5213 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5214 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5218 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5219 KBUILD_MODNAME, hdsp)) {
5220 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5224 hdsp->irq = pci->irq;
5225 hdsp->precise_ptr = 0;
5226 hdsp->use_midi_tasklet = 1;
5227 hdsp->dds_value = 0;
5229 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5232 if (!is_9652 && !is_9632) {
5233 /* we wait a maximum of 10 seconds to let freshly
5234 * inserted cardbus cards do their hardware init */
5235 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5240 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5241 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5242 /* we don't fail as this can happen
5243 if userspace is not ready for
5246 dev_err(hdsp->card->dev,
5247 "couldn't get firmware from userspace. try using hdsploader\n");
5249 /* init is complete, we return */
5251 /* we defer initialization */
5252 dev_info(hdsp->card->dev,
5253 "card initialization pending : waiting for firmware\n");
5254 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5258 dev_info(hdsp->card->dev,
5259 "Firmware already present, initializing card.\n");
5260 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5261 hdsp->io_type = RPM;
5262 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5263 hdsp->io_type = Multiface;
5265 hdsp->io_type = Digiface;
5269 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5273 hdsp->io_type = H9652;
5276 hdsp->io_type = H9632;
5278 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5281 snd_hdsp_initialize_channels(hdsp);
5282 snd_hdsp_initialize_midi_flush(hdsp);
5284 hdsp->state |= HDSP_FirmwareLoaded;
5286 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5292 static int snd_hdsp_free(struct hdsp *hdsp)
5295 /* stop the audio, and cancel all interrupts */
5296 tasklet_kill(&hdsp->midi_tasklet);
5297 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5298 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5302 free_irq(hdsp->irq, (void *)hdsp);
5304 snd_hdsp_free_buffers(hdsp);
5306 release_firmware(hdsp->firmware);
5307 vfree(hdsp->fw_uploaded);
5308 iounmap(hdsp->iobase);
5311 pci_release_regions(hdsp->pci);
5313 if (pci_is_enabled(hdsp->pci))
5314 pci_disable_device(hdsp->pci);
5318 static void snd_hdsp_card_free(struct snd_card *card)
5320 struct hdsp *hdsp = card->private_data;
5323 snd_hdsp_free(hdsp);
5326 static int snd_hdsp_probe(struct pci_dev *pci,
5327 const struct pci_device_id *pci_id)
5331 struct snd_card *card;
5334 if (dev >= SNDRV_CARDS)
5341 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5342 sizeof(struct hdsp), &card);
5346 hdsp = card->private_data;
5347 card->private_free = snd_hdsp_card_free;
5351 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5352 snd_card_free(card);
5356 strcpy(card->shortname, "Hammerfall DSP");
5357 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5358 hdsp->port, hdsp->irq);
5360 if ((err = snd_card_register(card)) < 0) {
5361 snd_card_free(card);
5364 pci_set_drvdata(pci, card);
5369 static void snd_hdsp_remove(struct pci_dev *pci)
5371 snd_card_free(pci_get_drvdata(pci));
5374 static struct pci_driver hdsp_driver = {
5375 .name = KBUILD_MODNAME,
5376 .id_table = snd_hdsp_ids,
5377 .probe = snd_hdsp_probe,
5378 .remove = snd_hdsp_remove,
5381 module_pci_driver(hdsp_driver);