1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
52 #define HDSP_MAX_CHANNELS 26
53 #define HDSP_MAX_DS_CHANNELS 14
54 #define HDSP_MAX_QS_CHANNELS 8
55 #define DIGIFACE_SS_CHANNELS 26
56 #define DIGIFACE_DS_CHANNELS 14
57 #define MULTIFACE_SS_CHANNELS 18
58 #define MULTIFACE_DS_CHANNELS 14
59 #define H9652_SS_CHANNELS 26
60 #define H9652_DS_CHANNELS 14
61 /* This does not include possible Analog Extension Boards
62 AEBs are detected at card initialization
64 #define H9632_SS_CHANNELS 12
65 #define H9632_DS_CHANNELS 8
66 #define H9632_QS_CHANNELS 4
67 #define RPM_CHANNELS 6
69 /* Write registers. These are defined as byte-offsets from the iobase value.
71 #define HDSP_resetPointer 0
72 #define HDSP_freqReg 0
73 #define HDSP_outputBufferAddress 32
74 #define HDSP_inputBufferAddress 36
75 #define HDSP_controlRegister 64
76 #define HDSP_interruptConfirmation 96
77 #define HDSP_outputEnable 128
78 #define HDSP_control2Reg 256
79 #define HDSP_midiDataOut0 352
80 #define HDSP_midiDataOut1 356
81 #define HDSP_fifoData 368
82 #define HDSP_inputEnable 384
84 /* Read registers. These are defined as byte-offsets from the iobase value
87 #define HDSP_statusRegister 0
88 #define HDSP_timecode 128
89 #define HDSP_status2Register 192
90 #define HDSP_midiDataIn0 360
91 #define HDSP_midiDataIn1 364
92 #define HDSP_midiStatusOut0 384
93 #define HDSP_midiStatusOut1 388
94 #define HDSP_midiStatusIn0 392
95 #define HDSP_midiStatusIn1 396
96 #define HDSP_fifoStatus 400
98 /* the meters are regular i/o-mapped registers, but offset
99 considerably from the rest. the peak registers are reset
100 when read; the least-significant 4 bits are full-scale counters;
101 the actual peak value is in the most-significant 24 bits.
104 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
105 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
106 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
107 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
108 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
111 /* This is for H9652 cards
112 Peak values are read downward from the base
113 Rms values are read upward
114 There are rms values for the outputs too
115 26*3 values are read in ss mode
116 14*3 in ds mode, with no gap between values
118 #define HDSP_9652_peakBase 7164
119 #define HDSP_9652_rmsBase 4096
121 /* c.f. the hdsp_9632_meters_t struct */
122 #define HDSP_9632_metersBase 4096
124 #define HDSP_IO_EXTENT 7168
126 /* control2 register bits */
128 #define HDSP_TMS 0x01
129 #define HDSP_TCK 0x02
130 #define HDSP_TDI 0x04
131 #define HDSP_JTAG 0x08
132 #define HDSP_PWDN 0x10
133 #define HDSP_PROGRAM 0x020
134 #define HDSP_CONFIG_MODE_0 0x040
135 #define HDSP_CONFIG_MODE_1 0x080
136 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
137 #define HDSP_BIGENDIAN_MODE 0x200
138 #define HDSP_RD_MULTIPLE 0x400
139 #define HDSP_9652_ENABLE_MIXER 0x800
140 #define HDSP_S200 0x800
141 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
142 #define HDSP_CYCLIC_MODE 0x1000
143 #define HDSP_TDO 0x10000000
145 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
146 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
148 /* Control Register bits */
150 #define HDSP_Start (1<<0) /* start engine */
151 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
152 #define HDSP_Latency1 (1<<2) /* [ see above ] */
153 #define HDSP_Latency2 (1<<3) /* [ see above ] */
154 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
155 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
156 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
157 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
158 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
159 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
160 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
161 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
162 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
163 #define HDSP_SyncRef2 (1<<13)
164 #define HDSP_SPDIFInputSelect0 (1<<14)
165 #define HDSP_SPDIFInputSelect1 (1<<15)
166 #define HDSP_SyncRef0 (1<<16)
167 #define HDSP_SyncRef1 (1<<17)
168 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
169 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
170 #define HDSP_Midi0InterruptEnable (1<<22)
171 #define HDSP_Midi1InterruptEnable (1<<23)
172 #define HDSP_LineOut (1<<24)
173 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
174 #define HDSP_ADGain1 (1<<26)
175 #define HDSP_DAGain0 (1<<27)
176 #define HDSP_DAGain1 (1<<28)
177 #define HDSP_PhoneGain0 (1<<29)
178 #define HDSP_PhoneGain1 (1<<30)
179 #define HDSP_QuadSpeed (1<<31)
181 /* RPM uses some of the registers for special purposes */
182 #define HDSP_RPM_Inp12 0x04A00
183 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
184 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
185 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
186 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
187 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
189 #define HDSP_RPM_Inp34 0x32000
190 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
191 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
192 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
193 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
194 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
196 #define HDSP_RPM_Bypass 0x01000
198 #define HDSP_RPM_Disconnect 0x00001
200 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
201 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
202 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
203 #define HDSP_ADGainLowGain 0
205 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
206 #define HDSP_DAGainHighGain HDSP_DAGainMask
207 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
208 #define HDSP_DAGainMinus10dBV 0
210 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
211 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
212 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
213 #define HDSP_PhoneGainMinus12dB 0
215 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
216 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
218 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
219 #define HDSP_SPDIFInputADAT1 0
220 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
221 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
222 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
224 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
225 #define HDSP_SyncRef_ADAT1 0
226 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
227 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
228 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
229 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
230 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
232 /* Sample Clock Sources */
234 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
235 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
236 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
237 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
238 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
239 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
240 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
241 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
242 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
243 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
245 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
247 #define HDSP_SYNC_FROM_WORD 0
248 #define HDSP_SYNC_FROM_SPDIF 1
249 #define HDSP_SYNC_FROM_ADAT1 2
250 #define HDSP_SYNC_FROM_ADAT_SYNC 3
251 #define HDSP_SYNC_FROM_ADAT2 4
252 #define HDSP_SYNC_FROM_ADAT3 5
254 /* SyncCheck status */
256 #define HDSP_SYNC_CHECK_NO_LOCK 0
257 #define HDSP_SYNC_CHECK_LOCK 1
258 #define HDSP_SYNC_CHECK_SYNC 2
260 /* AutoSync references - used by "autosync_ref" control switch */
262 #define HDSP_AUTOSYNC_FROM_WORD 0
263 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
264 #define HDSP_AUTOSYNC_FROM_SPDIF 2
265 #define HDSP_AUTOSYNC_FROM_NONE 3
266 #define HDSP_AUTOSYNC_FROM_ADAT1 4
267 #define HDSP_AUTOSYNC_FROM_ADAT2 5
268 #define HDSP_AUTOSYNC_FROM_ADAT3 6
270 /* Possible sources of S/PDIF input */
272 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
273 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
274 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
275 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
277 #define HDSP_Frequency32KHz HDSP_Frequency0
278 #define HDSP_Frequency44_1KHz HDSP_Frequency1
279 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
280 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
281 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
282 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
283 /* For H9632 cards */
284 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
285 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
286 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
288 return 104857600000000 / rate; // 100 MHz
289 return 110100480000000 / rate; // 105 MHz
291 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
293 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
294 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
296 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
297 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
299 /* Status Register bits */
301 #define HDSP_audioIRQPending (1<<0)
302 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
303 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
304 #define HDSP_Lock1 (1<<2)
305 #define HDSP_Lock0 (1<<3)
306 #define HDSP_SPDIFSync (1<<4)
307 #define HDSP_TimecodeLock (1<<5)
308 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
309 #define HDSP_Sync2 (1<<16)
310 #define HDSP_Sync1 (1<<17)
311 #define HDSP_Sync0 (1<<18)
312 #define HDSP_DoubleSpeedStatus (1<<19)
313 #define HDSP_ConfigError (1<<20)
314 #define HDSP_DllError (1<<21)
315 #define HDSP_spdifFrequency0 (1<<22)
316 #define HDSP_spdifFrequency1 (1<<23)
317 #define HDSP_spdifFrequency2 (1<<24)
318 #define HDSP_SPDIFErrorFlag (1<<25)
319 #define HDSP_BufferID (1<<26)
320 #define HDSP_TimecodeSync (1<<27)
321 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
322 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
323 #define HDSP_midi0IRQPending (1<<30)
324 #define HDSP_midi1IRQPending (1<<31)
326 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
327 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
328 HDSP_spdifFrequency1|\
329 HDSP_spdifFrequency2|\
330 HDSP_spdifFrequency3)
332 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
333 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
334 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
336 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
337 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
338 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
340 /* This is for H9632 cards */
341 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
342 HDSP_spdifFrequency1|\
343 HDSP_spdifFrequency2)
344 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
345 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
347 /* Status2 Register bits */
349 #define HDSP_version0 (1<<0)
350 #define HDSP_version1 (1<<1)
351 #define HDSP_version2 (1<<2)
352 #define HDSP_wc_lock (1<<3)
353 #define HDSP_wc_sync (1<<4)
354 #define HDSP_inp_freq0 (1<<5)
355 #define HDSP_inp_freq1 (1<<6)
356 #define HDSP_inp_freq2 (1<<7)
357 #define HDSP_SelSyncRef0 (1<<8)
358 #define HDSP_SelSyncRef1 (1<<9)
359 #define HDSP_SelSyncRef2 (1<<10)
361 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
363 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
364 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
365 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
366 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
367 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
368 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
369 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
370 /* FIXME : more values for 9632 cards ? */
372 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
373 #define HDSP_SelSyncRef_ADAT1 0
374 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
375 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
376 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
377 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
378 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
380 /* Card state flags */
382 #define HDSP_InitializationComplete (1<<0)
383 #define HDSP_FirmwareLoaded (1<<1)
384 #define HDSP_FirmwareCached (1<<2)
386 /* FIFO wait times, defined in terms of 1/10ths of msecs */
388 #define HDSP_LONG_WAIT 5000
389 #define HDSP_SHORT_WAIT 30
391 #define UNITY_GAIN 32768
392 #define MINUS_INFINITY_GAIN 0
394 /* the size of a substream (1 mono data stream) */
396 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
397 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
399 /* the size of the area we need to allocate for DMA transfers. the
400 size is the same regardless of the number of channels - the
401 Multiface still uses the same memory area.
403 Note that we allocate 1 more channel than is apparently needed
404 because the h/w seems to write 1 byte beyond the end of the last
408 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
409 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
411 #define HDSP_FIRMWARE_SIZE (24413 * 4)
413 struct hdsp_9632_meters {
415 u32 playback_peak[16];
419 u32 input_rms_low[16];
420 u32 playback_rms_low[16];
421 u32 output_rms_low[16];
423 u32 input_rms_high[16];
424 u32 playback_rms_high[16];
425 u32 output_rms_high[16];
426 u32 xxx_rms_high[16];
432 struct snd_rawmidi *rmidi;
433 struct snd_rawmidi_substream *input;
434 struct snd_rawmidi_substream *output;
435 char istimer; /* timer in use */
436 struct timer_list timer;
443 struct snd_pcm_substream *capture_substream;
444 struct snd_pcm_substream *playback_substream;
445 struct hdsp_midi midi[2];
446 struct tasklet_struct midi_tasklet;
447 int use_midi_tasklet;
449 u32 control_register; /* cached value */
450 u32 control2_register; /* cached value */
452 u32 creg_spdif_stream;
453 int clock_source_locked;
454 char *card_name; /* digiface/multiface/rpm */
455 enum HDSP_IO_Type io_type; /* ditto, but for code use */
456 unsigned short firmware_rev;
457 unsigned short state; /* stores state bits */
458 const struct firmware *firmware;
460 size_t period_bytes; /* guess what this is */
461 unsigned char max_channels;
462 unsigned char qs_in_channels; /* quad speed mode for H9632 */
463 unsigned char ds_in_channels;
464 unsigned char ss_in_channels; /* different for multiface/digiface */
465 unsigned char qs_out_channels;
466 unsigned char ds_out_channels;
467 unsigned char ss_out_channels;
469 struct snd_dma_buffer capture_dma_buf;
470 struct snd_dma_buffer playback_dma_buf;
471 unsigned char *capture_buffer; /* suitably aligned address */
472 unsigned char *playback_buffer; /* suitably aligned address */
477 int system_sample_rate;
482 void __iomem *iobase;
483 struct snd_card *card;
485 struct snd_hwdep *hwdep;
487 struct snd_kcontrol *spdif_ctl;
488 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
489 unsigned int dds_value; /* last value written to freq register */
492 /* These tables map the ALSA channels 1..N to the channels that we
493 need to use in order to find the relevant channel buffer. RME
494 refer to this kind of mapping as between "the ADAT channel and
495 the DMA channel." We index it using the logical audio channel,
496 and the value is the DMA channel (i.e. channel buffer number)
497 where the data for that channel can be read/written from/to.
500 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
501 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
502 18, 19, 20, 21, 22, 23, 24, 25
505 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
507 0, 1, 2, 3, 4, 5, 6, 7,
509 16, 17, 18, 19, 20, 21, 22, 23,
512 -1, -1, -1, -1, -1, -1, -1, -1
515 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
516 /* ADAT channels are remapped */
517 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
518 /* channels 12 and 13 are S/PDIF */
520 /* others don't exist */
521 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
524 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
526 0, 1, 2, 3, 4, 5, 6, 7,
531 /* AO4S-192 and AI4S-192 extension boards */
533 /* others don't exist */
534 -1, -1, -1, -1, -1, -1, -1, -1,
538 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
545 /* AO4S-192 and AI4S-192 extension boards */
547 /* others don't exist */
548 -1, -1, -1, -1, -1, -1, -1, -1,
549 -1, -1, -1, -1, -1, -1
552 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
553 /* ADAT is disabled in this mode */
558 /* AO4S-192 and AI4S-192 extension boards */
560 /* others don't exist */
561 -1, -1, -1, -1, -1, -1, -1, -1,
562 -1, -1, -1, -1, -1, -1, -1, -1,
566 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
568 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
569 dmab->dev.dev = snd_dma_pci_data(pci);
570 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
576 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
579 snd_dma_free_pages(dmab);
583 static const struct pci_device_id snd_hdsp_ids[] = {
585 .vendor = PCI_VENDOR_ID_XILINX,
586 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
587 .subvendor = PCI_ANY_ID,
588 .subdevice = PCI_ANY_ID,
589 }, /* RME Hammerfall-DSP */
593 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
596 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
597 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
598 static int snd_hdsp_enable_io (struct hdsp *hdsp);
599 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
600 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
601 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
602 static int hdsp_autosync_ref(struct hdsp *hdsp);
603 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
604 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
606 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
608 switch (hdsp->io_type) {
613 if (hdsp->firmware_rev == 0xa)
614 return (64 * out) + (32 + (in));
616 return (52 * out) + (26 + (in));
618 return (32 * out) + (16 + (in));
620 return (52 * out) + (26 + (in));
624 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
626 switch (hdsp->io_type) {
631 if (hdsp->firmware_rev == 0xa)
632 return (64 * out) + in;
634 return (52 * out) + in;
636 return (32 * out) + in;
638 return (52 * out) + in;
642 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
644 writel(val, hdsp->iobase + reg);
647 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
649 return readl (hdsp->iobase + reg);
652 static int hdsp_check_for_iobox (struct hdsp *hdsp)
656 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
657 for (i = 0; i < 500; i++) {
658 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
661 dev_dbg(hdsp->card->dev,
662 "IO box found after %d ms\n",
669 dev_err(hdsp->card->dev, "no IO box connected!\n");
670 hdsp->state &= ~HDSP_FirmwareLoaded;
674 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
679 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
682 for (i = 0; i != loops; ++i) {
683 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
686 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
692 dev_info(hdsp->card->dev, "no IO box connected!\n");
693 hdsp->state &= ~HDSP_FirmwareLoaded;
697 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
703 if (hdsp->fw_uploaded)
704 cache = hdsp->fw_uploaded;
708 cache = (u32 *)hdsp->firmware->data;
713 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
715 dev_info(hdsp->card->dev, "loading firmware\n");
717 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
718 hdsp_write (hdsp, HDSP_fifoData, 0);
720 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
721 dev_info(hdsp->card->dev,
722 "timeout waiting for download preparation\n");
723 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
727 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
729 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
730 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
731 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
732 dev_info(hdsp->card->dev,
733 "timeout during firmware loading\n");
734 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
739 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
740 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
743 #ifdef SNDRV_BIG_ENDIAN
744 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
746 hdsp->control2_register = 0;
748 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
749 dev_info(hdsp->card->dev, "finished firmware loading\n");
752 if (hdsp->state & HDSP_InitializationComplete) {
753 dev_info(hdsp->card->dev,
754 "firmware loaded from cache, restoring defaults\n");
755 spin_lock_irqsave(&hdsp->lock, flags);
756 snd_hdsp_set_defaults(hdsp);
757 spin_unlock_irqrestore(&hdsp->lock, flags);
760 hdsp->state |= HDSP_FirmwareLoaded;
765 static int hdsp_get_iobox_version (struct hdsp *hdsp)
767 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
769 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
770 hdsp_write(hdsp, HDSP_fifoData, 0);
772 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
773 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
774 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
777 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
778 hdsp_write (hdsp, HDSP_fifoData, 0);
779 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
782 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
783 hdsp_write(hdsp, HDSP_fifoData, 0);
784 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
785 hdsp->io_type = Digiface;
786 dev_info(hdsp->card->dev, "Digiface found\n");
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
792 hdsp_write(hdsp, HDSP_fifoData, 0);
793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
797 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
798 hdsp_write(hdsp, HDSP_fifoData, 0);
799 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
803 dev_info(hdsp->card->dev, "RPM found\n");
806 /* firmware was already loaded, get iobox type */
807 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
809 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
810 hdsp->io_type = Multiface;
812 hdsp->io_type = Digiface;
817 hdsp->io_type = Multiface;
818 dev_info(hdsp->card->dev, "Multiface found\n");
823 static int hdsp_request_fw_loader(struct hdsp *hdsp);
825 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
827 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
829 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
830 hdsp->state &= ~HDSP_FirmwareLoaded;
831 if (! load_on_demand)
833 dev_err(hdsp->card->dev, "firmware not present.\n");
834 /* try to load firmware */
835 if (! (hdsp->state & HDSP_FirmwareCached)) {
836 if (! hdsp_request_fw_loader(hdsp))
838 dev_err(hdsp->card->dev,
839 "No firmware loaded nor cached, please upload firmware.\n");
842 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
843 dev_err(hdsp->card->dev,
844 "Firmware loading from cache failed, please upload manually.\n");
852 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
856 /* the fifoStatus registers reports on how many words
857 are available in the command FIFO.
860 for (i = 0; i < timeout; i++) {
862 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
865 /* not very friendly, but we only do this during a firmware
866 load and changing the mixer, so we just put up with it.
872 dev_warn(hdsp->card->dev,
873 "wait for FIFO status <= %d failed after %d iterations\n",
878 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
880 if (addr >= HDSP_MATRIX_MIXER_SIZE)
883 return hdsp->mixer_matrix[addr];
886 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
890 if (addr >= HDSP_MATRIX_MIXER_SIZE)
893 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
895 /* from martin bjornsen:
897 "You can only write dwords to the
898 mixer memory which contain two
899 mixer values in the low and high
900 word. So if you want to change
901 value 0 you have to read value 1
902 from the cache and write both to
903 the first dword in the mixer
907 if (hdsp->io_type == H9632 && addr >= 512)
910 if (hdsp->io_type == H9652 && addr >= 1352)
913 hdsp->mixer_matrix[addr] = data;
916 /* `addr' addresses a 16-bit wide address, but
917 the address space accessed via hdsp_write
918 uses byte offsets. put another way, addr
919 varies from 0 to 1351, but to access the
920 corresponding memory location, we need
921 to access 0 to 2703 ...
925 hdsp_write (hdsp, 4096 + (ad*4),
926 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
927 hdsp->mixer_matrix[addr&0x7fe]);
933 ad = (addr << 16) + data;
935 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
938 hdsp_write (hdsp, HDSP_fifoData, ad);
939 hdsp->mixer_matrix[addr] = data;
946 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
951 spin_lock_irqsave(&hdsp->lock, flags);
952 if ((hdsp->playback_pid != hdsp->capture_pid) &&
953 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
955 spin_unlock_irqrestore(&hdsp->lock, flags);
959 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
961 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
962 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
964 /* For the 9632, the mask is different */
965 if (hdsp->io_type == H9632)
966 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
968 if (status & HDSP_SPDIFErrorFlag)
972 case HDSP_spdifFrequency32KHz: return 32000;
973 case HDSP_spdifFrequency44_1KHz: return 44100;
974 case HDSP_spdifFrequency48KHz: return 48000;
975 case HDSP_spdifFrequency64KHz: return 64000;
976 case HDSP_spdifFrequency88_2KHz: return 88200;
977 case HDSP_spdifFrequency96KHz: return 96000;
978 case HDSP_spdifFrequency128KHz:
979 if (hdsp->io_type == H9632) return 128000;
981 case HDSP_spdifFrequency176_4KHz:
982 if (hdsp->io_type == H9632) return 176400;
984 case HDSP_spdifFrequency192KHz:
985 if (hdsp->io_type == H9632) return 192000;
990 dev_warn(hdsp->card->dev,
991 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
996 static int hdsp_external_sample_rate(struct hdsp *hdsp)
998 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
999 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1001 /* For the 9632 card, there seems to be no bit for indicating external
1002 * sample rate greater than 96kHz. The card reports the corresponding
1003 * single speed. So the best means seems to get spdif rate when
1004 * autosync reference is spdif */
1005 if (hdsp->io_type == H9632 &&
1006 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1007 return hdsp_spdif_sample_rate(hdsp);
1009 switch (rate_bits) {
1010 case HDSP_systemFrequency32: return 32000;
1011 case HDSP_systemFrequency44_1: return 44100;
1012 case HDSP_systemFrequency48: return 48000;
1013 case HDSP_systemFrequency64: return 64000;
1014 case HDSP_systemFrequency88_2: return 88200;
1015 case HDSP_systemFrequency96: return 96000;
1021 static void hdsp_compute_period_size(struct hdsp *hdsp)
1023 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1026 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1030 position = hdsp_read(hdsp, HDSP_statusRegister);
1032 if (!hdsp->precise_ptr)
1033 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1035 position &= HDSP_BufferPositionMask;
1037 position &= (hdsp->period_bytes/2) - 1;
1041 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1043 hdsp_write (hdsp, HDSP_resetPointer, 0);
1044 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1045 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1046 * requires (?) to write again DDS value after a reset pointer
1047 * (at least, it works like this) */
1048 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1051 static void hdsp_start_audio(struct hdsp *s)
1053 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1054 hdsp_write(s, HDSP_controlRegister, s->control_register);
1057 static void hdsp_stop_audio(struct hdsp *s)
1059 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1060 hdsp_write(s, HDSP_controlRegister, s->control_register);
1063 static void hdsp_silence_playback(struct hdsp *hdsp)
1065 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1068 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1072 spin_lock_irq(&s->lock);
1081 s->control_register &= ~HDSP_LatencyMask;
1082 s->control_register |= hdsp_encode_latency(n);
1084 hdsp_write(s, HDSP_controlRegister, s->control_register);
1086 hdsp_compute_period_size(s);
1088 spin_unlock_irq(&s->lock);
1093 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1099 else if (rate >= 56000)
1103 n = div_u64(n, rate);
1104 /* n should be less than 2^32 for being written to FREQ register */
1105 snd_BUG_ON(n >> 32);
1106 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1107 value to write it after a reset */
1108 hdsp->dds_value = n;
1109 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1112 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1114 int reject_if_open = 0;
1118 /* ASSUMPTION: hdsp->lock is either held, or
1119 there is no need for it (e.g. during module
1123 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1124 if (called_internally) {
1125 /* request from ctl or card initialization */
1126 dev_err(hdsp->card->dev,
1127 "device is not running as a clock master: cannot set sample rate.\n");
1130 /* hw_param request while in AutoSync mode */
1131 int external_freq = hdsp_external_sample_rate(hdsp);
1132 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1134 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1135 dev_info(hdsp->card->dev,
1136 "Detected ADAT in double speed mode\n");
1137 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1138 dev_info(hdsp->card->dev,
1139 "Detected ADAT in quad speed mode\n");
1140 else if (rate != external_freq) {
1141 dev_info(hdsp->card->dev,
1142 "No AutoSync source for requested rate\n");
1148 current_rate = hdsp->system_sample_rate;
1150 /* Changing from a "single speed" to a "double speed" rate is
1151 not allowed if any substreams are open. This is because
1152 such a change causes a shift in the location of
1153 the DMA buffers and a reduction in the number of available
1156 Note that a similar but essentially insoluble problem
1157 exists for externally-driven rate changes. All we can do
1158 is to flag rate changes in the read/write routines. */
1160 if (rate > 96000 && hdsp->io_type != H9632)
1165 if (current_rate > 48000)
1167 rate_bits = HDSP_Frequency32KHz;
1170 if (current_rate > 48000)
1172 rate_bits = HDSP_Frequency44_1KHz;
1175 if (current_rate > 48000)
1177 rate_bits = HDSP_Frequency48KHz;
1180 if (current_rate <= 48000 || current_rate > 96000)
1182 rate_bits = HDSP_Frequency64KHz;
1185 if (current_rate <= 48000 || current_rate > 96000)
1187 rate_bits = HDSP_Frequency88_2KHz;
1190 if (current_rate <= 48000 || current_rate > 96000)
1192 rate_bits = HDSP_Frequency96KHz;
1195 if (current_rate < 128000)
1197 rate_bits = HDSP_Frequency128KHz;
1200 if (current_rate < 128000)
1202 rate_bits = HDSP_Frequency176_4KHz;
1205 if (current_rate < 128000)
1207 rate_bits = HDSP_Frequency192KHz;
1213 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1214 dev_warn(hdsp->card->dev,
1215 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1217 hdsp->playback_pid);
1221 hdsp->control_register &= ~HDSP_FrequencyMask;
1222 hdsp->control_register |= rate_bits;
1223 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1225 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1226 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1227 hdsp_set_dds_value(hdsp, rate);
1229 if (rate >= 128000) {
1230 hdsp->channel_map = channel_map_H9632_qs;
1231 } else if (rate > 48000) {
1232 if (hdsp->io_type == H9632)
1233 hdsp->channel_map = channel_map_H9632_ds;
1235 hdsp->channel_map = channel_map_ds;
1237 switch (hdsp->io_type) {
1240 hdsp->channel_map = channel_map_mf_ss;
1244 hdsp->channel_map = channel_map_df_ss;
1247 hdsp->channel_map = channel_map_H9632_ss;
1250 /* should never happen */
1255 hdsp->system_sample_rate = rate;
1260 /*----------------------------------------------------------------------------
1262 ----------------------------------------------------------------------------*/
1264 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1266 /* the hardware already does the relevant bit-mask with 0xff */
1268 return hdsp_read(hdsp, HDSP_midiDataIn1);
1270 return hdsp_read(hdsp, HDSP_midiDataIn0);
1273 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1275 /* the hardware already does the relevant bit-mask with 0xff */
1277 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1279 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1282 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1285 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1287 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1290 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1292 int fifo_bytes_used;
1295 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1297 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1299 if (fifo_bytes_used < 128)
1300 return 128 - fifo_bytes_used;
1305 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1307 while (snd_hdsp_midi_input_available (hdsp, id))
1308 snd_hdsp_midi_read_byte (hdsp, id);
1311 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1313 unsigned long flags;
1317 unsigned char buf[128];
1319 /* Output is not interrupt driven */
1321 spin_lock_irqsave (&hmidi->lock, flags);
1322 if (hmidi->output) {
1323 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1324 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1325 if (n_pending > (int)sizeof (buf))
1326 n_pending = sizeof (buf);
1328 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1329 for (i = 0; i < to_write; ++i)
1330 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1335 spin_unlock_irqrestore (&hmidi->lock, flags);
1339 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1341 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1342 unsigned long flags;
1346 spin_lock_irqsave (&hmidi->lock, flags);
1347 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1349 if (n_pending > (int)sizeof (buf))
1350 n_pending = sizeof (buf);
1351 for (i = 0; i < n_pending; ++i)
1352 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1354 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1356 /* flush the MIDI input FIFO */
1358 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1363 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1365 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1366 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1367 spin_unlock_irqrestore (&hmidi->lock, flags);
1368 return snd_hdsp_midi_output_write (hmidi);
1371 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1374 struct hdsp_midi *hmidi;
1375 unsigned long flags;
1378 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1380 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1381 spin_lock_irqsave (&hdsp->lock, flags);
1383 if (!(hdsp->control_register & ie)) {
1384 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1385 hdsp->control_register |= ie;
1388 hdsp->control_register &= ~ie;
1389 tasklet_kill(&hdsp->midi_tasklet);
1392 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1393 spin_unlock_irqrestore (&hdsp->lock, flags);
1396 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1398 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1399 unsigned long flags;
1401 snd_hdsp_midi_output_write(hmidi);
1402 spin_lock_irqsave (&hmidi->lock, flags);
1404 /* this does not bump hmidi->istimer, because the
1405 kernel automatically removed the timer when it
1406 expired, and we are now adding it back, thus
1407 leaving istimer wherever it was set before.
1411 mod_timer(&hmidi->timer, 1 + jiffies);
1413 spin_unlock_irqrestore (&hmidi->lock, flags);
1416 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1418 struct hdsp_midi *hmidi;
1419 unsigned long flags;
1421 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1422 spin_lock_irqsave (&hmidi->lock, flags);
1424 if (!hmidi->istimer) {
1425 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1427 mod_timer(&hmidi->timer, 1 + jiffies);
1431 if (hmidi->istimer && --hmidi->istimer <= 0)
1432 del_timer (&hmidi->timer);
1434 spin_unlock_irqrestore (&hmidi->lock, flags);
1436 snd_hdsp_midi_output_write(hmidi);
1439 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1441 struct hdsp_midi *hmidi;
1443 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1444 spin_lock_irq (&hmidi->lock);
1445 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1446 hmidi->input = substream;
1447 spin_unlock_irq (&hmidi->lock);
1452 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1454 struct hdsp_midi *hmidi;
1456 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1457 spin_lock_irq (&hmidi->lock);
1458 hmidi->output = substream;
1459 spin_unlock_irq (&hmidi->lock);
1464 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1466 struct hdsp_midi *hmidi;
1468 snd_hdsp_midi_input_trigger (substream, 0);
1470 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1471 spin_lock_irq (&hmidi->lock);
1472 hmidi->input = NULL;
1473 spin_unlock_irq (&hmidi->lock);
1478 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1480 struct hdsp_midi *hmidi;
1482 snd_hdsp_midi_output_trigger (substream, 0);
1484 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1485 spin_lock_irq (&hmidi->lock);
1486 hmidi->output = NULL;
1487 spin_unlock_irq (&hmidi->lock);
1492 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1494 .open = snd_hdsp_midi_output_open,
1495 .close = snd_hdsp_midi_output_close,
1496 .trigger = snd_hdsp_midi_output_trigger,
1499 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1501 .open = snd_hdsp_midi_input_open,
1502 .close = snd_hdsp_midi_input_close,
1503 .trigger = snd_hdsp_midi_input_trigger,
1506 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1510 hdsp->midi[id].id = id;
1511 hdsp->midi[id].rmidi = NULL;
1512 hdsp->midi[id].input = NULL;
1513 hdsp->midi[id].output = NULL;
1514 hdsp->midi[id].hdsp = hdsp;
1515 hdsp->midi[id].istimer = 0;
1516 hdsp->midi[id].pending = 0;
1517 spin_lock_init (&hdsp->midi[id].lock);
1519 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1520 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1523 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1524 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1526 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1527 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1529 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1530 SNDRV_RAWMIDI_INFO_INPUT |
1531 SNDRV_RAWMIDI_INFO_DUPLEX;
1536 /*-----------------------------------------------------------------------------
1538 ----------------------------------------------------------------------------*/
1540 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1543 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1544 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1545 if (val & HDSP_SPDIFProfessional)
1546 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1548 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1552 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1554 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1555 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1556 if (val & HDSP_SPDIFProfessional)
1557 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1559 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1562 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1564 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1569 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1571 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1573 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1577 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1579 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1583 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1584 spin_lock_irq(&hdsp->lock);
1585 change = val != hdsp->creg_spdif;
1586 hdsp->creg_spdif = val;
1587 spin_unlock_irq(&hdsp->lock);
1591 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1593 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1598 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1600 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1602 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1606 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1608 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1612 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1613 spin_lock_irq(&hdsp->lock);
1614 change = val != hdsp->creg_spdif_stream;
1615 hdsp->creg_spdif_stream = val;
1616 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1617 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1618 spin_unlock_irq(&hdsp->lock);
1622 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1624 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1629 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1631 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1635 #define HDSP_SPDIF_IN(xname, xindex) \
1636 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1639 .info = snd_hdsp_info_spdif_in, \
1640 .get = snd_hdsp_get_spdif_in, \
1641 .put = snd_hdsp_put_spdif_in }
1643 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1645 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1648 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1650 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1651 hdsp->control_register |= hdsp_encode_spdif_in(in);
1652 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1656 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1658 static const char * const texts[4] = {
1659 "Optical", "Coaxial", "Internal", "AES"
1661 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1663 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1667 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1669 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1671 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1675 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1677 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1681 if (!snd_hdsp_use_is_exclusive(hdsp))
1683 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1684 spin_lock_irq(&hdsp->lock);
1685 change = val != hdsp_spdif_in(hdsp);
1687 hdsp_set_spdif_input(hdsp, val);
1688 spin_unlock_irq(&hdsp->lock);
1692 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1693 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1695 .private_value = xindex, \
1696 .info = snd_hdsp_info_toggle_setting, \
1697 .get = snd_hdsp_get_toggle_setting, \
1698 .put = snd_hdsp_put_toggle_setting \
1701 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1703 return (hdsp->control_register & regmask) ? 1 : 0;
1706 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1709 hdsp->control_register |= regmask;
1711 hdsp->control_register &= ~regmask;
1712 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1717 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1719 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1720 struct snd_ctl_elem_value *ucontrol)
1722 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1723 u32 regmask = kcontrol->private_value;
1725 spin_lock_irq(&hdsp->lock);
1726 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1727 spin_unlock_irq(&hdsp->lock);
1731 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1732 struct snd_ctl_elem_value *ucontrol)
1734 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1735 u32 regmask = kcontrol->private_value;
1739 if (!snd_hdsp_use_is_exclusive(hdsp))
1741 val = ucontrol->value.integer.value[0] & 1;
1742 spin_lock_irq(&hdsp->lock);
1743 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1745 hdsp_set_toggle_setting(hdsp, regmask, val);
1746 spin_unlock_irq(&hdsp->lock);
1750 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1751 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1754 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1755 .info = snd_hdsp_info_spdif_sample_rate, \
1756 .get = snd_hdsp_get_spdif_sample_rate \
1759 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1761 static const char * const texts[] = {
1762 "32000", "44100", "48000", "64000", "88200", "96000",
1763 "None", "128000", "176400", "192000"
1765 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1767 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1771 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1773 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1775 switch (hdsp_spdif_sample_rate(hdsp)) {
1777 ucontrol->value.enumerated.item[0] = 0;
1780 ucontrol->value.enumerated.item[0] = 1;
1783 ucontrol->value.enumerated.item[0] = 2;
1786 ucontrol->value.enumerated.item[0] = 3;
1789 ucontrol->value.enumerated.item[0] = 4;
1792 ucontrol->value.enumerated.item[0] = 5;
1795 ucontrol->value.enumerated.item[0] = 7;
1798 ucontrol->value.enumerated.item[0] = 8;
1801 ucontrol->value.enumerated.item[0] = 9;
1804 ucontrol->value.enumerated.item[0] = 6;
1809 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1813 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1814 .info = snd_hdsp_info_system_sample_rate, \
1815 .get = snd_hdsp_get_system_sample_rate \
1818 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1820 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1825 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1827 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1829 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1833 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1834 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1837 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1838 .info = snd_hdsp_info_autosync_sample_rate, \
1839 .get = snd_hdsp_get_autosync_sample_rate \
1842 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1844 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1845 static const char * const texts[] = {
1846 "32000", "44100", "48000", "64000", "88200", "96000",
1847 "None", "128000", "176400", "192000"
1850 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1854 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1856 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1858 switch (hdsp_external_sample_rate(hdsp)) {
1860 ucontrol->value.enumerated.item[0] = 0;
1863 ucontrol->value.enumerated.item[0] = 1;
1866 ucontrol->value.enumerated.item[0] = 2;
1869 ucontrol->value.enumerated.item[0] = 3;
1872 ucontrol->value.enumerated.item[0] = 4;
1875 ucontrol->value.enumerated.item[0] = 5;
1878 ucontrol->value.enumerated.item[0] = 7;
1881 ucontrol->value.enumerated.item[0] = 8;
1884 ucontrol->value.enumerated.item[0] = 9;
1887 ucontrol->value.enumerated.item[0] = 6;
1892 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1893 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1896 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1897 .info = snd_hdsp_info_system_clock_mode, \
1898 .get = snd_hdsp_get_system_clock_mode \
1901 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1903 if (hdsp->control_register & HDSP_ClockModeMaster)
1905 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1910 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1912 static const char * const texts[] = {"Master", "Slave" };
1914 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1917 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1919 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1921 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1925 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1926 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1929 .info = snd_hdsp_info_clock_source, \
1930 .get = snd_hdsp_get_clock_source, \
1931 .put = snd_hdsp_put_clock_source \
1934 static int hdsp_clock_source(struct hdsp *hdsp)
1936 if (hdsp->control_register & HDSP_ClockModeMaster) {
1937 switch (hdsp->system_sample_rate) {
1964 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1968 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1969 if (hdsp_external_sample_rate(hdsp) != 0) {
1970 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1971 hdsp->control_register &= ~HDSP_ClockModeMaster;
1972 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1977 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1980 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1983 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1986 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1989 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1992 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1995 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1998 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2001 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2007 hdsp->control_register |= HDSP_ClockModeMaster;
2008 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2009 hdsp_set_rate(hdsp, rate, 1);
2013 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2015 static const char * const texts[] = {
2016 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2017 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2018 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2019 "Internal 192.0 KHz"
2021 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2023 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2027 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2029 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2031 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2035 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2037 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2041 if (!snd_hdsp_use_is_exclusive(hdsp))
2043 val = ucontrol->value.enumerated.item[0];
2044 if (val < 0) val = 0;
2045 if (hdsp->io_type == H9632) {
2052 spin_lock_irq(&hdsp->lock);
2053 if (val != hdsp_clock_source(hdsp))
2054 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2057 spin_unlock_irq(&hdsp->lock);
2061 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2063 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2065 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2067 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2071 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2073 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2076 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2078 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2082 #define HDSP_DA_GAIN(xname, xindex) \
2083 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2086 .info = snd_hdsp_info_da_gain, \
2087 .get = snd_hdsp_get_da_gain, \
2088 .put = snd_hdsp_put_da_gain \
2091 static int hdsp_da_gain(struct hdsp *hdsp)
2093 switch (hdsp->control_register & HDSP_DAGainMask) {
2094 case HDSP_DAGainHighGain:
2096 case HDSP_DAGainPlus4dBu:
2098 case HDSP_DAGainMinus10dBV:
2105 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2107 hdsp->control_register &= ~HDSP_DAGainMask;
2110 hdsp->control_register |= HDSP_DAGainHighGain;
2113 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2116 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2122 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2126 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2128 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2130 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2133 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2135 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2137 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2141 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2143 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2147 if (!snd_hdsp_use_is_exclusive(hdsp))
2149 val = ucontrol->value.enumerated.item[0];
2150 if (val < 0) val = 0;
2151 if (val > 2) val = 2;
2152 spin_lock_irq(&hdsp->lock);
2153 if (val != hdsp_da_gain(hdsp))
2154 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2157 spin_unlock_irq(&hdsp->lock);
2161 #define HDSP_AD_GAIN(xname, xindex) \
2162 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2165 .info = snd_hdsp_info_ad_gain, \
2166 .get = snd_hdsp_get_ad_gain, \
2167 .put = snd_hdsp_put_ad_gain \
2170 static int hdsp_ad_gain(struct hdsp *hdsp)
2172 switch (hdsp->control_register & HDSP_ADGainMask) {
2173 case HDSP_ADGainMinus10dBV:
2175 case HDSP_ADGainPlus4dBu:
2177 case HDSP_ADGainLowGain:
2184 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2186 hdsp->control_register &= ~HDSP_ADGainMask;
2189 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2192 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2195 hdsp->control_register |= HDSP_ADGainLowGain;
2201 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2205 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2207 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2209 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2212 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2214 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2216 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2220 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2222 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2226 if (!snd_hdsp_use_is_exclusive(hdsp))
2228 val = ucontrol->value.enumerated.item[0];
2229 if (val < 0) val = 0;
2230 if (val > 2) val = 2;
2231 spin_lock_irq(&hdsp->lock);
2232 if (val != hdsp_ad_gain(hdsp))
2233 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2236 spin_unlock_irq(&hdsp->lock);
2240 #define HDSP_PHONE_GAIN(xname, xindex) \
2241 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2244 .info = snd_hdsp_info_phone_gain, \
2245 .get = snd_hdsp_get_phone_gain, \
2246 .put = snd_hdsp_put_phone_gain \
2249 static int hdsp_phone_gain(struct hdsp *hdsp)
2251 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2252 case HDSP_PhoneGain0dB:
2254 case HDSP_PhoneGainMinus6dB:
2256 case HDSP_PhoneGainMinus12dB:
2263 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2265 hdsp->control_register &= ~HDSP_PhoneGainMask;
2268 hdsp->control_register |= HDSP_PhoneGain0dB;
2271 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2274 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2280 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2284 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2286 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2288 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2291 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2293 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2295 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2299 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2301 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2305 if (!snd_hdsp_use_is_exclusive(hdsp))
2307 val = ucontrol->value.enumerated.item[0];
2308 if (val < 0) val = 0;
2309 if (val > 2) val = 2;
2310 spin_lock_irq(&hdsp->lock);
2311 if (val != hdsp_phone_gain(hdsp))
2312 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2315 spin_unlock_irq(&hdsp->lock);
2319 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2320 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2323 .info = snd_hdsp_info_pref_sync_ref, \
2324 .get = snd_hdsp_get_pref_sync_ref, \
2325 .put = snd_hdsp_put_pref_sync_ref \
2328 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2330 /* Notice that this looks at the requested sync source,
2331 not the one actually in use.
2334 switch (hdsp->control_register & HDSP_SyncRefMask) {
2335 case HDSP_SyncRef_ADAT1:
2336 return HDSP_SYNC_FROM_ADAT1;
2337 case HDSP_SyncRef_ADAT2:
2338 return HDSP_SYNC_FROM_ADAT2;
2339 case HDSP_SyncRef_ADAT3:
2340 return HDSP_SYNC_FROM_ADAT3;
2341 case HDSP_SyncRef_SPDIF:
2342 return HDSP_SYNC_FROM_SPDIF;
2343 case HDSP_SyncRef_WORD:
2344 return HDSP_SYNC_FROM_WORD;
2345 case HDSP_SyncRef_ADAT_SYNC:
2346 return HDSP_SYNC_FROM_ADAT_SYNC;
2348 return HDSP_SYNC_FROM_WORD;
2353 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2355 hdsp->control_register &= ~HDSP_SyncRefMask;
2357 case HDSP_SYNC_FROM_ADAT1:
2358 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2360 case HDSP_SYNC_FROM_ADAT2:
2361 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2363 case HDSP_SYNC_FROM_ADAT3:
2364 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2366 case HDSP_SYNC_FROM_SPDIF:
2367 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2369 case HDSP_SYNC_FROM_WORD:
2370 hdsp->control_register |= HDSP_SyncRef_WORD;
2372 case HDSP_SYNC_FROM_ADAT_SYNC:
2373 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2378 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2382 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2384 static const char * const texts[] = {
2385 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2387 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2390 switch (hdsp->io_type) {
2405 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2408 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2410 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2412 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2416 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2418 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2422 if (!snd_hdsp_use_is_exclusive(hdsp))
2425 switch (hdsp->io_type) {
2440 val = ucontrol->value.enumerated.item[0] % max;
2441 spin_lock_irq(&hdsp->lock);
2442 change = (int)val != hdsp_pref_sync_ref(hdsp);
2443 hdsp_set_pref_sync_ref(hdsp, val);
2444 spin_unlock_irq(&hdsp->lock);
2448 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2449 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2452 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2453 .info = snd_hdsp_info_autosync_ref, \
2454 .get = snd_hdsp_get_autosync_ref, \
2457 static int hdsp_autosync_ref(struct hdsp *hdsp)
2459 /* This looks at the autosync selected sync reference */
2460 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2462 switch (status2 & HDSP_SelSyncRefMask) {
2463 case HDSP_SelSyncRef_WORD:
2464 return HDSP_AUTOSYNC_FROM_WORD;
2465 case HDSP_SelSyncRef_ADAT_SYNC:
2466 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2467 case HDSP_SelSyncRef_SPDIF:
2468 return HDSP_AUTOSYNC_FROM_SPDIF;
2469 case HDSP_SelSyncRefMask:
2470 return HDSP_AUTOSYNC_FROM_NONE;
2471 case HDSP_SelSyncRef_ADAT1:
2472 return HDSP_AUTOSYNC_FROM_ADAT1;
2473 case HDSP_SelSyncRef_ADAT2:
2474 return HDSP_AUTOSYNC_FROM_ADAT2;
2475 case HDSP_SelSyncRef_ADAT3:
2476 return HDSP_AUTOSYNC_FROM_ADAT3;
2478 return HDSP_AUTOSYNC_FROM_WORD;
2483 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2485 static const char * const texts[] = {
2486 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2489 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2492 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2494 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2496 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2500 #define HDSP_PRECISE_POINTER(xname, xindex) \
2501 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2504 .info = snd_hdsp_info_precise_pointer, \
2505 .get = snd_hdsp_get_precise_pointer, \
2506 .put = snd_hdsp_put_precise_pointer \
2509 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2512 hdsp->precise_ptr = 1;
2514 hdsp->precise_ptr = 0;
2518 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2520 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2522 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2524 spin_lock_irq(&hdsp->lock);
2525 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2526 spin_unlock_irq(&hdsp->lock);
2530 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2532 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2536 if (!snd_hdsp_use_is_exclusive(hdsp))
2538 val = ucontrol->value.integer.value[0] & 1;
2539 spin_lock_irq(&hdsp->lock);
2540 change = (int)val != hdsp->precise_ptr;
2541 hdsp_set_precise_pointer(hdsp, val);
2542 spin_unlock_irq(&hdsp->lock);
2546 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2547 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2550 .info = snd_hdsp_info_use_midi_tasklet, \
2551 .get = snd_hdsp_get_use_midi_tasklet, \
2552 .put = snd_hdsp_put_use_midi_tasklet \
2555 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2558 hdsp->use_midi_tasklet = 1;
2560 hdsp->use_midi_tasklet = 0;
2564 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2566 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2568 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2570 spin_lock_irq(&hdsp->lock);
2571 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2572 spin_unlock_irq(&hdsp->lock);
2576 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2578 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2582 if (!snd_hdsp_use_is_exclusive(hdsp))
2584 val = ucontrol->value.integer.value[0] & 1;
2585 spin_lock_irq(&hdsp->lock);
2586 change = (int)val != hdsp->use_midi_tasklet;
2587 hdsp_set_use_midi_tasklet(hdsp, val);
2588 spin_unlock_irq(&hdsp->lock);
2592 #define HDSP_MIXER(xname, xindex) \
2593 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2597 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2598 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2599 .info = snd_hdsp_info_mixer, \
2600 .get = snd_hdsp_get_mixer, \
2601 .put = snd_hdsp_put_mixer \
2604 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2606 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2608 uinfo->value.integer.min = 0;
2609 uinfo->value.integer.max = 65536;
2610 uinfo->value.integer.step = 1;
2614 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2616 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2621 source = ucontrol->value.integer.value[0];
2622 destination = ucontrol->value.integer.value[1];
2624 if (source >= hdsp->max_channels)
2625 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2627 addr = hdsp_input_to_output_key(hdsp,source, destination);
2629 spin_lock_irq(&hdsp->lock);
2630 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2631 spin_unlock_irq(&hdsp->lock);
2635 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2637 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2644 if (!snd_hdsp_use_is_exclusive(hdsp))
2647 source = ucontrol->value.integer.value[0];
2648 destination = ucontrol->value.integer.value[1];
2650 if (source >= hdsp->max_channels)
2651 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2653 addr = hdsp_input_to_output_key(hdsp,source, destination);
2655 gain = ucontrol->value.integer.value[2];
2657 spin_lock_irq(&hdsp->lock);
2658 change = gain != hdsp_read_gain(hdsp, addr);
2660 hdsp_write_gain(hdsp, addr, gain);
2661 spin_unlock_irq(&hdsp->lock);
2665 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2666 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2669 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2670 .info = snd_hdsp_info_sync_check, \
2671 .get = snd_hdsp_get_wc_sync_check \
2674 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2676 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2678 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2681 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2683 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2684 if (status2 & HDSP_wc_lock) {
2685 if (status2 & HDSP_wc_sync)
2694 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2696 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2698 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2702 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2703 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2706 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2707 .info = snd_hdsp_info_sync_check, \
2708 .get = snd_hdsp_get_spdif_sync_check \
2711 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2713 int status = hdsp_read(hdsp, HDSP_statusRegister);
2714 if (status & HDSP_SPDIFErrorFlag)
2717 if (status & HDSP_SPDIFSync)
2725 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2727 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2729 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2733 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2734 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2737 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2738 .info = snd_hdsp_info_sync_check, \
2739 .get = snd_hdsp_get_adatsync_sync_check \
2742 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2744 int status = hdsp_read(hdsp, HDSP_statusRegister);
2745 if (status & HDSP_TimecodeLock) {
2746 if (status & HDSP_TimecodeSync)
2754 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2756 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2758 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2762 #define HDSP_ADAT_SYNC_CHECK \
2763 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2764 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2765 .info = snd_hdsp_info_sync_check, \
2766 .get = snd_hdsp_get_adat_sync_check \
2769 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2771 int status = hdsp_read(hdsp, HDSP_statusRegister);
2773 if (status & (HDSP_Lock0>>idx)) {
2774 if (status & (HDSP_Sync0>>idx))
2782 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2785 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2787 offset = ucontrol->id.index - 1;
2788 if (snd_BUG_ON(offset < 0))
2791 switch (hdsp->io_type) {
2806 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2810 #define HDSP_DDS_OFFSET(xname, xindex) \
2811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2814 .info = snd_hdsp_info_dds_offset, \
2815 .get = snd_hdsp_get_dds_offset, \
2816 .put = snd_hdsp_put_dds_offset \
2819 static int hdsp_dds_offset(struct hdsp *hdsp)
2822 unsigned int dds_value = hdsp->dds_value;
2823 int system_sample_rate = hdsp->system_sample_rate;
2830 * dds_value = n / rate
2831 * rate = n / dds_value
2833 n = div_u64(n, dds_value);
2834 if (system_sample_rate >= 112000)
2836 else if (system_sample_rate >= 56000)
2838 return ((int)n) - system_sample_rate;
2841 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2843 int rate = hdsp->system_sample_rate + offset_hz;
2844 hdsp_set_dds_value(hdsp, rate);
2848 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2850 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2852 uinfo->value.integer.min = -5000;
2853 uinfo->value.integer.max = 5000;
2857 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2859 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2861 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2865 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2867 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2871 if (!snd_hdsp_use_is_exclusive(hdsp))
2873 val = ucontrol->value.integer.value[0];
2874 spin_lock_irq(&hdsp->lock);
2875 if (val != hdsp_dds_offset(hdsp))
2876 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2879 spin_unlock_irq(&hdsp->lock);
2883 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2884 HDSP_DA_GAIN("DA Gain", 0),
2885 HDSP_AD_GAIN("AD Gain", 0),
2886 HDSP_PHONE_GAIN("Phones Gain", 0),
2887 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2888 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2891 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2893 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2894 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2895 .info = snd_hdsp_control_spdif_info,
2896 .get = snd_hdsp_control_spdif_get,
2897 .put = snd_hdsp_control_spdif_put,
2900 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2901 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2902 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2903 .info = snd_hdsp_control_spdif_stream_info,
2904 .get = snd_hdsp_control_spdif_stream_get,
2905 .put = snd_hdsp_control_spdif_stream_put,
2908 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2909 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2910 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2911 .info = snd_hdsp_control_spdif_mask_info,
2912 .get = snd_hdsp_control_spdif_mask_get,
2913 .private_value = IEC958_AES0_NONAUDIO |
2914 IEC958_AES0_PROFESSIONAL |
2915 IEC958_AES0_CON_EMPHASIS,
2918 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2919 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2920 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2921 .info = snd_hdsp_control_spdif_mask_info,
2922 .get = snd_hdsp_control_spdif_mask_get,
2923 .private_value = IEC958_AES0_NONAUDIO |
2924 IEC958_AES0_PROFESSIONAL |
2925 IEC958_AES0_PRO_EMPHASIS,
2927 HDSP_MIXER("Mixer", 0),
2928 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2929 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2930 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2931 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2932 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2933 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2934 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2936 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2937 .name = "Sample Clock Source Locking",
2938 .info = snd_hdsp_info_clock_source_lock,
2939 .get = snd_hdsp_get_clock_source_lock,
2940 .put = snd_hdsp_put_clock_source_lock,
2942 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2943 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2944 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2945 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2946 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2947 /* 'External Rate' complies with the alsa control naming scheme */
2948 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2949 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2950 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2951 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2952 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2953 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2954 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2958 static int hdsp_rpm_input12(struct hdsp *hdsp)
2960 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2961 case HDSP_RPM_Inp12_Phon_6dB:
2963 case HDSP_RPM_Inp12_Phon_n6dB:
2965 case HDSP_RPM_Inp12_Line_0dB:
2967 case HDSP_RPM_Inp12_Line_n6dB:
2974 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2976 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2978 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2983 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2985 hdsp->control_register &= ~HDSP_RPM_Inp12;
2988 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2993 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2996 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2999 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3005 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3010 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3012 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3016 if (!snd_hdsp_use_is_exclusive(hdsp))
3018 val = ucontrol->value.enumerated.item[0];
3023 spin_lock_irq(&hdsp->lock);
3024 if (val != hdsp_rpm_input12(hdsp))
3025 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3028 spin_unlock_irq(&hdsp->lock);
3033 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3035 static const char * const texts[] = {
3036 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3039 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3043 static int hdsp_rpm_input34(struct hdsp *hdsp)
3045 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3046 case HDSP_RPM_Inp34_Phon_6dB:
3048 case HDSP_RPM_Inp34_Phon_n6dB:
3050 case HDSP_RPM_Inp34_Line_0dB:
3052 case HDSP_RPM_Inp34_Line_n6dB:
3059 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3061 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3063 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3068 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3070 hdsp->control_register &= ~HDSP_RPM_Inp34;
3073 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3078 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3081 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3084 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3090 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3095 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3097 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3101 if (!snd_hdsp_use_is_exclusive(hdsp))
3103 val = ucontrol->value.enumerated.item[0];
3108 spin_lock_irq(&hdsp->lock);
3109 if (val != hdsp_rpm_input34(hdsp))
3110 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3113 spin_unlock_irq(&hdsp->lock);
3118 /* RPM Bypass switch */
3119 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3121 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3125 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3127 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3129 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3134 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3137 hdsp->control_register |= HDSP_RPM_Bypass;
3139 hdsp->control_register &= ~HDSP_RPM_Bypass;
3140 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3145 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3147 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3151 if (!snd_hdsp_use_is_exclusive(hdsp))
3153 val = ucontrol->value.integer.value[0] & 1;
3154 spin_lock_irq(&hdsp->lock);
3155 change = (int)val != hdsp_rpm_bypass(hdsp);
3156 hdsp_set_rpm_bypass(hdsp, val);
3157 spin_unlock_irq(&hdsp->lock);
3162 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3164 static const char * const texts[] = {"On", "Off"};
3166 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3170 /* RPM Disconnect switch */
3171 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3173 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3177 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3179 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3181 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3186 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3189 hdsp->control_register |= HDSP_RPM_Disconnect;
3191 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3192 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3197 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3199 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3203 if (!snd_hdsp_use_is_exclusive(hdsp))
3205 val = ucontrol->value.integer.value[0] & 1;
3206 spin_lock_irq(&hdsp->lock);
3207 change = (int)val != hdsp_rpm_disconnect(hdsp);
3208 hdsp_set_rpm_disconnect(hdsp, val);
3209 spin_unlock_irq(&hdsp->lock);
3213 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3215 static const char * const texts[] = {"On", "Off"};
3217 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3220 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3222 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3223 .name = "RPM Bypass",
3224 .get = snd_hdsp_get_rpm_bypass,
3225 .put = snd_hdsp_put_rpm_bypass,
3226 .info = snd_hdsp_info_rpm_bypass
3229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3230 .name = "RPM Disconnect",
3231 .get = snd_hdsp_get_rpm_disconnect,
3232 .put = snd_hdsp_put_rpm_disconnect,
3233 .info = snd_hdsp_info_rpm_disconnect
3236 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3237 .name = "Input 1/2",
3238 .get = snd_hdsp_get_rpm_input12,
3239 .put = snd_hdsp_put_rpm_input12,
3240 .info = snd_hdsp_info_rpm_input
3243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3244 .name = "Input 3/4",
3245 .get = snd_hdsp_get_rpm_input34,
3246 .put = snd_hdsp_put_rpm_input34,
3247 .info = snd_hdsp_info_rpm_input
3249 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3250 HDSP_MIXER("Mixer", 0)
3253 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3254 HDSP_TOGGLE_SETTING("Analog Extension Board",
3255 HDSP_AnalogExtensionBoard);
3256 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3258 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3262 struct snd_kcontrol *kctl;
3264 if (hdsp->io_type == RPM) {
3265 /* RPM Bypass, Disconnect and Input switches */
3266 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3267 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3274 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3275 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3277 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3278 hdsp->spdif_ctl = kctl;
3281 /* ADAT SyncCheck status */
3282 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3283 snd_hdsp_adat_sync_check.index = 1;
3284 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3286 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3287 for (idx = 1; idx < 3; ++idx) {
3288 snd_hdsp_adat_sync_check.index = idx+1;
3289 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3294 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3295 if (hdsp->io_type == H9632) {
3296 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3297 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3302 /* AEB control for H96xx card */
3303 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3304 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3311 /*------------------------------------------------------------
3313 ------------------------------------------------------------*/
3316 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3318 struct hdsp *hdsp = entry->private_data;
3319 unsigned int status;
3320 unsigned int status2;
3321 char *pref_sync_ref;
3323 char *system_clock_mode;
3327 status = hdsp_read(hdsp, HDSP_statusRegister);
3328 status2 = hdsp_read(hdsp, HDSP_status2Register);
3330 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3331 hdsp->card->number + 1);
3332 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3333 hdsp->capture_buffer, hdsp->playback_buffer);
3334 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3335 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3336 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3337 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3338 hdsp->control2_register);
3339 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3340 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3342 if (hdsp_check_for_iobox(hdsp)) {
3343 snd_iprintf(buffer, "No I/O box connected.\n"
3344 "Please connect one and upload firmware.\n");
3348 if (hdsp_check_for_firmware(hdsp, 0)) {
3349 if (hdsp->state & HDSP_FirmwareCached) {
3350 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3351 snd_iprintf(buffer, "Firmware loading from "
3353 "please upload manually.\n");
3358 err = hdsp_request_fw_loader(hdsp);
3361 "No firmware loaded nor cached, "
3362 "please upload firmware.\n");
3368 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3369 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3370 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3371 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3372 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3373 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3375 snd_iprintf(buffer, "\n");
3377 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3379 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3380 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3381 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3382 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3384 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3386 snd_iprintf(buffer, "\n");
3388 switch (hdsp_clock_source(hdsp)) {
3389 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3390 clock_source = "AutoSync";
3392 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3393 clock_source = "Internal 32 kHz";
3395 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3396 clock_source = "Internal 44.1 kHz";
3398 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3399 clock_source = "Internal 48 kHz";
3401 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3402 clock_source = "Internal 64 kHz";
3404 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3405 clock_source = "Internal 88.2 kHz";
3407 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3408 clock_source = "Internal 96 kHz";
3410 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3411 clock_source = "Internal 128 kHz";
3413 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3414 clock_source = "Internal 176.4 kHz";
3416 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3417 clock_source = "Internal 192 kHz";
3420 clock_source = "Error";
3422 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3424 if (hdsp_system_clock_mode(hdsp))
3425 system_clock_mode = "Slave";
3427 system_clock_mode = "Master";
3429 switch (hdsp_pref_sync_ref (hdsp)) {
3430 case HDSP_SYNC_FROM_WORD:
3431 pref_sync_ref = "Word Clock";
3433 case HDSP_SYNC_FROM_ADAT_SYNC:
3434 pref_sync_ref = "ADAT Sync";
3436 case HDSP_SYNC_FROM_SPDIF:
3437 pref_sync_ref = "SPDIF";
3439 case HDSP_SYNC_FROM_ADAT1:
3440 pref_sync_ref = "ADAT1";
3442 case HDSP_SYNC_FROM_ADAT2:
3443 pref_sync_ref = "ADAT2";
3445 case HDSP_SYNC_FROM_ADAT3:
3446 pref_sync_ref = "ADAT3";
3449 pref_sync_ref = "Word Clock";
3452 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3454 switch (hdsp_autosync_ref (hdsp)) {
3455 case HDSP_AUTOSYNC_FROM_WORD:
3456 autosync_ref = "Word Clock";
3458 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3459 autosync_ref = "ADAT Sync";
3461 case HDSP_AUTOSYNC_FROM_SPDIF:
3462 autosync_ref = "SPDIF";
3464 case HDSP_AUTOSYNC_FROM_NONE:
3465 autosync_ref = "None";
3467 case HDSP_AUTOSYNC_FROM_ADAT1:
3468 autosync_ref = "ADAT1";
3470 case HDSP_AUTOSYNC_FROM_ADAT2:
3471 autosync_ref = "ADAT2";
3473 case HDSP_AUTOSYNC_FROM_ADAT3:
3474 autosync_ref = "ADAT3";
3477 autosync_ref = "---";
3480 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3482 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3484 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3486 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3487 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3489 snd_iprintf(buffer, "\n");
3491 if (hdsp->io_type != RPM) {
3492 switch (hdsp_spdif_in(hdsp)) {
3493 case HDSP_SPDIFIN_OPTICAL:
3494 snd_iprintf(buffer, "IEC958 input: Optical\n");
3496 case HDSP_SPDIFIN_COAXIAL:
3497 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3499 case HDSP_SPDIFIN_INTERNAL:
3500 snd_iprintf(buffer, "IEC958 input: Internal\n");
3502 case HDSP_SPDIFIN_AES:
3503 snd_iprintf(buffer, "IEC958 input: AES\n");
3506 snd_iprintf(buffer, "IEC958 input: ???\n");
3511 if (RPM == hdsp->io_type) {
3512 if (hdsp->control_register & HDSP_RPM_Bypass)
3513 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3515 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3516 if (hdsp->control_register & HDSP_RPM_Disconnect)
3517 snd_iprintf(buffer, "RPM disconnected\n");
3519 snd_iprintf(buffer, "RPM connected\n");
3521 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3522 case HDSP_RPM_Inp12_Phon_6dB:
3523 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3525 case HDSP_RPM_Inp12_Phon_0dB:
3526 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3528 case HDSP_RPM_Inp12_Phon_n6dB:
3529 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3531 case HDSP_RPM_Inp12_Line_0dB:
3532 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3534 case HDSP_RPM_Inp12_Line_n6dB:
3535 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3538 snd_iprintf(buffer, "Input 1/2: ???\n");
3541 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3542 case HDSP_RPM_Inp34_Phon_6dB:
3543 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3545 case HDSP_RPM_Inp34_Phon_0dB:
3546 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3548 case HDSP_RPM_Inp34_Phon_n6dB:
3549 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3551 case HDSP_RPM_Inp34_Line_0dB:
3552 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3554 case HDSP_RPM_Inp34_Line_n6dB:
3555 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3558 snd_iprintf(buffer, "Input 3/4: ???\n");
3562 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3563 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3565 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3567 if (hdsp->control_register & HDSP_SPDIFProfessional)
3568 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3570 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3572 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3573 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3575 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3577 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3578 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3580 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3581 x = hdsp_spdif_sample_rate(hdsp);
3583 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3585 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3587 snd_iprintf(buffer, "\n");
3590 x = status & HDSP_Sync0;
3591 if (status & HDSP_Lock0)
3592 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3594 snd_iprintf(buffer, "ADAT1: No Lock\n");
3596 switch (hdsp->io_type) {
3599 x = status & HDSP_Sync1;
3600 if (status & HDSP_Lock1)
3601 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3603 snd_iprintf(buffer, "ADAT2: No Lock\n");
3604 x = status & HDSP_Sync2;
3605 if (status & HDSP_Lock2)
3606 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3608 snd_iprintf(buffer, "ADAT3: No Lock\n");
3615 x = status & HDSP_SPDIFSync;
3616 if (status & HDSP_SPDIFErrorFlag)
3617 snd_iprintf (buffer, "SPDIF: No Lock\n");
3619 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3621 x = status2 & HDSP_wc_sync;
3622 if (status2 & HDSP_wc_lock)
3623 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3625 snd_iprintf (buffer, "Word Clock: No Lock\n");
3627 x = status & HDSP_TimecodeSync;
3628 if (status & HDSP_TimecodeLock)
3629 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3631 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3633 snd_iprintf(buffer, "\n");
3635 /* Informations about H9632 specific controls */
3636 if (hdsp->io_type == H9632) {
3639 switch (hdsp_ad_gain(hdsp)) {
3650 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3652 switch (hdsp_da_gain(hdsp)) {
3663 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3665 switch (hdsp_phone_gain(hdsp)) {
3676 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3678 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3679 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3682 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3683 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3685 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3686 snd_iprintf(buffer, "\n");
3691 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3693 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3696 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3698 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3699 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3702 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3704 unsigned long pb_bus, cb_bus;
3706 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3707 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3708 if (hdsp->capture_dma_buf.area)
3709 snd_dma_free_pages(&hdsp->capture_dma_buf);
3710 dev_err(hdsp->card->dev,
3711 "%s: no buffers available\n", hdsp->card_name);
3715 /* Align to bus-space 64K boundary */
3717 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3718 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3720 /* Tell the card where it is */
3722 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3723 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3725 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3726 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3731 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3735 /* ASSUMPTION: hdsp->lock is either held, or
3736 there is no need to hold it (e.g. during module
3742 SPDIF Input via Coax
3744 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3745 which implies 2 4096 sample, 32Kbyte periods).
3749 hdsp->control_register = HDSP_ClockModeMaster |
3750 HDSP_SPDIFInputCoaxial |
3751 hdsp_encode_latency(7) |
3755 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3757 #ifdef SNDRV_BIG_ENDIAN
3758 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3760 hdsp->control2_register = 0;
3762 if (hdsp->io_type == H9652)
3763 snd_hdsp_9652_enable_mixer (hdsp);
3765 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3767 hdsp_reset_hw_pointer(hdsp);
3768 hdsp_compute_period_size(hdsp);
3770 /* silence everything */
3772 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3773 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3775 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3776 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3780 /* H9632 specific defaults */
3781 if (hdsp->io_type == H9632) {
3782 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3783 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3786 /* set a default rate so that the channel map is set up.
3789 hdsp_set_rate(hdsp, 48000, 1);
3794 static void hdsp_midi_tasklet(unsigned long arg)
3796 struct hdsp *hdsp = (struct hdsp *)arg;
3798 if (hdsp->midi[0].pending)
3799 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3800 if (hdsp->midi[1].pending)
3801 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3804 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3806 struct hdsp *hdsp = (struct hdsp *) dev_id;
3807 unsigned int status;
3811 unsigned int midi0status;
3812 unsigned int midi1status;
3815 status = hdsp_read(hdsp, HDSP_statusRegister);
3817 audio = status & HDSP_audioIRQPending;
3818 midi0 = status & HDSP_midi0IRQPending;
3819 midi1 = status & HDSP_midi1IRQPending;
3821 if (!audio && !midi0 && !midi1)
3824 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3826 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3827 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3829 if (!(hdsp->state & HDSP_InitializationComplete))
3833 if (hdsp->capture_substream)
3834 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3836 if (hdsp->playback_substream)
3837 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3840 if (midi0 && midi0status) {
3841 if (hdsp->use_midi_tasklet) {
3842 /* we disable interrupts for this input until processing is done */
3843 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3844 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3845 hdsp->midi[0].pending = 1;
3848 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3851 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3852 if (hdsp->use_midi_tasklet) {
3853 /* we disable interrupts for this input until processing is done */
3854 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3855 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3856 hdsp->midi[1].pending = 1;
3859 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3862 if (hdsp->use_midi_tasklet && schedule)
3863 tasklet_schedule(&hdsp->midi_tasklet);
3867 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3869 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3870 return hdsp_hw_pointer(hdsp);
3873 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3880 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3883 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3886 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3887 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3889 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3892 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3893 int channel, unsigned long pos,
3894 void __user *src, unsigned long count)
3896 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3899 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3902 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3903 if (snd_BUG_ON(!channel_buf))
3905 if (copy_from_user(channel_buf + pos, src, count))
3910 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3911 int channel, unsigned long pos,
3912 void *src, unsigned long count)
3914 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3917 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3918 if (snd_BUG_ON(!channel_buf))
3920 memcpy(channel_buf + pos, src, count);
3924 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3925 int channel, unsigned long pos,
3926 void __user *dst, unsigned long count)
3928 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3931 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3934 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3935 if (snd_BUG_ON(!channel_buf))
3937 if (copy_to_user(dst, channel_buf + pos, count))
3942 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3943 int channel, unsigned long pos,
3944 void *dst, unsigned long count)
3946 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3949 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3950 if (snd_BUG_ON(!channel_buf))
3952 memcpy(dst, channel_buf + pos, count);
3956 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3957 int channel, unsigned long pos,
3958 unsigned long count)
3960 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3963 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3964 if (snd_BUG_ON(!channel_buf))
3966 memset(channel_buf + pos, 0, count);
3970 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3972 struct snd_pcm_runtime *runtime = substream->runtime;
3973 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3974 struct snd_pcm_substream *other;
3975 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3976 other = hdsp->capture_substream;
3978 other = hdsp->playback_substream;
3980 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3982 runtime->status->hw_ptr = 0;
3984 struct snd_pcm_substream *s;
3985 struct snd_pcm_runtime *oruntime = other->runtime;
3986 snd_pcm_group_for_each_entry(s, substream) {
3988 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3996 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3997 struct snd_pcm_hw_params *params)
3999 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4004 if (hdsp_check_for_iobox (hdsp))
4007 if (hdsp_check_for_firmware(hdsp, 1))
4010 spin_lock_irq(&hdsp->lock);
4012 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4013 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4014 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4015 this_pid = hdsp->playback_pid;
4016 other_pid = hdsp->capture_pid;
4018 this_pid = hdsp->capture_pid;
4019 other_pid = hdsp->playback_pid;
4022 if ((other_pid > 0) && (this_pid != other_pid)) {
4024 /* The other stream is open, and not by the same
4025 task as this one. Make sure that the parameters
4026 that matter are the same.
4029 if (params_rate(params) != hdsp->system_sample_rate) {
4030 spin_unlock_irq(&hdsp->lock);
4031 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4035 if (params_period_size(params) != hdsp->period_bytes / 4) {
4036 spin_unlock_irq(&hdsp->lock);
4037 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4043 spin_unlock_irq(&hdsp->lock);
4047 spin_unlock_irq(&hdsp->lock);
4050 /* how to make sure that the rate matches an externally-set one ?
4053 spin_lock_irq(&hdsp->lock);
4054 if (! hdsp->clock_source_locked) {
4055 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4056 spin_unlock_irq(&hdsp->lock);
4057 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4061 spin_unlock_irq(&hdsp->lock);
4063 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4064 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4071 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4072 struct snd_pcm_channel_info *info)
4074 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4075 unsigned int channel = info->channel;
4077 if (snd_BUG_ON(channel >= hdsp->max_channels))
4079 channel = array_index_nospec(channel, hdsp->max_channels);
4081 if (hdsp->channel_map[channel] < 0)
4084 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4090 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4091 unsigned int cmd, void *arg)
4094 case SNDRV_PCM_IOCTL1_RESET:
4095 return snd_hdsp_reset(substream);
4096 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4097 return snd_hdsp_channel_info(substream, arg);
4102 return snd_pcm_lib_ioctl(substream, cmd, arg);
4105 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4107 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4108 struct snd_pcm_substream *other;
4111 if (hdsp_check_for_iobox (hdsp))
4114 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4117 spin_lock(&hdsp->lock);
4118 running = hdsp->running;
4120 case SNDRV_PCM_TRIGGER_START:
4121 running |= 1 << substream->stream;
4123 case SNDRV_PCM_TRIGGER_STOP:
4124 running &= ~(1 << substream->stream);
4128 spin_unlock(&hdsp->lock);
4131 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4132 other = hdsp->capture_substream;
4134 other = hdsp->playback_substream;
4137 struct snd_pcm_substream *s;
4138 snd_pcm_group_for_each_entry(s, substream) {
4140 snd_pcm_trigger_done(s, substream);
4141 if (cmd == SNDRV_PCM_TRIGGER_START)
4142 running |= 1 << s->stream;
4144 running &= ~(1 << s->stream);
4148 if (cmd == SNDRV_PCM_TRIGGER_START) {
4149 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4150 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4151 hdsp_silence_playback(hdsp);
4154 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4155 hdsp_silence_playback(hdsp);
4158 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4159 hdsp_silence_playback(hdsp);
4162 snd_pcm_trigger_done(substream, substream);
4163 if (!hdsp->running && running)
4164 hdsp_start_audio(hdsp);
4165 else if (hdsp->running && !running)
4166 hdsp_stop_audio(hdsp);
4167 hdsp->running = running;
4168 spin_unlock(&hdsp->lock);
4173 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4175 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4178 if (hdsp_check_for_iobox (hdsp))
4181 if (hdsp_check_for_firmware(hdsp, 1))
4184 spin_lock_irq(&hdsp->lock);
4186 hdsp_reset_hw_pointer(hdsp);
4187 spin_unlock_irq(&hdsp->lock);
4191 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4193 .info = (SNDRV_PCM_INFO_MMAP |
4194 SNDRV_PCM_INFO_MMAP_VALID |
4195 SNDRV_PCM_INFO_NONINTERLEAVED |
4196 SNDRV_PCM_INFO_SYNC_START |
4197 SNDRV_PCM_INFO_DOUBLE),
4198 #ifdef SNDRV_BIG_ENDIAN
4199 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4201 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4203 .rates = (SNDRV_PCM_RATE_32000 |
4204 SNDRV_PCM_RATE_44100 |
4205 SNDRV_PCM_RATE_48000 |
4206 SNDRV_PCM_RATE_64000 |
4207 SNDRV_PCM_RATE_88200 |
4208 SNDRV_PCM_RATE_96000),
4212 .channels_max = HDSP_MAX_CHANNELS,
4213 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4214 .period_bytes_min = (64 * 4) * 10,
4215 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4221 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4223 .info = (SNDRV_PCM_INFO_MMAP |
4224 SNDRV_PCM_INFO_MMAP_VALID |
4225 SNDRV_PCM_INFO_NONINTERLEAVED |
4226 SNDRV_PCM_INFO_SYNC_START),
4227 #ifdef SNDRV_BIG_ENDIAN
4228 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4230 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4232 .rates = (SNDRV_PCM_RATE_32000 |
4233 SNDRV_PCM_RATE_44100 |
4234 SNDRV_PCM_RATE_48000 |
4235 SNDRV_PCM_RATE_64000 |
4236 SNDRV_PCM_RATE_88200 |
4237 SNDRV_PCM_RATE_96000),
4241 .channels_max = HDSP_MAX_CHANNELS,
4242 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4243 .period_bytes_min = (64 * 4) * 10,
4244 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4250 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4252 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4253 .count = ARRAY_SIZE(hdsp_period_sizes),
4254 .list = hdsp_period_sizes,
4258 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4260 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4261 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4262 .list = hdsp_9632_sample_rates,
4266 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4267 struct snd_pcm_hw_rule *rule)
4269 struct hdsp *hdsp = rule->private;
4270 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4271 if (hdsp->io_type == H9632) {
4272 unsigned int list[3];
4273 list[0] = hdsp->qs_in_channels;
4274 list[1] = hdsp->ds_in_channels;
4275 list[2] = hdsp->ss_in_channels;
4276 return snd_interval_list(c, 3, list, 0);
4278 unsigned int list[2];
4279 list[0] = hdsp->ds_in_channels;
4280 list[1] = hdsp->ss_in_channels;
4281 return snd_interval_list(c, 2, list, 0);
4285 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4286 struct snd_pcm_hw_rule *rule)
4288 unsigned int list[3];
4289 struct hdsp *hdsp = rule->private;
4290 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4291 if (hdsp->io_type == H9632) {
4292 list[0] = hdsp->qs_out_channels;
4293 list[1] = hdsp->ds_out_channels;
4294 list[2] = hdsp->ss_out_channels;
4295 return snd_interval_list(c, 3, list, 0);
4297 list[0] = hdsp->ds_out_channels;
4298 list[1] = hdsp->ss_out_channels;
4300 return snd_interval_list(c, 2, list, 0);
4303 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4304 struct snd_pcm_hw_rule *rule)
4306 struct hdsp *hdsp = rule->private;
4307 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4309 if (r->min > 96000 && hdsp->io_type == H9632) {
4310 struct snd_interval t = {
4311 .min = hdsp->qs_in_channels,
4312 .max = hdsp->qs_in_channels,
4315 return snd_interval_refine(c, &t);
4316 } else if (r->min > 48000 && r->max <= 96000) {
4317 struct snd_interval t = {
4318 .min = hdsp->ds_in_channels,
4319 .max = hdsp->ds_in_channels,
4322 return snd_interval_refine(c, &t);
4323 } else if (r->max < 64000) {
4324 struct snd_interval t = {
4325 .min = hdsp->ss_in_channels,
4326 .max = hdsp->ss_in_channels,
4329 return snd_interval_refine(c, &t);
4334 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4335 struct snd_pcm_hw_rule *rule)
4337 struct hdsp *hdsp = rule->private;
4338 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4340 if (r->min > 96000 && hdsp->io_type == H9632) {
4341 struct snd_interval t = {
4342 .min = hdsp->qs_out_channels,
4343 .max = hdsp->qs_out_channels,
4346 return snd_interval_refine(c, &t);
4347 } else if (r->min > 48000 && r->max <= 96000) {
4348 struct snd_interval t = {
4349 .min = hdsp->ds_out_channels,
4350 .max = hdsp->ds_out_channels,
4353 return snd_interval_refine(c, &t);
4354 } else if (r->max < 64000) {
4355 struct snd_interval t = {
4356 .min = hdsp->ss_out_channels,
4357 .max = hdsp->ss_out_channels,
4360 return snd_interval_refine(c, &t);
4365 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4366 struct snd_pcm_hw_rule *rule)
4368 struct hdsp *hdsp = rule->private;
4369 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4370 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4371 if (c->min >= hdsp->ss_out_channels) {
4372 struct snd_interval t = {
4377 return snd_interval_refine(r, &t);
4378 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4379 struct snd_interval t = {
4384 return snd_interval_refine(r, &t);
4385 } else if (c->max <= hdsp->ds_out_channels) {
4386 struct snd_interval t = {
4391 return snd_interval_refine(r, &t);
4396 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4397 struct snd_pcm_hw_rule *rule)
4399 struct hdsp *hdsp = rule->private;
4400 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4401 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4402 if (c->min >= hdsp->ss_in_channels) {
4403 struct snd_interval t = {
4408 return snd_interval_refine(r, &t);
4409 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4410 struct snd_interval t = {
4415 return snd_interval_refine(r, &t);
4416 } else if (c->max <= hdsp->ds_in_channels) {
4417 struct snd_interval t = {
4422 return snd_interval_refine(r, &t);
4427 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4429 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4430 struct snd_pcm_runtime *runtime = substream->runtime;
4432 if (hdsp_check_for_iobox (hdsp))
4435 if (hdsp_check_for_firmware(hdsp, 1))
4438 spin_lock_irq(&hdsp->lock);
4440 snd_pcm_set_sync(substream);
4442 runtime->hw = snd_hdsp_playback_subinfo;
4443 runtime->dma_area = hdsp->playback_buffer;
4444 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4446 hdsp->playback_pid = current->pid;
4447 hdsp->playback_substream = substream;
4449 spin_unlock_irq(&hdsp->lock);
4451 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4452 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4453 if (hdsp->clock_source_locked) {
4454 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4455 } else if (hdsp->io_type == H9632) {
4456 runtime->hw.rate_max = 192000;
4457 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4458 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4460 if (hdsp->io_type == H9632) {
4461 runtime->hw.channels_min = hdsp->qs_out_channels;
4462 runtime->hw.channels_max = hdsp->ss_out_channels;
4465 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4466 snd_hdsp_hw_rule_out_channels, hdsp,
4467 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4468 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4469 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4470 SNDRV_PCM_HW_PARAM_RATE, -1);
4471 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4472 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4473 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4475 if (RPM != hdsp->io_type) {
4476 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4477 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4478 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4479 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4484 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4486 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4488 spin_lock_irq(&hdsp->lock);
4490 hdsp->playback_pid = -1;
4491 hdsp->playback_substream = NULL;
4493 spin_unlock_irq(&hdsp->lock);
4495 if (RPM != hdsp->io_type) {
4496 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4497 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4498 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4504 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4506 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4507 struct snd_pcm_runtime *runtime = substream->runtime;
4509 if (hdsp_check_for_iobox (hdsp))
4512 if (hdsp_check_for_firmware(hdsp, 1))
4515 spin_lock_irq(&hdsp->lock);
4517 snd_pcm_set_sync(substream);
4519 runtime->hw = snd_hdsp_capture_subinfo;
4520 runtime->dma_area = hdsp->capture_buffer;
4521 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4523 hdsp->capture_pid = current->pid;
4524 hdsp->capture_substream = substream;
4526 spin_unlock_irq(&hdsp->lock);
4528 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4529 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4530 if (hdsp->io_type == H9632) {
4531 runtime->hw.channels_min = hdsp->qs_in_channels;
4532 runtime->hw.channels_max = hdsp->ss_in_channels;
4533 runtime->hw.rate_max = 192000;
4534 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4535 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4537 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4538 snd_hdsp_hw_rule_in_channels, hdsp,
4539 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4540 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4541 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4542 SNDRV_PCM_HW_PARAM_RATE, -1);
4543 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4544 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4545 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4549 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4551 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4553 spin_lock_irq(&hdsp->lock);
4555 hdsp->capture_pid = -1;
4556 hdsp->capture_substream = NULL;
4558 spin_unlock_irq(&hdsp->lock);
4562 /* helper functions for copying meter values */
4563 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4565 u32 val = readl(src);
4566 return copy_to_user(dest, &val, 4);
4569 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4571 u32 rms_low, rms_high;
4573 rms_low = readl(src_low);
4574 rms_high = readl(src_high);
4575 rms = ((u64)rms_high << 32) | rms_low;
4576 return copy_to_user(dest, &rms, 8);
4579 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4581 u32 rms_low, rms_high;
4583 rms_low = readl(src_low) & 0xffffff00;
4584 rms_high = readl(src_high) & 0xffffff00;
4585 rms = ((u64)rms_high << 32) | rms_low;
4586 return copy_to_user(dest, &rms, 8);
4589 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4591 int doublespeed = 0;
4592 int i, j, channels, ofs;
4594 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4596 channels = doublespeed ? 14 : 26;
4597 for (i = 0, j = 0; i < 26; ++i) {
4598 if (doublespeed && (i & 4))
4600 ofs = HDSP_9652_peakBase - j * 4;
4601 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4603 ofs -= channels * 4;
4604 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4606 ofs -= channels * 4;
4607 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4609 ofs = HDSP_9652_rmsBase + j * 8;
4610 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4611 hdsp->iobase + ofs + 4))
4613 ofs += channels * 8;
4614 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4615 hdsp->iobase + ofs + 4))
4617 ofs += channels * 8;
4618 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4619 hdsp->iobase + ofs + 4))
4626 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4629 struct hdsp_9632_meters __iomem *m;
4630 int doublespeed = 0;
4632 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4634 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4635 for (i = 0, j = 0; i < 16; ++i, ++j) {
4636 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4638 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4640 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4642 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4643 &m->input_rms_high[j]))
4645 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4646 &m->playback_rms_high[j]))
4648 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4649 &m->output_rms_high[j]))
4651 if (doublespeed && i == 3) i += 4;
4656 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4660 for (i = 0; i < 26; i++) {
4661 if (copy_u32_le(&peak_rms->playback_peaks[i],
4662 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4664 if (copy_u32_le(&peak_rms->input_peaks[i],
4665 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4668 for (i = 0; i < 28; i++) {
4669 if (copy_u32_le(&peak_rms->output_peaks[i],
4670 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4673 for (i = 0; i < 26; ++i) {
4674 if (copy_u64_le(&peak_rms->playback_rms[i],
4675 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4676 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4678 if (copy_u64_le(&peak_rms->input_rms[i],
4679 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4680 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4686 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4688 struct hdsp *hdsp = hw->private_data;
4689 void __user *argp = (void __user *)arg;
4693 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4694 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4696 err = hdsp_check_for_iobox(hdsp);
4700 err = hdsp_check_for_firmware(hdsp, 1);
4704 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4705 dev_err(hdsp->card->dev,
4706 "firmware needs to be uploaded to the card.\n");
4710 switch (hdsp->io_type) {
4712 return hdsp_9652_get_peak(hdsp, peak_rms);
4714 return hdsp_9632_get_peak(hdsp, peak_rms);
4716 return hdsp_get_peak(hdsp, peak_rms);
4719 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4720 struct hdsp_config_info info;
4721 unsigned long flags;
4724 err = hdsp_check_for_iobox(hdsp);
4728 err = hdsp_check_for_firmware(hdsp, 1);
4732 memset(&info, 0, sizeof(info));
4733 spin_lock_irqsave(&hdsp->lock, flags);
4734 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4735 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4736 if (hdsp->io_type != H9632)
4737 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4738 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4739 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4740 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4741 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4742 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4743 HDSP_SPDIFOpticalOut);
4744 info.spdif_professional = (unsigned char)
4745 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4746 info.spdif_emphasis = (unsigned char)
4747 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4748 info.spdif_nonaudio = (unsigned char)
4749 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4750 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4751 info.system_sample_rate = hdsp->system_sample_rate;
4752 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4753 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4754 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4755 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4756 info.line_out = (unsigned char)
4757 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4758 if (hdsp->io_type == H9632) {
4759 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4760 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4761 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4762 info.xlr_breakout_cable =
4763 (unsigned char)hdsp_toggle_setting(hdsp,
4764 HDSP_XLRBreakoutCable);
4766 } else if (hdsp->io_type == RPM) {
4767 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4768 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4770 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4771 info.analog_extension_board =
4772 (unsigned char)hdsp_toggle_setting(hdsp,
4773 HDSP_AnalogExtensionBoard);
4774 spin_unlock_irqrestore(&hdsp->lock, flags);
4775 if (copy_to_user(argp, &info, sizeof(info)))
4779 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4780 struct hdsp_9632_aeb h9632_aeb;
4782 if (hdsp->io_type != H9632) return -EINVAL;
4783 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4784 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4785 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4789 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4790 struct hdsp_version hdsp_version;
4793 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4794 if (hdsp->io_type == Undefined) {
4795 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4798 memset(&hdsp_version, 0, sizeof(hdsp_version));
4799 hdsp_version.io_type = hdsp->io_type;
4800 hdsp_version.firmware_rev = hdsp->firmware_rev;
4801 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4805 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4806 struct hdsp_firmware __user *firmware;
4807 u32 __user *firmware_data;
4810 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4811 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4812 if (hdsp->io_type == Undefined) return -EINVAL;
4814 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4817 dev_info(hdsp->card->dev,
4818 "initializing firmware upload\n");
4819 firmware = (struct hdsp_firmware __user *)argp;
4821 if (get_user(firmware_data, &firmware->firmware_data))
4824 if (hdsp_check_for_iobox (hdsp))
4827 if (!hdsp->fw_uploaded) {
4828 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4829 if (!hdsp->fw_uploaded)
4833 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4834 HDSP_FIRMWARE_SIZE)) {
4835 vfree(hdsp->fw_uploaded);
4836 hdsp->fw_uploaded = NULL;
4840 hdsp->state |= HDSP_FirmwareCached;
4842 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4845 if (!(hdsp->state & HDSP_InitializationComplete)) {
4846 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4849 snd_hdsp_initialize_channels(hdsp);
4850 snd_hdsp_initialize_midi_flush(hdsp);
4852 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4853 dev_err(hdsp->card->dev,
4854 "error creating alsa devices\n");
4860 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4861 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4862 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4872 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4873 .open = snd_hdsp_playback_open,
4874 .close = snd_hdsp_playback_release,
4875 .ioctl = snd_hdsp_ioctl,
4876 .hw_params = snd_hdsp_hw_params,
4877 .prepare = snd_hdsp_prepare,
4878 .trigger = snd_hdsp_trigger,
4879 .pointer = snd_hdsp_hw_pointer,
4880 .copy_user = snd_hdsp_playback_copy,
4881 .copy_kernel = snd_hdsp_playback_copy_kernel,
4882 .fill_silence = snd_hdsp_hw_silence,
4885 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4886 .open = snd_hdsp_capture_open,
4887 .close = snd_hdsp_capture_release,
4888 .ioctl = snd_hdsp_ioctl,
4889 .hw_params = snd_hdsp_hw_params,
4890 .prepare = snd_hdsp_prepare,
4891 .trigger = snd_hdsp_trigger,
4892 .pointer = snd_hdsp_hw_pointer,
4893 .copy_user = snd_hdsp_capture_copy,
4894 .copy_kernel = snd_hdsp_capture_copy_kernel,
4897 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4899 struct snd_hwdep *hw;
4902 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4906 hw->private_data = hdsp;
4907 strcpy(hw->name, "HDSP hwdep interface");
4909 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4910 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4915 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4917 struct snd_pcm *pcm;
4920 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4924 pcm->private_data = hdsp;
4925 strcpy(pcm->name, hdsp->card_name);
4927 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4928 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4930 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4935 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4937 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4938 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4941 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4945 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4946 dev_err(hdsp->card->dev,
4947 "enable_io fifo_wait failed\n");
4951 for (i = 0; i < hdsp->max_channels; ++i) {
4952 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4953 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4959 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4961 int status, aebi_channels, aebo_channels;
4963 switch (hdsp->io_type) {
4965 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4966 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4967 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4971 hdsp->card_name = "RME Hammerfall HDSP 9652";
4972 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4973 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4977 status = hdsp_read(hdsp, HDSP_statusRegister);
4978 /* HDSP_AEBx bits are low when AEB are connected */
4979 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4980 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4981 hdsp->card_name = "RME Hammerfall HDSP 9632";
4982 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4983 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4984 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4985 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4986 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4987 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4991 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4992 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4993 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4997 hdsp->card_name = "RME Hammerfall DSP + RPM";
4998 hdsp->ss_in_channels = RPM_CHANNELS-1;
4999 hdsp->ss_out_channels = RPM_CHANNELS;
5000 hdsp->ds_in_channels = RPM_CHANNELS-1;
5001 hdsp->ds_out_channels = RPM_CHANNELS;
5005 /* should never get here */
5010 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5012 snd_hdsp_flush_midi_input (hdsp, 0);
5013 snd_hdsp_flush_midi_input (hdsp, 1);
5016 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5020 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5022 "Error creating pcm interface\n");
5027 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5029 "Error creating first midi interface\n");
5033 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5034 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5036 "Error creating second midi interface\n");
5041 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5043 "Error creating ctl interface\n");
5047 snd_hdsp_proc_init(hdsp);
5049 hdsp->system_sample_rate = -1;
5050 hdsp->playback_pid = -1;
5051 hdsp->capture_pid = -1;
5052 hdsp->capture_substream = NULL;
5053 hdsp->playback_substream = NULL;
5055 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5057 "Error setting default values\n");
5061 if (!(hdsp->state & HDSP_InitializationComplete)) {
5062 strcpy(card->shortname, "Hammerfall DSP");
5063 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5064 hdsp->port, hdsp->irq);
5066 if ((err = snd_card_register(card)) < 0) {
5068 "error registering card\n");
5071 hdsp->state |= HDSP_InitializationComplete;
5077 /* load firmware via hotplug fw loader */
5078 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5081 const struct firmware *fw;
5084 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5086 if (hdsp->io_type == Undefined) {
5087 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5089 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5093 /* caution: max length of firmware filename is 30! */
5094 switch (hdsp->io_type) {
5096 fwfile = "/*(DEBLOBBED)*/";
5099 if (hdsp->firmware_rev == 0xa)
5100 fwfile = "/*(DEBLOBBED)*/";
5102 fwfile = "/*(DEBLOBBED)*/";
5105 if (hdsp->firmware_rev == 0xa)
5106 fwfile = "/*(DEBLOBBED)*/";
5108 fwfile = "/*(DEBLOBBED)*/";
5111 dev_err(hdsp->card->dev,
5112 "invalid io_type %d\n", hdsp->io_type);
5116 if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5117 dev_err(hdsp->card->dev,
5118 "cannot load firmware %s\n", fwfile);
5121 if (fw->size < HDSP_FIRMWARE_SIZE) {
5122 dev_err(hdsp->card->dev,
5123 "too short firmware size %d (expected %d)\n",
5124 (int)fw->size, HDSP_FIRMWARE_SIZE);
5125 release_firmware(fw);
5129 hdsp->firmware = fw;
5131 hdsp->state |= HDSP_FirmwareCached;
5133 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5136 if (!(hdsp->state & HDSP_InitializationComplete)) {
5137 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5140 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5141 dev_err(hdsp->card->dev,
5142 "error creating hwdep device\n");
5145 snd_hdsp_initialize_channels(hdsp);
5146 snd_hdsp_initialize_midi_flush(hdsp);
5147 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5148 dev_err(hdsp->card->dev,
5149 "error creating alsa devices\n");
5156 static int snd_hdsp_create(struct snd_card *card,
5159 struct pci_dev *pci = hdsp->pci;
5166 hdsp->midi[0].rmidi = NULL;
5167 hdsp->midi[1].rmidi = NULL;
5168 hdsp->midi[0].input = NULL;
5169 hdsp->midi[1].input = NULL;
5170 hdsp->midi[0].output = NULL;
5171 hdsp->midi[1].output = NULL;
5172 hdsp->midi[0].pending = 0;
5173 hdsp->midi[1].pending = 0;
5174 spin_lock_init(&hdsp->midi[0].lock);
5175 spin_lock_init(&hdsp->midi[1].lock);
5176 hdsp->iobase = NULL;
5177 hdsp->control_register = 0;
5178 hdsp->control2_register = 0;
5179 hdsp->io_type = Undefined;
5180 hdsp->max_channels = 26;
5184 spin_lock_init(&hdsp->lock);
5186 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5188 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5189 hdsp->firmware_rev &= 0xff;
5191 /* From Martin Bjoernsen :
5192 "It is important that the card's latency timer register in
5193 the PCI configuration space is set to a value much larger
5194 than 0 by the computer's BIOS or the driver.
5195 The windows driver always sets this 8 bit register [...]
5196 to its maximum 255 to avoid problems with some computers."
5198 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5200 strcpy(card->driver, "H-DSP");
5201 strcpy(card->mixername, "Xilinx FPGA");
5203 if (hdsp->firmware_rev < 0xa)
5205 else if (hdsp->firmware_rev < 0x64)
5206 hdsp->card_name = "RME Hammerfall DSP";
5207 else if (hdsp->firmware_rev < 0x96) {
5208 hdsp->card_name = "RME HDSP 9652";
5211 hdsp->card_name = "RME HDSP 9632";
5212 hdsp->max_channels = 16;
5216 if ((err = pci_enable_device(pci)) < 0)
5219 pci_set_master(hdsp->pci);
5221 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5223 hdsp->port = pci_resource_start(pci, 0);
5224 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5225 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5226 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5230 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5231 KBUILD_MODNAME, hdsp)) {
5232 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5236 hdsp->irq = pci->irq;
5237 hdsp->precise_ptr = 0;
5238 hdsp->use_midi_tasklet = 1;
5239 hdsp->dds_value = 0;
5241 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5244 if (!is_9652 && !is_9632) {
5245 /* we wait a maximum of 10 seconds to let freshly
5246 * inserted cardbus cards do their hardware init */
5247 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5252 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5253 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5254 /* we don't fail as this can happen
5255 if userspace is not ready for
5258 dev_err(hdsp->card->dev,
5259 "couldn't get firmware from userspace. try using hdsploader\n");
5261 /* init is complete, we return */
5263 /* we defer initialization */
5264 dev_info(hdsp->card->dev,
5265 "card initialization pending : waiting for firmware\n");
5266 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5270 dev_info(hdsp->card->dev,
5271 "Firmware already present, initializing card.\n");
5272 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5273 hdsp->io_type = RPM;
5274 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5275 hdsp->io_type = Multiface;
5277 hdsp->io_type = Digiface;
5281 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5285 hdsp->io_type = H9652;
5288 hdsp->io_type = H9632;
5290 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5293 snd_hdsp_initialize_channels(hdsp);
5294 snd_hdsp_initialize_midi_flush(hdsp);
5296 hdsp->state |= HDSP_FirmwareLoaded;
5298 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5304 static int snd_hdsp_free(struct hdsp *hdsp)
5307 /* stop the audio, and cancel all interrupts */
5308 tasklet_kill(&hdsp->midi_tasklet);
5309 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5310 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5314 free_irq(hdsp->irq, (void *)hdsp);
5316 snd_hdsp_free_buffers(hdsp);
5318 release_firmware(hdsp->firmware);
5319 vfree(hdsp->fw_uploaded);
5320 iounmap(hdsp->iobase);
5323 pci_release_regions(hdsp->pci);
5325 if (pci_is_enabled(hdsp->pci))
5326 pci_disable_device(hdsp->pci);
5330 static void snd_hdsp_card_free(struct snd_card *card)
5332 struct hdsp *hdsp = card->private_data;
5335 snd_hdsp_free(hdsp);
5338 static int snd_hdsp_probe(struct pci_dev *pci,
5339 const struct pci_device_id *pci_id)
5343 struct snd_card *card;
5346 if (dev >= SNDRV_CARDS)
5353 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5354 sizeof(struct hdsp), &card);
5358 hdsp = card->private_data;
5359 card->private_free = snd_hdsp_card_free;
5362 err = snd_hdsp_create(card, hdsp);
5366 strcpy(card->shortname, "Hammerfall DSP");
5367 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5368 hdsp->port, hdsp->irq);
5369 err = snd_card_register(card);
5372 snd_card_free(card);
5375 pci_set_drvdata(pci, card);
5380 static void snd_hdsp_remove(struct pci_dev *pci)
5382 snd_card_free(pci_get_drvdata(pci));
5385 static struct pci_driver hdsp_driver = {
5386 .name = KBUILD_MODNAME,
5387 .id_table = snd_hdsp_ids,
5388 .probe = snd_hdsp_probe,
5389 .remove = snd_hdsp_remove,
5392 module_pci_driver(hdsp_driver);