1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
4 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
5 * Takashi Iwai <tiwai@suse.de>
7 * Most of the hardware init stuffs are based on maestro3 driver for
8 * OSS/Free by Zach Brown. Many thanks to Zach!
12 * - Fixed deadlock on capture
13 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
16 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
17 #define DRIVER_NAME "Maestro3"
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/module.h>
28 #include <linux/firmware.h>
29 #include <linux/input.h>
30 #include <sound/core.h>
31 #include <sound/info.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/mpu401.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/initval.h>
37 #include <asm/byteorder.h>
39 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
40 MODULE_DESCRIPTION("ESS Maestro3 PCI");
41 MODULE_LICENSE("GPL");
44 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
45 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
46 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
47 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
48 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
50 module_param_array(index, int, NULL, 0444);
51 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
52 module_param_array(id, charp, NULL, 0444);
53 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
54 module_param_array(enable, bool, NULL, 0444);
55 MODULE_PARM_DESC(enable, "Enable this soundcard.");
56 module_param_array(external_amp, bool, NULL, 0444);
57 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
58 module_param_array(amp_gpio, int, NULL, 0444);
59 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
61 #define MAX_PLAYBACKS 2
62 #define MAX_CAPTURES 1
63 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
70 /* Allegro PCI configuration registers */
71 #define PCI_LEGACY_AUDIO_CTRL 0x40
72 #define SOUND_BLASTER_ENABLE 0x00000001
73 #define FM_SYNTHESIS_ENABLE 0x00000002
74 #define GAME_PORT_ENABLE 0x00000004
75 #define MPU401_IO_ENABLE 0x00000008
76 #define MPU401_IRQ_ENABLE 0x00000010
77 #define ALIAS_10BIT_IO 0x00000020
78 #define SB_DMA_MASK 0x000000C0
79 #define SB_DMA_0 0x00000040
80 #define SB_DMA_1 0x00000040
81 #define SB_DMA_R 0x00000080
82 #define SB_DMA_3 0x000000C0
83 #define SB_IRQ_MASK 0x00000700
84 #define SB_IRQ_5 0x00000000
85 #define SB_IRQ_7 0x00000100
86 #define SB_IRQ_9 0x00000200
87 #define SB_IRQ_10 0x00000300
88 #define MIDI_IRQ_MASK 0x00003800
89 #define SERIAL_IRQ_ENABLE 0x00004000
90 #define DISABLE_LEGACY 0x00008000
92 #define PCI_ALLEGRO_CONFIG 0x50
93 #define SB_ADDR_240 0x00000004
94 #define MPU_ADDR_MASK 0x00000018
95 #define MPU_ADDR_330 0x00000000
96 #define MPU_ADDR_300 0x00000008
97 #define MPU_ADDR_320 0x00000010
98 #define MPU_ADDR_340 0x00000018
99 #define USE_PCI_TIMING 0x00000040
100 #define POSTED_WRITE_ENABLE 0x00000080
101 #define DMA_POLICY_MASK 0x00000700
102 #define DMA_DDMA 0x00000000
103 #define DMA_TDMA 0x00000100
104 #define DMA_PCPCI 0x00000200
105 #define DMA_WBDMA16 0x00000400
106 #define DMA_WBDMA4 0x00000500
107 #define DMA_WBDMA2 0x00000600
108 #define DMA_WBDMA1 0x00000700
109 #define DMA_SAFE_GUARD 0x00000800
110 #define HI_PERF_GP_ENABLE 0x00001000
111 #define PIC_SNOOP_MODE_0 0x00002000
112 #define PIC_SNOOP_MODE_1 0x00004000
113 #define SOUNDBLASTER_IRQ_MASK 0x00008000
114 #define RING_IN_ENABLE 0x00010000
115 #define SPDIF_TEST_MODE 0x00020000
116 #define CLK_MULT_MODE_SELECT_2 0x00040000
117 #define EEPROM_WRITE_ENABLE 0x00080000
118 #define CODEC_DIR_IN 0x00100000
119 #define HV_BUTTON_FROM_GD 0x00200000
120 #define REDUCED_DEBOUNCE 0x00400000
121 #define HV_CTRL_ENABLE 0x00800000
122 #define SPDIF_ENABLE 0x01000000
123 #define CLK_DIV_SELECT 0x06000000
124 #define CLK_DIV_BY_48 0x00000000
125 #define CLK_DIV_BY_49 0x02000000
126 #define CLK_DIV_BY_50 0x04000000
127 #define CLK_DIV_RESERVED 0x06000000
128 #define PM_CTRL_ENABLE 0x08000000
129 #define CLK_MULT_MODE_SELECT 0x30000000
130 #define CLK_MULT_MODE_SHIFT 28
131 #define CLK_MULT_MODE_0 0x00000000
132 #define CLK_MULT_MODE_1 0x10000000
133 #define CLK_MULT_MODE_2 0x20000000
134 #define CLK_MULT_MODE_3 0x30000000
135 #define INT_CLK_SELECT 0x40000000
136 #define INT_CLK_MULT_RESET 0x80000000
139 #define INT_CLK_SRC_NOT_PCI 0x00100000
140 #define INT_CLK_MULT_ENABLE 0x80000000
142 #define PCI_ACPI_CONTROL 0x54
143 #define PCI_ACPI_D0 0x00000000
144 #define PCI_ACPI_D1 0xB4F70000
145 #define PCI_ACPI_D2 0xB4F7B4F7
147 #define PCI_USER_CONFIG 0x58
148 #define EXT_PCI_MASTER_ENABLE 0x00000001
149 #define SPDIF_OUT_SELECT 0x00000002
150 #define TEST_PIN_DIR_CTRL 0x00000004
151 #define AC97_CODEC_TEST 0x00000020
152 #define TRI_STATE_BUFFER 0x00000080
153 #define IN_CLK_12MHZ_SELECT 0x00000100
154 #define MULTI_FUNC_DISABLE 0x00000200
155 #define EXT_MASTER_PAIR_SEL 0x00000400
156 #define PCI_MASTER_SUPPORT 0x00000800
157 #define STOP_CLOCK_ENABLE 0x00001000
158 #define EAPD_DRIVE_ENABLE 0x00002000
159 #define REQ_TRI_STATE_ENABLE 0x00004000
160 #define REQ_LOW_ENABLE 0x00008000
161 #define MIDI_1_ENABLE 0x00010000
162 #define MIDI_2_ENABLE 0x00020000
163 #define SB_AUDIO_SYNC 0x00040000
164 #define HV_CTRL_TEST 0x00100000
165 #define SOUNDBLASTER_TEST 0x00400000
167 #define PCI_USER_CONFIG_C 0x5C
169 #define PCI_DDMA_CTRL 0x60
170 #define DDMA_ENABLE 0x00000001
173 /* Allegro registers */
174 #define HOST_INT_CTRL 0x18
175 #define SB_INT_ENABLE 0x0001
176 #define MPU401_INT_ENABLE 0x0002
177 #define ASSP_INT_ENABLE 0x0010
178 #define RING_INT_ENABLE 0x0020
179 #define HV_INT_ENABLE 0x0040
180 #define CLKRUN_GEN_ENABLE 0x0100
181 #define HV_CTRL_TO_PME 0x0400
182 #define SOFTWARE_RESET_ENABLE 0x8000
185 * should be using the above defines, probably.
187 #define REGB_ENABLE_RESET 0x01
188 #define REGB_STOP_CLOCK 0x10
190 #define HOST_INT_STATUS 0x1A
191 #define SB_INT_PENDING 0x01
192 #define MPU401_INT_PENDING 0x02
193 #define ASSP_INT_PENDING 0x10
194 #define RING_INT_PENDING 0x20
195 #define HV_INT_PENDING 0x40
197 #define HARDWARE_VOL_CTRL 0x1B
198 #define SHADOW_MIX_REG_VOICE 0x1C
199 #define HW_VOL_COUNTER_VOICE 0x1D
200 #define SHADOW_MIX_REG_MASTER 0x1E
201 #define HW_VOL_COUNTER_MASTER 0x1F
203 #define CODEC_COMMAND 0x30
204 #define CODEC_READ_B 0x80
206 #define CODEC_STATUS 0x30
207 #define CODEC_BUSY_B 0x01
209 #define CODEC_DATA 0x32
211 #define RING_BUS_CTRL_A 0x36
212 #define RAC_PME_ENABLE 0x0100
213 #define RAC_SDFS_ENABLE 0x0200
214 #define LAC_PME_ENABLE 0x0400
215 #define LAC_SDFS_ENABLE 0x0800
216 #define SERIAL_AC_LINK_ENABLE 0x1000
217 #define IO_SRAM_ENABLE 0x2000
218 #define IIS_INPUT_ENABLE 0x8000
220 #define RING_BUS_CTRL_B 0x38
221 #define SECOND_CODEC_ID_MASK 0x0003
222 #define SPDIF_FUNC_ENABLE 0x0010
223 #define SECOND_AC_ENABLE 0x0020
224 #define SB_MODULE_INTF_ENABLE 0x0040
225 #define SSPE_ENABLE 0x0040
226 #define M3I_DOCK_ENABLE 0x0080
228 #define SDO_OUT_DEST_CTRL 0x3A
229 #define COMMAND_ADDR_OUT 0x0003
230 #define PCM_LR_OUT_LOCAL 0x0000
231 #define PCM_LR_OUT_REMOTE 0x0004
232 #define PCM_LR_OUT_MUTE 0x0008
233 #define PCM_LR_OUT_BOTH 0x000C
234 #define LINE1_DAC_OUT_LOCAL 0x0000
235 #define LINE1_DAC_OUT_REMOTE 0x0010
236 #define LINE1_DAC_OUT_MUTE 0x0020
237 #define LINE1_DAC_OUT_BOTH 0x0030
238 #define PCM_CLS_OUT_LOCAL 0x0000
239 #define PCM_CLS_OUT_REMOTE 0x0040
240 #define PCM_CLS_OUT_MUTE 0x0080
241 #define PCM_CLS_OUT_BOTH 0x00C0
242 #define PCM_RLF_OUT_LOCAL 0x0000
243 #define PCM_RLF_OUT_REMOTE 0x0100
244 #define PCM_RLF_OUT_MUTE 0x0200
245 #define PCM_RLF_OUT_BOTH 0x0300
246 #define LINE2_DAC_OUT_LOCAL 0x0000
247 #define LINE2_DAC_OUT_REMOTE 0x0400
248 #define LINE2_DAC_OUT_MUTE 0x0800
249 #define LINE2_DAC_OUT_BOTH 0x0C00
250 #define HANDSET_OUT_LOCAL 0x0000
251 #define HANDSET_OUT_REMOTE 0x1000
252 #define HANDSET_OUT_MUTE 0x2000
253 #define HANDSET_OUT_BOTH 0x3000
254 #define IO_CTRL_OUT_LOCAL 0x0000
255 #define IO_CTRL_OUT_REMOTE 0x4000
256 #define IO_CTRL_OUT_MUTE 0x8000
257 #define IO_CTRL_OUT_BOTH 0xC000
259 #define SDO_IN_DEST_CTRL 0x3C
260 #define STATUS_ADDR_IN 0x0003
261 #define PCM_LR_IN_LOCAL 0x0000
262 #define PCM_LR_IN_REMOTE 0x0004
263 #define PCM_LR_RESERVED 0x0008
264 #define PCM_LR_IN_BOTH 0x000C
265 #define LINE1_ADC_IN_LOCAL 0x0000
266 #define LINE1_ADC_IN_REMOTE 0x0010
267 #define LINE1_ADC_IN_MUTE 0x0020
268 #define MIC_ADC_IN_LOCAL 0x0000
269 #define MIC_ADC_IN_REMOTE 0x0040
270 #define MIC_ADC_IN_MUTE 0x0080
271 #define LINE2_DAC_IN_LOCAL 0x0000
272 #define LINE2_DAC_IN_REMOTE 0x0400
273 #define LINE2_DAC_IN_MUTE 0x0800
274 #define HANDSET_IN_LOCAL 0x0000
275 #define HANDSET_IN_REMOTE 0x1000
276 #define HANDSET_IN_MUTE 0x2000
277 #define IO_STATUS_IN_LOCAL 0x0000
278 #define IO_STATUS_IN_REMOTE 0x4000
280 #define SPDIF_IN_CTRL 0x3E
281 #define SPDIF_IN_ENABLE 0x0001
283 #define GPIO_DATA 0x60
284 #define GPIO_DATA_MASK 0x0FFF
285 #define GPIO_HV_STATUS 0x3000
286 #define GPIO_PME_STATUS 0x4000
288 #define GPIO_MASK 0x64
289 #define GPIO_DIRECTION 0x68
290 #define GPO_PRIMARY_AC97 0x0001
291 #define GPI_LINEOUT_SENSE 0x0004
292 #define GPO_SECONDARY_AC97 0x0008
293 #define GPI_VOL_DOWN 0x0010
294 #define GPI_VOL_UP 0x0020
295 #define GPI_IIS_CLK 0x0040
296 #define GPI_IIS_LRCLK 0x0080
297 #define GPI_IIS_DATA 0x0100
298 #define GPI_DOCKING_STATUS 0x0100
299 #define GPI_HEADPHONE_SENSE 0x0200
300 #define GPO_EXT_AMP_SHUTDOWN 0x1000
302 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
303 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
306 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
308 #define ASSP_INDEX_PORT 0x80
309 #define ASSP_MEMORY_PORT 0x82
310 #define ASSP_DATA_PORT 0x84
312 #define MPU401_DATA_PORT 0x98
313 #define MPU401_STATUS_PORT 0x99
315 #define CLK_MULT_DATA_PORT 0x9C
317 #define ASSP_CONTROL_A 0xA2
318 #define ASSP_0_WS_ENABLE 0x01
319 #define ASSP_CTRL_A_RESERVED1 0x02
320 #define ASSP_CTRL_A_RESERVED2 0x04
321 #define ASSP_CLK_49MHZ_SELECT 0x08
322 #define FAST_PLU_ENABLE 0x10
323 #define ASSP_CTRL_A_RESERVED3 0x20
324 #define DSP_CLK_36MHZ_SELECT 0x40
326 #define ASSP_CONTROL_B 0xA4
327 #define RESET_ASSP 0x00
328 #define RUN_ASSP 0x01
329 #define ENABLE_ASSP_CLOCK 0x00
330 #define STOP_ASSP_CLOCK 0x10
331 #define RESET_TOGGLE 0x40
333 #define ASSP_CONTROL_C 0xA6
334 #define ASSP_HOST_INT_ENABLE 0x01
335 #define FM_ADDR_REMAP_DISABLE 0x02
336 #define HOST_WRITE_PORT_ENABLE 0x08
338 #define ASSP_HOST_INT_STATUS 0xAC
339 #define DSP2HOST_REQ_PIORECORD 0x01
340 #define DSP2HOST_REQ_I2SRATE 0x02
341 #define DSP2HOST_REQ_TIMER 0x04
346 #define DSP_PORT_TIMER_COUNT 0x06
348 #define DSP_PORT_MEMORY_INDEX 0x80
350 #define DSP_PORT_MEMORY_TYPE 0x82
351 #define MEMTYPE_INTERNAL_CODE 0x0002
352 #define MEMTYPE_INTERNAL_DATA 0x0003
353 #define MEMTYPE_MASK 0x0003
355 #define DSP_PORT_MEMORY_DATA 0x84
357 #define DSP_PORT_CONTROL_REG_A 0xA2
358 #define DSP_PORT_CONTROL_REG_B 0xA4
359 #define DSP_PORT_CONTROL_REG_C 0xA6
361 #define REV_A_CODE_MEMORY_BEGIN 0x0000
362 #define REV_A_CODE_MEMORY_END 0x0FFF
363 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
364 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
366 #define REV_B_CODE_MEMORY_BEGIN 0x0000
367 #define REV_B_CODE_MEMORY_END 0x0BFF
368 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
369 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
371 #define REV_A_DATA_MEMORY_BEGIN 0x1000
372 #define REV_A_DATA_MEMORY_END 0x2FFF
373 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
374 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
376 #define REV_B_DATA_MEMORY_BEGIN 0x1000
377 #define REV_B_DATA_MEMORY_END 0x2BFF
378 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
379 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
382 #define NUM_UNITS_KERNEL_CODE 16
383 #define NUM_UNITS_KERNEL_DATA 2
385 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
386 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
392 #define DP_SHIFT_COUNT 7
394 #define KDATA_BASE_ADDR 0x1000
395 #define KDATA_BASE_ADDR2 0x1080
397 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
398 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
399 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
400 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
401 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
402 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
403 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
404 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
405 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
407 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
408 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
410 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
411 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
412 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
413 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
414 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
415 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
416 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
417 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
418 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
419 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
421 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
422 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
424 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
425 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
427 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
428 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
430 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
431 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
432 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
434 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
435 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
436 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
437 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
438 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
440 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
441 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
442 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
444 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
445 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
446 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
448 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
449 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
450 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
451 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
452 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
453 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
454 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
455 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
456 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
457 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
459 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
460 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
461 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
463 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
464 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
466 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
467 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
468 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
470 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
471 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
472 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
473 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
474 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
475 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
477 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
478 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
479 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
480 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
481 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
482 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
484 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
485 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
486 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
487 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
488 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
489 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
491 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
492 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
493 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
494 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
496 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
497 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
499 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
500 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
502 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
503 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
504 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
505 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
506 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
508 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
509 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
511 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
512 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
513 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
515 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
516 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
518 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
520 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
521 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
522 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
523 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
524 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
525 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
526 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
527 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
528 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
529 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
530 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
531 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
533 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
534 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
535 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
536 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
538 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
539 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
541 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
542 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
543 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
544 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
546 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
547 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
548 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
549 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
550 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
553 * second 'segment' (?) reserved for mixer
557 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
558 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
559 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
560 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
561 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
562 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
563 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
564 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
565 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
566 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
567 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
568 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
569 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
570 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
571 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
572 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
574 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
575 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
576 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
577 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
578 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
579 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
580 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
581 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
582 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
583 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
584 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
586 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
587 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
588 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
589 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
590 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
591 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
593 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
594 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
595 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
596 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
599 * client data area offsets
601 #define CDATA_INSTANCE_READY 0x00
603 #define CDATA_HOST_SRC_ADDRL 0x01
604 #define CDATA_HOST_SRC_ADDRH 0x02
605 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
606 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
607 #define CDATA_HOST_SRC_CURRENTL 0x05
608 #define CDATA_HOST_SRC_CURRENTH 0x06
610 #define CDATA_IN_BUF_CONNECT 0x07
611 #define CDATA_OUT_BUF_CONNECT 0x08
613 #define CDATA_IN_BUF_BEGIN 0x09
614 #define CDATA_IN_BUF_END_PLUS_1 0x0A
615 #define CDATA_IN_BUF_HEAD 0x0B
616 #define CDATA_IN_BUF_TAIL 0x0C
617 #define CDATA_OUT_BUF_BEGIN 0x0D
618 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
619 #define CDATA_OUT_BUF_HEAD 0x0F
620 #define CDATA_OUT_BUF_TAIL 0x10
622 #define CDATA_DMA_CONTROL 0x11
623 #define CDATA_RESERVED 0x12
625 #define CDATA_FREQUENCY 0x13
626 #define CDATA_LEFT_VOLUME 0x14
627 #define CDATA_RIGHT_VOLUME 0x15
628 #define CDATA_LEFT_SUR_VOL 0x16
629 #define CDATA_RIGHT_SUR_VOL 0x17
631 #define CDATA_HEADER_LEN 0x18
633 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
634 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
635 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
636 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
637 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
638 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
639 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
640 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
642 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
643 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
644 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
645 #define MINISRC_BIQUAD_STAGE 2
646 #define MINISRC_COEF_LOC 0x175
648 #define DMACONTROL_BLOCK_MASK 0x000F
649 #define DMAC_BLOCK0_SELECTOR 0x0000
650 #define DMAC_BLOCK1_SELECTOR 0x0001
651 #define DMAC_BLOCK2_SELECTOR 0x0002
652 #define DMAC_BLOCK3_SELECTOR 0x0003
653 #define DMAC_BLOCK4_SELECTOR 0x0004
654 #define DMAC_BLOCK5_SELECTOR 0x0005
655 #define DMAC_BLOCK6_SELECTOR 0x0006
656 #define DMAC_BLOCK7_SELECTOR 0x0007
657 #define DMAC_BLOCK8_SELECTOR 0x0008
658 #define DMAC_BLOCK9_SELECTOR 0x0009
659 #define DMAC_BLOCKA_SELECTOR 0x000A
660 #define DMAC_BLOCKB_SELECTOR 0x000B
661 #define DMAC_BLOCKC_SELECTOR 0x000C
662 #define DMAC_BLOCKD_SELECTOR 0x000D
663 #define DMAC_BLOCKE_SELECTOR 0x000E
664 #define DMAC_BLOCKF_SELECTOR 0x000F
665 #define DMACONTROL_PAGE_MASK 0x00F0
666 #define DMAC_PAGE0_SELECTOR 0x0030
667 #define DMAC_PAGE1_SELECTOR 0x0020
668 #define DMAC_PAGE2_SELECTOR 0x0010
669 #define DMAC_PAGE3_SELECTOR 0x0000
670 #define DMACONTROL_AUTOREPEAT 0x1000
671 #define DMACONTROL_STOPPED 0x2000
672 #define DMACONTROL_DIRECTION 0x0100
675 * an arbitrary volume we set the internal
676 * volume settings to so that the ac97 volume
677 * range is a little less insane. 0x7fff is
680 #define ARB_VOLUME ( 0x6800 )
694 struct snd_pcm_substream *substream;
696 struct assp_instance {
697 unsigned short code, data;
703 unsigned long buffer_addr;
710 struct m3_list *index_list[3];
714 struct list_head list;
720 struct snd_card *card;
722 unsigned long iobase;
725 unsigned int allegro_flag : 1;
727 struct snd_ac97 *ac97;
736 struct m3_list msrc_list;
737 struct m3_list mixer_list;
738 struct m3_list adc1_list;
739 struct m3_list dma_list;
741 /* for storing reset state..*/
745 int amp_gpio; /* gpio pin # for external amp, -1 = default */
746 unsigned int hv_config; /* hardware-volume config bits */
747 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
748 (e.g. for IrDA on Dell Inspirons) */
749 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
752 struct snd_rawmidi *rmidi;
756 struct m3_dma *substreams;
760 #ifdef CONFIG_SND_MAESTRO3_INPUT
761 struct input_dev *input_dev;
762 char phys[64]; /* physical device path */
764 struct snd_kcontrol *master_switch;
765 struct snd_kcontrol *master_volume;
767 struct work_struct hwvol_work;
769 unsigned int in_suspend;
771 #ifdef CONFIG_PM_SLEEP
775 const struct firmware *assp_kernel_image;
776 const struct firmware *assp_minisrc_image;
782 static const struct pci_device_id snd_m3_ids[] = {
783 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
784 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
785 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
786 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
787 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
788 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
789 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
790 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
791 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
792 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
793 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
794 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
795 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
796 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
797 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
798 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
802 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
804 static const struct snd_pci_quirk m3_amp_quirk_list[] = {
805 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
806 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
807 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
808 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
809 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
813 static const struct snd_pci_quirk m3_irda_quirk_list[] = {
814 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
815 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
816 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
820 /* hardware volume quirks */
821 static const struct snd_pci_quirk m3_hv_quirk_list[] = {
823 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
824 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
825 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
826 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
827 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
828 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
829 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
830 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
831 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
832 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
833 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
834 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
835 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
836 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
837 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
838 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
839 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
840 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
841 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
842 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
843 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
844 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
848 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
849 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
850 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
851 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
852 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
853 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
854 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
855 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
856 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
857 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
858 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
859 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
860 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
861 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
862 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
863 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
864 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
865 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
866 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
867 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
868 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
869 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
870 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
871 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
872 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
873 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
874 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
875 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
876 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
878 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
879 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
880 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
881 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
882 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
883 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
884 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
885 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
886 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
887 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
888 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
889 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
890 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
891 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
892 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
893 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
894 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
898 /* HP Omnibook quirks */
899 static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
900 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
901 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
909 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
911 outw(value, chip->iobase + reg);
914 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
916 return inw(chip->iobase + reg);
919 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
921 outb(value, chip->iobase + reg);
924 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
926 return inb(chip->iobase + reg);
930 * access 16bit words to the code or data regions of the dsp's memory.
931 * index addresses 16bit words.
933 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
935 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
936 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
937 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
940 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
942 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
943 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
944 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
947 static void snd_m3_assp_halt(struct snd_m3 *chip)
949 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
951 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
954 static void snd_m3_assp_continue(struct snd_m3 *chip)
956 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
961 * This makes me sad. the maestro3 has lists
962 * internally that must be packed.. 0 terminates,
963 * apparently, or maybe all unused entries have
964 * to be 0, the lists have static lengths set
965 * by the binary code images.
968 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
970 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
971 list->mem_addr + list->curlen,
973 return list->curlen++;
976 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
979 int lastindex = list->curlen - 1;
981 if (index != lastindex) {
982 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
983 list->mem_addr + lastindex);
984 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
985 list->mem_addr + index,
989 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
990 list->mem_addr + lastindex,
996 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
999 if (chip->timer_users != 1)
1002 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1003 KDATA_TIMER_COUNT_RELOAD,
1006 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1007 KDATA_TIMER_COUNT_CURRENT,
1011 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1015 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1017 chip->timer_users--;
1018 if (chip->timer_users > 0)
1021 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1022 KDATA_TIMER_COUNT_RELOAD,
1025 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1026 KDATA_TIMER_COUNT_CURRENT,
1030 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1038 /* spinlock held! */
1039 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1040 struct snd_pcm_substream *subs)
1045 snd_m3_inc_timer_users(chip);
1046 switch (subs->stream) {
1047 case SNDRV_PCM_STREAM_PLAYBACK:
1048 chip->dacs_active++;
1049 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1050 s->inst.data + CDATA_INSTANCE_READY, 1);
1051 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1052 KDATA_MIXER_TASK_NUMBER,
1055 case SNDRV_PCM_STREAM_CAPTURE:
1056 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1057 KDATA_ADC1_REQUEST, 1);
1058 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1059 s->inst.data + CDATA_INSTANCE_READY, 1);
1065 /* spinlock held! */
1066 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1067 struct snd_pcm_substream *subs)
1072 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073 s->inst.data + CDATA_INSTANCE_READY, 0);
1074 snd_m3_dec_timer_users(chip);
1075 switch (subs->stream) {
1076 case SNDRV_PCM_STREAM_PLAYBACK:
1077 chip->dacs_active--;
1078 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1079 KDATA_MIXER_TASK_NUMBER,
1082 case SNDRV_PCM_STREAM_CAPTURE:
1083 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084 KDATA_ADC1_REQUEST, 0);
1091 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1093 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1094 struct m3_dma *s = subs->runtime->private_data;
1100 spin_lock(&chip->reg_lock);
1102 case SNDRV_PCM_TRIGGER_START:
1103 case SNDRV_PCM_TRIGGER_RESUME:
1108 err = snd_m3_pcm_start(chip, s, subs);
1111 case SNDRV_PCM_TRIGGER_STOP:
1112 case SNDRV_PCM_TRIGGER_SUSPEND:
1114 err = 0; /* should return error? */
1117 err = snd_m3_pcm_stop(chip, s, subs);
1121 spin_unlock(&chip->reg_lock);
1129 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1131 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1132 struct snd_pcm_runtime *runtime = subs->runtime;
1134 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1135 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1136 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1138 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1139 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1141 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1142 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1144 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1145 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1149 #define LO(x) ((x) & 0xffff)
1150 #define HI(x) LO((x) >> 16)
1152 /* host dma buffer pointers */
1153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1154 s->inst.data + CDATA_HOST_SRC_ADDRL,
1155 LO(s->buffer_addr));
1157 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1158 s->inst.data + CDATA_HOST_SRC_ADDRH,
1159 HI(s->buffer_addr));
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1163 LO(s->buffer_addr + s->dma_size));
1165 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1166 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1167 HI(s->buffer_addr + s->dma_size));
1169 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1170 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1171 LO(s->buffer_addr));
1173 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1174 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1175 HI(s->buffer_addr));
1181 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1182 s->inst.data + CDATA_IN_BUF_BEGIN,
1185 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1186 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1187 dsp_in_buffer + (dsp_in_size / 2));
1189 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1190 s->inst.data + CDATA_IN_BUF_HEAD,
1193 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1194 s->inst.data + CDATA_IN_BUF_TAIL,
1197 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1198 s->inst.data + CDATA_OUT_BUF_BEGIN,
1201 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1202 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1203 dsp_out_buffer + (dsp_out_size / 2));
1205 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1206 s->inst.data + CDATA_OUT_BUF_HEAD,
1209 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1210 s->inst.data + CDATA_OUT_BUF_TAIL,
1214 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1215 struct snd_pcm_runtime *runtime)
1220 * put us in the lists if we're not already there
1222 if (! s->in_lists) {
1223 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1224 s->inst.data >> DP_SHIFT_COUNT);
1225 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1226 s->inst.data >> DP_SHIFT_COUNT);
1227 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1228 s->inst.data >> DP_SHIFT_COUNT);
1232 /* write to 'mono' word */
1233 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1234 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1235 runtime->channels == 2 ? 0 : 1);
1236 /* write to '8bit' word */
1237 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1238 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1239 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1241 /* set up dac/adc rate */
1242 freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000);
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + CDATA_FREQUENCY,
1252 static const struct play_vals {
1255 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1256 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1257 {SRC3_DIRECTION_OFFSET, 0} ,
1258 /* +1, +2 are stereo/16 bit */
1259 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1260 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1261 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1262 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1263 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1264 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1265 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1266 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1267 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1268 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1269 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1270 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1271 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1272 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1273 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1274 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1275 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1279 /* the mode passed should be already shifted and masked */
1281 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1282 struct snd_pcm_substream *subs)
1287 * some per client initializers
1290 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1291 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1292 s->inst.data + 40 + 8);
1294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1296 s->inst.code + MINISRC_COEF_LOC);
1298 /* enable or disable low pass filter? */
1299 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1301 subs->runtime->rate > 45000 ? 0xff : 0);
1303 /* tell it which way dma is going? */
1304 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1305 s->inst.data + CDATA_DMA_CONTROL,
1306 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1309 * set an armload of static initializers
1311 for (i = 0; i < ARRAY_SIZE(pv); i++)
1312 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1313 s->inst.data + pv[i].addr, pv[i].val);
1317 * Native record driver
1319 static const struct rec_vals {
1322 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1323 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1324 {SRC3_DIRECTION_OFFSET, 1} ,
1325 /* +1, +2 are stereo/16 bit */
1326 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1327 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1328 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1329 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1330 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1331 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1332 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1333 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1334 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1335 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1336 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1337 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1338 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1339 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1340 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1341 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1342 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1343 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1344 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1348 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1353 * some per client initializers
1356 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1357 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1358 s->inst.data + 40 + 8);
1360 /* tell it which way dma is going? */
1361 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1362 s->inst.data + CDATA_DMA_CONTROL,
1363 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1364 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1367 * set an armload of static initializers
1369 for (i = 0; i < ARRAY_SIZE(rv); i++)
1370 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1371 s->inst.data + rv[i].addr, rv[i].val);
1374 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1375 struct snd_pcm_hw_params *hw_params)
1377 struct m3_dma *s = substream->runtime->private_data;
1379 /* set buffer address */
1380 s->buffer_addr = substream->runtime->dma_addr;
1381 if (s->buffer_addr & 0x3) {
1382 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1383 s->buffer_addr = s->buffer_addr & ~0x3;
1388 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1392 if (substream->runtime->private_data == NULL)
1394 s = substream->runtime->private_data;
1400 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1402 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1403 struct snd_pcm_runtime *runtime = subs->runtime;
1404 struct m3_dma *s = runtime->private_data;
1409 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1410 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1412 if (runtime->rate > 48000 ||
1413 runtime->rate < 8000)
1416 spin_lock_irq(&chip->reg_lock);
1418 snd_m3_pcm_setup1(chip, s, subs);
1420 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1421 snd_m3_playback_setup(chip, s, subs);
1423 snd_m3_capture_setup(chip, s, subs);
1425 snd_m3_pcm_setup2(chip, s, runtime);
1427 spin_unlock_irq(&chip->reg_lock);
1433 * get current pointer
1436 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1443 * try and get a valid answer
1446 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1447 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1449 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1450 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1452 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1453 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1456 addr = lo | ((u32)hi<<16);
1457 return (unsigned int)(addr - s->buffer_addr);
1460 static snd_pcm_uframes_t
1461 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1463 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1465 struct m3_dma *s = subs->runtime->private_data;
1470 spin_lock(&chip->reg_lock);
1471 ptr = snd_m3_get_pointer(chip, s, subs);
1472 spin_unlock(&chip->reg_lock);
1473 return bytes_to_frames(subs->runtime, ptr);
1477 /* update pointer */
1478 /* spinlock held! */
1479 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1481 struct snd_pcm_substream *subs = s->substream;
1488 hwptr = snd_m3_get_pointer(chip, s, subs);
1490 /* try to avoid expensive modulo divisions */
1491 if (hwptr >= s->dma_size)
1492 hwptr %= s->dma_size;
1494 diff = s->dma_size + hwptr - s->hwptr;
1495 if (diff >= s->dma_size)
1496 diff %= s->dma_size;
1501 if (s->count >= (signed)s->period_size) {
1503 if (s->count < 2 * (signed)s->period_size)
1504 s->count -= (signed)s->period_size;
1506 s->count %= s->period_size;
1508 spin_unlock(&chip->reg_lock);
1509 snd_pcm_period_elapsed(subs);
1510 spin_lock(&chip->reg_lock);
1514 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1515 (without wrap around) in response to volume button presses and then
1516 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1517 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1518 static void snd_m3_update_hw_volume(struct work_struct *work)
1520 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1523 /* Figure out which volume control button was pushed,
1524 based on differences from the default register
1526 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1528 /* Reset the volume counters to 4. Tests on the allegro integrated
1529 into a Compaq N600C laptop, have revealed that:
1530 1) Writing any value will result in the 2 counters being reset to
1531 4 so writing 0x88 is not strictly necessary
1532 2) Writing to any of the 4 involved registers will reset all 4
1533 of them (and reading them always returns the same value for all
1535 It could be that a maestro deviates from this, so leave the code
1537 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1538 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1539 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1540 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1542 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1543 mistaking them for a mute button press. */
1544 if (chip->in_suspend)
1547 #ifndef CONFIG_SND_MAESTRO3_INPUT
1548 if (!chip->master_switch || !chip->master_volume)
1551 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1554 /* The counters have not changed, yet we've received a HV
1555 interrupt. According to tests run by various people this
1556 happens when pressing the mute button. */
1560 /* counters increased by 1 -> volume up */
1561 if ((val & 0x7f) > 0)
1563 if ((val & 0x7f00) > 0)
1567 /* counters decreased by 1 -> volume down */
1568 if ((val & 0x7f) < 0x1f)
1570 if ((val & 0x7f00) < 0x1f00)
1574 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1575 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1576 &chip->master_switch->id);
1578 if (!chip->input_dev)
1584 /* The counters have not changed, yet we've received a HV
1585 interrupt. According to tests run by various people this
1586 happens when pressing the mute button. */
1590 /* counters increased by 1 -> volume up */
1594 /* counters decreased by 1 -> volume down */
1595 val = KEY_VOLUMEDOWN;
1600 input_report_key(chip->input_dev, val, 1);
1601 input_sync(chip->input_dev);
1602 input_report_key(chip->input_dev, val, 0);
1603 input_sync(chip->input_dev);
1608 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1610 struct snd_m3 *chip = dev_id;
1614 status = inb(chip->iobase + HOST_INT_STATUS);
1619 if (status & HV_INT_PENDING)
1620 schedule_work(&chip->hwvol_work);
1623 * ack an assp int if its running
1624 * and has an int pending
1626 if (status & ASSP_INT_PENDING) {
1627 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1628 if (!(ctl & STOP_ASSP_CLOCK)) {
1629 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1630 if (ctl & DSP2HOST_REQ_TIMER) {
1631 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1632 /* update adc/dac info if it was a timer int */
1633 spin_lock(&chip->reg_lock);
1634 for (i = 0; i < chip->num_substreams; i++) {
1635 struct m3_dma *s = &chip->substreams[i];
1637 snd_m3_update_ptr(chip, s);
1639 spin_unlock(&chip->reg_lock);
1644 #if 0 /* TODO: not supported yet */
1645 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1646 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1650 outb(status, chip->iobase + HOST_INT_STATUS);
1659 static const struct snd_pcm_hardware snd_m3_playback =
1661 .info = (SNDRV_PCM_INFO_MMAP |
1662 SNDRV_PCM_INFO_INTERLEAVED |
1663 SNDRV_PCM_INFO_MMAP_VALID |
1664 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1665 /*SNDRV_PCM_INFO_PAUSE |*/
1666 SNDRV_PCM_INFO_RESUME),
1667 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1668 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1673 .buffer_bytes_max = (512*1024),
1674 .period_bytes_min = 64,
1675 .period_bytes_max = (512*1024),
1677 .periods_max = 1024,
1680 static const struct snd_pcm_hardware snd_m3_capture =
1682 .info = (SNDRV_PCM_INFO_MMAP |
1683 SNDRV_PCM_INFO_INTERLEAVED |
1684 SNDRV_PCM_INFO_MMAP_VALID |
1685 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1686 /*SNDRV_PCM_INFO_PAUSE |*/
1687 SNDRV_PCM_INFO_RESUME),
1688 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1689 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1694 .buffer_bytes_max = (512*1024),
1695 .period_bytes_min = 64,
1696 .period_bytes_max = (512*1024),
1698 .periods_max = 1024,
1706 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1711 spin_lock_irq(&chip->reg_lock);
1712 for (i = 0; i < chip->num_substreams; i++) {
1713 s = &chip->substreams[i];
1717 spin_unlock_irq(&chip->reg_lock);
1722 spin_unlock_irq(&chip->reg_lock);
1724 subs->runtime->private_data = s;
1725 s->substream = subs;
1727 /* set list owners */
1728 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1729 s->index_list[0] = &chip->mixer_list;
1731 s->index_list[0] = &chip->adc1_list;
1732 s->index_list[1] = &chip->msrc_list;
1733 s->index_list[2] = &chip->dma_list;
1739 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1741 struct m3_dma *s = subs->runtime->private_data;
1744 return; /* not opened properly */
1746 spin_lock_irq(&chip->reg_lock);
1747 if (s->substream && s->running)
1748 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1750 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1751 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1752 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1757 spin_unlock_irq(&chip->reg_lock);
1761 snd_m3_playback_open(struct snd_pcm_substream *subs)
1763 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1764 struct snd_pcm_runtime *runtime = subs->runtime;
1767 err = snd_m3_substream_open(chip, subs);
1771 runtime->hw = snd_m3_playback;
1777 snd_m3_playback_close(struct snd_pcm_substream *subs)
1779 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1781 snd_m3_substream_close(chip, subs);
1786 snd_m3_capture_open(struct snd_pcm_substream *subs)
1788 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1789 struct snd_pcm_runtime *runtime = subs->runtime;
1792 err = snd_m3_substream_open(chip, subs);
1796 runtime->hw = snd_m3_capture;
1802 snd_m3_capture_close(struct snd_pcm_substream *subs)
1804 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1806 snd_m3_substream_close(chip, subs);
1811 * create pcm instance
1814 static const struct snd_pcm_ops snd_m3_playback_ops = {
1815 .open = snd_m3_playback_open,
1816 .close = snd_m3_playback_close,
1817 .hw_params = snd_m3_pcm_hw_params,
1818 .hw_free = snd_m3_pcm_hw_free,
1819 .prepare = snd_m3_pcm_prepare,
1820 .trigger = snd_m3_pcm_trigger,
1821 .pointer = snd_m3_pcm_pointer,
1824 static const struct snd_pcm_ops snd_m3_capture_ops = {
1825 .open = snd_m3_capture_open,
1826 .close = snd_m3_capture_close,
1827 .hw_params = snd_m3_pcm_hw_params,
1828 .hw_free = snd_m3_pcm_hw_free,
1829 .prepare = snd_m3_pcm_prepare,
1830 .trigger = snd_m3_pcm_trigger,
1831 .pointer = snd_m3_pcm_pointer,
1835 snd_m3_pcm(struct snd_m3 * chip, int device)
1837 struct snd_pcm *pcm;
1840 err = snd_pcm_new(chip->card, chip->card->driver, device,
1841 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1845 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1846 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1848 pcm->private_data = chip;
1849 pcm->info_flags = 0;
1850 strcpy(pcm->name, chip->card->driver);
1853 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1854 &chip->pci->dev, 64*1024, 64*1024);
1865 * Wait for the ac97 serial bus to be free.
1866 * return nonzero if the bus is still busy.
1868 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1873 if (! (snd_m3_inb(chip, 0x30) & 1))
1878 dev_err(chip->card->dev, "ac97 serial bus busy\n");
1882 static unsigned short
1883 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1885 struct snd_m3 *chip = ac97->private_data;
1886 unsigned short data = 0xffff;
1888 if (snd_m3_ac97_wait(chip))
1890 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1891 if (snd_m3_ac97_wait(chip))
1893 data = snd_m3_inw(chip, CODEC_DATA);
1899 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1901 struct snd_m3 *chip = ac97->private_data;
1903 if (snd_m3_ac97_wait(chip))
1905 snd_m3_outw(chip, val, CODEC_DATA);
1906 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1908 * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1909 * until the MASTER volume or mute is touched (alsactl restore does not
1912 if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1913 snd_m3_ac97_wait(chip);
1914 snd_m3_outw(chip, val, CODEC_DATA);
1915 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1920 static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1922 int io = chip->iobase;
1925 isremote = isremote ? 1 : 0;
1927 tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1928 /* enable dock on Dell Latitude C810 */
1929 if (chip->pci->subsystem_vendor == 0x1028 &&
1930 chip->pci->subsystem_device == 0x00e5)
1931 tmp |= M3I_DOCK_ENABLE;
1932 outw(tmp | isremote, io + RING_BUS_CTRL_B);
1933 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1934 io + SDO_OUT_DEST_CTRL);
1935 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1936 io + SDO_IN_DEST_CTRL);
1940 * hack, returns non zero on err
1942 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1946 if (snd_m3_ac97_wait(chip))
1949 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1951 if (snd_m3_ac97_wait(chip))
1954 ret = snd_m3_inw(chip, 0x32);
1956 return (ret == 0) || (ret == 0xffff);
1959 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1962 int delay1 = 0, delay2 = 0, i;
1963 int io = chip->iobase;
1965 if (chip->allegro_flag) {
1967 * the onboard codec on the allegro seems
1968 * to want to wait a very long time before
1969 * coming back to life
1979 for (i = 0; i < 5; i++) {
1980 dir = inw(io + GPIO_DIRECTION);
1981 if (!chip->irda_workaround)
1982 dir |= 0x10; /* assuming pci bus master? */
1984 snd_m3_remote_codec_config(chip, 0);
1986 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1989 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1990 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1991 outw(0, io + GPIO_DATA);
1992 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1994 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
1996 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1998 /* ok, bring back the ac-link */
1999 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2000 outw(~0, io + GPIO_MASK);
2002 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2004 if (! snd_m3_try_read_vendor(chip))
2010 dev_dbg(chip->card->dev,
2011 "retrying codec reset with delays of %d and %d ms\n",
2016 /* more gung-ho reset that doesn't
2017 * seem to work anywhere :)
2019 tmp = inw(io + RING_BUS_CTRL_A);
2020 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2022 outw(tmp, io + RING_BUS_CTRL_A);
2027 static int snd_m3_mixer(struct snd_m3 *chip)
2029 struct snd_ac97_bus *pbus;
2030 struct snd_ac97_template ac97;
2031 #ifndef CONFIG_SND_MAESTRO3_INPUT
2032 struct snd_ctl_elem_id elem_id;
2035 static const struct snd_ac97_bus_ops ops = {
2036 .write = snd_m3_ac97_write,
2037 .read = snd_m3_ac97_read,
2040 err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
2044 memset(&ac97, 0, sizeof(ac97));
2045 ac97.private_data = chip;
2046 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
2050 /* seems ac97 PCM needs initialization.. hack hack.. */
2051 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2052 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2053 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2055 #ifndef CONFIG_SND_MAESTRO3_INPUT
2056 memset(&elem_id, 0, sizeof(elem_id));
2057 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2058 strcpy(elem_id.name, "Master Playback Switch");
2059 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2060 memset(&elem_id, 0, sizeof(elem_id));
2061 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2062 strcpy(elem_id.name, "Master Playback Volume");
2063 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2074 #define MINISRC_LPF_LEN 10
2075 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2076 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2077 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2080 static void snd_m3_assp_init(struct snd_m3 *chip)
2085 /* zero kernel data */
2086 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2087 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2088 KDATA_BASE_ADDR + i, 0);
2090 /* zero mixer data? */
2091 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2092 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2093 KDATA_BASE_ADDR2 + i, 0);
2095 /* init dma pointer */
2096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2100 /* write kernel into code memory.. */
2101 data = (const __le16 *)chip->assp_kernel_image->data;
2102 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2103 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2104 REV_B_CODE_MEMORY_BEGIN + i,
2105 le16_to_cpu(data[i]));
2109 * We only have this one client and we know that 0x400
2110 * is free in our kernel's mem map, so lets just
2111 * drop it there. It seems that the minisrc doesn't
2112 * need vectors, so we won't bother with them..
2114 data = (const __le16 *)chip->assp_minisrc_image->data;
2115 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2116 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2117 0x400 + i, le16_to_cpu(data[i]));
2121 * write the coefficients for the low pass filter?
2123 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2124 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2125 0x400 + MINISRC_COEF_LOC + i,
2129 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2130 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2134 * the minisrc is the only thing on
2137 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2142 * init the mixer number..
2145 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2146 KDATA_MIXER_TASK_NUMBER,0);
2149 * EXTREME KERNEL MASTER VOLUME
2151 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2152 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2156 chip->mixer_list.curlen = 0;
2157 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2158 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2159 chip->adc1_list.curlen = 0;
2160 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2161 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2162 chip->dma_list.curlen = 0;
2163 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2164 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2165 chip->msrc_list.curlen = 0;
2166 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2167 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2171 static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2173 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2174 MINISRC_IN_BUFFER_SIZE / 2 +
2175 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2179 * the revb memory map has 0x1100 through 0x1c00
2184 * align instance address to 256 bytes so that its
2185 * shifted list address is aligned.
2186 * list address = (mem address >> 1) >> 7;
2188 data_bytes = ALIGN(data_bytes, 256);
2189 address = 0x1100 + ((data_bytes/2) * index);
2191 if ((address + (data_bytes/2)) >= 0x1c00) {
2192 dev_err(chip->card->dev,
2193 "no memory for %d bytes at ind %d (addr 0x%x)\n",
2194 data_bytes, index, address);
2199 s->inst.code = 0x400;
2200 s->inst.data = address;
2202 for (i = data_bytes / 2; i > 0; address++, i--) {
2203 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2212 * this works for the reference board, have to find
2215 * this needs more magic for 4 speaker, but..
2218 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2220 int io = chip->iobase;
2223 if (! chip->external_amp)
2226 polarity = enable ? 0 : 1;
2227 polarity = polarity << chip->amp_gpio;
2228 gpo = 1 << chip->amp_gpio;
2230 outw(~gpo, io + GPIO_MASK);
2232 outw(inw(io + GPIO_DIRECTION) | gpo,
2233 io + GPIO_DIRECTION);
2235 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2238 outw(0xffff, io + GPIO_MASK);
2242 snd_m3_hv_init(struct snd_m3 *chip)
2244 unsigned long io = chip->iobase;
2245 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2247 if (!chip->is_omnibook)
2251 * Volume buttons on some HP OmniBook laptops
2252 * require some GPIO magic to work correctly.
2254 outw(0xffff, io + GPIO_MASK);
2255 outw(0x0000, io + GPIO_DATA);
2257 outw(~val, io + GPIO_MASK);
2258 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2259 outw(val, io + GPIO_MASK);
2261 outw(0xffff, io + GPIO_MASK);
2265 snd_m3_chip_init(struct snd_m3 *chip)
2267 struct pci_dev *pcidev = chip->pci;
2268 unsigned long io = chip->iobase;
2271 u8 t; /* makes as much sense as 'n', no? */
2273 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2274 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2275 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2277 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2279 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2280 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2281 n |= chip->hv_config;
2282 /* For some reason we must always use reduced debounce. */
2283 n |= REDUCED_DEBOUNCE;
2284 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2285 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2287 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2288 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2289 n &= ~INT_CLK_SELECT;
2290 if (!chip->allegro_flag) {
2291 n &= ~INT_CLK_MULT_ENABLE;
2292 n |= INT_CLK_SRC_NOT_PCI;
2294 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2295 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2297 if (chip->allegro_flag) {
2298 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2299 n |= IN_CLK_12MHZ_SELECT;
2300 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2303 t = inb(chip->iobase + ASSP_CONTROL_A);
2304 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2305 t |= ASSP_CLK_49MHZ_SELECT;
2306 t |= ASSP_0_WS_ENABLE;
2307 outb(t, chip->iobase + ASSP_CONTROL_A);
2309 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2310 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2312 outb(0x00, io + HARDWARE_VOL_CTRL);
2313 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2314 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2315 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2316 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2322 snd_m3_enable_ints(struct snd_m3 *chip)
2324 unsigned long io = chip->iobase;
2327 /* TODO: MPU401 not supported yet */
2328 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2329 if (chip->hv_config & HV_CTRL_ENABLE)
2330 val |= HV_INT_ENABLE;
2331 outb(val, chip->iobase + HOST_INT_STATUS);
2332 outw(val, io + HOST_INT_CTRL);
2333 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2334 io + ASSP_CONTROL_C);
2341 static void snd_m3_free(struct snd_card *card)
2343 struct snd_m3 *chip = card->private_data;
2347 cancel_work_sync(&chip->hwvol_work);
2349 if (chip->substreams) {
2350 spin_lock_irq(&chip->reg_lock);
2351 for (i = 0; i < chip->num_substreams; i++) {
2352 s = &chip->substreams[i];
2353 /* check surviving pcms; this should not happen though.. */
2354 if (s->substream && s->running)
2355 snd_m3_pcm_stop(chip, s, s->substream);
2357 spin_unlock_irq(&chip->reg_lock);
2360 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2363 #ifdef CONFIG_PM_SLEEP
2364 vfree(chip->suspend_mem);
2366 release_firmware(chip->assp_kernel_image);
2367 release_firmware(chip->assp_minisrc_image);
2374 #ifdef CONFIG_PM_SLEEP
2375 static int m3_suspend(struct device *dev)
2377 struct snd_card *card = dev_get_drvdata(dev);
2378 struct snd_m3 *chip = card->private_data;
2381 if (chip->suspend_mem == NULL)
2384 chip->in_suspend = 1;
2385 cancel_work_sync(&chip->hwvol_work);
2386 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2387 snd_ac97_suspend(chip->ac97);
2389 msleep(10); /* give the assp a chance to idle.. */
2391 snd_m3_assp_halt(chip);
2393 /* save dsp image */
2395 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2396 chip->suspend_mem[dsp_index++] =
2397 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2398 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2399 chip->suspend_mem[dsp_index++] =
2400 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2404 static int m3_resume(struct device *dev)
2406 struct snd_card *card = dev_get_drvdata(dev);
2407 struct snd_m3 *chip = card->private_data;
2410 if (chip->suspend_mem == NULL)
2413 /* first lets just bring everything back. .*/
2414 snd_m3_outw(chip, 0, 0x54);
2415 snd_m3_outw(chip, 0, 0x56);
2417 snd_m3_chip_init(chip);
2418 snd_m3_assp_halt(chip);
2419 snd_m3_ac97_reset(chip);
2421 /* restore dsp image */
2423 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2424 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2425 chip->suspend_mem[dsp_index++]);
2426 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2427 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2428 chip->suspend_mem[dsp_index++]);
2430 /* tell the dma engine to restart itself */
2431 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2432 KDATA_DMA_ACTIVE, 0);
2434 /* restore ac97 registers */
2435 snd_ac97_resume(chip->ac97);
2437 snd_m3_assp_continue(chip);
2438 snd_m3_enable_ints(chip);
2439 snd_m3_amp_enable(chip, 1);
2441 snd_m3_hv_init(chip);
2443 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2444 chip->in_suspend = 0;
2448 static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2449 #define M3_PM_OPS &m3_pm
2451 #define M3_PM_OPS NULL
2452 #endif /* CONFIG_PM_SLEEP */
2454 #ifdef CONFIG_SND_MAESTRO3_INPUT
2455 static int snd_m3_input_register(struct snd_m3 *chip)
2457 struct input_dev *input_dev;
2460 input_dev = devm_input_allocate_device(&chip->pci->dev);
2464 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2465 pci_name(chip->pci));
2467 input_dev->name = chip->card->driver;
2468 input_dev->phys = chip->phys;
2469 input_dev->id.bustype = BUS_PCI;
2470 input_dev->id.vendor = chip->pci->vendor;
2471 input_dev->id.product = chip->pci->device;
2472 input_dev->dev.parent = &chip->pci->dev;
2474 __set_bit(EV_KEY, input_dev->evbit);
2475 __set_bit(KEY_MUTE, input_dev->keybit);
2476 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2477 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2479 err = input_register_device(input_dev);
2483 chip->input_dev = input_dev;
2486 #endif /* CONFIG_INPUT */
2492 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2496 struct snd_m3 *chip = card->private_data;
2498 const struct snd_pci_quirk *quirk;
2500 if (pcim_enable_device(pci))
2503 /* check, if we can restrict PCI DMA transfers to 28 bits */
2504 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) {
2506 "architecture does not support 28bit PCI busmaster DMA\n");
2510 spin_lock_init(&chip->reg_lock);
2512 switch (pci->device) {
2513 case PCI_DEVICE_ID_ESS_ALLEGRO:
2514 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2515 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2516 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2517 chip->allegro_flag = 1;
2524 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2525 card->private_free = snd_m3_free;
2527 chip->external_amp = enable_amp;
2528 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2529 chip->amp_gpio = amp_gpio;
2531 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2533 dev_info(card->dev, "set amp-gpio for '%s'\n",
2534 snd_pci_quirk_name(quirk));
2535 chip->amp_gpio = quirk->value;
2536 } else if (chip->allegro_flag)
2537 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2538 else /* presumably this is for all 'maestro3's.. */
2539 chip->amp_gpio = GPO_EXT_AMP_M3;
2542 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2544 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2545 snd_pci_quirk_name(quirk));
2546 chip->irda_workaround = 1;
2548 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2550 chip->hv_config = quirk->value;
2551 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2552 chip->is_omnibook = 1;
2554 chip->num_substreams = NR_DSPS;
2555 chip->substreams = devm_kcalloc(&pci->dev, chip->num_substreams,
2556 sizeof(struct m3_dma), GFP_KERNEL);
2557 if (!chip->substreams)
2560 err = reject_firmware(&chip->assp_kernel_image,
2561 "/*(DEBLOBBED)*/", &pci->dev);
2565 err = reject_firmware(&chip->assp_minisrc_image,
2566 "/*(DEBLOBBED)*/", &pci->dev);
2570 err = pci_request_regions(pci, card->driver);
2574 chip->iobase = pci_resource_start(pci, 0);
2576 /* just to be sure */
2577 pci_set_master(pci);
2579 snd_m3_chip_init(chip);
2580 snd_m3_assp_halt(chip);
2582 snd_m3_ac97_reset(chip);
2584 snd_m3_amp_enable(chip, 1);
2586 snd_m3_hv_init(chip);
2588 if (devm_request_irq(&pci->dev, pci->irq, snd_m3_interrupt, IRQF_SHARED,
2589 KBUILD_MODNAME, chip)) {
2590 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2593 chip->irq = pci->irq;
2594 card->sync_irq = chip->irq;
2596 #ifdef CONFIG_PM_SLEEP
2598 vmalloc(array_size(sizeof(u16),
2599 REV_B_CODE_MEMORY_LENGTH +
2600 REV_B_DATA_MEMORY_LENGTH));
2601 if (chip->suspend_mem == NULL)
2602 dev_warn(card->dev, "can't allocate apm buffer\n");
2605 err = snd_m3_mixer(chip);
2609 for (i = 0; i < chip->num_substreams; i++) {
2610 struct m3_dma *s = &chip->substreams[i];
2611 err = snd_m3_assp_client_init(chip, s, i);
2616 err = snd_m3_pcm(chip, 0);
2620 #ifdef CONFIG_SND_MAESTRO3_INPUT
2621 if (chip->hv_config & HV_CTRL_ENABLE) {
2622 err = snd_m3_input_register(chip);
2625 "Input device registration failed with error %i",
2630 snd_m3_enable_ints(chip);
2631 snd_m3_assp_continue(chip);
2639 __snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2642 struct snd_card *card;
2643 struct snd_m3 *chip;
2646 /* don't pick up modems */
2647 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2650 if (dev >= SNDRV_CARDS)
2657 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2658 sizeof(*chip), &card);
2661 chip = card->private_data;
2663 switch (pci->device) {
2664 case PCI_DEVICE_ID_ESS_ALLEGRO:
2665 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2666 strcpy(card->driver, "Allegro");
2668 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2669 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2670 strcpy(card->driver, "Canyon3D-2");
2673 strcpy(card->driver, "Maestro3");
2677 err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev]);
2681 sprintf(card->shortname, "ESS %s PCI", card->driver);
2682 sprintf(card->longname, "%s at 0x%lx, irq %d",
2683 card->shortname, chip->iobase, chip->irq);
2685 err = snd_card_register(card);
2689 #if 0 /* TODO: not supported yet */
2690 /* TODO enable MIDI IRQ and I/O */
2691 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2692 chip->iobase + MPU401_DATA_PORT,
2693 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2696 dev_warn(card->dev, "no MIDI support.\n");
2699 pci_set_drvdata(pci, card);
2705 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2707 return snd_card_free_on_error(&pci->dev, __snd_m3_probe(pci, pci_id));
2710 static struct pci_driver m3_driver = {
2711 .name = KBUILD_MODNAME,
2712 .id_table = snd_m3_ids,
2713 .probe = snd_m3_probe,
2719 module_pci_driver(m3_driver);