1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
4 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
5 * Takashi Iwai <tiwai@suse.de>
7 * Most of the hardware init stuffs are based on maestro3 driver for
8 * OSS/Free by Zach Brown. Many thanks to Zach!
12 * - Fixed deadlock on capture
13 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
16 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
17 #define DRIVER_NAME "Maestro3"
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/module.h>
28 #include <linux/firmware.h>
29 #include <linux/input.h>
30 #include <sound/core.h>
31 #include <sound/info.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/mpu401.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/initval.h>
37 #include <asm/byteorder.h>
39 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
40 MODULE_DESCRIPTION("ESS Maestro3 PCI");
41 MODULE_LICENSE("GPL");
42 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
45 "{ESS,Allegro-1 PCI},"
46 "{ESS,Canyon3D-2/LE PCI}}");
49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
51 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
52 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
53 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
55 module_param_array(index, int, NULL, 0444);
56 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
57 module_param_array(id, charp, NULL, 0444);
58 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
59 module_param_array(enable, bool, NULL, 0444);
60 MODULE_PARM_DESC(enable, "Enable this soundcard.");
61 module_param_array(external_amp, bool, NULL, 0444);
62 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
63 module_param_array(amp_gpio, int, NULL, 0444);
64 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
66 #define MAX_PLAYBACKS 2
67 #define MAX_CAPTURES 1
68 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
75 /* Allegro PCI configuration registers */
76 #define PCI_LEGACY_AUDIO_CTRL 0x40
77 #define SOUND_BLASTER_ENABLE 0x00000001
78 #define FM_SYNTHESIS_ENABLE 0x00000002
79 #define GAME_PORT_ENABLE 0x00000004
80 #define MPU401_IO_ENABLE 0x00000008
81 #define MPU401_IRQ_ENABLE 0x00000010
82 #define ALIAS_10BIT_IO 0x00000020
83 #define SB_DMA_MASK 0x000000C0
84 #define SB_DMA_0 0x00000040
85 #define SB_DMA_1 0x00000040
86 #define SB_DMA_R 0x00000080
87 #define SB_DMA_3 0x000000C0
88 #define SB_IRQ_MASK 0x00000700
89 #define SB_IRQ_5 0x00000000
90 #define SB_IRQ_7 0x00000100
91 #define SB_IRQ_9 0x00000200
92 #define SB_IRQ_10 0x00000300
93 #define MIDI_IRQ_MASK 0x00003800
94 #define SERIAL_IRQ_ENABLE 0x00004000
95 #define DISABLE_LEGACY 0x00008000
97 #define PCI_ALLEGRO_CONFIG 0x50
98 #define SB_ADDR_240 0x00000004
99 #define MPU_ADDR_MASK 0x00000018
100 #define MPU_ADDR_330 0x00000000
101 #define MPU_ADDR_300 0x00000008
102 #define MPU_ADDR_320 0x00000010
103 #define MPU_ADDR_340 0x00000018
104 #define USE_PCI_TIMING 0x00000040
105 #define POSTED_WRITE_ENABLE 0x00000080
106 #define DMA_POLICY_MASK 0x00000700
107 #define DMA_DDMA 0x00000000
108 #define DMA_TDMA 0x00000100
109 #define DMA_PCPCI 0x00000200
110 #define DMA_WBDMA16 0x00000400
111 #define DMA_WBDMA4 0x00000500
112 #define DMA_WBDMA2 0x00000600
113 #define DMA_WBDMA1 0x00000700
114 #define DMA_SAFE_GUARD 0x00000800
115 #define HI_PERF_GP_ENABLE 0x00001000
116 #define PIC_SNOOP_MODE_0 0x00002000
117 #define PIC_SNOOP_MODE_1 0x00004000
118 #define SOUNDBLASTER_IRQ_MASK 0x00008000
119 #define RING_IN_ENABLE 0x00010000
120 #define SPDIF_TEST_MODE 0x00020000
121 #define CLK_MULT_MODE_SELECT_2 0x00040000
122 #define EEPROM_WRITE_ENABLE 0x00080000
123 #define CODEC_DIR_IN 0x00100000
124 #define HV_BUTTON_FROM_GD 0x00200000
125 #define REDUCED_DEBOUNCE 0x00400000
126 #define HV_CTRL_ENABLE 0x00800000
127 #define SPDIF_ENABLE 0x01000000
128 #define CLK_DIV_SELECT 0x06000000
129 #define CLK_DIV_BY_48 0x00000000
130 #define CLK_DIV_BY_49 0x02000000
131 #define CLK_DIV_BY_50 0x04000000
132 #define CLK_DIV_RESERVED 0x06000000
133 #define PM_CTRL_ENABLE 0x08000000
134 #define CLK_MULT_MODE_SELECT 0x30000000
135 #define CLK_MULT_MODE_SHIFT 28
136 #define CLK_MULT_MODE_0 0x00000000
137 #define CLK_MULT_MODE_1 0x10000000
138 #define CLK_MULT_MODE_2 0x20000000
139 #define CLK_MULT_MODE_3 0x30000000
140 #define INT_CLK_SELECT 0x40000000
141 #define INT_CLK_MULT_RESET 0x80000000
144 #define INT_CLK_SRC_NOT_PCI 0x00100000
145 #define INT_CLK_MULT_ENABLE 0x80000000
147 #define PCI_ACPI_CONTROL 0x54
148 #define PCI_ACPI_D0 0x00000000
149 #define PCI_ACPI_D1 0xB4F70000
150 #define PCI_ACPI_D2 0xB4F7B4F7
152 #define PCI_USER_CONFIG 0x58
153 #define EXT_PCI_MASTER_ENABLE 0x00000001
154 #define SPDIF_OUT_SELECT 0x00000002
155 #define TEST_PIN_DIR_CTRL 0x00000004
156 #define AC97_CODEC_TEST 0x00000020
157 #define TRI_STATE_BUFFER 0x00000080
158 #define IN_CLK_12MHZ_SELECT 0x00000100
159 #define MULTI_FUNC_DISABLE 0x00000200
160 #define EXT_MASTER_PAIR_SEL 0x00000400
161 #define PCI_MASTER_SUPPORT 0x00000800
162 #define STOP_CLOCK_ENABLE 0x00001000
163 #define EAPD_DRIVE_ENABLE 0x00002000
164 #define REQ_TRI_STATE_ENABLE 0x00004000
165 #define REQ_LOW_ENABLE 0x00008000
166 #define MIDI_1_ENABLE 0x00010000
167 #define MIDI_2_ENABLE 0x00020000
168 #define SB_AUDIO_SYNC 0x00040000
169 #define HV_CTRL_TEST 0x00100000
170 #define SOUNDBLASTER_TEST 0x00400000
172 #define PCI_USER_CONFIG_C 0x5C
174 #define PCI_DDMA_CTRL 0x60
175 #define DDMA_ENABLE 0x00000001
178 /* Allegro registers */
179 #define HOST_INT_CTRL 0x18
180 #define SB_INT_ENABLE 0x0001
181 #define MPU401_INT_ENABLE 0x0002
182 #define ASSP_INT_ENABLE 0x0010
183 #define RING_INT_ENABLE 0x0020
184 #define HV_INT_ENABLE 0x0040
185 #define CLKRUN_GEN_ENABLE 0x0100
186 #define HV_CTRL_TO_PME 0x0400
187 #define SOFTWARE_RESET_ENABLE 0x8000
190 * should be using the above defines, probably.
192 #define REGB_ENABLE_RESET 0x01
193 #define REGB_STOP_CLOCK 0x10
195 #define HOST_INT_STATUS 0x1A
196 #define SB_INT_PENDING 0x01
197 #define MPU401_INT_PENDING 0x02
198 #define ASSP_INT_PENDING 0x10
199 #define RING_INT_PENDING 0x20
200 #define HV_INT_PENDING 0x40
202 #define HARDWARE_VOL_CTRL 0x1B
203 #define SHADOW_MIX_REG_VOICE 0x1C
204 #define HW_VOL_COUNTER_VOICE 0x1D
205 #define SHADOW_MIX_REG_MASTER 0x1E
206 #define HW_VOL_COUNTER_MASTER 0x1F
208 #define CODEC_COMMAND 0x30
209 #define CODEC_READ_B 0x80
211 #define CODEC_STATUS 0x30
212 #define CODEC_BUSY_B 0x01
214 #define CODEC_DATA 0x32
216 #define RING_BUS_CTRL_A 0x36
217 #define RAC_PME_ENABLE 0x0100
218 #define RAC_SDFS_ENABLE 0x0200
219 #define LAC_PME_ENABLE 0x0400
220 #define LAC_SDFS_ENABLE 0x0800
221 #define SERIAL_AC_LINK_ENABLE 0x1000
222 #define IO_SRAM_ENABLE 0x2000
223 #define IIS_INPUT_ENABLE 0x8000
225 #define RING_BUS_CTRL_B 0x38
226 #define SECOND_CODEC_ID_MASK 0x0003
227 #define SPDIF_FUNC_ENABLE 0x0010
228 #define SECOND_AC_ENABLE 0x0020
229 #define SB_MODULE_INTF_ENABLE 0x0040
230 #define SSPE_ENABLE 0x0040
231 #define M3I_DOCK_ENABLE 0x0080
233 #define SDO_OUT_DEST_CTRL 0x3A
234 #define COMMAND_ADDR_OUT 0x0003
235 #define PCM_LR_OUT_LOCAL 0x0000
236 #define PCM_LR_OUT_REMOTE 0x0004
237 #define PCM_LR_OUT_MUTE 0x0008
238 #define PCM_LR_OUT_BOTH 0x000C
239 #define LINE1_DAC_OUT_LOCAL 0x0000
240 #define LINE1_DAC_OUT_REMOTE 0x0010
241 #define LINE1_DAC_OUT_MUTE 0x0020
242 #define LINE1_DAC_OUT_BOTH 0x0030
243 #define PCM_CLS_OUT_LOCAL 0x0000
244 #define PCM_CLS_OUT_REMOTE 0x0040
245 #define PCM_CLS_OUT_MUTE 0x0080
246 #define PCM_CLS_OUT_BOTH 0x00C0
247 #define PCM_RLF_OUT_LOCAL 0x0000
248 #define PCM_RLF_OUT_REMOTE 0x0100
249 #define PCM_RLF_OUT_MUTE 0x0200
250 #define PCM_RLF_OUT_BOTH 0x0300
251 #define LINE2_DAC_OUT_LOCAL 0x0000
252 #define LINE2_DAC_OUT_REMOTE 0x0400
253 #define LINE2_DAC_OUT_MUTE 0x0800
254 #define LINE2_DAC_OUT_BOTH 0x0C00
255 #define HANDSET_OUT_LOCAL 0x0000
256 #define HANDSET_OUT_REMOTE 0x1000
257 #define HANDSET_OUT_MUTE 0x2000
258 #define HANDSET_OUT_BOTH 0x3000
259 #define IO_CTRL_OUT_LOCAL 0x0000
260 #define IO_CTRL_OUT_REMOTE 0x4000
261 #define IO_CTRL_OUT_MUTE 0x8000
262 #define IO_CTRL_OUT_BOTH 0xC000
264 #define SDO_IN_DEST_CTRL 0x3C
265 #define STATUS_ADDR_IN 0x0003
266 #define PCM_LR_IN_LOCAL 0x0000
267 #define PCM_LR_IN_REMOTE 0x0004
268 #define PCM_LR_RESERVED 0x0008
269 #define PCM_LR_IN_BOTH 0x000C
270 #define LINE1_ADC_IN_LOCAL 0x0000
271 #define LINE1_ADC_IN_REMOTE 0x0010
272 #define LINE1_ADC_IN_MUTE 0x0020
273 #define MIC_ADC_IN_LOCAL 0x0000
274 #define MIC_ADC_IN_REMOTE 0x0040
275 #define MIC_ADC_IN_MUTE 0x0080
276 #define LINE2_DAC_IN_LOCAL 0x0000
277 #define LINE2_DAC_IN_REMOTE 0x0400
278 #define LINE2_DAC_IN_MUTE 0x0800
279 #define HANDSET_IN_LOCAL 0x0000
280 #define HANDSET_IN_REMOTE 0x1000
281 #define HANDSET_IN_MUTE 0x2000
282 #define IO_STATUS_IN_LOCAL 0x0000
283 #define IO_STATUS_IN_REMOTE 0x4000
285 #define SPDIF_IN_CTRL 0x3E
286 #define SPDIF_IN_ENABLE 0x0001
288 #define GPIO_DATA 0x60
289 #define GPIO_DATA_MASK 0x0FFF
290 #define GPIO_HV_STATUS 0x3000
291 #define GPIO_PME_STATUS 0x4000
293 #define GPIO_MASK 0x64
294 #define GPIO_DIRECTION 0x68
295 #define GPO_PRIMARY_AC97 0x0001
296 #define GPI_LINEOUT_SENSE 0x0004
297 #define GPO_SECONDARY_AC97 0x0008
298 #define GPI_VOL_DOWN 0x0010
299 #define GPI_VOL_UP 0x0020
300 #define GPI_IIS_CLK 0x0040
301 #define GPI_IIS_LRCLK 0x0080
302 #define GPI_IIS_DATA 0x0100
303 #define GPI_DOCKING_STATUS 0x0100
304 #define GPI_HEADPHONE_SENSE 0x0200
305 #define GPO_EXT_AMP_SHUTDOWN 0x1000
307 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
308 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
311 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
313 #define ASSP_INDEX_PORT 0x80
314 #define ASSP_MEMORY_PORT 0x82
315 #define ASSP_DATA_PORT 0x84
317 #define MPU401_DATA_PORT 0x98
318 #define MPU401_STATUS_PORT 0x99
320 #define CLK_MULT_DATA_PORT 0x9C
322 #define ASSP_CONTROL_A 0xA2
323 #define ASSP_0_WS_ENABLE 0x01
324 #define ASSP_CTRL_A_RESERVED1 0x02
325 #define ASSP_CTRL_A_RESERVED2 0x04
326 #define ASSP_CLK_49MHZ_SELECT 0x08
327 #define FAST_PLU_ENABLE 0x10
328 #define ASSP_CTRL_A_RESERVED3 0x20
329 #define DSP_CLK_36MHZ_SELECT 0x40
331 #define ASSP_CONTROL_B 0xA4
332 #define RESET_ASSP 0x00
333 #define RUN_ASSP 0x01
334 #define ENABLE_ASSP_CLOCK 0x00
335 #define STOP_ASSP_CLOCK 0x10
336 #define RESET_TOGGLE 0x40
338 #define ASSP_CONTROL_C 0xA6
339 #define ASSP_HOST_INT_ENABLE 0x01
340 #define FM_ADDR_REMAP_DISABLE 0x02
341 #define HOST_WRITE_PORT_ENABLE 0x08
343 #define ASSP_HOST_INT_STATUS 0xAC
344 #define DSP2HOST_REQ_PIORECORD 0x01
345 #define DSP2HOST_REQ_I2SRATE 0x02
346 #define DSP2HOST_REQ_TIMER 0x04
351 #define DSP_PORT_TIMER_COUNT 0x06
353 #define DSP_PORT_MEMORY_INDEX 0x80
355 #define DSP_PORT_MEMORY_TYPE 0x82
356 #define MEMTYPE_INTERNAL_CODE 0x0002
357 #define MEMTYPE_INTERNAL_DATA 0x0003
358 #define MEMTYPE_MASK 0x0003
360 #define DSP_PORT_MEMORY_DATA 0x84
362 #define DSP_PORT_CONTROL_REG_A 0xA2
363 #define DSP_PORT_CONTROL_REG_B 0xA4
364 #define DSP_PORT_CONTROL_REG_C 0xA6
366 #define REV_A_CODE_MEMORY_BEGIN 0x0000
367 #define REV_A_CODE_MEMORY_END 0x0FFF
368 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
369 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
371 #define REV_B_CODE_MEMORY_BEGIN 0x0000
372 #define REV_B_CODE_MEMORY_END 0x0BFF
373 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
374 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
376 #define REV_A_DATA_MEMORY_BEGIN 0x1000
377 #define REV_A_DATA_MEMORY_END 0x2FFF
378 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
379 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
381 #define REV_B_DATA_MEMORY_BEGIN 0x1000
382 #define REV_B_DATA_MEMORY_END 0x2BFF
383 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
384 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
387 #define NUM_UNITS_KERNEL_CODE 16
388 #define NUM_UNITS_KERNEL_DATA 2
390 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
391 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
397 #define DP_SHIFT_COUNT 7
399 #define KDATA_BASE_ADDR 0x1000
400 #define KDATA_BASE_ADDR2 0x1080
402 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
403 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
404 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
405 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
406 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
407 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
408 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
409 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
410 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
412 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
413 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
415 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
416 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
417 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
418 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
419 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
420 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
421 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
422 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
423 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
424 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
426 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
427 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
429 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
430 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
432 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
433 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
435 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
436 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
437 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
439 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
440 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
441 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
442 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
443 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
445 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
446 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
447 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
449 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
450 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
451 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
453 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
454 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
455 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
456 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
457 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
458 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
459 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
460 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
461 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
462 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
464 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
465 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
466 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
468 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
469 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
471 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
472 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
473 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
475 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
476 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
477 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
478 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
479 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
480 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
482 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
483 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
484 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
485 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
486 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
487 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
489 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
490 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
491 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
492 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
493 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
494 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
496 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
497 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
498 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
499 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
501 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
502 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
504 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
505 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
507 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
508 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
509 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
510 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
511 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
513 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
514 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
516 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
517 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
518 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
520 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
521 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
523 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
525 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
526 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
527 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
528 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
529 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
530 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
531 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
532 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
533 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
534 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
535 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
536 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
538 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
539 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
540 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
541 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
543 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
544 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
546 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
547 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
548 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
549 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
551 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
552 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
553 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
554 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
555 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
558 * second 'segment' (?) reserved for mixer
562 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
563 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
564 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
565 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
566 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
567 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
568 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
569 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
570 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
571 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
572 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
573 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
574 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
575 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
576 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
577 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
579 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
580 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
581 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
582 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
583 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
584 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
585 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
586 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
587 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
588 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
589 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
591 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
592 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
593 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
594 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
595 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
596 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
598 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
599 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
600 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
601 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
604 * client data area offsets
606 #define CDATA_INSTANCE_READY 0x00
608 #define CDATA_HOST_SRC_ADDRL 0x01
609 #define CDATA_HOST_SRC_ADDRH 0x02
610 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
611 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
612 #define CDATA_HOST_SRC_CURRENTL 0x05
613 #define CDATA_HOST_SRC_CURRENTH 0x06
615 #define CDATA_IN_BUF_CONNECT 0x07
616 #define CDATA_OUT_BUF_CONNECT 0x08
618 #define CDATA_IN_BUF_BEGIN 0x09
619 #define CDATA_IN_BUF_END_PLUS_1 0x0A
620 #define CDATA_IN_BUF_HEAD 0x0B
621 #define CDATA_IN_BUF_TAIL 0x0C
622 #define CDATA_OUT_BUF_BEGIN 0x0D
623 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
624 #define CDATA_OUT_BUF_HEAD 0x0F
625 #define CDATA_OUT_BUF_TAIL 0x10
627 #define CDATA_DMA_CONTROL 0x11
628 #define CDATA_RESERVED 0x12
630 #define CDATA_FREQUENCY 0x13
631 #define CDATA_LEFT_VOLUME 0x14
632 #define CDATA_RIGHT_VOLUME 0x15
633 #define CDATA_LEFT_SUR_VOL 0x16
634 #define CDATA_RIGHT_SUR_VOL 0x17
636 #define CDATA_HEADER_LEN 0x18
638 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
639 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
640 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
641 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
642 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
643 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
644 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
645 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
647 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
648 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
649 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
650 #define MINISRC_BIQUAD_STAGE 2
651 #define MINISRC_COEF_LOC 0x175
653 #define DMACONTROL_BLOCK_MASK 0x000F
654 #define DMAC_BLOCK0_SELECTOR 0x0000
655 #define DMAC_BLOCK1_SELECTOR 0x0001
656 #define DMAC_BLOCK2_SELECTOR 0x0002
657 #define DMAC_BLOCK3_SELECTOR 0x0003
658 #define DMAC_BLOCK4_SELECTOR 0x0004
659 #define DMAC_BLOCK5_SELECTOR 0x0005
660 #define DMAC_BLOCK6_SELECTOR 0x0006
661 #define DMAC_BLOCK7_SELECTOR 0x0007
662 #define DMAC_BLOCK8_SELECTOR 0x0008
663 #define DMAC_BLOCK9_SELECTOR 0x0009
664 #define DMAC_BLOCKA_SELECTOR 0x000A
665 #define DMAC_BLOCKB_SELECTOR 0x000B
666 #define DMAC_BLOCKC_SELECTOR 0x000C
667 #define DMAC_BLOCKD_SELECTOR 0x000D
668 #define DMAC_BLOCKE_SELECTOR 0x000E
669 #define DMAC_BLOCKF_SELECTOR 0x000F
670 #define DMACONTROL_PAGE_MASK 0x00F0
671 #define DMAC_PAGE0_SELECTOR 0x0030
672 #define DMAC_PAGE1_SELECTOR 0x0020
673 #define DMAC_PAGE2_SELECTOR 0x0010
674 #define DMAC_PAGE3_SELECTOR 0x0000
675 #define DMACONTROL_AUTOREPEAT 0x1000
676 #define DMACONTROL_STOPPED 0x2000
677 #define DMACONTROL_DIRECTION 0x0100
680 * an arbitrary volume we set the internal
681 * volume settings to so that the ac97 volume
682 * range is a little less insane. 0x7fff is
685 #define ARB_VOLUME ( 0x6800 )
699 struct snd_pcm_substream *substream;
701 struct assp_instance {
702 unsigned short code, data;
708 unsigned long buffer_addr;
715 struct m3_list *index_list[3];
719 struct list_head list;
725 struct snd_card *card;
727 unsigned long iobase;
730 unsigned int allegro_flag : 1;
732 struct snd_ac97 *ac97;
741 struct m3_list msrc_list;
742 struct m3_list mixer_list;
743 struct m3_list adc1_list;
744 struct m3_list dma_list;
746 /* for storing reset state..*/
750 int amp_gpio; /* gpio pin # for external amp, -1 = default */
751 unsigned int hv_config; /* hardware-volume config bits */
752 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
753 (e.g. for IrDA on Dell Inspirons) */
754 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
757 struct snd_rawmidi *rmidi;
761 struct m3_dma *substreams;
765 #ifdef CONFIG_SND_MAESTRO3_INPUT
766 struct input_dev *input_dev;
767 char phys[64]; /* physical device path */
769 struct snd_kcontrol *master_switch;
770 struct snd_kcontrol *master_volume;
772 struct work_struct hwvol_work;
774 unsigned int in_suspend;
776 #ifdef CONFIG_PM_SLEEP
780 const struct firmware *assp_kernel_image;
781 const struct firmware *assp_minisrc_image;
787 static const struct pci_device_id snd_m3_ids[] = {
788 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
789 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
790 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
791 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
792 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
793 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
794 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
795 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
796 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
797 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
798 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
799 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
800 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
801 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
802 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
803 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
807 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
809 static struct snd_pci_quirk m3_amp_quirk_list[] = {
810 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
811 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
812 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
813 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
814 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
818 static struct snd_pci_quirk m3_irda_quirk_list[] = {
819 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
820 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
821 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
825 /* hardware volume quirks */
826 static struct snd_pci_quirk m3_hv_quirk_list[] = {
828 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
829 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
830 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
831 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
832 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
833 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
834 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
835 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
836 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
837 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
838 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
839 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
840 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
841 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
842 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
843 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
844 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
848 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
849 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
850 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
851 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
852 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
853 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
854 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
855 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
856 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
857 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
858 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
859 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
860 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
861 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
862 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
863 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
864 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
865 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
866 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
867 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
868 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
869 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
870 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
871 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
872 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
873 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
874 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
875 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
876 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
877 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
878 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
879 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
880 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
881 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
883 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
884 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
885 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
886 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
887 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
888 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
889 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
890 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
891 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
892 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
893 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
894 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
895 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
896 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
897 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
898 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
899 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
903 /* HP Omnibook quirks */
904 static struct snd_pci_quirk m3_omnibook_quirk_list[] = {
905 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
906 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
914 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
916 outw(value, chip->iobase + reg);
919 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
921 return inw(chip->iobase + reg);
924 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
926 outb(value, chip->iobase + reg);
929 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
931 return inb(chip->iobase + reg);
935 * access 16bit words to the code or data regions of the dsp's memory.
936 * index addresses 16bit words.
938 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
940 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
941 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
942 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
945 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
947 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
948 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
949 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
952 static void snd_m3_assp_halt(struct snd_m3 *chip)
954 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
956 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
959 static void snd_m3_assp_continue(struct snd_m3 *chip)
961 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
966 * This makes me sad. the maestro3 has lists
967 * internally that must be packed.. 0 terminates,
968 * apparently, or maybe all unused entries have
969 * to be 0, the lists have static lengths set
970 * by the binary code images.
973 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
975 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
976 list->mem_addr + list->curlen,
978 return list->curlen++;
981 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
984 int lastindex = list->curlen - 1;
986 if (index != lastindex) {
987 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
988 list->mem_addr + lastindex);
989 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
990 list->mem_addr + index,
994 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
995 list->mem_addr + lastindex,
1001 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1003 chip->timer_users++;
1004 if (chip->timer_users != 1)
1007 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1008 KDATA_TIMER_COUNT_RELOAD,
1011 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1012 KDATA_TIMER_COUNT_CURRENT,
1016 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1020 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1022 chip->timer_users--;
1023 if (chip->timer_users > 0)
1026 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1027 KDATA_TIMER_COUNT_RELOAD,
1030 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1031 KDATA_TIMER_COUNT_CURRENT,
1035 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1043 /* spinlock held! */
1044 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1045 struct snd_pcm_substream *subs)
1050 snd_m3_inc_timer_users(chip);
1051 switch (subs->stream) {
1052 case SNDRV_PCM_STREAM_PLAYBACK:
1053 chip->dacs_active++;
1054 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055 s->inst.data + CDATA_INSTANCE_READY, 1);
1056 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1057 KDATA_MIXER_TASK_NUMBER,
1060 case SNDRV_PCM_STREAM_CAPTURE:
1061 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1062 KDATA_ADC1_REQUEST, 1);
1063 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1064 s->inst.data + CDATA_INSTANCE_READY, 1);
1070 /* spinlock held! */
1071 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1072 struct snd_pcm_substream *subs)
1077 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1078 s->inst.data + CDATA_INSTANCE_READY, 0);
1079 snd_m3_dec_timer_users(chip);
1080 switch (subs->stream) {
1081 case SNDRV_PCM_STREAM_PLAYBACK:
1082 chip->dacs_active--;
1083 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084 KDATA_MIXER_TASK_NUMBER,
1087 case SNDRV_PCM_STREAM_CAPTURE:
1088 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1089 KDATA_ADC1_REQUEST, 0);
1096 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1098 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1099 struct m3_dma *s = subs->runtime->private_data;
1105 spin_lock(&chip->reg_lock);
1107 case SNDRV_PCM_TRIGGER_START:
1108 case SNDRV_PCM_TRIGGER_RESUME:
1113 err = snd_m3_pcm_start(chip, s, subs);
1116 case SNDRV_PCM_TRIGGER_STOP:
1117 case SNDRV_PCM_TRIGGER_SUSPEND:
1119 err = 0; /* should return error? */
1122 err = snd_m3_pcm_stop(chip, s, subs);
1126 spin_unlock(&chip->reg_lock);
1134 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1136 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1137 struct snd_pcm_runtime *runtime = subs->runtime;
1139 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1140 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1141 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1143 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1144 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1146 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1147 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1149 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1150 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1154 #define LO(x) ((x) & 0xffff)
1155 #define HI(x) LO((x) >> 16)
1157 /* host dma buffer pointers */
1158 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1159 s->inst.data + CDATA_HOST_SRC_ADDRL,
1160 LO(s->buffer_addr));
1162 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1163 s->inst.data + CDATA_HOST_SRC_ADDRH,
1164 HI(s->buffer_addr));
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1168 LO(s->buffer_addr + s->dma_size));
1170 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1171 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1172 HI(s->buffer_addr + s->dma_size));
1174 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1175 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1176 LO(s->buffer_addr));
1178 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1179 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1180 HI(s->buffer_addr));
1186 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1187 s->inst.data + CDATA_IN_BUF_BEGIN,
1190 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1191 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1192 dsp_in_buffer + (dsp_in_size / 2));
1194 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1195 s->inst.data + CDATA_IN_BUF_HEAD,
1198 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1199 s->inst.data + CDATA_IN_BUF_TAIL,
1202 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1203 s->inst.data + CDATA_OUT_BUF_BEGIN,
1206 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1207 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1208 dsp_out_buffer + (dsp_out_size / 2));
1210 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1211 s->inst.data + CDATA_OUT_BUF_HEAD,
1214 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1215 s->inst.data + CDATA_OUT_BUF_TAIL,
1219 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1220 struct snd_pcm_runtime *runtime)
1225 * put us in the lists if we're not already there
1227 if (! s->in_lists) {
1228 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1229 s->inst.data >> DP_SHIFT_COUNT);
1230 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1231 s->inst.data >> DP_SHIFT_COUNT);
1232 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1233 s->inst.data >> DP_SHIFT_COUNT);
1237 /* write to 'mono' word */
1238 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1239 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1240 runtime->channels == 2 ? 0 : 1);
1241 /* write to '8bit' word */
1242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1243 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1244 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1246 /* set up dac/adc rate */
1247 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252 s->inst.data + CDATA_FREQUENCY,
1257 static const struct play_vals {
1260 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1261 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1262 {SRC3_DIRECTION_OFFSET, 0} ,
1263 /* +1, +2 are stereo/16 bit */
1264 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1265 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1266 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1267 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1268 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1269 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1270 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1271 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1272 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1273 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1274 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1275 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1276 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1277 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1278 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1279 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1280 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1284 /* the mode passed should be already shifted and masked */
1286 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1287 struct snd_pcm_substream *subs)
1292 * some per client initializers
1295 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1296 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1297 s->inst.data + 40 + 8);
1299 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1301 s->inst.code + MINISRC_COEF_LOC);
1303 /* enable or disable low pass filter? */
1304 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1305 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1306 subs->runtime->rate > 45000 ? 0xff : 0);
1308 /* tell it which way dma is going? */
1309 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1310 s->inst.data + CDATA_DMA_CONTROL,
1311 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1314 * set an armload of static initializers
1316 for (i = 0; i < ARRAY_SIZE(pv); i++)
1317 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318 s->inst.data + pv[i].addr, pv[i].val);
1322 * Native record driver
1324 static const struct rec_vals {
1327 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1328 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1329 {SRC3_DIRECTION_OFFSET, 1} ,
1330 /* +1, +2 are stereo/16 bit */
1331 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1332 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1333 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1334 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1335 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1336 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1337 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1338 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1339 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1340 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1341 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1342 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1343 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1344 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1345 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1346 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1347 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1348 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1349 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1353 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1358 * some per client initializers
1361 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1362 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1363 s->inst.data + 40 + 8);
1365 /* tell it which way dma is going? */
1366 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1367 s->inst.data + CDATA_DMA_CONTROL,
1368 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1369 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1372 * set an armload of static initializers
1374 for (i = 0; i < ARRAY_SIZE(rv); i++)
1375 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1376 s->inst.data + rv[i].addr, rv[i].val);
1379 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1380 struct snd_pcm_hw_params *hw_params)
1382 struct m3_dma *s = substream->runtime->private_data;
1385 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1387 /* set buffer address */
1388 s->buffer_addr = substream->runtime->dma_addr;
1389 if (s->buffer_addr & 0x3) {
1390 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1391 s->buffer_addr = s->buffer_addr & ~0x3;
1396 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1400 if (substream->runtime->private_data == NULL)
1402 s = substream->runtime->private_data;
1403 snd_pcm_lib_free_pages(substream);
1409 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1411 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1412 struct snd_pcm_runtime *runtime = subs->runtime;
1413 struct m3_dma *s = runtime->private_data;
1418 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1419 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1421 if (runtime->rate > 48000 ||
1422 runtime->rate < 8000)
1425 spin_lock_irq(&chip->reg_lock);
1427 snd_m3_pcm_setup1(chip, s, subs);
1429 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1430 snd_m3_playback_setup(chip, s, subs);
1432 snd_m3_capture_setup(chip, s, subs);
1434 snd_m3_pcm_setup2(chip, s, runtime);
1436 spin_unlock_irq(&chip->reg_lock);
1442 * get current pointer
1445 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1452 * try and get a valid answer
1455 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1456 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1458 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1459 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1461 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1462 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1465 addr = lo | ((u32)hi<<16);
1466 return (unsigned int)(addr - s->buffer_addr);
1469 static snd_pcm_uframes_t
1470 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1472 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1474 struct m3_dma *s = subs->runtime->private_data;
1479 spin_lock(&chip->reg_lock);
1480 ptr = snd_m3_get_pointer(chip, s, subs);
1481 spin_unlock(&chip->reg_lock);
1482 return bytes_to_frames(subs->runtime, ptr);
1486 /* update pointer */
1487 /* spinlock held! */
1488 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1490 struct snd_pcm_substream *subs = s->substream;
1497 hwptr = snd_m3_get_pointer(chip, s, subs);
1499 /* try to avoid expensive modulo divisions */
1500 if (hwptr >= s->dma_size)
1501 hwptr %= s->dma_size;
1503 diff = s->dma_size + hwptr - s->hwptr;
1504 if (diff >= s->dma_size)
1505 diff %= s->dma_size;
1510 if (s->count >= (signed)s->period_size) {
1512 if (s->count < 2 * (signed)s->period_size)
1513 s->count -= (signed)s->period_size;
1515 s->count %= s->period_size;
1517 spin_unlock(&chip->reg_lock);
1518 snd_pcm_period_elapsed(subs);
1519 spin_lock(&chip->reg_lock);
1523 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1524 (without wrap around) in response to volume button presses and then
1525 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1526 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1527 static void snd_m3_update_hw_volume(struct work_struct *work)
1529 struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1532 /* Figure out which volume control button was pushed,
1533 based on differences from the default register
1535 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1537 /* Reset the volume counters to 4. Tests on the allegro integrated
1538 into a Compaq N600C laptop, have revealed that:
1539 1) Writing any value will result in the 2 counters being reset to
1540 4 so writing 0x88 is not strictly necessary
1541 2) Writing to any of the 4 involved registers will reset all 4
1542 of them (and reading them always returns the same value for all
1544 It could be that a maestro deviates from this, so leave the code
1546 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1547 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1548 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1549 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1551 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1552 mistaking them for a mute button press. */
1553 if (chip->in_suspend)
1556 #ifndef CONFIG_SND_MAESTRO3_INPUT
1557 if (!chip->master_switch || !chip->master_volume)
1560 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1563 /* The counters have not changed, yet we've received a HV
1564 interrupt. According to tests run by various people this
1565 happens when pressing the mute button. */
1569 /* counters increased by 1 -> volume up */
1570 if ((val & 0x7f) > 0)
1572 if ((val & 0x7f00) > 0)
1576 /* counters decreased by 1 -> volume down */
1577 if ((val & 0x7f) < 0x1f)
1579 if ((val & 0x7f00) < 0x1f00)
1583 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1584 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1585 &chip->master_switch->id);
1587 if (!chip->input_dev)
1593 /* The counters have not changed, yet we've received a HV
1594 interrupt. According to tests run by various people this
1595 happens when pressing the mute button. */
1599 /* counters increased by 1 -> volume up */
1603 /* counters decreased by 1 -> volume down */
1604 val = KEY_VOLUMEDOWN;
1609 input_report_key(chip->input_dev, val, 1);
1610 input_sync(chip->input_dev);
1611 input_report_key(chip->input_dev, val, 0);
1612 input_sync(chip->input_dev);
1617 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1619 struct snd_m3 *chip = dev_id;
1623 status = inb(chip->iobase + HOST_INT_STATUS);
1628 if (status & HV_INT_PENDING)
1629 schedule_work(&chip->hwvol_work);
1632 * ack an assp int if its running
1633 * and has an int pending
1635 if (status & ASSP_INT_PENDING) {
1636 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1637 if (!(ctl & STOP_ASSP_CLOCK)) {
1638 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1639 if (ctl & DSP2HOST_REQ_TIMER) {
1640 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1641 /* update adc/dac info if it was a timer int */
1642 spin_lock(&chip->reg_lock);
1643 for (i = 0; i < chip->num_substreams; i++) {
1644 struct m3_dma *s = &chip->substreams[i];
1646 snd_m3_update_ptr(chip, s);
1648 spin_unlock(&chip->reg_lock);
1653 #if 0 /* TODO: not supported yet */
1654 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1655 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1659 outb(status, chip->iobase + HOST_INT_STATUS);
1668 static const struct snd_pcm_hardware snd_m3_playback =
1670 .info = (SNDRV_PCM_INFO_MMAP |
1671 SNDRV_PCM_INFO_INTERLEAVED |
1672 SNDRV_PCM_INFO_MMAP_VALID |
1673 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1674 /*SNDRV_PCM_INFO_PAUSE |*/
1675 SNDRV_PCM_INFO_RESUME),
1676 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1677 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1682 .buffer_bytes_max = (512*1024),
1683 .period_bytes_min = 64,
1684 .period_bytes_max = (512*1024),
1686 .periods_max = 1024,
1689 static const struct snd_pcm_hardware snd_m3_capture =
1691 .info = (SNDRV_PCM_INFO_MMAP |
1692 SNDRV_PCM_INFO_INTERLEAVED |
1693 SNDRV_PCM_INFO_MMAP_VALID |
1694 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1695 /*SNDRV_PCM_INFO_PAUSE |*/
1696 SNDRV_PCM_INFO_RESUME),
1697 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1698 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1703 .buffer_bytes_max = (512*1024),
1704 .period_bytes_min = 64,
1705 .period_bytes_max = (512*1024),
1707 .periods_max = 1024,
1715 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1720 spin_lock_irq(&chip->reg_lock);
1721 for (i = 0; i < chip->num_substreams; i++) {
1722 s = &chip->substreams[i];
1726 spin_unlock_irq(&chip->reg_lock);
1731 spin_unlock_irq(&chip->reg_lock);
1733 subs->runtime->private_data = s;
1734 s->substream = subs;
1736 /* set list owners */
1737 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1738 s->index_list[0] = &chip->mixer_list;
1740 s->index_list[0] = &chip->adc1_list;
1741 s->index_list[1] = &chip->msrc_list;
1742 s->index_list[2] = &chip->dma_list;
1748 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1750 struct m3_dma *s = subs->runtime->private_data;
1753 return; /* not opened properly */
1755 spin_lock_irq(&chip->reg_lock);
1756 if (s->substream && s->running)
1757 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1759 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1760 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1761 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1766 spin_unlock_irq(&chip->reg_lock);
1770 snd_m3_playback_open(struct snd_pcm_substream *subs)
1772 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1773 struct snd_pcm_runtime *runtime = subs->runtime;
1776 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1779 runtime->hw = snd_m3_playback;
1785 snd_m3_playback_close(struct snd_pcm_substream *subs)
1787 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1789 snd_m3_substream_close(chip, subs);
1794 snd_m3_capture_open(struct snd_pcm_substream *subs)
1796 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1797 struct snd_pcm_runtime *runtime = subs->runtime;
1800 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1803 runtime->hw = snd_m3_capture;
1809 snd_m3_capture_close(struct snd_pcm_substream *subs)
1811 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1813 snd_m3_substream_close(chip, subs);
1818 * create pcm instance
1821 static const struct snd_pcm_ops snd_m3_playback_ops = {
1822 .open = snd_m3_playback_open,
1823 .close = snd_m3_playback_close,
1824 .ioctl = snd_pcm_lib_ioctl,
1825 .hw_params = snd_m3_pcm_hw_params,
1826 .hw_free = snd_m3_pcm_hw_free,
1827 .prepare = snd_m3_pcm_prepare,
1828 .trigger = snd_m3_pcm_trigger,
1829 .pointer = snd_m3_pcm_pointer,
1832 static const struct snd_pcm_ops snd_m3_capture_ops = {
1833 .open = snd_m3_capture_open,
1834 .close = snd_m3_capture_close,
1835 .ioctl = snd_pcm_lib_ioctl,
1836 .hw_params = snd_m3_pcm_hw_params,
1837 .hw_free = snd_m3_pcm_hw_free,
1838 .prepare = snd_m3_pcm_prepare,
1839 .trigger = snd_m3_pcm_trigger,
1840 .pointer = snd_m3_pcm_pointer,
1844 snd_m3_pcm(struct snd_m3 * chip, int device)
1846 struct snd_pcm *pcm;
1849 err = snd_pcm_new(chip->card, chip->card->driver, device,
1850 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1854 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1855 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1857 pcm->private_data = chip;
1858 pcm->info_flags = 0;
1859 strcpy(pcm->name, chip->card->driver);
1862 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1863 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1874 * Wait for the ac97 serial bus to be free.
1875 * return nonzero if the bus is still busy.
1877 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1882 if (! (snd_m3_inb(chip, 0x30) & 1))
1887 dev_err(chip->card->dev, "ac97 serial bus busy\n");
1891 static unsigned short
1892 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1894 struct snd_m3 *chip = ac97->private_data;
1895 unsigned short data = 0xffff;
1897 if (snd_m3_ac97_wait(chip))
1899 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1900 if (snd_m3_ac97_wait(chip))
1902 data = snd_m3_inw(chip, CODEC_DATA);
1908 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1910 struct snd_m3 *chip = ac97->private_data;
1912 if (snd_m3_ac97_wait(chip))
1914 snd_m3_outw(chip, val, CODEC_DATA);
1915 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1917 * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1918 * until the MASTER volume or mute is touched (alsactl restore does not
1921 if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1922 snd_m3_ac97_wait(chip);
1923 snd_m3_outw(chip, val, CODEC_DATA);
1924 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1929 static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1931 int io = chip->iobase;
1934 isremote = isremote ? 1 : 0;
1936 tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1937 /* enable dock on Dell Latitude C810 */
1938 if (chip->pci->subsystem_vendor == 0x1028 &&
1939 chip->pci->subsystem_device == 0x00e5)
1940 tmp |= M3I_DOCK_ENABLE;
1941 outw(tmp | isremote, io + RING_BUS_CTRL_B);
1942 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1943 io + SDO_OUT_DEST_CTRL);
1944 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1945 io + SDO_IN_DEST_CTRL);
1949 * hack, returns non zero on err
1951 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1955 if (snd_m3_ac97_wait(chip))
1958 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1960 if (snd_m3_ac97_wait(chip))
1963 ret = snd_m3_inw(chip, 0x32);
1965 return (ret == 0) || (ret == 0xffff);
1968 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1971 int delay1 = 0, delay2 = 0, i;
1972 int io = chip->iobase;
1974 if (chip->allegro_flag) {
1976 * the onboard codec on the allegro seems
1977 * to want to wait a very long time before
1978 * coming back to life
1988 for (i = 0; i < 5; i++) {
1989 dir = inw(io + GPIO_DIRECTION);
1990 if (!chip->irda_workaround)
1991 dir |= 0x10; /* assuming pci bus master? */
1993 snd_m3_remote_codec_config(chip, 0);
1995 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1998 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1999 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2000 outw(0, io + GPIO_DATA);
2001 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2003 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2005 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2007 /* ok, bring back the ac-link */
2008 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2009 outw(~0, io + GPIO_MASK);
2011 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2013 if (! snd_m3_try_read_vendor(chip))
2019 dev_dbg(chip->card->dev,
2020 "retrying codec reset with delays of %d and %d ms\n",
2025 /* more gung-ho reset that doesn't
2026 * seem to work anywhere :)
2028 tmp = inw(io + RING_BUS_CTRL_A);
2029 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2031 outw(tmp, io + RING_BUS_CTRL_A);
2036 static int snd_m3_mixer(struct snd_m3 *chip)
2038 struct snd_ac97_bus *pbus;
2039 struct snd_ac97_template ac97;
2040 #ifndef CONFIG_SND_MAESTRO3_INPUT
2041 struct snd_ctl_elem_id elem_id;
2044 static struct snd_ac97_bus_ops ops = {
2045 .write = snd_m3_ac97_write,
2046 .read = snd_m3_ac97_read,
2049 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2052 memset(&ac97, 0, sizeof(ac97));
2053 ac97.private_data = chip;
2054 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2057 /* seems ac97 PCM needs initialization.. hack hack.. */
2058 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2059 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2060 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2062 #ifndef CONFIG_SND_MAESTRO3_INPUT
2063 memset(&elem_id, 0, sizeof(elem_id));
2064 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2065 strcpy(elem_id.name, "Master Playback Switch");
2066 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2067 memset(&elem_id, 0, sizeof(elem_id));
2068 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2069 strcpy(elem_id.name, "Master Playback Volume");
2070 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2081 #define MINISRC_LPF_LEN 10
2082 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2083 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2084 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2087 static void snd_m3_assp_init(struct snd_m3 *chip)
2092 /* zero kernel data */
2093 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2094 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2095 KDATA_BASE_ADDR + i, 0);
2097 /* zero mixer data? */
2098 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2099 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2100 KDATA_BASE_ADDR2 + i, 0);
2102 /* init dma pointer */
2103 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2107 /* write kernel into code memory.. */
2108 data = (const __le16 *)chip->assp_kernel_image->data;
2109 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2110 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2111 REV_B_CODE_MEMORY_BEGIN + i,
2112 le16_to_cpu(data[i]));
2116 * We only have this one client and we know that 0x400
2117 * is free in our kernel's mem map, so lets just
2118 * drop it there. It seems that the minisrc doesn't
2119 * need vectors, so we won't bother with them..
2121 data = (const __le16 *)chip->assp_minisrc_image->data;
2122 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2123 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2124 0x400 + i, le16_to_cpu(data[i]));
2128 * write the coefficients for the low pass filter?
2130 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2131 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2132 0x400 + MINISRC_COEF_LOC + i,
2136 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2137 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2141 * the minisrc is the only thing on
2144 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2149 * init the mixer number..
2152 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2153 KDATA_MIXER_TASK_NUMBER,0);
2156 * EXTREME KERNEL MASTER VOLUME
2158 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2159 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2160 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2161 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2163 chip->mixer_list.curlen = 0;
2164 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2165 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2166 chip->adc1_list.curlen = 0;
2167 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2168 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2169 chip->dma_list.curlen = 0;
2170 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2171 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2172 chip->msrc_list.curlen = 0;
2173 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2174 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2178 static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2180 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2181 MINISRC_IN_BUFFER_SIZE / 2 +
2182 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2186 * the revb memory map has 0x1100 through 0x1c00
2191 * align instance address to 256 bytes so that its
2192 * shifted list address is aligned.
2193 * list address = (mem address >> 1) >> 7;
2195 data_bytes = ALIGN(data_bytes, 256);
2196 address = 0x1100 + ((data_bytes/2) * index);
2198 if ((address + (data_bytes/2)) >= 0x1c00) {
2199 dev_err(chip->card->dev,
2200 "no memory for %d bytes at ind %d (addr 0x%x)\n",
2201 data_bytes, index, address);
2206 s->inst.code = 0x400;
2207 s->inst.data = address;
2209 for (i = data_bytes / 2; i > 0; address++, i--) {
2210 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2219 * this works for the reference board, have to find
2222 * this needs more magic for 4 speaker, but..
2225 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2227 int io = chip->iobase;
2230 if (! chip->external_amp)
2233 polarity = enable ? 0 : 1;
2234 polarity = polarity << chip->amp_gpio;
2235 gpo = 1 << chip->amp_gpio;
2237 outw(~gpo, io + GPIO_MASK);
2239 outw(inw(io + GPIO_DIRECTION) | gpo,
2240 io + GPIO_DIRECTION);
2242 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2245 outw(0xffff, io + GPIO_MASK);
2249 snd_m3_hv_init(struct snd_m3 *chip)
2251 unsigned long io = chip->iobase;
2252 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2254 if (!chip->is_omnibook)
2258 * Volume buttons on some HP OmniBook laptops
2259 * require some GPIO magic to work correctly.
2261 outw(0xffff, io + GPIO_MASK);
2262 outw(0x0000, io + GPIO_DATA);
2264 outw(~val, io + GPIO_MASK);
2265 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2266 outw(val, io + GPIO_MASK);
2268 outw(0xffff, io + GPIO_MASK);
2272 snd_m3_chip_init(struct snd_m3 *chip)
2274 struct pci_dev *pcidev = chip->pci;
2275 unsigned long io = chip->iobase;
2278 u8 t; /* makes as much sense as 'n', no? */
2280 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2281 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2282 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2284 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2286 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2287 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2288 n |= chip->hv_config;
2289 /* For some reason we must always use reduced debounce. */
2290 n |= REDUCED_DEBOUNCE;
2291 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2292 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2294 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2295 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2296 n &= ~INT_CLK_SELECT;
2297 if (!chip->allegro_flag) {
2298 n &= ~INT_CLK_MULT_ENABLE;
2299 n |= INT_CLK_SRC_NOT_PCI;
2301 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2302 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2304 if (chip->allegro_flag) {
2305 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2306 n |= IN_CLK_12MHZ_SELECT;
2307 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2310 t = inb(chip->iobase + ASSP_CONTROL_A);
2311 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2312 t |= ASSP_CLK_49MHZ_SELECT;
2313 t |= ASSP_0_WS_ENABLE;
2314 outb(t, chip->iobase + ASSP_CONTROL_A);
2316 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2317 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2319 outb(0x00, io + HARDWARE_VOL_CTRL);
2320 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2321 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2322 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2323 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2329 snd_m3_enable_ints(struct snd_m3 *chip)
2331 unsigned long io = chip->iobase;
2334 /* TODO: MPU401 not supported yet */
2335 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2336 if (chip->hv_config & HV_CTRL_ENABLE)
2337 val |= HV_INT_ENABLE;
2338 outb(val, chip->iobase + HOST_INT_STATUS);
2339 outw(val, io + HOST_INT_CTRL);
2340 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2341 io + ASSP_CONTROL_C);
2348 static int snd_m3_free(struct snd_m3 *chip)
2353 cancel_work_sync(&chip->hwvol_work);
2354 #ifdef CONFIG_SND_MAESTRO3_INPUT
2355 if (chip->input_dev)
2356 input_unregister_device(chip->input_dev);
2359 if (chip->substreams) {
2360 spin_lock_irq(&chip->reg_lock);
2361 for (i = 0; i < chip->num_substreams; i++) {
2362 s = &chip->substreams[i];
2363 /* check surviving pcms; this should not happen though.. */
2364 if (s->substream && s->running)
2365 snd_m3_pcm_stop(chip, s, s->substream);
2367 spin_unlock_irq(&chip->reg_lock);
2368 kfree(chip->substreams);
2371 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2374 #ifdef CONFIG_PM_SLEEP
2375 vfree(chip->suspend_mem);
2379 free_irq(chip->irq, chip);
2382 pci_release_regions(chip->pci);
2384 release_firmware(chip->assp_kernel_image);
2385 release_firmware(chip->assp_minisrc_image);
2387 pci_disable_device(chip->pci);
2396 #ifdef CONFIG_PM_SLEEP
2397 static int m3_suspend(struct device *dev)
2399 struct snd_card *card = dev_get_drvdata(dev);
2400 struct snd_m3 *chip = card->private_data;
2403 if (chip->suspend_mem == NULL)
2406 chip->in_suspend = 1;
2407 cancel_work_sync(&chip->hwvol_work);
2408 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2409 snd_ac97_suspend(chip->ac97);
2411 msleep(10); /* give the assp a chance to idle.. */
2413 snd_m3_assp_halt(chip);
2415 /* save dsp image */
2417 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2418 chip->suspend_mem[dsp_index++] =
2419 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2420 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2421 chip->suspend_mem[dsp_index++] =
2422 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2426 static int m3_resume(struct device *dev)
2428 struct snd_card *card = dev_get_drvdata(dev);
2429 struct snd_m3 *chip = card->private_data;
2432 if (chip->suspend_mem == NULL)
2435 /* first lets just bring everything back. .*/
2436 snd_m3_outw(chip, 0, 0x54);
2437 snd_m3_outw(chip, 0, 0x56);
2439 snd_m3_chip_init(chip);
2440 snd_m3_assp_halt(chip);
2441 snd_m3_ac97_reset(chip);
2443 /* restore dsp image */
2445 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2446 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2447 chip->suspend_mem[dsp_index++]);
2448 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2449 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2450 chip->suspend_mem[dsp_index++]);
2452 /* tell the dma engine to restart itself */
2453 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2454 KDATA_DMA_ACTIVE, 0);
2456 /* restore ac97 registers */
2457 snd_ac97_resume(chip->ac97);
2459 snd_m3_assp_continue(chip);
2460 snd_m3_enable_ints(chip);
2461 snd_m3_amp_enable(chip, 1);
2463 snd_m3_hv_init(chip);
2465 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2466 chip->in_suspend = 0;
2470 static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2471 #define M3_PM_OPS &m3_pm
2473 #define M3_PM_OPS NULL
2474 #endif /* CONFIG_PM_SLEEP */
2476 #ifdef CONFIG_SND_MAESTRO3_INPUT
2477 static int snd_m3_input_register(struct snd_m3 *chip)
2479 struct input_dev *input_dev;
2482 input_dev = input_allocate_device();
2486 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2487 pci_name(chip->pci));
2489 input_dev->name = chip->card->driver;
2490 input_dev->phys = chip->phys;
2491 input_dev->id.bustype = BUS_PCI;
2492 input_dev->id.vendor = chip->pci->vendor;
2493 input_dev->id.product = chip->pci->device;
2494 input_dev->dev.parent = &chip->pci->dev;
2496 __set_bit(EV_KEY, input_dev->evbit);
2497 __set_bit(KEY_MUTE, input_dev->keybit);
2498 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2499 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2501 err = input_register_device(input_dev);
2503 input_free_device(input_dev);
2507 chip->input_dev = input_dev;
2510 #endif /* CONFIG_INPUT */
2515 static int snd_m3_dev_free(struct snd_device *device)
2517 struct snd_m3 *chip = device->device_data;
2518 return snd_m3_free(chip);
2522 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2525 struct snd_m3 **chip_ret)
2527 struct snd_m3 *chip;
2529 const struct snd_pci_quirk *quirk;
2530 static struct snd_device_ops ops = {
2531 .dev_free = snd_m3_dev_free,
2536 if (pci_enable_device(pci))
2539 /* check, if we can restrict PCI DMA transfers to 28 bits */
2540 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2541 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2543 "architecture does not support 28bit PCI busmaster DMA\n");
2544 pci_disable_device(pci);
2548 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2550 pci_disable_device(pci);
2554 spin_lock_init(&chip->reg_lock);
2556 switch (pci->device) {
2557 case PCI_DEVICE_ID_ESS_ALLEGRO:
2558 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2559 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2560 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2561 chip->allegro_flag = 1;
2568 INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2570 chip->external_amp = enable_amp;
2571 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2572 chip->amp_gpio = amp_gpio;
2574 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2576 dev_info(card->dev, "set amp-gpio for '%s'\n",
2577 snd_pci_quirk_name(quirk));
2578 chip->amp_gpio = quirk->value;
2579 } else if (chip->allegro_flag)
2580 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2581 else /* presumably this is for all 'maestro3's.. */
2582 chip->amp_gpio = GPO_EXT_AMP_M3;
2585 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2587 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2588 snd_pci_quirk_name(quirk));
2589 chip->irda_workaround = 1;
2591 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2593 chip->hv_config = quirk->value;
2594 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2595 chip->is_omnibook = 1;
2597 chip->num_substreams = NR_DSPS;
2598 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2600 if (chip->substreams == NULL) {
2602 pci_disable_device(pci);
2606 err = reject_firmware(&chip->assp_kernel_image,
2607 "/*(DEBLOBBED)*/", &pci->dev);
2611 err = reject_firmware(&chip->assp_minisrc_image,
2612 "/*(DEBLOBBED)*/", &pci->dev);
2616 err = pci_request_regions(pci, card->driver);
2620 chip->iobase = pci_resource_start(pci, 0);
2622 /* just to be sure */
2623 pci_set_master(pci);
2625 snd_m3_chip_init(chip);
2626 snd_m3_assp_halt(chip);
2628 snd_m3_ac97_reset(chip);
2630 snd_m3_amp_enable(chip, 1);
2632 snd_m3_hv_init(chip);
2634 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2635 KBUILD_MODNAME, chip)) {
2636 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2640 chip->irq = pci->irq;
2642 #ifdef CONFIG_PM_SLEEP
2644 vmalloc(array_size(sizeof(u16),
2645 REV_B_CODE_MEMORY_LENGTH +
2646 REV_B_DATA_MEMORY_LENGTH));
2647 if (chip->suspend_mem == NULL)
2648 dev_warn(card->dev, "can't allocate apm buffer\n");
2651 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2655 if ((err = snd_m3_mixer(chip)) < 0)
2658 for (i = 0; i < chip->num_substreams; i++) {
2659 struct m3_dma *s = &chip->substreams[i];
2660 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2664 if ((err = snd_m3_pcm(chip, 0)) < 0)
2667 #ifdef CONFIG_SND_MAESTRO3_INPUT
2668 if (chip->hv_config & HV_CTRL_ENABLE) {
2669 err = snd_m3_input_register(chip);
2672 "Input device registration failed with error %i",
2677 snd_m3_enable_ints(chip);
2678 snd_m3_assp_continue(chip);
2692 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2695 struct snd_card *card;
2696 struct snd_m3 *chip;
2699 /* don't pick up modems */
2700 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2703 if (dev >= SNDRV_CARDS)
2710 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2715 switch (pci->device) {
2716 case PCI_DEVICE_ID_ESS_ALLEGRO:
2717 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2718 strcpy(card->driver, "Allegro");
2720 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2721 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2722 strcpy(card->driver, "Canyon3D-2");
2725 strcpy(card->driver, "Maestro3");
2729 err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
2733 card->private_data = chip;
2735 sprintf(card->shortname, "ESS %s PCI", card->driver);
2736 sprintf(card->longname, "%s at 0x%lx, irq %d",
2737 card->shortname, chip->iobase, chip->irq);
2739 err = snd_card_register(card);
2743 #if 0 /* TODO: not supported yet */
2744 /* TODO enable MIDI IRQ and I/O */
2745 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2746 chip->iobase + MPU401_DATA_PORT,
2747 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2750 dev_warn(card->dev, "no MIDI support.\n");
2753 pci_set_drvdata(pci, card);
2758 snd_card_free(card);
2762 static void snd_m3_remove(struct pci_dev *pci)
2764 snd_card_free(pci_get_drvdata(pci));
2767 static struct pci_driver m3_driver = {
2768 .name = KBUILD_MODNAME,
2769 .id_table = snd_m3_ids,
2770 .probe = snd_m3_probe,
2771 .remove = snd_m3_remove,
2777 module_pci_driver(m3_driver);