sound/pci/maestro3.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   4  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   5  *                       Takashi Iwai <tiwai@suse.de>
   6  *
   7  * Most of the hardware init stuffs are based on maestro3 driver for
   8  * OSS/Free by Zach Brown.  Many thanks to Zach!
   9  *
  10  * ChangeLog:
  11  * Aug. 27, 2001
  12  *     - Fixed deadlock on capture
  13  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  14  */
  15
  16 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  17 #define DRIVER_NAME "Maestro3"
  18
  19 #include <linux/io.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/init.h>
  23 #include <linux/pci.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/module.h>
  28 #include <linux/firmware.h>
  29 #include <linux/input.h>
  30 #include <sound/core.h>
  31 #include <sound/info.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/mpu401.h>
  35 #include <sound/ac97_codec.h>
  36 #include <sound/initval.h>
  37 #include <asm/byteorder.h>
  38
  39 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  40 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  41 MODULE_LICENSE("GPL");
  42 /*(DEBLOBBED)*/
  43
  44 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  45 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  46 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  47 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  48 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  49
  50 module_param_array(index, int, NULL, 0444);
  51 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  52 module_param_array(id, charp, NULL, 0444);
  53 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  54 module_param_array(enable, bool, NULL, 0444);
  55 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  56 module_param_array(external_amp, bool, NULL, 0444);
  57 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  58 module_param_array(amp_gpio, int, NULL, 0444);
  59 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  60
  61 #define MAX_PLAYBACKS   2
  62 #define MAX_CAPTURES    1
  63 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  64
  65
  66 /*
  67  * maestro3 registers
  68  */
  69
  70 /* Allegro PCI configuration registers */
  71 #define PCI_LEGACY_AUDIO_CTRL   0x40
  72 #define SOUND_BLASTER_ENABLE    0x00000001
  73 #define FM_SYNTHESIS_ENABLE     0x00000002
  74 #define GAME_PORT_ENABLE        0x00000004
  75 #define MPU401_IO_ENABLE        0x00000008
  76 #define MPU401_IRQ_ENABLE       0x00000010
  77 #define ALIAS_10BIT_IO          0x00000020
  78 #define SB_DMA_MASK             0x000000C0
  79 #define SB_DMA_0                0x00000040
  80 #define SB_DMA_1                0x00000040
  81 #define SB_DMA_R                0x00000080
  82 #define SB_DMA_3                0x000000C0
  83 #define SB_IRQ_MASK             0x00000700
  84 #define SB_IRQ_5                0x00000000
  85 #define SB_IRQ_7                0x00000100
  86 #define SB_IRQ_9                0x00000200
  87 #define SB_IRQ_10               0x00000300
  88 #define MIDI_IRQ_MASK           0x00003800
  89 #define SERIAL_IRQ_ENABLE       0x00004000
  90 #define DISABLE_LEGACY          0x00008000
  91
  92 #define PCI_ALLEGRO_CONFIG      0x50
  93 #define SB_ADDR_240             0x00000004
  94 #define MPU_ADDR_MASK           0x00000018
  95 #define MPU_ADDR_330            0x00000000
  96 #define MPU_ADDR_300            0x00000008
  97 #define MPU_ADDR_320            0x00000010
  98 #define MPU_ADDR_340            0x00000018
  99 #define USE_PCI_TIMING          0x00000040
 100 #define POSTED_WRITE_ENABLE     0x00000080
 101 #define DMA_POLICY_MASK         0x00000700
 102 #define DMA_DDMA                0x00000000
 103 #define DMA_TDMA                0x00000100
 104 #define DMA_PCPCI               0x00000200
 105 #define DMA_WBDMA16             0x00000400
 106 #define DMA_WBDMA4              0x00000500
 107 #define DMA_WBDMA2              0x00000600
 108 #define DMA_WBDMA1              0x00000700
 109 #define DMA_SAFE_GUARD          0x00000800
 110 #define HI_PERF_GP_ENABLE       0x00001000
 111 #define PIC_SNOOP_MODE_0        0x00002000
 112 #define PIC_SNOOP_MODE_1        0x00004000
 113 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 114 #define RING_IN_ENABLE          0x00010000
 115 #define SPDIF_TEST_MODE         0x00020000
 116 #define CLK_MULT_MODE_SELECT_2  0x00040000
 117 #define EEPROM_WRITE_ENABLE     0x00080000
 118 #define CODEC_DIR_IN            0x00100000
 119 #define HV_BUTTON_FROM_GD       0x00200000
 120 #define REDUCED_DEBOUNCE        0x00400000
 121 #define HV_CTRL_ENABLE          0x00800000
 122 #define SPDIF_ENABLE            0x01000000
 123 #define CLK_DIV_SELECT          0x06000000
 124 #define CLK_DIV_BY_48           0x00000000
 125 #define CLK_DIV_BY_49           0x02000000
 126 #define CLK_DIV_BY_50           0x04000000
 127 #define CLK_DIV_RESERVED        0x06000000
 128 #define PM_CTRL_ENABLE          0x08000000
 129 #define CLK_MULT_MODE_SELECT    0x30000000
 130 #define CLK_MULT_MODE_SHIFT     28
 131 #define CLK_MULT_MODE_0         0x00000000
 132 #define CLK_MULT_MODE_1         0x10000000
 133 #define CLK_MULT_MODE_2         0x20000000
 134 #define CLK_MULT_MODE_3         0x30000000
 135 #define INT_CLK_SELECT          0x40000000
 136 #define INT_CLK_MULT_RESET      0x80000000
 137
 138 /* M3 */
 139 #define INT_CLK_SRC_NOT_PCI     0x00100000
 140 #define INT_CLK_MULT_ENABLE     0x80000000
 141
 142 #define PCI_ACPI_CONTROL        0x54
 143 #define PCI_ACPI_D0             0x00000000
 144 #define PCI_ACPI_D1             0xB4F70000
 145 #define PCI_ACPI_D2             0xB4F7B4F7
 146
 147 #define PCI_USER_CONFIG         0x58
 148 #define EXT_PCI_MASTER_ENABLE   0x00000001
 149 #define SPDIF_OUT_SELECT        0x00000002
 150 #define TEST_PIN_DIR_CTRL       0x00000004
 151 #define AC97_CODEC_TEST         0x00000020
 152 #define TRI_STATE_BUFFER        0x00000080
 153 #define IN_CLK_12MHZ_SELECT     0x00000100
 154 #define MULTI_FUNC_DISABLE      0x00000200
 155 #define EXT_MASTER_PAIR_SEL     0x00000400
 156 #define PCI_MASTER_SUPPORT      0x00000800
 157 #define STOP_CLOCK_ENABLE       0x00001000
 158 #define EAPD_DRIVE_ENABLE       0x00002000
 159 #define REQ_TRI_STATE_ENABLE    0x00004000
 160 #define REQ_LOW_ENABLE          0x00008000
 161 #define MIDI_1_ENABLE           0x00010000
 162 #define MIDI_2_ENABLE           0x00020000
 163 #define SB_AUDIO_SYNC           0x00040000
 164 #define HV_CTRL_TEST            0x00100000
 165 #define SOUNDBLASTER_TEST       0x00400000
 166
 167 #define PCI_USER_CONFIG_C       0x5C
 168
 169 #define PCI_DDMA_CTRL           0x60
 170 #define DDMA_ENABLE             0x00000001
 171
 172
 173 /* Allegro registers */
 174 #define HOST_INT_CTRL           0x18
 175 #define SB_INT_ENABLE           0x0001
 176 #define MPU401_INT_ENABLE       0x0002
 177 #define ASSP_INT_ENABLE         0x0010
 178 #define RING_INT_ENABLE         0x0020
 179 #define HV_INT_ENABLE           0x0040
 180 #define CLKRUN_GEN_ENABLE       0x0100
 181 #define HV_CTRL_TO_PME          0x0400
 182 #define SOFTWARE_RESET_ENABLE   0x8000
 183
 184 /*
 185  * should be using the above defines, probably.
 186  */
 187 #define REGB_ENABLE_RESET               0x01
 188 #define REGB_STOP_CLOCK                 0x10
 189
 190 #define HOST_INT_STATUS         0x1A
 191 #define SB_INT_PENDING          0x01
 192 #define MPU401_INT_PENDING      0x02
 193 #define ASSP_INT_PENDING        0x10
 194 #define RING_INT_PENDING        0x20
 195 #define HV_INT_PENDING          0x40
 196
 197 #define HARDWARE_VOL_CTRL       0x1B
 198 #define SHADOW_MIX_REG_VOICE    0x1C
 199 #define HW_VOL_COUNTER_VOICE    0x1D
 200 #define SHADOW_MIX_REG_MASTER   0x1E
 201 #define HW_VOL_COUNTER_MASTER   0x1F
 202
 203 #define CODEC_COMMAND           0x30
 204 #define CODEC_READ_B            0x80
 205
 206 #define CODEC_STATUS            0x30
 207 #define CODEC_BUSY_B            0x01
 208
 209 #define CODEC_DATA              0x32
 210
 211 #define RING_BUS_CTRL_A         0x36
 212 #define RAC_PME_ENABLE          0x0100
 213 #define RAC_SDFS_ENABLE         0x0200
 214 #define LAC_PME_ENABLE          0x0400
 215 #define LAC_SDFS_ENABLE         0x0800
 216 #define SERIAL_AC_LINK_ENABLE   0x1000
 217 #define IO_SRAM_ENABLE          0x2000
 218 #define IIS_INPUT_ENABLE        0x8000
 219
 220 #define RING_BUS_CTRL_B         0x38
 221 #define SECOND_CODEC_ID_MASK    0x0003
 222 #define SPDIF_FUNC_ENABLE       0x0010
 223 #define SECOND_AC_ENABLE        0x0020
 224 #define SB_MODULE_INTF_ENABLE   0x0040
 225 #define SSPE_ENABLE             0x0040
 226 #define M3I_DOCK_ENABLE         0x0080
 227
 228 #define SDO_OUT_DEST_CTRL       0x3A
 229 #define COMMAND_ADDR_OUT        0x0003
 230 #define PCM_LR_OUT_LOCAL        0x0000
 231 #define PCM_LR_OUT_REMOTE       0x0004
 232 #define PCM_LR_OUT_MUTE         0x0008
 233 #define PCM_LR_OUT_BOTH         0x000C
 234 #define LINE1_DAC_OUT_LOCAL     0x0000
 235 #define LINE1_DAC_OUT_REMOTE    0x0010
 236 #define LINE1_DAC_OUT_MUTE      0x0020
 237 #define LINE1_DAC_OUT_BOTH      0x0030
 238 #define PCM_CLS_OUT_LOCAL       0x0000
 239 #define PCM_CLS_OUT_REMOTE      0x0040
 240 #define PCM_CLS_OUT_MUTE        0x0080
 241 #define PCM_CLS_OUT_BOTH        0x00C0
 242 #define PCM_RLF_OUT_LOCAL       0x0000
 243 #define PCM_RLF_OUT_REMOTE      0x0100
 244 #define PCM_RLF_OUT_MUTE        0x0200
 245 #define PCM_RLF_OUT_BOTH        0x0300
 246 #define LINE2_DAC_OUT_LOCAL     0x0000
 247 #define LINE2_DAC_OUT_REMOTE    0x0400
 248 #define LINE2_DAC_OUT_MUTE      0x0800
 249 #define LINE2_DAC_OUT_BOTH      0x0C00
 250 #define HANDSET_OUT_LOCAL       0x0000
 251 #define HANDSET_OUT_REMOTE      0x1000
 252 #define HANDSET_OUT_MUTE        0x2000
 253 #define HANDSET_OUT_BOTH        0x3000
 254 #define IO_CTRL_OUT_LOCAL       0x0000
 255 #define IO_CTRL_OUT_REMOTE      0x4000
 256 #define IO_CTRL_OUT_MUTE        0x8000
 257 #define IO_CTRL_OUT_BOTH        0xC000
 258
 259 #define SDO_IN_DEST_CTRL        0x3C
 260 #define STATUS_ADDR_IN          0x0003
 261 #define PCM_LR_IN_LOCAL         0x0000
 262 #define PCM_LR_IN_REMOTE        0x0004
 263 #define PCM_LR_RESERVED         0x0008
 264 #define PCM_LR_IN_BOTH          0x000C
 265 #define LINE1_ADC_IN_LOCAL      0x0000
 266 #define LINE1_ADC_IN_REMOTE     0x0010
 267 #define LINE1_ADC_IN_MUTE       0x0020
 268 #define MIC_ADC_IN_LOCAL        0x0000
 269 #define MIC_ADC_IN_REMOTE       0x0040
 270 #define MIC_ADC_IN_MUTE         0x0080
 271 #define LINE2_DAC_IN_LOCAL      0x0000
 272 #define LINE2_DAC_IN_REMOTE     0x0400
 273 #define LINE2_DAC_IN_MUTE       0x0800
 274 #define HANDSET_IN_LOCAL        0x0000
 275 #define HANDSET_IN_REMOTE       0x1000
 276 #define HANDSET_IN_MUTE         0x2000
 277 #define IO_STATUS_IN_LOCAL      0x0000
 278 #define IO_STATUS_IN_REMOTE     0x4000
 279
 280 #define SPDIF_IN_CTRL           0x3E
 281 #define SPDIF_IN_ENABLE         0x0001
 282
 283 #define GPIO_DATA               0x60
 284 #define GPIO_DATA_MASK          0x0FFF
 285 #define GPIO_HV_STATUS          0x3000
 286 #define GPIO_PME_STATUS         0x4000
 287
 288 #define GPIO_MASK               0x64
 289 #define GPIO_DIRECTION          0x68
 290 #define GPO_PRIMARY_AC97        0x0001
 291 #define GPI_LINEOUT_SENSE       0x0004
 292 #define GPO_SECONDARY_AC97      0x0008
 293 #define GPI_VOL_DOWN            0x0010
 294 #define GPI_VOL_UP              0x0020
 295 #define GPI_IIS_CLK             0x0040
 296 #define GPI_IIS_LRCLK           0x0080
 297 #define GPI_IIS_DATA            0x0100
 298 #define GPI_DOCKING_STATUS      0x0100
 299 #define GPI_HEADPHONE_SENSE     0x0200
 300 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 301
 302 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 303 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 304
 305 /* M3 */
 306 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 307
 308 #define ASSP_INDEX_PORT         0x80
 309 #define ASSP_MEMORY_PORT        0x82
 310 #define ASSP_DATA_PORT          0x84
 311
 312 #define MPU401_DATA_PORT        0x98
 313 #define MPU401_STATUS_PORT      0x99
 314
 315 #define CLK_MULT_DATA_PORT      0x9C
 316
 317 #define ASSP_CONTROL_A          0xA2
 318 #define ASSP_0_WS_ENABLE        0x01
 319 #define ASSP_CTRL_A_RESERVED1   0x02
 320 #define ASSP_CTRL_A_RESERVED2   0x04
 321 #define ASSP_CLK_49MHZ_SELECT   0x08
 322 #define FAST_PLU_ENABLE         0x10
 323 #define ASSP_CTRL_A_RESERVED3   0x20
 324 #define DSP_CLK_36MHZ_SELECT    0x40
 325
 326 #define ASSP_CONTROL_B          0xA4
 327 #define RESET_ASSP              0x00
 328 #define RUN_ASSP                0x01
 329 #define ENABLE_ASSP_CLOCK       0x00
 330 #define STOP_ASSP_CLOCK         0x10
 331 #define RESET_TOGGLE            0x40
 332
 333 #define ASSP_CONTROL_C          0xA6
 334 #define ASSP_HOST_INT_ENABLE    0x01
 335 #define FM_ADDR_REMAP_DISABLE   0x02
 336 #define HOST_WRITE_PORT_ENABLE  0x08
 337
 338 #define ASSP_HOST_INT_STATUS    0xAC
 339 #define DSP2HOST_REQ_PIORECORD  0x01
 340 #define DSP2HOST_REQ_I2SRATE    0x02
 341 #define DSP2HOST_REQ_TIMER      0x04
 342
 343 /*
 344  * ASSP control regs
 345  */
 346 #define DSP_PORT_TIMER_COUNT    0x06
 347
 348 #define DSP_PORT_MEMORY_INDEX   0x80
 349
 350 #define DSP_PORT_MEMORY_TYPE    0x82
 351 #define MEMTYPE_INTERNAL_CODE   0x0002
 352 #define MEMTYPE_INTERNAL_DATA   0x0003
 353 #define MEMTYPE_MASK            0x0003
 354
 355 #define DSP_PORT_MEMORY_DATA    0x84
 356
 357 #define DSP_PORT_CONTROL_REG_A  0xA2
 358 #define DSP_PORT_CONTROL_REG_B  0xA4
 359 #define DSP_PORT_CONTROL_REG_C  0xA6
 360
 361 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 362 #define REV_A_CODE_MEMORY_END           0x0FFF
 363 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 364 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 365
 366 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 367 #define REV_B_CODE_MEMORY_END           0x0BFF
 368 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 369 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 370
 371 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 372 #define REV_A_DATA_MEMORY_END           0x2FFF
 373 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 374 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 375
 376 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 377 #define REV_B_DATA_MEMORY_END           0x2BFF
 378 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 379 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 380
 381
 382 #define NUM_UNITS_KERNEL_CODE          16
 383 #define NUM_UNITS_KERNEL_DATA           2
 384
 385 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 386 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 387
 388 /*
 389  * Kernel data layout
 390  */
 391
 392 #define DP_SHIFT_COUNT                  7
 393
 394 #define KDATA_BASE_ADDR                 0x1000
 395 #define KDATA_BASE_ADDR2                0x1080
 396
 397 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 398 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 399 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 400 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 401 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 402 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 403 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 404 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 405 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 406
 407 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 408 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 409
 410 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 411 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 412 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 413 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 414 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 415 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 416 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 417 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 418 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 419 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 420
 421 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 422 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 423
 424 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 425 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 426
 427 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 428 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 429
 430 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 431 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 432 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 433
 434 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 435 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 436 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 437 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 438 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 439
 440 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 441 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 442 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 443
 444 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 445 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 446 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 447
 448 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 449 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 450 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 451 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 452 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 453 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 454 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 455 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 456 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 457 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 458
 459 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 460 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 461 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 462
 463 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 464 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 465
 466 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 467 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 468 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 469
 470 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 471 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 472 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 473 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 474 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 475 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 476
 477 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 478 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 479 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 480 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 481 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 482 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 483
 484 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 485 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 486 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 487 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 488 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 489 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 490
 491 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 492 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 493 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 494 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 495
 496 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 497 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 498
 499 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 500 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 501
 502 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 503 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 504 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 505 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 506 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 507
 508 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 509 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 510
 511 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 512 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 513 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 514
 515 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 516 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 517
 518 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 519
 520 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 521 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 522 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 523 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 524 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 525 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 526 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 527 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 528 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 529 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 530 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 531 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 532
 533 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 534 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 535 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 536 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 537
 538 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 539 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 540
 541 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 542 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 543 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 544 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 545
 546 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 547 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 548 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 549 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 550 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 551
 552 /*
 553  * second 'segment' (?) reserved for mixer
 554  * buffers..
 555  */
 556
 557 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 558 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 559 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 560 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 561 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 562 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 563 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 564 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 565 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 566 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 567 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 568 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 569 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 570 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 571 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 572 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 573
 574 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 575 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 576 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 577 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 578 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 579 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 580 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 581 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 582 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 583 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 584 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 585
 586 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 587 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 588 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 589 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 590 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 591 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 592
 593 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 594 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 595 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 596 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 597
 598 /*
 599  * client data area offsets
 600  */
 601 #define CDATA_INSTANCE_READY            0x00
 602
 603 #define CDATA_HOST_SRC_ADDRL            0x01
 604 #define CDATA_HOST_SRC_ADDRH            0x02
 605 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 606 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 607 #define CDATA_HOST_SRC_CURRENTL         0x05
 608 #define CDATA_HOST_SRC_CURRENTH         0x06
 609
 610 #define CDATA_IN_BUF_CONNECT            0x07
 611 #define CDATA_OUT_BUF_CONNECT           0x08
 612
 613 #define CDATA_IN_BUF_BEGIN              0x09
 614 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 615 #define CDATA_IN_BUF_HEAD               0x0B
 616 #define CDATA_IN_BUF_TAIL               0x0C
 617 #define CDATA_OUT_BUF_BEGIN             0x0D
 618 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 619 #define CDATA_OUT_BUF_HEAD              0x0F
 620 #define CDATA_OUT_BUF_TAIL              0x10
 621
 622 #define CDATA_DMA_CONTROL               0x11
 623 #define CDATA_RESERVED                  0x12
 624
 625 #define CDATA_FREQUENCY                 0x13
 626 #define CDATA_LEFT_VOLUME               0x14
 627 #define CDATA_RIGHT_VOLUME              0x15
 628 #define CDATA_LEFT_SUR_VOL              0x16
 629 #define CDATA_RIGHT_SUR_VOL             0x17
 630
 631 #define CDATA_HEADER_LEN                0x18
 632
 633 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 634 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 635 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 636 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 637 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 638 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 639 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 640 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 641
 642 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 643 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 644 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 645 #define MINISRC_BIQUAD_STAGE    2
 646 #define MINISRC_COEF_LOC          0x175
 647
 648 #define DMACONTROL_BLOCK_MASK           0x000F
 649 #define  DMAC_BLOCK0_SELECTOR           0x0000
 650 #define  DMAC_BLOCK1_SELECTOR           0x0001
 651 #define  DMAC_BLOCK2_SELECTOR           0x0002
 652 #define  DMAC_BLOCK3_SELECTOR           0x0003
 653 #define  DMAC_BLOCK4_SELECTOR           0x0004
 654 #define  DMAC_BLOCK5_SELECTOR           0x0005
 655 #define  DMAC_BLOCK6_SELECTOR           0x0006
 656 #define  DMAC_BLOCK7_SELECTOR           0x0007
 657 #define  DMAC_BLOCK8_SELECTOR           0x0008
 658 #define  DMAC_BLOCK9_SELECTOR           0x0009
 659 #define  DMAC_BLOCKA_SELECTOR           0x000A
 660 #define  DMAC_BLOCKB_SELECTOR           0x000B
 661 #define  DMAC_BLOCKC_SELECTOR           0x000C
 662 #define  DMAC_BLOCKD_SELECTOR           0x000D
 663 #define  DMAC_BLOCKE_SELECTOR           0x000E
 664 #define  DMAC_BLOCKF_SELECTOR           0x000F
 665 #define DMACONTROL_PAGE_MASK            0x00F0
 666 #define  DMAC_PAGE0_SELECTOR            0x0030
 667 #define  DMAC_PAGE1_SELECTOR            0x0020
 668 #define  DMAC_PAGE2_SELECTOR            0x0010
 669 #define  DMAC_PAGE3_SELECTOR            0x0000
 670 #define DMACONTROL_AUTOREPEAT           0x1000
 671 #define DMACONTROL_STOPPED              0x2000
 672 #define DMACONTROL_DIRECTION            0x0100
 673
 674 /*
 675  * an arbitrary volume we set the internal
 676  * volume settings to so that the ac97 volume
 677  * range is a little less insane.  0x7fff is
 678  * max.
 679  */
 680 #define ARB_VOLUME ( 0x6800 )
 681
 682 /*
 683  */
 684
 685 struct m3_list {
 686         int curlen;
 687         int mem_addr;
 688         int max;
 689 };
 690
 691 struct m3_dma {
 692
 693         int number;
 694         struct snd_pcm_substream *substream;
 695
 696         struct assp_instance {
 697                 unsigned short code, data;
 698         } inst;
 699
 700         int running;
 701         int opened;
 702
 703         unsigned long buffer_addr;
 704         int dma_size;
 705         int period_size;
 706         unsigned int hwptr;
 707         int count;
 708
 709         int index[3];
 710         struct m3_list *index_list[3];
 711
 712         int in_lists;
 713
 714         struct list_head list;
 715
 716 };
 717
 718 struct snd_m3 {
 719
 720         struct snd_card *card;
 721
 722         unsigned long iobase;
 723
 724         int irq;
 725         unsigned int allegro_flag : 1;
 726
 727         struct snd_ac97 *ac97;
 728
 729         struct snd_pcm *pcm;
 730
 731         struct pci_dev *pci;
 732
 733         int dacs_active;
 734         int timer_users;
 735
 736         struct m3_list  msrc_list;
 737         struct m3_list  mixer_list;
 738         struct m3_list  adc1_list;
 739         struct m3_list  dma_list;
 740
 741         /* for storing reset state..*/
 742         u8 reset_state;
 743
 744         int external_amp;
 745         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
 746         unsigned int hv_config;         /* hardware-volume config bits */
 747         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
 748                                            (e.g. for IrDA on Dell Inspirons) */
 749         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
 750
 751         /* midi */
 752         struct snd_rawmidi *rmidi;
 753
 754         /* pcm streams */
 755         int num_substreams;
 756         struct m3_dma *substreams;
 757
 758         spinlock_t reg_lock;
 759
 760 #ifdef CONFIG_SND_MAESTRO3_INPUT
 761         struct input_dev *input_dev;
 762         char phys[64];                  /* physical device path */
 763 #else
 764         struct snd_kcontrol *master_switch;
 765         struct snd_kcontrol *master_volume;
 766 #endif
 767         struct work_struct hwvol_work;
 768
 769         unsigned int in_suspend;
 770
 771         u16 *suspend_mem;
 772
 773         const struct firmware *assp_kernel_image;
 774         const struct firmware *assp_minisrc_image;
 775 };
 776
 777 /*
 778  * pci ids
 779  */
 780 static const struct pci_device_id snd_m3_ids[] = {
 781         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 782          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 783         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 784          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 785         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 786          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 787         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 788          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 789         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 790          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 791         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 792          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 793         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 794          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 795         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 796          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 797         {0,},
 798 };
 799
 800 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 801
 802 static const struct snd_pci_quirk m3_amp_quirk_list[] = {
 803         SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
 804         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
 805         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
 806         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
 807         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
 808         { } /* END */
 809 };
 810
 811 static const struct snd_pci_quirk m3_irda_quirk_list[] = {
 812         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
 813         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
 814         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
 815         { } /* END */
 816 };
 817
 818 /* hardware volume quirks */
 819 static const struct snd_pci_quirk m3_hv_quirk_list[] = {
 820         /* Allegro chips */
 821         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 822         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 823         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 824         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 825         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 826         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 827         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 828         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 829         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 830         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 831         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 832         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 833         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 834         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 835         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 836         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 837         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 838         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 839         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 840         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 841         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 842         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 843         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 844         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 845         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 846         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
 847                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 848         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
 849                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 850         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
 851                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 852         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
 853                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 854         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
 855                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 856         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
 857                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 858         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
 859                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 860         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
 861                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 862         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
 863                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 864         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
 865                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 866         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
 867                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 868         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
 869                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 870         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
 871         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
 872         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
 873         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
 874         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
 875         /* Maestro3 chips */
 876         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
 877         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
 878         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
 879         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
 880         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
 881         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
 882         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
 883         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
 884         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
 885         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
 886         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
 887         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
 888         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
 889         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 890         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 891         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 892         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 893         { } /* END */
 894 };
 895
 896 /* HP Omnibook quirks */
 897 static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
 898         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
 899         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
 900         { } /* END */
 901 };
 902
 903 /*
 904  * lowlevel functions
 905  */
 906
 907 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
 908 {
 909         outw(value, chip->iobase + reg);
 910 }
 911
 912 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
 913 {
 914         return inw(chip->iobase + reg);
 915 }
 916
 917 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
 918 {
 919         outb(value, chip->iobase + reg);
 920 }
 921
 922 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
 923 {
 924         return inb(chip->iobase + reg);
 925 }
 926
 927 /*
 928  * access 16bit words to the code or data regions of the dsp's memory.
 929  * index addresses 16bit words.
 930  */
 931 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
 932 {
 933         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 934         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 935         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
 936 }
 937
 938 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
 939 {
 940         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 941         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 942         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
 943 }
 944
 945 static void snd_m3_assp_halt(struct snd_m3 *chip)
 946 {
 947         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
 948         msleep(10);
 949         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 950 }
 951
 952 static void snd_m3_assp_continue(struct snd_m3 *chip)
 953 {
 954         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 955 }
 956
 957
 958 /*
 959  * This makes me sad. the maestro3 has lists
 960  * internally that must be packed.. 0 terminates,
 961  * apparently, or maybe all unused entries have
 962  * to be 0, the lists have static lengths set
 963  * by the binary code images.
 964  */
 965
 966 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
 967 {
 968         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 969                           list->mem_addr + list->curlen,
 970                           val);
 971         return list->curlen++;
 972 }
 973
 974 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
 975 {
 976         u16  val;
 977         int lastindex = list->curlen - 1;
 978
 979         if (index != lastindex) {
 980                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
 981                                        list->mem_addr + lastindex);
 982                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 983                                   list->mem_addr + index,
 984                                   val);
 985         }
 986
 987         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 988                           list->mem_addr + lastindex,
 989                           0);
 990
 991         list->curlen--;
 992 }
 993
 994 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
 995 {
 996         chip->timer_users++;
 997         if (chip->timer_users != 1)
 998                 return;
 999
1000         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1001                           KDATA_TIMER_COUNT_RELOAD,
1002                           240);
1003
1004         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1005                           KDATA_TIMER_COUNT_CURRENT,
1006                           240);
1007
1008         snd_m3_outw(chip,
1009                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1010                     HOST_INT_CTRL);
1011 }
1012
1013 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1014 {
1015         chip->timer_users--;
1016         if (chip->timer_users > 0)
1017                 return;
1018
1019         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1020                           KDATA_TIMER_COUNT_RELOAD,
1021                           0);
1022
1023         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1024                           KDATA_TIMER_COUNT_CURRENT,
1025                           0);
1026
1027         snd_m3_outw(chip,
1028                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1029                     HOST_INT_CTRL);
1030 }
1031
1032 /*
1033  * start/stop
1034  */
1035
1036 /* spinlock held! */
1037 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1038                             struct snd_pcm_substream *subs)
1039 {
1040         if (! s || ! subs)
1041                 return -EINVAL;
1042
1043         snd_m3_inc_timer_users(chip);
1044         switch (subs->stream) {
1045         case SNDRV_PCM_STREAM_PLAYBACK:
1046                 chip->dacs_active++;
1047                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1048                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1049                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1050                                   KDATA_MIXER_TASK_NUMBER,
1051                                   chip->dacs_active);
1052                 break;
1053         case SNDRV_PCM_STREAM_CAPTURE:
1054                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055                                   KDATA_ADC1_REQUEST, 1);
1056                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1057                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1058                 break;
1059         }
1060         return 0;
1061 }
1062
1063 /* spinlock held! */
1064 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1065                            struct snd_pcm_substream *subs)
1066 {
1067         if (! s || ! subs)
1068                 return -EINVAL;
1069
1070         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1071                           s->inst.data + CDATA_INSTANCE_READY, 0);
1072         snd_m3_dec_timer_users(chip);
1073         switch (subs->stream) {
1074         case SNDRV_PCM_STREAM_PLAYBACK:
1075                 chip->dacs_active--;
1076                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1077                                   KDATA_MIXER_TASK_NUMBER,
1078                                   chip->dacs_active);
1079                 break;
1080         case SNDRV_PCM_STREAM_CAPTURE:
1081                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1082                                   KDATA_ADC1_REQUEST, 0);
1083                 break;
1084         }
1085         return 0;
1086 }
1087
1088 static int
1089 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1090 {
1091         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1092         struct m3_dma *s = subs->runtime->private_data;
1093         int err = -EINVAL;
1094
1095         if (snd_BUG_ON(!s))
1096                 return -ENXIO;
1097
1098         spin_lock(&chip->reg_lock);
1099         switch (cmd) {
1100         case SNDRV_PCM_TRIGGER_START:
1101         case SNDRV_PCM_TRIGGER_RESUME:
1102                 if (s->running)
1103                         err = -EBUSY;
1104                 else {
1105                         s->running = 1;
1106                         err = snd_m3_pcm_start(chip, s, subs);
1107                 }
1108                 break;
1109         case SNDRV_PCM_TRIGGER_STOP:
1110         case SNDRV_PCM_TRIGGER_SUSPEND:
1111                 if (! s->running)
1112                         err = 0; /* should return error? */
1113                 else {
1114                         s->running = 0;
1115                         err = snd_m3_pcm_stop(chip, s, subs);
1116                 }
1117                 break;
1118         }
1119         spin_unlock(&chip->reg_lock);
1120         return err;
1121 }
1122
1123 /*
1124  * setup
1125  */
1126 static void
1127 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1128 {
1129         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1130         struct snd_pcm_runtime *runtime = subs->runtime;
1131
1132         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1133                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1134                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1135         } else {
1136                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1137                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1138         }
1139         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1140         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1141
1142         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1143         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1144         s->hwptr = 0;
1145         s->count = 0;
1146
1147 #define LO(x) ((x) & 0xffff)
1148 #define HI(x) LO((x) >> 16)
1149
1150         /* host dma buffer pointers */
1151         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1152                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1153                           LO(s->buffer_addr));
1154
1155         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1156                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1157                           HI(s->buffer_addr));
1158
1159         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1160                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1161                           LO(s->buffer_addr + s->dma_size));
1162
1163         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1165                           HI(s->buffer_addr + s->dma_size));
1166
1167         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1168                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1169                           LO(s->buffer_addr));
1170
1171         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1172                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1173                           HI(s->buffer_addr));
1174 #undef LO
1175 #undef HI
1176
1177         /* dsp buffers */
1178
1179         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1180                           s->inst.data + CDATA_IN_BUF_BEGIN,
1181                           dsp_in_buffer);
1182
1183         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1184                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1185                           dsp_in_buffer + (dsp_in_size / 2));
1186
1187         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1188                           s->inst.data + CDATA_IN_BUF_HEAD,
1189                           dsp_in_buffer);
1190
1191         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1192                           s->inst.data + CDATA_IN_BUF_TAIL,
1193                           dsp_in_buffer);
1194
1195         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1196                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1197                           dsp_out_buffer);
1198
1199         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1200                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1201                           dsp_out_buffer + (dsp_out_size / 2));
1202
1203         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1204                           s->inst.data + CDATA_OUT_BUF_HEAD,
1205                           dsp_out_buffer);
1206
1207         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1208                           s->inst.data + CDATA_OUT_BUF_TAIL,
1209                           dsp_out_buffer);
1210 }
1211
1212 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1213                               struct snd_pcm_runtime *runtime)
1214 {
1215         u32 freq;
1216
1217         /*
1218          * put us in the lists if we're not already there
1219          */
1220         if (! s->in_lists) {
1221                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1222                                               s->inst.data >> DP_SHIFT_COUNT);
1223                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1224                                               s->inst.data >> DP_SHIFT_COUNT);
1225                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1226                                               s->inst.data >> DP_SHIFT_COUNT);
1227                 s->in_lists = 1;
1228         }
1229
1230         /* write to 'mono' word */
1231         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1232                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1233                           runtime->channels == 2 ? 0 : 1);
1234         /* write to '8bit' word */
1235         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1236                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1237                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1238
1239         /* set up dac/adc rate */
1240         freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000);
1241         if (freq)
1242                 freq--;
1243
1244         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245                           s->inst.data + CDATA_FREQUENCY,
1246                           freq);
1247 }
1248
1249
1250 static const struct play_vals {
1251         u16 addr, val;
1252 } pv[] = {
1253         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1254         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1255         {SRC3_DIRECTION_OFFSET, 0} ,
1256         /* +1, +2 are stereo/16 bit */
1257         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1258         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1259         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1260         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1261         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1262         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1263         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1264         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1265         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1266         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1267         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1268         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1269         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1270         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1271         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1272         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1273         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1274 };
1275
1276
1277 /* the mode passed should be already shifted and masked */
1278 static void
1279 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1280                       struct snd_pcm_substream *subs)
1281 {
1282         unsigned int i;
1283
1284         /*
1285          * some per client initializers
1286          */
1287
1288         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1289                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1290                           s->inst.data + 40 + 8);
1291
1292         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1293                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1294                           s->inst.code + MINISRC_COEF_LOC);
1295
1296         /* enable or disable low pass filter? */
1297         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1298                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1299                           subs->runtime->rate > 45000 ? 0xff : 0);
1300
1301         /* tell it which way dma is going? */
1302         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1303                           s->inst.data + CDATA_DMA_CONTROL,
1304                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1305
1306         /*
1307          * set an armload of static initializers
1308          */
1309         for (i = 0; i < ARRAY_SIZE(pv); i++)
1310                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1311                                   s->inst.data + pv[i].addr, pv[i].val);
1312 }
1313
1314 /*
1315  *    Native record driver
1316  */
1317 static const struct rec_vals {
1318         u16 addr, val;
1319 } rv[] = {
1320         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1321         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1322         {SRC3_DIRECTION_OFFSET, 1} ,
1323         /* +1, +2 are stereo/16 bit */
1324         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1325         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1326         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1327         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1328         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1329         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1330         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1331         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1332         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1333         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1334         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1335         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1336         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1337         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1338         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1339         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1340         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1341         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1342         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1343 };
1344
1345 static void
1346 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1347 {
1348         unsigned int i;
1349
1350         /*
1351          * some per client initializers
1352          */
1353
1354         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1355                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1356                           s->inst.data + 40 + 8);
1357
1358         /* tell it which way dma is going? */
1359         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1360                           s->inst.data + CDATA_DMA_CONTROL,
1361                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1362                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1363
1364         /*
1365          * set an armload of static initializers
1366          */
1367         for (i = 0; i < ARRAY_SIZE(rv); i++)
1368                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1369                                   s->inst.data + rv[i].addr, rv[i].val);
1370 }
1371
1372 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1373                                 struct snd_pcm_hw_params *hw_params)
1374 {
1375         struct m3_dma *s = substream->runtime->private_data;
1376
1377         /* set buffer address */
1378         s->buffer_addr = substream->runtime->dma_addr;
1379         if (s->buffer_addr & 0x3) {
1380                 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1381                 s->buffer_addr = s->buffer_addr & ~0x3;
1382         }
1383         return 0;
1384 }
1385
1386 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1387 {
1388         struct m3_dma *s;
1389
1390         if (substream->runtime->private_data == NULL)
1391                 return 0;
1392         s = substream->runtime->private_data;
1393         s->buffer_addr = 0;
1394         return 0;
1395 }
1396
1397 static int
1398 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1399 {
1400         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1401         struct snd_pcm_runtime *runtime = subs->runtime;
1402         struct m3_dma *s = runtime->private_data;
1403
1404         if (snd_BUG_ON(!s))
1405                 return -ENXIO;
1406
1407         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1408             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1409                 return -EINVAL;
1410         if (runtime->rate > 48000 ||
1411             runtime->rate < 8000)
1412                 return -EINVAL;
1413
1414         spin_lock_irq(&chip->reg_lock);
1415
1416         snd_m3_pcm_setup1(chip, s, subs);
1417
1418         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1419                 snd_m3_playback_setup(chip, s, subs);
1420         else
1421                 snd_m3_capture_setup(chip, s, subs);
1422
1423         snd_m3_pcm_setup2(chip, s, runtime);
1424
1425         spin_unlock_irq(&chip->reg_lock);
1426
1427         return 0;
1428 }
1429
1430 /*
1431  * get current pointer
1432  */
1433 static unsigned int
1434 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1435 {
1436         u16 hi = 0, lo = 0;
1437         int retry = 10;
1438         u32 addr;
1439
1440         /*
1441          * try and get a valid answer
1442          */
1443         while (retry--) {
1444                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1445                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1446
1447                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1448                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1449
1450                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1451                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1452                         break;
1453         }
1454         addr = lo | ((u32)hi<<16);
1455         return (unsigned int)(addr - s->buffer_addr);
1456 }
1457
1458 static snd_pcm_uframes_t
1459 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1460 {
1461         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1462         unsigned int ptr;
1463         struct m3_dma *s = subs->runtime->private_data;
1464
1465         if (snd_BUG_ON(!s))
1466                 return 0;
1467
1468         spin_lock(&chip->reg_lock);
1469         ptr = snd_m3_get_pointer(chip, s, subs);
1470         spin_unlock(&chip->reg_lock);
1471         return bytes_to_frames(subs->runtime, ptr);
1472 }
1473
1474
1475 /* update pointer */
1476 /* spinlock held! */
1477 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1478 {
1479         struct snd_pcm_substream *subs = s->substream;
1480         unsigned int hwptr;
1481         int diff;
1482
1483         if (! s->running)
1484                 return;
1485
1486         hwptr = snd_m3_get_pointer(chip, s, subs);
1487
1488         /* try to avoid expensive modulo divisions */
1489         if (hwptr >= s->dma_size)
1490                 hwptr %= s->dma_size;
1491
1492         diff = s->dma_size + hwptr - s->hwptr;
1493         if (diff >= s->dma_size)
1494                 diff %= s->dma_size;
1495
1496         s->hwptr = hwptr;
1497         s->count += diff;
1498
1499         if (s->count >= (signed)s->period_size) {
1500
1501                 if (s->count < 2 * (signed)s->period_size)
1502                         s->count -= (signed)s->period_size;
1503                 else
1504                         s->count %= s->period_size;
1505
1506                 spin_unlock(&chip->reg_lock);
1507                 snd_pcm_period_elapsed(subs);
1508                 spin_lock(&chip->reg_lock);
1509         }
1510 }
1511
1512 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1513    (without wrap around) in response to volume button presses and then
1514    generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1515    of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1516 static void snd_m3_update_hw_volume(struct work_struct *work)
1517 {
1518         struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1519         int x, val;
1520
1521         /* Figure out which volume control button was pushed,
1522            based on differences from the default register
1523            values. */
1524         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1525
1526         /* Reset the volume counters to 4. Tests on the allegro integrated
1527            into a Compaq N600C laptop, have revealed that:
1528            1) Writing any value will result in the 2 counters being reset to
1529               4 so writing 0x88 is not strictly necessary
1530            2) Writing to any of the 4 involved registers will reset all 4
1531               of them (and reading them always returns the same value for all
1532               of them)
1533            It could be that a maestro deviates from this, so leave the code
1534            as is. */
1535         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1536         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1537         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1538         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1539
1540         /* Ignore spurious HV interrupts during suspend / resume, this avoids
1541            mistaking them for a mute button press. */
1542         if (chip->in_suspend)
1543                 return;
1544
1545 #ifndef CONFIG_SND_MAESTRO3_INPUT
1546         if (!chip->master_switch || !chip->master_volume)
1547                 return;
1548
1549         val = snd_ac97_read(chip->ac97, AC97_MASTER);
1550         switch (x) {
1551         case 0x88:
1552                 /* The counters have not changed, yet we've received a HV
1553                    interrupt. According to tests run by various people this
1554                    happens when pressing the mute button. */
1555                 val ^= 0x8000;
1556                 break;
1557         case 0xaa:
1558                 /* counters increased by 1 -> volume up */
1559                 if ((val & 0x7f) > 0)
1560                         val--;
1561                 if ((val & 0x7f00) > 0)
1562                         val -= 0x0100;
1563                 break;
1564         case 0x66:
1565                 /* counters decreased by 1 -> volume down */
1566                 if ((val & 0x7f) < 0x1f)
1567                         val++;
1568                 if ((val & 0x7f00) < 0x1f00)
1569                         val += 0x0100;
1570                 break;
1571         }
1572         if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1573                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1574                                &chip->master_switch->id);
1575 #else
1576         if (!chip->input_dev)
1577                 return;
1578
1579         val = 0;
1580         switch (x) {
1581         case 0x88:
1582                 /* The counters have not changed, yet we've received a HV
1583                    interrupt. According to tests run by various people this
1584                    happens when pressing the mute button. */
1585                 val = KEY_MUTE;
1586                 break;
1587         case 0xaa:
1588                 /* counters increased by 1 -> volume up */
1589                 val = KEY_VOLUMEUP;
1590                 break;
1591         case 0x66:
1592                 /* counters decreased by 1 -> volume down */
1593                 val = KEY_VOLUMEDOWN;
1594                 break;
1595         }
1596
1597         if (val) {
1598                 input_report_key(chip->input_dev, val, 1);
1599                 input_sync(chip->input_dev);
1600                 input_report_key(chip->input_dev, val, 0);
1601                 input_sync(chip->input_dev);
1602         }
1603 #endif
1604 }
1605
1606 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1607 {
1608         struct snd_m3 *chip = dev_id;
1609         u8 status;
1610         int i;
1611
1612         status = inb(chip->iobase + HOST_INT_STATUS);
1613
1614         if (status == 0xff)
1615                 return IRQ_NONE;
1616
1617         if (status & HV_INT_PENDING)
1618                 schedule_work(&chip->hwvol_work);
1619
1620         /*
1621          * ack an assp int if its running
1622          * and has an int pending
1623          */
1624         if (status & ASSP_INT_PENDING) {
1625                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1626                 if (!(ctl & STOP_ASSP_CLOCK)) {
1627                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1628                         if (ctl & DSP2HOST_REQ_TIMER) {
1629                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1630                                 /* update adc/dac info if it was a timer int */
1631                                 spin_lock(&chip->reg_lock);
1632                                 for (i = 0; i < chip->num_substreams; i++) {
1633                                         struct m3_dma *s = &chip->substreams[i];
1634                                         if (s->running)
1635                                                 snd_m3_update_ptr(chip, s);
1636                                 }
1637                                 spin_unlock(&chip->reg_lock);
1638                         }
1639                 }
1640         }
1641
1642 #if 0 /* TODO: not supported yet */
1643         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1644                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1645 #endif
1646
1647         /* ack ints */
1648         outb(status, chip->iobase + HOST_INT_STATUS);
1649
1650         return IRQ_HANDLED;
1651 }
1652
1653
1654 /*
1655  */
1656
1657 static const struct snd_pcm_hardware snd_m3_playback =
1658 {
1659         .info =                 (SNDRV_PCM_INFO_MMAP |
1660                                  SNDRV_PCM_INFO_INTERLEAVED |
1661                                  SNDRV_PCM_INFO_MMAP_VALID |
1662                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1663                                  /*SNDRV_PCM_INFO_PAUSE |*/
1664                                  SNDRV_PCM_INFO_RESUME),
1665         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1666         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1667         .rate_min =             8000,
1668         .rate_max =             48000,
1669         .channels_min =         1,
1670         .channels_max =         2,
1671         .buffer_bytes_max =     (512*1024),
1672         .period_bytes_min =     64,
1673         .period_bytes_max =     (512*1024),
1674         .periods_min =          1,
1675         .periods_max =          1024,
1676 };
1677
1678 static const struct snd_pcm_hardware snd_m3_capture =
1679 {
1680         .info =                 (SNDRV_PCM_INFO_MMAP |
1681                                  SNDRV_PCM_INFO_INTERLEAVED |
1682                                  SNDRV_PCM_INFO_MMAP_VALID |
1683                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1684                                  /*SNDRV_PCM_INFO_PAUSE |*/
1685                                  SNDRV_PCM_INFO_RESUME),
1686         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1687         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1688         .rate_min =             8000,
1689         .rate_max =             48000,
1690         .channels_min =         1,
1691         .channels_max =         2,
1692         .buffer_bytes_max =     (512*1024),
1693         .period_bytes_min =     64,
1694         .period_bytes_max =     (512*1024),
1695         .periods_min =          1,
1696         .periods_max =          1024,
1697 };
1698
1699
1700 /*
1701  */
1702
1703 static int
1704 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1705 {
1706         int i;
1707         struct m3_dma *s;
1708
1709         spin_lock_irq(&chip->reg_lock);
1710         for (i = 0; i < chip->num_substreams; i++) {
1711                 s = &chip->substreams[i];
1712                 if (! s->opened)
1713                         goto __found;
1714         }
1715         spin_unlock_irq(&chip->reg_lock);
1716         return -ENOMEM;
1717 __found:
1718         s->opened = 1;
1719         s->running = 0;
1720         spin_unlock_irq(&chip->reg_lock);
1721
1722         subs->runtime->private_data = s;
1723         s->substream = subs;
1724
1725         /* set list owners */
1726         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1727                 s->index_list[0] = &chip->mixer_list;
1728         } else
1729                 s->index_list[0] = &chip->adc1_list;
1730         s->index_list[1] = &chip->msrc_list;
1731         s->index_list[2] = &chip->dma_list;
1732
1733         return 0;
1734 }
1735
1736 static void
1737 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1738 {
1739         struct m3_dma *s = subs->runtime->private_data;
1740
1741         if (s == NULL)
1742                 return; /* not opened properly */
1743
1744         spin_lock_irq(&chip->reg_lock);
1745         if (s->substream && s->running)
1746                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1747         if (s->in_lists) {
1748                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1749                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1750                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1751                 s->in_lists = 0;
1752         }
1753         s->running = 0;
1754         s->opened = 0;
1755         spin_unlock_irq(&chip->reg_lock);
1756 }
1757
1758 static int
1759 snd_m3_playback_open(struct snd_pcm_substream *subs)
1760 {
1761         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1762         struct snd_pcm_runtime *runtime = subs->runtime;
1763         int err;
1764
1765         err = snd_m3_substream_open(chip, subs);
1766         if (err < 0)
1767                 return err;
1768
1769         runtime->hw = snd_m3_playback;
1770
1771         return 0;
1772 }
1773
1774 static int
1775 snd_m3_playback_close(struct snd_pcm_substream *subs)
1776 {
1777         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1778
1779         snd_m3_substream_close(chip, subs);
1780         return 0;
1781 }
1782
1783 static int
1784 snd_m3_capture_open(struct snd_pcm_substream *subs)
1785 {
1786         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1787         struct snd_pcm_runtime *runtime = subs->runtime;
1788         int err;
1789
1790         err = snd_m3_substream_open(chip, subs);
1791         if (err < 0)
1792                 return err;
1793
1794         runtime->hw = snd_m3_capture;
1795
1796         return 0;
1797 }
1798
1799 static int
1800 snd_m3_capture_close(struct snd_pcm_substream *subs)
1801 {
1802         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1803
1804         snd_m3_substream_close(chip, subs);
1805         return 0;
1806 }
1807
1808 /*
1809  * create pcm instance
1810  */
1811
1812 static const struct snd_pcm_ops snd_m3_playback_ops = {
1813         .open =         snd_m3_playback_open,
1814         .close =        snd_m3_playback_close,
1815         .hw_params =    snd_m3_pcm_hw_params,
1816         .hw_free =      snd_m3_pcm_hw_free,
1817         .prepare =      snd_m3_pcm_prepare,
1818         .trigger =      snd_m3_pcm_trigger,
1819         .pointer =      snd_m3_pcm_pointer,
1820 };
1821
1822 static const struct snd_pcm_ops snd_m3_capture_ops = {
1823         .open =         snd_m3_capture_open,
1824         .close =        snd_m3_capture_close,
1825         .hw_params =    snd_m3_pcm_hw_params,
1826         .hw_free =      snd_m3_pcm_hw_free,
1827         .prepare =      snd_m3_pcm_prepare,
1828         .trigger =      snd_m3_pcm_trigger,
1829         .pointer =      snd_m3_pcm_pointer,
1830 };
1831
1832 static int
1833 snd_m3_pcm(struct snd_m3 * chip, int device)
1834 {
1835         struct snd_pcm *pcm;
1836         int err;
1837
1838         err = snd_pcm_new(chip->card, chip->card->driver, device,
1839                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1840         if (err < 0)
1841                 return err;
1842
1843         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1844         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1845
1846         pcm->private_data = chip;
1847         pcm->info_flags = 0;
1848         strcpy(pcm->name, chip->card->driver);
1849         chip->pcm = pcm;
1850
1851         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1852                                        &chip->pci->dev, 64*1024, 64*1024);
1853
1854         return 0;
1855 }
1856
1857
1858 /*
1859  * ac97 interface
1860  */
1861
1862 /*
1863  * Wait for the ac97 serial bus to be free.
1864  * return nonzero if the bus is still busy.
1865  */
1866 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1867 {
1868         int i = 10000;
1869
1870         do {
1871                 if (! (snd_m3_inb(chip, 0x30) & 1))
1872                         return 0;
1873                 cpu_relax();
1874         } while (i-- > 0);
1875
1876         dev_err(chip->card->dev, "ac97 serial bus busy\n");
1877         return 1;
1878 }
1879
1880 static unsigned short
1881 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1882 {
1883         struct snd_m3 *chip = ac97->private_data;
1884         unsigned short data = 0xffff;
1885
1886         if (snd_m3_ac97_wait(chip))
1887                 goto fail;
1888         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1889         if (snd_m3_ac97_wait(chip))
1890                 goto fail;
1891         data = snd_m3_inw(chip, CODEC_DATA);
1892 fail:
1893         return data;
1894 }
1895
1896 static void
1897 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1898 {
1899         struct snd_m3 *chip = ac97->private_data;
1900
1901         if (snd_m3_ac97_wait(chip))
1902                 return;
1903         snd_m3_outw(chip, val, CODEC_DATA);
1904         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1905         /*
1906          * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1907          * until the MASTER volume or mute is touched (alsactl restore does not
1908          * work).
1909          */
1910         if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1911                 snd_m3_ac97_wait(chip);
1912                 snd_m3_outw(chip, val, CODEC_DATA);
1913                 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1914         }
1915 }
1916
1917
1918 static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1919 {
1920         int io = chip->iobase;
1921         u16 tmp;
1922
1923         isremote = isremote ? 1 : 0;
1924
1925         tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1926         /* enable dock on Dell Latitude C810 */
1927         if (chip->pci->subsystem_vendor == 0x1028 &&
1928             chip->pci->subsystem_device == 0x00e5)
1929                 tmp |= M3I_DOCK_ENABLE;
1930         outw(tmp | isremote, io + RING_BUS_CTRL_B);
1931         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1932              io + SDO_OUT_DEST_CTRL);
1933         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1934              io + SDO_IN_DEST_CTRL);
1935 }
1936
1937 /*
1938  * hack, returns non zero on err
1939  */
1940 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1941 {
1942         u16 ret;
1943
1944         if (snd_m3_ac97_wait(chip))
1945                 return 1;
1946
1947         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1948
1949         if (snd_m3_ac97_wait(chip))
1950                 return 1;
1951
1952         ret = snd_m3_inw(chip, 0x32);
1953
1954         return (ret == 0) || (ret == 0xffff);
1955 }
1956
1957 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1958 {
1959         u16 dir;
1960         int delay1 = 0, delay2 = 0, i;
1961         int io = chip->iobase;
1962
1963         if (chip->allegro_flag) {
1964                 /*
1965                  * the onboard codec on the allegro seems
1966                  * to want to wait a very long time before
1967                  * coming back to life
1968                  */
1969                 delay1 = 50;
1970                 delay2 = 800;
1971         } else {
1972                 /* maestro3 */
1973                 delay1 = 20;
1974                 delay2 = 500;
1975         }
1976
1977         for (i = 0; i < 5; i++) {
1978                 dir = inw(io + GPIO_DIRECTION);
1979                 if (!chip->irda_workaround)
1980                         dir |= 0x10; /* assuming pci bus master? */
1981
1982                 snd_m3_remote_codec_config(chip, 0);
1983
1984                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1985                 udelay(20);
1986
1987                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1988                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1989                 outw(0, io + GPIO_DATA);
1990                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1991
1992                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
1993
1994                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1995                 udelay(5);
1996                 /* ok, bring back the ac-link */
1997                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1998                 outw(~0, io + GPIO_MASK);
1999
2000                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2001
2002                 if (! snd_m3_try_read_vendor(chip))
2003                         break;
2004
2005                 delay1 += 10;
2006                 delay2 += 100;
2007
2008                 dev_dbg(chip->card->dev,
2009                         "retrying codec reset with delays of %d and %d ms\n",
2010                            delay1, delay2);
2011         }
2012
2013 #if 0
2014         /* more gung-ho reset that doesn't
2015          * seem to work anywhere :)
2016          */
2017         tmp = inw(io + RING_BUS_CTRL_A);
2018         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2019         msleep(20);
2020         outw(tmp, io + RING_BUS_CTRL_A);
2021         msleep(50);
2022 #endif
2023 }
2024
2025 static int snd_m3_mixer(struct snd_m3 *chip)
2026 {
2027         struct snd_ac97_bus *pbus;
2028         struct snd_ac97_template ac97;
2029         int err;
2030         static const struct snd_ac97_bus_ops ops = {
2031                 .write = snd_m3_ac97_write,
2032                 .read = snd_m3_ac97_read,
2033         };
2034
2035         err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
2036         if (err < 0)
2037                 return err;
2038
2039         memset(&ac97, 0, sizeof(ac97));
2040         ac97.private_data = chip;
2041         err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
2042         if (err < 0)
2043                 return err;
2044
2045         /* seems ac97 PCM needs initialization.. hack hack.. */
2046         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2047         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2048         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2049
2050 #ifndef CONFIG_SND_MAESTRO3_INPUT
2051         chip->master_switch = snd_ctl_find_id_mixer(chip->card,
2052                                                     "Master Playback Switch");
2053         chip->master_volume = snd_ctl_find_id_mixer(chip->card,
2054                                                     "Master Playback Volume");
2055 #endif
2056
2057         return 0;
2058 }
2059
2060
2061 /*
2062  * initialize ASSP
2063  */
2064
2065 #define MINISRC_LPF_LEN 10
2066 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2067         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2068         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2069 };
2070
2071 static void snd_m3_assp_init(struct snd_m3 *chip)
2072 {
2073         unsigned int i;
2074         const __le16 *data;
2075
2076         /* zero kernel data */
2077         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2078                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2079                                   KDATA_BASE_ADDR + i, 0);
2080
2081         /* zero mixer data? */
2082         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2083                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2084                                   KDATA_BASE_ADDR2 + i, 0);
2085
2086         /* init dma pointer */
2087         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2088                           KDATA_CURRENT_DMA,
2089                           KDATA_DMA_XFER0);
2090
2091         /* write kernel into code memory.. */
2092         data = (const __le16 *)chip->assp_kernel_image->data;
2093         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2094                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2095                                   REV_B_CODE_MEMORY_BEGIN + i,
2096                                   le16_to_cpu(data[i]));
2097         }
2098
2099         /*
2100          * We only have this one client and we know that 0x400
2101          * is free in our kernel's mem map, so lets just
2102          * drop it there.  It seems that the minisrc doesn't
2103          * need vectors, so we won't bother with them..
2104          */
2105         data = (const __le16 *)chip->assp_minisrc_image->data;
2106         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2107                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2108                                   0x400 + i, le16_to_cpu(data[i]));
2109         }
2110
2111         /*
2112          * write the coefficients for the low pass filter?
2113          */
2114         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2115                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2116                                   0x400 + MINISRC_COEF_LOC + i,
2117                                   minisrc_lpf[i]);
2118         }
2119
2120         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2121                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2122                           0x8000);
2123
2124         /*
2125          * the minisrc is the only thing on
2126          * our task list..
2127          */
2128         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2129                           KDATA_TASK0,
2130                           0x400);
2131
2132         /*
2133          * init the mixer number..
2134          */
2135
2136         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2137                           KDATA_MIXER_TASK_NUMBER,0);
2138
2139         /*
2140          * EXTREME KERNEL MASTER VOLUME
2141          */
2142         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2143                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2144         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2145                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2146
2147         chip->mixer_list.curlen = 0;
2148         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2149         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2150         chip->adc1_list.curlen = 0;
2151         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2152         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2153         chip->dma_list.curlen = 0;
2154         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2155         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2156         chip->msrc_list.curlen = 0;
2157         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2158         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2159 }
2160
2161
2162 static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2163 {
2164         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2165                                MINISRC_IN_BUFFER_SIZE / 2 +
2166                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2167         int address, i;
2168
2169         /*
2170          * the revb memory map has 0x1100 through 0x1c00
2171          * free.
2172          */
2173
2174         /*
2175          * align instance address to 256 bytes so that its
2176          * shifted list address is aligned.
2177          * list address = (mem address >> 1) >> 7;
2178          */
2179         data_bytes = ALIGN(data_bytes, 256);
2180         address = 0x1100 + ((data_bytes/2) * index);
2181
2182         if ((address + (data_bytes/2)) >= 0x1c00) {
2183                 dev_err(chip->card->dev,
2184                         "no memory for %d bytes at ind %d (addr 0x%x)\n",
2185                            data_bytes, index, address);
2186                 return -ENOMEM;
2187         }
2188
2189         s->number = index;
2190         s->inst.code = 0x400;
2191         s->inst.data = address;
2192
2193         for (i = data_bytes / 2; i > 0; address++, i--) {
2194                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2195                                   address, 0);
2196         }
2197
2198         return 0;
2199 }
2200
2201
2202 /*
2203  * this works for the reference board, have to find
2204  * out about others
2205  *
2206  * this needs more magic for 4 speaker, but..
2207  */
2208 static void
2209 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2210 {
2211         int io = chip->iobase;
2212         u16 gpo, polarity;
2213
2214         if (! chip->external_amp)
2215                 return;
2216
2217         polarity = enable ? 0 : 1;
2218         polarity = polarity << chip->amp_gpio;
2219         gpo = 1 << chip->amp_gpio;
2220
2221         outw(~gpo, io + GPIO_MASK);
2222
2223         outw(inw(io + GPIO_DIRECTION) | gpo,
2224              io + GPIO_DIRECTION);
2225
2226         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2227              io + GPIO_DATA);
2228
2229         outw(0xffff, io + GPIO_MASK);
2230 }
2231
2232 static void
2233 snd_m3_hv_init(struct snd_m3 *chip)
2234 {
2235         unsigned long io = chip->iobase;
2236         u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2237
2238         if (!chip->is_omnibook)
2239                 return;
2240
2241         /*
2242          * Volume buttons on some HP OmniBook laptops
2243          * require some GPIO magic to work correctly.
2244          */
2245         outw(0xffff, io + GPIO_MASK);
2246         outw(0x0000, io + GPIO_DATA);
2247
2248         outw(~val, io + GPIO_MASK);
2249         outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2250         outw(val, io + GPIO_MASK);
2251
2252         outw(0xffff, io + GPIO_MASK);
2253 }
2254
2255 static int
2256 snd_m3_chip_init(struct snd_m3 *chip)
2257 {
2258         struct pci_dev *pcidev = chip->pci;
2259         unsigned long io = chip->iobase;
2260         u32 n;
2261         u16 w;
2262         u8 t; /* makes as much sense as 'n', no? */
2263
2264         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2265         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2266                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2267                DISABLE_LEGACY);
2268         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2269
2270         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2271         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2272         n |= chip->hv_config;
2273         /* For some reason we must always use reduced debounce. */
2274         n |= REDUCED_DEBOUNCE;
2275         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2276         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2277
2278         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2279         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2280         n &= ~INT_CLK_SELECT;
2281         if (!chip->allegro_flag) {
2282                 n &= ~INT_CLK_MULT_ENABLE;
2283                 n |= INT_CLK_SRC_NOT_PCI;
2284         }
2285         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2286         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2287
2288         if (chip->allegro_flag) {
2289                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2290                 n |= IN_CLK_12MHZ_SELECT;
2291                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2292         }
2293
2294         t = inb(chip->iobase + ASSP_CONTROL_A);
2295         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2296         t |= ASSP_CLK_49MHZ_SELECT;
2297         t |= ASSP_0_WS_ENABLE;
2298         outb(t, chip->iobase + ASSP_CONTROL_A);
2299
2300         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2301         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2302
2303         outb(0x00, io + HARDWARE_VOL_CTRL);
2304         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2305         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2306         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2307         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2308
2309         return 0;
2310 }
2311
2312 static void
2313 snd_m3_enable_ints(struct snd_m3 *chip)
2314 {
2315         unsigned long io = chip->iobase;
2316         unsigned short val;
2317
2318         /* TODO: MPU401 not supported yet */
2319         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2320         if (chip->hv_config & HV_CTRL_ENABLE)
2321                 val |= HV_INT_ENABLE;
2322         outb(val, chip->iobase + HOST_INT_STATUS);
2323         outw(val, io + HOST_INT_CTRL);
2324         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2325              io + ASSP_CONTROL_C);
2326 }
2327
2328
2329 /*
2330  */
2331
2332 static void snd_m3_free(struct snd_card *card)
2333 {
2334         struct snd_m3 *chip = card->private_data;
2335         struct m3_dma *s;
2336         int i;
2337
2338         cancel_work_sync(&chip->hwvol_work);
2339
2340         if (chip->substreams) {
2341                 spin_lock_irq(&chip->reg_lock);
2342                 for (i = 0; i < chip->num_substreams; i++) {
2343                         s = &chip->substreams[i];
2344                         /* check surviving pcms; this should not happen though.. */
2345                         if (s->substream && s->running)
2346                                 snd_m3_pcm_stop(chip, s, s->substream);
2347                 }
2348                 spin_unlock_irq(&chip->reg_lock);
2349         }
2350         if (chip->iobase) {
2351                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2352         }
2353
2354         vfree(chip->suspend_mem);
2355         release_firmware(chip->assp_kernel_image);
2356         release_firmware(chip->assp_minisrc_image);
2357 }
2358
2359
2360 /*
2361  * APM support
2362  */
2363 static int m3_suspend(struct device *dev)
2364 {
2365         struct snd_card *card = dev_get_drvdata(dev);
2366         struct snd_m3 *chip = card->private_data;
2367         int i, dsp_index;
2368
2369         if (chip->suspend_mem == NULL)
2370                 return 0;
2371
2372         chip->in_suspend = 1;
2373         cancel_work_sync(&chip->hwvol_work);
2374         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2375         snd_ac97_suspend(chip->ac97);
2376
2377         msleep(10); /* give the assp a chance to idle.. */
2378
2379         snd_m3_assp_halt(chip);
2380
2381         /* save dsp image */
2382         dsp_index = 0;
2383         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2384                 chip->suspend_mem[dsp_index++] =
2385                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2386         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2387                 chip->suspend_mem[dsp_index++] =
2388                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2389         return 0;
2390 }
2391
2392 static int m3_resume(struct device *dev)
2393 {
2394         struct snd_card *card = dev_get_drvdata(dev);
2395         struct snd_m3 *chip = card->private_data;
2396         int i, dsp_index;
2397
2398         if (chip->suspend_mem == NULL)
2399                 return 0;
2400
2401         /* first lets just bring everything back. .*/
2402         snd_m3_outw(chip, 0, 0x54);
2403         snd_m3_outw(chip, 0, 0x56);
2404
2405         snd_m3_chip_init(chip);
2406         snd_m3_assp_halt(chip);
2407         snd_m3_ac97_reset(chip);
2408
2409         /* restore dsp image */
2410         dsp_index = 0;
2411         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2412                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2413                                   chip->suspend_mem[dsp_index++]);
2414         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2415                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2416                                   chip->suspend_mem[dsp_index++]);
2417
2418         /* tell the dma engine to restart itself */
2419         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2420                           KDATA_DMA_ACTIVE, 0);
2421
2422         /* restore ac97 registers */
2423         snd_ac97_resume(chip->ac97);
2424
2425         snd_m3_assp_continue(chip);
2426         snd_m3_enable_ints(chip);
2427         snd_m3_amp_enable(chip, 1);
2428
2429         snd_m3_hv_init(chip);
2430
2431         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2432         chip->in_suspend = 0;
2433         return 0;
2434 }
2435
2436 static DEFINE_SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2437
2438 #ifdef CONFIG_SND_MAESTRO3_INPUT
2439 static int snd_m3_input_register(struct snd_m3 *chip)
2440 {
2441         struct input_dev *input_dev;
2442         int err;
2443
2444         input_dev = devm_input_allocate_device(&chip->pci->dev);
2445         if (!input_dev)
2446                 return -ENOMEM;
2447
2448         snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2449                  pci_name(chip->pci));
2450
2451         input_dev->name = chip->card->driver;
2452         input_dev->phys = chip->phys;
2453         input_dev->id.bustype = BUS_PCI;
2454         input_dev->id.vendor  = chip->pci->vendor;
2455         input_dev->id.product = chip->pci->device;
2456         input_dev->dev.parent = &chip->pci->dev;
2457
2458         __set_bit(EV_KEY, input_dev->evbit);
2459         __set_bit(KEY_MUTE, input_dev->keybit);
2460         __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2461         __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2462
2463         err = input_register_device(input_dev);
2464         if (err)
2465                 return err;
2466
2467         chip->input_dev = input_dev;
2468         return 0;
2469 }
2470 #endif /* CONFIG_INPUT */
2471
2472 /*
2473  */
2474
2475 static int
2476 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2477               int enable_amp,
2478               int amp_gpio)
2479 {
2480         struct snd_m3 *chip = card->private_data;
2481         int i, err;
2482         const struct snd_pci_quirk *quirk;
2483
2484         if (pcim_enable_device(pci))
2485                 return -EIO;
2486
2487         /* check, if we can restrict PCI DMA transfers to 28 bits */
2488         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) {
2489                 dev_err(card->dev,
2490                         "architecture does not support 28bit PCI busmaster DMA\n");
2491                 return -ENXIO;
2492         }
2493
2494         spin_lock_init(&chip->reg_lock);
2495
2496         switch (pci->device) {
2497         case PCI_DEVICE_ID_ESS_ALLEGRO:
2498         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2499         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2500         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2501                 chip->allegro_flag = 1;
2502                 break;
2503         }
2504
2505         chip->card = card;
2506         chip->pci = pci;
2507         chip->irq = -1;
2508         INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2509         card->private_free = snd_m3_free;
2510
2511         chip->external_amp = enable_amp;
2512         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2513                 chip->amp_gpio = amp_gpio;
2514         else {
2515                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2516                 if (quirk) {
2517                         dev_info(card->dev, "set amp-gpio for '%s'\n",
2518                                  snd_pci_quirk_name(quirk));
2519                         chip->amp_gpio = quirk->value;
2520                 } else if (chip->allegro_flag)
2521                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2522                 else /* presumably this is for all 'maestro3's.. */
2523                         chip->amp_gpio = GPO_EXT_AMP_M3;
2524         }
2525
2526         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2527         if (quirk) {
2528                 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2529                          snd_pci_quirk_name(quirk));
2530                 chip->irda_workaround = 1;
2531         }
2532         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2533         if (quirk)
2534                 chip->hv_config = quirk->value;
2535         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2536                 chip->is_omnibook = 1;
2537
2538         chip->num_substreams = NR_DSPS;
2539         chip->substreams = devm_kcalloc(&pci->dev, chip->num_substreams,
2540                                         sizeof(struct m3_dma), GFP_KERNEL);
2541         if (!chip->substreams)
2542                 return -ENOMEM;
2543
2544         err = reject_firmware(&chip->assp_kernel_image,
2545                                "/*(DEBLOBBED)*/", &pci->dev);
2546         if (err < 0)
2547                 return err;
2548
2549         err = reject_firmware(&chip->assp_minisrc_image,
2550                                "/*(DEBLOBBED)*/", &pci->dev);
2551         if (err < 0)
2552                 return err;
2553
2554         err = pci_request_regions(pci, card->driver);
2555         if (err < 0)
2556                 return err;
2557
2558         chip->iobase = pci_resource_start(pci, 0);
2559
2560         /* just to be sure */
2561         pci_set_master(pci);
2562
2563         snd_m3_chip_init(chip);
2564         snd_m3_assp_halt(chip);
2565
2566         snd_m3_ac97_reset(chip);
2567
2568         snd_m3_amp_enable(chip, 1);
2569
2570         snd_m3_hv_init(chip);
2571
2572         if (devm_request_irq(&pci->dev, pci->irq, snd_m3_interrupt, IRQF_SHARED,
2573                              KBUILD_MODNAME, chip)) {
2574                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2575                 return -ENOMEM;
2576         }
2577         chip->irq = pci->irq;
2578         card->sync_irq = chip->irq;
2579
2580         if (IS_ENABLED(CONFIG_PM_SLEEP)) {
2581                 chip->suspend_mem =
2582                         vmalloc(array_size(sizeof(u16),
2583                                            REV_B_CODE_MEMORY_LENGTH +
2584                                            REV_B_DATA_MEMORY_LENGTH));
2585                 if (!chip->suspend_mem)
2586                         dev_warn(card->dev, "can't allocate apm buffer\n");
2587         }
2588
2589         err = snd_m3_mixer(chip);
2590         if (err < 0)
2591                 return err;
2592
2593         for (i = 0; i < chip->num_substreams; i++) {
2594                 struct m3_dma *s = &chip->substreams[i];
2595                 err = snd_m3_assp_client_init(chip, s, i);
2596                 if (err < 0)
2597                         return err;
2598         }
2599
2600         err = snd_m3_pcm(chip, 0);
2601         if (err < 0)
2602                 return err;
2603
2604 #ifdef CONFIG_SND_MAESTRO3_INPUT
2605         if (chip->hv_config & HV_CTRL_ENABLE) {
2606                 err = snd_m3_input_register(chip);
2607                 if (err)
2608                         dev_warn(card->dev,
2609                                  "Input device registration failed with error %i",
2610                                  err);
2611         }
2612 #endif
2613
2614         snd_m3_enable_ints(chip);
2615         snd_m3_assp_continue(chip);
2616
2617         return 0;
2618 }
2619
2620 /*
2621  */
2622 static int
2623 __snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2624 {
2625         static int dev;
2626         struct snd_card *card;
2627         struct snd_m3 *chip;
2628         int err;
2629
2630         /* don't pick up modems */
2631         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2632                 return -ENODEV;
2633
2634         if (dev >= SNDRV_CARDS)
2635                 return -ENODEV;
2636         if (!enable[dev]) {
2637                 dev++;
2638                 return -ENOENT;
2639         }
2640
2641         err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2642                                 sizeof(*chip), &card);
2643         if (err < 0)
2644                 return err;
2645         chip = card->private_data;
2646
2647         switch (pci->device) {
2648         case PCI_DEVICE_ID_ESS_ALLEGRO:
2649         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2650                 strcpy(card->driver, "Allegro");
2651                 break;
2652         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2653         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2654                 strcpy(card->driver, "Canyon3D-2");
2655                 break;
2656         default:
2657                 strcpy(card->driver, "Maestro3");
2658                 break;
2659         }
2660
2661         err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev]);
2662         if (err < 0)
2663                 return err;
2664
2665         sprintf(card->shortname, "ESS %s PCI", card->driver);
2666         sprintf(card->longname, "%s at 0x%lx, irq %d",
2667                 card->shortname, chip->iobase, chip->irq);
2668
2669         err = snd_card_register(card);
2670         if (err < 0)
2671                 return err;
2672
2673 #if 0 /* TODO: not supported yet */
2674         /* TODO enable MIDI IRQ and I/O */
2675         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2676                                   chip->iobase + MPU401_DATA_PORT,
2677                                   MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2678                                   -1, &chip->rmidi);
2679         if (err < 0)
2680                 dev_warn(card->dev, "no MIDI support.\n");
2681 #endif
2682
2683         pci_set_drvdata(pci, card);
2684         dev++;
2685         return 0;
2686 }
2687
2688 static int
2689 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2690 {
2691         return snd_card_free_on_error(&pci->dev, __snd_m3_probe(pci, pci_id));
2692 }
2693
2694 static struct pci_driver m3_driver = {
2695         .name = KBUILD_MODNAME,
2696         .id_table = snd_m3_ids,
2697         .probe = snd_m3_probe,
2698         .driver = {
2699                 .pm = &m3_pm,
2700         },
2701 };
2702
2703 module_pci_driver(m3_driver);