1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * ALSA driver for the digigram lx6464es interface
7 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
10 /* #define RMH_DEBUG 1 */
12 #include <linux/bitops.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
20 /* low-level register access */
22 static const unsigned long dsp_port_offsets[] = {
55 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
57 void __iomem *base_address = chip->port_dsp_bar;
58 return base_address + dsp_port_offsets[port]*4;
61 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
63 void __iomem *address = lx_dsp_register(chip, port);
64 return ioread32(address);
67 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data,
70 u32 __iomem *address = lx_dsp_register(chip, port);
73 /* we cannot use memcpy_fromio */
74 for (i = 0; i != len; ++i)
75 data[i] = ioread32(address + i);
79 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
81 void __iomem *address = lx_dsp_register(chip, port);
82 iowrite32(data, address);
85 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port,
86 const u32 *data, u32 len)
88 u32 __iomem *address = lx_dsp_register(chip, port);
91 /* we cannot use memcpy_to */
92 for (i = 0; i != len; ++i)
93 iowrite32(data[i], address + i);
97 static const unsigned long plx_port_offsets[] = {
112 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
114 void __iomem *base_address = chip->port_plx_remapped;
115 return base_address + plx_port_offsets[port];
118 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
120 void __iomem *address = lx_plx_register(chip, port);
121 return ioread32(address);
124 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
126 void __iomem *address = lx_plx_register(chip, port);
127 iowrite32(data, address);
132 #ifdef CONFIG_SND_DEBUG
133 #define CMD_NAME(a) a
135 #define CMD_NAME(a) NULL
138 #define Reg_CSM_MR 0x00000002
139 #define Reg_CSM_MC 0x00000001
141 struct dsp_cmd_info {
142 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits
144 u16 dcCmdLength; /* Command length in words of 24 bits.*/
145 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for
147 u16 dcStatusLength; /* Status length (if fixed).*/
152 Initialization and control data for the Microblaze interface
154 the opcode field of the command set at the proper offset
156 the number of command words
158 offset in the status registers: 0 means that the return value may be
159 different from 0, and must be read
161 the number of status words (in addition to the return value)
164 static const struct dsp_cmd_info dsp_commands[] =
166 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/
167 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
168 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/
169 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") },
170 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/
171 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
172 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/
173 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
174 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/
175 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
176 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/
177 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") },
178 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/
179 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
180 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/
181 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
182 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/
183 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") },
184 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/
185 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
186 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/
187 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") },
188 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/
189 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
190 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/
191 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
192 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/
193 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
194 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/
195 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") },
196 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/
197 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
198 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/
199 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") },
200 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/
201 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") },
202 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/
203 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") },
204 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/
205 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
208 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
210 snd_BUG_ON(cmd >= CMD_14_INVALID);
212 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
213 rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
214 rmh->stat_len = dsp_commands[cmd].dcStatusLength;
215 rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
217 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
219 #ifdef CONFIG_SND_DEBUG
220 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
228 #define LXRMH "lx6464es rmh: "
229 static void lx_message_dump(struct lx_rmh *rmh)
231 u8 idx = rmh->cmd_idx;
234 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
236 for (i = 0; i != rmh->cmd_len; ++i)
237 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
239 for (i = 0; i != rmh->stat_len; ++i)
240 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
244 static inline void lx_message_dump(struct lx_rmh *rmh)
250 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
251 #define XILINX_TIMEOUT_MS 40
252 #define XILINX_POLL_NO_SLEEP 100
253 #define XILINX_POLL_ITERATIONS 150
256 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
258 u32 reg = ED_DSP_TIMED_OUT;
261 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
262 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg);
267 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
269 /* MicoBlaze gogogo */
270 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
272 /* wait for device to answer */
273 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
274 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
275 if (rmh->dsp_stat == 0)
276 reg = lx_dsp_reg_read(chip, eReg_CRM1);
279 goto polling_successful;
283 dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! "
287 if ((reg & ERROR_VALUE) == 0) {
290 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
291 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
295 dev_err(chip->card->dev, "rmh error: %08x\n", reg);
297 /* clear Reg_CSM_MR */
298 lx_dsp_reg_write(chip, eReg_CSM, 0);
301 case ED_DSP_TIMED_OUT:
302 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n");
306 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n");
310 lx_message_dump(rmh);
316 /* low-level dsp access */
317 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
321 mutex_lock(&chip->msg_lock);
323 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
324 ret = lx_message_send_atomic(chip, &chip->rmh);
326 *rdsp_version = chip->rmh.stat[1];
327 mutex_unlock(&chip->msg_lock);
331 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
338 mutex_lock(&chip->msg_lock);
340 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
341 ret = lx_message_send_atomic(chip, &chip->rmh);
344 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
345 freq = freq_raw & XES_FREQ_COUNT8_MASK;
347 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
348 (freq > XES_FREQ_COUNT8_44_MIN))
349 frequency = 0; /* unknown */
350 else if (freq >= XES_FREQ_COUNT8_44_MAX)
356 mutex_unlock(&chip->msg_lock);
358 *rfreq = frequency * chip->freq_ratio;
363 int lx_dsp_get_mac(struct lx6464es *chip)
367 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
368 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
370 /* todo: endianess handling */
371 chip->mac_address[5] = ((u8 *)(&maclsb))[0];
372 chip->mac_address[4] = ((u8 *)(&maclsb))[1];
373 chip->mac_address[3] = ((u8 *)(&maclsb))[2];
374 chip->mac_address[2] = ((u8 *)(&macmsb))[0];
375 chip->mac_address[1] = ((u8 *)(&macmsb))[1];
376 chip->mac_address[0] = ((u8 *)(&macmsb))[2];
382 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
386 mutex_lock(&chip->msg_lock);
388 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
389 chip->rmh.cmd[0] |= gran;
391 ret = lx_message_send_atomic(chip, &chip->rmh);
392 mutex_unlock(&chip->msg_lock);
396 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
400 mutex_lock(&chip->msg_lock);
402 lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
403 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
405 ret = lx_message_send_atomic(chip, &chip->rmh);
408 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
410 mutex_unlock(&chip->msg_lock);
414 #define PIPE_INFO_TO_CMD(capture, pipe) \
415 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
419 /* low-level pipe handling */
420 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
424 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
426 mutex_lock(&chip->msg_lock);
427 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
429 chip->rmh.cmd[0] |= pipe_cmd;
430 chip->rmh.cmd[0] |= channels;
432 err = lx_message_send_atomic(chip, &chip->rmh);
433 mutex_unlock(&chip->msg_lock);
436 dev_err(chip->card->dev, "could not allocate pipe\n");
441 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
444 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
446 mutex_lock(&chip->msg_lock);
447 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
449 chip->rmh.cmd[0] |= pipe_cmd;
451 err = lx_message_send_atomic(chip, &chip->rmh);
452 mutex_unlock(&chip->msg_lock);
457 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
458 u32 *r_needed, u32 *r_freed, u32 *size_array)
461 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
463 #ifdef CONFIG_SND_DEBUG
465 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
471 mutex_lock(&chip->msg_lock);
472 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
474 chip->rmh.cmd[0] |= pipe_cmd;
476 err = lx_message_send_atomic(chip, &chip->rmh);
480 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
481 u32 stat = chip->rmh.stat[i];
482 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
486 size_array[i] = stat & MASK_DATA_SIZE;
487 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
493 dev_dbg(chip->card->dev,
494 "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
495 *r_needed, *r_freed);
496 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
497 for (i = 0; i != chip->rmh.stat_len; ++i)
498 dev_dbg(chip->card->dev,
499 " stat[%d]: %x, %x\n", i,
501 chip->rmh.stat[i] & MASK_DATA_SIZE);
505 mutex_unlock(&chip->msg_lock);
510 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
513 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
515 mutex_lock(&chip->msg_lock);
516 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
518 chip->rmh.cmd[0] |= pipe_cmd;
520 err = lx_message_send_atomic(chip, &chip->rmh);
522 mutex_unlock(&chip->msg_lock);
526 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
529 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
531 mutex_lock(&chip->msg_lock);
532 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
534 chip->rmh.cmd[0] |= pipe_cmd;
536 err = lx_message_send_atomic(chip, &chip->rmh);
538 mutex_unlock(&chip->msg_lock);
543 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
547 err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
551 err = lx_pipe_toggle_state(chip, pipe, is_capture);
556 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
560 err = lx_pipe_wait_for_start(chip, pipe, is_capture);
564 err = lx_pipe_toggle_state(chip, pipe, is_capture);
570 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
574 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
576 mutex_lock(&chip->msg_lock);
577 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
579 chip->rmh.cmd[0] |= pipe_cmd;
580 chip->rmh.stat_len = 2; /* need all words here! */
582 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
585 dev_err(chip->card->dev,
586 "could not query pipe's sample count\n");
588 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
590 + chip->rmh.stat[1]; /* lo part */
593 mutex_unlock(&chip->msg_lock);
597 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
600 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
602 mutex_lock(&chip->msg_lock);
603 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
605 chip->rmh.cmd[0] |= pipe_cmd;
607 err = lx_message_send_atomic(chip, &chip->rmh);
610 dev_err(chip->card->dev, "could not query pipe's state\n");
612 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
614 mutex_unlock(&chip->msg_lock);
618 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
619 int is_capture, u16 state)
623 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
625 for (i = 0; i != 50; ++i) {
627 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state);
632 if (!err && current_state == state)
641 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
643 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
646 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
648 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
651 /* low-level stream handling */
652 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
653 int is_capture, enum stream_state_t state)
656 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
658 mutex_lock(&chip->msg_lock);
659 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
661 chip->rmh.cmd[0] |= pipe_cmd;
662 chip->rmh.cmd[0] |= state;
664 err = lx_message_send_atomic(chip, &chip->rmh);
665 mutex_unlock(&chip->msg_lock);
670 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
671 u32 pipe, int is_capture)
674 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
675 u32 channels = runtime->channels;
677 mutex_lock(&chip->msg_lock);
678 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
680 chip->rmh.cmd[0] |= pipe_cmd;
682 if (runtime->sample_bits == 16)
684 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
686 if (snd_pcm_format_little_endian(runtime->format))
687 /* little endian/intel format */
688 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
690 chip->rmh.cmd[0] |= channels-1;
692 err = lx_message_send_atomic(chip, &chip->rmh);
693 mutex_unlock(&chip->msg_lock);
698 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
702 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
704 mutex_lock(&chip->msg_lock);
705 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
707 chip->rmh.cmd[0] |= pipe_cmd;
709 err = lx_message_send_atomic(chip, &chip->rmh);
711 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
713 mutex_unlock(&chip->msg_lock);
717 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
721 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
723 mutex_lock(&chip->msg_lock);
724 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
726 chip->rmh.cmd[0] |= pipe_cmd;
728 err = lx_message_send_atomic(chip, &chip->rmh);
730 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
732 + chip->rmh.stat[1]; /* lo part */
734 mutex_unlock(&chip->msg_lock);
738 /* low-level buffer handling */
739 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
740 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
744 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
746 mutex_lock(&chip->msg_lock);
747 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
749 chip->rmh.cmd[0] |= pipe_cmd;
750 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
752 /* todo: pause request, circular buffer */
754 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
755 chip->rmh.cmd[2] = buf_address_lo;
757 if (buf_address_hi) {
758 chip->rmh.cmd_len = 4;
759 chip->rmh.cmd[3] = buf_address_hi;
760 chip->rmh.cmd[0] |= BF_64BITS_ADR;
763 err = lx_message_send_atomic(chip, &chip->rmh);
766 *r_buffer_index = chip->rmh.stat[0];
770 if (err == EB_RBUFFERS_TABLE_OVERFLOW)
771 dev_err(chip->card->dev,
772 "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
774 if (err == EB_INVALID_STREAM)
775 dev_err(chip->card->dev,
776 "lx_buffer_give EB_INVALID_STREAM\n");
778 if (err == EB_CMD_REFUSED)
779 dev_err(chip->card->dev,
780 "lx_buffer_give EB_CMD_REFUSED\n");
783 mutex_unlock(&chip->msg_lock);
787 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
791 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
793 mutex_lock(&chip->msg_lock);
794 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
796 chip->rmh.cmd[0] |= pipe_cmd;
797 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
798 * microblaze will seek for it */
800 err = lx_message_send_atomic(chip, &chip->rmh);
803 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE;
805 mutex_unlock(&chip->msg_lock);
809 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
813 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
815 mutex_lock(&chip->msg_lock);
816 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
818 chip->rmh.cmd[0] |= pipe_cmd;
819 chip->rmh.cmd[0] |= buffer_index;
821 err = lx_message_send_atomic(chip, &chip->rmh);
823 mutex_unlock(&chip->msg_lock);
828 /* low-level gain/peak handling
830 * \todo: can we unmute capture/playback channels independently?
833 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
836 /* bit set to 1: channel muted */
837 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
839 mutex_lock(&chip->msg_lock);
840 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
842 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
844 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */
845 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
847 dev_dbg(chip->card->dev,
848 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
851 err = lx_message_send_atomic(chip, &chip->rmh);
853 mutex_unlock(&chip->msg_lock);
857 static const u32 peak_map[] = {
858 0x00000109, /* -90.308dB */
859 0x0000083B, /* -72.247dB */
860 0x000020C4, /* -60.205dB */
861 0x00008273, /* -48.030dB */
862 0x00020756, /* -36.005dB */
863 0x00040C37, /* -30.001dB */
864 0x00081385, /* -24.002dB */
865 0x00101D3F, /* -18.000dB */
866 0x0016C310, /* -15.000dB */
867 0x002026F2, /* -12.001dB */
868 0x002D6A86, /* -9.000dB */
869 0x004026E6, /* -6.004dB */
870 0x005A9DF6, /* -3.000dB */
871 0x0065AC8B, /* -2.000dB */
872 0x00721481, /* -1.000dB */
876 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
882 mutex_lock(&chip->msg_lock);
883 for (i = 0; i < channels; i += 4) {
886 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
887 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
889 err = lx_message_send_atomic(chip, &chip->rmh);
892 s0 = peak_map[chip->rmh.stat[0] & 0x0F];
893 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf];
894 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf];
895 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf];
897 s0 = s1 = s2 = s3 = 0;
907 mutex_unlock(&chip->msg_lock);
911 /* interrupt handling */
912 #define PCX_IRQ_NONE 0
913 #define IRQCS_ACTIVE_PCIDB BIT(13)
914 #define IRQCS_ENABLE_PCIIRQ BIT(8)
915 #define IRQCS_ENABLE_PCIDB BIT(9)
917 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
919 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
921 /* Test if PCI Doorbell interrupt is active */
922 if (irqcs & IRQCS_ACTIVE_PCIDB) {
924 irqcs = PCX_IRQ_NONE;
926 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
929 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
937 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
938 int *r_async_pending, int *r_async_escmd)
941 u32 irqsrc = lx_interrupt_test_ack(chip);
943 if (irqsrc == PCX_IRQ_NONE)
948 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
949 * (set by xilinx) + EOB */
951 if (irq_async & MASK_SYS_STATUS_ESA) {
952 irq_async &= ~MASK_SYS_STATUS_ESA;
957 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */
958 *r_async_pending = 1;
964 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
966 u64 *r_notified_in_pipe_mask,
967 u64 *r_notified_out_pipe_mask)
970 u32 stat[9]; /* answer from CMD_04_GET_EVENT */
972 /* We can optimize this to not read dumb events.
973 * Answer words are in the following order:
974 * Stat[0] general status
975 * Stat[1] end of buffer OUT pF
976 * Stat[2] end of buffer OUT pf
977 * Stat[3] end of buffer IN pF
978 * Stat[4] end of buffer IN pf
979 * Stat[5] MSB underrun
980 * Stat[6] LSB underrun
981 * Stat[7] MSB overrun
982 * Stat[8] LSB overrun
985 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
986 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
988 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
990 err = lx_dsp_read_async_events(chip, stat);
995 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
997 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n",
998 *r_notified_in_pipe_mask);
1000 if (eb_pending_out) {
1001 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1003 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n",
1004 *r_notified_out_pipe_mask);
1007 /* todo: handle xrun notification */
1012 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1013 struct lx_stream *lx_stream)
1015 struct snd_pcm_substream *substream = lx_stream->stream;
1016 const unsigned int is_capture = lx_stream->is_capture;
1019 const u32 channels = substream->runtime->channels;
1020 const u32 bytes_per_frame = channels * 3;
1021 const u32 period_size = substream->runtime->period_size;
1022 const u32 period_bytes = period_size * bytes_per_frame;
1023 const u32 pos = lx_stream->frame_pos;
1024 const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1027 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1030 u32 buffer_index = 0;
1033 u32 size_array[MAX_STREAM_BUFFER];
1035 dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n");
1037 mutex_lock(&chip->lock);
1039 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1040 dev_dbg(chip->card->dev,
1041 "interrupt: needed %d, freed %d\n", needed, freed);
1043 unpack_pointer(buf, &buf_lo, &buf_hi);
1044 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1046 dev_dbg(chip->card->dev,
1047 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n",
1048 buffer_index, (unsigned long)buf, period_bytes);
1050 lx_stream->frame_pos = next_pos;
1051 mutex_unlock(&chip->lock);
1056 irqreturn_t lx_interrupt(int irq, void *dev_id)
1058 struct lx6464es *chip = dev_id;
1059 int async_pending, async_escmd;
1061 bool wake_thread = false;
1063 dev_dbg(chip->card->dev,
1064 "**************************************************\n");
1066 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1067 dev_dbg(chip->card->dev, "IRQ_NONE\n");
1068 return IRQ_NONE; /* this device did not cause the interrupt */
1071 if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1074 if (irqsrc & MASK_SYS_STATUS_EOBI)
1075 dev_dbg(chip->card->dev, "interrupt: EOBI\n");
1077 if (irqsrc & MASK_SYS_STATUS_EOBO)
1078 dev_dbg(chip->card->dev, "interrupt: EOBO\n");
1080 if (irqsrc & MASK_SYS_STATUS_URUN)
1081 dev_dbg(chip->card->dev, "interrupt: URUN\n");
1083 if (irqsrc & MASK_SYS_STATUS_ORUN)
1084 dev_dbg(chip->card->dev, "interrupt: ORUN\n");
1086 if (async_pending) {
1088 chip->irqsrc = irqsrc;
1092 /* backdoor for ethersound commands
1094 * for now, we do not need this
1098 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n");
1101 return wake_thread ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1104 irqreturn_t lx_threaded_irq(int irq, void *dev_id)
1106 struct lx6464es *chip = dev_id;
1107 u64 notified_in_pipe_mask = 0;
1108 u64 notified_out_pipe_mask = 0;
1112 /* handle async events */
1113 err = lx_interrupt_handle_async_events(chip, chip->irqsrc,
1115 ¬ified_in_pipe_mask,
1116 ¬ified_out_pipe_mask);
1118 dev_err(chip->card->dev, "error handling async events\n");
1120 if (notified_in_pipe_mask) {
1121 struct lx_stream *lx_stream = &chip->capture_stream;
1123 dev_dbg(chip->card->dev,
1124 "requesting audio transfer for capture\n");
1125 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1127 dev_err(chip->card->dev,
1128 "cannot request new buffer for capture\n");
1129 snd_pcm_period_elapsed(lx_stream->stream);
1132 if (notified_out_pipe_mask) {
1133 struct lx_stream *lx_stream = &chip->playback_stream;
1135 dev_dbg(chip->card->dev,
1136 "requesting audio transfer for playback\n");
1137 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1139 dev_err(chip->card->dev,
1140 "cannot request new buffer for playback\n");
1141 snd_pcm_period_elapsed(lx_stream->stream);
1148 static void lx_irq_set(struct lx6464es *chip, int enable)
1150 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1152 /* enable/disable interrupts
1154 * Set the Doorbell and PCI interrupt enable bits
1158 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1160 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1161 lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1164 void lx_irq_enable(struct lx6464es *chip)
1166 dev_dbg(chip->card->dev, "->lx_irq_enable\n");
1167 lx_irq_set(chip, 1);
1170 void lx_irq_disable(struct lx6464es *chip)
1172 dev_dbg(chip->card->dev, "->lx_irq_disable\n");
1173 lx_irq_set(chip, 0);