sound/pci/lx6464es/lx_core.c

   1 /* -*- linux-c -*- *
   2  *
   3  * ALSA driver for the digigram lx6464es interface
   4  * low-level interface
   5  *
   6  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, write to
  20  * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  21  * Boston, MA 02111-1307, USA.
  22  *
  23  */
  24
  25 /* #define RMH_DEBUG 1 */
  26
  27 #include <linux/bitops.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31
  32 #include "lx6464es.h"
  33 #include "lx_core.h"
  34
  35 /* low-level register access */
  36
  37 static const unsigned long dsp_port_offsets[] = {
  38         0,
  39         0x400,
  40         0x401,
  41         0x402,
  42         0x403,
  43         0x404,
  44         0x405,
  45         0x406,
  46         0x407,
  47         0x408,
  48         0x409,
  49         0x40a,
  50         0x40b,
  51         0x40c,
  52
  53         0x410,
  54         0x411,
  55         0x412,
  56         0x413,
  57         0x414,
  58         0x415,
  59         0x416,
  60
  61         0x420,
  62         0x430,
  63         0x431,
  64         0x432,
  65         0x433,
  66         0x434,
  67         0x440
  68 };
  69
  70 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
  71 {
  72         void __iomem *base_address = chip->port_dsp_bar;
  73         return base_address + dsp_port_offsets[port]*4;
  74 }
  75
  76 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
  77 {
  78         void __iomem *address = lx_dsp_register(chip, port);
  79         return ioread32(address);
  80 }
  81
  82 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data,
  83                                u32 len)
  84 {
  85         u32 __iomem *address = lx_dsp_register(chip, port);
  86         int i;
  87
  88         /* we cannot use memcpy_fromio */
  89         for (i = 0; i != len; ++i)
  90                 data[i] = ioread32(address + i);
  91 }
  92
  93
  94 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
  95 {
  96         void __iomem *address = lx_dsp_register(chip, port);
  97         iowrite32(data, address);
  98 }
  99
 100 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port,
 101                                 const u32 *data, u32 len)
 102 {
 103         u32 __iomem *address = lx_dsp_register(chip, port);
 104         int i;
 105
 106         /* we cannot use memcpy_to */
 107         for (i = 0; i != len; ++i)
 108                 iowrite32(data[i], address + i);
 109 }
 110
 111
 112 static const unsigned long plx_port_offsets[] = {
 113         0x04,
 114         0x40,
 115         0x44,
 116         0x48,
 117         0x4c,
 118         0x50,
 119         0x54,
 120         0x58,
 121         0x5c,
 122         0x64,
 123         0x68,
 124         0x6C
 125 };
 126
 127 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
 128 {
 129         void __iomem *base_address = chip->port_plx_remapped;
 130         return base_address + plx_port_offsets[port];
 131 }
 132
 133 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
 134 {
 135         void __iomem *address = lx_plx_register(chip, port);
 136         return ioread32(address);
 137 }
 138
 139 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
 140 {
 141         void __iomem *address = lx_plx_register(chip, port);
 142         iowrite32(data, address);
 143 }
 144
 145 /* rmh */
 146
 147 #ifdef CONFIG_SND_DEBUG
 148 #define CMD_NAME(a) a
 149 #else
 150 #define CMD_NAME(a) NULL
 151 #endif
 152
 153 #define Reg_CSM_MR                      0x00000002
 154 #define Reg_CSM_MC                      0x00000001
 155
 156 struct dsp_cmd_info {
 157         u32    dcCodeOp;        /* Op Code of the command (usually 1st 24-bits
 158                                  * word).*/
 159         u16    dcCmdLength;     /* Command length in words of 24 bits.*/
 160         u16    dcStatusType;    /* Status type: 0 for fixed length, 1 for
 161                                  * random. */
 162         u16    dcStatusLength;  /* Status length (if fixed).*/
 163         char  *dcOpName;
 164 };
 165
 166 /*
 167   Initialization and control data for the Microblaze interface
 168   - OpCode:
 169     the opcode field of the command set at the proper offset
 170   - CmdLength
 171     the number of command words
 172   - StatusType
 173     offset in the status registers: 0 means that the return value may be
 174     different from 0, and must be read
 175   - StatusLength
 176     the number of status words (in addition to the return value)
 177 */
 178
 179 static struct dsp_cmd_info dsp_commands[] =
 180 {
 181         { (CMD_00_INFO_DEBUG << OPCODE_OFFSET)                  , 1 /*custom*/
 182           , 1   , 0 /**/                    , CMD_NAME("INFO_DEBUG") },
 183         { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET)                 , 1 /**/
 184           , 1      , 2 /**/                 , CMD_NAME("GET_SYS_CFG") },
 185         { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET)             , 1 /**/
 186           , 1      , 0 /**/                 , CMD_NAME("SET_GRANULARITY") },
 187         { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET)               , 1 /**/
 188           , 1      , 0 /**/                 , CMD_NAME("SET_TIMER_IRQ") },
 189         { (CMD_04_GET_EVENT << OPCODE_OFFSET)                   , 1 /**/
 190           , 1      , 0 /*up to 10*/     , CMD_NAME("GET_EVENT") },
 191         { (CMD_05_GET_PIPES << OPCODE_OFFSET)                   , 1 /**/
 192           , 1      , 2 /*up to 4*/      , CMD_NAME("GET_PIPES") },
 193         { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET)               , 1 /**/
 194           , 0      , 0 /**/                 , CMD_NAME("ALLOCATE_PIPE") },
 195         { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET)                , 1 /**/
 196           , 0      , 0 /**/                 , CMD_NAME("RELEASE_PIPE") },
 197         { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET)                 , 1 /**/
 198           , 1      , MAX_STREAM_BUFFER  , CMD_NAME("ASK_BUFFERS") },
 199         { (CMD_09_STOP_PIPE << OPCODE_OFFSET)                   , 1 /**/
 200           , 0      , 0 /*up to 2*/      , CMD_NAME("STOP_PIPE") },
 201         { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET)          , 1 /**/
 202           , 1      , 1 /*up to 2*/      , CMD_NAME("GET_PIPE_SPL_COUNT") },
 203         { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET)           , 1 /*up to 5*/
 204           , 1      , 0 /**/                 , CMD_NAME("TOGGLE_PIPE_STATE") },
 205         { (CMD_0C_DEF_STREAM << OPCODE_OFFSET)                  , 1 /*up to 4*/
 206           , 1      , 0 /**/                 , CMD_NAME("DEF_STREAM") },
 207         { (CMD_0D_SET_MUTE  << OPCODE_OFFSET)                   , 3 /**/
 208           , 1      , 0 /**/                 , CMD_NAME("SET_MUTE") },
 209         { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET)        , 1/**/
 210           , 1      , 2 /**/                 , CMD_NAME("GET_STREAM_SPL_COUNT") },
 211         { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET)               , 3 /*up to 4*/
 212           , 0      , 1 /**/                 , CMD_NAME("UPDATE_BUFFER") },
 213         { (CMD_10_GET_BUFFER << OPCODE_OFFSET)                  , 1 /**/
 214           , 1      , 4 /**/                 , CMD_NAME("GET_BUFFER") },
 215         { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET)               , 1 /**/
 216           , 1      , 1 /*up to 4*/      , CMD_NAME("CANCEL_BUFFER") },
 217         { (CMD_12_GET_PEAK << OPCODE_OFFSET)                    , 1 /**/
 218           , 1      , 1 /**/                 , CMD_NAME("GET_PEAK") },
 219         { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET)            , 1 /**/
 220           , 1      , 0 /**/                 , CMD_NAME("SET_STREAM_STATE") },
 221 };
 222
 223 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
 224 {
 225         snd_BUG_ON(cmd >= CMD_14_INVALID);
 226
 227         rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
 228         rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
 229         rmh->stat_len = dsp_commands[cmd].dcStatusLength;
 230         rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
 231         rmh->cmd_idx = cmd;
 232         memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
 233
 234 #ifdef CONFIG_SND_DEBUG
 235         memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
 236 #endif
 237 #ifdef RMH_DEBUG
 238         rmh->cmd_idx = cmd;
 239 #endif
 240 }
 241
 242 #ifdef RMH_DEBUG
 243 #define LXRMH "lx6464es rmh: "
 244 static void lx_message_dump(struct lx_rmh *rmh)
 245 {
 246         u8 idx = rmh->cmd_idx;
 247         int i;
 248
 249         snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
 250
 251         for (i = 0; i != rmh->cmd_len; ++i)
 252                 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
 253
 254         for (i = 0; i != rmh->stat_len; ++i)
 255                 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
 256         snd_printk("\n");
 257 }
 258 #else
 259 static inline void lx_message_dump(struct lx_rmh *rmh)
 260 {}
 261 #endif
 262
 263
 264
 265 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
 266 #define XILINX_TIMEOUT_MS       40
 267 #define XILINX_POLL_NO_SLEEP    100
 268 #define XILINX_POLL_ITERATIONS  150
 269
 270
 271 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
 272 {
 273         u32 reg = ED_DSP_TIMED_OUT;
 274         int dwloop;
 275
 276         if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
 277                 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg);
 278                 return -EBUSY;
 279         }
 280
 281         /* write command */
 282         lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
 283
 284         /* MicoBlaze gogogo */
 285         lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
 286
 287         /* wait for device to answer */
 288         for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
 289                 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
 290                         if (rmh->dsp_stat == 0)
 291                                 reg = lx_dsp_reg_read(chip, eReg_CRM1);
 292                         else
 293                                 reg = 0;
 294                         goto polling_successful;
 295                 } else
 296                         udelay(1);
 297         }
 298         dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! "
 299                    "polling failed\n");
 300
 301 polling_successful:
 302         if ((reg & ERROR_VALUE) == 0) {
 303                 /* read response */
 304                 if (rmh->stat_len) {
 305                         snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
 306                         lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
 307                                            rmh->stat_len);
 308                 }
 309         } else
 310                 dev_err(chip->card->dev, "rmh error: %08x\n", reg);
 311
 312         /* clear Reg_CSM_MR */
 313         lx_dsp_reg_write(chip, eReg_CSM, 0);
 314
 315         switch (reg) {
 316         case ED_DSP_TIMED_OUT:
 317                 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n");
 318                 return -ETIMEDOUT;
 319
 320         case ED_DSP_CRASHED:
 321                 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n");
 322                 return -EAGAIN;
 323         }
 324
 325         lx_message_dump(rmh);
 326
 327         return reg;
 328 }
 329
 330
 331 /* low-level dsp access */
 332 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
 333 {
 334         u16 ret;
 335
 336         mutex_lock(&chip->msg_lock);
 337
 338         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 339         ret = lx_message_send_atomic(chip, &chip->rmh);
 340
 341         *rdsp_version = chip->rmh.stat[1];
 342         mutex_unlock(&chip->msg_lock);
 343         return ret;
 344 }
 345
 346 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
 347 {
 348         u16 ret = 0;
 349         u32 freq_raw = 0;
 350         u32 freq = 0;
 351         u32 frequency = 0;
 352
 353         mutex_lock(&chip->msg_lock);
 354
 355         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 356         ret = lx_message_send_atomic(chip, &chip->rmh);
 357
 358         if (ret == 0) {
 359                 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
 360                 freq = freq_raw & XES_FREQ_COUNT8_MASK;
 361
 362                 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
 363                     (freq > XES_FREQ_COUNT8_44_MIN))
 364                         frequency = 0; /* unknown */
 365                 else if (freq >= XES_FREQ_COUNT8_44_MAX)
 366                         frequency = 44100;
 367                 else
 368                         frequency = 48000;
 369         }
 370
 371         mutex_unlock(&chip->msg_lock);
 372
 373         *rfreq = frequency * chip->freq_ratio;
 374
 375         return ret;
 376 }
 377
 378 int lx_dsp_get_mac(struct lx6464es *chip)
 379 {
 380         u32 macmsb, maclsb;
 381
 382         macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
 383         maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
 384
 385         /* todo: endianess handling */
 386         chip->mac_address[5] = ((u8 *)(&maclsb))[0];
 387         chip->mac_address[4] = ((u8 *)(&maclsb))[1];
 388         chip->mac_address[3] = ((u8 *)(&maclsb))[2];
 389         chip->mac_address[2] = ((u8 *)(&macmsb))[0];
 390         chip->mac_address[1] = ((u8 *)(&macmsb))[1];
 391         chip->mac_address[0] = ((u8 *)(&macmsb))[2];
 392
 393         return 0;
 394 }
 395
 396
 397 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
 398 {
 399         int ret;
 400
 401         mutex_lock(&chip->msg_lock);
 402
 403         lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
 404         chip->rmh.cmd[0] |= gran;
 405
 406         ret = lx_message_send_atomic(chip, &chip->rmh);
 407         mutex_unlock(&chip->msg_lock);
 408         return ret;
 409 }
 410
 411 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
 412 {
 413         int ret;
 414
 415         mutex_lock(&chip->msg_lock);
 416
 417         lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
 418         chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
 419
 420         ret = lx_message_send_atomic(chip, &chip->rmh);
 421
 422         if (!ret)
 423                 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
 424
 425         mutex_unlock(&chip->msg_lock);
 426         return ret;
 427 }
 428
 429 #define PIPE_INFO_TO_CMD(capture, pipe)                                 \
 430         ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
 431
 432
 433
 434 /* low-level pipe handling */
 435 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
 436                      int channels)
 437 {
 438         int err;
 439         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 440
 441         mutex_lock(&chip->msg_lock);
 442         lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
 443
 444         chip->rmh.cmd[0] |= pipe_cmd;
 445         chip->rmh.cmd[0] |= channels;
 446
 447         err = lx_message_send_atomic(chip, &chip->rmh);
 448         mutex_unlock(&chip->msg_lock);
 449
 450         if (err != 0)
 451                 dev_err(chip->card->dev, "could not allocate pipe\n");
 452
 453         return err;
 454 }
 455
 456 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
 457 {
 458         int err;
 459         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 460
 461         mutex_lock(&chip->msg_lock);
 462         lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
 463
 464         chip->rmh.cmd[0] |= pipe_cmd;
 465
 466         err = lx_message_send_atomic(chip, &chip->rmh);
 467         mutex_unlock(&chip->msg_lock);
 468
 469         return err;
 470 }
 471
 472 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
 473                   u32 *r_needed, u32 *r_freed, u32 *size_array)
 474 {
 475         int err;
 476         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 477
 478 #ifdef CONFIG_SND_DEBUG
 479         if (size_array)
 480                 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
 481 #endif
 482
 483         *r_needed = 0;
 484         *r_freed = 0;
 485
 486         mutex_lock(&chip->msg_lock);
 487         lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
 488
 489         chip->rmh.cmd[0] |= pipe_cmd;
 490
 491         err = lx_message_send_atomic(chip, &chip->rmh);
 492
 493         if (!err) {
 494                 int i;
 495                 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
 496                         u32 stat = chip->rmh.stat[i];
 497                         if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
 498                                 /* finished */
 499                                 *r_freed += 1;
 500                                 if (size_array)
 501                                         size_array[i] = stat & MASK_DATA_SIZE;
 502                         } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
 503                                    == 0)
 504                                 /* free */
 505                                 *r_needed += 1;
 506                 }
 507
 508                 dev_dbg(chip->card->dev,
 509                         "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
 510                             *r_needed, *r_freed);
 511                 for (i = 0; i < MAX_STREAM_BUFFER && i < chip->rmh.stat_len;
 512                      ++i) {
 513                         dev_dbg(chip->card->dev, "  stat[%d]: %x, %x\n", i,
 514                                 chip->rmh.stat[i],
 515                                 chip->rmh.stat[i] & MASK_DATA_SIZE);
 516                 }
 517         }
 518
 519         mutex_unlock(&chip->msg_lock);
 520         return err;
 521 }
 522
 523
 524 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
 525 {
 526         int err;
 527         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 528
 529         mutex_lock(&chip->msg_lock);
 530         lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
 531
 532         chip->rmh.cmd[0] |= pipe_cmd;
 533
 534         err = lx_message_send_atomic(chip, &chip->rmh);
 535
 536         mutex_unlock(&chip->msg_lock);
 537         return err;
 538 }
 539
 540 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
 541 {
 542         int err;
 543         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 544
 545         mutex_lock(&chip->msg_lock);
 546         lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
 547
 548         chip->rmh.cmd[0] |= pipe_cmd;
 549
 550         err = lx_message_send_atomic(chip, &chip->rmh);
 551
 552         mutex_unlock(&chip->msg_lock);
 553         return err;
 554 }
 555
 556
 557 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
 558 {
 559         int err;
 560
 561         err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
 562         if (err < 0)
 563                 return err;
 564
 565         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 566
 567         return err;
 568 }
 569
 570 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
 571 {
 572         int err = 0;
 573
 574         err = lx_pipe_wait_for_start(chip, pipe, is_capture);
 575         if (err < 0)
 576                 return err;
 577
 578         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 579
 580         return err;
 581 }
 582
 583
 584 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
 585                          u64 *rsample_count)
 586 {
 587         int err;
 588         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 589
 590         mutex_lock(&chip->msg_lock);
 591         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 592
 593         chip->rmh.cmd[0] |= pipe_cmd;
 594         chip->rmh.stat_len = 2; /* need all words here! */
 595
 596         err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
 597
 598         if (err != 0)
 599                 dev_err(chip->card->dev,
 600                         "could not query pipe's sample count\n");
 601         else {
 602                 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 603                                   << 24)     /* hi part */
 604                         + chip->rmh.stat[1]; /* lo part */
 605         }
 606
 607         mutex_unlock(&chip->msg_lock);
 608         return err;
 609 }
 610
 611 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
 612 {
 613         int err;
 614         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 615
 616         mutex_lock(&chip->msg_lock);
 617         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 618
 619         chip->rmh.cmd[0] |= pipe_cmd;
 620
 621         err = lx_message_send_atomic(chip, &chip->rmh);
 622
 623         if (err != 0)
 624                 dev_err(chip->card->dev, "could not query pipe's state\n");
 625         else
 626                 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
 627
 628         mutex_unlock(&chip->msg_lock);
 629         return err;
 630 }
 631
 632 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
 633                                   int is_capture, u16 state)
 634 {
 635         int i;
 636
 637         /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
 638          * timeout 50 ms */
 639         for (i = 0; i != 50; ++i) {
 640                 u16 current_state;
 641                 int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
 642
 643                 if (err < 0)
 644                         return err;
 645
 646                 if (!err && current_state == state)
 647                         return 0;
 648
 649                 mdelay(1);
 650         }
 651
 652         return -ETIMEDOUT;
 653 }
 654
 655 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
 656 {
 657         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
 658 }
 659
 660 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
 661 {
 662         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
 663 }
 664
 665 /* low-level stream handling */
 666 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
 667                                int is_capture, enum stream_state_t state)
 668 {
 669         int err;
 670         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 671
 672         mutex_lock(&chip->msg_lock);
 673         lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
 674
 675         chip->rmh.cmd[0] |= pipe_cmd;
 676         chip->rmh.cmd[0] |= state;
 677
 678         err = lx_message_send_atomic(chip, &chip->rmh);
 679         mutex_unlock(&chip->msg_lock);
 680
 681         return err;
 682 }
 683
 684 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
 685                          u32 pipe, int is_capture)
 686 {
 687         int err;
 688         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 689         u32 channels = runtime->channels;
 690
 691         if (runtime->channels != channels)
 692                 dev_err(chip->card->dev, "channel count mismatch: %d vs %d",
 693                            runtime->channels, channels);
 694
 695         mutex_lock(&chip->msg_lock);
 696         lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
 697
 698         chip->rmh.cmd[0] |= pipe_cmd;
 699
 700         if (runtime->sample_bits == 16)
 701                 /* 16 bit format */
 702                 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
 703
 704         if (snd_pcm_format_little_endian(runtime->format))
 705                 /* little endian/intel format */
 706                 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
 707
 708         chip->rmh.cmd[0] |= channels-1;
 709
 710         err = lx_message_send_atomic(chip, &chip->rmh);
 711         mutex_unlock(&chip->msg_lock);
 712
 713         return err;
 714 }
 715
 716 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
 717                     int *rstate)
 718 {
 719         int err;
 720         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 721
 722         mutex_lock(&chip->msg_lock);
 723         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 724
 725         chip->rmh.cmd[0] |= pipe_cmd;
 726
 727         err = lx_message_send_atomic(chip, &chip->rmh);
 728
 729         *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
 730
 731         mutex_unlock(&chip->msg_lock);
 732         return err;
 733 }
 734
 735 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
 736                               u64 *r_bytepos)
 737 {
 738         int err;
 739         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 740
 741         mutex_lock(&chip->msg_lock);
 742         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 743
 744         chip->rmh.cmd[0] |= pipe_cmd;
 745
 746         err = lx_message_send_atomic(chip, &chip->rmh);
 747
 748         *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 749                       << 32)         /* hi part */
 750                 + chip->rmh.stat[1]; /* lo part */
 751
 752         mutex_unlock(&chip->msg_lock);
 753         return err;
 754 }
 755
 756 /* low-level buffer handling */
 757 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
 758                    u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
 759                    u32 *r_buffer_index)
 760 {
 761         int err;
 762         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 763
 764         mutex_lock(&chip->msg_lock);
 765         lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
 766
 767         chip->rmh.cmd[0] |= pipe_cmd;
 768         chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
 769
 770         /* todo: pause request, circular buffer */
 771
 772         chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
 773         chip->rmh.cmd[2] = buf_address_lo;
 774
 775         if (buf_address_hi) {
 776                 chip->rmh.cmd_len = 4;
 777                 chip->rmh.cmd[3] = buf_address_hi;
 778                 chip->rmh.cmd[0] |= BF_64BITS_ADR;
 779         }
 780
 781         err = lx_message_send_atomic(chip, &chip->rmh);
 782
 783         if (err == 0) {
 784                 *r_buffer_index = chip->rmh.stat[0];
 785                 goto done;
 786         }
 787
 788         if (err == EB_RBUFFERS_TABLE_OVERFLOW)
 789                 dev_err(chip->card->dev,
 790                         "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
 791
 792         if (err == EB_INVALID_STREAM)
 793                 dev_err(chip->card->dev,
 794                         "lx_buffer_give EB_INVALID_STREAM\n");
 795
 796         if (err == EB_CMD_REFUSED)
 797                 dev_err(chip->card->dev,
 798                         "lx_buffer_give EB_CMD_REFUSED\n");
 799
 800  done:
 801         mutex_unlock(&chip->msg_lock);
 802         return err;
 803 }
 804
 805 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
 806                    u32 *r_buffer_size)
 807 {
 808         int err;
 809         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 810
 811         mutex_lock(&chip->msg_lock);
 812         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
 813
 814         chip->rmh.cmd[0] |= pipe_cmd;
 815         chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
 816                                              * microblaze will seek for it */
 817
 818         err = lx_message_send_atomic(chip, &chip->rmh);
 819
 820         if (err == 0)
 821                 *r_buffer_size = chip->rmh.stat[0]  & MASK_DATA_SIZE;
 822
 823         mutex_unlock(&chip->msg_lock);
 824         return err;
 825 }
 826
 827 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
 828                      u32 buffer_index)
 829 {
 830         int err;
 831         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 832
 833         mutex_lock(&chip->msg_lock);
 834         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
 835
 836         chip->rmh.cmd[0] |= pipe_cmd;
 837         chip->rmh.cmd[0] |= buffer_index;
 838
 839         err = lx_message_send_atomic(chip, &chip->rmh);
 840
 841         mutex_unlock(&chip->msg_lock);
 842         return err;
 843 }
 844
 845
 846 /* low-level gain/peak handling
 847  *
 848  * \todo: can we unmute capture/playback channels independently?
 849  *
 850  * */
 851 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
 852 {
 853         int err;
 854         /* bit set to 1: channel muted */
 855         u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
 856
 857         mutex_lock(&chip->msg_lock);
 858         lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
 859
 860         chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
 861
 862         chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32);        /* hi part */
 863         chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
 864
 865         dev_dbg(chip->card->dev,
 866                 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
 867                    chip->rmh.cmd[2]);
 868
 869         err = lx_message_send_atomic(chip, &chip->rmh);
 870
 871         mutex_unlock(&chip->msg_lock);
 872         return err;
 873 }
 874
 875 static u32 peak_map[] = {
 876         0x00000109, /* -90.308dB */
 877         0x0000083B, /* -72.247dB */
 878         0x000020C4, /* -60.205dB */
 879         0x00008273, /* -48.030dB */
 880         0x00020756, /* -36.005dB */
 881         0x00040C37, /* -30.001dB */
 882         0x00081385, /* -24.002dB */
 883         0x00101D3F, /* -18.000dB */
 884         0x0016C310, /* -15.000dB */
 885         0x002026F2, /* -12.001dB */
 886         0x002D6A86, /* -9.000dB */
 887         0x004026E6, /* -6.004dB */
 888         0x005A9DF6, /* -3.000dB */
 889         0x0065AC8B, /* -2.000dB */
 890         0x00721481, /* -1.000dB */
 891         0x007FFFFF, /* FS */
 892 };
 893
 894 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
 895                    u32 *r_levels)
 896 {
 897         int err = 0;
 898         int i;
 899
 900         mutex_lock(&chip->msg_lock);
 901         for (i = 0; i < channels; i += 4) {
 902                 u32 s0, s1, s2, s3;
 903
 904                 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
 905                 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
 906
 907                 err = lx_message_send_atomic(chip, &chip->rmh);
 908
 909                 if (err == 0) {
 910                         s0 = peak_map[chip->rmh.stat[0] & 0x0F];
 911                         s1 = peak_map[(chip->rmh.stat[0] >>  4) & 0xf];
 912                         s2 = peak_map[(chip->rmh.stat[0] >>  8) & 0xf];
 913                         s3 = peak_map[(chip->rmh.stat[0] >>  12) & 0xf];
 914                 } else
 915                         s0 = s1 = s2 = s3 = 0;
 916
 917                 r_levels[0] = s0;
 918                 r_levels[1] = s1;
 919                 r_levels[2] = s2;
 920                 r_levels[3] = s3;
 921
 922                 r_levels += 4;
 923         }
 924
 925         mutex_unlock(&chip->msg_lock);
 926         return err;
 927 }
 928
 929 /* interrupt handling */
 930 #define PCX_IRQ_NONE 0
 931 #define IRQCS_ACTIVE_PCIDB      BIT(13)
 932 #define IRQCS_ENABLE_PCIIRQ     BIT(8)
 933 #define IRQCS_ENABLE_PCIDB      BIT(9)
 934
 935 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
 936 {
 937         u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
 938
 939         /* Test if PCI Doorbell interrupt is active */
 940         if (irqcs & IRQCS_ACTIVE_PCIDB) {
 941                 u32 temp;
 942                 irqcs = PCX_IRQ_NONE;
 943
 944                 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
 945                         /* RAZ interrupt */
 946                         irqcs |= temp;
 947                         lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
 948                 }
 949
 950                 return irqcs;
 951         }
 952         return PCX_IRQ_NONE;
 953 }
 954
 955 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
 956                             int *r_async_pending, int *r_async_escmd)
 957 {
 958         u32 irq_async;
 959         u32 irqsrc = lx_interrupt_test_ack(chip);
 960
 961         if (irqsrc == PCX_IRQ_NONE)
 962                 return 0;
 963
 964         *r_irqsrc = irqsrc;
 965
 966         irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
 967                                                      * (set by xilinx) + EOB */
 968
 969         if (irq_async & MASK_SYS_STATUS_ESA) {
 970                 irq_async &= ~MASK_SYS_STATUS_ESA;
 971                 *r_async_escmd = 1;
 972         }
 973
 974         if (irq_async) {
 975                 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */
 976                 *r_async_pending = 1;
 977         }
 978
 979         return 1;
 980 }
 981
 982 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
 983                                             int *r_freq_changed,
 984                                             u64 *r_notified_in_pipe_mask,
 985                                             u64 *r_notified_out_pipe_mask)
 986 {
 987         int err;
 988         u32 stat[9];            /* answer from CMD_04_GET_EVENT */
 989
 990         /* We can optimize this to not read dumb events.
 991          * Answer words are in the following order:
 992          * Stat[0]      general status
 993          * Stat[1]      end of buffer OUT pF
 994          * Stat[2]      end of buffer OUT pf
 995          * Stat[3]      end of buffer IN pF
 996          * Stat[4]      end of buffer IN pf
 997          * Stat[5]      MSB underrun
 998          * Stat[6]      LSB underrun
 999          * Stat[7]      MSB overrun
1000          * Stat[8]      LSB overrun
1001          * */
1002
1003         u64 orun_mask;
1004         u64 urun_mask;
1005         int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1006         int eb_pending_in  = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1007
1008         *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1009
1010         err = lx_dsp_read_async_events(chip, stat);
1011         if (err < 0)
1012                 return err;
1013
1014         if (eb_pending_in) {
1015                 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1016                         + stat[4];
1017                 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n",
1018                             *r_notified_in_pipe_mask);
1019         }
1020         if (eb_pending_out) {
1021                 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1022                         + stat[2];
1023                 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n",
1024                             *r_notified_out_pipe_mask);
1025         }
1026
1027         orun_mask = ((u64)stat[7] << 32) + stat[8];
1028         urun_mask = ((u64)stat[5] << 32) + stat[6];
1029
1030         /* todo: handle xrun notification */
1031
1032         return err;
1033 }
1034
1035 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1036                                            struct lx_stream *lx_stream)
1037 {
1038         struct snd_pcm_substream *substream = lx_stream->stream;
1039         const unsigned int is_capture = lx_stream->is_capture;
1040         int err;
1041
1042         const u32 channels = substream->runtime->channels;
1043         const u32 bytes_per_frame = channels * 3;
1044         const u32 period_size = substream->runtime->period_size;
1045         const u32 period_bytes = period_size * bytes_per_frame;
1046         const u32 pos = lx_stream->frame_pos;
1047         const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1048                 0 : pos + 1;
1049
1050         dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1051         u32 buf_hi = 0;
1052         u32 buf_lo = 0;
1053         u32 buffer_index = 0;
1054
1055         u32 needed, freed;
1056         u32 size_array[MAX_STREAM_BUFFER];
1057
1058         dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n");
1059
1060         mutex_lock(&chip->lock);
1061
1062         err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1063         dev_dbg(chip->card->dev,
1064                 "interrupt: needed %d, freed %d\n", needed, freed);
1065
1066         unpack_pointer(buf, &buf_lo, &buf_hi);
1067         err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1068                              &buffer_index);
1069         dev_dbg(chip->card->dev,
1070                 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n",
1071                     buffer_index, (unsigned long)buf, period_bytes);
1072
1073         lx_stream->frame_pos = next_pos;
1074         mutex_unlock(&chip->lock);
1075
1076         return err;
1077 }
1078
1079 irqreturn_t lx_interrupt(int irq, void *dev_id)
1080 {
1081         struct lx6464es *chip = dev_id;
1082         int async_pending, async_escmd;
1083         u32 irqsrc;
1084         bool wake_thread = false;
1085
1086         dev_dbg(chip->card->dev,
1087                 "**************************************************\n");
1088
1089         if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1090                 dev_dbg(chip->card->dev, "IRQ_NONE\n");
1091                 return IRQ_NONE; /* this device did not cause the interrupt */
1092         }
1093
1094         if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1095                 return IRQ_HANDLED;
1096
1097         if (irqsrc & MASK_SYS_STATUS_EOBI)
1098                 dev_dbg(chip->card->dev, "interrupt: EOBI\n");
1099
1100         if (irqsrc & MASK_SYS_STATUS_EOBO)
1101                 dev_dbg(chip->card->dev, "interrupt: EOBO\n");
1102
1103         if (irqsrc & MASK_SYS_STATUS_URUN)
1104                 dev_dbg(chip->card->dev, "interrupt: URUN\n");
1105
1106         if (irqsrc & MASK_SYS_STATUS_ORUN)
1107                 dev_dbg(chip->card->dev, "interrupt: ORUN\n");
1108
1109         if (async_pending) {
1110                 wake_thread = true;
1111                 chip->irqsrc = irqsrc;
1112         }
1113
1114         if (async_escmd) {
1115                 /* backdoor for ethersound commands
1116                  *
1117                  * for now, we do not need this
1118                  *
1119                  * */
1120
1121                 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n");
1122         }
1123
1124         return wake_thread ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1125 }
1126
1127 irqreturn_t lx_threaded_irq(int irq, void *dev_id)
1128 {
1129         struct lx6464es *chip = dev_id;
1130         u64 notified_in_pipe_mask = 0;
1131         u64 notified_out_pipe_mask = 0;
1132         int freq_changed;
1133         int err;
1134
1135         /* handle async events */
1136         err = lx_interrupt_handle_async_events(chip, chip->irqsrc,
1137                                                &freq_changed,
1138                                                &notified_in_pipe_mask,
1139                                                &notified_out_pipe_mask);
1140         if (err)
1141                 dev_err(chip->card->dev, "error handling async events\n");
1142
1143         if (notified_in_pipe_mask) {
1144                 struct lx_stream *lx_stream = &chip->capture_stream;
1145
1146                 dev_dbg(chip->card->dev,
1147                         "requesting audio transfer for capture\n");
1148                 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1149                 if (err < 0)
1150                         dev_err(chip->card->dev,
1151                                 "cannot request new buffer for capture\n");
1152                 snd_pcm_period_elapsed(lx_stream->stream);
1153         }
1154
1155         if (notified_out_pipe_mask) {
1156                 struct lx_stream *lx_stream = &chip->playback_stream;
1157
1158                 dev_dbg(chip->card->dev,
1159                         "requesting audio transfer for playback\n");
1160                 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1161                 if (err < 0)
1162                         dev_err(chip->card->dev,
1163                                 "cannot request new buffer for playback\n");
1164                 snd_pcm_period_elapsed(lx_stream->stream);
1165         }
1166
1167         return IRQ_HANDLED;
1168 }
1169
1170
1171 static void lx_irq_set(struct lx6464es *chip, int enable)
1172 {
1173         u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1174
1175         /* enable/disable interrupts
1176          *
1177          * Set the Doorbell and PCI interrupt enable bits
1178          *
1179          * */
1180         if (enable)
1181                 reg |=  (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1182         else
1183                 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1184         lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1185 }
1186
1187 void lx_irq_enable(struct lx6464es *chip)
1188 {
1189         dev_dbg(chip->card->dev, "->lx_irq_enable\n");
1190         lx_irq_set(chip, 1);
1191 }
1192
1193 void lx_irq_disable(struct lx6464es *chip)
1194 {
1195         dev_dbg(chip->card->dev, "->lx_irq_disable\n");
1196         lx_irq_set(chip, 0);
1197 }