1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for Intel ICH (i8x0) chipsets
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/ac97_codec.h>
24 #include <sound/info.h>
25 #include <sound/initval.h>
27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
29 MODULE_LICENSE("GPL");
30 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
31 "{Intel,82901AB-ICH0},"
32 "{Intel,82801BA-ICH2},"
33 "{Intel,82801CA-ICH3},"
34 "{Intel,82801DB-ICH4},"
42 "{NVidia,nForce Audio},"
43 "{NVidia,nForce2 Audio},"
44 "{NVidia,nForce3 Audio},"
54 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
55 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
56 static int ac97_clock;
57 static char *ac97_quirk;
58 static bool buggy_semaphore;
59 static int buggy_irq = -1; /* auto-check */
61 static int spdif_aclink = -1;
62 static int inside_vm = -1;
64 module_param(index, int, 0444);
65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
66 module_param(id, charp, 0444);
67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
68 module_param(ac97_clock, int, 0444);
69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
70 module_param(ac97_quirk, charp, 0444);
71 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
72 module_param(buggy_semaphore, bool, 0444);
73 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
74 module_param(buggy_irq, bint, 0444);
75 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
76 module_param(xbox, bool, 0444);
77 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
78 module_param(spdif_aclink, int, 0444);
79 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
80 module_param(inside_vm, bint, 0444);
81 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
83 /* just for backward compatibility */
85 module_param(enable, bool, 0444);
87 module_param(joystick, int, 0444);
92 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
94 #define ICHREG(x) ICH_REG_##x
96 #define DEFINE_REGSET(name,base) \
98 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
99 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
100 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
101 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
102 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
103 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
104 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
107 /* busmaster blocks */
108 DEFINE_REGSET(OFF, 0); /* offset */
109 DEFINE_REGSET(PI, 0x00); /* PCM in */
110 DEFINE_REGSET(PO, 0x10); /* PCM out */
111 DEFINE_REGSET(MC, 0x20); /* Mic in */
113 /* ICH4 busmaster blocks */
114 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
115 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
116 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
118 /* values for each busmaster block */
121 #define ICH_REG_LVI_MASK 0x1f
124 #define ICH_FIFOE 0x10 /* FIFO error */
125 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
126 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
127 #define ICH_CELV 0x02 /* current equals last valid */
128 #define ICH_DCH 0x01 /* DMA controller halted */
131 #define ICH_REG_PIV_MASK 0x1f /* mask */
134 #define ICH_IOCE 0x10 /* interrupt on completion enable */
135 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
136 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
137 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
138 #define ICH_STARTBM 0x01 /* start busmaster operation */
142 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
143 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
144 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
145 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
146 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
147 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
148 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
149 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
150 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
151 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
152 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
153 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
154 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
155 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
156 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
157 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
158 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
159 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
160 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
161 #define ICH_ACLINK 0x00000008 /* AClink shut off */
162 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
163 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
164 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
165 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
166 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
167 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
168 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
169 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
170 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
171 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
172 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
173 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
174 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
175 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
176 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
177 #define ICH_MD3 0x00020000 /* modem power down semaphore */
178 #define ICH_AD3 0x00010000 /* audio power down semaphore */
179 #define ICH_RCS 0x00008000 /* read completion status */
180 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
181 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
182 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
183 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
184 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
185 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
186 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
187 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
188 #define ICH_POINT 0x00000040 /* playback interrupt */
189 #define ICH_PIINT 0x00000020 /* capture interrupt */
190 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
191 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
192 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
193 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
194 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
195 #define ICH_CAS 0x01 /* codec access semaphore */
196 #define ICH_REG_SDM 0x80
197 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
198 #define ICH_DI2L_SHIFT 6
199 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
200 #define ICH_DI1L_SHIFT 4
201 #define ICH_SE 0x00000008 /* steer enable */
202 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
204 #define ICH_MAX_FRAGS 32 /* max hw frags */
208 * registers for Ali5455
211 /* ALi 5455 busmaster blocks */
212 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
213 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
214 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
215 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
216 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
217 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
218 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
219 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
220 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
221 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
222 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
225 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
226 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
227 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
228 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
229 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
230 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
231 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
232 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
233 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
234 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
235 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
236 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
237 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
238 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
239 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
240 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
241 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
242 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
243 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
244 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
245 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
248 #define ALI_CAS_SEM_BUSY 0x80000000
249 #define ALI_CPR_ADDR_SECONDARY 0x100
250 #define ALI_CPR_ADDR_READ 0x80
251 #define ALI_CSPSR_CODEC_READY 0x08
252 #define ALI_CSPSR_READ_OK 0x02
253 #define ALI_CSPSR_WRITE_OK 0x01
255 /* interrupts for the whole chip by interrupt status register finish */
257 #define ALI_INT_MICIN2 (1<<26)
258 #define ALI_INT_PCMIN2 (1<<25)
259 #define ALI_INT_I2SIN (1<<24)
260 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
261 #define ALI_INT_SPDIFIN (1<<22)
262 #define ALI_INT_LFEOUT (1<<21)
263 #define ALI_INT_CENTEROUT (1<<20)
264 #define ALI_INT_CODECSPDIFOUT (1<<19)
265 #define ALI_INT_MICIN (1<<18)
266 #define ALI_INT_PCMOUT (1<<17)
267 #define ALI_INT_PCMIN (1<<16)
268 #define ALI_INT_CPRAIS (1<<7) /* command port available */
269 #define ALI_INT_SPRAIS (1<<5) /* status port available */
270 #define ALI_INT_GPIO (1<<1)
271 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
272 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
274 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
275 #define ICH_ALI_SC_AC97_DBL (1<<30)
276 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
277 #define ICH_ALI_SC_IN_BITS (3<<18)
278 #define ICH_ALI_SC_OUT_BITS (3<<16)
279 #define ICH_ALI_SC_6CH_CFG (3<<14)
280 #define ICH_ALI_SC_PCM_4 (1<<8)
281 #define ICH_ALI_SC_PCM_6 (2<<8)
282 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
284 #define ICH_ALI_SS_SEC_ID (3<<5)
285 #define ICH_ALI_SS_PRI_ID (3<<3)
287 #define ICH_ALI_IF_AC97SP (1<<21)
288 #define ICH_ALI_IF_MC (1<<20)
289 #define ICH_ALI_IF_PI (1<<19)
290 #define ICH_ALI_IF_MC2 (1<<18)
291 #define ICH_ALI_IF_PI2 (1<<17)
292 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
293 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
294 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
295 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
296 #define ICH_ALI_IF_PO_SPDF (1<<3)
297 #define ICH_ALI_IF_PO (1<<1)
310 ICHD_LAST = ICHD_SPBAR
326 ALID_LAST = ALID_SPDIFOUT
329 #define get_ichdev(substream) (substream->runtime->private_data)
332 unsigned int ichd; /* ich device number */
333 unsigned long reg_offset; /* offset to bmaddr */
334 __le32 *bdbar; /* CPU address (32bit) */
335 unsigned int bdbar_addr; /* PCI bus address (32bit) */
336 struct snd_pcm_substream *substream;
337 unsigned int physbuf; /* physical address (32bit) */
339 unsigned int fragsize;
340 unsigned int fragsize1;
341 unsigned int position;
342 unsigned int pos_shift;
343 unsigned int last_pos;
350 unsigned int ack_bit;
351 unsigned int roff_sr;
352 unsigned int roff_picb;
353 unsigned int int_sta_mask; /* interrupt status mask */
354 unsigned int ali_slot; /* ALI DMA slot */
355 struct ac97_pcm *pcm;
357 unsigned int prepared:1;
358 unsigned int suspended: 1;
362 unsigned int device_type;
367 void __iomem *bmaddr;
370 struct snd_card *card;
373 struct snd_pcm *pcm[6];
374 struct ichdev ichd[6];
381 unsigned in_ac97_init: 1,
383 unsigned in_measurement: 1; /* during ac97 clock measurement */
384 unsigned fix_nocache: 1; /* workaround for 440MX */
385 unsigned buggy_irq: 1; /* workaround for buggy mobos */
386 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
387 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
388 unsigned inside_vm: 1; /* enable VM optimization */
390 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
391 unsigned int sdm_saved; /* SDM reg value */
393 struct snd_ac97_bus *ac97_bus;
394 struct snd_ac97 *ac97[3];
395 unsigned int ac97_sdin[3];
396 unsigned int max_codecs, ncodecs;
397 unsigned int *codec_bit;
398 unsigned int codec_isr_bits;
399 unsigned int codec_ready_bits;
404 struct snd_dma_buffer bdbars;
405 u32 int_sta_reg; /* interrupt status register */
406 u32 int_sta_mask; /* interrupt status mask */
409 static const struct pci_device_id snd_intel8x0_ids[] = {
410 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
411 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
412 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
413 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
414 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
415 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
416 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
417 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
418 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
419 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
420 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
421 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
422 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
423 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
424 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
425 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
426 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
427 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
428 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
429 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
430 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
431 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
432 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
436 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
439 * Lowlevel I/O - busmaster
442 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
444 return ioread8(chip->bmaddr + offset);
447 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
449 return ioread16(chip->bmaddr + offset);
452 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
454 return ioread32(chip->bmaddr + offset);
457 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
459 iowrite8(val, chip->bmaddr + offset);
462 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
464 iowrite16(val, chip->bmaddr + offset);
467 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
469 iowrite32(val, chip->bmaddr + offset);
473 * Lowlevel I/O - AC'97 registers
476 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
478 return ioread16(chip->addr + offset);
481 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
483 iowrite16(val, chip->addr + offset);
491 * access to AC97 codec via normal i/o (for ICH and SIS7012)
494 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
500 if (chip->in_sdin_init) {
501 /* we don't know the ready bit assignment at the moment */
502 /* so we check any */
503 codec = chip->codec_isr_bits;
505 codec = chip->codec_bit[chip->ac97_sdin[codec]];
509 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
512 if (chip->buggy_semaphore)
513 return 0; /* just ignore ... */
515 /* Anyone holding a semaphore for 1 msec should be shot... */
518 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
523 /* access to some forbidden (non existent) ac97 registers will not
524 * reset the semaphore. So even if you don't get the semaphore, still
525 * continue the access. We don't need the semaphore anyway. */
526 dev_err(chip->card->dev,
527 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
528 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
529 iagetword(chip, 0); /* clear semaphore flag */
530 /* I don't care about the semaphore */
534 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
538 struct intel8x0 *chip = ac97->private_data;
540 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
541 if (! chip->in_ac97_init)
542 dev_err(chip->card->dev,
543 "codec_write %d: semaphore is not ready for register 0x%x\n",
546 iaputword(chip, reg + ac97->num * 0x80, val);
549 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
552 struct intel8x0 *chip = ac97->private_data;
556 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
557 if (! chip->in_ac97_init)
558 dev_err(chip->card->dev,
559 "codec_read %d: semaphore is not ready for register 0x%x\n",
563 res = iagetword(chip, reg + ac97->num * 0x80);
564 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
565 /* reset RCS and preserve other R/WC bits */
566 iputdword(chip, ICHREG(GLOB_STA), tmp &
567 ~(chip->codec_ready_bits | ICH_GSCI));
568 if (! chip->in_ac97_init)
569 dev_err(chip->card->dev,
570 "codec_read %d: read timeout for register 0x%x\n",
578 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
583 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
584 iagetword(chip, codec * 0x80);
585 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
586 /* reset RCS and preserve other R/WC bits */
587 iputdword(chip, ICHREG(GLOB_STA), tmp &
588 ~(chip->codec_ready_bits | ICH_GSCI));
594 * access to AC97 for Ali5455
596 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
599 for (count = 0; count < 0x7f; count++) {
600 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
604 if (! chip->in_ac97_init)
605 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
609 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
612 if (chip->buggy_semaphore)
613 return 0; /* just ignore ... */
614 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
616 if (! time && ! chip->in_ac97_init)
617 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
618 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
621 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
623 struct intel8x0 *chip = ac97->private_data;
624 unsigned short data = 0xffff;
626 if (snd_intel8x0_ali_codec_semaphore(chip))
628 reg |= ALI_CPR_ADDR_READ;
630 reg |= ALI_CPR_ADDR_SECONDARY;
631 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
632 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
634 data = igetword(chip, ICHREG(ALI_SPR));
639 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
642 struct intel8x0 *chip = ac97->private_data;
644 if (snd_intel8x0_ali_codec_semaphore(chip))
646 iputword(chip, ICHREG(ALI_CPR), val);
648 reg |= ALI_CPR_ADDR_SECONDARY;
649 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
650 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
657 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
660 __le32 *bdbar = ichdev->bdbar;
661 unsigned long port = ichdev->reg_offset;
663 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
664 if (ichdev->size == ichdev->fragsize) {
665 ichdev->ack_reload = ichdev->ack = 2;
666 ichdev->fragsize1 = ichdev->fragsize >> 1;
667 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
668 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
669 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
670 ichdev->fragsize1 >> ichdev->pos_shift);
671 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
672 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
673 ichdev->fragsize1 >> ichdev->pos_shift);
677 ichdev->ack_reload = ichdev->ack = 1;
678 ichdev->fragsize1 = ichdev->fragsize;
679 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
680 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
681 (((idx >> 1) * ichdev->fragsize) %
683 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
684 ichdev->fragsize >> ichdev->pos_shift);
686 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
687 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
690 ichdev->frags = ichdev->size / ichdev->fragsize;
692 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
694 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
695 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
696 ichdev->position = 0;
698 dev_dbg(chip->card->dev,
699 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
700 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
703 /* clear interrupts */
704 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
711 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
713 unsigned long port = ichdev->reg_offset;
715 int status, civ, i, step;
718 if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
721 spin_lock_irqsave(&chip->reg_lock, flags);
722 status = igetbyte(chip, port + ichdev->roff_sr);
723 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
724 if (!(status & ICH_BCIS)) {
726 } else if (civ == ichdev->civ) {
727 // snd_printd("civ same %d\n", civ);
730 ichdev->civ &= ICH_REG_LVI_MASK;
732 step = civ - ichdev->civ;
734 step += ICH_REG_LVI_MASK + 1;
736 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
740 ichdev->position += step * ichdev->fragsize1;
741 if (! chip->in_measurement)
742 ichdev->position %= ichdev->size;
744 ichdev->lvi &= ICH_REG_LVI_MASK;
745 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
746 for (i = 0; i < step; i++) {
748 ichdev->lvi_frag %= ichdev->frags;
749 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
751 dev_dbg(chip->card->dev,
752 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
753 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
754 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
755 inl(port + 4), inb(port + ICH_REG_OFF_CR));
757 if (--ichdev->ack == 0) {
758 ichdev->ack = ichdev->ack_reload;
762 spin_unlock_irqrestore(&chip->reg_lock, flags);
763 if (ack && ichdev->substream) {
764 snd_pcm_period_elapsed(ichdev->substream);
766 iputbyte(chip, port + ichdev->roff_sr,
767 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
770 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
772 struct intel8x0 *chip = dev_id;
773 struct ichdev *ichdev;
777 status = igetdword(chip, chip->int_sta_reg);
778 if (status == 0xffffffff) /* we are not yet resumed */
781 if ((status & chip->int_sta_mask) == 0) {
784 iputdword(chip, chip->int_sta_reg, status);
785 if (! chip->buggy_irq)
788 return IRQ_RETVAL(status);
791 for (i = 0; i < chip->bdbars_count; i++) {
792 ichdev = &chip->ichd[i];
793 if (status & ichdev->int_sta_mask)
794 snd_intel8x0_update(chip, ichdev);
798 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
807 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
809 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
810 struct ichdev *ichdev = get_ichdev(substream);
811 unsigned char val = 0;
812 unsigned long port = ichdev->reg_offset;
815 case SNDRV_PCM_TRIGGER_RESUME:
816 ichdev->suspended = 0;
818 case SNDRV_PCM_TRIGGER_START:
819 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
820 val = ICH_IOCE | ICH_STARTBM;
821 ichdev->last_pos = ichdev->position;
823 case SNDRV_PCM_TRIGGER_SUSPEND:
824 ichdev->suspended = 1;
826 case SNDRV_PCM_TRIGGER_STOP:
829 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
835 iputbyte(chip, port + ICH_REG_OFF_CR, val);
836 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
837 /* wait until DMA stopped */
838 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
839 /* reset whole DMA things */
840 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
845 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
847 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
848 struct ichdev *ichdev = get_ichdev(substream);
849 unsigned long port = ichdev->reg_offset;
850 static int fiforeg[] = {
851 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
853 unsigned int val, fifo;
855 val = igetdword(chip, ICHREG(ALI_DMACR));
857 case SNDRV_PCM_TRIGGER_RESUME:
858 ichdev->suspended = 0;
860 case SNDRV_PCM_TRIGGER_START:
861 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
862 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
863 /* clear FIFO for synchronization of channels */
864 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
865 fifo &= ~(0xff << (ichdev->ali_slot % 4));
866 fifo |= 0x83 << (ichdev->ali_slot % 4);
867 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
869 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
870 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
872 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
874 case SNDRV_PCM_TRIGGER_SUSPEND:
875 ichdev->suspended = 1;
877 case SNDRV_PCM_TRIGGER_STOP:
878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
880 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
881 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
882 while (igetbyte(chip, port + ICH_REG_OFF_CR))
884 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
886 /* reset whole DMA things */
887 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
888 /* clear interrupts */
889 iputbyte(chip, port + ICH_REG_OFF_SR,
890 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
891 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
892 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
900 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
901 struct snd_pcm_hw_params *hw_params)
903 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
904 struct ichdev *ichdev = get_ichdev(substream);
905 int dbl = params_rate(hw_params) > 48000;
908 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
911 if (ichdev->pcm_open_flag) {
912 snd_ac97_pcm_close(ichdev->pcm);
913 ichdev->pcm_open_flag = 0;
914 ichdev->prepared = 0;
916 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
917 params_channels(hw_params),
918 ichdev->pcm->r[dbl].slots);
920 ichdev->pcm_open_flag = 1;
921 /* Force SPDIF setting */
922 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
923 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
924 params_rate(hw_params));
929 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
931 struct ichdev *ichdev = get_ichdev(substream);
933 if (ichdev->pcm_open_flag) {
934 snd_ac97_pcm_close(ichdev->pcm);
935 ichdev->pcm_open_flag = 0;
936 ichdev->prepared = 0;
938 return snd_pcm_lib_free_pages(substream);
941 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
942 struct snd_pcm_runtime *runtime)
945 int dbl = runtime->rate > 48000;
947 spin_lock_irq(&chip->reg_lock);
948 switch (chip->device_type) {
950 cnt = igetdword(chip, ICHREG(ALI_SCR));
951 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
952 if (runtime->channels == 4 || dbl)
953 cnt |= ICH_ALI_SC_PCM_4;
954 else if (runtime->channels == 6)
955 cnt |= ICH_ALI_SC_PCM_6;
956 iputdword(chip, ICHREG(ALI_SCR), cnt);
959 cnt = igetdword(chip, ICHREG(GLOB_CNT));
960 cnt &= ~ICH_SIS_PCM_246_MASK;
961 if (runtime->channels == 4 || dbl)
962 cnt |= ICH_SIS_PCM_4;
963 else if (runtime->channels == 6)
964 cnt |= ICH_SIS_PCM_6;
965 iputdword(chip, ICHREG(GLOB_CNT), cnt);
968 cnt = igetdword(chip, ICHREG(GLOB_CNT));
969 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
970 if (runtime->channels == 4 || dbl)
972 else if (runtime->channels == 6)
974 else if (runtime->channels == 8)
976 if (chip->device_type == DEVICE_NFORCE) {
977 /* reset to 2ch once to keep the 6 channel data in alignment,
978 * to start from Front Left always
980 if (cnt & ICH_PCM_246_MASK) {
981 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
982 spin_unlock_irq(&chip->reg_lock);
983 msleep(50); /* grrr... */
984 spin_lock_irq(&chip->reg_lock);
986 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
987 if (runtime->sample_bits > 16)
988 cnt |= ICH_PCM_20BIT;
990 iputdword(chip, ICHREG(GLOB_CNT), cnt);
993 spin_unlock_irq(&chip->reg_lock);
996 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
998 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
999 struct snd_pcm_runtime *runtime = substream->runtime;
1000 struct ichdev *ichdev = get_ichdev(substream);
1002 ichdev->physbuf = runtime->dma_addr;
1003 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1004 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1005 if (ichdev->ichd == ICHD_PCMOUT) {
1006 snd_intel8x0_setup_pcm_out(chip, runtime);
1007 if (chip->device_type == DEVICE_INTEL_ICH4)
1008 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1010 snd_intel8x0_setup_periods(chip, ichdev);
1011 ichdev->prepared = 1;
1015 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1017 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1018 struct ichdev *ichdev = get_ichdev(substream);
1020 int civ, timeout = 10;
1021 unsigned int position;
1023 spin_lock(&chip->reg_lock);
1025 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1026 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1027 position = ichdev->position;
1032 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1035 /* IO read operation is very expensive inside virtual machine
1036 * as it is emulated. The probability that subsequent PICB read
1037 * will return different result is high enough to loop till
1039 * Same CIV is strict enough condition to be sure that PICB
1040 * is valid inside VM on emulated card. */
1041 if (chip->inside_vm)
1043 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1045 } while (timeout--);
1046 ptr = ichdev->last_pos;
1048 ptr1 <<= ichdev->pos_shift;
1049 ptr = ichdev->fragsize1 - ptr1;
1051 if (ptr < ichdev->last_pos) {
1052 unsigned int pos_base, last_base;
1053 pos_base = position / ichdev->fragsize1;
1054 last_base = ichdev->last_pos / ichdev->fragsize1;
1055 /* another sanity check; ptr1 can go back to full
1056 * before the base position is updated
1058 if (pos_base == last_base)
1059 ptr = ichdev->last_pos;
1062 ichdev->last_pos = ptr;
1063 spin_unlock(&chip->reg_lock);
1064 if (ptr >= ichdev->size)
1066 return bytes_to_frames(substream->runtime, ptr);
1069 static const struct snd_pcm_hardware snd_intel8x0_stream =
1071 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1072 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1073 SNDRV_PCM_INFO_MMAP_VALID |
1074 SNDRV_PCM_INFO_PAUSE |
1075 SNDRV_PCM_INFO_RESUME),
1076 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1077 .rates = SNDRV_PCM_RATE_48000,
1082 .buffer_bytes_max = 128 * 1024,
1083 .period_bytes_min = 32,
1084 .period_bytes_max = 128 * 1024,
1086 .periods_max = 1024,
1090 static const unsigned int channels4[] = {
1094 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1095 .count = ARRAY_SIZE(channels4),
1100 static const unsigned int channels6[] = {
1104 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1105 .count = ARRAY_SIZE(channels6),
1110 static const unsigned int channels8[] = {
1114 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1115 .count = ARRAY_SIZE(channels8),
1120 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1122 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1123 struct snd_pcm_runtime *runtime = substream->runtime;
1126 ichdev->substream = substream;
1127 runtime->hw = snd_intel8x0_stream;
1128 runtime->hw.rates = ichdev->pcm->rates;
1129 snd_pcm_limit_hw_rates(runtime);
1130 if (chip->device_type == DEVICE_SIS) {
1131 runtime->hw.buffer_bytes_max = 64*1024;
1132 runtime->hw.period_bytes_max = 64*1024;
1134 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1136 runtime->private_data = ichdev;
1140 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1142 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1143 struct snd_pcm_runtime *runtime = substream->runtime;
1146 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1151 runtime->hw.channels_max = 8;
1152 snd_pcm_hw_constraint_list(runtime, 0,
1153 SNDRV_PCM_HW_PARAM_CHANNELS,
1154 &hw_constraints_channels8);
1155 } else if (chip->multi6) {
1156 runtime->hw.channels_max = 6;
1157 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1158 &hw_constraints_channels6);
1159 } else if (chip->multi4) {
1160 runtime->hw.channels_max = 4;
1161 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1162 &hw_constraints_channels4);
1165 snd_ac97_pcm_double_rate_rules(runtime);
1167 if (chip->smp20bit) {
1168 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1169 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1174 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1176 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1178 chip->ichd[ICHD_PCMOUT].substream = NULL;
1182 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1184 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1186 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1189 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1191 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1193 chip->ichd[ICHD_PCMIN].substream = NULL;
1197 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1199 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1201 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1204 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1206 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1208 chip->ichd[ICHD_MIC].substream = NULL;
1212 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1214 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1216 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1219 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1221 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1223 chip->ichd[ICHD_MIC2].substream = NULL;
1227 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1229 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1234 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1236 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238 chip->ichd[ICHD_PCM2IN].substream = NULL;
1242 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1244 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1245 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1250 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1252 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1255 chip->ichd[idx].substream = NULL;
1259 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1261 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264 spin_lock_irq(&chip->reg_lock);
1265 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1266 val |= ICH_ALI_IF_AC97SP;
1267 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1268 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1269 spin_unlock_irq(&chip->reg_lock);
1271 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1274 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1276 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1279 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1280 spin_lock_irq(&chip->reg_lock);
1281 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1282 val &= ~ICH_ALI_IF_AC97SP;
1283 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1284 spin_unlock_irq(&chip->reg_lock);
1290 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1292 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1294 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1297 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1299 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1301 chip->ichd[ALID_SPDIFIN].substream = NULL;
1305 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1309 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1312 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1314 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1316 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1321 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1322 .open = snd_intel8x0_playback_open,
1323 .close = snd_intel8x0_playback_close,
1324 .ioctl = snd_pcm_lib_ioctl,
1325 .hw_params = snd_intel8x0_hw_params,
1326 .hw_free = snd_intel8x0_hw_free,
1327 .prepare = snd_intel8x0_pcm_prepare,
1328 .trigger = snd_intel8x0_pcm_trigger,
1329 .pointer = snd_intel8x0_pcm_pointer,
1332 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1333 .open = snd_intel8x0_capture_open,
1334 .close = snd_intel8x0_capture_close,
1335 .ioctl = snd_pcm_lib_ioctl,
1336 .hw_params = snd_intel8x0_hw_params,
1337 .hw_free = snd_intel8x0_hw_free,
1338 .prepare = snd_intel8x0_pcm_prepare,
1339 .trigger = snd_intel8x0_pcm_trigger,
1340 .pointer = snd_intel8x0_pcm_pointer,
1343 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1344 .open = snd_intel8x0_mic_open,
1345 .close = snd_intel8x0_mic_close,
1346 .ioctl = snd_pcm_lib_ioctl,
1347 .hw_params = snd_intel8x0_hw_params,
1348 .hw_free = snd_intel8x0_hw_free,
1349 .prepare = snd_intel8x0_pcm_prepare,
1350 .trigger = snd_intel8x0_pcm_trigger,
1351 .pointer = snd_intel8x0_pcm_pointer,
1354 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1355 .open = snd_intel8x0_mic2_open,
1356 .close = snd_intel8x0_mic2_close,
1357 .ioctl = snd_pcm_lib_ioctl,
1358 .hw_params = snd_intel8x0_hw_params,
1359 .hw_free = snd_intel8x0_hw_free,
1360 .prepare = snd_intel8x0_pcm_prepare,
1361 .trigger = snd_intel8x0_pcm_trigger,
1362 .pointer = snd_intel8x0_pcm_pointer,
1365 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1366 .open = snd_intel8x0_capture2_open,
1367 .close = snd_intel8x0_capture2_close,
1368 .ioctl = snd_pcm_lib_ioctl,
1369 .hw_params = snd_intel8x0_hw_params,
1370 .hw_free = snd_intel8x0_hw_free,
1371 .prepare = snd_intel8x0_pcm_prepare,
1372 .trigger = snd_intel8x0_pcm_trigger,
1373 .pointer = snd_intel8x0_pcm_pointer,
1376 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1377 .open = snd_intel8x0_spdif_open,
1378 .close = snd_intel8x0_spdif_close,
1379 .ioctl = snd_pcm_lib_ioctl,
1380 .hw_params = snd_intel8x0_hw_params,
1381 .hw_free = snd_intel8x0_hw_free,
1382 .prepare = snd_intel8x0_pcm_prepare,
1383 .trigger = snd_intel8x0_pcm_trigger,
1384 .pointer = snd_intel8x0_pcm_pointer,
1387 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1388 .open = snd_intel8x0_playback_open,
1389 .close = snd_intel8x0_playback_close,
1390 .ioctl = snd_pcm_lib_ioctl,
1391 .hw_params = snd_intel8x0_hw_params,
1392 .hw_free = snd_intel8x0_hw_free,
1393 .prepare = snd_intel8x0_pcm_prepare,
1394 .trigger = snd_intel8x0_ali_trigger,
1395 .pointer = snd_intel8x0_pcm_pointer,
1398 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1399 .open = snd_intel8x0_capture_open,
1400 .close = snd_intel8x0_capture_close,
1401 .ioctl = snd_pcm_lib_ioctl,
1402 .hw_params = snd_intel8x0_hw_params,
1403 .hw_free = snd_intel8x0_hw_free,
1404 .prepare = snd_intel8x0_pcm_prepare,
1405 .trigger = snd_intel8x0_ali_trigger,
1406 .pointer = snd_intel8x0_pcm_pointer,
1409 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1410 .open = snd_intel8x0_mic_open,
1411 .close = snd_intel8x0_mic_close,
1412 .ioctl = snd_pcm_lib_ioctl,
1413 .hw_params = snd_intel8x0_hw_params,
1414 .hw_free = snd_intel8x0_hw_free,
1415 .prepare = snd_intel8x0_pcm_prepare,
1416 .trigger = snd_intel8x0_ali_trigger,
1417 .pointer = snd_intel8x0_pcm_pointer,
1420 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1421 .open = snd_intel8x0_ali_ac97spdifout_open,
1422 .close = snd_intel8x0_ali_ac97spdifout_close,
1423 .ioctl = snd_pcm_lib_ioctl,
1424 .hw_params = snd_intel8x0_hw_params,
1425 .hw_free = snd_intel8x0_hw_free,
1426 .prepare = snd_intel8x0_pcm_prepare,
1427 .trigger = snd_intel8x0_ali_trigger,
1428 .pointer = snd_intel8x0_pcm_pointer,
1432 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1433 .open = snd_intel8x0_ali_spdifin_open,
1434 .close = snd_intel8x0_ali_spdifin_close,
1435 .ioctl = snd_pcm_lib_ioctl,
1436 .hw_params = snd_intel8x0_hw_params,
1437 .hw_free = snd_intel8x0_hw_free,
1438 .prepare = snd_intel8x0_pcm_prepare,
1439 .trigger = snd_intel8x0_pcm_trigger,
1440 .pointer = snd_intel8x0_pcm_pointer,
1443 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1444 .open = snd_intel8x0_ali_spdifout_open,
1445 .close = snd_intel8x0_ali_spdifout_close,
1446 .ioctl = snd_pcm_lib_ioctl,
1447 .hw_params = snd_intel8x0_hw_params,
1448 .hw_free = snd_intel8x0_hw_free,
1449 .prepare = snd_intel8x0_pcm_prepare,
1450 .trigger = snd_intel8x0_pcm_trigger,
1451 .pointer = snd_intel8x0_pcm_pointer,
1455 struct ich_pcm_table {
1457 const struct snd_pcm_ops *playback_ops;
1458 const struct snd_pcm_ops *capture_ops;
1459 size_t prealloc_size;
1460 size_t prealloc_max_size;
1464 #define intel8x0_dma_type(chip) \
1465 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1467 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1468 struct ich_pcm_table *rec)
1470 struct snd_pcm *pcm;
1475 sprintf(name, "Intel ICH - %s", rec->suffix);
1477 strcpy(name, "Intel ICH");
1478 err = snd_pcm_new(chip->card, name, device,
1479 rec->playback_ops ? 1 : 0,
1480 rec->capture_ops ? 1 : 0, &pcm);
1484 if (rec->playback_ops)
1485 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1486 if (rec->capture_ops)
1487 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1489 pcm->private_data = chip;
1490 pcm->info_flags = 0;
1492 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1494 strcpy(pcm->name, chip->card->shortname);
1495 chip->pcm[device] = pcm;
1497 snd_pcm_lib_preallocate_pages_for_all(pcm, intel8x0_dma_type(chip),
1498 snd_dma_pci_data(chip->pci),
1499 rec->prealloc_size, rec->prealloc_max_size);
1501 if (rec->playback_ops &&
1502 rec->playback_ops->open == snd_intel8x0_playback_open) {
1503 struct snd_pcm_chmap *chmap;
1507 else if (chip->multi6)
1509 else if (chip->multi4)
1511 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1512 snd_pcm_alt_chmaps, chs, 0,
1516 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1517 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1523 static struct ich_pcm_table intel_pcms[] = {
1525 .playback_ops = &snd_intel8x0_playback_ops,
1526 .capture_ops = &snd_intel8x0_capture_ops,
1527 .prealloc_size = 64 * 1024,
1528 .prealloc_max_size = 128 * 1024,
1531 .suffix = "MIC ADC",
1532 .capture_ops = &snd_intel8x0_capture_mic_ops,
1534 .prealloc_max_size = 128 * 1024,
1535 .ac97_idx = ICHD_MIC,
1538 .suffix = "MIC2 ADC",
1539 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1541 .prealloc_max_size = 128 * 1024,
1542 .ac97_idx = ICHD_MIC2,
1546 .capture_ops = &snd_intel8x0_capture2_ops,
1548 .prealloc_max_size = 128 * 1024,
1549 .ac97_idx = ICHD_PCM2IN,
1553 .playback_ops = &snd_intel8x0_spdif_ops,
1554 .prealloc_size = 64 * 1024,
1555 .prealloc_max_size = 128 * 1024,
1556 .ac97_idx = ICHD_SPBAR,
1560 static struct ich_pcm_table nforce_pcms[] = {
1562 .playback_ops = &snd_intel8x0_playback_ops,
1563 .capture_ops = &snd_intel8x0_capture_ops,
1564 .prealloc_size = 64 * 1024,
1565 .prealloc_max_size = 128 * 1024,
1568 .suffix = "MIC ADC",
1569 .capture_ops = &snd_intel8x0_capture_mic_ops,
1571 .prealloc_max_size = 128 * 1024,
1572 .ac97_idx = NVD_MIC,
1576 .playback_ops = &snd_intel8x0_spdif_ops,
1577 .prealloc_size = 64 * 1024,
1578 .prealloc_max_size = 128 * 1024,
1579 .ac97_idx = NVD_SPBAR,
1583 static struct ich_pcm_table ali_pcms[] = {
1585 .playback_ops = &snd_intel8x0_ali_playback_ops,
1586 .capture_ops = &snd_intel8x0_ali_capture_ops,
1587 .prealloc_size = 64 * 1024,
1588 .prealloc_max_size = 128 * 1024,
1591 .suffix = "MIC ADC",
1592 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1594 .prealloc_max_size = 128 * 1024,
1595 .ac97_idx = ALID_MIC,
1599 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1600 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1601 .prealloc_size = 64 * 1024,
1602 .prealloc_max_size = 128 * 1024,
1603 .ac97_idx = ALID_AC97SPDIFOUT,
1607 .suffix = "HW IEC958",
1608 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1609 .prealloc_size = 64 * 1024,
1610 .prealloc_max_size = 128 * 1024,
1615 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1617 int i, tblsize, device, err;
1618 struct ich_pcm_table *tbl, *rec;
1620 switch (chip->device_type) {
1621 case DEVICE_INTEL_ICH4:
1623 tblsize = ARRAY_SIZE(intel_pcms);
1629 tblsize = ARRAY_SIZE(nforce_pcms);
1635 tblsize = ARRAY_SIZE(ali_pcms);
1644 for (i = 0; i < tblsize; i++) {
1646 if (i > 0 && rec->ac97_idx) {
1647 /* activate PCM only when associated AC'97 codec */
1648 if (! chip->ichd[rec->ac97_idx].pcm)
1651 err = snd_intel8x0_pcm1(chip, device, rec);
1657 chip->pcm_devs = device;
1666 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1668 struct intel8x0 *chip = bus->private_data;
1669 chip->ac97_bus = NULL;
1672 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1674 struct intel8x0 *chip = ac97->private_data;
1675 chip->ac97[ac97->num] = NULL;
1678 static const struct ac97_pcm ac97_pcm_defs[] = {
1683 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1684 (1 << AC97_SLOT_PCM_RIGHT) |
1685 (1 << AC97_SLOT_PCM_CENTER) |
1686 (1 << AC97_SLOT_PCM_SLEFT) |
1687 (1 << AC97_SLOT_PCM_SRIGHT) |
1688 (1 << AC97_SLOT_LFE)
1691 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692 (1 << AC97_SLOT_PCM_RIGHT) |
1693 (1 << AC97_SLOT_PCM_LEFT_0) |
1694 (1 << AC97_SLOT_PCM_RIGHT_0)
1703 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1704 (1 << AC97_SLOT_PCM_RIGHT)
1713 .slots = (1 << AC97_SLOT_MIC)
1722 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1723 (1 << AC97_SLOT_SPDIF_RIGHT2)
1732 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1733 (1 << AC97_SLOT_PCM_RIGHT)
1742 .slots = (1 << AC97_SLOT_MIC)
1748 static const struct ac97_quirk ac97_quirks[] = {
1750 .subvendor = 0x0e11,
1751 .subdevice = 0x000e,
1752 .name = "Compaq Deskpro EN", /* AD1885 */
1753 .type = AC97_TUNE_HP_ONLY
1756 .subvendor = 0x0e11,
1757 .subdevice = 0x008a,
1758 .name = "Compaq Evo W4000", /* AD1885 */
1759 .type = AC97_TUNE_HP_ONLY
1762 .subvendor = 0x0e11,
1763 .subdevice = 0x00b8,
1764 .name = "Compaq Evo D510C",
1765 .type = AC97_TUNE_HP_ONLY
1768 .subvendor = 0x0e11,
1769 .subdevice = 0x0860,
1770 .name = "HP/Compaq nx7010",
1771 .type = AC97_TUNE_MUTE_LED
1774 .subvendor = 0x1014,
1775 .subdevice = 0x0534,
1776 .name = "ThinkPad X31",
1777 .type = AC97_TUNE_INV_EAPD
1780 .subvendor = 0x1014,
1781 .subdevice = 0x1f00,
1783 .type = AC97_TUNE_ALC_JACK
1786 .subvendor = 0x1014,
1787 .subdevice = 0x0267,
1788 .name = "IBM NetVista A30p", /* AD1981B */
1789 .type = AC97_TUNE_HP_ONLY
1792 .subvendor = 0x1025,
1793 .subdevice = 0x0082,
1794 .name = "Acer Travelmate 2310",
1795 .type = AC97_TUNE_HP_ONLY
1798 .subvendor = 0x1025,
1799 .subdevice = 0x0083,
1800 .name = "Acer Aspire 3003LCi",
1801 .type = AC97_TUNE_HP_ONLY
1804 .subvendor = 0x1028,
1805 .subdevice = 0x00d8,
1806 .name = "Dell Precision 530", /* AD1885 */
1807 .type = AC97_TUNE_HP_ONLY
1810 .subvendor = 0x1028,
1811 .subdevice = 0x010d,
1812 .name = "Dell", /* which model? AD1885 */
1813 .type = AC97_TUNE_HP_ONLY
1816 .subvendor = 0x1028,
1817 .subdevice = 0x0126,
1818 .name = "Dell Optiplex GX260", /* AD1981A */
1819 .type = AC97_TUNE_HP_ONLY
1822 .subvendor = 0x1028,
1823 .subdevice = 0x012c,
1824 .name = "Dell Precision 650", /* AD1981A */
1825 .type = AC97_TUNE_HP_ONLY
1828 .subvendor = 0x1028,
1829 .subdevice = 0x012d,
1830 .name = "Dell Precision 450", /* AD1981B*/
1831 .type = AC97_TUNE_HP_ONLY
1834 .subvendor = 0x1028,
1835 .subdevice = 0x0147,
1836 .name = "Dell", /* which model? AD1981B*/
1837 .type = AC97_TUNE_HP_ONLY
1840 .subvendor = 0x1028,
1841 .subdevice = 0x0151,
1842 .name = "Dell Optiplex GX270", /* AD1981B */
1843 .type = AC97_TUNE_HP_ONLY
1846 .subvendor = 0x1028,
1847 .subdevice = 0x014e,
1848 .name = "Dell D800", /* STAC9750/51 */
1849 .type = AC97_TUNE_HP_ONLY
1852 .subvendor = 0x1028,
1853 .subdevice = 0x0163,
1854 .name = "Dell Unknown", /* STAC9750/51 */
1855 .type = AC97_TUNE_HP_ONLY
1858 .subvendor = 0x1028,
1859 .subdevice = 0x016a,
1860 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1861 .type = AC97_TUNE_HP_ONLY
1864 .subvendor = 0x1028,
1865 .subdevice = 0x0182,
1866 .name = "Dell Latitude D610", /* STAC9750/51 */
1867 .type = AC97_TUNE_HP_ONLY
1870 .subvendor = 0x1028,
1871 .subdevice = 0x0186,
1872 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1873 .type = AC97_TUNE_HP_MUTE_LED
1876 .subvendor = 0x1028,
1877 .subdevice = 0x0188,
1878 .name = "Dell Inspiron 6000",
1879 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1882 .subvendor = 0x1028,
1883 .subdevice = 0x0189,
1884 .name = "Dell Inspiron 9300",
1885 .type = AC97_TUNE_HP_MUTE_LED
1888 .subvendor = 0x1028,
1889 .subdevice = 0x0191,
1890 .name = "Dell Inspiron 8600",
1891 .type = AC97_TUNE_HP_ONLY
1894 .subvendor = 0x103c,
1895 .subdevice = 0x006d,
1896 .name = "HP zv5000",
1897 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1899 { /* FIXME: which codec? */
1900 .subvendor = 0x103c,
1901 .subdevice = 0x00c3,
1902 .name = "HP xw6000",
1903 .type = AC97_TUNE_HP_ONLY
1906 .subvendor = 0x103c,
1907 .subdevice = 0x088c,
1908 .name = "HP nc8000",
1909 .type = AC97_TUNE_HP_MUTE_LED
1912 .subvendor = 0x103c,
1913 .subdevice = 0x0890,
1914 .name = "HP nc6000",
1915 .type = AC97_TUNE_MUTE_LED
1918 .subvendor = 0x103c,
1919 .subdevice = 0x129d,
1920 .name = "HP xw8000",
1921 .type = AC97_TUNE_HP_ONLY
1924 .subvendor = 0x103c,
1925 .subdevice = 0x0938,
1926 .name = "HP nc4200",
1927 .type = AC97_TUNE_HP_MUTE_LED
1930 .subvendor = 0x103c,
1931 .subdevice = 0x099c,
1932 .name = "HP nx6110/nc6120",
1933 .type = AC97_TUNE_HP_MUTE_LED
1936 .subvendor = 0x103c,
1937 .subdevice = 0x0944,
1938 .name = "HP nc6220",
1939 .type = AC97_TUNE_HP_MUTE_LED
1942 .subvendor = 0x103c,
1943 .subdevice = 0x0934,
1944 .name = "HP nc8220",
1945 .type = AC97_TUNE_HP_MUTE_LED
1948 .subvendor = 0x103c,
1949 .subdevice = 0x12f1,
1950 .name = "HP xw8200", /* AD1981B*/
1951 .type = AC97_TUNE_HP_ONLY
1954 .subvendor = 0x103c,
1955 .subdevice = 0x12f2,
1956 .name = "HP xw6200",
1957 .type = AC97_TUNE_HP_ONLY
1960 .subvendor = 0x103c,
1961 .subdevice = 0x3008,
1962 .name = "HP xw4200", /* AD1981B*/
1963 .type = AC97_TUNE_HP_ONLY
1966 .subvendor = 0x104d,
1967 .subdevice = 0x8144,
1969 .type = AC97_TUNE_INV_EAPD
1972 .subvendor = 0x104d,
1973 .subdevice = 0x8197,
1974 .name = "Sony S1XP",
1975 .type = AC97_TUNE_INV_EAPD
1978 .subvendor = 0x104d,
1979 .subdevice = 0x81c0,
1980 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1981 .type = AC97_TUNE_INV_EAPD
1984 .subvendor = 0x104d,
1985 .subdevice = 0x81c5,
1986 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1987 .type = AC97_TUNE_INV_EAPD
1990 .subvendor = 0x1043,
1991 .subdevice = 0x80f3,
1992 .name = "ASUS ICH5/AD1985",
1993 .type = AC97_TUNE_AD_SHARING
1996 .subvendor = 0x10cf,
1997 .subdevice = 0x11c3,
1998 .name = "Fujitsu-Siemens E4010",
1999 .type = AC97_TUNE_HP_ONLY
2002 .subvendor = 0x10cf,
2003 .subdevice = 0x1225,
2004 .name = "Fujitsu-Siemens T3010",
2005 .type = AC97_TUNE_HP_ONLY
2008 .subvendor = 0x10cf,
2009 .subdevice = 0x1253,
2010 .name = "Fujitsu S6210", /* STAC9750/51 */
2011 .type = AC97_TUNE_HP_ONLY
2014 .subvendor = 0x10cf,
2015 .subdevice = 0x127d,
2016 .name = "Fujitsu Lifebook P7010",
2017 .type = AC97_TUNE_HP_ONLY
2020 .subvendor = 0x10cf,
2021 .subdevice = 0x127e,
2022 .name = "Fujitsu Lifebook C1211D",
2023 .type = AC97_TUNE_HP_ONLY
2026 .subvendor = 0x10cf,
2027 .subdevice = 0x12ec,
2028 .name = "Fujitsu-Siemens 4010",
2029 .type = AC97_TUNE_HP_ONLY
2032 .subvendor = 0x10cf,
2033 .subdevice = 0x12f2,
2034 .name = "Fujitsu-Siemens Celsius H320",
2035 .type = AC97_TUNE_SWAP_HP
2038 .subvendor = 0x10f1,
2039 .subdevice = 0x2665,
2040 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2041 .type = AC97_TUNE_HP_ONLY
2044 .subvendor = 0x10f1,
2045 .subdevice = 0x2885,
2046 .name = "AMD64 Mobo", /* ALC650 */
2047 .type = AC97_TUNE_HP_ONLY
2050 .subvendor = 0x10f1,
2051 .subdevice = 0x2895,
2052 .name = "Tyan Thunder K8WE",
2053 .type = AC97_TUNE_HP_ONLY
2056 .subvendor = 0x10f7,
2057 .subdevice = 0x834c,
2058 .name = "Panasonic CF-R4",
2059 .type = AC97_TUNE_HP_ONLY,
2062 .subvendor = 0x110a,
2063 .subdevice = 0x0056,
2064 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2065 .type = AC97_TUNE_HP_ONLY
2068 .subvendor = 0x11d4,
2069 .subdevice = 0x5375,
2070 .name = "ADI AD1985 (discrete)",
2071 .type = AC97_TUNE_HP_ONLY
2074 .subvendor = 0x1462,
2075 .subdevice = 0x5470,
2076 .name = "MSI P4 ATX 645 Ultra",
2077 .type = AC97_TUNE_HP_ONLY
2080 .subvendor = 0x161f,
2081 .subdevice = 0x202f,
2082 .name = "Gateway M520",
2083 .type = AC97_TUNE_INV_EAPD
2086 .subvendor = 0x161f,
2087 .subdevice = 0x203a,
2088 .name = "Gateway 4525GZ", /* AD1981B */
2089 .type = AC97_TUNE_INV_EAPD
2092 .subvendor = 0x1734,
2093 .subdevice = 0x0088,
2094 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2095 .type = AC97_TUNE_HP_ONLY
2098 .subvendor = 0x8086,
2099 .subdevice = 0x2000,
2101 .name = "Intel ICH5/AD1985",
2102 .type = AC97_TUNE_AD_SHARING
2105 .subvendor = 0x8086,
2106 .subdevice = 0x4000,
2108 .name = "Intel ICH5/AD1985",
2109 .type = AC97_TUNE_AD_SHARING
2112 .subvendor = 0x8086,
2113 .subdevice = 0x4856,
2114 .name = "Intel D845WN (82801BA)",
2115 .type = AC97_TUNE_SWAP_HP
2118 .subvendor = 0x8086,
2119 .subdevice = 0x4d44,
2120 .name = "Intel D850EMV2", /* AD1885 */
2121 .type = AC97_TUNE_HP_ONLY
2124 .subvendor = 0x8086,
2125 .subdevice = 0x4d56,
2126 .name = "Intel ICH/AD1885",
2127 .type = AC97_TUNE_HP_ONLY
2130 .subvendor = 0x8086,
2131 .subdevice = 0x6000,
2133 .name = "Intel ICH5/AD1985",
2134 .type = AC97_TUNE_AD_SHARING
2137 .subvendor = 0x8086,
2138 .subdevice = 0xe000,
2140 .name = "Intel ICH5/AD1985",
2141 .type = AC97_TUNE_AD_SHARING
2143 #if 0 /* FIXME: this seems wrong on most boards */
2145 .subvendor = 0x8086,
2146 .subdevice = 0xa000,
2148 .name = "Intel ICH5/AD1985",
2149 .type = AC97_TUNE_HP_ONLY
2152 { } /* terminator */
2155 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2156 const char *quirk_override)
2158 struct snd_ac97_bus *pbus;
2159 struct snd_ac97_template ac97;
2161 unsigned int i, codecs;
2162 unsigned int glob_sta = 0;
2163 struct snd_ac97_bus_ops *ops;
2164 static struct snd_ac97_bus_ops standard_bus_ops = {
2165 .write = snd_intel8x0_codec_write,
2166 .read = snd_intel8x0_codec_read,
2168 static struct snd_ac97_bus_ops ali_bus_ops = {
2169 .write = snd_intel8x0_ali_codec_write,
2170 .read = snd_intel8x0_ali_codec_read,
2173 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2174 if (!spdif_aclink) {
2175 switch (chip->device_type) {
2177 chip->spdif_idx = NVD_SPBAR;
2180 chip->spdif_idx = ALID_AC97SPDIFOUT;
2182 case DEVICE_INTEL_ICH4:
2183 chip->spdif_idx = ICHD_SPBAR;
2188 chip->in_ac97_init = 1;
2190 memset(&ac97, 0, sizeof(ac97));
2191 ac97.private_data = chip;
2192 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2193 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2195 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2196 if (chip->device_type != DEVICE_ALI) {
2197 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2198 ops = &standard_bus_ops;
2199 chip->in_sdin_init = 1;
2201 for (i = 0; i < chip->max_codecs; i++) {
2202 if (! (glob_sta & chip->codec_bit[i]))
2204 if (chip->device_type == DEVICE_INTEL_ICH4) {
2205 snd_intel8x0_codec_read_test(chip, codecs);
2206 chip->ac97_sdin[codecs] =
2207 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2208 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2209 chip->ac97_sdin[codecs] = 0;
2211 chip->ac97_sdin[codecs] = i;
2214 chip->in_sdin_init = 0;
2220 /* detect the secondary codec */
2221 for (i = 0; i < 100; i++) {
2222 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2227 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2231 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2233 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2234 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2235 pbus->clock = ac97_clock;
2236 /* FIXME: my test board doesn't work well with VRA... */
2237 if (chip->device_type == DEVICE_ALI)
2241 chip->ac97_bus = pbus;
2242 chip->ncodecs = codecs;
2244 ac97.pci = chip->pci;
2245 for (i = 0; i < codecs; i++) {
2247 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2249 dev_err(chip->card->dev,
2250 "Unable to initialize codec #%d\n", i);
2255 /* tune up the primary codec */
2256 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2257 /* enable separate SDINs for ICH4 */
2258 if (chip->device_type == DEVICE_INTEL_ICH4)
2260 /* find the available PCM streams */
2261 i = ARRAY_SIZE(ac97_pcm_defs);
2262 if (chip->device_type != DEVICE_INTEL_ICH4)
2263 i -= 2; /* do not allocate PCM2IN and MIC2 */
2264 if (chip->spdif_idx < 0)
2265 i--; /* do not allocate S/PDIF */
2266 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2269 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2270 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2271 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2272 if (chip->spdif_idx >= 0)
2273 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2274 if (chip->device_type == DEVICE_INTEL_ICH4) {
2275 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2276 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2278 /* enable separate SDINs for ICH4 */
2279 if (chip->device_type == DEVICE_INTEL_ICH4) {
2280 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2281 u8 tmp = igetbyte(chip, ICHREG(SDM));
2282 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2284 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2285 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2286 for (i = 1; i < 4; i++) {
2287 if (pcm->r[0].codec[i]) {
2288 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2293 tmp &= ~ICH_SE; /* steer disable */
2295 iputbyte(chip, ICHREG(SDM), tmp);
2297 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2299 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2301 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2305 if (pbus->pcms[0].r[1].rslots[0]) {
2308 if (chip->device_type == DEVICE_INTEL_ICH4) {
2309 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2312 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2314 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2316 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2317 /* use slot 10/11 for SPDIF */
2319 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2320 val |= ICH_PCM_SPDIF_1011;
2321 iputdword(chip, ICHREG(GLOB_CNT), val);
2322 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2324 chip->in_ac97_init = 0;
2328 /* clear the cold-reset bit for the next chance */
2329 if (chip->device_type != DEVICE_ALI)
2330 iputdword(chip, ICHREG(GLOB_CNT),
2331 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2340 static void do_ali_reset(struct intel8x0 *chip)
2342 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2343 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2344 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2345 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2346 iputdword(chip, ICHREG(ALI_INTERFACECR),
2347 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2348 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2349 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2352 #ifdef CONFIG_SND_AC97_POWER_SAVE
2353 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2354 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2358 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2361 /* ACLink on, 2 channels */
2363 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2366 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2367 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2369 /* do cold reset - the full ac97 powerdown may leave the controller
2370 * in a warm state but actually it cannot communicate with the codec.
2372 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2373 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2375 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2379 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2380 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2382 #define snd_intel8x0_ich_chip_cold_reset(chip) 0
2383 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2386 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2388 unsigned long end_time;
2390 /* ACLink on, 2 channels */
2391 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2392 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2393 /* finish cold or do warm reset */
2394 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2395 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2396 end_time = (jiffies + (HZ / 4)) + 1;
2398 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2400 schedule_timeout_uninterruptible(1);
2401 } while (time_after_eq(end_time, jiffies));
2402 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2403 igetdword(chip, ICHREG(GLOB_CNT)));
2407 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2409 unsigned long end_time;
2410 unsigned int status, nstatus;
2414 /* put logic to right state */
2415 /* first clear status bits */
2416 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2417 if (chip->device_type == DEVICE_NFORCE)
2418 status |= ICH_NVSPINT;
2419 cnt = igetdword(chip, ICHREG(GLOB_STA));
2420 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2422 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2423 err = snd_intel8x0_ich_chip_cold_reset(chip);
2425 err = snd_intel8x0_ich_chip_reset(chip);
2430 /* wait for any codec ready status.
2431 * Once it becomes ready it should remain ready
2432 * as long as we do not disable the ac97 link.
2434 end_time = jiffies + HZ;
2436 status = igetdword(chip, ICHREG(GLOB_STA)) &
2437 chip->codec_isr_bits;
2440 schedule_timeout_uninterruptible(1);
2441 } while (time_after_eq(end_time, jiffies));
2443 /* no codec is found */
2444 dev_err(chip->card->dev,
2445 "codec_ready: codec is not ready [0x%x]\n",
2446 igetdword(chip, ICHREG(GLOB_STA)));
2450 /* wait for other codecs ready status. */
2451 end_time = jiffies + HZ / 4;
2452 while (status != chip->codec_isr_bits &&
2453 time_after_eq(end_time, jiffies)) {
2454 schedule_timeout_uninterruptible(1);
2455 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2456 chip->codec_isr_bits;
2463 for (i = 0; i < chip->ncodecs; i++)
2465 status |= chip->codec_bit[chip->ac97_sdin[i]];
2466 /* wait until all the probed codecs are ready */
2467 end_time = jiffies + HZ;
2469 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2470 chip->codec_isr_bits;
2471 if (status == nstatus)
2473 schedule_timeout_uninterruptible(1);
2474 } while (time_after_eq(end_time, jiffies));
2477 if (chip->device_type == DEVICE_SIS) {
2478 /* unmute the output on SIS7012 */
2479 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2481 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2482 /* enable SPDIF interrupt */
2484 pci_read_config_dword(chip->pci, 0x4c, &val);
2486 pci_write_config_dword(chip->pci, 0x4c, val);
2491 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2496 reg = igetdword(chip, ICHREG(ALI_SCR));
2497 if ((reg & 2) == 0) /* Cold required */
2500 reg |= 1; /* Warm */
2501 reg &= ~0x80000000; /* ACLink on */
2502 iputdword(chip, ICHREG(ALI_SCR), reg);
2504 for (i = 0; i < HZ / 2; i++) {
2505 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2507 schedule_timeout_uninterruptible(1);
2509 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2514 for (i = 0; i < HZ / 2; i++) {
2515 reg = igetdword(chip, ICHREG(ALI_RTSR));
2516 if (reg & 0x80) /* primary codec */
2518 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2519 schedule_timeout_uninterruptible(1);
2526 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2528 unsigned int i, timeout;
2531 if (chip->device_type != DEVICE_ALI) {
2532 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2534 iagetword(chip, 0); /* clear semaphore flag */
2536 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2540 /* disable interrupts */
2541 for (i = 0; i < chip->bdbars_count; i++)
2542 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2543 /* reset channels */
2544 for (i = 0; i < chip->bdbars_count; i++)
2545 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2546 for (i = 0; i < chip->bdbars_count; i++) {
2548 while (--timeout != 0) {
2549 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2553 dev_err(chip->card->dev, "reset of registers failed?\n");
2555 /* initialize Buffer Descriptor Lists */
2556 for (i = 0; i < chip->bdbars_count; i++)
2557 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2558 chip->ichd[i].bdbar_addr);
2562 static int snd_intel8x0_free(struct intel8x0 *chip)
2568 /* disable interrupts */
2569 for (i = 0; i < chip->bdbars_count; i++)
2570 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2571 /* reset channels */
2572 for (i = 0; i < chip->bdbars_count; i++)
2573 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2574 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2575 /* stop the spdif interrupt */
2577 pci_read_config_dword(chip->pci, 0x4c, &val);
2579 pci_write_config_dword(chip->pci, 0x4c, val);
2585 free_irq(chip->irq, chip);
2586 if (chip->bdbars.area)
2587 snd_dma_free_pages(&chip->bdbars);
2589 pci_iounmap(chip->pci, chip->addr);
2591 pci_iounmap(chip->pci, chip->bmaddr);
2592 pci_release_regions(chip->pci);
2593 pci_disable_device(chip->pci);
2598 #ifdef CONFIG_PM_SLEEP
2602 static int intel8x0_suspend(struct device *dev)
2604 struct snd_card *card = dev_get_drvdata(dev);
2605 struct intel8x0 *chip = card->private_data;
2608 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2609 for (i = 0; i < chip->ncodecs; i++)
2610 snd_ac97_suspend(chip->ac97[i]);
2611 if (chip->device_type == DEVICE_INTEL_ICH4)
2612 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2614 if (chip->irq >= 0) {
2615 free_irq(chip->irq, chip);
2621 static int intel8x0_resume(struct device *dev)
2623 struct pci_dev *pci = to_pci_dev(dev);
2624 struct snd_card *card = dev_get_drvdata(dev);
2625 struct intel8x0 *chip = card->private_data;
2628 snd_intel8x0_chip_init(chip, 0);
2629 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2630 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2631 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2633 snd_card_disconnect(card);
2636 chip->irq = pci->irq;
2637 synchronize_irq(chip->irq);
2639 /* re-initialize mixer stuff */
2640 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2641 /* enable separate SDINs for ICH4 */
2642 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2643 /* use slot 10/11 for SPDIF */
2644 iputdword(chip, ICHREG(GLOB_CNT),
2645 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2646 ICH_PCM_SPDIF_1011);
2649 for (i = 0; i < chip->ncodecs; i++)
2650 snd_ac97_resume(chip->ac97[i]);
2653 for (i = 0; i < chip->bdbars_count; i++) {
2654 struct ichdev *ichdev = &chip->ichd[i];
2655 unsigned long port = ichdev->reg_offset;
2656 if (! ichdev->substream || ! ichdev->suspended)
2658 if (ichdev->ichd == ICHD_PCMOUT)
2659 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2660 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2661 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2662 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2663 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2666 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2670 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2671 #define INTEL8X0_PM_OPS &intel8x0_pm
2673 #define INTEL8X0_PM_OPS NULL
2674 #endif /* CONFIG_PM_SLEEP */
2676 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2678 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2680 struct snd_pcm_substream *subs;
2681 struct ichdev *ichdev;
2683 unsigned long pos, pos1, t;
2684 int civ, timeout = 1000, attempt = 1;
2685 ktime_t start_time, stop_time;
2687 if (chip->ac97_bus->clock != 48000)
2688 return; /* specified in module option */
2691 subs = chip->pcm[0]->streams[0].substream;
2692 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2693 dev_warn(chip->card->dev,
2694 "no playback buffer allocated - aborting measure ac97 clock\n");
2697 ichdev = &chip->ichd[ICHD_PCMOUT];
2698 ichdev->physbuf = subs->dma_buffer.addr;
2699 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2700 ichdev->substream = NULL; /* don't process interrupts */
2703 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2704 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2705 chip->ac97_bus->clock);
2708 snd_intel8x0_setup_periods(chip, ichdev);
2709 port = ichdev->reg_offset;
2710 spin_lock_irq(&chip->reg_lock);
2711 chip->in_measurement = 1;
2713 if (chip->device_type != DEVICE_ALI)
2714 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2716 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2717 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2719 start_time = ktime_get();
2720 spin_unlock_irq(&chip->reg_lock);
2722 spin_lock_irq(&chip->reg_lock);
2723 /* check the position */
2725 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2726 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2731 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2732 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2734 } while (timeout--);
2735 if (pos1 == 0) { /* oops, this value is not reliable */
2738 pos = ichdev->fragsize1;
2739 pos -= pos1 << ichdev->pos_shift;
2740 pos += ichdev->position;
2742 chip->in_measurement = 0;
2743 stop_time = ktime_get();
2745 if (chip->device_type == DEVICE_ALI) {
2746 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2747 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2748 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2751 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2752 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2755 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2756 spin_unlock_irq(&chip->reg_lock);
2759 dev_err(chip->card->dev,
2760 "measure - unreliable DMA position..\n");
2771 t = ktime_us_delta(stop_time, start_time);
2772 dev_info(chip->card->dev,
2773 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2775 dev_err(chip->card->dev, "?? calculation error..\n");
2779 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2780 if (pos < 40000 || pos >= 60000) {
2781 /* abnormal value. hw problem? */
2782 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2784 } else if (pos > 40500 && pos < 41500)
2785 /* first exception - 41000Hz reference clock */
2786 chip->ac97_bus->clock = 41000;
2787 else if (pos > 43600 && pos < 44600)
2788 /* second exception - 44100HZ reference clock */
2789 chip->ac97_bus->clock = 44100;
2790 else if (pos < 47500 || pos > 48500)
2791 /* not 48000Hz, tuning the clock.. */
2792 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2794 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2795 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2798 static struct snd_pci_quirk intel8x0_clock_list[] = {
2799 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2800 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2801 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2802 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2803 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2804 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2805 { } /* terminator */
2808 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2810 struct pci_dev *pci = chip->pci;
2811 const struct snd_pci_quirk *wl;
2813 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2816 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2817 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2818 chip->ac97_bus->clock = wl->value;
2822 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2823 struct snd_info_buffer *buffer)
2825 struct intel8x0 *chip = entry->private_data;
2828 snd_iprintf(buffer, "Intel8x0\n\n");
2829 if (chip->device_type == DEVICE_ALI)
2831 tmp = igetdword(chip, ICHREG(GLOB_STA));
2832 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2833 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2834 if (chip->device_type == DEVICE_INTEL_ICH4)
2835 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2836 snd_iprintf(buffer, "AC'97 codecs ready :");
2837 if (tmp & chip->codec_isr_bits) {
2839 static const char *codecs[3] = {
2840 "primary", "secondary", "tertiary"
2842 for (i = 0; i < chip->max_codecs; i++)
2843 if (tmp & chip->codec_bit[i])
2844 snd_iprintf(buffer, " %s", codecs[i]);
2846 snd_iprintf(buffer, " none");
2847 snd_iprintf(buffer, "\n");
2848 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2849 chip->device_type == DEVICE_SIS)
2850 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2853 chip->ac97_sdin[2]);
2856 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2858 snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2859 snd_intel8x0_proc_read);
2862 static int snd_intel8x0_dev_free(struct snd_device *device)
2864 struct intel8x0 *chip = device->device_data;
2865 return snd_intel8x0_free(chip);
2868 struct ich_reg_info {
2869 unsigned int int_sta_mask;
2870 unsigned int offset;
2873 static unsigned int ich_codec_bits[3] = {
2874 ICH_PCR, ICH_SCR, ICH_TCR
2876 static unsigned int sis_codec_bits[3] = {
2877 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2880 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2882 int result = inside_vm;
2885 /* check module parameter first (override detection) */
2887 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2891 /* check for known (emulated) devices */
2893 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2894 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2895 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2898 } else if (pci->subsystem_vendor == 0x1ab8) {
2899 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2900 msg = "enable Parallels VM";
2906 dev_info(&pci->dev, "%s optimization\n", msg);
2911 static int snd_intel8x0_create(struct snd_card *card,
2912 struct pci_dev *pci,
2913 unsigned long device_type,
2914 struct intel8x0 **r_intel8x0)
2916 struct intel8x0 *chip;
2919 unsigned int int_sta_masks;
2920 struct ichdev *ichdev;
2921 static struct snd_device_ops ops = {
2922 .dev_free = snd_intel8x0_dev_free,
2925 static unsigned int bdbars[] = {
2926 3, /* DEVICE_INTEL */
2927 6, /* DEVICE_INTEL_ICH4 */
2930 4, /* DEVICE_NFORCE */
2932 static struct ich_reg_info intel_regs[6] = {
2934 { ICH_POINT, 0x10 },
2935 { ICH_MCINT, 0x20 },
2936 { ICH_M2INT, 0x40 },
2937 { ICH_P2INT, 0x50 },
2938 { ICH_SPINT, 0x60 },
2940 static struct ich_reg_info nforce_regs[4] = {
2942 { ICH_POINT, 0x10 },
2943 { ICH_MCINT, 0x20 },
2944 { ICH_NVSPINT, 0x70 },
2946 static struct ich_reg_info ali_regs[6] = {
2947 { ALI_INT_PCMIN, 0x40 },
2948 { ALI_INT_PCMOUT, 0x50 },
2949 { ALI_INT_MICIN, 0x60 },
2950 { ALI_INT_CODECSPDIFOUT, 0x70 },
2951 { ALI_INT_SPDIFIN, 0xa0 },
2952 { ALI_INT_SPDIFOUT, 0xb0 },
2954 struct ich_reg_info *tbl;
2958 if ((err = pci_enable_device(pci)) < 0)
2961 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2963 pci_disable_device(pci);
2966 spin_lock_init(&chip->reg_lock);
2967 chip->device_type = device_type;
2972 /* module parameters */
2973 chip->buggy_irq = buggy_irq;
2974 chip->buggy_semaphore = buggy_semaphore;
2978 chip->inside_vm = snd_intel8x0_inside_vm(pci);
2981 * Intel 82443MX running a 100MHz processor system bus has a hardware
2982 * bug, which aborts PCI busmaster for audio transfer. A workaround
2983 * is to set the pages as non-cached. For details, see the errata in
2984 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2986 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2987 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2988 chip->fix_nocache = 1; /* enable workaround */
2990 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2992 pci_disable_device(pci);
2996 if (device_type == DEVICE_ALI) {
2997 /* ALI5455 has no ac97 region */
2998 chip->bmaddr = pci_iomap(pci, 0, 0);
3002 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3003 chip->addr = pci_iomap(pci, 2, 0);
3005 chip->addr = pci_iomap(pci, 0, 0);
3007 dev_err(card->dev, "AC'97 space ioremap problem\n");
3008 snd_intel8x0_free(chip);
3011 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3012 chip->bmaddr = pci_iomap(pci, 3, 0);
3014 chip->bmaddr = pci_iomap(pci, 1, 0);
3017 if (!chip->bmaddr) {
3018 dev_err(card->dev, "Controller space ioremap problem\n");
3019 snd_intel8x0_free(chip);
3022 chip->bdbars_count = bdbars[device_type];
3024 /* initialize offsets */
3025 switch (device_type) {
3036 for (i = 0; i < chip->bdbars_count; i++) {
3037 ichdev = &chip->ichd[i];
3039 ichdev->reg_offset = tbl[i].offset;
3040 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3041 if (device_type == DEVICE_SIS) {
3042 /* SiS 7012 swaps the registers */
3043 ichdev->roff_sr = ICH_REG_OFF_PICB;
3044 ichdev->roff_picb = ICH_REG_OFF_SR;
3046 ichdev->roff_sr = ICH_REG_OFF_SR;
3047 ichdev->roff_picb = ICH_REG_OFF_PICB;
3049 if (device_type == DEVICE_ALI)
3050 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3051 /* SIS7012 handles the pcm data in bytes, others are in samples */
3052 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3055 /* allocate buffer descriptor lists */
3056 /* the start of each lists must be aligned to 8 bytes */
3057 if (snd_dma_alloc_pages(intel8x0_dma_type(chip), snd_dma_pci_data(pci),
3058 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3059 &chip->bdbars) < 0) {
3060 snd_intel8x0_free(chip);
3061 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3064 /* tables must be aligned to 8 bytes here, but the kernel pages
3065 are much bigger, so we don't care (on i386) */
3067 for (i = 0; i < chip->bdbars_count; i++) {
3068 ichdev = &chip->ichd[i];
3069 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3070 (i * ICH_MAX_FRAGS * 2);
3071 ichdev->bdbar_addr = chip->bdbars.addr +
3072 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3073 int_sta_masks |= ichdev->int_sta_mask;
3075 chip->int_sta_reg = device_type == DEVICE_ALI ?
3076 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3077 chip->int_sta_mask = int_sta_masks;
3079 pci_set_master(pci);
3081 switch(chip->device_type) {
3082 case DEVICE_INTEL_ICH4:
3083 /* ICH4 can have three codecs */
3084 chip->max_codecs = 3;
3085 chip->codec_bit = ich_codec_bits;
3086 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3089 /* recent SIS7012 can have three codecs */
3090 chip->max_codecs = 3;
3091 chip->codec_bit = sis_codec_bits;
3092 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3095 /* others up to two codecs */
3096 chip->max_codecs = 2;
3097 chip->codec_bit = ich_codec_bits;
3098 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3101 for (i = 0; i < chip->max_codecs; i++)
3102 chip->codec_isr_bits |= chip->codec_bit[i];
3104 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3105 snd_intel8x0_free(chip);
3109 /* request irq after initializaing int_sta_mask, etc */
3110 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3111 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3112 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3113 snd_intel8x0_free(chip);
3116 chip->irq = pci->irq;
3118 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3119 snd_intel8x0_free(chip);
3127 static struct shortname_table {
3131 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3132 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3133 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3134 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3135 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3136 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3137 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3138 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3139 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3140 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3141 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3142 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3143 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3144 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3145 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3146 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3147 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3148 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3149 { 0x003a, "NVidia MCP04" },
3150 { 0x746d, "AMD AMD8111" },
3151 { 0x7445, "AMD AMD768" },
3152 { 0x5455, "ALi M5455" },
3156 static struct snd_pci_quirk spdif_aclink_defaults[] = {
3157 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3161 /* look up white/black list for SPDIF over ac-link */
3162 static int check_default_spdif_aclink(struct pci_dev *pci)
3164 const struct snd_pci_quirk *w;
3166 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3170 "Using SPDIF over AC-Link for %s\n",
3171 snd_pci_quirk_name(w));
3174 "Using integrated SPDIF DMA for %s\n",
3175 snd_pci_quirk_name(w));
3181 static int snd_intel8x0_probe(struct pci_dev *pci,
3182 const struct pci_device_id *pci_id)
3184 struct snd_card *card;
3185 struct intel8x0 *chip;
3187 struct shortname_table *name;
3189 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3193 if (spdif_aclink < 0)
3194 spdif_aclink = check_default_spdif_aclink(pci);
3196 strcpy(card->driver, "ICH");
3197 if (!spdif_aclink) {
3198 switch (pci_id->driver_data) {
3200 strcpy(card->driver, "NFORCE");
3202 case DEVICE_INTEL_ICH4:
3203 strcpy(card->driver, "ICH4");
3207 strcpy(card->shortname, "Intel ICH");
3208 for (name = shortnames; name->id; name++) {
3209 if (pci->device == name->id) {
3210 strcpy(card->shortname, name->s);
3215 if (buggy_irq < 0) {
3216 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3217 * Needs to return IRQ_HANDLED for unknown irqs.
3219 if (pci_id->driver_data == DEVICE_NFORCE)
3225 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3227 snd_card_free(card);
3230 card->private_data = chip;
3232 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3233 snd_card_free(card);
3236 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3237 snd_card_free(card);
3241 snd_intel8x0_proc_init(chip);
3243 snprintf(card->longname, sizeof(card->longname),
3244 "%s with %s at irq %i", card->shortname,
3245 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3247 if (ac97_clock == 0 || ac97_clock == 1) {
3248 if (ac97_clock == 0) {
3249 if (intel8x0_in_clock_list(chip) == 0)
3250 intel8x0_measure_ac97_clock(chip);
3252 intel8x0_measure_ac97_clock(chip);
3256 if ((err = snd_card_register(card)) < 0) {
3257 snd_card_free(card);
3260 pci_set_drvdata(pci, card);
3264 static void snd_intel8x0_remove(struct pci_dev *pci)
3266 snd_card_free(pci_get_drvdata(pci));
3269 static struct pci_driver intel8x0_driver = {
3270 .name = KBUILD_MODNAME,
3271 .id_table = snd_intel8x0_ids,
3272 .probe = snd_intel8x0_probe,
3273 .remove = snd_intel8x0_remove,
3275 .pm = INTEL8X0_PM_OPS,
3279 module_pci_driver(intel8x0_driver);