sound/pci/intel8x0.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for Intel ICH (i8x0) chipsets
   4  *
   5  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/ac97_codec.h>
  24 #include <sound/info.h>
  25 #include <sound/initval.h>
  26
  27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  29 MODULE_LICENSE("GPL");
  30 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  31                 "{Intel,82901AB-ICH0},"
  32                 "{Intel,82801BA-ICH2},"
  33                 "{Intel,82801CA-ICH3},"
  34                 "{Intel,82801DB-ICH4},"
  35                 "{Intel,ICH5},"
  36                 "{Intel,ICH6},"
  37                 "{Intel,ICH7},"
  38                 "{Intel,6300ESB},"
  39                 "{Intel,ESB2},"
  40                 "{Intel,MX440},"
  41                 "{SiS,SI7012},"
  42                 "{NVidia,nForce Audio},"
  43                 "{NVidia,nForce2 Audio},"
  44                 "{NVidia,nForce3 Audio},"
  45                 "{NVidia,MCP04},"
  46                 "{NVidia,MCP501},"
  47                 "{NVidia,CK804},"
  48                 "{NVidia,CK8},"
  49                 "{NVidia,CK8S},"
  50                 "{AMD,AMD768},"
  51                 "{AMD,AMD8111},"
  52                 "{ALI,M5455}}");
  53
  54 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  55 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  56 static int ac97_clock;
  57 static char *ac97_quirk;
  58 static bool buggy_semaphore;
  59 static int buggy_irq = -1; /* auto-check */
  60 static bool xbox;
  61 static int spdif_aclink = -1;
  62 static int inside_vm = -1;
  63
  64 module_param(index, int, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  66 module_param(id, charp, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  68 module_param(ac97_clock, int, 0444);
  69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
  70 module_param(ac97_quirk, charp, 0444);
  71 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  72 module_param(buggy_semaphore, bool, 0444);
  73 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  74 module_param(buggy_irq, bint, 0444);
  75 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  76 module_param(xbox, bool, 0444);
  77 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  78 module_param(spdif_aclink, int, 0444);
  79 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  80 module_param(inside_vm, bint, 0444);
  81 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  82
  83 /* just for backward compatibility */
  84 static bool enable;
  85 module_param(enable, bool, 0444);
  86 static int joystick;
  87 module_param(joystick, int, 0444);
  88
  89 /*
  90  *  Direct registers
  91  */
  92 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  93
  94 #define ICHREG(x) ICH_REG_##x
  95
  96 #define DEFINE_REGSET(name,base) \
  97 enum { \
  98         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
  99         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 100         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 101         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 102         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 103         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 104         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 105 };
 106
 107 /* busmaster blocks */
 108 DEFINE_REGSET(OFF, 0);          /* offset */
 109 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 110 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 111 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 112
 113 /* ICH4 busmaster blocks */
 114 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 115 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 116 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 117
 118 /* values for each busmaster block */
 119
 120 /* LVI */
 121 #define ICH_REG_LVI_MASK                0x1f
 122
 123 /* SR */
 124 #define ICH_FIFOE                       0x10    /* FIFO error */
 125 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 126 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 127 #define ICH_CELV                        0x02    /* current equals last valid */
 128 #define ICH_DCH                         0x01    /* DMA controller halted */
 129
 130 /* PIV */
 131 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 132
 133 /* CR */
 134 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 135 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 136 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 137 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 138 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 139
 140
 141 /* global block */
 142 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 143 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 144 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 145 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 146 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 147 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 148 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 149 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 150 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 151 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 152 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 153 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 154 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 155 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 156 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 157 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 158 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 159 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 160 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 161 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 162 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 163 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 164 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 165 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 166 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 167 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 168 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 169 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 170 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 171 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 172 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 173 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 174 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 175 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 176 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 177 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 178 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 179 #define   ICH_RCS               0x00008000      /* read completion status */
 180 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 181 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 182 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 183 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 184 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 185 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 186 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 187 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 188 #define   ICH_POINT             0x00000040      /* playback interrupt */
 189 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 190 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 191 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 192 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 193 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 194 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 195 #define   ICH_CAS               0x01            /* codec access semaphore */
 196 #define ICH_REG_SDM             0x80
 197 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 198 #define   ICH_DI2L_SHIFT        6
 199 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 200 #define   ICH_DI1L_SHIFT        4
 201 #define   ICH_SE                0x00000008      /* steer enable */
 202 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 203
 204 #define ICH_MAX_FRAGS           32              /* max hw frags */
 205
 206
 207 /*
 208  * registers for Ali5455
 209  */
 210
 211 /* ALi 5455 busmaster blocks */
 212 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 213 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 214 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 215 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 216 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 217 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 218 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 219 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 220 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 221 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 222 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 223
 224 enum {
 225         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 226         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 227         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 228         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 229         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 230         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 231         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 232         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 233         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 234         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 235         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 236         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 237         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 238         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 239         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 240         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 241         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 242         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 243         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 244         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 245         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 246 };
 247
 248 #define ALI_CAS_SEM_BUSY        0x80000000
 249 #define ALI_CPR_ADDR_SECONDARY  0x100
 250 #define ALI_CPR_ADDR_READ       0x80
 251 #define ALI_CSPSR_CODEC_READY   0x08
 252 #define ALI_CSPSR_READ_OK       0x02
 253 #define ALI_CSPSR_WRITE_OK      0x01
 254
 255 /* interrupts for the whole chip by interrupt status register finish */
 256
 257 #define ALI_INT_MICIN2          (1<<26)
 258 #define ALI_INT_PCMIN2          (1<<25)
 259 #define ALI_INT_I2SIN           (1<<24)
 260 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 261 #define ALI_INT_SPDIFIN         (1<<22)
 262 #define ALI_INT_LFEOUT          (1<<21)
 263 #define ALI_INT_CENTEROUT       (1<<20)
 264 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 265 #define ALI_INT_MICIN           (1<<18)
 266 #define ALI_INT_PCMOUT          (1<<17)
 267 #define ALI_INT_PCMIN           (1<<16)
 268 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 269 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 270 #define ALI_INT_GPIO            (1<<1)
 271 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 272                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 273
 274 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 275 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 276 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 277 #define ICH_ALI_SC_IN_BITS      (3<<18)
 278 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 279 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 280 #define ICH_ALI_SC_PCM_4        (1<<8)
 281 #define ICH_ALI_SC_PCM_6        (2<<8)
 282 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 283
 284 #define ICH_ALI_SS_SEC_ID       (3<<5)
 285 #define ICH_ALI_SS_PRI_ID       (3<<3)
 286
 287 #define ICH_ALI_IF_AC97SP       (1<<21)
 288 #define ICH_ALI_IF_MC           (1<<20)
 289 #define ICH_ALI_IF_PI           (1<<19)
 290 #define ICH_ALI_IF_MC2          (1<<18)
 291 #define ICH_ALI_IF_PI2          (1<<17)
 292 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 293 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 294 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 295 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 296 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 297 #define ICH_ALI_IF_PO           (1<<1)
 298
 299 /*
 300  *
 301  */
 302
 303 enum {
 304         ICHD_PCMIN,
 305         ICHD_PCMOUT,
 306         ICHD_MIC,
 307         ICHD_MIC2,
 308         ICHD_PCM2IN,
 309         ICHD_SPBAR,
 310         ICHD_LAST = ICHD_SPBAR
 311 };
 312 enum {
 313         NVD_PCMIN,
 314         NVD_PCMOUT,
 315         NVD_MIC,
 316         NVD_SPBAR,
 317         NVD_LAST = NVD_SPBAR
 318 };
 319 enum {
 320         ALID_PCMIN,
 321         ALID_PCMOUT,
 322         ALID_MIC,
 323         ALID_AC97SPDIFOUT,
 324         ALID_SPDIFIN,
 325         ALID_SPDIFOUT,
 326         ALID_LAST = ALID_SPDIFOUT
 327 };
 328
 329 #define get_ichdev(substream) (substream->runtime->private_data)
 330
 331 struct ichdev {
 332         unsigned int ichd;                      /* ich device number */
 333         unsigned long reg_offset;               /* offset to bmaddr */
 334         __le32 *bdbar;                          /* CPU address (32bit) */
 335         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 336         struct snd_pcm_substream *substream;
 337         unsigned int physbuf;                   /* physical address (32bit) */
 338         unsigned int size;
 339         unsigned int fragsize;
 340         unsigned int fragsize1;
 341         unsigned int position;
 342         unsigned int pos_shift;
 343         unsigned int last_pos;
 344         int frags;
 345         int lvi;
 346         int lvi_frag;
 347         int civ;
 348         int ack;
 349         int ack_reload;
 350         unsigned int ack_bit;
 351         unsigned int roff_sr;
 352         unsigned int roff_picb;
 353         unsigned int int_sta_mask;              /* interrupt status mask */
 354         unsigned int ali_slot;                  /* ALI DMA slot */
 355         struct ac97_pcm *pcm;
 356         int pcm_open_flag;
 357         unsigned int prepared:1;
 358         unsigned int suspended: 1;
 359 };
 360
 361 struct intel8x0 {
 362         unsigned int device_type;
 363
 364         int irq;
 365
 366         void __iomem *addr;
 367         void __iomem *bmaddr;
 368
 369         struct pci_dev *pci;
 370         struct snd_card *card;
 371
 372         int pcm_devs;
 373         struct snd_pcm *pcm[6];
 374         struct ichdev ichd[6];
 375
 376         unsigned multi4: 1,
 377                  multi6: 1,
 378                  multi8 :1,
 379                  dra: 1,
 380                  smp20bit: 1;
 381         unsigned in_ac97_init: 1,
 382                  in_sdin_init: 1;
 383         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 384         unsigned fix_nocache: 1;        /* workaround for 440MX */
 385         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 386         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 387         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 388         unsigned inside_vm: 1;          /* enable VM optimization */
 389
 390         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 391         unsigned int sdm_saved; /* SDM reg value */
 392
 393         struct snd_ac97_bus *ac97_bus;
 394         struct snd_ac97 *ac97[3];
 395         unsigned int ac97_sdin[3];
 396         unsigned int max_codecs, ncodecs;
 397         unsigned int *codec_bit;
 398         unsigned int codec_isr_bits;
 399         unsigned int codec_ready_bits;
 400
 401         spinlock_t reg_lock;
 402
 403         u32 bdbars_count;
 404         struct snd_dma_buffer bdbars;
 405         u32 int_sta_reg;                /* interrupt status register */
 406         u32 int_sta_mask;               /* interrupt status mask */
 407 };
 408
 409 static const struct pci_device_id snd_intel8x0_ids[] = {
 410         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
 411         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
 412         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
 413         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
 414         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
 415         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
 416         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
 417         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
 418         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
 419         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
 420         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
 421         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
 422         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
 423         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
 424         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
 425         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
 426         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
 427         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
 428         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
 429         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
 430         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
 431         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
 432         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
 433         { 0, }
 434 };
 435
 436 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 437
 438 /*
 439  *  Lowlevel I/O - busmaster
 440  */
 441
 442 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 443 {
 444         return ioread8(chip->bmaddr + offset);
 445 }
 446
 447 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 448 {
 449         return ioread16(chip->bmaddr + offset);
 450 }
 451
 452 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 453 {
 454         return ioread32(chip->bmaddr + offset);
 455 }
 456
 457 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 458 {
 459         iowrite8(val, chip->bmaddr + offset);
 460 }
 461
 462 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 463 {
 464         iowrite16(val, chip->bmaddr + offset);
 465 }
 466
 467 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 468 {
 469         iowrite32(val, chip->bmaddr + offset);
 470 }
 471
 472 /*
 473  *  Lowlevel I/O - AC'97 registers
 474  */
 475
 476 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 477 {
 478         return ioread16(chip->addr + offset);
 479 }
 480
 481 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 482 {
 483         iowrite16(val, chip->addr + offset);
 484 }
 485
 486 /*
 487  *  Basic I/O
 488  */
 489
 490 /*
 491  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 492  */
 493
 494 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 495 {
 496         int time;
 497
 498         if (codec > 2)
 499                 return -EIO;
 500         if (chip->in_sdin_init) {
 501                 /* we don't know the ready bit assignment at the moment */
 502                 /* so we check any */
 503                 codec = chip->codec_isr_bits;
 504         } else {
 505                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 506         }
 507
 508         /* codec ready ? */
 509         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 510                 return -EIO;
 511
 512         if (chip->buggy_semaphore)
 513                 return 0; /* just ignore ... */
 514
 515         /* Anyone holding a semaphore for 1 msec should be shot... */
 516         time = 100;
 517         do {
 518                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 519                         return 0;
 520                 udelay(10);
 521         } while (time--);
 522
 523         /* access to some forbidden (non existent) ac97 registers will not
 524          * reset the semaphore. So even if you don't get the semaphore, still
 525          * continue the access. We don't need the semaphore anyway. */
 526         dev_err(chip->card->dev,
 527                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 528                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 529         iagetword(chip, 0);     /* clear semaphore flag */
 530         /* I don't care about the semaphore */
 531         return -EBUSY;
 532 }
 533
 534 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 535                                      unsigned short reg,
 536                                      unsigned short val)
 537 {
 538         struct intel8x0 *chip = ac97->private_data;
 539
 540         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 541                 if (! chip->in_ac97_init)
 542                         dev_err(chip->card->dev,
 543                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
 544                                 ac97->num, reg);
 545         }
 546         iaputword(chip, reg + ac97->num * 0x80, val);
 547 }
 548
 549 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 550                                               unsigned short reg)
 551 {
 552         struct intel8x0 *chip = ac97->private_data;
 553         unsigned short res;
 554         unsigned int tmp;
 555
 556         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 557                 if (! chip->in_ac97_init)
 558                         dev_err(chip->card->dev,
 559                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
 560                                 ac97->num, reg);
 561                 res = 0xffff;
 562         } else {
 563                 res = iagetword(chip, reg + ac97->num * 0x80);
 564                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 565                         /* reset RCS and preserve other R/WC bits */
 566                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 567                                   ~(chip->codec_ready_bits | ICH_GSCI));
 568                         if (! chip->in_ac97_init)
 569                                 dev_err(chip->card->dev,
 570                                         "codec_read %d: read timeout for register 0x%x\n",
 571                                         ac97->num, reg);
 572                         res = 0xffff;
 573                 }
 574         }
 575         return res;
 576 }
 577
 578 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 579                                          unsigned int codec)
 580 {
 581         unsigned int tmp;
 582
 583         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 584                 iagetword(chip, codec * 0x80);
 585                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 586                         /* reset RCS and preserve other R/WC bits */
 587                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 588                                   ~(chip->codec_ready_bits | ICH_GSCI));
 589                 }
 590         }
 591 }
 592
 593 /*
 594  * access to AC97 for Ali5455
 595  */
 596 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 597 {
 598         int count = 0;
 599         for (count = 0; count < 0x7f; count++) {
 600                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 601                 if (val & mask)
 602                         return 0;
 603         }
 604         if (! chip->in_ac97_init)
 605                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
 606         return -EBUSY;
 607 }
 608
 609 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 610 {
 611         int time = 100;
 612         if (chip->buggy_semaphore)
 613                 return 0; /* just ignore ... */
 614         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 615                 udelay(1);
 616         if (! time && ! chip->in_ac97_init)
 617                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
 618         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 619 }
 620
 621 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 622 {
 623         struct intel8x0 *chip = ac97->private_data;
 624         unsigned short data = 0xffff;
 625
 626         if (snd_intel8x0_ali_codec_semaphore(chip))
 627                 goto __err;
 628         reg |= ALI_CPR_ADDR_READ;
 629         if (ac97->num)
 630                 reg |= ALI_CPR_ADDR_SECONDARY;
 631         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 632         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 633                 goto __err;
 634         data = igetword(chip, ICHREG(ALI_SPR));
 635  __err:
 636         return data;
 637 }
 638
 639 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 640                                          unsigned short val)
 641 {
 642         struct intel8x0 *chip = ac97->private_data;
 643
 644         if (snd_intel8x0_ali_codec_semaphore(chip))
 645                 return;
 646         iputword(chip, ICHREG(ALI_CPR), val);
 647         if (ac97->num)
 648                 reg |= ALI_CPR_ADDR_SECONDARY;
 649         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 650         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 651 }
 652
 653
 654 /*
 655  * DMA I/O
 656  */
 657 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 658 {
 659         int idx;
 660         __le32 *bdbar = ichdev->bdbar;
 661         unsigned long port = ichdev->reg_offset;
 662
 663         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 664         if (ichdev->size == ichdev->fragsize) {
 665                 ichdev->ack_reload = ichdev->ack = 2;
 666                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 667                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 668                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 669                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 670                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 671                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 672                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 673                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 674                 }
 675                 ichdev->frags = 2;
 676         } else {
 677                 ichdev->ack_reload = ichdev->ack = 1;
 678                 ichdev->fragsize1 = ichdev->fragsize;
 679                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 680                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 681                                                      (((idx >> 1) * ichdev->fragsize) %
 682                                                       ichdev->size));
 683                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 684                                                      ichdev->fragsize >> ichdev->pos_shift);
 685 #if 0
 686                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
 687                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 688 #endif
 689                 }
 690                 ichdev->frags = ichdev->size / ichdev->fragsize;
 691         }
 692         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 693         ichdev->civ = 0;
 694         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 695         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 696         ichdev->position = 0;
 697 #if 0
 698         dev_dbg(chip->card->dev,
 699                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 700                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
 701                ichdev->fragsize1);
 702 #endif
 703         /* clear interrupts */
 704         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 705 }
 706
 707 /*
 708  *  Interrupt handler
 709  */
 710
 711 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 712 {
 713         unsigned long port = ichdev->reg_offset;
 714         unsigned long flags;
 715         int status, civ, i, step;
 716         int ack = 0;
 717
 718         if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
 719                 return;
 720
 721         spin_lock_irqsave(&chip->reg_lock, flags);
 722         status = igetbyte(chip, port + ichdev->roff_sr);
 723         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 724         if (!(status & ICH_BCIS)) {
 725                 step = 0;
 726         } else if (civ == ichdev->civ) {
 727                 // snd_printd("civ same %d\n", civ);
 728                 step = 1;
 729                 ichdev->civ++;
 730                 ichdev->civ &= ICH_REG_LVI_MASK;
 731         } else {
 732                 step = civ - ichdev->civ;
 733                 if (step < 0)
 734                         step += ICH_REG_LVI_MASK + 1;
 735                 // if (step != 1)
 736                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 737                 ichdev->civ = civ;
 738         }
 739
 740         ichdev->position += step * ichdev->fragsize1;
 741         if (! chip->in_measurement)
 742                 ichdev->position %= ichdev->size;
 743         ichdev->lvi += step;
 744         ichdev->lvi &= ICH_REG_LVI_MASK;
 745         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 746         for (i = 0; i < step; i++) {
 747                 ichdev->lvi_frag++;
 748                 ichdev->lvi_frag %= ichdev->frags;
 749                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 750 #if 0
 751         dev_dbg(chip->card->dev,
 752                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 753                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 754                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 755                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 756 #endif
 757                 if (--ichdev->ack == 0) {
 758                         ichdev->ack = ichdev->ack_reload;
 759                         ack = 1;
 760                 }
 761         }
 762         spin_unlock_irqrestore(&chip->reg_lock, flags);
 763         if (ack && ichdev->substream) {
 764                 snd_pcm_period_elapsed(ichdev->substream);
 765         }
 766         iputbyte(chip, port + ichdev->roff_sr,
 767                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 768 }
 769
 770 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 771 {
 772         struct intel8x0 *chip = dev_id;
 773         struct ichdev *ichdev;
 774         unsigned int status;
 775         unsigned int i;
 776
 777         status = igetdword(chip, chip->int_sta_reg);
 778         if (status == 0xffffffff)       /* we are not yet resumed */
 779                 return IRQ_NONE;
 780
 781         if ((status & chip->int_sta_mask) == 0) {
 782                 if (status) {
 783                         /* ack */
 784                         iputdword(chip, chip->int_sta_reg, status);
 785                         if (! chip->buggy_irq)
 786                                 status = 0;
 787                 }
 788                 return IRQ_RETVAL(status);
 789         }
 790
 791         for (i = 0; i < chip->bdbars_count; i++) {
 792                 ichdev = &chip->ichd[i];
 793                 if (status & ichdev->int_sta_mask)
 794                         snd_intel8x0_update(chip, ichdev);
 795         }
 796
 797         /* ack them */
 798         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 799
 800         return IRQ_HANDLED;
 801 }
 802
 803 /*
 804  *  PCM part
 805  */
 806
 807 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 808 {
 809         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 810         struct ichdev *ichdev = get_ichdev(substream);
 811         unsigned char val = 0;
 812         unsigned long port = ichdev->reg_offset;
 813
 814         switch (cmd) {
 815         case SNDRV_PCM_TRIGGER_RESUME:
 816                 ichdev->suspended = 0;
 817                 /* fall through */
 818         case SNDRV_PCM_TRIGGER_START:
 819         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 820                 val = ICH_IOCE | ICH_STARTBM;
 821                 ichdev->last_pos = ichdev->position;
 822                 break;
 823         case SNDRV_PCM_TRIGGER_SUSPEND:
 824                 ichdev->suspended = 1;
 825                 /* fall through */
 826         case SNDRV_PCM_TRIGGER_STOP:
 827                 val = 0;
 828                 break;
 829         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 830                 val = ICH_IOCE;
 831                 break;
 832         default:
 833                 return -EINVAL;
 834         }
 835         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 836         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 837                 /* wait until DMA stopped */
 838                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 839                 /* reset whole DMA things */
 840                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 841         }
 842         return 0;
 843 }
 844
 845 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 846 {
 847         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 848         struct ichdev *ichdev = get_ichdev(substream);
 849         unsigned long port = ichdev->reg_offset;
 850         static int fiforeg[] = {
 851                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 852         };
 853         unsigned int val, fifo;
 854
 855         val = igetdword(chip, ICHREG(ALI_DMACR));
 856         switch (cmd) {
 857         case SNDRV_PCM_TRIGGER_RESUME:
 858                 ichdev->suspended = 0;
 859                 /* fall through */
 860         case SNDRV_PCM_TRIGGER_START:
 861         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 862                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 863                         /* clear FIFO for synchronization of channels */
 864                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 865                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 866                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 867                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 868                 }
 869                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 870                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 871                 /* start DMA */
 872                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 873                 break;
 874         case SNDRV_PCM_TRIGGER_SUSPEND:
 875                 ichdev->suspended = 1;
 876                 /* fall through */
 877         case SNDRV_PCM_TRIGGER_STOP:
 878         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 879                 /* pause */
 880                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 881                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 882                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 883                         ;
 884                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 885                         break;
 886                 /* reset whole DMA things */
 887                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 888                 /* clear interrupts */
 889                 iputbyte(chip, port + ICH_REG_OFF_SR,
 890                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 891                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 892                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 893                 break;
 894         default:
 895                 return -EINVAL;
 896         }
 897         return 0;
 898 }
 899
 900 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 901                                   struct snd_pcm_hw_params *hw_params)
 902 {
 903         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 904         struct ichdev *ichdev = get_ichdev(substream);
 905         int dbl = params_rate(hw_params) > 48000;
 906         int err;
 907
 908         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 909         if (err < 0)
 910                 return err;
 911         if (ichdev->pcm_open_flag) {
 912                 snd_ac97_pcm_close(ichdev->pcm);
 913                 ichdev->pcm_open_flag = 0;
 914                 ichdev->prepared = 0;
 915         }
 916         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 917                                 params_channels(hw_params),
 918                                 ichdev->pcm->r[dbl].slots);
 919         if (err >= 0) {
 920                 ichdev->pcm_open_flag = 1;
 921                 /* Force SPDIF setting */
 922                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 923                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 924                                           params_rate(hw_params));
 925         }
 926         return err;
 927 }
 928
 929 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 930 {
 931         struct ichdev *ichdev = get_ichdev(substream);
 932
 933         if (ichdev->pcm_open_flag) {
 934                 snd_ac97_pcm_close(ichdev->pcm);
 935                 ichdev->pcm_open_flag = 0;
 936                 ichdev->prepared = 0;
 937         }
 938         return snd_pcm_lib_free_pages(substream);
 939 }
 940
 941 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 942                                        struct snd_pcm_runtime *runtime)
 943 {
 944         unsigned int cnt;
 945         int dbl = runtime->rate > 48000;
 946
 947         spin_lock_irq(&chip->reg_lock);
 948         switch (chip->device_type) {
 949         case DEVICE_ALI:
 950                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 951                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 952                 if (runtime->channels == 4 || dbl)
 953                         cnt |= ICH_ALI_SC_PCM_4;
 954                 else if (runtime->channels == 6)
 955                         cnt |= ICH_ALI_SC_PCM_6;
 956                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 957                 break;
 958         case DEVICE_SIS:
 959                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 960                 cnt &= ~ICH_SIS_PCM_246_MASK;
 961                 if (runtime->channels == 4 || dbl)
 962                         cnt |= ICH_SIS_PCM_4;
 963                 else if (runtime->channels == 6)
 964                         cnt |= ICH_SIS_PCM_6;
 965                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 966                 break;
 967         default:
 968                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 969                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 970                 if (runtime->channels == 4 || dbl)
 971                         cnt |= ICH_PCM_4;
 972                 else if (runtime->channels == 6)
 973                         cnt |= ICH_PCM_6;
 974                 else if (runtime->channels == 8)
 975                         cnt |= ICH_PCM_8;
 976                 if (chip->device_type == DEVICE_NFORCE) {
 977                         /* reset to 2ch once to keep the 6 channel data in alignment,
 978                          * to start from Front Left always
 979                          */
 980                         if (cnt & ICH_PCM_246_MASK) {
 981                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 982                                 spin_unlock_irq(&chip->reg_lock);
 983                                 msleep(50); /* grrr... */
 984                                 spin_lock_irq(&chip->reg_lock);
 985                         }
 986                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 987                         if (runtime->sample_bits > 16)
 988                                 cnt |= ICH_PCM_20BIT;
 989                 }
 990                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 991                 break;
 992         }
 993         spin_unlock_irq(&chip->reg_lock);
 994 }
 995
 996 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
 997 {
 998         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 999         struct snd_pcm_runtime *runtime = substream->runtime;
1000         struct ichdev *ichdev = get_ichdev(substream);
1001
1002         ichdev->physbuf = runtime->dma_addr;
1003         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1004         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1005         if (ichdev->ichd == ICHD_PCMOUT) {
1006                 snd_intel8x0_setup_pcm_out(chip, runtime);
1007                 if (chip->device_type == DEVICE_INTEL_ICH4)
1008                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1009         }
1010         snd_intel8x0_setup_periods(chip, ichdev);
1011         ichdev->prepared = 1;
1012         return 0;
1013 }
1014
1015 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1016 {
1017         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1018         struct ichdev *ichdev = get_ichdev(substream);
1019         size_t ptr1, ptr;
1020         int civ, timeout = 10;
1021         unsigned int position;
1022
1023         spin_lock(&chip->reg_lock);
1024         do {
1025                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1026                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1027                 position = ichdev->position;
1028                 if (ptr1 == 0) {
1029                         udelay(10);
1030                         continue;
1031                 }
1032                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1033                         continue;
1034
1035                 /* IO read operation is very expensive inside virtual machine
1036                  * as it is emulated. The probability that subsequent PICB read
1037                  * will return different result is high enough to loop till
1038                  * timeout here.
1039                  * Same CIV is strict enough condition to be sure that PICB
1040                  * is valid inside VM on emulated card. */
1041                 if (chip->inside_vm)
1042                         break;
1043                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1044                         break;
1045         } while (timeout--);
1046         ptr = ichdev->last_pos;
1047         if (ptr1 != 0) {
1048                 ptr1 <<= ichdev->pos_shift;
1049                 ptr = ichdev->fragsize1 - ptr1;
1050                 ptr += position;
1051                 if (ptr < ichdev->last_pos) {
1052                         unsigned int pos_base, last_base;
1053                         pos_base = position / ichdev->fragsize1;
1054                         last_base = ichdev->last_pos / ichdev->fragsize1;
1055                         /* another sanity check; ptr1 can go back to full
1056                          * before the base position is updated
1057                          */
1058                         if (pos_base == last_base)
1059                                 ptr = ichdev->last_pos;
1060                 }
1061         }
1062         ichdev->last_pos = ptr;
1063         spin_unlock(&chip->reg_lock);
1064         if (ptr >= ichdev->size)
1065                 return 0;
1066         return bytes_to_frames(substream->runtime, ptr);
1067 }
1068
1069 static const struct snd_pcm_hardware snd_intel8x0_stream =
1070 {
1071         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1072                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1073                                  SNDRV_PCM_INFO_MMAP_VALID |
1074                                  SNDRV_PCM_INFO_PAUSE |
1075                                  SNDRV_PCM_INFO_RESUME),
1076         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1077         .rates =                SNDRV_PCM_RATE_48000,
1078         .rate_min =             48000,
1079         .rate_max =             48000,
1080         .channels_min =         2,
1081         .channels_max =         2,
1082         .buffer_bytes_max =     128 * 1024,
1083         .period_bytes_min =     32,
1084         .period_bytes_max =     128 * 1024,
1085         .periods_min =          1,
1086         .periods_max =          1024,
1087         .fifo_size =            0,
1088 };
1089
1090 static const unsigned int channels4[] = {
1091         2, 4,
1092 };
1093
1094 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1095         .count = ARRAY_SIZE(channels4),
1096         .list = channels4,
1097         .mask = 0,
1098 };
1099
1100 static const unsigned int channels6[] = {
1101         2, 4, 6,
1102 };
1103
1104 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1105         .count = ARRAY_SIZE(channels6),
1106         .list = channels6,
1107         .mask = 0,
1108 };
1109
1110 static const unsigned int channels8[] = {
1111         2, 4, 6, 8,
1112 };
1113
1114 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1115         .count = ARRAY_SIZE(channels8),
1116         .list = channels8,
1117         .mask = 0,
1118 };
1119
1120 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1121 {
1122         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1123         struct snd_pcm_runtime *runtime = substream->runtime;
1124         int err;
1125
1126         ichdev->substream = substream;
1127         runtime->hw = snd_intel8x0_stream;
1128         runtime->hw.rates = ichdev->pcm->rates;
1129         snd_pcm_limit_hw_rates(runtime);
1130         if (chip->device_type == DEVICE_SIS) {
1131                 runtime->hw.buffer_bytes_max = 64*1024;
1132                 runtime->hw.period_bytes_max = 64*1024;
1133         }
1134         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1135                 return err;
1136         runtime->private_data = ichdev;
1137         return 0;
1138 }
1139
1140 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1141 {
1142         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1143         struct snd_pcm_runtime *runtime = substream->runtime;
1144         int err;
1145
1146         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1147         if (err < 0)
1148                 return err;
1149
1150         if (chip->multi8) {
1151                 runtime->hw.channels_max = 8;
1152                 snd_pcm_hw_constraint_list(runtime, 0,
1153                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1154                                                 &hw_constraints_channels8);
1155         } else if (chip->multi6) {
1156                 runtime->hw.channels_max = 6;
1157                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1158                                            &hw_constraints_channels6);
1159         } else if (chip->multi4) {
1160                 runtime->hw.channels_max = 4;
1161                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1162                                            &hw_constraints_channels4);
1163         }
1164         if (chip->dra) {
1165                 snd_ac97_pcm_double_rate_rules(runtime);
1166         }
1167         if (chip->smp20bit) {
1168                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1169                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1170         }
1171         return 0;
1172 }
1173
1174 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1175 {
1176         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1177
1178         chip->ichd[ICHD_PCMOUT].substream = NULL;
1179         return 0;
1180 }
1181
1182 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1183 {
1184         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1185
1186         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1187 }
1188
1189 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1190 {
1191         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1192
1193         chip->ichd[ICHD_PCMIN].substream = NULL;
1194         return 0;
1195 }
1196
1197 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1198 {
1199         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1200
1201         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1202 }
1203
1204 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1205 {
1206         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1207
1208         chip->ichd[ICHD_MIC].substream = NULL;
1209         return 0;
1210 }
1211
1212 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1213 {
1214         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1215
1216         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1217 }
1218
1219 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1220 {
1221         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1222
1223         chip->ichd[ICHD_MIC2].substream = NULL;
1224         return 0;
1225 }
1226
1227 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1228 {
1229         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1230
1231         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1232 }
1233
1234 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1235 {
1236         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1237
1238         chip->ichd[ICHD_PCM2IN].substream = NULL;
1239         return 0;
1240 }
1241
1242 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1243 {
1244         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1245         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1246
1247         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1248 }
1249
1250 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1251 {
1252         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1254
1255         chip->ichd[idx].substream = NULL;
1256         return 0;
1257 }
1258
1259 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1260 {
1261         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1262         unsigned int val;
1263
1264         spin_lock_irq(&chip->reg_lock);
1265         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1266         val |= ICH_ALI_IF_AC97SP;
1267         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1268         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1269         spin_unlock_irq(&chip->reg_lock);
1270
1271         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1272 }
1273
1274 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1275 {
1276         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1277         unsigned int val;
1278
1279         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1280         spin_lock_irq(&chip->reg_lock);
1281         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1282         val &= ~ICH_ALI_IF_AC97SP;
1283         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1284         spin_unlock_irq(&chip->reg_lock);
1285
1286         return 0;
1287 }
1288
1289 #if 0 // NYI
1290 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1291 {
1292         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1293
1294         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1295 }
1296
1297 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1298 {
1299         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1300
1301         chip->ichd[ALID_SPDIFIN].substream = NULL;
1302         return 0;
1303 }
1304
1305 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1306 {
1307         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1308
1309         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1310 }
1311
1312 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1313 {
1314         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1315
1316         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1317         return 0;
1318 }
1319 #endif
1320
1321 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1322         .open =         snd_intel8x0_playback_open,
1323         .close =        snd_intel8x0_playback_close,
1324         .ioctl =        snd_pcm_lib_ioctl,
1325         .hw_params =    snd_intel8x0_hw_params,
1326         .hw_free =      snd_intel8x0_hw_free,
1327         .prepare =      snd_intel8x0_pcm_prepare,
1328         .trigger =      snd_intel8x0_pcm_trigger,
1329         .pointer =      snd_intel8x0_pcm_pointer,
1330 };
1331
1332 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1333         .open =         snd_intel8x0_capture_open,
1334         .close =        snd_intel8x0_capture_close,
1335         .ioctl =        snd_pcm_lib_ioctl,
1336         .hw_params =    snd_intel8x0_hw_params,
1337         .hw_free =      snd_intel8x0_hw_free,
1338         .prepare =      snd_intel8x0_pcm_prepare,
1339         .trigger =      snd_intel8x0_pcm_trigger,
1340         .pointer =      snd_intel8x0_pcm_pointer,
1341 };
1342
1343 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1344         .open =         snd_intel8x0_mic_open,
1345         .close =        snd_intel8x0_mic_close,
1346         .ioctl =        snd_pcm_lib_ioctl,
1347         .hw_params =    snd_intel8x0_hw_params,
1348         .hw_free =      snd_intel8x0_hw_free,
1349         .prepare =      snd_intel8x0_pcm_prepare,
1350         .trigger =      snd_intel8x0_pcm_trigger,
1351         .pointer =      snd_intel8x0_pcm_pointer,
1352 };
1353
1354 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1355         .open =         snd_intel8x0_mic2_open,
1356         .close =        snd_intel8x0_mic2_close,
1357         .ioctl =        snd_pcm_lib_ioctl,
1358         .hw_params =    snd_intel8x0_hw_params,
1359         .hw_free =      snd_intel8x0_hw_free,
1360         .prepare =      snd_intel8x0_pcm_prepare,
1361         .trigger =      snd_intel8x0_pcm_trigger,
1362         .pointer =      snd_intel8x0_pcm_pointer,
1363 };
1364
1365 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1366         .open =         snd_intel8x0_capture2_open,
1367         .close =        snd_intel8x0_capture2_close,
1368         .ioctl =        snd_pcm_lib_ioctl,
1369         .hw_params =    snd_intel8x0_hw_params,
1370         .hw_free =      snd_intel8x0_hw_free,
1371         .prepare =      snd_intel8x0_pcm_prepare,
1372         .trigger =      snd_intel8x0_pcm_trigger,
1373         .pointer =      snd_intel8x0_pcm_pointer,
1374 };
1375
1376 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1377         .open =         snd_intel8x0_spdif_open,
1378         .close =        snd_intel8x0_spdif_close,
1379         .ioctl =        snd_pcm_lib_ioctl,
1380         .hw_params =    snd_intel8x0_hw_params,
1381         .hw_free =      snd_intel8x0_hw_free,
1382         .prepare =      snd_intel8x0_pcm_prepare,
1383         .trigger =      snd_intel8x0_pcm_trigger,
1384         .pointer =      snd_intel8x0_pcm_pointer,
1385 };
1386
1387 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1388         .open =         snd_intel8x0_playback_open,
1389         .close =        snd_intel8x0_playback_close,
1390         .ioctl =        snd_pcm_lib_ioctl,
1391         .hw_params =    snd_intel8x0_hw_params,
1392         .hw_free =      snd_intel8x0_hw_free,
1393         .prepare =      snd_intel8x0_pcm_prepare,
1394         .trigger =      snd_intel8x0_ali_trigger,
1395         .pointer =      snd_intel8x0_pcm_pointer,
1396 };
1397
1398 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1399         .open =         snd_intel8x0_capture_open,
1400         .close =        snd_intel8x0_capture_close,
1401         .ioctl =        snd_pcm_lib_ioctl,
1402         .hw_params =    snd_intel8x0_hw_params,
1403         .hw_free =      snd_intel8x0_hw_free,
1404         .prepare =      snd_intel8x0_pcm_prepare,
1405         .trigger =      snd_intel8x0_ali_trigger,
1406         .pointer =      snd_intel8x0_pcm_pointer,
1407 };
1408
1409 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1410         .open =         snd_intel8x0_mic_open,
1411         .close =        snd_intel8x0_mic_close,
1412         .ioctl =        snd_pcm_lib_ioctl,
1413         .hw_params =    snd_intel8x0_hw_params,
1414         .hw_free =      snd_intel8x0_hw_free,
1415         .prepare =      snd_intel8x0_pcm_prepare,
1416         .trigger =      snd_intel8x0_ali_trigger,
1417         .pointer =      snd_intel8x0_pcm_pointer,
1418 };
1419
1420 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1421         .open =         snd_intel8x0_ali_ac97spdifout_open,
1422         .close =        snd_intel8x0_ali_ac97spdifout_close,
1423         .ioctl =        snd_pcm_lib_ioctl,
1424         .hw_params =    snd_intel8x0_hw_params,
1425         .hw_free =      snd_intel8x0_hw_free,
1426         .prepare =      snd_intel8x0_pcm_prepare,
1427         .trigger =      snd_intel8x0_ali_trigger,
1428         .pointer =      snd_intel8x0_pcm_pointer,
1429 };
1430
1431 #if 0 // NYI
1432 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1433         .open =         snd_intel8x0_ali_spdifin_open,
1434         .close =        snd_intel8x0_ali_spdifin_close,
1435         .ioctl =        snd_pcm_lib_ioctl,
1436         .hw_params =    snd_intel8x0_hw_params,
1437         .hw_free =      snd_intel8x0_hw_free,
1438         .prepare =      snd_intel8x0_pcm_prepare,
1439         .trigger =      snd_intel8x0_pcm_trigger,
1440         .pointer =      snd_intel8x0_pcm_pointer,
1441 };
1442
1443 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1444         .open =         snd_intel8x0_ali_spdifout_open,
1445         .close =        snd_intel8x0_ali_spdifout_close,
1446         .ioctl =        snd_pcm_lib_ioctl,
1447         .hw_params =    snd_intel8x0_hw_params,
1448         .hw_free =      snd_intel8x0_hw_free,
1449         .prepare =      snd_intel8x0_pcm_prepare,
1450         .trigger =      snd_intel8x0_pcm_trigger,
1451         .pointer =      snd_intel8x0_pcm_pointer,
1452 };
1453 #endif // NYI
1454
1455 struct ich_pcm_table {
1456         char *suffix;
1457         const struct snd_pcm_ops *playback_ops;
1458         const struct snd_pcm_ops *capture_ops;
1459         size_t prealloc_size;
1460         size_t prealloc_max_size;
1461         int ac97_idx;
1462 };
1463
1464 #define intel8x0_dma_type(chip) \
1465         ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1466
1467 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1468                              struct ich_pcm_table *rec)
1469 {
1470         struct snd_pcm *pcm;
1471         int err;
1472         char name[32];
1473
1474         if (rec->suffix)
1475                 sprintf(name, "Intel ICH - %s", rec->suffix);
1476         else
1477                 strcpy(name, "Intel ICH");
1478         err = snd_pcm_new(chip->card, name, device,
1479                           rec->playback_ops ? 1 : 0,
1480                           rec->capture_ops ? 1 : 0, &pcm);
1481         if (err < 0)
1482                 return err;
1483
1484         if (rec->playback_ops)
1485                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1486         if (rec->capture_ops)
1487                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1488
1489         pcm->private_data = chip;
1490         pcm->info_flags = 0;
1491         if (rec->suffix)
1492                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1493         else
1494                 strcpy(pcm->name, chip->card->shortname);
1495         chip->pcm[device] = pcm;
1496
1497         snd_pcm_lib_preallocate_pages_for_all(pcm, intel8x0_dma_type(chip),
1498                                               snd_dma_pci_data(chip->pci),
1499                                               rec->prealloc_size, rec->prealloc_max_size);
1500
1501         if (rec->playback_ops &&
1502             rec->playback_ops->open == snd_intel8x0_playback_open) {
1503                 struct snd_pcm_chmap *chmap;
1504                 int chs = 2;
1505                 if (chip->multi8)
1506                         chs = 8;
1507                 else if (chip->multi6)
1508                         chs = 6;
1509                 else if (chip->multi4)
1510                         chs = 4;
1511                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1512                                              snd_pcm_alt_chmaps, chs, 0,
1513                                              &chmap);
1514                 if (err < 0)
1515                         return err;
1516                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1517                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1518         }
1519
1520         return 0;
1521 }
1522
1523 static struct ich_pcm_table intel_pcms[] = {
1524         {
1525                 .playback_ops = &snd_intel8x0_playback_ops,
1526                 .capture_ops = &snd_intel8x0_capture_ops,
1527                 .prealloc_size = 64 * 1024,
1528                 .prealloc_max_size = 128 * 1024,
1529         },
1530         {
1531                 .suffix = "MIC ADC",
1532                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1533                 .prealloc_size = 0,
1534                 .prealloc_max_size = 128 * 1024,
1535                 .ac97_idx = ICHD_MIC,
1536         },
1537         {
1538                 .suffix = "MIC2 ADC",
1539                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1540                 .prealloc_size = 0,
1541                 .prealloc_max_size = 128 * 1024,
1542                 .ac97_idx = ICHD_MIC2,
1543         },
1544         {
1545                 .suffix = "ADC2",
1546                 .capture_ops = &snd_intel8x0_capture2_ops,
1547                 .prealloc_size = 0,
1548                 .prealloc_max_size = 128 * 1024,
1549                 .ac97_idx = ICHD_PCM2IN,
1550         },
1551         {
1552                 .suffix = "IEC958",
1553                 .playback_ops = &snd_intel8x0_spdif_ops,
1554                 .prealloc_size = 64 * 1024,
1555                 .prealloc_max_size = 128 * 1024,
1556                 .ac97_idx = ICHD_SPBAR,
1557         },
1558 };
1559
1560 static struct ich_pcm_table nforce_pcms[] = {
1561         {
1562                 .playback_ops = &snd_intel8x0_playback_ops,
1563                 .capture_ops = &snd_intel8x0_capture_ops,
1564                 .prealloc_size = 64 * 1024,
1565                 .prealloc_max_size = 128 * 1024,
1566         },
1567         {
1568                 .suffix = "MIC ADC",
1569                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1570                 .prealloc_size = 0,
1571                 .prealloc_max_size = 128 * 1024,
1572                 .ac97_idx = NVD_MIC,
1573         },
1574         {
1575                 .suffix = "IEC958",
1576                 .playback_ops = &snd_intel8x0_spdif_ops,
1577                 .prealloc_size = 64 * 1024,
1578                 .prealloc_max_size = 128 * 1024,
1579                 .ac97_idx = NVD_SPBAR,
1580         },
1581 };
1582
1583 static struct ich_pcm_table ali_pcms[] = {
1584         {
1585                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1586                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1587                 .prealloc_size = 64 * 1024,
1588                 .prealloc_max_size = 128 * 1024,
1589         },
1590         {
1591                 .suffix = "MIC ADC",
1592                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1593                 .prealloc_size = 0,
1594                 .prealloc_max_size = 128 * 1024,
1595                 .ac97_idx = ALID_MIC,
1596         },
1597         {
1598                 .suffix = "IEC958",
1599                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1600                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1601                 .prealloc_size = 64 * 1024,
1602                 .prealloc_max_size = 128 * 1024,
1603                 .ac97_idx = ALID_AC97SPDIFOUT,
1604         },
1605 #if 0 // NYI
1606         {
1607                 .suffix = "HW IEC958",
1608                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1609                 .prealloc_size = 64 * 1024,
1610                 .prealloc_max_size = 128 * 1024,
1611         },
1612 #endif
1613 };
1614
1615 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1616 {
1617         int i, tblsize, device, err;
1618         struct ich_pcm_table *tbl, *rec;
1619
1620         switch (chip->device_type) {
1621         case DEVICE_INTEL_ICH4:
1622                 tbl = intel_pcms;
1623                 tblsize = ARRAY_SIZE(intel_pcms);
1624                 if (spdif_aclink)
1625                         tblsize--;
1626                 break;
1627         case DEVICE_NFORCE:
1628                 tbl = nforce_pcms;
1629                 tblsize = ARRAY_SIZE(nforce_pcms);
1630                 if (spdif_aclink)
1631                         tblsize--;
1632                 break;
1633         case DEVICE_ALI:
1634                 tbl = ali_pcms;
1635                 tblsize = ARRAY_SIZE(ali_pcms);
1636                 break;
1637         default:
1638                 tbl = intel_pcms;
1639                 tblsize = 2;
1640                 break;
1641         }
1642
1643         device = 0;
1644         for (i = 0; i < tblsize; i++) {
1645                 rec = tbl + i;
1646                 if (i > 0 && rec->ac97_idx) {
1647                         /* activate PCM only when associated AC'97 codec */
1648                         if (! chip->ichd[rec->ac97_idx].pcm)
1649                                 continue;
1650                 }
1651                 err = snd_intel8x0_pcm1(chip, device, rec);
1652                 if (err < 0)
1653                         return err;
1654                 device++;
1655         }
1656
1657         chip->pcm_devs = device;
1658         return 0;
1659 }
1660
1661
1662 /*
1663  *  Mixer part
1664  */
1665
1666 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1667 {
1668         struct intel8x0 *chip = bus->private_data;
1669         chip->ac97_bus = NULL;
1670 }
1671
1672 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1673 {
1674         struct intel8x0 *chip = ac97->private_data;
1675         chip->ac97[ac97->num] = NULL;
1676 }
1677
1678 static const struct ac97_pcm ac97_pcm_defs[] = {
1679         /* front PCM */
1680         {
1681                 .exclusive = 1,
1682                 .r = {  {
1683                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1684                                          (1 << AC97_SLOT_PCM_RIGHT) |
1685                                          (1 << AC97_SLOT_PCM_CENTER) |
1686                                          (1 << AC97_SLOT_PCM_SLEFT) |
1687                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1688                                          (1 << AC97_SLOT_LFE)
1689                         },
1690                         {
1691                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692                                          (1 << AC97_SLOT_PCM_RIGHT) |
1693                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1694                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1695                         }
1696                 }
1697         },
1698         /* PCM IN #1 */
1699         {
1700                 .stream = 1,
1701                 .exclusive = 1,
1702                 .r = {  {
1703                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1704                                          (1 << AC97_SLOT_PCM_RIGHT)
1705                         }
1706                 }
1707         },
1708         /* MIC IN #1 */
1709         {
1710                 .stream = 1,
1711                 .exclusive = 1,
1712                 .r = {  {
1713                                 .slots = (1 << AC97_SLOT_MIC)
1714                         }
1715                 }
1716         },
1717         /* S/PDIF PCM */
1718         {
1719                 .exclusive = 1,
1720                 .spdif = 1,
1721                 .r = {  {
1722                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1723                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1724                         }
1725                 }
1726         },
1727         /* PCM IN #2 */
1728         {
1729                 .stream = 1,
1730                 .exclusive = 1,
1731                 .r = {  {
1732                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1733                                          (1 << AC97_SLOT_PCM_RIGHT)
1734                         }
1735                 }
1736         },
1737         /* MIC IN #2 */
1738         {
1739                 .stream = 1,
1740                 .exclusive = 1,
1741                 .r = {  {
1742                                 .slots = (1 << AC97_SLOT_MIC)
1743                         }
1744                 }
1745         },
1746 };
1747
1748 static const struct ac97_quirk ac97_quirks[] = {
1749         {
1750                 .subvendor = 0x0e11,
1751                 .subdevice = 0x000e,
1752                 .name = "Compaq Deskpro EN",    /* AD1885 */
1753                 .type = AC97_TUNE_HP_ONLY
1754         },
1755         {
1756                 .subvendor = 0x0e11,
1757                 .subdevice = 0x008a,
1758                 .name = "Compaq Evo W4000",     /* AD1885 */
1759                 .type = AC97_TUNE_HP_ONLY
1760         },
1761         {
1762                 .subvendor = 0x0e11,
1763                 .subdevice = 0x00b8,
1764                 .name = "Compaq Evo D510C",
1765                 .type = AC97_TUNE_HP_ONLY
1766         },
1767         {
1768                 .subvendor = 0x0e11,
1769                 .subdevice = 0x0860,
1770                 .name = "HP/Compaq nx7010",
1771                 .type = AC97_TUNE_MUTE_LED
1772         },
1773         {
1774                 .subvendor = 0x1014,
1775                 .subdevice = 0x0534,
1776                 .name = "ThinkPad X31",
1777                 .type = AC97_TUNE_INV_EAPD
1778         },
1779         {
1780                 .subvendor = 0x1014,
1781                 .subdevice = 0x1f00,
1782                 .name = "MS-9128",
1783                 .type = AC97_TUNE_ALC_JACK
1784         },
1785         {
1786                 .subvendor = 0x1014,
1787                 .subdevice = 0x0267,
1788                 .name = "IBM NetVista A30p",    /* AD1981B */
1789                 .type = AC97_TUNE_HP_ONLY
1790         },
1791         {
1792                 .subvendor = 0x1025,
1793                 .subdevice = 0x0082,
1794                 .name = "Acer Travelmate 2310",
1795                 .type = AC97_TUNE_HP_ONLY
1796         },
1797         {
1798                 .subvendor = 0x1025,
1799                 .subdevice = 0x0083,
1800                 .name = "Acer Aspire 3003LCi",
1801                 .type = AC97_TUNE_HP_ONLY
1802         },
1803         {
1804                 .subvendor = 0x1028,
1805                 .subdevice = 0x00d8,
1806                 .name = "Dell Precision 530",   /* AD1885 */
1807                 .type = AC97_TUNE_HP_ONLY
1808         },
1809         {
1810                 .subvendor = 0x1028,
1811                 .subdevice = 0x010d,
1812                 .name = "Dell", /* which model?  AD1885 */
1813                 .type = AC97_TUNE_HP_ONLY
1814         },
1815         {
1816                 .subvendor = 0x1028,
1817                 .subdevice = 0x0126,
1818                 .name = "Dell Optiplex GX260",  /* AD1981A */
1819                 .type = AC97_TUNE_HP_ONLY
1820         },
1821         {
1822                 .subvendor = 0x1028,
1823                 .subdevice = 0x012c,
1824                 .name = "Dell Precision 650",   /* AD1981A */
1825                 .type = AC97_TUNE_HP_ONLY
1826         },
1827         {
1828                 .subvendor = 0x1028,
1829                 .subdevice = 0x012d,
1830                 .name = "Dell Precision 450",   /* AD1981B*/
1831                 .type = AC97_TUNE_HP_ONLY
1832         },
1833         {
1834                 .subvendor = 0x1028,
1835                 .subdevice = 0x0147,
1836                 .name = "Dell", /* which model?  AD1981B*/
1837                 .type = AC97_TUNE_HP_ONLY
1838         },
1839         {
1840                 .subvendor = 0x1028,
1841                 .subdevice = 0x0151,
1842                 .name = "Dell Optiplex GX270",  /* AD1981B */
1843                 .type = AC97_TUNE_HP_ONLY
1844         },
1845         {
1846                 .subvendor = 0x1028,
1847                 .subdevice = 0x014e,
1848                 .name = "Dell D800", /* STAC9750/51 */
1849                 .type = AC97_TUNE_HP_ONLY
1850         },
1851         {
1852                 .subvendor = 0x1028,
1853                 .subdevice = 0x0163,
1854                 .name = "Dell Unknown", /* STAC9750/51 */
1855                 .type = AC97_TUNE_HP_ONLY
1856         },
1857         {
1858                 .subvendor = 0x1028,
1859                 .subdevice = 0x016a,
1860                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1861                 .type = AC97_TUNE_HP_ONLY
1862         },
1863         {
1864                 .subvendor = 0x1028,
1865                 .subdevice = 0x0182,
1866                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1867                 .type = AC97_TUNE_HP_ONLY
1868         },
1869         {
1870                 .subvendor = 0x1028,
1871                 .subdevice = 0x0186,
1872                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1873                 .type = AC97_TUNE_HP_MUTE_LED
1874         },
1875         {
1876                 .subvendor = 0x1028,
1877                 .subdevice = 0x0188,
1878                 .name = "Dell Inspiron 6000",
1879                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1880         },
1881         {
1882                 .subvendor = 0x1028,
1883                 .subdevice = 0x0189,
1884                 .name = "Dell Inspiron 9300",
1885                 .type = AC97_TUNE_HP_MUTE_LED
1886         },
1887         {
1888                 .subvendor = 0x1028,
1889                 .subdevice = 0x0191,
1890                 .name = "Dell Inspiron 8600",
1891                 .type = AC97_TUNE_HP_ONLY
1892         },
1893         {
1894                 .subvendor = 0x103c,
1895                 .subdevice = 0x006d,
1896                 .name = "HP zv5000",
1897                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1898         },
1899         {       /* FIXME: which codec? */
1900                 .subvendor = 0x103c,
1901                 .subdevice = 0x00c3,
1902                 .name = "HP xw6000",
1903                 .type = AC97_TUNE_HP_ONLY
1904         },
1905         {
1906                 .subvendor = 0x103c,
1907                 .subdevice = 0x088c,
1908                 .name = "HP nc8000",
1909                 .type = AC97_TUNE_HP_MUTE_LED
1910         },
1911         {
1912                 .subvendor = 0x103c,
1913                 .subdevice = 0x0890,
1914                 .name = "HP nc6000",
1915                 .type = AC97_TUNE_MUTE_LED
1916         },
1917         {
1918                 .subvendor = 0x103c,
1919                 .subdevice = 0x129d,
1920                 .name = "HP xw8000",
1921                 .type = AC97_TUNE_HP_ONLY
1922         },
1923         {
1924                 .subvendor = 0x103c,
1925                 .subdevice = 0x0938,
1926                 .name = "HP nc4200",
1927                 .type = AC97_TUNE_HP_MUTE_LED
1928         },
1929         {
1930                 .subvendor = 0x103c,
1931                 .subdevice = 0x099c,
1932                 .name = "HP nx6110/nc6120",
1933                 .type = AC97_TUNE_HP_MUTE_LED
1934         },
1935         {
1936                 .subvendor = 0x103c,
1937                 .subdevice = 0x0944,
1938                 .name = "HP nc6220",
1939                 .type = AC97_TUNE_HP_MUTE_LED
1940         },
1941         {
1942                 .subvendor = 0x103c,
1943                 .subdevice = 0x0934,
1944                 .name = "HP nc8220",
1945                 .type = AC97_TUNE_HP_MUTE_LED
1946         },
1947         {
1948                 .subvendor = 0x103c,
1949                 .subdevice = 0x12f1,
1950                 .name = "HP xw8200",    /* AD1981B*/
1951                 .type = AC97_TUNE_HP_ONLY
1952         },
1953         {
1954                 .subvendor = 0x103c,
1955                 .subdevice = 0x12f2,
1956                 .name = "HP xw6200",
1957                 .type = AC97_TUNE_HP_ONLY
1958         },
1959         {
1960                 .subvendor = 0x103c,
1961                 .subdevice = 0x3008,
1962                 .name = "HP xw4200",    /* AD1981B*/
1963                 .type = AC97_TUNE_HP_ONLY
1964         },
1965         {
1966                 .subvendor = 0x104d,
1967                 .subdevice = 0x8144,
1968                 .name = "Sony",
1969                 .type = AC97_TUNE_INV_EAPD
1970         },
1971         {
1972                 .subvendor = 0x104d,
1973                 .subdevice = 0x8197,
1974                 .name = "Sony S1XP",
1975                 .type = AC97_TUNE_INV_EAPD
1976         },
1977         {
1978                 .subvendor = 0x104d,
1979                 .subdevice = 0x81c0,
1980                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1981                 .type = AC97_TUNE_INV_EAPD
1982         },
1983         {
1984                 .subvendor = 0x104d,
1985                 .subdevice = 0x81c5,
1986                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1987                 .type = AC97_TUNE_INV_EAPD
1988         },
1989         {
1990                 .subvendor = 0x1043,
1991                 .subdevice = 0x80f3,
1992                 .name = "ASUS ICH5/AD1985",
1993                 .type = AC97_TUNE_AD_SHARING
1994         },
1995         {
1996                 .subvendor = 0x10cf,
1997                 .subdevice = 0x11c3,
1998                 .name = "Fujitsu-Siemens E4010",
1999                 .type = AC97_TUNE_HP_ONLY
2000         },
2001         {
2002                 .subvendor = 0x10cf,
2003                 .subdevice = 0x1225,
2004                 .name = "Fujitsu-Siemens T3010",
2005                 .type = AC97_TUNE_HP_ONLY
2006         },
2007         {
2008                 .subvendor = 0x10cf,
2009                 .subdevice = 0x1253,
2010                 .name = "Fujitsu S6210",        /* STAC9750/51 */
2011                 .type = AC97_TUNE_HP_ONLY
2012         },
2013         {
2014                 .subvendor = 0x10cf,
2015                 .subdevice = 0x127d,
2016                 .name = "Fujitsu Lifebook P7010",
2017                 .type = AC97_TUNE_HP_ONLY
2018         },
2019         {
2020                 .subvendor = 0x10cf,
2021                 .subdevice = 0x127e,
2022                 .name = "Fujitsu Lifebook C1211D",
2023                 .type = AC97_TUNE_HP_ONLY
2024         },
2025         {
2026                 .subvendor = 0x10cf,
2027                 .subdevice = 0x12ec,
2028                 .name = "Fujitsu-Siemens 4010",
2029                 .type = AC97_TUNE_HP_ONLY
2030         },
2031         {
2032                 .subvendor = 0x10cf,
2033                 .subdevice = 0x12f2,
2034                 .name = "Fujitsu-Siemens Celsius H320",
2035                 .type = AC97_TUNE_SWAP_HP
2036         },
2037         {
2038                 .subvendor = 0x10f1,
2039                 .subdevice = 0x2665,
2040                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2041                 .type = AC97_TUNE_HP_ONLY
2042         },
2043         {
2044                 .subvendor = 0x10f1,
2045                 .subdevice = 0x2885,
2046                 .name = "AMD64 Mobo",   /* ALC650 */
2047                 .type = AC97_TUNE_HP_ONLY
2048         },
2049         {
2050                 .subvendor = 0x10f1,
2051                 .subdevice = 0x2895,
2052                 .name = "Tyan Thunder K8WE",
2053                 .type = AC97_TUNE_HP_ONLY
2054         },
2055         {
2056                 .subvendor = 0x10f7,
2057                 .subdevice = 0x834c,
2058                 .name = "Panasonic CF-R4",
2059                 .type = AC97_TUNE_HP_ONLY,
2060         },
2061         {
2062                 .subvendor = 0x110a,
2063                 .subdevice = 0x0056,
2064                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2065                 .type = AC97_TUNE_HP_ONLY
2066         },
2067         {
2068                 .subvendor = 0x11d4,
2069                 .subdevice = 0x5375,
2070                 .name = "ADI AD1985 (discrete)",
2071                 .type = AC97_TUNE_HP_ONLY
2072         },
2073         {
2074                 .subvendor = 0x1462,
2075                 .subdevice = 0x5470,
2076                 .name = "MSI P4 ATX 645 Ultra",
2077                 .type = AC97_TUNE_HP_ONLY
2078         },
2079         {
2080                 .subvendor = 0x161f,
2081                 .subdevice = 0x202f,
2082                 .name = "Gateway M520",
2083                 .type = AC97_TUNE_INV_EAPD
2084         },
2085         {
2086                 .subvendor = 0x161f,
2087                 .subdevice = 0x203a,
2088                 .name = "Gateway 4525GZ",               /* AD1981B */
2089                 .type = AC97_TUNE_INV_EAPD
2090         },
2091         {
2092                 .subvendor = 0x1734,
2093                 .subdevice = 0x0088,
2094                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2095                 .type = AC97_TUNE_HP_ONLY
2096         },
2097         {
2098                 .subvendor = 0x8086,
2099                 .subdevice = 0x2000,
2100                 .mask = 0xfff0,
2101                 .name = "Intel ICH5/AD1985",
2102                 .type = AC97_TUNE_AD_SHARING
2103         },
2104         {
2105                 .subvendor = 0x8086,
2106                 .subdevice = 0x4000,
2107                 .mask = 0xfff0,
2108                 .name = "Intel ICH5/AD1985",
2109                 .type = AC97_TUNE_AD_SHARING
2110         },
2111         {
2112                 .subvendor = 0x8086,
2113                 .subdevice = 0x4856,
2114                 .name = "Intel D845WN (82801BA)",
2115                 .type = AC97_TUNE_SWAP_HP
2116         },
2117         {
2118                 .subvendor = 0x8086,
2119                 .subdevice = 0x4d44,
2120                 .name = "Intel D850EMV2",       /* AD1885 */
2121                 .type = AC97_TUNE_HP_ONLY
2122         },
2123         {
2124                 .subvendor = 0x8086,
2125                 .subdevice = 0x4d56,
2126                 .name = "Intel ICH/AD1885",
2127                 .type = AC97_TUNE_HP_ONLY
2128         },
2129         {
2130                 .subvendor = 0x8086,
2131                 .subdevice = 0x6000,
2132                 .mask = 0xfff0,
2133                 .name = "Intel ICH5/AD1985",
2134                 .type = AC97_TUNE_AD_SHARING
2135         },
2136         {
2137                 .subvendor = 0x8086,
2138                 .subdevice = 0xe000,
2139                 .mask = 0xfff0,
2140                 .name = "Intel ICH5/AD1985",
2141                 .type = AC97_TUNE_AD_SHARING
2142         },
2143 #if 0 /* FIXME: this seems wrong on most boards */
2144         {
2145                 .subvendor = 0x8086,
2146                 .subdevice = 0xa000,
2147                 .mask = 0xfff0,
2148                 .name = "Intel ICH5/AD1985",
2149                 .type = AC97_TUNE_HP_ONLY
2150         },
2151 #endif
2152         { } /* terminator */
2153 };
2154
2155 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2156                               const char *quirk_override)
2157 {
2158         struct snd_ac97_bus *pbus;
2159         struct snd_ac97_template ac97;
2160         int err;
2161         unsigned int i, codecs;
2162         unsigned int glob_sta = 0;
2163         struct snd_ac97_bus_ops *ops;
2164         static struct snd_ac97_bus_ops standard_bus_ops = {
2165                 .write = snd_intel8x0_codec_write,
2166                 .read = snd_intel8x0_codec_read,
2167         };
2168         static struct snd_ac97_bus_ops ali_bus_ops = {
2169                 .write = snd_intel8x0_ali_codec_write,
2170                 .read = snd_intel8x0_ali_codec_read,
2171         };
2172
2173         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2174         if (!spdif_aclink) {
2175                 switch (chip->device_type) {
2176                 case DEVICE_NFORCE:
2177                         chip->spdif_idx = NVD_SPBAR;
2178                         break;
2179                 case DEVICE_ALI:
2180                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2181                         break;
2182                 case DEVICE_INTEL_ICH4:
2183                         chip->spdif_idx = ICHD_SPBAR;
2184                         break;
2185                 }
2186         }
2187
2188         chip->in_ac97_init = 1;
2189
2190         memset(&ac97, 0, sizeof(ac97));
2191         ac97.private_data = chip;
2192         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2193         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2194         if (chip->xbox)
2195                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2196         if (chip->device_type != DEVICE_ALI) {
2197                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2198                 ops = &standard_bus_ops;
2199                 chip->in_sdin_init = 1;
2200                 codecs = 0;
2201                 for (i = 0; i < chip->max_codecs; i++) {
2202                         if (! (glob_sta & chip->codec_bit[i]))
2203                                 continue;
2204                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2205                                 snd_intel8x0_codec_read_test(chip, codecs);
2206                                 chip->ac97_sdin[codecs] =
2207                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2208                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2209                                         chip->ac97_sdin[codecs] = 0;
2210                         } else
2211                                 chip->ac97_sdin[codecs] = i;
2212                         codecs++;
2213                 }
2214                 chip->in_sdin_init = 0;
2215                 if (! codecs)
2216                         codecs = 1;
2217         } else {
2218                 ops = &ali_bus_ops;
2219                 codecs = 1;
2220                 /* detect the secondary codec */
2221                 for (i = 0; i < 100; i++) {
2222                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2223                         if (reg & 0x40) {
2224                                 codecs = 2;
2225                                 break;
2226                         }
2227                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2228                         udelay(1);
2229                 }
2230         }
2231         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2232                 goto __err;
2233         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2234         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2235                 pbus->clock = ac97_clock;
2236         /* FIXME: my test board doesn't work well with VRA... */
2237         if (chip->device_type == DEVICE_ALI)
2238                 pbus->no_vra = 1;
2239         else
2240                 pbus->dra = 1;
2241         chip->ac97_bus = pbus;
2242         chip->ncodecs = codecs;
2243
2244         ac97.pci = chip->pci;
2245         for (i = 0; i < codecs; i++) {
2246                 ac97.num = i;
2247                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2248                         if (err != -EACCES)
2249                                 dev_err(chip->card->dev,
2250                                         "Unable to initialize codec #%d\n", i);
2251                         if (i == 0)
2252                                 goto __err;
2253                 }
2254         }
2255         /* tune up the primary codec */
2256         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2257         /* enable separate SDINs for ICH4 */
2258         if (chip->device_type == DEVICE_INTEL_ICH4)
2259                 pbus->isdin = 1;
2260         /* find the available PCM streams */
2261         i = ARRAY_SIZE(ac97_pcm_defs);
2262         if (chip->device_type != DEVICE_INTEL_ICH4)
2263                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2264         if (chip->spdif_idx < 0)
2265                 i--;            /* do not allocate S/PDIF */
2266         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2267         if (err < 0)
2268                 goto __err;
2269         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2270         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2271         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2272         if (chip->spdif_idx >= 0)
2273                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2274         if (chip->device_type == DEVICE_INTEL_ICH4) {
2275                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2276                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2277         }
2278         /* enable separate SDINs for ICH4 */
2279         if (chip->device_type == DEVICE_INTEL_ICH4) {
2280                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2281                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2282                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2283                 if (pcm) {
2284                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2285                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2286                         for (i = 1; i < 4; i++) {
2287                                 if (pcm->r[0].codec[i]) {
2288                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2289                                         break;
2290                                 }
2291                         }
2292                 } else {
2293                         tmp &= ~ICH_SE; /* steer disable */
2294                 }
2295                 iputbyte(chip, ICHREG(SDM), tmp);
2296         }
2297         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2298                 chip->multi4 = 1;
2299                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2300                         chip->multi6 = 1;
2301                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2302                                 chip->multi8 = 1;
2303                 }
2304         }
2305         if (pbus->pcms[0].r[1].rslots[0]) {
2306                 chip->dra = 1;
2307         }
2308         if (chip->device_type == DEVICE_INTEL_ICH4) {
2309                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2310                         chip->smp20bit = 1;
2311         }
2312         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2313                 /* 48kHz only */
2314                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2315         }
2316         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2317                 /* use slot 10/11 for SPDIF */
2318                 u32 val;
2319                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2320                 val |= ICH_PCM_SPDIF_1011;
2321                 iputdword(chip, ICHREG(GLOB_CNT), val);
2322                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2323         }
2324         chip->in_ac97_init = 0;
2325         return 0;
2326
2327  __err:
2328         /* clear the cold-reset bit for the next chance */
2329         if (chip->device_type != DEVICE_ALI)
2330                 iputdword(chip, ICHREG(GLOB_CNT),
2331                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2332         return err;
2333 }
2334
2335
2336 /*
2337  *
2338  */
2339
2340 static void do_ali_reset(struct intel8x0 *chip)
2341 {
2342         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2343         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2344         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2345         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2346         iputdword(chip, ICHREG(ALI_INTERFACECR),
2347                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2348         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2349         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2350 }
2351
2352 #ifdef CONFIG_SND_AC97_POWER_SAVE
2353 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2354         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2355         { } /* end */
2356 };
2357
2358 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2359 {
2360         unsigned int cnt;
2361         /* ACLink on, 2 channels */
2362
2363         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2364                 return -EIO;
2365
2366         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2367         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2368
2369         /* do cold reset - the full ac97 powerdown may leave the controller
2370          * in a warm state but actually it cannot communicate with the codec.
2371          */
2372         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2373         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2374         udelay(10);
2375         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2376         msleep(1);
2377         return 0;
2378 }
2379 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2380         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2381 #else
2382 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2383 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2384 #endif
2385
2386 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2387 {
2388         unsigned long end_time;
2389         unsigned int cnt;
2390         /* ACLink on, 2 channels */
2391         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2392         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2393         /* finish cold or do warm reset */
2394         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2395         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2396         end_time = (jiffies + (HZ / 4)) + 1;
2397         do {
2398                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2399                         return 0;
2400                 schedule_timeout_uninterruptible(1);
2401         } while (time_after_eq(end_time, jiffies));
2402         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2403                    igetdword(chip, ICHREG(GLOB_CNT)));
2404         return -EIO;
2405 }
2406
2407 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2408 {
2409         unsigned long end_time;
2410         unsigned int status, nstatus;
2411         unsigned int cnt;
2412         int err;
2413
2414         /* put logic to right state */
2415         /* first clear status bits */
2416         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2417         if (chip->device_type == DEVICE_NFORCE)
2418                 status |= ICH_NVSPINT;
2419         cnt = igetdword(chip, ICHREG(GLOB_STA));
2420         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2421
2422         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2423                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2424         else
2425                 err = snd_intel8x0_ich_chip_reset(chip);
2426         if (err < 0)
2427                 return err;
2428
2429         if (probing) {
2430                 /* wait for any codec ready status.
2431                  * Once it becomes ready it should remain ready
2432                  * as long as we do not disable the ac97 link.
2433                  */
2434                 end_time = jiffies + HZ;
2435                 do {
2436                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2437                                 chip->codec_isr_bits;
2438                         if (status)
2439                                 break;
2440                         schedule_timeout_uninterruptible(1);
2441                 } while (time_after_eq(end_time, jiffies));
2442                 if (! status) {
2443                         /* no codec is found */
2444                         dev_err(chip->card->dev,
2445                                 "codec_ready: codec is not ready [0x%x]\n",
2446                                    igetdword(chip, ICHREG(GLOB_STA)));
2447                         return -EIO;
2448                 }
2449
2450                 /* wait for other codecs ready status. */
2451                 end_time = jiffies + HZ / 4;
2452                 while (status != chip->codec_isr_bits &&
2453                        time_after_eq(end_time, jiffies)) {
2454                         schedule_timeout_uninterruptible(1);
2455                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2456                                 chip->codec_isr_bits;
2457                 }
2458
2459         } else {
2460                 /* resume phase */
2461                 int i;
2462                 status = 0;
2463                 for (i = 0; i < chip->ncodecs; i++)
2464                         if (chip->ac97[i])
2465                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2466                 /* wait until all the probed codecs are ready */
2467                 end_time = jiffies + HZ;
2468                 do {
2469                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2470                                 chip->codec_isr_bits;
2471                         if (status == nstatus)
2472                                 break;
2473                         schedule_timeout_uninterruptible(1);
2474                 } while (time_after_eq(end_time, jiffies));
2475         }
2476
2477         if (chip->device_type == DEVICE_SIS) {
2478                 /* unmute the output on SIS7012 */
2479                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2480         }
2481         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2482                 /* enable SPDIF interrupt */
2483                 unsigned int val;
2484                 pci_read_config_dword(chip->pci, 0x4c, &val);
2485                 val |= 0x1000000;
2486                 pci_write_config_dword(chip->pci, 0x4c, val);
2487         }
2488         return 0;
2489 }
2490
2491 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2492 {
2493         u32 reg;
2494         int i = 0;
2495
2496         reg = igetdword(chip, ICHREG(ALI_SCR));
2497         if ((reg & 2) == 0)     /* Cold required */
2498                 reg |= 2;
2499         else
2500                 reg |= 1;       /* Warm */
2501         reg &= ~0x80000000;     /* ACLink on */
2502         iputdword(chip, ICHREG(ALI_SCR), reg);
2503
2504         for (i = 0; i < HZ / 2; i++) {
2505                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2506                         goto __ok;
2507                 schedule_timeout_uninterruptible(1);
2508         }
2509         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2510         if (probing)
2511                 return -EIO;
2512
2513  __ok:
2514         for (i = 0; i < HZ / 2; i++) {
2515                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2516                 if (reg & 0x80) /* primary codec */
2517                         break;
2518                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2519                 schedule_timeout_uninterruptible(1);
2520         }
2521
2522         do_ali_reset(chip);
2523         return 0;
2524 }
2525
2526 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2527 {
2528         unsigned int i, timeout;
2529         int err;
2530
2531         if (chip->device_type != DEVICE_ALI) {
2532                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2533                         return err;
2534                 iagetword(chip, 0);     /* clear semaphore flag */
2535         } else {
2536                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2537                         return err;
2538         }
2539
2540         /* disable interrupts */
2541         for (i = 0; i < chip->bdbars_count; i++)
2542                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2543         /* reset channels */
2544         for (i = 0; i < chip->bdbars_count; i++)
2545                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2546         for (i = 0; i < chip->bdbars_count; i++) {
2547                 timeout = 100000;
2548                 while (--timeout != 0) {
2549                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2550                                 break;
2551                 }
2552                 if (timeout == 0)
2553                         dev_err(chip->card->dev, "reset of registers failed?\n");
2554         }
2555         /* initialize Buffer Descriptor Lists */
2556         for (i = 0; i < chip->bdbars_count; i++)
2557                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2558                           chip->ichd[i].bdbar_addr);
2559         return 0;
2560 }
2561
2562 static int snd_intel8x0_free(struct intel8x0 *chip)
2563 {
2564         unsigned int i;
2565
2566         if (chip->irq < 0)
2567                 goto __hw_end;
2568         /* disable interrupts */
2569         for (i = 0; i < chip->bdbars_count; i++)
2570                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2571         /* reset channels */
2572         for (i = 0; i < chip->bdbars_count; i++)
2573                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2574         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2575                 /* stop the spdif interrupt */
2576                 unsigned int val;
2577                 pci_read_config_dword(chip->pci, 0x4c, &val);
2578                 val &= ~0x1000000;
2579                 pci_write_config_dword(chip->pci, 0x4c, val);
2580         }
2581         /* --- */
2582
2583       __hw_end:
2584         if (chip->irq >= 0)
2585                 free_irq(chip->irq, chip);
2586         if (chip->bdbars.area)
2587                 snd_dma_free_pages(&chip->bdbars);
2588         if (chip->addr)
2589                 pci_iounmap(chip->pci, chip->addr);
2590         if (chip->bmaddr)
2591                 pci_iounmap(chip->pci, chip->bmaddr);
2592         pci_release_regions(chip->pci);
2593         pci_disable_device(chip->pci);
2594         kfree(chip);
2595         return 0;
2596 }
2597
2598 #ifdef CONFIG_PM_SLEEP
2599 /*
2600  * power management
2601  */
2602 static int intel8x0_suspend(struct device *dev)
2603 {
2604         struct snd_card *card = dev_get_drvdata(dev);
2605         struct intel8x0 *chip = card->private_data;
2606         int i;
2607
2608         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2609         for (i = 0; i < chip->ncodecs; i++)
2610                 snd_ac97_suspend(chip->ac97[i]);
2611         if (chip->device_type == DEVICE_INTEL_ICH4)
2612                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2613
2614         if (chip->irq >= 0) {
2615                 free_irq(chip->irq, chip);
2616                 chip->irq = -1;
2617         }
2618         return 0;
2619 }
2620
2621 static int intel8x0_resume(struct device *dev)
2622 {
2623         struct pci_dev *pci = to_pci_dev(dev);
2624         struct snd_card *card = dev_get_drvdata(dev);
2625         struct intel8x0 *chip = card->private_data;
2626         int i;
2627
2628         snd_intel8x0_chip_init(chip, 0);
2629         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2630                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2631                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2632                         pci->irq);
2633                 snd_card_disconnect(card);
2634                 return -EIO;
2635         }
2636         chip->irq = pci->irq;
2637         synchronize_irq(chip->irq);
2638
2639         /* re-initialize mixer stuff */
2640         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2641                 /* enable separate SDINs for ICH4 */
2642                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2643                 /* use slot 10/11 for SPDIF */
2644                 iputdword(chip, ICHREG(GLOB_CNT),
2645                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2646                           ICH_PCM_SPDIF_1011);
2647         }
2648
2649         for (i = 0; i < chip->ncodecs; i++)
2650                 snd_ac97_resume(chip->ac97[i]);
2651
2652         /* resume status */
2653         for (i = 0; i < chip->bdbars_count; i++) {
2654                 struct ichdev *ichdev = &chip->ichd[i];
2655                 unsigned long port = ichdev->reg_offset;
2656                 if (! ichdev->substream || ! ichdev->suspended)
2657                         continue;
2658                 if (ichdev->ichd == ICHD_PCMOUT)
2659                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2660                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2661                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2662                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2663                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2664         }
2665
2666         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2667         return 0;
2668 }
2669
2670 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2671 #define INTEL8X0_PM_OPS &intel8x0_pm
2672 #else
2673 #define INTEL8X0_PM_OPS NULL
2674 #endif /* CONFIG_PM_SLEEP */
2675
2676 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2677
2678 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2679 {
2680         struct snd_pcm_substream *subs;
2681         struct ichdev *ichdev;
2682         unsigned long port;
2683         unsigned long pos, pos1, t;
2684         int civ, timeout = 1000, attempt = 1;
2685         ktime_t start_time, stop_time;
2686
2687         if (chip->ac97_bus->clock != 48000)
2688                 return; /* specified in module option */
2689
2690       __again:
2691         subs = chip->pcm[0]->streams[0].substream;
2692         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2693                 dev_warn(chip->card->dev,
2694                          "no playback buffer allocated - aborting measure ac97 clock\n");
2695                 return;
2696         }
2697         ichdev = &chip->ichd[ICHD_PCMOUT];
2698         ichdev->physbuf = subs->dma_buffer.addr;
2699         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2700         ichdev->substream = NULL; /* don't process interrupts */
2701
2702         /* set rate */
2703         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2704                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2705                         chip->ac97_bus->clock);
2706                 return;
2707         }
2708         snd_intel8x0_setup_periods(chip, ichdev);
2709         port = ichdev->reg_offset;
2710         spin_lock_irq(&chip->reg_lock);
2711         chip->in_measurement = 1;
2712         /* trigger */
2713         if (chip->device_type != DEVICE_ALI)
2714                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2715         else {
2716                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2717                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2718         }
2719         start_time = ktime_get();
2720         spin_unlock_irq(&chip->reg_lock);
2721         msleep(50);
2722         spin_lock_irq(&chip->reg_lock);
2723         /* check the position */
2724         do {
2725                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2726                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2727                 if (pos1 == 0) {
2728                         udelay(10);
2729                         continue;
2730                 }
2731                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2732                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2733                         break;
2734         } while (timeout--);
2735         if (pos1 == 0) {        /* oops, this value is not reliable */
2736                 pos = 0;
2737         } else {
2738                 pos = ichdev->fragsize1;
2739                 pos -= pos1 << ichdev->pos_shift;
2740                 pos += ichdev->position;
2741         }
2742         chip->in_measurement = 0;
2743         stop_time = ktime_get();
2744         /* stop */
2745         if (chip->device_type == DEVICE_ALI) {
2746                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2747                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2748                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2749                         ;
2750         } else {
2751                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2752                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2753                         ;
2754         }
2755         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2756         spin_unlock_irq(&chip->reg_lock);
2757
2758         if (pos == 0) {
2759                 dev_err(chip->card->dev,
2760                         "measure - unreliable DMA position..\n");
2761               __retry:
2762                 if (attempt < 3) {
2763                         msleep(300);
2764                         attempt++;
2765                         goto __again;
2766                 }
2767                 goto __end;
2768         }
2769
2770         pos /= 4;
2771         t = ktime_us_delta(stop_time, start_time);
2772         dev_info(chip->card->dev,
2773                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2774         if (t == 0) {
2775                 dev_err(chip->card->dev, "?? calculation error..\n");
2776                 goto __retry;
2777         }
2778         pos *= 1000;
2779         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2780         if (pos < 40000 || pos >= 60000) {
2781                 /* abnormal value. hw problem? */
2782                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2783                 goto __retry;
2784         } else if (pos > 40500 && pos < 41500)
2785                 /* first exception - 41000Hz reference clock */
2786                 chip->ac97_bus->clock = 41000;
2787         else if (pos > 43600 && pos < 44600)
2788                 /* second exception - 44100HZ reference clock */
2789                 chip->ac97_bus->clock = 44100;
2790         else if (pos < 47500 || pos > 48500)
2791                 /* not 48000Hz, tuning the clock.. */
2792                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2793       __end:
2794         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2795         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2796 }
2797
2798 static struct snd_pci_quirk intel8x0_clock_list[] = {
2799         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2800         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2801         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2802         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2803         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2804         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2805         { }     /* terminator */
2806 };
2807
2808 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2809 {
2810         struct pci_dev *pci = chip->pci;
2811         const struct snd_pci_quirk *wl;
2812
2813         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2814         if (!wl)
2815                 return 0;
2816         dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2817                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2818         chip->ac97_bus->clock = wl->value;
2819         return 1;
2820 }
2821
2822 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2823                                    struct snd_info_buffer *buffer)
2824 {
2825         struct intel8x0 *chip = entry->private_data;
2826         unsigned int tmp;
2827
2828         snd_iprintf(buffer, "Intel8x0\n\n");
2829         if (chip->device_type == DEVICE_ALI)
2830                 return;
2831         tmp = igetdword(chip, ICHREG(GLOB_STA));
2832         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2833         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2834         if (chip->device_type == DEVICE_INTEL_ICH4)
2835                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2836         snd_iprintf(buffer, "AC'97 codecs ready    :");
2837         if (tmp & chip->codec_isr_bits) {
2838                 int i;
2839                 static const char *codecs[3] = {
2840                         "primary", "secondary", "tertiary"
2841                 };
2842                 for (i = 0; i < chip->max_codecs; i++)
2843                         if (tmp & chip->codec_bit[i])
2844                                 snd_iprintf(buffer, " %s", codecs[i]);
2845         } else
2846                 snd_iprintf(buffer, " none");
2847         snd_iprintf(buffer, "\n");
2848         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2849             chip->device_type == DEVICE_SIS)
2850                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2851                         chip->ac97_sdin[0],
2852                         chip->ac97_sdin[1],
2853                         chip->ac97_sdin[2]);
2854 }
2855
2856 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2857 {
2858         snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2859                              snd_intel8x0_proc_read);
2860 }
2861
2862 static int snd_intel8x0_dev_free(struct snd_device *device)
2863 {
2864         struct intel8x0 *chip = device->device_data;
2865         return snd_intel8x0_free(chip);
2866 }
2867
2868 struct ich_reg_info {
2869         unsigned int int_sta_mask;
2870         unsigned int offset;
2871 };
2872
2873 static unsigned int ich_codec_bits[3] = {
2874         ICH_PCR, ICH_SCR, ICH_TCR
2875 };
2876 static unsigned int sis_codec_bits[3] = {
2877         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2878 };
2879
2880 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2881 {
2882         int result  = inside_vm;
2883         char *msg   = NULL;
2884
2885         /* check module parameter first (override detection) */
2886         if (result >= 0) {
2887                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2888                 goto fini;
2889         }
2890
2891         /* check for known (emulated) devices */
2892         result = 0;
2893         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2894             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2895                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2896                 msg = "enable KVM";
2897                 result = 1;
2898         } else if (pci->subsystem_vendor == 0x1ab8) {
2899                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2900                 msg = "enable Parallels VM";
2901                 result = 1;
2902         }
2903
2904 fini:
2905         if (msg != NULL)
2906                 dev_info(&pci->dev, "%s optimization\n", msg);
2907
2908         return result;
2909 }
2910
2911 static int snd_intel8x0_create(struct snd_card *card,
2912                                struct pci_dev *pci,
2913                                unsigned long device_type,
2914                                struct intel8x0 **r_intel8x0)
2915 {
2916         struct intel8x0 *chip;
2917         int err;
2918         unsigned int i;
2919         unsigned int int_sta_masks;
2920         struct ichdev *ichdev;
2921         static struct snd_device_ops ops = {
2922                 .dev_free =     snd_intel8x0_dev_free,
2923         };
2924
2925         static unsigned int bdbars[] = {
2926                 3, /* DEVICE_INTEL */
2927                 6, /* DEVICE_INTEL_ICH4 */
2928                 3, /* DEVICE_SIS */
2929                 6, /* DEVICE_ALI */
2930                 4, /* DEVICE_NFORCE */
2931         };
2932         static struct ich_reg_info intel_regs[6] = {
2933                 { ICH_PIINT, 0 },
2934                 { ICH_POINT, 0x10 },
2935                 { ICH_MCINT, 0x20 },
2936                 { ICH_M2INT, 0x40 },
2937                 { ICH_P2INT, 0x50 },
2938                 { ICH_SPINT, 0x60 },
2939         };
2940         static struct ich_reg_info nforce_regs[4] = {
2941                 { ICH_PIINT, 0 },
2942                 { ICH_POINT, 0x10 },
2943                 { ICH_MCINT, 0x20 },
2944                 { ICH_NVSPINT, 0x70 },
2945         };
2946         static struct ich_reg_info ali_regs[6] = {
2947                 { ALI_INT_PCMIN, 0x40 },
2948                 { ALI_INT_PCMOUT, 0x50 },
2949                 { ALI_INT_MICIN, 0x60 },
2950                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2951                 { ALI_INT_SPDIFIN, 0xa0 },
2952                 { ALI_INT_SPDIFOUT, 0xb0 },
2953         };
2954         struct ich_reg_info *tbl;
2955
2956         *r_intel8x0 = NULL;
2957
2958         if ((err = pci_enable_device(pci)) < 0)
2959                 return err;
2960
2961         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2962         if (chip == NULL) {
2963                 pci_disable_device(pci);
2964                 return -ENOMEM;
2965         }
2966         spin_lock_init(&chip->reg_lock);
2967         chip->device_type = device_type;
2968         chip->card = card;
2969         chip->pci = pci;
2970         chip->irq = -1;
2971
2972         /* module parameters */
2973         chip->buggy_irq = buggy_irq;
2974         chip->buggy_semaphore = buggy_semaphore;
2975         if (xbox)
2976                 chip->xbox = 1;
2977
2978         chip->inside_vm = snd_intel8x0_inside_vm(pci);
2979
2980         /*
2981          * Intel 82443MX running a 100MHz processor system bus has a hardware
2982          * bug, which aborts PCI busmaster for audio transfer.  A workaround
2983          * is to set the pages as non-cached.  For details, see the errata in
2984          *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2985          */
2986         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2987             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2988                 chip->fix_nocache = 1; /* enable workaround */
2989
2990         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2991                 kfree(chip);
2992                 pci_disable_device(pci);
2993                 return err;
2994         }
2995
2996         if (device_type == DEVICE_ALI) {
2997                 /* ALI5455 has no ac97 region */
2998                 chip->bmaddr = pci_iomap(pci, 0, 0);
2999                 goto port_inited;
3000         }
3001
3002         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3003                 chip->addr = pci_iomap(pci, 2, 0);
3004         else
3005                 chip->addr = pci_iomap(pci, 0, 0);
3006         if (!chip->addr) {
3007                 dev_err(card->dev, "AC'97 space ioremap problem\n");
3008                 snd_intel8x0_free(chip);
3009                 return -EIO;
3010         }
3011         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3012                 chip->bmaddr = pci_iomap(pci, 3, 0);
3013         else
3014                 chip->bmaddr = pci_iomap(pci, 1, 0);
3015
3016  port_inited:
3017         if (!chip->bmaddr) {
3018                 dev_err(card->dev, "Controller space ioremap problem\n");
3019                 snd_intel8x0_free(chip);
3020                 return -EIO;
3021         }
3022         chip->bdbars_count = bdbars[device_type];
3023
3024         /* initialize offsets */
3025         switch (device_type) {
3026         case DEVICE_NFORCE:
3027                 tbl = nforce_regs;
3028                 break;
3029         case DEVICE_ALI:
3030                 tbl = ali_regs;
3031                 break;
3032         default:
3033                 tbl = intel_regs;
3034                 break;
3035         }
3036         for (i = 0; i < chip->bdbars_count; i++) {
3037                 ichdev = &chip->ichd[i];
3038                 ichdev->ichd = i;
3039                 ichdev->reg_offset = tbl[i].offset;
3040                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3041                 if (device_type == DEVICE_SIS) {
3042                         /* SiS 7012 swaps the registers */
3043                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3044                         ichdev->roff_picb = ICH_REG_OFF_SR;
3045                 } else {
3046                         ichdev->roff_sr = ICH_REG_OFF_SR;
3047                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3048                 }
3049                 if (device_type == DEVICE_ALI)
3050                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3051                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3052                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3053         }
3054
3055         /* allocate buffer descriptor lists */
3056         /* the start of each lists must be aligned to 8 bytes */
3057         if (snd_dma_alloc_pages(intel8x0_dma_type(chip), snd_dma_pci_data(pci),
3058                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3059                                 &chip->bdbars) < 0) {
3060                 snd_intel8x0_free(chip);
3061                 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3062                 return -ENOMEM;
3063         }
3064         /* tables must be aligned to 8 bytes here, but the kernel pages
3065            are much bigger, so we don't care (on i386) */
3066         int_sta_masks = 0;
3067         for (i = 0; i < chip->bdbars_count; i++) {
3068                 ichdev = &chip->ichd[i];
3069                 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3070                         (i * ICH_MAX_FRAGS * 2);
3071                 ichdev->bdbar_addr = chip->bdbars.addr +
3072                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3073                 int_sta_masks |= ichdev->int_sta_mask;
3074         }
3075         chip->int_sta_reg = device_type == DEVICE_ALI ?
3076                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3077         chip->int_sta_mask = int_sta_masks;
3078
3079         pci_set_master(pci);
3080
3081         switch(chip->device_type) {
3082         case DEVICE_INTEL_ICH4:
3083                 /* ICH4 can have three codecs */
3084                 chip->max_codecs = 3;
3085                 chip->codec_bit = ich_codec_bits;
3086                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3087                 break;
3088         case DEVICE_SIS:
3089                 /* recent SIS7012 can have three codecs */
3090                 chip->max_codecs = 3;
3091                 chip->codec_bit = sis_codec_bits;
3092                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3093                 break;
3094         default:
3095                 /* others up to two codecs */
3096                 chip->max_codecs = 2;
3097                 chip->codec_bit = ich_codec_bits;
3098                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3099                 break;
3100         }
3101         for (i = 0; i < chip->max_codecs; i++)
3102                 chip->codec_isr_bits |= chip->codec_bit[i];
3103
3104         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3105                 snd_intel8x0_free(chip);
3106                 return err;
3107         }
3108
3109         /* request irq after initializaing int_sta_mask, etc */
3110         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3111                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3112                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3113                 snd_intel8x0_free(chip);
3114                 return -EBUSY;
3115         }
3116         chip->irq = pci->irq;
3117
3118         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3119                 snd_intel8x0_free(chip);
3120                 return err;
3121         }
3122
3123         *r_intel8x0 = chip;
3124         return 0;
3125 }
3126
3127 static struct shortname_table {
3128         unsigned int id;
3129         const char *s;
3130 } shortnames[] = {
3131         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3132         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3133         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3134         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3135         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3136         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3137         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3138         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3139         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3140         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3141         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3142         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3143         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3144         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3145         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3146         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3147         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3148         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3149         { 0x003a, "NVidia MCP04" },
3150         { 0x746d, "AMD AMD8111" },
3151         { 0x7445, "AMD AMD768" },
3152         { 0x5455, "ALi M5455" },
3153         { 0, NULL },
3154 };
3155
3156 static struct snd_pci_quirk spdif_aclink_defaults[] = {
3157         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3158         { } /* end */
3159 };
3160
3161 /* look up white/black list for SPDIF over ac-link */
3162 static int check_default_spdif_aclink(struct pci_dev *pci)
3163 {
3164         const struct snd_pci_quirk *w;
3165
3166         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3167         if (w) {
3168                 if (w->value)
3169                         dev_dbg(&pci->dev,
3170                                 "Using SPDIF over AC-Link for %s\n",
3171                                     snd_pci_quirk_name(w));
3172                 else
3173                         dev_dbg(&pci->dev,
3174                                 "Using integrated SPDIF DMA for %s\n",
3175                                     snd_pci_quirk_name(w));
3176                 return w->value;
3177         }
3178         return 0;
3179 }
3180
3181 static int snd_intel8x0_probe(struct pci_dev *pci,
3182                               const struct pci_device_id *pci_id)
3183 {
3184         struct snd_card *card;
3185         struct intel8x0 *chip;
3186         int err;
3187         struct shortname_table *name;
3188
3189         err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3190         if (err < 0)
3191                 return err;
3192
3193         if (spdif_aclink < 0)
3194                 spdif_aclink = check_default_spdif_aclink(pci);
3195
3196         strcpy(card->driver, "ICH");
3197         if (!spdif_aclink) {
3198                 switch (pci_id->driver_data) {
3199                 case DEVICE_NFORCE:
3200                         strcpy(card->driver, "NFORCE");
3201                         break;
3202                 case DEVICE_INTEL_ICH4:
3203                         strcpy(card->driver, "ICH4");
3204                 }
3205         }
3206
3207         strcpy(card->shortname, "Intel ICH");
3208         for (name = shortnames; name->id; name++) {
3209                 if (pci->device == name->id) {
3210                         strcpy(card->shortname, name->s);
3211                         break;
3212                 }
3213         }
3214
3215         if (buggy_irq < 0) {
3216                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3217                  * Needs to return IRQ_HANDLED for unknown irqs.
3218                  */
3219                 if (pci_id->driver_data == DEVICE_NFORCE)
3220                         buggy_irq = 1;
3221                 else
3222                         buggy_irq = 0;
3223         }
3224
3225         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3226                                        &chip)) < 0) {
3227                 snd_card_free(card);
3228                 return err;
3229         }
3230         card->private_data = chip;
3231
3232         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3233                 snd_card_free(card);
3234                 return err;
3235         }
3236         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3237                 snd_card_free(card);
3238                 return err;
3239         }
3240
3241         snd_intel8x0_proc_init(chip);
3242
3243         snprintf(card->longname, sizeof(card->longname),
3244                  "%s with %s at irq %i", card->shortname,
3245                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3246
3247         if (ac97_clock == 0 || ac97_clock == 1) {
3248                 if (ac97_clock == 0) {
3249                         if (intel8x0_in_clock_list(chip) == 0)
3250                                 intel8x0_measure_ac97_clock(chip);
3251                 } else {
3252                         intel8x0_measure_ac97_clock(chip);
3253                 }
3254         }
3255
3256         if ((err = snd_card_register(card)) < 0) {
3257                 snd_card_free(card);
3258                 return err;
3259         }
3260         pci_set_drvdata(pci, card);
3261         return 0;
3262 }
3263
3264 static void snd_intel8x0_remove(struct pci_dev *pci)
3265 {
3266         snd_card_free(pci_get_drvdata(pci));
3267 }
3268
3269 static struct pci_driver intel8x0_driver = {
3270         .name = KBUILD_MODNAME,
3271         .id_table = snd_intel8x0_ids,
3272         .probe = snd_intel8x0_probe,
3273         .remove = snd_intel8x0_remove,
3274         .driver = {
3275                 .pm = INTEL8X0_PM_OPS,
3276         },
3277 };
3278
3279 module_pci_driver(intel8x0_driver);