sound/pci/intel8x0.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for Intel ICH (i8x0) chipsets
   4  *
   5  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/ac97_codec.h>
  24 #include <sound/info.h>
  25 #include <sound/initval.h>
  26
  27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  29 MODULE_LICENSE("GPL");
  30 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  31                 "{Intel,82901AB-ICH0},"
  32                 "{Intel,82801BA-ICH2},"
  33                 "{Intel,82801CA-ICH3},"
  34                 "{Intel,82801DB-ICH4},"
  35                 "{Intel,ICH5},"
  36                 "{Intel,ICH6},"
  37                 "{Intel,ICH7},"
  38                 "{Intel,6300ESB},"
  39                 "{Intel,ESB2},"
  40                 "{Intel,MX440},"
  41                 "{SiS,SI7012},"
  42                 "{NVidia,nForce Audio},"
  43                 "{NVidia,nForce2 Audio},"
  44                 "{NVidia,nForce3 Audio},"
  45                 "{NVidia,MCP04},"
  46                 "{NVidia,MCP501},"
  47                 "{NVidia,CK804},"
  48                 "{NVidia,CK8},"
  49                 "{NVidia,CK8S},"
  50                 "{AMD,AMD768},"
  51                 "{AMD,AMD8111},"
  52                 "{ALI,M5455}}");
  53
  54 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  55 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  56 static int ac97_clock;
  57 static char *ac97_quirk;
  58 static bool buggy_semaphore;
  59 static int buggy_irq = -1; /* auto-check */
  60 static bool xbox;
  61 static int spdif_aclink = -1;
  62 static int inside_vm = -1;
  63
  64 module_param(index, int, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  66 module_param(id, charp, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  68 module_param(ac97_clock, int, 0444);
  69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
  70 module_param(ac97_quirk, charp, 0444);
  71 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  72 module_param(buggy_semaphore, bool, 0444);
  73 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  74 module_param(buggy_irq, bint, 0444);
  75 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  76 module_param(xbox, bool, 0444);
  77 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  78 module_param(spdif_aclink, int, 0444);
  79 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  80 module_param(inside_vm, bint, 0444);
  81 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  82
  83 /* just for backward compatibility */
  84 static bool enable;
  85 module_param(enable, bool, 0444);
  86 static int joystick;
  87 module_param(joystick, int, 0444);
  88
  89 /*
  90  *  Direct registers
  91  */
  92 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  93
  94 #define ICHREG(x) ICH_REG_##x
  95
  96 #define DEFINE_REGSET(name,base) \
  97 enum { \
  98         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
  99         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 100         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 101         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 102         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 103         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 104         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 105 };
 106
 107 /* busmaster blocks */
 108 DEFINE_REGSET(OFF, 0);          /* offset */
 109 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 110 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 111 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 112
 113 /* ICH4 busmaster blocks */
 114 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 115 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 116 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 117
 118 /* values for each busmaster block */
 119
 120 /* LVI */
 121 #define ICH_REG_LVI_MASK                0x1f
 122
 123 /* SR */
 124 #define ICH_FIFOE                       0x10    /* FIFO error */
 125 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 126 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 127 #define ICH_CELV                        0x02    /* current equals last valid */
 128 #define ICH_DCH                         0x01    /* DMA controller halted */
 129
 130 /* PIV */
 131 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 132
 133 /* CR */
 134 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 135 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 136 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 137 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 138 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 139
 140
 141 /* global block */
 142 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 143 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 144 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 145 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 146 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 147 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 148 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 149 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 150 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 151 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 152 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 153 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 154 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 155 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 156 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 157 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 158 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 159 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 160 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 161 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 162 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 163 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 164 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 165 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 166 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 167 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 168 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 169 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 170 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 171 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 172 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 173 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 174 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 175 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 176 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 177 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 178 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 179 #define   ICH_RCS               0x00008000      /* read completion status */
 180 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 181 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 182 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 183 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 184 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 185 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 186 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 187 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 188 #define   ICH_POINT             0x00000040      /* playback interrupt */
 189 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 190 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 191 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 192 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 193 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 194 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 195 #define   ICH_CAS               0x01            /* codec access semaphore */
 196 #define ICH_REG_SDM             0x80
 197 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 198 #define   ICH_DI2L_SHIFT        6
 199 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 200 #define   ICH_DI1L_SHIFT        4
 201 #define   ICH_SE                0x00000008      /* steer enable */
 202 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 203
 204 #define ICH_MAX_FRAGS           32              /* max hw frags */
 205
 206
 207 /*
 208  * registers for Ali5455
 209  */
 210
 211 /* ALi 5455 busmaster blocks */
 212 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 213 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 214 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 215 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 216 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 217 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 218 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 219 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 220 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 221 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 222 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 223
 224 enum {
 225         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 226         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 227         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 228         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 229         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 230         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 231         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 232         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 233         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 234         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 235         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 236         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 237         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 238         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 239         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 240         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 241         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 242         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 243         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 244         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 245         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 246 };
 247
 248 #define ALI_CAS_SEM_BUSY        0x80000000
 249 #define ALI_CPR_ADDR_SECONDARY  0x100
 250 #define ALI_CPR_ADDR_READ       0x80
 251 #define ALI_CSPSR_CODEC_READY   0x08
 252 #define ALI_CSPSR_READ_OK       0x02
 253 #define ALI_CSPSR_WRITE_OK      0x01
 254
 255 /* interrupts for the whole chip by interrupt status register finish */
 256
 257 #define ALI_INT_MICIN2          (1<<26)
 258 #define ALI_INT_PCMIN2          (1<<25)
 259 #define ALI_INT_I2SIN           (1<<24)
 260 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 261 #define ALI_INT_SPDIFIN         (1<<22)
 262 #define ALI_INT_LFEOUT          (1<<21)
 263 #define ALI_INT_CENTEROUT       (1<<20)
 264 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 265 #define ALI_INT_MICIN           (1<<18)
 266 #define ALI_INT_PCMOUT          (1<<17)
 267 #define ALI_INT_PCMIN           (1<<16)
 268 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 269 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 270 #define ALI_INT_GPIO            (1<<1)
 271 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 272                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 273
 274 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 275 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 276 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 277 #define ICH_ALI_SC_IN_BITS      (3<<18)
 278 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 279 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 280 #define ICH_ALI_SC_PCM_4        (1<<8)
 281 #define ICH_ALI_SC_PCM_6        (2<<8)
 282 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 283
 284 #define ICH_ALI_SS_SEC_ID       (3<<5)
 285 #define ICH_ALI_SS_PRI_ID       (3<<3)
 286
 287 #define ICH_ALI_IF_AC97SP       (1<<21)
 288 #define ICH_ALI_IF_MC           (1<<20)
 289 #define ICH_ALI_IF_PI           (1<<19)
 290 #define ICH_ALI_IF_MC2          (1<<18)
 291 #define ICH_ALI_IF_PI2          (1<<17)
 292 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 293 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 294 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 295 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 296 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 297 #define ICH_ALI_IF_PO           (1<<1)
 298
 299 /*
 300  *
 301  */
 302
 303 enum {
 304         ICHD_PCMIN,
 305         ICHD_PCMOUT,
 306         ICHD_MIC,
 307         ICHD_MIC2,
 308         ICHD_PCM2IN,
 309         ICHD_SPBAR,
 310         ICHD_LAST = ICHD_SPBAR
 311 };
 312 enum {
 313         NVD_PCMIN,
 314         NVD_PCMOUT,
 315         NVD_MIC,
 316         NVD_SPBAR,
 317         NVD_LAST = NVD_SPBAR
 318 };
 319 enum {
 320         ALID_PCMIN,
 321         ALID_PCMOUT,
 322         ALID_MIC,
 323         ALID_AC97SPDIFOUT,
 324         ALID_SPDIFIN,
 325         ALID_SPDIFOUT,
 326         ALID_LAST = ALID_SPDIFOUT
 327 };
 328
 329 #define get_ichdev(substream) (substream->runtime->private_data)
 330
 331 struct ichdev {
 332         unsigned int ichd;                      /* ich device number */
 333         unsigned long reg_offset;               /* offset to bmaddr */
 334         __le32 *bdbar;                          /* CPU address (32bit) */
 335         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 336         struct snd_pcm_substream *substream;
 337         unsigned int physbuf;                   /* physical address (32bit) */
 338         unsigned int size;
 339         unsigned int fragsize;
 340         unsigned int fragsize1;
 341         unsigned int position;
 342         unsigned int pos_shift;
 343         unsigned int last_pos;
 344         int frags;
 345         int lvi;
 346         int lvi_frag;
 347         int civ;
 348         int ack;
 349         int ack_reload;
 350         unsigned int ack_bit;
 351         unsigned int roff_sr;
 352         unsigned int roff_picb;
 353         unsigned int int_sta_mask;              /* interrupt status mask */
 354         unsigned int ali_slot;                  /* ALI DMA slot */
 355         struct ac97_pcm *pcm;
 356         int pcm_open_flag;
 357         unsigned int prepared:1;
 358         unsigned int suspended: 1;
 359 };
 360
 361 struct intel8x0 {
 362         unsigned int device_type;
 363
 364         int irq;
 365
 366         void __iomem *addr;
 367         void __iomem *bmaddr;
 368
 369         struct pci_dev *pci;
 370         struct snd_card *card;
 371
 372         int pcm_devs;
 373         struct snd_pcm *pcm[6];
 374         struct ichdev ichd[6];
 375
 376         unsigned multi4: 1,
 377                  multi6: 1,
 378                  multi8 :1,
 379                  dra: 1,
 380                  smp20bit: 1;
 381         unsigned in_ac97_init: 1,
 382                  in_sdin_init: 1;
 383         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 384         unsigned fix_nocache: 1;        /* workaround for 440MX */
 385         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 386         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 387         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 388         unsigned inside_vm: 1;          /* enable VM optimization */
 389
 390         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 391         unsigned int sdm_saved; /* SDM reg value */
 392
 393         struct snd_ac97_bus *ac97_bus;
 394         struct snd_ac97 *ac97[3];
 395         unsigned int ac97_sdin[3];
 396         unsigned int max_codecs, ncodecs;
 397         const unsigned int *codec_bit;
 398         unsigned int codec_isr_bits;
 399         unsigned int codec_ready_bits;
 400
 401         spinlock_t reg_lock;
 402
 403         u32 bdbars_count;
 404         struct snd_dma_buffer bdbars;
 405         u32 int_sta_reg;                /* interrupt status register */
 406         u32 int_sta_mask;               /* interrupt status mask */
 407 };
 408
 409 static const struct pci_device_id snd_intel8x0_ids[] = {
 410         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
 411         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
 412         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
 413         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
 414         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
 415         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
 416         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
 417         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
 418         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
 419         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
 420         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
 421         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
 422         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
 423         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
 424         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
 425         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
 426         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
 427         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
 428         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
 429         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
 430         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
 431         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
 432         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
 433         { 0, }
 434 };
 435
 436 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 437
 438 /*
 439  *  Lowlevel I/O - busmaster
 440  */
 441
 442 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 443 {
 444         return ioread8(chip->bmaddr + offset);
 445 }
 446
 447 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 448 {
 449         return ioread16(chip->bmaddr + offset);
 450 }
 451
 452 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 453 {
 454         return ioread32(chip->bmaddr + offset);
 455 }
 456
 457 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 458 {
 459         iowrite8(val, chip->bmaddr + offset);
 460 }
 461
 462 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 463 {
 464         iowrite16(val, chip->bmaddr + offset);
 465 }
 466
 467 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 468 {
 469         iowrite32(val, chip->bmaddr + offset);
 470 }
 471
 472 /*
 473  *  Lowlevel I/O - AC'97 registers
 474  */
 475
 476 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 477 {
 478         return ioread16(chip->addr + offset);
 479 }
 480
 481 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 482 {
 483         iowrite16(val, chip->addr + offset);
 484 }
 485
 486 /*
 487  *  Basic I/O
 488  */
 489
 490 /*
 491  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 492  */
 493
 494 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 495 {
 496         int time;
 497
 498         if (codec > 2)
 499                 return -EIO;
 500         if (chip->in_sdin_init) {
 501                 /* we don't know the ready bit assignment at the moment */
 502                 /* so we check any */
 503                 codec = chip->codec_isr_bits;
 504         } else {
 505                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 506         }
 507
 508         /* codec ready ? */
 509         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 510                 return -EIO;
 511
 512         if (chip->buggy_semaphore)
 513                 return 0; /* just ignore ... */
 514
 515         /* Anyone holding a semaphore for 1 msec should be shot... */
 516         time = 100;
 517         do {
 518                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 519                         return 0;
 520                 udelay(10);
 521         } while (time--);
 522
 523         /* access to some forbidden (non existent) ac97 registers will not
 524          * reset the semaphore. So even if you don't get the semaphore, still
 525          * continue the access. We don't need the semaphore anyway. */
 526         dev_err(chip->card->dev,
 527                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 528                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 529         iagetword(chip, 0);     /* clear semaphore flag */
 530         /* I don't care about the semaphore */
 531         return -EBUSY;
 532 }
 533
 534 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 535                                      unsigned short reg,
 536                                      unsigned short val)
 537 {
 538         struct intel8x0 *chip = ac97->private_data;
 539
 540         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 541                 if (! chip->in_ac97_init)
 542                         dev_err(chip->card->dev,
 543                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
 544                                 ac97->num, reg);
 545         }
 546         iaputword(chip, reg + ac97->num * 0x80, val);
 547 }
 548
 549 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 550                                               unsigned short reg)
 551 {
 552         struct intel8x0 *chip = ac97->private_data;
 553         unsigned short res;
 554         unsigned int tmp;
 555
 556         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 557                 if (! chip->in_ac97_init)
 558                         dev_err(chip->card->dev,
 559                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
 560                                 ac97->num, reg);
 561                 res = 0xffff;
 562         } else {
 563                 res = iagetword(chip, reg + ac97->num * 0x80);
 564                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 565                         /* reset RCS and preserve other R/WC bits */
 566                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 567                                   ~(chip->codec_ready_bits | ICH_GSCI));
 568                         if (! chip->in_ac97_init)
 569                                 dev_err(chip->card->dev,
 570                                         "codec_read %d: read timeout for register 0x%x\n",
 571                                         ac97->num, reg);
 572                         res = 0xffff;
 573                 }
 574         }
 575         return res;
 576 }
 577
 578 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 579                                          unsigned int codec)
 580 {
 581         unsigned int tmp;
 582
 583         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 584                 iagetword(chip, codec * 0x80);
 585                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 586                         /* reset RCS and preserve other R/WC bits */
 587                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 588                                   ~(chip->codec_ready_bits | ICH_GSCI));
 589                 }
 590         }
 591 }
 592
 593 /*
 594  * access to AC97 for Ali5455
 595  */
 596 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 597 {
 598         int count = 0;
 599         for (count = 0; count < 0x7f; count++) {
 600                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 601                 if (val & mask)
 602                         return 0;
 603         }
 604         if (! chip->in_ac97_init)
 605                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
 606         return -EBUSY;
 607 }
 608
 609 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 610 {
 611         int time = 100;
 612         if (chip->buggy_semaphore)
 613                 return 0; /* just ignore ... */
 614         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 615                 udelay(1);
 616         if (! time && ! chip->in_ac97_init)
 617                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
 618         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 619 }
 620
 621 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 622 {
 623         struct intel8x0 *chip = ac97->private_data;
 624         unsigned short data = 0xffff;
 625
 626         if (snd_intel8x0_ali_codec_semaphore(chip))
 627                 goto __err;
 628         reg |= ALI_CPR_ADDR_READ;
 629         if (ac97->num)
 630                 reg |= ALI_CPR_ADDR_SECONDARY;
 631         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 632         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 633                 goto __err;
 634         data = igetword(chip, ICHREG(ALI_SPR));
 635  __err:
 636         return data;
 637 }
 638
 639 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 640                                          unsigned short val)
 641 {
 642         struct intel8x0 *chip = ac97->private_data;
 643
 644         if (snd_intel8x0_ali_codec_semaphore(chip))
 645                 return;
 646         iputword(chip, ICHREG(ALI_CPR), val);
 647         if (ac97->num)
 648                 reg |= ALI_CPR_ADDR_SECONDARY;
 649         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 650         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 651 }
 652
 653
 654 /*
 655  * DMA I/O
 656  */
 657 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 658 {
 659         int idx;
 660         __le32 *bdbar = ichdev->bdbar;
 661         unsigned long port = ichdev->reg_offset;
 662
 663         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 664         if (ichdev->size == ichdev->fragsize) {
 665                 ichdev->ack_reload = ichdev->ack = 2;
 666                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 667                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 668                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 669                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 670                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 671                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 672                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 673                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 674                 }
 675                 ichdev->frags = 2;
 676         } else {
 677                 ichdev->ack_reload = ichdev->ack = 1;
 678                 ichdev->fragsize1 = ichdev->fragsize;
 679                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 680                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 681                                                      (((idx >> 1) * ichdev->fragsize) %
 682                                                       ichdev->size));
 683                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 684                                                      ichdev->fragsize >> ichdev->pos_shift);
 685 #if 0
 686                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
 687                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 688 #endif
 689                 }
 690                 ichdev->frags = ichdev->size / ichdev->fragsize;
 691         }
 692         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 693         ichdev->civ = 0;
 694         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 695         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 696         ichdev->position = 0;
 697 #if 0
 698         dev_dbg(chip->card->dev,
 699                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 700                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
 701                ichdev->fragsize1);
 702 #endif
 703         /* clear interrupts */
 704         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 705 }
 706
 707 /*
 708  *  Interrupt handler
 709  */
 710
 711 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 712 {
 713         unsigned long port = ichdev->reg_offset;
 714         unsigned long flags;
 715         int status, civ, i, step;
 716         int ack = 0;
 717
 718         if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
 719                 return;
 720
 721         spin_lock_irqsave(&chip->reg_lock, flags);
 722         status = igetbyte(chip, port + ichdev->roff_sr);
 723         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 724         if (!(status & ICH_BCIS)) {
 725                 step = 0;
 726         } else if (civ == ichdev->civ) {
 727                 // snd_printd("civ same %d\n", civ);
 728                 step = 1;
 729                 ichdev->civ++;
 730                 ichdev->civ &= ICH_REG_LVI_MASK;
 731         } else {
 732                 step = civ - ichdev->civ;
 733                 if (step < 0)
 734                         step += ICH_REG_LVI_MASK + 1;
 735                 // if (step != 1)
 736                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 737                 ichdev->civ = civ;
 738         }
 739
 740         ichdev->position += step * ichdev->fragsize1;
 741         if (! chip->in_measurement)
 742                 ichdev->position %= ichdev->size;
 743         ichdev->lvi += step;
 744         ichdev->lvi &= ICH_REG_LVI_MASK;
 745         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 746         for (i = 0; i < step; i++) {
 747                 ichdev->lvi_frag++;
 748                 ichdev->lvi_frag %= ichdev->frags;
 749                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 750 #if 0
 751         dev_dbg(chip->card->dev,
 752                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 753                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 754                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 755                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 756 #endif
 757                 if (--ichdev->ack == 0) {
 758                         ichdev->ack = ichdev->ack_reload;
 759                         ack = 1;
 760                 }
 761         }
 762         spin_unlock_irqrestore(&chip->reg_lock, flags);
 763         if (ack && ichdev->substream) {
 764                 snd_pcm_period_elapsed(ichdev->substream);
 765         }
 766         iputbyte(chip, port + ichdev->roff_sr,
 767                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 768 }
 769
 770 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 771 {
 772         struct intel8x0 *chip = dev_id;
 773         struct ichdev *ichdev;
 774         unsigned int status;
 775         unsigned int i;
 776
 777         status = igetdword(chip, chip->int_sta_reg);
 778         if (status == 0xffffffff)       /* we are not yet resumed */
 779                 return IRQ_NONE;
 780
 781         if ((status & chip->int_sta_mask) == 0) {
 782                 if (status) {
 783                         /* ack */
 784                         iputdword(chip, chip->int_sta_reg, status);
 785                         if (! chip->buggy_irq)
 786                                 status = 0;
 787                 }
 788                 return IRQ_RETVAL(status);
 789         }
 790
 791         for (i = 0; i < chip->bdbars_count; i++) {
 792                 ichdev = &chip->ichd[i];
 793                 if (status & ichdev->int_sta_mask)
 794                         snd_intel8x0_update(chip, ichdev);
 795         }
 796
 797         /* ack them */
 798         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 799
 800         return IRQ_HANDLED;
 801 }
 802
 803 /*
 804  *  PCM part
 805  */
 806
 807 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 808 {
 809         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 810         struct ichdev *ichdev = get_ichdev(substream);
 811         unsigned char val = 0;
 812         unsigned long port = ichdev->reg_offset;
 813
 814         switch (cmd) {
 815         case SNDRV_PCM_TRIGGER_RESUME:
 816                 ichdev->suspended = 0;
 817                 fallthrough;
 818         case SNDRV_PCM_TRIGGER_START:
 819         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 820                 val = ICH_IOCE | ICH_STARTBM;
 821                 ichdev->last_pos = ichdev->position;
 822                 break;
 823         case SNDRV_PCM_TRIGGER_SUSPEND:
 824                 ichdev->suspended = 1;
 825                 fallthrough;
 826         case SNDRV_PCM_TRIGGER_STOP:
 827                 val = 0;
 828                 break;
 829         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 830                 val = ICH_IOCE;
 831                 break;
 832         default:
 833                 return -EINVAL;
 834         }
 835         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 836         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 837                 /* wait until DMA stopped */
 838                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 839                 /* reset whole DMA things */
 840                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 841         }
 842         return 0;
 843 }
 844
 845 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 846 {
 847         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 848         struct ichdev *ichdev = get_ichdev(substream);
 849         unsigned long port = ichdev->reg_offset;
 850         static const int fiforeg[] = {
 851                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 852         };
 853         unsigned int val, fifo;
 854
 855         val = igetdword(chip, ICHREG(ALI_DMACR));
 856         switch (cmd) {
 857         case SNDRV_PCM_TRIGGER_RESUME:
 858                 ichdev->suspended = 0;
 859                 fallthrough;
 860         case SNDRV_PCM_TRIGGER_START:
 861         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 862                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 863                         /* clear FIFO for synchronization of channels */
 864                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 865                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 866                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 867                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 868                 }
 869                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 870                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 871                 /* start DMA */
 872                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 873                 break;
 874         case SNDRV_PCM_TRIGGER_SUSPEND:
 875                 ichdev->suspended = 1;
 876                 fallthrough;
 877         case SNDRV_PCM_TRIGGER_STOP:
 878         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 879                 /* pause */
 880                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 881                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 882                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 883                         ;
 884                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 885                         break;
 886                 /* reset whole DMA things */
 887                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 888                 /* clear interrupts */
 889                 iputbyte(chip, port + ICH_REG_OFF_SR,
 890                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 891                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 892                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 893                 break;
 894         default:
 895                 return -EINVAL;
 896         }
 897         return 0;
 898 }
 899
 900 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 901                                   struct snd_pcm_hw_params *hw_params)
 902 {
 903         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 904         struct ichdev *ichdev = get_ichdev(substream);
 905         int dbl = params_rate(hw_params) > 48000;
 906         int err;
 907
 908         if (ichdev->pcm_open_flag) {
 909                 snd_ac97_pcm_close(ichdev->pcm);
 910                 ichdev->pcm_open_flag = 0;
 911                 ichdev->prepared = 0;
 912         }
 913         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 914                                 params_channels(hw_params),
 915                                 ichdev->pcm->r[dbl].slots);
 916         if (err >= 0) {
 917                 ichdev->pcm_open_flag = 1;
 918                 /* Force SPDIF setting */
 919                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 920                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 921                                           params_rate(hw_params));
 922         }
 923         return err;
 924 }
 925
 926 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 927 {
 928         struct ichdev *ichdev = get_ichdev(substream);
 929
 930         if (ichdev->pcm_open_flag) {
 931                 snd_ac97_pcm_close(ichdev->pcm);
 932                 ichdev->pcm_open_flag = 0;
 933                 ichdev->prepared = 0;
 934         }
 935         return 0;
 936 }
 937
 938 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 939                                        struct snd_pcm_runtime *runtime)
 940 {
 941         unsigned int cnt;
 942         int dbl = runtime->rate > 48000;
 943
 944         spin_lock_irq(&chip->reg_lock);
 945         switch (chip->device_type) {
 946         case DEVICE_ALI:
 947                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 948                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 949                 if (runtime->channels == 4 || dbl)
 950                         cnt |= ICH_ALI_SC_PCM_4;
 951                 else if (runtime->channels == 6)
 952                         cnt |= ICH_ALI_SC_PCM_6;
 953                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 954                 break;
 955         case DEVICE_SIS:
 956                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 957                 cnt &= ~ICH_SIS_PCM_246_MASK;
 958                 if (runtime->channels == 4 || dbl)
 959                         cnt |= ICH_SIS_PCM_4;
 960                 else if (runtime->channels == 6)
 961                         cnt |= ICH_SIS_PCM_6;
 962                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 963                 break;
 964         default:
 965                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 966                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 967                 if (runtime->channels == 4 || dbl)
 968                         cnt |= ICH_PCM_4;
 969                 else if (runtime->channels == 6)
 970                         cnt |= ICH_PCM_6;
 971                 else if (runtime->channels == 8)
 972                         cnt |= ICH_PCM_8;
 973                 if (chip->device_type == DEVICE_NFORCE) {
 974                         /* reset to 2ch once to keep the 6 channel data in alignment,
 975                          * to start from Front Left always
 976                          */
 977                         if (cnt & ICH_PCM_246_MASK) {
 978                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 979                                 spin_unlock_irq(&chip->reg_lock);
 980                                 msleep(50); /* grrr... */
 981                                 spin_lock_irq(&chip->reg_lock);
 982                         }
 983                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 984                         if (runtime->sample_bits > 16)
 985                                 cnt |= ICH_PCM_20BIT;
 986                 }
 987                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 988                 break;
 989         }
 990         spin_unlock_irq(&chip->reg_lock);
 991 }
 992
 993 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
 994 {
 995         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 996         struct snd_pcm_runtime *runtime = substream->runtime;
 997         struct ichdev *ichdev = get_ichdev(substream);
 998
 999         ichdev->physbuf = runtime->dma_addr;
1000         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1001         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1002         if (ichdev->ichd == ICHD_PCMOUT) {
1003                 snd_intel8x0_setup_pcm_out(chip, runtime);
1004                 if (chip->device_type == DEVICE_INTEL_ICH4)
1005                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1006         }
1007         snd_intel8x0_setup_periods(chip, ichdev);
1008         ichdev->prepared = 1;
1009         return 0;
1010 }
1011
1012 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1013 {
1014         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1015         struct ichdev *ichdev = get_ichdev(substream);
1016         size_t ptr1, ptr;
1017         int civ, timeout = 10;
1018         unsigned int position;
1019
1020         spin_lock(&chip->reg_lock);
1021         do {
1022                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1023                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1024                 position = ichdev->position;
1025                 if (ptr1 == 0) {
1026                         udelay(10);
1027                         continue;
1028                 }
1029                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1030                         continue;
1031
1032                 /* IO read operation is very expensive inside virtual machine
1033                  * as it is emulated. The probability that subsequent PICB read
1034                  * will return different result is high enough to loop till
1035                  * timeout here.
1036                  * Same CIV is strict enough condition to be sure that PICB
1037                  * is valid inside VM on emulated card. */
1038                 if (chip->inside_vm)
1039                         break;
1040                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1041                         break;
1042         } while (timeout--);
1043         ptr = ichdev->last_pos;
1044         if (ptr1 != 0) {
1045                 ptr1 <<= ichdev->pos_shift;
1046                 ptr = ichdev->fragsize1 - ptr1;
1047                 ptr += position;
1048                 if (ptr < ichdev->last_pos) {
1049                         unsigned int pos_base, last_base;
1050                         pos_base = position / ichdev->fragsize1;
1051                         last_base = ichdev->last_pos / ichdev->fragsize1;
1052                         /* another sanity check; ptr1 can go back to full
1053                          * before the base position is updated
1054                          */
1055                         if (pos_base == last_base)
1056                                 ptr = ichdev->last_pos;
1057                 }
1058         }
1059         ichdev->last_pos = ptr;
1060         spin_unlock(&chip->reg_lock);
1061         if (ptr >= ichdev->size)
1062                 return 0;
1063         return bytes_to_frames(substream->runtime, ptr);
1064 }
1065
1066 static const struct snd_pcm_hardware snd_intel8x0_stream =
1067 {
1068         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1069                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1070                                  SNDRV_PCM_INFO_MMAP_VALID |
1071                                  SNDRV_PCM_INFO_PAUSE |
1072                                  SNDRV_PCM_INFO_RESUME),
1073         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1074         .rates =                SNDRV_PCM_RATE_48000,
1075         .rate_min =             48000,
1076         .rate_max =             48000,
1077         .channels_min =         2,
1078         .channels_max =         2,
1079         .buffer_bytes_max =     128 * 1024,
1080         .period_bytes_min =     32,
1081         .period_bytes_max =     128 * 1024,
1082         .periods_min =          1,
1083         .periods_max =          1024,
1084         .fifo_size =            0,
1085 };
1086
1087 static const unsigned int channels4[] = {
1088         2, 4,
1089 };
1090
1091 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1092         .count = ARRAY_SIZE(channels4),
1093         .list = channels4,
1094         .mask = 0,
1095 };
1096
1097 static const unsigned int channels6[] = {
1098         2, 4, 6,
1099 };
1100
1101 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1102         .count = ARRAY_SIZE(channels6),
1103         .list = channels6,
1104         .mask = 0,
1105 };
1106
1107 static const unsigned int channels8[] = {
1108         2, 4, 6, 8,
1109 };
1110
1111 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1112         .count = ARRAY_SIZE(channels8),
1113         .list = channels8,
1114         .mask = 0,
1115 };
1116
1117 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1118 {
1119         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1120         struct snd_pcm_runtime *runtime = substream->runtime;
1121         int err;
1122
1123         ichdev->substream = substream;
1124         runtime->hw = snd_intel8x0_stream;
1125         runtime->hw.rates = ichdev->pcm->rates;
1126         snd_pcm_limit_hw_rates(runtime);
1127         if (chip->device_type == DEVICE_SIS) {
1128                 runtime->hw.buffer_bytes_max = 64*1024;
1129                 runtime->hw.period_bytes_max = 64*1024;
1130         }
1131         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1132                 return err;
1133         runtime->private_data = ichdev;
1134         return 0;
1135 }
1136
1137 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1138 {
1139         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1140         struct snd_pcm_runtime *runtime = substream->runtime;
1141         int err;
1142
1143         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1144         if (err < 0)
1145                 return err;
1146
1147         if (chip->multi8) {
1148                 runtime->hw.channels_max = 8;
1149                 snd_pcm_hw_constraint_list(runtime, 0,
1150                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1151                                                 &hw_constraints_channels8);
1152         } else if (chip->multi6) {
1153                 runtime->hw.channels_max = 6;
1154                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1155                                            &hw_constraints_channels6);
1156         } else if (chip->multi4) {
1157                 runtime->hw.channels_max = 4;
1158                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1159                                            &hw_constraints_channels4);
1160         }
1161         if (chip->dra) {
1162                 snd_ac97_pcm_double_rate_rules(runtime);
1163         }
1164         if (chip->smp20bit) {
1165                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1166                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1167         }
1168         return 0;
1169 }
1170
1171 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1172 {
1173         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1174
1175         chip->ichd[ICHD_PCMOUT].substream = NULL;
1176         return 0;
1177 }
1178
1179 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1180 {
1181         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1182
1183         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1184 }
1185
1186 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1187 {
1188         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189
1190         chip->ichd[ICHD_PCMIN].substream = NULL;
1191         return 0;
1192 }
1193
1194 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1195 {
1196         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197
1198         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1199 }
1200
1201 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1202 {
1203         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205         chip->ichd[ICHD_MIC].substream = NULL;
1206         return 0;
1207 }
1208
1209 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1210 {
1211         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212
1213         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1214 }
1215
1216 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1217 {
1218         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219
1220         chip->ichd[ICHD_MIC2].substream = NULL;
1221         return 0;
1222 }
1223
1224 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1225 {
1226         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227
1228         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1229 }
1230
1231 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1232 {
1233         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234
1235         chip->ichd[ICHD_PCM2IN].substream = NULL;
1236         return 0;
1237 }
1238
1239 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1240 {
1241         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1242         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1243
1244         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1245 }
1246
1247 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1248 {
1249         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1250         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1251
1252         chip->ichd[idx].substream = NULL;
1253         return 0;
1254 }
1255
1256 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1257 {
1258         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1259         unsigned int val;
1260
1261         spin_lock_irq(&chip->reg_lock);
1262         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1263         val |= ICH_ALI_IF_AC97SP;
1264         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1265         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1266         spin_unlock_irq(&chip->reg_lock);
1267
1268         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1269 }
1270
1271 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1272 {
1273         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1274         unsigned int val;
1275
1276         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1277         spin_lock_irq(&chip->reg_lock);
1278         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1279         val &= ~ICH_ALI_IF_AC97SP;
1280         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1281         spin_unlock_irq(&chip->reg_lock);
1282
1283         return 0;
1284 }
1285
1286 #if 0 // NYI
1287 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1288 {
1289         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290
1291         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1292 }
1293
1294 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1295 {
1296         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1297
1298         chip->ichd[ALID_SPDIFIN].substream = NULL;
1299         return 0;
1300 }
1301
1302 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1303 {
1304         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1305
1306         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1307 }
1308
1309 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1310 {
1311         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1312
1313         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1314         return 0;
1315 }
1316 #endif
1317
1318 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1319         .open =         snd_intel8x0_playback_open,
1320         .close =        snd_intel8x0_playback_close,
1321         .hw_params =    snd_intel8x0_hw_params,
1322         .hw_free =      snd_intel8x0_hw_free,
1323         .prepare =      snd_intel8x0_pcm_prepare,
1324         .trigger =      snd_intel8x0_pcm_trigger,
1325         .pointer =      snd_intel8x0_pcm_pointer,
1326 };
1327
1328 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1329         .open =         snd_intel8x0_capture_open,
1330         .close =        snd_intel8x0_capture_close,
1331         .hw_params =    snd_intel8x0_hw_params,
1332         .hw_free =      snd_intel8x0_hw_free,
1333         .prepare =      snd_intel8x0_pcm_prepare,
1334         .trigger =      snd_intel8x0_pcm_trigger,
1335         .pointer =      snd_intel8x0_pcm_pointer,
1336 };
1337
1338 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1339         .open =         snd_intel8x0_mic_open,
1340         .close =        snd_intel8x0_mic_close,
1341         .hw_params =    snd_intel8x0_hw_params,
1342         .hw_free =      snd_intel8x0_hw_free,
1343         .prepare =      snd_intel8x0_pcm_prepare,
1344         .trigger =      snd_intel8x0_pcm_trigger,
1345         .pointer =      snd_intel8x0_pcm_pointer,
1346 };
1347
1348 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1349         .open =         snd_intel8x0_mic2_open,
1350         .close =        snd_intel8x0_mic2_close,
1351         .hw_params =    snd_intel8x0_hw_params,
1352         .hw_free =      snd_intel8x0_hw_free,
1353         .prepare =      snd_intel8x0_pcm_prepare,
1354         .trigger =      snd_intel8x0_pcm_trigger,
1355         .pointer =      snd_intel8x0_pcm_pointer,
1356 };
1357
1358 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1359         .open =         snd_intel8x0_capture2_open,
1360         .close =        snd_intel8x0_capture2_close,
1361         .hw_params =    snd_intel8x0_hw_params,
1362         .hw_free =      snd_intel8x0_hw_free,
1363         .prepare =      snd_intel8x0_pcm_prepare,
1364         .trigger =      snd_intel8x0_pcm_trigger,
1365         .pointer =      snd_intel8x0_pcm_pointer,
1366 };
1367
1368 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1369         .open =         snd_intel8x0_spdif_open,
1370         .close =        snd_intel8x0_spdif_close,
1371         .hw_params =    snd_intel8x0_hw_params,
1372         .hw_free =      snd_intel8x0_hw_free,
1373         .prepare =      snd_intel8x0_pcm_prepare,
1374         .trigger =      snd_intel8x0_pcm_trigger,
1375         .pointer =      snd_intel8x0_pcm_pointer,
1376 };
1377
1378 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1379         .open =         snd_intel8x0_playback_open,
1380         .close =        snd_intel8x0_playback_close,
1381         .hw_params =    snd_intel8x0_hw_params,
1382         .hw_free =      snd_intel8x0_hw_free,
1383         .prepare =      snd_intel8x0_pcm_prepare,
1384         .trigger =      snd_intel8x0_ali_trigger,
1385         .pointer =      snd_intel8x0_pcm_pointer,
1386 };
1387
1388 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1389         .open =         snd_intel8x0_capture_open,
1390         .close =        snd_intel8x0_capture_close,
1391         .hw_params =    snd_intel8x0_hw_params,
1392         .hw_free =      snd_intel8x0_hw_free,
1393         .prepare =      snd_intel8x0_pcm_prepare,
1394         .trigger =      snd_intel8x0_ali_trigger,
1395         .pointer =      snd_intel8x0_pcm_pointer,
1396 };
1397
1398 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1399         .open =         snd_intel8x0_mic_open,
1400         .close =        snd_intel8x0_mic_close,
1401         .hw_params =    snd_intel8x0_hw_params,
1402         .hw_free =      snd_intel8x0_hw_free,
1403         .prepare =      snd_intel8x0_pcm_prepare,
1404         .trigger =      snd_intel8x0_ali_trigger,
1405         .pointer =      snd_intel8x0_pcm_pointer,
1406 };
1407
1408 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1409         .open =         snd_intel8x0_ali_ac97spdifout_open,
1410         .close =        snd_intel8x0_ali_ac97spdifout_close,
1411         .hw_params =    snd_intel8x0_hw_params,
1412         .hw_free =      snd_intel8x0_hw_free,
1413         .prepare =      snd_intel8x0_pcm_prepare,
1414         .trigger =      snd_intel8x0_ali_trigger,
1415         .pointer =      snd_intel8x0_pcm_pointer,
1416 };
1417
1418 #if 0 // NYI
1419 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1420         .open =         snd_intel8x0_ali_spdifin_open,
1421         .close =        snd_intel8x0_ali_spdifin_close,
1422         .hw_params =    snd_intel8x0_hw_params,
1423         .hw_free =      snd_intel8x0_hw_free,
1424         .prepare =      snd_intel8x0_pcm_prepare,
1425         .trigger =      snd_intel8x0_pcm_trigger,
1426         .pointer =      snd_intel8x0_pcm_pointer,
1427 };
1428
1429 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1430         .open =         snd_intel8x0_ali_spdifout_open,
1431         .close =        snd_intel8x0_ali_spdifout_close,
1432         .hw_params =    snd_intel8x0_hw_params,
1433         .hw_free =      snd_intel8x0_hw_free,
1434         .prepare =      snd_intel8x0_pcm_prepare,
1435         .trigger =      snd_intel8x0_pcm_trigger,
1436         .pointer =      snd_intel8x0_pcm_pointer,
1437 };
1438 #endif // NYI
1439
1440 struct ich_pcm_table {
1441         char *suffix;
1442         const struct snd_pcm_ops *playback_ops;
1443         const struct snd_pcm_ops *capture_ops;
1444         size_t prealloc_size;
1445         size_t prealloc_max_size;
1446         int ac97_idx;
1447 };
1448
1449 #define intel8x0_dma_type(chip) \
1450         ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1451
1452 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1453                              const struct ich_pcm_table *rec)
1454 {
1455         struct snd_pcm *pcm;
1456         int err;
1457         char name[32];
1458
1459         if (rec->suffix)
1460                 sprintf(name, "Intel ICH - %s", rec->suffix);
1461         else
1462                 strcpy(name, "Intel ICH");
1463         err = snd_pcm_new(chip->card, name, device,
1464                           rec->playback_ops ? 1 : 0,
1465                           rec->capture_ops ? 1 : 0, &pcm);
1466         if (err < 0)
1467                 return err;
1468
1469         if (rec->playback_ops)
1470                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1471         if (rec->capture_ops)
1472                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1473
1474         pcm->private_data = chip;
1475         pcm->info_flags = 0;
1476         if (rec->suffix)
1477                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1478         else
1479                 strcpy(pcm->name, chip->card->shortname);
1480         chip->pcm[device] = pcm;
1481
1482         snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1483                                        &chip->pci->dev,
1484                                        rec->prealloc_size, rec->prealloc_max_size);
1485
1486         if (rec->playback_ops &&
1487             rec->playback_ops->open == snd_intel8x0_playback_open) {
1488                 struct snd_pcm_chmap *chmap;
1489                 int chs = 2;
1490                 if (chip->multi8)
1491                         chs = 8;
1492                 else if (chip->multi6)
1493                         chs = 6;
1494                 else if (chip->multi4)
1495                         chs = 4;
1496                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1497                                              snd_pcm_alt_chmaps, chs, 0,
1498                                              &chmap);
1499                 if (err < 0)
1500                         return err;
1501                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1502                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1503         }
1504
1505         return 0;
1506 }
1507
1508 static const struct ich_pcm_table intel_pcms[] = {
1509         {
1510                 .playback_ops = &snd_intel8x0_playback_ops,
1511                 .capture_ops = &snd_intel8x0_capture_ops,
1512                 .prealloc_size = 64 * 1024,
1513                 .prealloc_max_size = 128 * 1024,
1514         },
1515         {
1516                 .suffix = "MIC ADC",
1517                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1518                 .prealloc_size = 0,
1519                 .prealloc_max_size = 128 * 1024,
1520                 .ac97_idx = ICHD_MIC,
1521         },
1522         {
1523                 .suffix = "MIC2 ADC",
1524                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1525                 .prealloc_size = 0,
1526                 .prealloc_max_size = 128 * 1024,
1527                 .ac97_idx = ICHD_MIC2,
1528         },
1529         {
1530                 .suffix = "ADC2",
1531                 .capture_ops = &snd_intel8x0_capture2_ops,
1532                 .prealloc_size = 0,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = ICHD_PCM2IN,
1535         },
1536         {
1537                 .suffix = "IEC958",
1538                 .playback_ops = &snd_intel8x0_spdif_ops,
1539                 .prealloc_size = 64 * 1024,
1540                 .prealloc_max_size = 128 * 1024,
1541                 .ac97_idx = ICHD_SPBAR,
1542         },
1543 };
1544
1545 static const struct ich_pcm_table nforce_pcms[] = {
1546         {
1547                 .playback_ops = &snd_intel8x0_playback_ops,
1548                 .capture_ops = &snd_intel8x0_capture_ops,
1549                 .prealloc_size = 64 * 1024,
1550                 .prealloc_max_size = 128 * 1024,
1551         },
1552         {
1553                 .suffix = "MIC ADC",
1554                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1555                 .prealloc_size = 0,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = NVD_MIC,
1558         },
1559         {
1560                 .suffix = "IEC958",
1561                 .playback_ops = &snd_intel8x0_spdif_ops,
1562                 .prealloc_size = 64 * 1024,
1563                 .prealloc_max_size = 128 * 1024,
1564                 .ac97_idx = NVD_SPBAR,
1565         },
1566 };
1567
1568 static const struct ich_pcm_table ali_pcms[] = {
1569         {
1570                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1571                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1572                 .prealloc_size = 64 * 1024,
1573                 .prealloc_max_size = 128 * 1024,
1574         },
1575         {
1576                 .suffix = "MIC ADC",
1577                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1578                 .prealloc_size = 0,
1579                 .prealloc_max_size = 128 * 1024,
1580                 .ac97_idx = ALID_MIC,
1581         },
1582         {
1583                 .suffix = "IEC958",
1584                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1585                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1586                 .prealloc_size = 64 * 1024,
1587                 .prealloc_max_size = 128 * 1024,
1588                 .ac97_idx = ALID_AC97SPDIFOUT,
1589         },
1590 #if 0 // NYI
1591         {
1592                 .suffix = "HW IEC958",
1593                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1594                 .prealloc_size = 64 * 1024,
1595                 .prealloc_max_size = 128 * 1024,
1596         },
1597 #endif
1598 };
1599
1600 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1601 {
1602         int i, tblsize, device, err;
1603         const struct ich_pcm_table *tbl, *rec;
1604
1605         switch (chip->device_type) {
1606         case DEVICE_INTEL_ICH4:
1607                 tbl = intel_pcms;
1608                 tblsize = ARRAY_SIZE(intel_pcms);
1609                 if (spdif_aclink)
1610                         tblsize--;
1611                 break;
1612         case DEVICE_NFORCE:
1613                 tbl = nforce_pcms;
1614                 tblsize = ARRAY_SIZE(nforce_pcms);
1615                 if (spdif_aclink)
1616                         tblsize--;
1617                 break;
1618         case DEVICE_ALI:
1619                 tbl = ali_pcms;
1620                 tblsize = ARRAY_SIZE(ali_pcms);
1621                 break;
1622         default:
1623                 tbl = intel_pcms;
1624                 tblsize = 2;
1625                 break;
1626         }
1627
1628         device = 0;
1629         for (i = 0; i < tblsize; i++) {
1630                 rec = tbl + i;
1631                 if (i > 0 && rec->ac97_idx) {
1632                         /* activate PCM only when associated AC'97 codec */
1633                         if (! chip->ichd[rec->ac97_idx].pcm)
1634                                 continue;
1635                 }
1636                 err = snd_intel8x0_pcm1(chip, device, rec);
1637                 if (err < 0)
1638                         return err;
1639                 device++;
1640         }
1641
1642         chip->pcm_devs = device;
1643         return 0;
1644 }
1645
1646
1647 /*
1648  *  Mixer part
1649  */
1650
1651 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1652 {
1653         struct intel8x0 *chip = bus->private_data;
1654         chip->ac97_bus = NULL;
1655 }
1656
1657 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1658 {
1659         struct intel8x0 *chip = ac97->private_data;
1660         chip->ac97[ac97->num] = NULL;
1661 }
1662
1663 static const struct ac97_pcm ac97_pcm_defs[] = {
1664         /* front PCM */
1665         {
1666                 .exclusive = 1,
1667                 .r = {  {
1668                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1669                                          (1 << AC97_SLOT_PCM_RIGHT) |
1670                                          (1 << AC97_SLOT_PCM_CENTER) |
1671                                          (1 << AC97_SLOT_PCM_SLEFT) |
1672                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1673                                          (1 << AC97_SLOT_LFE)
1674                         },
1675                         {
1676                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1677                                          (1 << AC97_SLOT_PCM_RIGHT) |
1678                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1679                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1680                         }
1681                 }
1682         },
1683         /* PCM IN #1 */
1684         {
1685                 .stream = 1,
1686                 .exclusive = 1,
1687                 .r = {  {
1688                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1689                                          (1 << AC97_SLOT_PCM_RIGHT)
1690                         }
1691                 }
1692         },
1693         /* MIC IN #1 */
1694         {
1695                 .stream = 1,
1696                 .exclusive = 1,
1697                 .r = {  {
1698                                 .slots = (1 << AC97_SLOT_MIC)
1699                         }
1700                 }
1701         },
1702         /* S/PDIF PCM */
1703         {
1704                 .exclusive = 1,
1705                 .spdif = 1,
1706                 .r = {  {
1707                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1708                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1709                         }
1710                 }
1711         },
1712         /* PCM IN #2 */
1713         {
1714                 .stream = 1,
1715                 .exclusive = 1,
1716                 .r = {  {
1717                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1718                                          (1 << AC97_SLOT_PCM_RIGHT)
1719                         }
1720                 }
1721         },
1722         /* MIC IN #2 */
1723         {
1724                 .stream = 1,
1725                 .exclusive = 1,
1726                 .r = {  {
1727                                 .slots = (1 << AC97_SLOT_MIC)
1728                         }
1729                 }
1730         },
1731 };
1732
1733 static const struct ac97_quirk ac97_quirks[] = {
1734         {
1735                 .subvendor = 0x0e11,
1736                 .subdevice = 0x000e,
1737                 .name = "Compaq Deskpro EN",    /* AD1885 */
1738                 .type = AC97_TUNE_HP_ONLY
1739         },
1740         {
1741                 .subvendor = 0x0e11,
1742                 .subdevice = 0x008a,
1743                 .name = "Compaq Evo W4000",     /* AD1885 */
1744                 .type = AC97_TUNE_HP_ONLY
1745         },
1746         {
1747                 .subvendor = 0x0e11,
1748                 .subdevice = 0x00b8,
1749                 .name = "Compaq Evo D510C",
1750                 .type = AC97_TUNE_HP_ONLY
1751         },
1752         {
1753                 .subvendor = 0x0e11,
1754                 .subdevice = 0x0860,
1755                 .name = "HP/Compaq nx7010",
1756                 .type = AC97_TUNE_MUTE_LED
1757         },
1758         {
1759                 .subvendor = 0x1014,
1760                 .subdevice = 0x0534,
1761                 .name = "ThinkPad X31",
1762                 .type = AC97_TUNE_INV_EAPD
1763         },
1764         {
1765                 .subvendor = 0x1014,
1766                 .subdevice = 0x1f00,
1767                 .name = "MS-9128",
1768                 .type = AC97_TUNE_ALC_JACK
1769         },
1770         {
1771                 .subvendor = 0x1014,
1772                 .subdevice = 0x0267,
1773                 .name = "IBM NetVista A30p",    /* AD1981B */
1774                 .type = AC97_TUNE_HP_ONLY
1775         },
1776         {
1777                 .subvendor = 0x1025,
1778                 .subdevice = 0x0082,
1779                 .name = "Acer Travelmate 2310",
1780                 .type = AC97_TUNE_HP_ONLY
1781         },
1782         {
1783                 .subvendor = 0x1025,
1784                 .subdevice = 0x0083,
1785                 .name = "Acer Aspire 3003LCi",
1786                 .type = AC97_TUNE_HP_ONLY
1787         },
1788         {
1789                 .subvendor = 0x1028,
1790                 .subdevice = 0x00d8,
1791                 .name = "Dell Precision 530",   /* AD1885 */
1792                 .type = AC97_TUNE_HP_ONLY
1793         },
1794         {
1795                 .subvendor = 0x1028,
1796                 .subdevice = 0x010d,
1797                 .name = "Dell", /* which model?  AD1885 */
1798                 .type = AC97_TUNE_HP_ONLY
1799         },
1800         {
1801                 .subvendor = 0x1028,
1802                 .subdevice = 0x0126,
1803                 .name = "Dell Optiplex GX260",  /* AD1981A */
1804                 .type = AC97_TUNE_HP_ONLY
1805         },
1806         {
1807                 .subvendor = 0x1028,
1808                 .subdevice = 0x012c,
1809                 .name = "Dell Precision 650",   /* AD1981A */
1810                 .type = AC97_TUNE_HP_ONLY
1811         },
1812         {
1813                 .subvendor = 0x1028,
1814                 .subdevice = 0x012d,
1815                 .name = "Dell Precision 450",   /* AD1981B*/
1816                 .type = AC97_TUNE_HP_ONLY
1817         },
1818         {
1819                 .subvendor = 0x1028,
1820                 .subdevice = 0x0147,
1821                 .name = "Dell", /* which model?  AD1981B*/
1822                 .type = AC97_TUNE_HP_ONLY
1823         },
1824         {
1825                 .subvendor = 0x1028,
1826                 .subdevice = 0x0151,
1827                 .name = "Dell Optiplex GX270",  /* AD1981B */
1828                 .type = AC97_TUNE_HP_ONLY
1829         },
1830         {
1831                 .subvendor = 0x1028,
1832                 .subdevice = 0x014e,
1833                 .name = "Dell D800", /* STAC9750/51 */
1834                 .type = AC97_TUNE_HP_ONLY
1835         },
1836         {
1837                 .subvendor = 0x1028,
1838                 .subdevice = 0x0163,
1839                 .name = "Dell Unknown", /* STAC9750/51 */
1840                 .type = AC97_TUNE_HP_ONLY
1841         },
1842         {
1843                 .subvendor = 0x1028,
1844                 .subdevice = 0x016a,
1845                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1846                 .type = AC97_TUNE_HP_ONLY
1847         },
1848         {
1849                 .subvendor = 0x1028,
1850                 .subdevice = 0x0182,
1851                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1852                 .type = AC97_TUNE_HP_ONLY
1853         },
1854         {
1855                 .subvendor = 0x1028,
1856                 .subdevice = 0x0186,
1857                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1858                 .type = AC97_TUNE_HP_MUTE_LED
1859         },
1860         {
1861                 .subvendor = 0x1028,
1862                 .subdevice = 0x0188,
1863                 .name = "Dell Inspiron 6000",
1864                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1865         },
1866         {
1867                 .subvendor = 0x1028,
1868                 .subdevice = 0x0189,
1869                 .name = "Dell Inspiron 9300",
1870                 .type = AC97_TUNE_HP_MUTE_LED
1871         },
1872         {
1873                 .subvendor = 0x1028,
1874                 .subdevice = 0x0191,
1875                 .name = "Dell Inspiron 8600",
1876                 .type = AC97_TUNE_HP_ONLY
1877         },
1878         {
1879                 .subvendor = 0x103c,
1880                 .subdevice = 0x006d,
1881                 .name = "HP zv5000",
1882                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1883         },
1884         {       /* FIXME: which codec? */
1885                 .subvendor = 0x103c,
1886                 .subdevice = 0x00c3,
1887                 .name = "HP xw6000",
1888                 .type = AC97_TUNE_HP_ONLY
1889         },
1890         {
1891                 .subvendor = 0x103c,
1892                 .subdevice = 0x088c,
1893                 .name = "HP nc8000",
1894                 .type = AC97_TUNE_HP_MUTE_LED
1895         },
1896         {
1897                 .subvendor = 0x103c,
1898                 .subdevice = 0x0890,
1899                 .name = "HP nc6000",
1900                 .type = AC97_TUNE_MUTE_LED
1901         },
1902         {
1903                 .subvendor = 0x103c,
1904                 .subdevice = 0x129d,
1905                 .name = "HP xw8000",
1906                 .type = AC97_TUNE_HP_ONLY
1907         },
1908         {
1909                 .subvendor = 0x103c,
1910                 .subdevice = 0x0938,
1911                 .name = "HP nc4200",
1912                 .type = AC97_TUNE_HP_MUTE_LED
1913         },
1914         {
1915                 .subvendor = 0x103c,
1916                 .subdevice = 0x099c,
1917                 .name = "HP nx6110/nc6120",
1918                 .type = AC97_TUNE_HP_MUTE_LED
1919         },
1920         {
1921                 .subvendor = 0x103c,
1922                 .subdevice = 0x0944,
1923                 .name = "HP nc6220",
1924                 .type = AC97_TUNE_HP_MUTE_LED
1925         },
1926         {
1927                 .subvendor = 0x103c,
1928                 .subdevice = 0x0934,
1929                 .name = "HP nc8220",
1930                 .type = AC97_TUNE_HP_MUTE_LED
1931         },
1932         {
1933                 .subvendor = 0x103c,
1934                 .subdevice = 0x12f1,
1935                 .name = "HP xw8200",    /* AD1981B*/
1936                 .type = AC97_TUNE_HP_ONLY
1937         },
1938         {
1939                 .subvendor = 0x103c,
1940                 .subdevice = 0x12f2,
1941                 .name = "HP xw6200",
1942                 .type = AC97_TUNE_HP_ONLY
1943         },
1944         {
1945                 .subvendor = 0x103c,
1946                 .subdevice = 0x3008,
1947                 .name = "HP xw4200",    /* AD1981B*/
1948                 .type = AC97_TUNE_HP_ONLY
1949         },
1950         {
1951                 .subvendor = 0x104d,
1952                 .subdevice = 0x8144,
1953                 .name = "Sony",
1954                 .type = AC97_TUNE_INV_EAPD
1955         },
1956         {
1957                 .subvendor = 0x104d,
1958                 .subdevice = 0x8197,
1959                 .name = "Sony S1XP",
1960                 .type = AC97_TUNE_INV_EAPD
1961         },
1962         {
1963                 .subvendor = 0x104d,
1964                 .subdevice = 0x81c0,
1965                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1966                 .type = AC97_TUNE_INV_EAPD
1967         },
1968         {
1969                 .subvendor = 0x104d,
1970                 .subdevice = 0x81c5,
1971                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1972                 .type = AC97_TUNE_INV_EAPD
1973         },
1974         {
1975                 .subvendor = 0x1043,
1976                 .subdevice = 0x80f3,
1977                 .name = "ASUS ICH5/AD1985",
1978                 .type = AC97_TUNE_AD_SHARING
1979         },
1980         {
1981                 .subvendor = 0x10cf,
1982                 .subdevice = 0x11c3,
1983                 .name = "Fujitsu-Siemens E4010",
1984                 .type = AC97_TUNE_HP_ONLY
1985         },
1986         {
1987                 .subvendor = 0x10cf,
1988                 .subdevice = 0x1225,
1989                 .name = "Fujitsu-Siemens T3010",
1990                 .type = AC97_TUNE_HP_ONLY
1991         },
1992         {
1993                 .subvendor = 0x10cf,
1994                 .subdevice = 0x1253,
1995                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1996                 .type = AC97_TUNE_HP_ONLY
1997         },
1998         {
1999                 .subvendor = 0x10cf,
2000                 .subdevice = 0x127d,
2001                 .name = "Fujitsu Lifebook P7010",
2002                 .type = AC97_TUNE_HP_ONLY
2003         },
2004         {
2005                 .subvendor = 0x10cf,
2006                 .subdevice = 0x127e,
2007                 .name = "Fujitsu Lifebook C1211D",
2008                 .type = AC97_TUNE_HP_ONLY
2009         },
2010         {
2011                 .subvendor = 0x10cf,
2012                 .subdevice = 0x12ec,
2013                 .name = "Fujitsu-Siemens 4010",
2014                 .type = AC97_TUNE_HP_ONLY
2015         },
2016         {
2017                 .subvendor = 0x10cf,
2018                 .subdevice = 0x12f2,
2019                 .name = "Fujitsu-Siemens Celsius H320",
2020                 .type = AC97_TUNE_SWAP_HP
2021         },
2022         {
2023                 .subvendor = 0x10f1,
2024                 .subdevice = 0x2665,
2025                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2026                 .type = AC97_TUNE_HP_ONLY
2027         },
2028         {
2029                 .subvendor = 0x10f1,
2030                 .subdevice = 0x2885,
2031                 .name = "AMD64 Mobo",   /* ALC650 */
2032                 .type = AC97_TUNE_HP_ONLY
2033         },
2034         {
2035                 .subvendor = 0x10f1,
2036                 .subdevice = 0x2895,
2037                 .name = "Tyan Thunder K8WE",
2038                 .type = AC97_TUNE_HP_ONLY
2039         },
2040         {
2041                 .subvendor = 0x10f7,
2042                 .subdevice = 0x834c,
2043                 .name = "Panasonic CF-R4",
2044                 .type = AC97_TUNE_HP_ONLY,
2045         },
2046         {
2047                 .subvendor = 0x110a,
2048                 .subdevice = 0x0056,
2049                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2050                 .type = AC97_TUNE_HP_ONLY
2051         },
2052         {
2053                 .subvendor = 0x11d4,
2054                 .subdevice = 0x5375,
2055                 .name = "ADI AD1985 (discrete)",
2056                 .type = AC97_TUNE_HP_ONLY
2057         },
2058         {
2059                 .subvendor = 0x1462,
2060                 .subdevice = 0x5470,
2061                 .name = "MSI P4 ATX 645 Ultra",
2062                 .type = AC97_TUNE_HP_ONLY
2063         },
2064         {
2065                 .subvendor = 0x161f,
2066                 .subdevice = 0x202f,
2067                 .name = "Gateway M520",
2068                 .type = AC97_TUNE_INV_EAPD
2069         },
2070         {
2071                 .subvendor = 0x161f,
2072                 .subdevice = 0x203a,
2073                 .name = "Gateway 4525GZ",               /* AD1981B */
2074                 .type = AC97_TUNE_INV_EAPD
2075         },
2076         {
2077                 .subvendor = 0x1734,
2078                 .subdevice = 0x0088,
2079                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2080                 .type = AC97_TUNE_HP_ONLY
2081         },
2082         {
2083                 .subvendor = 0x8086,
2084                 .subdevice = 0x2000,
2085                 .mask = 0xfff0,
2086                 .name = "Intel ICH5/AD1985",
2087                 .type = AC97_TUNE_AD_SHARING
2088         },
2089         {
2090                 .subvendor = 0x8086,
2091                 .subdevice = 0x4000,
2092                 .mask = 0xfff0,
2093                 .name = "Intel ICH5/AD1985",
2094                 .type = AC97_TUNE_AD_SHARING
2095         },
2096         {
2097                 .subvendor = 0x8086,
2098                 .subdevice = 0x4856,
2099                 .name = "Intel D845WN (82801BA)",
2100                 .type = AC97_TUNE_SWAP_HP
2101         },
2102         {
2103                 .subvendor = 0x8086,
2104                 .subdevice = 0x4d44,
2105                 .name = "Intel D850EMV2",       /* AD1885 */
2106                 .type = AC97_TUNE_HP_ONLY
2107         },
2108         {
2109                 .subvendor = 0x8086,
2110                 .subdevice = 0x4d56,
2111                 .name = "Intel ICH/AD1885",
2112                 .type = AC97_TUNE_HP_ONLY
2113         },
2114         {
2115                 .subvendor = 0x8086,
2116                 .subdevice = 0x6000,
2117                 .mask = 0xfff0,
2118                 .name = "Intel ICH5/AD1985",
2119                 .type = AC97_TUNE_AD_SHARING
2120         },
2121         {
2122                 .subvendor = 0x8086,
2123                 .subdevice = 0xe000,
2124                 .mask = 0xfff0,
2125                 .name = "Intel ICH5/AD1985",
2126                 .type = AC97_TUNE_AD_SHARING
2127         },
2128 #if 0 /* FIXME: this seems wrong on most boards */
2129         {
2130                 .subvendor = 0x8086,
2131                 .subdevice = 0xa000,
2132                 .mask = 0xfff0,
2133                 .name = "Intel ICH5/AD1985",
2134                 .type = AC97_TUNE_HP_ONLY
2135         },
2136 #endif
2137         { } /* terminator */
2138 };
2139
2140 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2141                               const char *quirk_override)
2142 {
2143         struct snd_ac97_bus *pbus;
2144         struct snd_ac97_template ac97;
2145         int err;
2146         unsigned int i, codecs;
2147         unsigned int glob_sta = 0;
2148         const struct snd_ac97_bus_ops *ops;
2149         static const struct snd_ac97_bus_ops standard_bus_ops = {
2150                 .write = snd_intel8x0_codec_write,
2151                 .read = snd_intel8x0_codec_read,
2152         };
2153         static const struct snd_ac97_bus_ops ali_bus_ops = {
2154                 .write = snd_intel8x0_ali_codec_write,
2155                 .read = snd_intel8x0_ali_codec_read,
2156         };
2157
2158         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2159         if (!spdif_aclink) {
2160                 switch (chip->device_type) {
2161                 case DEVICE_NFORCE:
2162                         chip->spdif_idx = NVD_SPBAR;
2163                         break;
2164                 case DEVICE_ALI:
2165                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2166                         break;
2167                 case DEVICE_INTEL_ICH4:
2168                         chip->spdif_idx = ICHD_SPBAR;
2169                         break;
2170                 }
2171         }
2172
2173         chip->in_ac97_init = 1;
2174
2175         memset(&ac97, 0, sizeof(ac97));
2176         ac97.private_data = chip;
2177         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2178         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2179         if (chip->xbox)
2180                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2181         if (chip->device_type != DEVICE_ALI) {
2182                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2183                 ops = &standard_bus_ops;
2184                 chip->in_sdin_init = 1;
2185                 codecs = 0;
2186                 for (i = 0; i < chip->max_codecs; i++) {
2187                         if (! (glob_sta & chip->codec_bit[i]))
2188                                 continue;
2189                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2190                                 snd_intel8x0_codec_read_test(chip, codecs);
2191                                 chip->ac97_sdin[codecs] =
2192                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2193                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2194                                         chip->ac97_sdin[codecs] = 0;
2195                         } else
2196                                 chip->ac97_sdin[codecs] = i;
2197                         codecs++;
2198                 }
2199                 chip->in_sdin_init = 0;
2200                 if (! codecs)
2201                         codecs = 1;
2202         } else {
2203                 ops = &ali_bus_ops;
2204                 codecs = 1;
2205                 /* detect the secondary codec */
2206                 for (i = 0; i < 100; i++) {
2207                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2208                         if (reg & 0x40) {
2209                                 codecs = 2;
2210                                 break;
2211                         }
2212                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2213                         udelay(1);
2214                 }
2215         }
2216         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2217                 goto __err;
2218         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2219         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2220                 pbus->clock = ac97_clock;
2221         /* FIXME: my test board doesn't work well with VRA... */
2222         if (chip->device_type == DEVICE_ALI)
2223                 pbus->no_vra = 1;
2224         else
2225                 pbus->dra = 1;
2226         chip->ac97_bus = pbus;
2227         chip->ncodecs = codecs;
2228
2229         ac97.pci = chip->pci;
2230         for (i = 0; i < codecs; i++) {
2231                 ac97.num = i;
2232                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2233                         if (err != -EACCES)
2234                                 dev_err(chip->card->dev,
2235                                         "Unable to initialize codec #%d\n", i);
2236                         if (i == 0)
2237                                 goto __err;
2238                 }
2239         }
2240         /* tune up the primary codec */
2241         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2242         /* enable separate SDINs for ICH4 */
2243         if (chip->device_type == DEVICE_INTEL_ICH4)
2244                 pbus->isdin = 1;
2245         /* find the available PCM streams */
2246         i = ARRAY_SIZE(ac97_pcm_defs);
2247         if (chip->device_type != DEVICE_INTEL_ICH4)
2248                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2249         if (chip->spdif_idx < 0)
2250                 i--;            /* do not allocate S/PDIF */
2251         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2252         if (err < 0)
2253                 goto __err;
2254         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2255         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2256         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2257         if (chip->spdif_idx >= 0)
2258                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2259         if (chip->device_type == DEVICE_INTEL_ICH4) {
2260                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2261                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2262         }
2263         /* enable separate SDINs for ICH4 */
2264         if (chip->device_type == DEVICE_INTEL_ICH4) {
2265                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2266                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2267                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2268                 if (pcm) {
2269                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2270                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2271                         for (i = 1; i < 4; i++) {
2272                                 if (pcm->r[0].codec[i]) {
2273                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2274                                         break;
2275                                 }
2276                         }
2277                 } else {
2278                         tmp &= ~ICH_SE; /* steer disable */
2279                 }
2280                 iputbyte(chip, ICHREG(SDM), tmp);
2281         }
2282         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2283                 chip->multi4 = 1;
2284                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2285                         chip->multi6 = 1;
2286                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2287                                 chip->multi8 = 1;
2288                 }
2289         }
2290         if (pbus->pcms[0].r[1].rslots[0]) {
2291                 chip->dra = 1;
2292         }
2293         if (chip->device_type == DEVICE_INTEL_ICH4) {
2294                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2295                         chip->smp20bit = 1;
2296         }
2297         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2298                 /* 48kHz only */
2299                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2300         }
2301         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2302                 /* use slot 10/11 for SPDIF */
2303                 u32 val;
2304                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2305                 val |= ICH_PCM_SPDIF_1011;
2306                 iputdword(chip, ICHREG(GLOB_CNT), val);
2307                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2308         }
2309         chip->in_ac97_init = 0;
2310         return 0;
2311
2312  __err:
2313         /* clear the cold-reset bit for the next chance */
2314         if (chip->device_type != DEVICE_ALI)
2315                 iputdword(chip, ICHREG(GLOB_CNT),
2316                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2317         return err;
2318 }
2319
2320
2321 /*
2322  *
2323  */
2324
2325 static void do_ali_reset(struct intel8x0 *chip)
2326 {
2327         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2328         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2329         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2330         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2331         iputdword(chip, ICHREG(ALI_INTERFACECR),
2332                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2333         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2334         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2335 }
2336
2337 #ifdef CONFIG_SND_AC97_POWER_SAVE
2338 static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2339         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2340         { } /* end */
2341 };
2342
2343 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2344 {
2345         unsigned int cnt;
2346         /* ACLink on, 2 channels */
2347
2348         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2349                 return -EIO;
2350
2351         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2352         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2353
2354         /* do cold reset - the full ac97 powerdown may leave the controller
2355          * in a warm state but actually it cannot communicate with the codec.
2356          */
2357         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2358         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2359         udelay(10);
2360         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2361         msleep(1);
2362         return 0;
2363 }
2364 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2365         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2366 #else
2367 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2368 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2369 #endif
2370
2371 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2372 {
2373         unsigned long end_time;
2374         unsigned int cnt;
2375         /* ACLink on, 2 channels */
2376         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2377         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2378         /* finish cold or do warm reset */
2379         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2380         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2381         end_time = (jiffies + (HZ / 4)) + 1;
2382         do {
2383                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2384                         return 0;
2385                 schedule_timeout_uninterruptible(1);
2386         } while (time_after_eq(end_time, jiffies));
2387         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2388                    igetdword(chip, ICHREG(GLOB_CNT)));
2389         return -EIO;
2390 }
2391
2392 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2393 {
2394         unsigned long end_time;
2395         unsigned int status, nstatus;
2396         unsigned int cnt;
2397         int err;
2398
2399         /* put logic to right state */
2400         /* first clear status bits */
2401         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2402         if (chip->device_type == DEVICE_NFORCE)
2403                 status |= ICH_NVSPINT;
2404         cnt = igetdword(chip, ICHREG(GLOB_STA));
2405         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2406
2407         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2408                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2409         else
2410                 err = snd_intel8x0_ich_chip_reset(chip);
2411         if (err < 0)
2412                 return err;
2413
2414         if (probing) {
2415                 /* wait for any codec ready status.
2416                  * Once it becomes ready it should remain ready
2417                  * as long as we do not disable the ac97 link.
2418                  */
2419                 end_time = jiffies + HZ;
2420                 do {
2421                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2422                                 chip->codec_isr_bits;
2423                         if (status)
2424                                 break;
2425                         schedule_timeout_uninterruptible(1);
2426                 } while (time_after_eq(end_time, jiffies));
2427                 if (! status) {
2428                         /* no codec is found */
2429                         dev_err(chip->card->dev,
2430                                 "codec_ready: codec is not ready [0x%x]\n",
2431                                    igetdword(chip, ICHREG(GLOB_STA)));
2432                         return -EIO;
2433                 }
2434
2435                 /* wait for other codecs ready status. */
2436                 end_time = jiffies + HZ / 4;
2437                 while (status != chip->codec_isr_bits &&
2438                        time_after_eq(end_time, jiffies)) {
2439                         schedule_timeout_uninterruptible(1);
2440                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2441                                 chip->codec_isr_bits;
2442                 }
2443
2444         } else {
2445                 /* resume phase */
2446                 int i;
2447                 status = 0;
2448                 for (i = 0; i < chip->ncodecs; i++)
2449                         if (chip->ac97[i])
2450                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2451                 /* wait until all the probed codecs are ready */
2452                 end_time = jiffies + HZ;
2453                 do {
2454                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2455                                 chip->codec_isr_bits;
2456                         if (status == nstatus)
2457                                 break;
2458                         schedule_timeout_uninterruptible(1);
2459                 } while (time_after_eq(end_time, jiffies));
2460         }
2461
2462         if (chip->device_type == DEVICE_SIS) {
2463                 /* unmute the output on SIS7012 */
2464                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2465         }
2466         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2467                 /* enable SPDIF interrupt */
2468                 unsigned int val;
2469                 pci_read_config_dword(chip->pci, 0x4c, &val);
2470                 val |= 0x1000000;
2471                 pci_write_config_dword(chip->pci, 0x4c, val);
2472         }
2473         return 0;
2474 }
2475
2476 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2477 {
2478         u32 reg;
2479         int i = 0;
2480
2481         reg = igetdword(chip, ICHREG(ALI_SCR));
2482         if ((reg & 2) == 0)     /* Cold required */
2483                 reg |= 2;
2484         else
2485                 reg |= 1;       /* Warm */
2486         reg &= ~0x80000000;     /* ACLink on */
2487         iputdword(chip, ICHREG(ALI_SCR), reg);
2488
2489         for (i = 0; i < HZ / 2; i++) {
2490                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2491                         goto __ok;
2492                 schedule_timeout_uninterruptible(1);
2493         }
2494         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2495         if (probing)
2496                 return -EIO;
2497
2498  __ok:
2499         for (i = 0; i < HZ / 2; i++) {
2500                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2501                 if (reg & 0x80) /* primary codec */
2502                         break;
2503                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2504                 schedule_timeout_uninterruptible(1);
2505         }
2506
2507         do_ali_reset(chip);
2508         return 0;
2509 }
2510
2511 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2512 {
2513         unsigned int i, timeout;
2514         int err;
2515
2516         if (chip->device_type != DEVICE_ALI) {
2517                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2518                         return err;
2519                 iagetword(chip, 0);     /* clear semaphore flag */
2520         } else {
2521                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2522                         return err;
2523         }
2524
2525         /* disable interrupts */
2526         for (i = 0; i < chip->bdbars_count; i++)
2527                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2528         /* reset channels */
2529         for (i = 0; i < chip->bdbars_count; i++)
2530                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2531         for (i = 0; i < chip->bdbars_count; i++) {
2532                 timeout = 100000;
2533                 while (--timeout != 0) {
2534                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2535                                 break;
2536                 }
2537                 if (timeout == 0)
2538                         dev_err(chip->card->dev, "reset of registers failed?\n");
2539         }
2540         /* initialize Buffer Descriptor Lists */
2541         for (i = 0; i < chip->bdbars_count; i++)
2542                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2543                           chip->ichd[i].bdbar_addr);
2544         return 0;
2545 }
2546
2547 static int snd_intel8x0_free(struct intel8x0 *chip)
2548 {
2549         unsigned int i;
2550
2551         if (chip->irq < 0)
2552                 goto __hw_end;
2553         /* disable interrupts */
2554         for (i = 0; i < chip->bdbars_count; i++)
2555                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2556         /* reset channels */
2557         for (i = 0; i < chip->bdbars_count; i++)
2558                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2559         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2560                 /* stop the spdif interrupt */
2561                 unsigned int val;
2562                 pci_read_config_dword(chip->pci, 0x4c, &val);
2563                 val &= ~0x1000000;
2564                 pci_write_config_dword(chip->pci, 0x4c, val);
2565         }
2566         /* --- */
2567
2568       __hw_end:
2569         if (chip->irq >= 0)
2570                 free_irq(chip->irq, chip);
2571         if (chip->bdbars.area)
2572                 snd_dma_free_pages(&chip->bdbars);
2573         if (chip->addr)
2574                 pci_iounmap(chip->pci, chip->addr);
2575         if (chip->bmaddr)
2576                 pci_iounmap(chip->pci, chip->bmaddr);
2577         pci_release_regions(chip->pci);
2578         pci_disable_device(chip->pci);
2579         kfree(chip);
2580         return 0;
2581 }
2582
2583 #ifdef CONFIG_PM_SLEEP
2584 /*
2585  * power management
2586  */
2587 static int intel8x0_suspend(struct device *dev)
2588 {
2589         struct snd_card *card = dev_get_drvdata(dev);
2590         struct intel8x0 *chip = card->private_data;
2591         int i;
2592
2593         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2594         for (i = 0; i < chip->ncodecs; i++)
2595                 snd_ac97_suspend(chip->ac97[i]);
2596         if (chip->device_type == DEVICE_INTEL_ICH4)
2597                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2598
2599         if (chip->irq >= 0) {
2600                 free_irq(chip->irq, chip);
2601                 chip->irq = -1;
2602                 card->sync_irq = -1;
2603         }
2604         return 0;
2605 }
2606
2607 static int intel8x0_resume(struct device *dev)
2608 {
2609         struct pci_dev *pci = to_pci_dev(dev);
2610         struct snd_card *card = dev_get_drvdata(dev);
2611         struct intel8x0 *chip = card->private_data;
2612         int i;
2613
2614         snd_intel8x0_chip_init(chip, 0);
2615         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2616                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2617                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2618                         pci->irq);
2619                 snd_card_disconnect(card);
2620                 return -EIO;
2621         }
2622         chip->irq = pci->irq;
2623         card->sync_irq = chip->irq;
2624
2625         /* re-initialize mixer stuff */
2626         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2627                 /* enable separate SDINs for ICH4 */
2628                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2629                 /* use slot 10/11 for SPDIF */
2630                 iputdword(chip, ICHREG(GLOB_CNT),
2631                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2632                           ICH_PCM_SPDIF_1011);
2633         }
2634
2635         for (i = 0; i < chip->ncodecs; i++)
2636                 snd_ac97_resume(chip->ac97[i]);
2637
2638         /* resume status */
2639         for (i = 0; i < chip->bdbars_count; i++) {
2640                 struct ichdev *ichdev = &chip->ichd[i];
2641                 unsigned long port = ichdev->reg_offset;
2642                 if (! ichdev->substream || ! ichdev->suspended)
2643                         continue;
2644                 if (ichdev->ichd == ICHD_PCMOUT)
2645                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2646                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2647                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2648                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2649                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2650         }
2651
2652         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2653         return 0;
2654 }
2655
2656 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2657 #define INTEL8X0_PM_OPS &intel8x0_pm
2658 #else
2659 #define INTEL8X0_PM_OPS NULL
2660 #endif /* CONFIG_PM_SLEEP */
2661
2662 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2663
2664 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2665 {
2666         struct snd_pcm_substream *subs;
2667         struct ichdev *ichdev;
2668         unsigned long port;
2669         unsigned long pos, pos1, t;
2670         int civ, timeout = 1000, attempt = 1;
2671         ktime_t start_time, stop_time;
2672
2673         if (chip->ac97_bus->clock != 48000)
2674                 return; /* specified in module option */
2675
2676       __again:
2677         subs = chip->pcm[0]->streams[0].substream;
2678         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2679                 dev_warn(chip->card->dev,
2680                          "no playback buffer allocated - aborting measure ac97 clock\n");
2681                 return;
2682         }
2683         ichdev = &chip->ichd[ICHD_PCMOUT];
2684         ichdev->physbuf = subs->dma_buffer.addr;
2685         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2686         ichdev->substream = NULL; /* don't process interrupts */
2687
2688         /* set rate */
2689         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2690                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2691                         chip->ac97_bus->clock);
2692                 return;
2693         }
2694         snd_intel8x0_setup_periods(chip, ichdev);
2695         port = ichdev->reg_offset;
2696         spin_lock_irq(&chip->reg_lock);
2697         chip->in_measurement = 1;
2698         /* trigger */
2699         if (chip->device_type != DEVICE_ALI)
2700                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2701         else {
2702                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2703                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2704         }
2705         start_time = ktime_get();
2706         spin_unlock_irq(&chip->reg_lock);
2707         msleep(50);
2708         spin_lock_irq(&chip->reg_lock);
2709         /* check the position */
2710         do {
2711                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2712                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2713                 if (pos1 == 0) {
2714                         udelay(10);
2715                         continue;
2716                 }
2717                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2718                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2719                         break;
2720         } while (timeout--);
2721         if (pos1 == 0) {        /* oops, this value is not reliable */
2722                 pos = 0;
2723         } else {
2724                 pos = ichdev->fragsize1;
2725                 pos -= pos1 << ichdev->pos_shift;
2726                 pos += ichdev->position;
2727         }
2728         chip->in_measurement = 0;
2729         stop_time = ktime_get();
2730         /* stop */
2731         if (chip->device_type == DEVICE_ALI) {
2732                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2733                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2734                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2735                         ;
2736         } else {
2737                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2738                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2739                         ;
2740         }
2741         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2742         spin_unlock_irq(&chip->reg_lock);
2743
2744         if (pos == 0) {
2745                 dev_err(chip->card->dev,
2746                         "measure - unreliable DMA position..\n");
2747               __retry:
2748                 if (attempt < 3) {
2749                         msleep(300);
2750                         attempt++;
2751                         goto __again;
2752                 }
2753                 goto __end;
2754         }
2755
2756         pos /= 4;
2757         t = ktime_us_delta(stop_time, start_time);
2758         dev_info(chip->card->dev,
2759                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2760         if (t == 0) {
2761                 dev_err(chip->card->dev, "?? calculation error..\n");
2762                 goto __retry;
2763         }
2764         pos *= 1000;
2765         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2766         if (pos < 40000 || pos >= 60000) {
2767                 /* abnormal value. hw problem? */
2768                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2769                 goto __retry;
2770         } else if (pos > 40500 && pos < 41500)
2771                 /* first exception - 41000Hz reference clock */
2772                 chip->ac97_bus->clock = 41000;
2773         else if (pos > 43600 && pos < 44600)
2774                 /* second exception - 44100HZ reference clock */
2775                 chip->ac97_bus->clock = 44100;
2776         else if (pos < 47500 || pos > 48500)
2777                 /* not 48000Hz, tuning the clock.. */
2778                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2779       __end:
2780         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2781         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2782 }
2783
2784 static const struct snd_pci_quirk intel8x0_clock_list[] = {
2785         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2786         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2787         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2788         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2789         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2790         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2791         { }     /* terminator */
2792 };
2793
2794 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2795 {
2796         struct pci_dev *pci = chip->pci;
2797         const struct snd_pci_quirk *wl;
2798
2799         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2800         if (!wl)
2801                 return 0;
2802         dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2803                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2804         chip->ac97_bus->clock = wl->value;
2805         return 1;
2806 }
2807
2808 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2809                                    struct snd_info_buffer *buffer)
2810 {
2811         struct intel8x0 *chip = entry->private_data;
2812         unsigned int tmp;
2813
2814         snd_iprintf(buffer, "Intel8x0\n\n");
2815         if (chip->device_type == DEVICE_ALI)
2816                 return;
2817         tmp = igetdword(chip, ICHREG(GLOB_STA));
2818         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2819         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2820         if (chip->device_type == DEVICE_INTEL_ICH4)
2821                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2822         snd_iprintf(buffer, "AC'97 codecs ready    :");
2823         if (tmp & chip->codec_isr_bits) {
2824                 int i;
2825                 static const char *codecs[3] = {
2826                         "primary", "secondary", "tertiary"
2827                 };
2828                 for (i = 0; i < chip->max_codecs; i++)
2829                         if (tmp & chip->codec_bit[i])
2830                                 snd_iprintf(buffer, " %s", codecs[i]);
2831         } else
2832                 snd_iprintf(buffer, " none");
2833         snd_iprintf(buffer, "\n");
2834         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2835             chip->device_type == DEVICE_SIS)
2836                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2837                         chip->ac97_sdin[0],
2838                         chip->ac97_sdin[1],
2839                         chip->ac97_sdin[2]);
2840 }
2841
2842 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2843 {
2844         snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2845                              snd_intel8x0_proc_read);
2846 }
2847
2848 static int snd_intel8x0_dev_free(struct snd_device *device)
2849 {
2850         struct intel8x0 *chip = device->device_data;
2851         return snd_intel8x0_free(chip);
2852 }
2853
2854 struct ich_reg_info {
2855         unsigned int int_sta_mask;
2856         unsigned int offset;
2857 };
2858
2859 static const unsigned int ich_codec_bits[3] = {
2860         ICH_PCR, ICH_SCR, ICH_TCR
2861 };
2862 static const unsigned int sis_codec_bits[3] = {
2863         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2864 };
2865
2866 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2867 {
2868         int result  = inside_vm;
2869         char *msg   = NULL;
2870
2871         /* check module parameter first (override detection) */
2872         if (result >= 0) {
2873                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2874                 goto fini;
2875         }
2876
2877         /* check for known (emulated) devices */
2878         result = 0;
2879         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2880             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2881                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2882                 msg = "enable KVM";
2883                 result = 1;
2884         } else if (pci->subsystem_vendor == 0x1ab8) {
2885                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2886                 msg = "enable Parallels VM";
2887                 result = 1;
2888         }
2889
2890 fini:
2891         if (msg != NULL)
2892                 dev_info(&pci->dev, "%s optimization\n", msg);
2893
2894         return result;
2895 }
2896
2897 static int snd_intel8x0_create(struct snd_card *card,
2898                                struct pci_dev *pci,
2899                                unsigned long device_type,
2900                                struct intel8x0 **r_intel8x0)
2901 {
2902         struct intel8x0 *chip;
2903         int err;
2904         unsigned int i;
2905         unsigned int int_sta_masks;
2906         struct ichdev *ichdev;
2907         static const struct snd_device_ops ops = {
2908                 .dev_free =     snd_intel8x0_dev_free,
2909         };
2910
2911         static const unsigned int bdbars[] = {
2912                 3, /* DEVICE_INTEL */
2913                 6, /* DEVICE_INTEL_ICH4 */
2914                 3, /* DEVICE_SIS */
2915                 6, /* DEVICE_ALI */
2916                 4, /* DEVICE_NFORCE */
2917         };
2918         static const struct ich_reg_info intel_regs[6] = {
2919                 { ICH_PIINT, 0 },
2920                 { ICH_POINT, 0x10 },
2921                 { ICH_MCINT, 0x20 },
2922                 { ICH_M2INT, 0x40 },
2923                 { ICH_P2INT, 0x50 },
2924                 { ICH_SPINT, 0x60 },
2925         };
2926         static const struct ich_reg_info nforce_regs[4] = {
2927                 { ICH_PIINT, 0 },
2928                 { ICH_POINT, 0x10 },
2929                 { ICH_MCINT, 0x20 },
2930                 { ICH_NVSPINT, 0x70 },
2931         };
2932         static const struct ich_reg_info ali_regs[6] = {
2933                 { ALI_INT_PCMIN, 0x40 },
2934                 { ALI_INT_PCMOUT, 0x50 },
2935                 { ALI_INT_MICIN, 0x60 },
2936                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2937                 { ALI_INT_SPDIFIN, 0xa0 },
2938                 { ALI_INT_SPDIFOUT, 0xb0 },
2939         };
2940         const struct ich_reg_info *tbl;
2941
2942         *r_intel8x0 = NULL;
2943
2944         if ((err = pci_enable_device(pci)) < 0)
2945                 return err;
2946
2947         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2948         if (chip == NULL) {
2949                 pci_disable_device(pci);
2950                 return -ENOMEM;
2951         }
2952         spin_lock_init(&chip->reg_lock);
2953         chip->device_type = device_type;
2954         chip->card = card;
2955         chip->pci = pci;
2956         chip->irq = -1;
2957
2958         /* module parameters */
2959         chip->buggy_irq = buggy_irq;
2960         chip->buggy_semaphore = buggy_semaphore;
2961         if (xbox)
2962                 chip->xbox = 1;
2963
2964         chip->inside_vm = snd_intel8x0_inside_vm(pci);
2965
2966         /*
2967          * Intel 82443MX running a 100MHz processor system bus has a hardware
2968          * bug, which aborts PCI busmaster for audio transfer.  A workaround
2969          * is to set the pages as non-cached.  For details, see the errata in
2970          *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2971          */
2972         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2973             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2974                 chip->fix_nocache = 1; /* enable workaround */
2975
2976         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2977                 kfree(chip);
2978                 pci_disable_device(pci);
2979                 return err;
2980         }
2981
2982         if (device_type == DEVICE_ALI) {
2983                 /* ALI5455 has no ac97 region */
2984                 chip->bmaddr = pci_iomap(pci, 0, 0);
2985                 goto port_inited;
2986         }
2987
2988         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2989                 chip->addr = pci_iomap(pci, 2, 0);
2990         else
2991                 chip->addr = pci_iomap(pci, 0, 0);
2992         if (!chip->addr) {
2993                 dev_err(card->dev, "AC'97 space ioremap problem\n");
2994                 snd_intel8x0_free(chip);
2995                 return -EIO;
2996         }
2997         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2998                 chip->bmaddr = pci_iomap(pci, 3, 0);
2999         else
3000                 chip->bmaddr = pci_iomap(pci, 1, 0);
3001
3002  port_inited:
3003         if (!chip->bmaddr) {
3004                 dev_err(card->dev, "Controller space ioremap problem\n");
3005                 snd_intel8x0_free(chip);
3006                 return -EIO;
3007         }
3008         chip->bdbars_count = bdbars[device_type];
3009
3010         /* initialize offsets */
3011         switch (device_type) {
3012         case DEVICE_NFORCE:
3013                 tbl = nforce_regs;
3014                 break;
3015         case DEVICE_ALI:
3016                 tbl = ali_regs;
3017                 break;
3018         default:
3019                 tbl = intel_regs;
3020                 break;
3021         }
3022         for (i = 0; i < chip->bdbars_count; i++) {
3023                 ichdev = &chip->ichd[i];
3024                 ichdev->ichd = i;
3025                 ichdev->reg_offset = tbl[i].offset;
3026                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3027                 if (device_type == DEVICE_SIS) {
3028                         /* SiS 7012 swaps the registers */
3029                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3030                         ichdev->roff_picb = ICH_REG_OFF_SR;
3031                 } else {
3032                         ichdev->roff_sr = ICH_REG_OFF_SR;
3033                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3034                 }
3035                 if (device_type == DEVICE_ALI)
3036                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3037                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3038                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3039         }
3040
3041         /* allocate buffer descriptor lists */
3042         /* the start of each lists must be aligned to 8 bytes */
3043         if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
3044                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3045                                 &chip->bdbars) < 0) {
3046                 snd_intel8x0_free(chip);
3047                 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3048                 return -ENOMEM;
3049         }
3050         /* tables must be aligned to 8 bytes here, but the kernel pages
3051            are much bigger, so we don't care (on i386) */
3052         int_sta_masks = 0;
3053         for (i = 0; i < chip->bdbars_count; i++) {
3054                 ichdev = &chip->ichd[i];
3055                 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3056                         (i * ICH_MAX_FRAGS * 2);
3057                 ichdev->bdbar_addr = chip->bdbars.addr +
3058                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3059                 int_sta_masks |= ichdev->int_sta_mask;
3060         }
3061         chip->int_sta_reg = device_type == DEVICE_ALI ?
3062                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3063         chip->int_sta_mask = int_sta_masks;
3064
3065         pci_set_master(pci);
3066
3067         switch(chip->device_type) {
3068         case DEVICE_INTEL_ICH4:
3069                 /* ICH4 can have three codecs */
3070                 chip->max_codecs = 3;
3071                 chip->codec_bit = ich_codec_bits;
3072                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3073                 break;
3074         case DEVICE_SIS:
3075                 /* recent SIS7012 can have three codecs */
3076                 chip->max_codecs = 3;
3077                 chip->codec_bit = sis_codec_bits;
3078                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3079                 break;
3080         default:
3081                 /* others up to two codecs */
3082                 chip->max_codecs = 2;
3083                 chip->codec_bit = ich_codec_bits;
3084                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3085                 break;
3086         }
3087         for (i = 0; i < chip->max_codecs; i++)
3088                 chip->codec_isr_bits |= chip->codec_bit[i];
3089
3090         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3091                 snd_intel8x0_free(chip);
3092                 return err;
3093         }
3094
3095         /* request irq after initializaing int_sta_mask, etc */
3096         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3097                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3098                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3099                 snd_intel8x0_free(chip);
3100                 return -EBUSY;
3101         }
3102         chip->irq = pci->irq;
3103         card->sync_irq = chip->irq;
3104
3105         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3106                 snd_intel8x0_free(chip);
3107                 return err;
3108         }
3109
3110         *r_intel8x0 = chip;
3111         return 0;
3112 }
3113
3114 static struct shortname_table {
3115         unsigned int id;
3116         const char *s;
3117 } shortnames[] = {
3118         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3119         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3120         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3121         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3122         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3123         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3124         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3125         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3126         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3127         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3128         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3129         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3130         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3131         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3132         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3133         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3134         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3135         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3136         { 0x003a, "NVidia MCP04" },
3137         { 0x746d, "AMD AMD8111" },
3138         { 0x7445, "AMD AMD768" },
3139         { 0x5455, "ALi M5455" },
3140         { 0, NULL },
3141 };
3142
3143 static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3144         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3145         { } /* end */
3146 };
3147
3148 /* look up allow/deny list for SPDIF over ac-link */
3149 static int check_default_spdif_aclink(struct pci_dev *pci)
3150 {
3151         const struct snd_pci_quirk *w;
3152
3153         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3154         if (w) {
3155                 if (w->value)
3156                         dev_dbg(&pci->dev,
3157                                 "Using SPDIF over AC-Link for %s\n",
3158                                     snd_pci_quirk_name(w));
3159                 else
3160                         dev_dbg(&pci->dev,
3161                                 "Using integrated SPDIF DMA for %s\n",
3162                                     snd_pci_quirk_name(w));
3163                 return w->value;
3164         }
3165         return 0;
3166 }
3167
3168 static int snd_intel8x0_probe(struct pci_dev *pci,
3169                               const struct pci_device_id *pci_id)
3170 {
3171         struct snd_card *card;
3172         struct intel8x0 *chip;
3173         int err;
3174         struct shortname_table *name;
3175
3176         err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3177         if (err < 0)
3178                 return err;
3179
3180         if (spdif_aclink < 0)
3181                 spdif_aclink = check_default_spdif_aclink(pci);
3182
3183         strcpy(card->driver, "ICH");
3184         if (!spdif_aclink) {
3185                 switch (pci_id->driver_data) {
3186                 case DEVICE_NFORCE:
3187                         strcpy(card->driver, "NFORCE");
3188                         break;
3189                 case DEVICE_INTEL_ICH4:
3190                         strcpy(card->driver, "ICH4");
3191                 }
3192         }
3193
3194         strcpy(card->shortname, "Intel ICH");
3195         for (name = shortnames; name->id; name++) {
3196                 if (pci->device == name->id) {
3197                         strcpy(card->shortname, name->s);
3198                         break;
3199                 }
3200         }
3201
3202         if (buggy_irq < 0) {
3203                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3204                  * Needs to return IRQ_HANDLED for unknown irqs.
3205                  */
3206                 if (pci_id->driver_data == DEVICE_NFORCE)
3207                         buggy_irq = 1;
3208                 else
3209                         buggy_irq = 0;
3210         }
3211
3212         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3213                                        &chip)) < 0) {
3214                 snd_card_free(card);
3215                 return err;
3216         }
3217         card->private_data = chip;
3218
3219         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3220                 snd_card_free(card);
3221                 return err;
3222         }
3223         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3224                 snd_card_free(card);
3225                 return err;
3226         }
3227
3228         snd_intel8x0_proc_init(chip);
3229
3230         snprintf(card->longname, sizeof(card->longname),
3231                  "%s with %s at irq %i", card->shortname,
3232                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3233
3234         if (ac97_clock == 0 || ac97_clock == 1) {
3235                 if (ac97_clock == 0) {
3236                         if (intel8x0_in_clock_list(chip) == 0)
3237                                 intel8x0_measure_ac97_clock(chip);
3238                 } else {
3239                         intel8x0_measure_ac97_clock(chip);
3240                 }
3241         }
3242
3243         if ((err = snd_card_register(card)) < 0) {
3244                 snd_card_free(card);
3245                 return err;
3246         }
3247         pci_set_drvdata(pci, card);
3248         return 0;
3249 }
3250
3251 static void snd_intel8x0_remove(struct pci_dev *pci)
3252 {
3253         snd_card_free(pci_get_drvdata(pci));
3254 }
3255
3256 static struct pci_driver intel8x0_driver = {
3257         .name = KBUILD_MODNAME,
3258         .id_table = snd_intel8x0_ids,
3259         .probe = snd_intel8x0_probe,
3260         .remove = snd_intel8x0_remove,
3261         .driver = {
3262                 .pm = INTEL8X0_PM_OPS,
3263         },
3264 };
3265
3266 module_pci_driver(intel8x0_driver);