1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for Intel ICH (i8x0) chipsets
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/ac97_codec.h>
24 #include <sound/info.h>
25 #include <sound/initval.h>
27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
29 MODULE_LICENSE("GPL");
31 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
32 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
33 static int ac97_clock;
34 static char *ac97_quirk;
35 static bool buggy_semaphore;
36 static int buggy_irq = -1; /* auto-check */
38 static int spdif_aclink = -1;
39 static int inside_vm = -1;
41 module_param(index, int, 0444);
42 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
43 module_param(id, charp, 0444);
44 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
45 module_param(ac97_clock, int, 0444);
46 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
47 module_param(ac97_quirk, charp, 0444);
48 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
49 module_param(buggy_semaphore, bool, 0444);
50 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
51 module_param(buggy_irq, bint, 0444);
52 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
53 module_param(xbox, bool, 0444);
54 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
55 module_param(spdif_aclink, int, 0444);
56 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
57 module_param(inside_vm, bint, 0444);
58 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
60 /* just for backward compatibility */
62 module_param(enable, bool, 0444);
64 module_param(joystick, int, 0444);
69 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
71 #define ICHREG(x) ICH_REG_##x
73 #define DEFINE_REGSET(name,base) \
75 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
76 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
77 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
78 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
79 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
80 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
81 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
84 /* busmaster blocks */
85 DEFINE_REGSET(OFF, 0); /* offset */
86 DEFINE_REGSET(PI, 0x00); /* PCM in */
87 DEFINE_REGSET(PO, 0x10); /* PCM out */
88 DEFINE_REGSET(MC, 0x20); /* Mic in */
90 /* ICH4 busmaster blocks */
91 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
92 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
93 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
95 /* values for each busmaster block */
98 #define ICH_REG_LVI_MASK 0x1f
101 #define ICH_FIFOE 0x10 /* FIFO error */
102 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
103 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
104 #define ICH_CELV 0x02 /* current equals last valid */
105 #define ICH_DCH 0x01 /* DMA controller halted */
108 #define ICH_REG_PIV_MASK 0x1f /* mask */
111 #define ICH_IOCE 0x10 /* interrupt on completion enable */
112 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
113 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
114 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
115 #define ICH_STARTBM 0x01 /* start busmaster operation */
119 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
120 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
121 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
122 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
123 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
124 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
125 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
126 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
127 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
128 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
129 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
130 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
131 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
132 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
133 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
134 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
135 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
136 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
137 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
138 #define ICH_ACLINK 0x00000008 /* AClink shut off */
139 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
140 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
141 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
142 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
143 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
144 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
145 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
146 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
147 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
148 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
149 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
150 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
151 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
152 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
153 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
154 #define ICH_MD3 0x00020000 /* modem power down semaphore */
155 #define ICH_AD3 0x00010000 /* audio power down semaphore */
156 #define ICH_RCS 0x00008000 /* read completion status */
157 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
158 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
159 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
160 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
161 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
162 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
163 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
164 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
165 #define ICH_POINT 0x00000040 /* playback interrupt */
166 #define ICH_PIINT 0x00000020 /* capture interrupt */
167 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
168 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
169 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
170 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
171 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
172 #define ICH_CAS 0x01 /* codec access semaphore */
173 #define ICH_REG_SDM 0x80
174 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
175 #define ICH_DI2L_SHIFT 6
176 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
177 #define ICH_DI1L_SHIFT 4
178 #define ICH_SE 0x00000008 /* steer enable */
179 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
181 #define ICH_MAX_FRAGS 32 /* max hw frags */
185 * registers for Ali5455
188 /* ALi 5455 busmaster blocks */
189 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
190 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
191 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
192 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
193 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
194 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
195 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
196 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
197 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
198 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
199 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
202 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
203 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
204 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
205 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
206 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
207 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
208 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
209 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
210 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
211 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
212 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
213 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
214 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
215 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
216 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
217 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
218 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
219 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
220 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
221 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
222 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
225 #define ALI_CAS_SEM_BUSY 0x80000000
226 #define ALI_CPR_ADDR_SECONDARY 0x100
227 #define ALI_CPR_ADDR_READ 0x80
228 #define ALI_CSPSR_CODEC_READY 0x08
229 #define ALI_CSPSR_READ_OK 0x02
230 #define ALI_CSPSR_WRITE_OK 0x01
232 /* interrupts for the whole chip by interrupt status register finish */
234 #define ALI_INT_MICIN2 (1<<26)
235 #define ALI_INT_PCMIN2 (1<<25)
236 #define ALI_INT_I2SIN (1<<24)
237 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
238 #define ALI_INT_SPDIFIN (1<<22)
239 #define ALI_INT_LFEOUT (1<<21)
240 #define ALI_INT_CENTEROUT (1<<20)
241 #define ALI_INT_CODECSPDIFOUT (1<<19)
242 #define ALI_INT_MICIN (1<<18)
243 #define ALI_INT_PCMOUT (1<<17)
244 #define ALI_INT_PCMIN (1<<16)
245 #define ALI_INT_CPRAIS (1<<7) /* command port available */
246 #define ALI_INT_SPRAIS (1<<5) /* status port available */
247 #define ALI_INT_GPIO (1<<1)
248 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
249 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
251 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
252 #define ICH_ALI_SC_AC97_DBL (1<<30)
253 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
254 #define ICH_ALI_SC_IN_BITS (3<<18)
255 #define ICH_ALI_SC_OUT_BITS (3<<16)
256 #define ICH_ALI_SC_6CH_CFG (3<<14)
257 #define ICH_ALI_SC_PCM_4 (1<<8)
258 #define ICH_ALI_SC_PCM_6 (2<<8)
259 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
261 #define ICH_ALI_SS_SEC_ID (3<<5)
262 #define ICH_ALI_SS_PRI_ID (3<<3)
264 #define ICH_ALI_IF_AC97SP (1<<21)
265 #define ICH_ALI_IF_MC (1<<20)
266 #define ICH_ALI_IF_PI (1<<19)
267 #define ICH_ALI_IF_MC2 (1<<18)
268 #define ICH_ALI_IF_PI2 (1<<17)
269 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
270 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
271 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
272 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
273 #define ICH_ALI_IF_PO_SPDF (1<<3)
274 #define ICH_ALI_IF_PO (1<<1)
287 ICHD_LAST = ICHD_SPBAR
303 ALID_LAST = ALID_SPDIFOUT
306 #define get_ichdev(substream) (substream->runtime->private_data)
309 unsigned int ichd; /* ich device number */
310 unsigned long reg_offset; /* offset to bmaddr */
311 __le32 *bdbar; /* CPU address (32bit) */
312 unsigned int bdbar_addr; /* PCI bus address (32bit) */
313 struct snd_pcm_substream *substream;
314 unsigned int physbuf; /* physical address (32bit) */
316 unsigned int fragsize;
317 unsigned int fragsize1;
318 unsigned int position;
319 unsigned int pos_shift;
320 unsigned int last_pos;
327 unsigned int ack_bit;
328 unsigned int roff_sr;
329 unsigned int roff_picb;
330 unsigned int int_sta_mask; /* interrupt status mask */
331 unsigned int ali_slot; /* ALI DMA slot */
332 struct ac97_pcm *pcm;
334 unsigned int prepared:1;
335 unsigned int suspended: 1;
339 unsigned int device_type;
344 void __iomem *bmaddr;
347 struct snd_card *card;
350 struct snd_pcm *pcm[6];
351 struct ichdev ichd[6];
358 unsigned in_ac97_init: 1,
360 unsigned in_measurement: 1; /* during ac97 clock measurement */
361 unsigned fix_nocache: 1; /* workaround for 440MX */
362 unsigned buggy_irq: 1; /* workaround for buggy mobos */
363 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
364 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
365 unsigned inside_vm: 1; /* enable VM optimization */
367 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
368 unsigned int sdm_saved; /* SDM reg value */
370 struct snd_ac97_bus *ac97_bus;
371 struct snd_ac97 *ac97[3];
372 unsigned int ac97_sdin[3];
373 unsigned int max_codecs, ncodecs;
374 const unsigned int *codec_bit;
375 unsigned int codec_isr_bits;
376 unsigned int codec_ready_bits;
381 struct snd_dma_buffer bdbars;
382 u32 int_sta_reg; /* interrupt status register */
383 u32 int_sta_mask; /* interrupt status mask */
386 static const struct pci_device_id snd_intel8x0_ids[] = {
387 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
388 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
389 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
390 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
391 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
392 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
393 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
394 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
395 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
396 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
397 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
398 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
399 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
400 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
401 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
402 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
403 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
404 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
405 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
406 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
407 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
408 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
409 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
413 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
416 * Lowlevel I/O - busmaster
419 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
421 return ioread8(chip->bmaddr + offset);
424 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
426 return ioread16(chip->bmaddr + offset);
429 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
431 return ioread32(chip->bmaddr + offset);
434 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
436 iowrite8(val, chip->bmaddr + offset);
439 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
441 iowrite16(val, chip->bmaddr + offset);
444 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
446 iowrite32(val, chip->bmaddr + offset);
450 * Lowlevel I/O - AC'97 registers
453 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
455 return ioread16(chip->addr + offset);
458 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
460 iowrite16(val, chip->addr + offset);
468 * access to AC97 codec via normal i/o (for ICH and SIS7012)
471 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
477 if (chip->in_sdin_init) {
478 /* we don't know the ready bit assignment at the moment */
479 /* so we check any */
480 codec = chip->codec_isr_bits;
482 codec = chip->codec_bit[chip->ac97_sdin[codec]];
486 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
489 if (chip->buggy_semaphore)
490 return 0; /* just ignore ... */
492 /* Anyone holding a semaphore for 1 msec should be shot... */
495 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
500 /* access to some forbidden (non existent) ac97 registers will not
501 * reset the semaphore. So even if you don't get the semaphore, still
502 * continue the access. We don't need the semaphore anyway. */
503 dev_err(chip->card->dev,
504 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
505 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
506 iagetword(chip, 0); /* clear semaphore flag */
507 /* I don't care about the semaphore */
511 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
515 struct intel8x0 *chip = ac97->private_data;
517 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
518 if (! chip->in_ac97_init)
519 dev_err(chip->card->dev,
520 "codec_write %d: semaphore is not ready for register 0x%x\n",
523 iaputword(chip, reg + ac97->num * 0x80, val);
526 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
529 struct intel8x0 *chip = ac97->private_data;
533 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
534 if (! chip->in_ac97_init)
535 dev_err(chip->card->dev,
536 "codec_read %d: semaphore is not ready for register 0x%x\n",
540 res = iagetword(chip, reg + ac97->num * 0x80);
541 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
542 /* reset RCS and preserve other R/WC bits */
543 iputdword(chip, ICHREG(GLOB_STA), tmp &
544 ~(chip->codec_ready_bits | ICH_GSCI));
545 if (! chip->in_ac97_init)
546 dev_err(chip->card->dev,
547 "codec_read %d: read timeout for register 0x%x\n",
555 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
560 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
561 iagetword(chip, codec * 0x80);
562 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
563 /* reset RCS and preserve other R/WC bits */
564 iputdword(chip, ICHREG(GLOB_STA), tmp &
565 ~(chip->codec_ready_bits | ICH_GSCI));
571 * access to AC97 for Ali5455
573 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
576 for (count = 0; count < 0x7f; count++) {
577 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
581 if (! chip->in_ac97_init)
582 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
586 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
589 if (chip->buggy_semaphore)
590 return 0; /* just ignore ... */
591 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
593 if (! time && ! chip->in_ac97_init)
594 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
595 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
598 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
600 struct intel8x0 *chip = ac97->private_data;
601 unsigned short data = 0xffff;
603 if (snd_intel8x0_ali_codec_semaphore(chip))
605 reg |= ALI_CPR_ADDR_READ;
607 reg |= ALI_CPR_ADDR_SECONDARY;
608 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
609 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
611 data = igetword(chip, ICHREG(ALI_SPR));
616 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
619 struct intel8x0 *chip = ac97->private_data;
621 if (snd_intel8x0_ali_codec_semaphore(chip))
623 iputword(chip, ICHREG(ALI_CPR), val);
625 reg |= ALI_CPR_ADDR_SECONDARY;
626 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
627 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
634 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
637 __le32 *bdbar = ichdev->bdbar;
638 unsigned long port = ichdev->reg_offset;
640 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
641 if (ichdev->size == ichdev->fragsize) {
642 ichdev->ack_reload = ichdev->ack = 2;
643 ichdev->fragsize1 = ichdev->fragsize >> 1;
644 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
645 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
646 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
647 ichdev->fragsize1 >> ichdev->pos_shift);
648 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
649 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
650 ichdev->fragsize1 >> ichdev->pos_shift);
654 ichdev->ack_reload = ichdev->ack = 1;
655 ichdev->fragsize1 = ichdev->fragsize;
656 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
657 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
658 (((idx >> 1) * ichdev->fragsize) %
660 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
661 ichdev->fragsize >> ichdev->pos_shift);
663 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
664 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
667 ichdev->frags = ichdev->size / ichdev->fragsize;
669 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
671 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
672 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
673 ichdev->position = 0;
675 dev_dbg(chip->card->dev,
676 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
677 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
680 /* clear interrupts */
681 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
688 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
690 unsigned long port = ichdev->reg_offset;
692 int status, civ, i, step;
695 if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
698 spin_lock_irqsave(&chip->reg_lock, flags);
699 status = igetbyte(chip, port + ichdev->roff_sr);
700 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
701 if (!(status & ICH_BCIS)) {
703 } else if (civ == ichdev->civ) {
704 // snd_printd("civ same %d\n", civ);
707 ichdev->civ &= ICH_REG_LVI_MASK;
709 step = civ - ichdev->civ;
711 step += ICH_REG_LVI_MASK + 1;
713 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
717 ichdev->position += step * ichdev->fragsize1;
718 if (! chip->in_measurement)
719 ichdev->position %= ichdev->size;
721 ichdev->lvi &= ICH_REG_LVI_MASK;
722 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
723 for (i = 0; i < step; i++) {
725 ichdev->lvi_frag %= ichdev->frags;
726 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
728 dev_dbg(chip->card->dev,
729 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
730 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
731 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
732 inl(port + 4), inb(port + ICH_REG_OFF_CR));
734 if (--ichdev->ack == 0) {
735 ichdev->ack = ichdev->ack_reload;
739 spin_unlock_irqrestore(&chip->reg_lock, flags);
740 if (ack && ichdev->substream) {
741 snd_pcm_period_elapsed(ichdev->substream);
743 iputbyte(chip, port + ichdev->roff_sr,
744 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
747 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
749 struct intel8x0 *chip = dev_id;
750 struct ichdev *ichdev;
754 status = igetdword(chip, chip->int_sta_reg);
755 if (status == 0xffffffff) /* we are not yet resumed */
758 if ((status & chip->int_sta_mask) == 0) {
761 iputdword(chip, chip->int_sta_reg, status);
762 if (! chip->buggy_irq)
765 return IRQ_RETVAL(status);
768 for (i = 0; i < chip->bdbars_count; i++) {
769 ichdev = &chip->ichd[i];
770 if (status & ichdev->int_sta_mask)
771 snd_intel8x0_update(chip, ichdev);
775 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
784 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
786 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
787 struct ichdev *ichdev = get_ichdev(substream);
788 unsigned char val = 0;
789 unsigned long port = ichdev->reg_offset;
792 case SNDRV_PCM_TRIGGER_RESUME:
793 ichdev->suspended = 0;
795 case SNDRV_PCM_TRIGGER_START:
796 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
797 val = ICH_IOCE | ICH_STARTBM;
798 ichdev->last_pos = ichdev->position;
800 case SNDRV_PCM_TRIGGER_SUSPEND:
801 ichdev->suspended = 1;
803 case SNDRV_PCM_TRIGGER_STOP:
806 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
812 iputbyte(chip, port + ICH_REG_OFF_CR, val);
813 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
814 /* wait until DMA stopped */
815 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
816 /* reset whole DMA things */
817 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
822 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
824 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
825 struct ichdev *ichdev = get_ichdev(substream);
826 unsigned long port = ichdev->reg_offset;
827 static const int fiforeg[] = {
828 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
830 unsigned int val, fifo;
832 val = igetdword(chip, ICHREG(ALI_DMACR));
834 case SNDRV_PCM_TRIGGER_RESUME:
835 ichdev->suspended = 0;
837 case SNDRV_PCM_TRIGGER_START:
838 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
839 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
840 /* clear FIFO for synchronization of channels */
841 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
842 fifo &= ~(0xff << (ichdev->ali_slot % 4));
843 fifo |= 0x83 << (ichdev->ali_slot % 4);
844 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
846 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
847 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
849 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
851 case SNDRV_PCM_TRIGGER_SUSPEND:
852 ichdev->suspended = 1;
854 case SNDRV_PCM_TRIGGER_STOP:
855 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
857 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
858 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
859 while (igetbyte(chip, port + ICH_REG_OFF_CR))
861 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
863 /* reset whole DMA things */
864 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
865 /* clear interrupts */
866 iputbyte(chip, port + ICH_REG_OFF_SR,
867 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
868 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
869 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
877 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
878 struct snd_pcm_hw_params *hw_params)
880 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
881 struct ichdev *ichdev = get_ichdev(substream);
882 int dbl = params_rate(hw_params) > 48000;
885 if (ichdev->pcm_open_flag) {
886 snd_ac97_pcm_close(ichdev->pcm);
887 ichdev->pcm_open_flag = 0;
888 ichdev->prepared = 0;
890 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
891 params_channels(hw_params),
892 ichdev->pcm->r[dbl].slots);
894 ichdev->pcm_open_flag = 1;
895 /* Force SPDIF setting */
896 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
897 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
898 params_rate(hw_params));
903 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
905 struct ichdev *ichdev = get_ichdev(substream);
907 if (ichdev->pcm_open_flag) {
908 snd_ac97_pcm_close(ichdev->pcm);
909 ichdev->pcm_open_flag = 0;
910 ichdev->prepared = 0;
915 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
916 struct snd_pcm_runtime *runtime)
919 int dbl = runtime->rate > 48000;
921 spin_lock_irq(&chip->reg_lock);
922 switch (chip->device_type) {
924 cnt = igetdword(chip, ICHREG(ALI_SCR));
925 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
926 if (runtime->channels == 4 || dbl)
927 cnt |= ICH_ALI_SC_PCM_4;
928 else if (runtime->channels == 6)
929 cnt |= ICH_ALI_SC_PCM_6;
930 iputdword(chip, ICHREG(ALI_SCR), cnt);
933 cnt = igetdword(chip, ICHREG(GLOB_CNT));
934 cnt &= ~ICH_SIS_PCM_246_MASK;
935 if (runtime->channels == 4 || dbl)
936 cnt |= ICH_SIS_PCM_4;
937 else if (runtime->channels == 6)
938 cnt |= ICH_SIS_PCM_6;
939 iputdword(chip, ICHREG(GLOB_CNT), cnt);
942 cnt = igetdword(chip, ICHREG(GLOB_CNT));
943 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
944 if (runtime->channels == 4 || dbl)
946 else if (runtime->channels == 6)
948 else if (runtime->channels == 8)
950 if (chip->device_type == DEVICE_NFORCE) {
951 /* reset to 2ch once to keep the 6 channel data in alignment,
952 * to start from Front Left always
954 if (cnt & ICH_PCM_246_MASK) {
955 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
956 spin_unlock_irq(&chip->reg_lock);
957 msleep(50); /* grrr... */
958 spin_lock_irq(&chip->reg_lock);
960 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
961 if (runtime->sample_bits > 16)
962 cnt |= ICH_PCM_20BIT;
964 iputdword(chip, ICHREG(GLOB_CNT), cnt);
967 spin_unlock_irq(&chip->reg_lock);
970 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
972 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
973 struct snd_pcm_runtime *runtime = substream->runtime;
974 struct ichdev *ichdev = get_ichdev(substream);
976 ichdev->physbuf = runtime->dma_addr;
977 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
978 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
979 if (ichdev->ichd == ICHD_PCMOUT) {
980 snd_intel8x0_setup_pcm_out(chip, runtime);
981 if (chip->device_type == DEVICE_INTEL_ICH4)
982 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
984 snd_intel8x0_setup_periods(chip, ichdev);
985 ichdev->prepared = 1;
989 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
991 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
992 struct ichdev *ichdev = get_ichdev(substream);
994 int civ, timeout = 10;
995 unsigned int position;
997 spin_lock(&chip->reg_lock);
999 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1000 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1001 position = ichdev->position;
1006 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1009 /* IO read operation is very expensive inside virtual machine
1010 * as it is emulated. The probability that subsequent PICB read
1011 * will return different result is high enough to loop till
1013 * Same CIV is strict enough condition to be sure that PICB
1014 * is valid inside VM on emulated card. */
1015 if (chip->inside_vm)
1017 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1019 } while (timeout--);
1020 ptr = ichdev->last_pos;
1022 ptr1 <<= ichdev->pos_shift;
1023 ptr = ichdev->fragsize1 - ptr1;
1025 if (ptr < ichdev->last_pos) {
1026 unsigned int pos_base, last_base;
1027 pos_base = position / ichdev->fragsize1;
1028 last_base = ichdev->last_pos / ichdev->fragsize1;
1029 /* another sanity check; ptr1 can go back to full
1030 * before the base position is updated
1032 if (pos_base == last_base)
1033 ptr = ichdev->last_pos;
1036 ichdev->last_pos = ptr;
1037 spin_unlock(&chip->reg_lock);
1038 if (ptr >= ichdev->size)
1040 return bytes_to_frames(substream->runtime, ptr);
1043 static const struct snd_pcm_hardware snd_intel8x0_stream =
1045 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1046 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1047 SNDRV_PCM_INFO_MMAP_VALID |
1048 SNDRV_PCM_INFO_PAUSE |
1049 SNDRV_PCM_INFO_RESUME),
1050 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1051 .rates = SNDRV_PCM_RATE_48000,
1056 .buffer_bytes_max = 128 * 1024,
1057 .period_bytes_min = 32,
1058 .period_bytes_max = 128 * 1024,
1060 .periods_max = 1024,
1064 static const unsigned int channels4[] = {
1068 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1069 .count = ARRAY_SIZE(channels4),
1074 static const unsigned int channels6[] = {
1078 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1079 .count = ARRAY_SIZE(channels6),
1084 static const unsigned int channels8[] = {
1088 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1089 .count = ARRAY_SIZE(channels8),
1094 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1096 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1097 struct snd_pcm_runtime *runtime = substream->runtime;
1100 ichdev->substream = substream;
1101 runtime->hw = snd_intel8x0_stream;
1102 runtime->hw.rates = ichdev->pcm->rates;
1103 snd_pcm_limit_hw_rates(runtime);
1104 if (chip->device_type == DEVICE_SIS) {
1105 runtime->hw.buffer_bytes_max = 64*1024;
1106 runtime->hw.period_bytes_max = 64*1024;
1108 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1110 runtime->private_data = ichdev;
1114 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1116 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1117 struct snd_pcm_runtime *runtime = substream->runtime;
1120 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1125 runtime->hw.channels_max = 8;
1126 snd_pcm_hw_constraint_list(runtime, 0,
1127 SNDRV_PCM_HW_PARAM_CHANNELS,
1128 &hw_constraints_channels8);
1129 } else if (chip->multi6) {
1130 runtime->hw.channels_max = 6;
1131 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1132 &hw_constraints_channels6);
1133 } else if (chip->multi4) {
1134 runtime->hw.channels_max = 4;
1135 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1136 &hw_constraints_channels4);
1139 snd_ac97_pcm_double_rate_rules(runtime);
1141 if (chip->smp20bit) {
1142 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1143 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1148 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1150 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1152 chip->ichd[ICHD_PCMOUT].substream = NULL;
1156 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1158 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1160 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1163 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1165 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1167 chip->ichd[ICHD_PCMIN].substream = NULL;
1171 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1173 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1175 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1178 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1180 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1182 chip->ichd[ICHD_MIC].substream = NULL;
1186 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1190 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1193 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1195 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197 chip->ichd[ICHD_MIC2].substream = NULL;
1201 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1203 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1205 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1208 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212 chip->ichd[ICHD_PCM2IN].substream = NULL;
1216 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1218 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1221 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1224 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1226 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1229 chip->ichd[idx].substream = NULL;
1233 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1235 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238 spin_lock_irq(&chip->reg_lock);
1239 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1240 val |= ICH_ALI_IF_AC97SP;
1241 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1242 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1243 spin_unlock_irq(&chip->reg_lock);
1245 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1248 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1250 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1254 spin_lock_irq(&chip->reg_lock);
1255 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1256 val &= ~ICH_ALI_IF_AC97SP;
1257 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1258 spin_unlock_irq(&chip->reg_lock);
1264 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1266 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1268 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1271 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1273 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1275 chip->ichd[ALID_SPDIFIN].substream = NULL;
1279 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1281 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1283 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1286 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1288 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1295 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1296 .open = snd_intel8x0_playback_open,
1297 .close = snd_intel8x0_playback_close,
1298 .hw_params = snd_intel8x0_hw_params,
1299 .hw_free = snd_intel8x0_hw_free,
1300 .prepare = snd_intel8x0_pcm_prepare,
1301 .trigger = snd_intel8x0_pcm_trigger,
1302 .pointer = snd_intel8x0_pcm_pointer,
1305 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1306 .open = snd_intel8x0_capture_open,
1307 .close = snd_intel8x0_capture_close,
1308 .hw_params = snd_intel8x0_hw_params,
1309 .hw_free = snd_intel8x0_hw_free,
1310 .prepare = snd_intel8x0_pcm_prepare,
1311 .trigger = snd_intel8x0_pcm_trigger,
1312 .pointer = snd_intel8x0_pcm_pointer,
1315 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1316 .open = snd_intel8x0_mic_open,
1317 .close = snd_intel8x0_mic_close,
1318 .hw_params = snd_intel8x0_hw_params,
1319 .hw_free = snd_intel8x0_hw_free,
1320 .prepare = snd_intel8x0_pcm_prepare,
1321 .trigger = snd_intel8x0_pcm_trigger,
1322 .pointer = snd_intel8x0_pcm_pointer,
1325 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1326 .open = snd_intel8x0_mic2_open,
1327 .close = snd_intel8x0_mic2_close,
1328 .hw_params = snd_intel8x0_hw_params,
1329 .hw_free = snd_intel8x0_hw_free,
1330 .prepare = snd_intel8x0_pcm_prepare,
1331 .trigger = snd_intel8x0_pcm_trigger,
1332 .pointer = snd_intel8x0_pcm_pointer,
1335 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1336 .open = snd_intel8x0_capture2_open,
1337 .close = snd_intel8x0_capture2_close,
1338 .hw_params = snd_intel8x0_hw_params,
1339 .hw_free = snd_intel8x0_hw_free,
1340 .prepare = snd_intel8x0_pcm_prepare,
1341 .trigger = snd_intel8x0_pcm_trigger,
1342 .pointer = snd_intel8x0_pcm_pointer,
1345 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1346 .open = snd_intel8x0_spdif_open,
1347 .close = snd_intel8x0_spdif_close,
1348 .hw_params = snd_intel8x0_hw_params,
1349 .hw_free = snd_intel8x0_hw_free,
1350 .prepare = snd_intel8x0_pcm_prepare,
1351 .trigger = snd_intel8x0_pcm_trigger,
1352 .pointer = snd_intel8x0_pcm_pointer,
1355 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1356 .open = snd_intel8x0_playback_open,
1357 .close = snd_intel8x0_playback_close,
1358 .hw_params = snd_intel8x0_hw_params,
1359 .hw_free = snd_intel8x0_hw_free,
1360 .prepare = snd_intel8x0_pcm_prepare,
1361 .trigger = snd_intel8x0_ali_trigger,
1362 .pointer = snd_intel8x0_pcm_pointer,
1365 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1366 .open = snd_intel8x0_capture_open,
1367 .close = snd_intel8x0_capture_close,
1368 .hw_params = snd_intel8x0_hw_params,
1369 .hw_free = snd_intel8x0_hw_free,
1370 .prepare = snd_intel8x0_pcm_prepare,
1371 .trigger = snd_intel8x0_ali_trigger,
1372 .pointer = snd_intel8x0_pcm_pointer,
1375 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1376 .open = snd_intel8x0_mic_open,
1377 .close = snd_intel8x0_mic_close,
1378 .hw_params = snd_intel8x0_hw_params,
1379 .hw_free = snd_intel8x0_hw_free,
1380 .prepare = snd_intel8x0_pcm_prepare,
1381 .trigger = snd_intel8x0_ali_trigger,
1382 .pointer = snd_intel8x0_pcm_pointer,
1385 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1386 .open = snd_intel8x0_ali_ac97spdifout_open,
1387 .close = snd_intel8x0_ali_ac97spdifout_close,
1388 .hw_params = snd_intel8x0_hw_params,
1389 .hw_free = snd_intel8x0_hw_free,
1390 .prepare = snd_intel8x0_pcm_prepare,
1391 .trigger = snd_intel8x0_ali_trigger,
1392 .pointer = snd_intel8x0_pcm_pointer,
1396 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1397 .open = snd_intel8x0_ali_spdifin_open,
1398 .close = snd_intel8x0_ali_spdifin_close,
1399 .hw_params = snd_intel8x0_hw_params,
1400 .hw_free = snd_intel8x0_hw_free,
1401 .prepare = snd_intel8x0_pcm_prepare,
1402 .trigger = snd_intel8x0_pcm_trigger,
1403 .pointer = snd_intel8x0_pcm_pointer,
1406 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1407 .open = snd_intel8x0_ali_spdifout_open,
1408 .close = snd_intel8x0_ali_spdifout_close,
1409 .hw_params = snd_intel8x0_hw_params,
1410 .hw_free = snd_intel8x0_hw_free,
1411 .prepare = snd_intel8x0_pcm_prepare,
1412 .trigger = snd_intel8x0_pcm_trigger,
1413 .pointer = snd_intel8x0_pcm_pointer,
1417 struct ich_pcm_table {
1419 const struct snd_pcm_ops *playback_ops;
1420 const struct snd_pcm_ops *capture_ops;
1421 size_t prealloc_size;
1422 size_t prealloc_max_size;
1426 #define intel8x0_dma_type(chip) \
1427 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1429 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1430 const struct ich_pcm_table *rec)
1432 struct snd_pcm *pcm;
1437 sprintf(name, "Intel ICH - %s", rec->suffix);
1439 strcpy(name, "Intel ICH");
1440 err = snd_pcm_new(chip->card, name, device,
1441 rec->playback_ops ? 1 : 0,
1442 rec->capture_ops ? 1 : 0, &pcm);
1446 if (rec->playback_ops)
1447 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1448 if (rec->capture_ops)
1449 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1451 pcm->private_data = chip;
1452 pcm->info_flags = 0;
1454 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1456 strcpy(pcm->name, chip->card->shortname);
1457 chip->pcm[device] = pcm;
1459 snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1461 rec->prealloc_size, rec->prealloc_max_size);
1463 if (rec->playback_ops &&
1464 rec->playback_ops->open == snd_intel8x0_playback_open) {
1465 struct snd_pcm_chmap *chmap;
1469 else if (chip->multi6)
1471 else if (chip->multi4)
1473 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1474 snd_pcm_alt_chmaps, chs, 0,
1478 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1479 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1485 static const struct ich_pcm_table intel_pcms[] = {
1487 .playback_ops = &snd_intel8x0_playback_ops,
1488 .capture_ops = &snd_intel8x0_capture_ops,
1489 .prealloc_size = 64 * 1024,
1490 .prealloc_max_size = 128 * 1024,
1493 .suffix = "MIC ADC",
1494 .capture_ops = &snd_intel8x0_capture_mic_ops,
1496 .prealloc_max_size = 128 * 1024,
1497 .ac97_idx = ICHD_MIC,
1500 .suffix = "MIC2 ADC",
1501 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1503 .prealloc_max_size = 128 * 1024,
1504 .ac97_idx = ICHD_MIC2,
1508 .capture_ops = &snd_intel8x0_capture2_ops,
1510 .prealloc_max_size = 128 * 1024,
1511 .ac97_idx = ICHD_PCM2IN,
1515 .playback_ops = &snd_intel8x0_spdif_ops,
1516 .prealloc_size = 64 * 1024,
1517 .prealloc_max_size = 128 * 1024,
1518 .ac97_idx = ICHD_SPBAR,
1522 static const struct ich_pcm_table nforce_pcms[] = {
1524 .playback_ops = &snd_intel8x0_playback_ops,
1525 .capture_ops = &snd_intel8x0_capture_ops,
1526 .prealloc_size = 64 * 1024,
1527 .prealloc_max_size = 128 * 1024,
1530 .suffix = "MIC ADC",
1531 .capture_ops = &snd_intel8x0_capture_mic_ops,
1533 .prealloc_max_size = 128 * 1024,
1534 .ac97_idx = NVD_MIC,
1538 .playback_ops = &snd_intel8x0_spdif_ops,
1539 .prealloc_size = 64 * 1024,
1540 .prealloc_max_size = 128 * 1024,
1541 .ac97_idx = NVD_SPBAR,
1545 static const struct ich_pcm_table ali_pcms[] = {
1547 .playback_ops = &snd_intel8x0_ali_playback_ops,
1548 .capture_ops = &snd_intel8x0_ali_capture_ops,
1549 .prealloc_size = 64 * 1024,
1550 .prealloc_max_size = 128 * 1024,
1553 .suffix = "MIC ADC",
1554 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1556 .prealloc_max_size = 128 * 1024,
1557 .ac97_idx = ALID_MIC,
1561 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1562 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1563 .prealloc_size = 64 * 1024,
1564 .prealloc_max_size = 128 * 1024,
1565 .ac97_idx = ALID_AC97SPDIFOUT,
1569 .suffix = "HW IEC958",
1570 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1571 .prealloc_size = 64 * 1024,
1572 .prealloc_max_size = 128 * 1024,
1577 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1579 int i, tblsize, device, err;
1580 const struct ich_pcm_table *tbl, *rec;
1582 switch (chip->device_type) {
1583 case DEVICE_INTEL_ICH4:
1585 tblsize = ARRAY_SIZE(intel_pcms);
1591 tblsize = ARRAY_SIZE(nforce_pcms);
1597 tblsize = ARRAY_SIZE(ali_pcms);
1606 for (i = 0; i < tblsize; i++) {
1608 if (i > 0 && rec->ac97_idx) {
1609 /* activate PCM only when associated AC'97 codec */
1610 if (! chip->ichd[rec->ac97_idx].pcm)
1613 err = snd_intel8x0_pcm1(chip, device, rec);
1619 chip->pcm_devs = device;
1628 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1630 struct intel8x0 *chip = bus->private_data;
1631 chip->ac97_bus = NULL;
1634 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1636 struct intel8x0 *chip = ac97->private_data;
1637 chip->ac97[ac97->num] = NULL;
1640 static const struct ac97_pcm ac97_pcm_defs[] = {
1645 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1646 (1 << AC97_SLOT_PCM_RIGHT) |
1647 (1 << AC97_SLOT_PCM_CENTER) |
1648 (1 << AC97_SLOT_PCM_SLEFT) |
1649 (1 << AC97_SLOT_PCM_SRIGHT) |
1650 (1 << AC97_SLOT_LFE)
1653 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1654 (1 << AC97_SLOT_PCM_RIGHT) |
1655 (1 << AC97_SLOT_PCM_LEFT_0) |
1656 (1 << AC97_SLOT_PCM_RIGHT_0)
1665 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1666 (1 << AC97_SLOT_PCM_RIGHT)
1675 .slots = (1 << AC97_SLOT_MIC)
1684 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1685 (1 << AC97_SLOT_SPDIF_RIGHT2)
1694 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1695 (1 << AC97_SLOT_PCM_RIGHT)
1704 .slots = (1 << AC97_SLOT_MIC)
1710 static const struct ac97_quirk ac97_quirks[] = {
1712 .subvendor = 0x0e11,
1713 .subdevice = 0x000e,
1714 .name = "Compaq Deskpro EN", /* AD1885 */
1715 .type = AC97_TUNE_HP_ONLY
1718 .subvendor = 0x0e11,
1719 .subdevice = 0x008a,
1720 .name = "Compaq Evo W4000", /* AD1885 */
1721 .type = AC97_TUNE_HP_ONLY
1724 .subvendor = 0x0e11,
1725 .subdevice = 0x00b8,
1726 .name = "Compaq Evo D510C",
1727 .type = AC97_TUNE_HP_ONLY
1730 .subvendor = 0x0e11,
1731 .subdevice = 0x0860,
1732 .name = "HP/Compaq nx7010",
1733 .type = AC97_TUNE_MUTE_LED
1736 .subvendor = 0x1014,
1737 .subdevice = 0x0534,
1738 .name = "ThinkPad X31",
1739 .type = AC97_TUNE_INV_EAPD
1742 .subvendor = 0x1014,
1743 .subdevice = 0x1f00,
1745 .type = AC97_TUNE_ALC_JACK
1748 .subvendor = 0x1014,
1749 .subdevice = 0x0267,
1750 .name = "IBM NetVista A30p", /* AD1981B */
1751 .type = AC97_TUNE_HP_ONLY
1754 .subvendor = 0x1025,
1755 .subdevice = 0x0082,
1756 .name = "Acer Travelmate 2310",
1757 .type = AC97_TUNE_HP_ONLY
1760 .subvendor = 0x1025,
1761 .subdevice = 0x0083,
1762 .name = "Acer Aspire 3003LCi",
1763 .type = AC97_TUNE_HP_ONLY
1766 .subvendor = 0x1028,
1767 .subdevice = 0x00d8,
1768 .name = "Dell Precision 530", /* AD1885 */
1769 .type = AC97_TUNE_HP_ONLY
1772 .subvendor = 0x1028,
1773 .subdevice = 0x010d,
1774 .name = "Dell", /* which model? AD1885 */
1775 .type = AC97_TUNE_HP_ONLY
1778 .subvendor = 0x1028,
1779 .subdevice = 0x0126,
1780 .name = "Dell Optiplex GX260", /* AD1981A */
1781 .type = AC97_TUNE_HP_ONLY
1784 .subvendor = 0x1028,
1785 .subdevice = 0x012c,
1786 .name = "Dell Precision 650", /* AD1981A */
1787 .type = AC97_TUNE_HP_ONLY
1790 .subvendor = 0x1028,
1791 .subdevice = 0x012d,
1792 .name = "Dell Precision 450", /* AD1981B*/
1793 .type = AC97_TUNE_HP_ONLY
1796 .subvendor = 0x1028,
1797 .subdevice = 0x0147,
1798 .name = "Dell", /* which model? AD1981B*/
1799 .type = AC97_TUNE_HP_ONLY
1802 .subvendor = 0x1028,
1803 .subdevice = 0x0151,
1804 .name = "Dell Optiplex GX270", /* AD1981B */
1805 .type = AC97_TUNE_HP_ONLY
1808 .subvendor = 0x1028,
1809 .subdevice = 0x014e,
1810 .name = "Dell D800", /* STAC9750/51 */
1811 .type = AC97_TUNE_HP_ONLY
1814 .subvendor = 0x1028,
1815 .subdevice = 0x0163,
1816 .name = "Dell Unknown", /* STAC9750/51 */
1817 .type = AC97_TUNE_HP_ONLY
1820 .subvendor = 0x1028,
1821 .subdevice = 0x016a,
1822 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1823 .type = AC97_TUNE_HP_ONLY
1826 .subvendor = 0x1028,
1827 .subdevice = 0x0182,
1828 .name = "Dell Latitude D610", /* STAC9750/51 */
1829 .type = AC97_TUNE_HP_ONLY
1832 .subvendor = 0x1028,
1833 .subdevice = 0x0186,
1834 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1835 .type = AC97_TUNE_HP_MUTE_LED
1838 .subvendor = 0x1028,
1839 .subdevice = 0x0188,
1840 .name = "Dell Inspiron 6000",
1841 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1844 .subvendor = 0x1028,
1845 .subdevice = 0x0189,
1846 .name = "Dell Inspiron 9300",
1847 .type = AC97_TUNE_HP_MUTE_LED
1850 .subvendor = 0x1028,
1851 .subdevice = 0x0191,
1852 .name = "Dell Inspiron 8600",
1853 .type = AC97_TUNE_HP_ONLY
1856 .subvendor = 0x103c,
1857 .subdevice = 0x006d,
1858 .name = "HP zv5000",
1859 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1861 { /* FIXME: which codec? */
1862 .subvendor = 0x103c,
1863 .subdevice = 0x00c3,
1864 .name = "HP xw6000",
1865 .type = AC97_TUNE_HP_ONLY
1868 .subvendor = 0x103c,
1869 .subdevice = 0x088c,
1870 .name = "HP nc8000",
1871 .type = AC97_TUNE_HP_MUTE_LED
1874 .subvendor = 0x103c,
1875 .subdevice = 0x0890,
1876 .name = "HP nc6000",
1877 .type = AC97_TUNE_MUTE_LED
1880 .subvendor = 0x103c,
1881 .subdevice = 0x129d,
1882 .name = "HP xw8000",
1883 .type = AC97_TUNE_HP_ONLY
1886 .subvendor = 0x103c,
1887 .subdevice = 0x0938,
1888 .name = "HP nc4200",
1889 .type = AC97_TUNE_HP_MUTE_LED
1892 .subvendor = 0x103c,
1893 .subdevice = 0x099c,
1894 .name = "HP nx6110/nc6120",
1895 .type = AC97_TUNE_HP_MUTE_LED
1898 .subvendor = 0x103c,
1899 .subdevice = 0x0944,
1900 .name = "HP nc6220",
1901 .type = AC97_TUNE_HP_MUTE_LED
1904 .subvendor = 0x103c,
1905 .subdevice = 0x0934,
1906 .name = "HP nc8220",
1907 .type = AC97_TUNE_HP_MUTE_LED
1910 .subvendor = 0x103c,
1911 .subdevice = 0x12f1,
1912 .name = "HP xw8200", /* AD1981B*/
1913 .type = AC97_TUNE_HP_ONLY
1916 .subvendor = 0x103c,
1917 .subdevice = 0x12f2,
1918 .name = "HP xw6200",
1919 .type = AC97_TUNE_HP_ONLY
1922 .subvendor = 0x103c,
1923 .subdevice = 0x3008,
1924 .name = "HP xw4200", /* AD1981B*/
1925 .type = AC97_TUNE_HP_ONLY
1928 .subvendor = 0x104d,
1929 .subdevice = 0x8144,
1931 .type = AC97_TUNE_INV_EAPD
1934 .subvendor = 0x104d,
1935 .subdevice = 0x8197,
1936 .name = "Sony S1XP",
1937 .type = AC97_TUNE_INV_EAPD
1940 .subvendor = 0x104d,
1941 .subdevice = 0x81c0,
1942 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1943 .type = AC97_TUNE_INV_EAPD
1946 .subvendor = 0x104d,
1947 .subdevice = 0x81c5,
1948 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1949 .type = AC97_TUNE_INV_EAPD
1952 .subvendor = 0x1043,
1953 .subdevice = 0x80f3,
1954 .name = "ASUS ICH5/AD1985",
1955 .type = AC97_TUNE_AD_SHARING
1958 .subvendor = 0x10cf,
1959 .subdevice = 0x11c3,
1960 .name = "Fujitsu-Siemens E4010",
1961 .type = AC97_TUNE_HP_ONLY
1964 .subvendor = 0x10cf,
1965 .subdevice = 0x1225,
1966 .name = "Fujitsu-Siemens T3010",
1967 .type = AC97_TUNE_HP_ONLY
1970 .subvendor = 0x10cf,
1971 .subdevice = 0x1253,
1972 .name = "Fujitsu S6210", /* STAC9750/51 */
1973 .type = AC97_TUNE_HP_ONLY
1976 .subvendor = 0x10cf,
1977 .subdevice = 0x127d,
1978 .name = "Fujitsu Lifebook P7010",
1979 .type = AC97_TUNE_HP_ONLY
1982 .subvendor = 0x10cf,
1983 .subdevice = 0x127e,
1984 .name = "Fujitsu Lifebook C1211D",
1985 .type = AC97_TUNE_HP_ONLY
1988 .subvendor = 0x10cf,
1989 .subdevice = 0x12ec,
1990 .name = "Fujitsu-Siemens 4010",
1991 .type = AC97_TUNE_HP_ONLY
1994 .subvendor = 0x10cf,
1995 .subdevice = 0x12f2,
1996 .name = "Fujitsu-Siemens Celsius H320",
1997 .type = AC97_TUNE_SWAP_HP
2000 .subvendor = 0x10f1,
2001 .subdevice = 0x2665,
2002 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2003 .type = AC97_TUNE_HP_ONLY
2006 .subvendor = 0x10f1,
2007 .subdevice = 0x2885,
2008 .name = "AMD64 Mobo", /* ALC650 */
2009 .type = AC97_TUNE_HP_ONLY
2012 .subvendor = 0x10f1,
2013 .subdevice = 0x2895,
2014 .name = "Tyan Thunder K8WE",
2015 .type = AC97_TUNE_HP_ONLY
2018 .subvendor = 0x10f7,
2019 .subdevice = 0x834c,
2020 .name = "Panasonic CF-R4",
2021 .type = AC97_TUNE_HP_ONLY,
2024 .subvendor = 0x110a,
2025 .subdevice = 0x0056,
2026 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2027 .type = AC97_TUNE_HP_ONLY
2030 .subvendor = 0x11d4,
2031 .subdevice = 0x5375,
2032 .name = "ADI AD1985 (discrete)",
2033 .type = AC97_TUNE_HP_ONLY
2036 .subvendor = 0x1462,
2037 .subdevice = 0x5470,
2038 .name = "MSI P4 ATX 645 Ultra",
2039 .type = AC97_TUNE_HP_ONLY
2042 .subvendor = 0x161f,
2043 .subdevice = 0x202f,
2044 .name = "Gateway M520",
2045 .type = AC97_TUNE_INV_EAPD
2048 .subvendor = 0x161f,
2049 .subdevice = 0x203a,
2050 .name = "Gateway 4525GZ", /* AD1981B */
2051 .type = AC97_TUNE_INV_EAPD
2054 .subvendor = 0x1734,
2055 .subdevice = 0x0088,
2056 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2057 .type = AC97_TUNE_HP_ONLY
2060 .subvendor = 0x8086,
2061 .subdevice = 0x2000,
2063 .name = "Intel ICH5/AD1985",
2064 .type = AC97_TUNE_AD_SHARING
2067 .subvendor = 0x8086,
2068 .subdevice = 0x4000,
2070 .name = "Intel ICH5/AD1985",
2071 .type = AC97_TUNE_AD_SHARING
2074 .subvendor = 0x8086,
2075 .subdevice = 0x4856,
2076 .name = "Intel D845WN (82801BA)",
2077 .type = AC97_TUNE_SWAP_HP
2080 .subvendor = 0x8086,
2081 .subdevice = 0x4d44,
2082 .name = "Intel D850EMV2", /* AD1885 */
2083 .type = AC97_TUNE_HP_ONLY
2086 .subvendor = 0x8086,
2087 .subdevice = 0x4d56,
2088 .name = "Intel ICH/AD1885",
2089 .type = AC97_TUNE_HP_ONLY
2092 .subvendor = 0x8086,
2093 .subdevice = 0x6000,
2095 .name = "Intel ICH5/AD1985",
2096 .type = AC97_TUNE_AD_SHARING
2099 .subvendor = 0x8086,
2100 .subdevice = 0xe000,
2102 .name = "Intel ICH5/AD1985",
2103 .type = AC97_TUNE_AD_SHARING
2105 #if 0 /* FIXME: this seems wrong on most boards */
2107 .subvendor = 0x8086,
2108 .subdevice = 0xa000,
2110 .name = "Intel ICH5/AD1985",
2111 .type = AC97_TUNE_HP_ONLY
2114 { } /* terminator */
2117 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2118 const char *quirk_override)
2120 struct snd_ac97_bus *pbus;
2121 struct snd_ac97_template ac97;
2123 unsigned int i, codecs;
2124 unsigned int glob_sta = 0;
2125 const struct snd_ac97_bus_ops *ops;
2126 static const struct snd_ac97_bus_ops standard_bus_ops = {
2127 .write = snd_intel8x0_codec_write,
2128 .read = snd_intel8x0_codec_read,
2130 static const struct snd_ac97_bus_ops ali_bus_ops = {
2131 .write = snd_intel8x0_ali_codec_write,
2132 .read = snd_intel8x0_ali_codec_read,
2135 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2136 if (!spdif_aclink) {
2137 switch (chip->device_type) {
2139 chip->spdif_idx = NVD_SPBAR;
2142 chip->spdif_idx = ALID_AC97SPDIFOUT;
2144 case DEVICE_INTEL_ICH4:
2145 chip->spdif_idx = ICHD_SPBAR;
2150 chip->in_ac97_init = 1;
2152 memset(&ac97, 0, sizeof(ac97));
2153 ac97.private_data = chip;
2154 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2155 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2157 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2158 if (chip->device_type != DEVICE_ALI) {
2159 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2160 ops = &standard_bus_ops;
2161 chip->in_sdin_init = 1;
2163 for (i = 0; i < chip->max_codecs; i++) {
2164 if (! (glob_sta & chip->codec_bit[i]))
2166 if (chip->device_type == DEVICE_INTEL_ICH4) {
2167 snd_intel8x0_codec_read_test(chip, codecs);
2168 chip->ac97_sdin[codecs] =
2169 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2170 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2171 chip->ac97_sdin[codecs] = 0;
2173 chip->ac97_sdin[codecs] = i;
2176 chip->in_sdin_init = 0;
2182 /* detect the secondary codec */
2183 for (i = 0; i < 100; i++) {
2184 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2189 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2193 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2195 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2196 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2197 pbus->clock = ac97_clock;
2198 /* FIXME: my test board doesn't work well with VRA... */
2199 if (chip->device_type == DEVICE_ALI)
2203 chip->ac97_bus = pbus;
2204 chip->ncodecs = codecs;
2206 ac97.pci = chip->pci;
2207 for (i = 0; i < codecs; i++) {
2209 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2211 dev_err(chip->card->dev,
2212 "Unable to initialize codec #%d\n", i);
2217 /* tune up the primary codec */
2218 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2219 /* enable separate SDINs for ICH4 */
2220 if (chip->device_type == DEVICE_INTEL_ICH4)
2222 /* find the available PCM streams */
2223 i = ARRAY_SIZE(ac97_pcm_defs);
2224 if (chip->device_type != DEVICE_INTEL_ICH4)
2225 i -= 2; /* do not allocate PCM2IN and MIC2 */
2226 if (chip->spdif_idx < 0)
2227 i--; /* do not allocate S/PDIF */
2228 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2231 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2232 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2233 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2234 if (chip->spdif_idx >= 0)
2235 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2236 if (chip->device_type == DEVICE_INTEL_ICH4) {
2237 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2238 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2240 /* enable separate SDINs for ICH4 */
2241 if (chip->device_type == DEVICE_INTEL_ICH4) {
2242 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2243 u8 tmp = igetbyte(chip, ICHREG(SDM));
2244 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2246 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2247 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2248 for (i = 1; i < 4; i++) {
2249 if (pcm->r[0].codec[i]) {
2250 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2255 tmp &= ~ICH_SE; /* steer disable */
2257 iputbyte(chip, ICHREG(SDM), tmp);
2259 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2261 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2263 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2267 if (pbus->pcms[0].r[1].rslots[0]) {
2270 if (chip->device_type == DEVICE_INTEL_ICH4) {
2271 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2274 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2276 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2278 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2279 /* use slot 10/11 for SPDIF */
2281 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2282 val |= ICH_PCM_SPDIF_1011;
2283 iputdword(chip, ICHREG(GLOB_CNT), val);
2284 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2286 chip->in_ac97_init = 0;
2290 /* clear the cold-reset bit for the next chance */
2291 if (chip->device_type != DEVICE_ALI)
2292 iputdword(chip, ICHREG(GLOB_CNT),
2293 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2302 static void do_ali_reset(struct intel8x0 *chip)
2304 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2305 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2306 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2307 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2308 iputdword(chip, ICHREG(ALI_INTERFACECR),
2309 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2310 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2311 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2314 #ifdef CONFIG_SND_AC97_POWER_SAVE
2315 static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2316 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2320 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2323 /* ACLink on, 2 channels */
2325 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2328 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2329 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2331 /* do cold reset - the full ac97 powerdown may leave the controller
2332 * in a warm state but actually it cannot communicate with the codec.
2334 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2335 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2337 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2341 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2342 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2344 #define snd_intel8x0_ich_chip_cold_reset(chip) 0
2345 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2348 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2350 unsigned long end_time;
2352 /* ACLink on, 2 channels */
2353 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2354 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2355 /* finish cold or do warm reset */
2356 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2357 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2358 end_time = (jiffies + (HZ / 4)) + 1;
2360 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2362 schedule_timeout_uninterruptible(1);
2363 } while (time_after_eq(end_time, jiffies));
2364 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2365 igetdword(chip, ICHREG(GLOB_CNT)));
2369 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2371 unsigned long end_time;
2372 unsigned int status, nstatus;
2376 /* put logic to right state */
2377 /* first clear status bits */
2378 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2379 if (chip->device_type == DEVICE_NFORCE)
2380 status |= ICH_NVSPINT;
2381 cnt = igetdword(chip, ICHREG(GLOB_STA));
2382 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2384 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2385 err = snd_intel8x0_ich_chip_cold_reset(chip);
2387 err = snd_intel8x0_ich_chip_reset(chip);
2392 /* wait for any codec ready status.
2393 * Once it becomes ready it should remain ready
2394 * as long as we do not disable the ac97 link.
2396 end_time = jiffies + HZ;
2398 status = igetdword(chip, ICHREG(GLOB_STA)) &
2399 chip->codec_isr_bits;
2402 schedule_timeout_uninterruptible(1);
2403 } while (time_after_eq(end_time, jiffies));
2405 /* no codec is found */
2406 dev_err(chip->card->dev,
2407 "codec_ready: codec is not ready [0x%x]\n",
2408 igetdword(chip, ICHREG(GLOB_STA)));
2412 /* wait for other codecs ready status. */
2413 end_time = jiffies + HZ / 4;
2414 while (status != chip->codec_isr_bits &&
2415 time_after_eq(end_time, jiffies)) {
2416 schedule_timeout_uninterruptible(1);
2417 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2418 chip->codec_isr_bits;
2425 for (i = 0; i < chip->ncodecs; i++)
2427 status |= chip->codec_bit[chip->ac97_sdin[i]];
2428 /* wait until all the probed codecs are ready */
2429 end_time = jiffies + HZ;
2431 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2432 chip->codec_isr_bits;
2433 if (status == nstatus)
2435 schedule_timeout_uninterruptible(1);
2436 } while (time_after_eq(end_time, jiffies));
2439 if (chip->device_type == DEVICE_SIS) {
2440 /* unmute the output on SIS7012 */
2441 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2443 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2444 /* enable SPDIF interrupt */
2446 pci_read_config_dword(chip->pci, 0x4c, &val);
2448 pci_write_config_dword(chip->pci, 0x4c, val);
2453 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2458 reg = igetdword(chip, ICHREG(ALI_SCR));
2459 if ((reg & 2) == 0) /* Cold required */
2462 reg |= 1; /* Warm */
2463 reg &= ~0x80000000; /* ACLink on */
2464 iputdword(chip, ICHREG(ALI_SCR), reg);
2466 for (i = 0; i < HZ / 2; i++) {
2467 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2469 schedule_timeout_uninterruptible(1);
2471 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2476 for (i = 0; i < HZ / 2; i++) {
2477 reg = igetdword(chip, ICHREG(ALI_RTSR));
2478 if (reg & 0x80) /* primary codec */
2480 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2481 schedule_timeout_uninterruptible(1);
2488 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2490 unsigned int i, timeout;
2493 if (chip->device_type != DEVICE_ALI) {
2494 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2496 iagetword(chip, 0); /* clear semaphore flag */
2498 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2502 /* disable interrupts */
2503 for (i = 0; i < chip->bdbars_count; i++)
2504 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2505 /* reset channels */
2506 for (i = 0; i < chip->bdbars_count; i++)
2507 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2508 for (i = 0; i < chip->bdbars_count; i++) {
2510 while (--timeout != 0) {
2511 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2515 dev_err(chip->card->dev, "reset of registers failed?\n");
2517 /* initialize Buffer Descriptor Lists */
2518 for (i = 0; i < chip->bdbars_count; i++)
2519 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2520 chip->ichd[i].bdbar_addr);
2524 static int snd_intel8x0_free(struct intel8x0 *chip)
2530 /* disable interrupts */
2531 for (i = 0; i < chip->bdbars_count; i++)
2532 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2533 /* reset channels */
2534 for (i = 0; i < chip->bdbars_count; i++)
2535 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2536 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2537 /* stop the spdif interrupt */
2539 pci_read_config_dword(chip->pci, 0x4c, &val);
2541 pci_write_config_dword(chip->pci, 0x4c, val);
2547 free_irq(chip->irq, chip);
2548 if (chip->bdbars.area)
2549 snd_dma_free_pages(&chip->bdbars);
2551 pci_iounmap(chip->pci, chip->addr);
2553 pci_iounmap(chip->pci, chip->bmaddr);
2554 pci_release_regions(chip->pci);
2555 pci_disable_device(chip->pci);
2560 #ifdef CONFIG_PM_SLEEP
2564 static int intel8x0_suspend(struct device *dev)
2566 struct snd_card *card = dev_get_drvdata(dev);
2567 struct intel8x0 *chip = card->private_data;
2570 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2571 for (i = 0; i < chip->ncodecs; i++)
2572 snd_ac97_suspend(chip->ac97[i]);
2573 if (chip->device_type == DEVICE_INTEL_ICH4)
2574 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2576 if (chip->irq >= 0) {
2577 free_irq(chip->irq, chip);
2579 card->sync_irq = -1;
2584 static int intel8x0_resume(struct device *dev)
2586 struct pci_dev *pci = to_pci_dev(dev);
2587 struct snd_card *card = dev_get_drvdata(dev);
2588 struct intel8x0 *chip = card->private_data;
2591 snd_intel8x0_chip_init(chip, 0);
2592 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2593 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2594 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2596 snd_card_disconnect(card);
2599 chip->irq = pci->irq;
2600 card->sync_irq = chip->irq;
2602 /* re-initialize mixer stuff */
2603 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2604 /* enable separate SDINs for ICH4 */
2605 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2606 /* use slot 10/11 for SPDIF */
2607 iputdword(chip, ICHREG(GLOB_CNT),
2608 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2609 ICH_PCM_SPDIF_1011);
2612 for (i = 0; i < chip->ncodecs; i++)
2613 snd_ac97_resume(chip->ac97[i]);
2616 for (i = 0; i < chip->bdbars_count; i++) {
2617 struct ichdev *ichdev = &chip->ichd[i];
2618 unsigned long port = ichdev->reg_offset;
2619 if (! ichdev->substream || ! ichdev->suspended)
2621 if (ichdev->ichd == ICHD_PCMOUT)
2622 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2623 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2624 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2625 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2626 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2629 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2633 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2634 #define INTEL8X0_PM_OPS &intel8x0_pm
2636 #define INTEL8X0_PM_OPS NULL
2637 #endif /* CONFIG_PM_SLEEP */
2639 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2641 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2643 struct snd_pcm_substream *subs;
2644 struct ichdev *ichdev;
2646 unsigned long pos, pos1, t;
2647 int civ, timeout = 1000, attempt = 1;
2648 ktime_t start_time, stop_time;
2650 if (chip->ac97_bus->clock != 48000)
2651 return; /* specified in module option */
2654 subs = chip->pcm[0]->streams[0].substream;
2655 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2656 dev_warn(chip->card->dev,
2657 "no playback buffer allocated - aborting measure ac97 clock\n");
2660 ichdev = &chip->ichd[ICHD_PCMOUT];
2661 ichdev->physbuf = subs->dma_buffer.addr;
2662 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2663 ichdev->substream = NULL; /* don't process interrupts */
2666 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2667 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2668 chip->ac97_bus->clock);
2671 snd_intel8x0_setup_periods(chip, ichdev);
2672 port = ichdev->reg_offset;
2673 spin_lock_irq(&chip->reg_lock);
2674 chip->in_measurement = 1;
2676 if (chip->device_type != DEVICE_ALI)
2677 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2679 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2680 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2682 start_time = ktime_get();
2683 spin_unlock_irq(&chip->reg_lock);
2685 spin_lock_irq(&chip->reg_lock);
2686 /* check the position */
2688 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2689 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2694 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2695 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2697 } while (timeout--);
2698 if (pos1 == 0) { /* oops, this value is not reliable */
2701 pos = ichdev->fragsize1;
2702 pos -= pos1 << ichdev->pos_shift;
2703 pos += ichdev->position;
2705 chip->in_measurement = 0;
2706 stop_time = ktime_get();
2708 if (chip->device_type == DEVICE_ALI) {
2709 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2710 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2711 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2714 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2715 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2718 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2719 spin_unlock_irq(&chip->reg_lock);
2722 dev_err(chip->card->dev,
2723 "measure - unreliable DMA position..\n");
2734 t = ktime_us_delta(stop_time, start_time);
2735 dev_info(chip->card->dev,
2736 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2738 dev_err(chip->card->dev, "?? calculation error..\n");
2742 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2743 if (pos < 40000 || pos >= 60000) {
2744 /* abnormal value. hw problem? */
2745 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2747 } else if (pos > 40500 && pos < 41500)
2748 /* first exception - 41000Hz reference clock */
2749 chip->ac97_bus->clock = 41000;
2750 else if (pos > 43600 && pos < 44600)
2751 /* second exception - 44100HZ reference clock */
2752 chip->ac97_bus->clock = 44100;
2753 else if (pos < 47500 || pos > 48500)
2754 /* not 48000Hz, tuning the clock.. */
2755 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2757 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2758 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2761 static const struct snd_pci_quirk intel8x0_clock_list[] = {
2762 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2763 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2764 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2765 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2766 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2767 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2768 { } /* terminator */
2771 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2773 struct pci_dev *pci = chip->pci;
2774 const struct snd_pci_quirk *wl;
2776 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2779 dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2780 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2781 chip->ac97_bus->clock = wl->value;
2785 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2786 struct snd_info_buffer *buffer)
2788 struct intel8x0 *chip = entry->private_data;
2791 snd_iprintf(buffer, "Intel8x0\n\n");
2792 if (chip->device_type == DEVICE_ALI)
2794 tmp = igetdword(chip, ICHREG(GLOB_STA));
2795 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2796 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2797 if (chip->device_type == DEVICE_INTEL_ICH4)
2798 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2799 snd_iprintf(buffer, "AC'97 codecs ready :");
2800 if (tmp & chip->codec_isr_bits) {
2802 static const char *codecs[3] = {
2803 "primary", "secondary", "tertiary"
2805 for (i = 0; i < chip->max_codecs; i++)
2806 if (tmp & chip->codec_bit[i])
2807 snd_iprintf(buffer, " %s", codecs[i]);
2809 snd_iprintf(buffer, " none");
2810 snd_iprintf(buffer, "\n");
2811 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2812 chip->device_type == DEVICE_SIS)
2813 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2816 chip->ac97_sdin[2]);
2819 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2821 snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2822 snd_intel8x0_proc_read);
2825 static int snd_intel8x0_dev_free(struct snd_device *device)
2827 struct intel8x0 *chip = device->device_data;
2828 return snd_intel8x0_free(chip);
2831 struct ich_reg_info {
2832 unsigned int int_sta_mask;
2833 unsigned int offset;
2836 static const unsigned int ich_codec_bits[3] = {
2837 ICH_PCR, ICH_SCR, ICH_TCR
2839 static const unsigned int sis_codec_bits[3] = {
2840 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2843 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2845 int result = inside_vm;
2848 /* check module parameter first (override detection) */
2850 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2854 /* check for known (emulated) devices */
2856 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2857 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2858 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2861 } else if (pci->subsystem_vendor == 0x1ab8) {
2862 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2863 msg = "enable Parallels VM";
2869 dev_info(&pci->dev, "%s optimization\n", msg);
2874 static int snd_intel8x0_create(struct snd_card *card,
2875 struct pci_dev *pci,
2876 unsigned long device_type,
2877 struct intel8x0 **r_intel8x0)
2879 struct intel8x0 *chip;
2882 unsigned int int_sta_masks;
2883 struct ichdev *ichdev;
2884 static const struct snd_device_ops ops = {
2885 .dev_free = snd_intel8x0_dev_free,
2888 static const unsigned int bdbars[] = {
2889 3, /* DEVICE_INTEL */
2890 6, /* DEVICE_INTEL_ICH4 */
2893 4, /* DEVICE_NFORCE */
2895 static const struct ich_reg_info intel_regs[6] = {
2897 { ICH_POINT, 0x10 },
2898 { ICH_MCINT, 0x20 },
2899 { ICH_M2INT, 0x40 },
2900 { ICH_P2INT, 0x50 },
2901 { ICH_SPINT, 0x60 },
2903 static const struct ich_reg_info nforce_regs[4] = {
2905 { ICH_POINT, 0x10 },
2906 { ICH_MCINT, 0x20 },
2907 { ICH_NVSPINT, 0x70 },
2909 static const struct ich_reg_info ali_regs[6] = {
2910 { ALI_INT_PCMIN, 0x40 },
2911 { ALI_INT_PCMOUT, 0x50 },
2912 { ALI_INT_MICIN, 0x60 },
2913 { ALI_INT_CODECSPDIFOUT, 0x70 },
2914 { ALI_INT_SPDIFIN, 0xa0 },
2915 { ALI_INT_SPDIFOUT, 0xb0 },
2917 const struct ich_reg_info *tbl;
2921 if ((err = pci_enable_device(pci)) < 0)
2924 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2926 pci_disable_device(pci);
2929 spin_lock_init(&chip->reg_lock);
2930 chip->device_type = device_type;
2935 /* module parameters */
2936 chip->buggy_irq = buggy_irq;
2937 chip->buggy_semaphore = buggy_semaphore;
2941 chip->inside_vm = snd_intel8x0_inside_vm(pci);
2944 * Intel 82443MX running a 100MHz processor system bus has a hardware
2945 * bug, which aborts PCI busmaster for audio transfer. A workaround
2946 * is to set the pages as non-cached. For details, see the errata in
2947 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2949 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2950 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2951 chip->fix_nocache = 1; /* enable workaround */
2953 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2955 pci_disable_device(pci);
2959 if (device_type == DEVICE_ALI) {
2960 /* ALI5455 has no ac97 region */
2961 chip->bmaddr = pci_iomap(pci, 0, 0);
2965 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2966 chip->addr = pci_iomap(pci, 2, 0);
2968 chip->addr = pci_iomap(pci, 0, 0);
2970 dev_err(card->dev, "AC'97 space ioremap problem\n");
2971 snd_intel8x0_free(chip);
2974 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2975 chip->bmaddr = pci_iomap(pci, 3, 0);
2977 chip->bmaddr = pci_iomap(pci, 1, 0);
2980 if (!chip->bmaddr) {
2981 dev_err(card->dev, "Controller space ioremap problem\n");
2982 snd_intel8x0_free(chip);
2985 chip->bdbars_count = bdbars[device_type];
2987 /* initialize offsets */
2988 switch (device_type) {
2999 for (i = 0; i < chip->bdbars_count; i++) {
3000 ichdev = &chip->ichd[i];
3002 ichdev->reg_offset = tbl[i].offset;
3003 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3004 if (device_type == DEVICE_SIS) {
3005 /* SiS 7012 swaps the registers */
3006 ichdev->roff_sr = ICH_REG_OFF_PICB;
3007 ichdev->roff_picb = ICH_REG_OFF_SR;
3009 ichdev->roff_sr = ICH_REG_OFF_SR;
3010 ichdev->roff_picb = ICH_REG_OFF_PICB;
3012 if (device_type == DEVICE_ALI)
3013 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3014 /* SIS7012 handles the pcm data in bytes, others are in samples */
3015 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3018 /* allocate buffer descriptor lists */
3019 /* the start of each lists must be aligned to 8 bytes */
3020 if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
3021 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3022 &chip->bdbars) < 0) {
3023 snd_intel8x0_free(chip);
3024 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3027 /* tables must be aligned to 8 bytes here, but the kernel pages
3028 are much bigger, so we don't care (on i386) */
3030 for (i = 0; i < chip->bdbars_count; i++) {
3031 ichdev = &chip->ichd[i];
3032 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3033 (i * ICH_MAX_FRAGS * 2);
3034 ichdev->bdbar_addr = chip->bdbars.addr +
3035 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3036 int_sta_masks |= ichdev->int_sta_mask;
3038 chip->int_sta_reg = device_type == DEVICE_ALI ?
3039 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3040 chip->int_sta_mask = int_sta_masks;
3042 pci_set_master(pci);
3044 switch(chip->device_type) {
3045 case DEVICE_INTEL_ICH4:
3046 /* ICH4 can have three codecs */
3047 chip->max_codecs = 3;
3048 chip->codec_bit = ich_codec_bits;
3049 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3052 /* recent SIS7012 can have three codecs */
3053 chip->max_codecs = 3;
3054 chip->codec_bit = sis_codec_bits;
3055 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3058 /* others up to two codecs */
3059 chip->max_codecs = 2;
3060 chip->codec_bit = ich_codec_bits;
3061 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3064 for (i = 0; i < chip->max_codecs; i++)
3065 chip->codec_isr_bits |= chip->codec_bit[i];
3067 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3068 snd_intel8x0_free(chip);
3072 /* request irq after initializaing int_sta_mask, etc */
3073 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3074 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3075 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3076 snd_intel8x0_free(chip);
3079 chip->irq = pci->irq;
3080 card->sync_irq = chip->irq;
3082 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3083 snd_intel8x0_free(chip);
3091 static struct shortname_table {
3095 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3096 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3097 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3098 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3099 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3100 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3101 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3102 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3103 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3104 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3105 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3106 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3107 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3108 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3109 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3110 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3111 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3112 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3113 { 0x003a, "NVidia MCP04" },
3114 { 0x746d, "AMD AMD8111" },
3115 { 0x7445, "AMD AMD768" },
3116 { 0x5455, "ALi M5455" },
3120 static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3121 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3125 /* look up allow/deny list for SPDIF over ac-link */
3126 static int check_default_spdif_aclink(struct pci_dev *pci)
3128 const struct snd_pci_quirk *w;
3130 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3134 "Using SPDIF over AC-Link for %s\n",
3135 snd_pci_quirk_name(w));
3138 "Using integrated SPDIF DMA for %s\n",
3139 snd_pci_quirk_name(w));
3145 static int snd_intel8x0_probe(struct pci_dev *pci,
3146 const struct pci_device_id *pci_id)
3148 struct snd_card *card;
3149 struct intel8x0 *chip;
3151 struct shortname_table *name;
3153 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3157 if (spdif_aclink < 0)
3158 spdif_aclink = check_default_spdif_aclink(pci);
3160 strcpy(card->driver, "ICH");
3161 if (!spdif_aclink) {
3162 switch (pci_id->driver_data) {
3164 strcpy(card->driver, "NFORCE");
3166 case DEVICE_INTEL_ICH4:
3167 strcpy(card->driver, "ICH4");
3171 strcpy(card->shortname, "Intel ICH");
3172 for (name = shortnames; name->id; name++) {
3173 if (pci->device == name->id) {
3174 strcpy(card->shortname, name->s);
3179 if (buggy_irq < 0) {
3180 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3181 * Needs to return IRQ_HANDLED for unknown irqs.
3183 if (pci_id->driver_data == DEVICE_NFORCE)
3189 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3191 snd_card_free(card);
3194 card->private_data = chip;
3196 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3197 snd_card_free(card);
3200 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3201 snd_card_free(card);
3205 snd_intel8x0_proc_init(chip);
3207 snprintf(card->longname, sizeof(card->longname),
3208 "%s with %s at irq %i", card->shortname,
3209 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3211 if (ac97_clock == 0 || ac97_clock == 1) {
3212 if (ac97_clock == 0) {
3213 if (intel8x0_in_clock_list(chip) == 0)
3214 intel8x0_measure_ac97_clock(chip);
3216 intel8x0_measure_ac97_clock(chip);
3220 if ((err = snd_card_register(card)) < 0) {
3221 snd_card_free(card);
3224 pci_set_drvdata(pci, card);
3228 static void snd_intel8x0_remove(struct pci_dev *pci)
3230 snd_card_free(pci_get_drvdata(pci));
3233 static struct pci_driver intel8x0_driver = {
3234 .name = KBUILD_MODNAME,
3235 .id_table = snd_intel8x0_ids,
3236 .probe = snd_intel8x0_probe,
3237 .remove = snd_intel8x0_remove,
3239 .pm = INTEL8X0_PM_OPS,
3243 module_pci_driver(intel8x0_driver);