2 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
4 * Lowlevel functions for Infrasonic Quartet
6 * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/slab.h>
29 #include <linux/string.h>
30 #include <sound/core.h>
31 #include <sound/tlv.h>
32 #include <sound/info.h>
36 #include <sound/ak4113.h>
40 struct ak4113 *ak4113;
41 unsigned int scr; /* system control register */
42 unsigned int mcr; /* monitoring control register */
43 unsigned int cpld; /* cpld register */
46 struct qtet_kcontrol_private {
48 void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
49 unsigned int (*get_register)(struct snd_ice1712 *ice);
50 const char * const texts[2];
66 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
69 /* chip address on I2C bus */
70 #define AK4113_ADDR 0x26 /* S/PDIF receiver */
72 /* chip address on SPI bus */
73 #define AK4620_ADDR 0x02 /* ADC/DAC */
80 /* GPIO0 - O - DATA0, def. 0 */
81 #define GPIO_D0 (1<<0)
82 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
83 #define GPIO_D1_JACKDTC0 (1<<1)
84 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
85 #define GPIO_D2_JACKDTC1 (1<<2)
86 /* GPIO3 - I/O - DATA3, def. 1 */
87 #define GPIO_D3 (1<<3)
88 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
89 #define GPIO_D4_SPI_CDTO (1<<4)
90 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
91 #define GPIO_D5_SPI_CCLK (1<<5)
92 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
93 #define GPIO_D6_CD (1<<6)
94 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
95 #define GPIO_D7_DD (1<<7)
96 /* GPIO8 - O - CPLD Chip Select, def. 1 */
97 #define GPIO_CPLD_CSN (1<<8)
98 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
99 #define GPIO_CPLD_RW (1<<9)
100 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
101 #define GPIO_SPI_CSN0 (1<<10)
102 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
103 #define GPIO_SPI_CSN1 (1<<11)
104 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
106 #define GPIO_EX_GPIOE (1<<12)
107 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
109 #define GPIO_SCR (1<<13)
110 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
112 #define GPIO_MCR (1<<14)
114 #define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
115 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
117 #define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
118 GPIO_D2_JACKDTC1 | GPIO_D3 | \
119 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
120 GPIO_D6_CD | GPIO_D7_DD)
122 /* System Control Register GPIO_SCR data bits */
123 /* Mic/Line select relay (0:line, 1:mic) */
124 #define SCR_RELAY GPIO_D0
125 /* Phantom power drive control (0:5V, 1:48V) */
126 #define SCR_PHP_V GPIO_D1_JACKDTC0
127 /* H/W mute control (0:Normal, 1:Mute) */
128 #define SCR_MUTE GPIO_D2_JACKDTC1
129 /* Phantom power control (0:Phantom on, 1:off) */
130 #define SCR_PHP GPIO_D3
131 /* Analog input 1/2 Source Select */
132 #define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
133 #define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
134 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
135 #define SCR_AIN34_SEL GPIO_D6_CD
136 /* Codec Power Down (0:power down, 1:normal) */
137 #define SCR_CODEC_PDN GPIO_D7_DD
139 #define SCR_AIN12_LINE (0)
140 #define SCR_AIN12_MIC (SCR_AIN12_SEL0)
141 #define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
143 /* Monitor Control Register GPIO_MCR data bits */
144 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
145 #define MCR_IN12_MON12 GPIO_D0
146 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
147 #define MCR_IN12_MON34 GPIO_D1_JACKDTC0
148 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
149 #define MCR_IN34_MON12 GPIO_D2_JACKDTC1
150 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
151 #define MCR_IN34_MON34 GPIO_D3
152 /* Output to Monitor 1/2 (0:off, 1:on) */
153 #define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
154 /* Output to Monitor 3/4 (0:off, 1:on) */
155 #define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
157 /* CPLD Register DATA bits */
158 /* Clock Rate Select */
159 #define CPLD_CKS0 GPIO_D0
160 #define CPLD_CKS1 GPIO_D1_JACKDTC0
161 #define CPLD_CKS2 GPIO_D2_JACKDTC1
162 /* Sync Source Select (0:Internal, 1:External) */
163 #define CPLD_SYNC_SEL GPIO_D3
164 /* Word Clock FS Select (0:FS, 1:256FS) */
165 #define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
166 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
167 #define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
168 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
169 #define CPLD_IN12_SEL GPIO_D6_CD
170 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
171 #define CPLD_IN34_SEL GPIO_D7_DD
173 /* internal clock (CPLD_SYNC_SEL = 0) options */
174 #define CPLD_CKS_44100HZ (0)
175 #define CPLD_CKS_48000HZ (CPLD_CKS0)
176 #define CPLD_CKS_88200HZ (CPLD_CKS1)
177 #define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
178 #define CPLD_CKS_176400HZ (CPLD_CKS2)
179 #define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
181 #define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
183 /* external clock (CPLD_SYNC_SEL = 1) options */
184 /* external clock - SPDIF */
185 #define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
186 /* external clock - WordClock 1xfs */
187 #define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
188 /* external clock - WordClock 256xfs */
189 #define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
192 #define EXT_SPDIF_TYPE 0
193 #define EXT_WORDCLOCK_1FS_TYPE 1
194 #define EXT_WORDCLOCK_256FS_TYPE 2
196 #define AK4620_DFS0 (1<<0)
197 #define AK4620_DFS1 (1<<1)
198 #define AK4620_CKS0 (1<<2)
199 #define AK4620_CKS1 (1<<3)
200 /* Clock and Format Control register */
201 #define AK4620_DFS_REG 0x02
203 /* Deem and Volume Control register */
204 #define AK4620_DEEMVOL_REG 0x03
205 #define AK4620_SMUTE (1<<7)
208 * Conversion from int value to its binary form. Used for debugging.
209 * The output buffer must be allocated prior to calling the function.
211 static char *get_binary(char *buffer, int value)
215 for (i = 0; i < 4; ++i) {
216 for (j = 0; j < 8; ++j) {
217 if (value & (1 << (31-(i*8 + j))))
233 * Initial setup of the conversion array GPIO <-> rate
235 static const unsigned int qtet_rates[] = {
237 96000, 176400, 192000,
240 static const unsigned int cks_vals[] = {
241 CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
242 CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
245 static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
246 .count = ARRAY_SIZE(qtet_rates),
251 static void qtet_ak4113_write(void *private_data, unsigned char reg,
254 snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
258 static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
260 return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
270 * Write data to addr register of ak4620
272 static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
273 unsigned char addr, unsigned char data)
275 unsigned int tmp, orig_dir;
277 unsigned int addrdata;
278 struct snd_ice1712 *ice = ak->private_data[0];
280 if (snd_BUG_ON(chip < 0 || chip >= 4))
282 /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
283 data=0x%x\n", chip, addr, data);*/
284 orig_dir = ice->gpio.get_dir(ice);
285 ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
286 /* set mask - only SPI bits */
287 ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
289 tmp = ice->gpio.get_data(ice);
292 ice->gpio.set_data(ice, tmp);
294 /* drop chip select */
297 tmp &= ~GPIO_SPI_CSN1;
299 tmp &= ~GPIO_SPI_CSN0;
300 ice->gpio.set_data(ice, tmp);
303 /* build I2C address + data byte */
304 addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
305 addrdata = (addrdata << 8) | data;
306 for (idx = 15; idx >= 0; idx--) {
308 tmp &= ~GPIO_D5_SPI_CCLK;
309 ice->gpio.set_data(ice, tmp);
312 if (addrdata & (1 << idx))
313 tmp |= GPIO_D4_SPI_CDTO;
315 tmp &= ~GPIO_D4_SPI_CDTO;
316 ice->gpio.set_data(ice, tmp);
319 tmp |= GPIO_D5_SPI_CCLK;
320 ice->gpio.set_data(ice, tmp);
325 ice->gpio.set_data(ice, tmp);
328 /* return all gpios to non-writable */
329 ice->gpio.set_mask(ice, 0xffffff);
330 /* restore GPIOs direction */
331 ice->gpio.set_dir(ice, orig_dir);
334 static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
335 unsigned char mask, unsigned char value)
339 for (chip = 0; chip < ak->num_chips; chip++) {
340 tmp = snd_akm4xxx_get(ak, chip, addr);
343 /* set the new bits */
345 snd_akm4xxx_write(ak, chip, addr, tmp);
350 * change the rate of AK4620
352 static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
354 unsigned char ak4620_dfs;
356 if (rate == 0) /* no hint - S/PDIF input is master or the new spdif
357 input rate undetected, simply return */
360 /* adjust DFS on codecs - see datasheet */
362 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
363 else if (rate > 54000)
364 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
369 qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
370 AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
373 #define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
375 #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
376 #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
377 #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
378 #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
380 static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
381 AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
382 AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
385 static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
386 AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
387 AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
390 static const struct snd_akm4xxx akm_qtet_dac = {
392 .num_dacs = 4, /* DAC1 - Output 12
394 .num_adcs = 4, /* ADC1 - Input 12
397 .write = qtet_akm_write,
398 .set_rate_val = qtet_akm_set_rate_val,
400 .dac_info = qtet_dac,
401 .adc_info = qtet_adc,
404 /* Communication routines with the CPLD */
407 /* Writes data to external register reg, both reg and data are
408 * GPIO representations */
409 static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
414 mutex_lock(&ice->gpio_mutex);
415 /* set direction of used GPIOs*/
418 ice->gpio.set_dir(ice, tmp);
419 /* mask - writable bits */
420 ice->gpio.set_mask(ice, ~(tmp));
422 tmp = ice->gpio.get_data(ice);
423 tmp &= ~GPIO_DATA_MASK;
425 ice->gpio.set_data(ice, tmp);
427 /* drop output enable */
428 tmp &= ~GPIO_EX_GPIOE;
429 ice->gpio.set_data(ice, tmp);
431 /* drop the register gpio */
433 ice->gpio.set_data(ice, tmp);
435 /* raise the register GPIO */
437 ice->gpio.set_data(ice, tmp);
440 /* raise all data gpios */
441 tmp |= GPIO_DATA_MASK;
442 ice->gpio.set_data(ice, tmp);
443 /* mask - immutable bits */
444 ice->gpio.set_mask(ice, 0xffffff);
445 /* outputs only 8-15 */
446 ice->gpio.set_dir(ice, 0x00ff00);
447 mutex_unlock(&ice->gpio_mutex);
450 static unsigned int get_scr(struct snd_ice1712 *ice)
452 struct qtet_spec *spec = ice->spec;
456 static unsigned int get_mcr(struct snd_ice1712 *ice)
458 struct qtet_spec *spec = ice->spec;
462 static unsigned int get_cpld(struct snd_ice1712 *ice)
464 struct qtet_spec *spec = ice->spec;
468 static void set_scr(struct snd_ice1712 *ice, unsigned int val)
470 struct qtet_spec *spec = ice->spec;
471 reg_write(ice, GPIO_SCR, val);
475 static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
477 struct qtet_spec *spec = ice->spec;
478 reg_write(ice, GPIO_MCR, val);
482 static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
484 struct qtet_spec *spec = ice->spec;
485 reg_write(ice, GPIO_CPLD_CSN, val);
489 static void proc_regs_read(struct snd_info_entry *entry,
490 struct snd_info_buffer *buffer)
492 struct snd_ice1712 *ice = entry->private_data;
495 snd_iprintf(buffer, "SCR: %s\n", get_binary(bin_buffer,
497 snd_iprintf(buffer, "MCR: %s\n", get_binary(bin_buffer,
499 snd_iprintf(buffer, "CPLD: %s\n", get_binary(bin_buffer,
503 static void proc_init(struct snd_ice1712 *ice)
505 struct snd_info_entry *entry;
506 if (!snd_card_proc_new(ice->card, "quartet", &entry))
507 snd_info_set_text_ops(entry, ice, proc_regs_read);
510 static int qtet_mute_get(struct snd_kcontrol *kcontrol,
511 struct snd_ctl_elem_value *ucontrol)
513 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
515 val = get_scr(ice) & SCR_MUTE;
516 ucontrol->value.integer.value[0] = (val) ? 0 : 1;
520 static int qtet_mute_put(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
523 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
524 unsigned int old, new, smute;
525 old = get_scr(ice) & SCR_MUTE;
526 if (ucontrol->value.integer.value[0]) {
535 smute = AK4620_SMUTE;
538 struct snd_akm4xxx *ak = ice->akm;
539 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
541 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
548 static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
549 struct snd_ctl_elem_info *uinfo)
551 static const char * const texts[3] =
552 {"Line In 1/2", "Mic", "Mic + Low-cut"};
553 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
556 static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
557 struct snd_ctl_elem_value *ucontrol)
559 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
560 unsigned int val, result;
561 val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
569 case SCR_AIN12_LOWCUT:
573 /* BUG - no other combinations allowed */
577 ucontrol->value.integer.value[0] = result;
581 static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
582 struct snd_ctl_elem_value *ucontrol)
584 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
585 unsigned int old, new, tmp, masked_old;
586 old = new = get_scr(ice);
587 masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
588 tmp = ucontrol->value.integer.value[0];
590 tmp = 3; /* binary 10 is not supported */
591 tmp <<= 4; /* shifting to SCR_AIN12_SEL0 */
592 if (tmp != masked_old) {
593 /* change requested */
596 new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
604 new = old | SCR_RELAY;
606 new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
609 case SCR_AIN12_LOWCUT:
611 new = old | SCR_RELAY;
613 new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
625 static int qtet_php_get(struct snd_kcontrol *kcontrol,
626 struct snd_ctl_elem_value *ucontrol)
628 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
630 /* if phantom voltage =48V, phantom on */
631 val = get_scr(ice) & SCR_PHP_V;
632 ucontrol->value.integer.value[0] = val ? 1 : 0;
636 static int qtet_php_put(struct snd_kcontrol *kcontrol,
637 struct snd_ctl_elem_value *ucontrol)
639 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
640 unsigned int old, new;
641 old = new = get_scr(ice);
642 if (ucontrol->value.integer.value[0] /* phantom on requested */
643 && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
644 /* is off, turn on */
645 /* turn voltage on first, = 1 */
646 new = old | SCR_PHP_V;
648 /* turn phantom on, = 0 */
651 } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
652 /* phantom off requested and 1 = voltage 48V */
653 /* is on, turn off */
654 /* turn voltage off first, = 0 */
655 new = old & ~SCR_PHP_V;
657 /* turn phantom off, = 1 */
667 #define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
668 .set_register = set_##xreg,\
669 .get_register = get_##xreg, }
672 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
673 .set_register = set_##xreg,\
674 .get_register = get_##xreg,\
675 .texts = {xtext1, xtext2} }
677 static struct qtet_kcontrol_private qtet_privates[] = {
678 PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
679 PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
680 PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
681 PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
682 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
683 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
684 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
685 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
686 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
687 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
690 static int qtet_enum_info(struct snd_kcontrol *kcontrol,
691 struct snd_ctl_elem_info *uinfo)
693 struct qtet_kcontrol_private private =
694 qtet_privates[kcontrol->private_value];
695 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
699 static int qtet_sw_get(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
702 struct qtet_kcontrol_private private =
703 qtet_privates[kcontrol->private_value];
704 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
705 ucontrol->value.integer.value[0] =
706 (private.get_register(ice) & private.bit) ? 1 : 0;
710 static int qtet_sw_put(struct snd_kcontrol *kcontrol,
711 struct snd_ctl_elem_value *ucontrol)
713 struct qtet_kcontrol_private private =
714 qtet_privates[kcontrol->private_value];
715 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
716 unsigned int old, new;
717 old = private.get_register(ice);
718 if (ucontrol->value.integer.value[0])
719 new = old | private.bit;
721 new = old & ~private.bit;
723 private.set_register(ice, new);
730 #define qtet_sw_info snd_ctl_boolean_mono_info
732 #define QTET_CONTROL(xname, xtype, xpriv) \
733 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
735 .info = qtet_##xtype##_info,\
738 .private_value = xpriv }
740 static struct snd_kcontrol_new qtet_controls[] = {
742 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
743 .name = "Master Playback Switch",
744 .info = qtet_sw_info,
745 .get = qtet_mute_get,
746 .put = qtet_mute_put,
750 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
751 .name = "Phantom Power",
752 .info = qtet_sw_info,
758 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
759 .name = "Analog In 1/2 Capture Switch",
760 .info = qtet_ain12_enum_info,
761 .get = qtet_ain12_sw_get,
762 .put = qtet_ain12_sw_put,
765 QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
766 QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
767 QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
768 QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
769 QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
770 QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
771 QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
772 QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
773 QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
774 QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
777 static char *slave_vols[] = {
778 PCM_12_PLAYBACK_VOLUME,
779 PCM_34_PLAYBACK_VOLUME,
784 DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
786 static struct snd_kcontrol *ctl_find(struct snd_card *card,
789 struct snd_ctl_elem_id sid = {0};
791 strlcpy(sid.name, name, sizeof(sid.name));
792 sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
793 return snd_ctl_find_id(card, &sid);
796 static void add_slaves(struct snd_card *card,
797 struct snd_kcontrol *master, char * const *list)
799 for (; *list; list++) {
800 struct snd_kcontrol *slave = ctl_find(card, *list);
802 snd_ctl_add_slave(master, slave);
806 static int qtet_add_controls(struct snd_ice1712 *ice)
808 struct qtet_spec *spec = ice->spec;
810 struct snd_kcontrol *vmaster;
811 err = snd_ice1712_akm4xxx_build_controls(ice);
814 for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
815 err = snd_ctl_add(ice->card,
816 snd_ctl_new1(&qtet_controls[i], ice));
821 /* Create virtual master control */
822 vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
823 qtet_master_db_scale);
826 add_slaves(ice->card, vmaster, slave_vols);
827 err = snd_ctl_add(ice->card, vmaster);
830 /* only capture SPDIF over AK4113 */
831 return snd_ak4113_build(spec->ak4113,
832 ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
835 static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
837 /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
838 return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
841 static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
844 unsigned char result;
846 result = get_cpld(ice) & CPLD_CKS_MASK;
847 for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
848 if (cks_vals[i] == result)
849 return qtet_rates[i];
853 static int get_cks_val(int rate)
856 for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
857 if (qtet_rates[i] == rate)
862 /* setting new rate */
863 static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
867 /* switching ice1724 to external clock - supplied by ext. circuits */
868 val = inb(ICEMT1724(ice, RATE));
869 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
871 new = (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
872 /* switch to internal clock, drop CPLD_SYNC_SEL */
873 new &= ~CPLD_SYNC_SEL;
874 /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
875 get_cpld(ice), new); */
879 static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
882 /* no change in master clock */
886 /* setting clock to external - SPDIF */
887 static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
889 unsigned int old, new;
891 old = new = get_cpld(ice);
892 new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
895 new |= CPLD_EXT_SPDIF;
897 case EXT_WORDCLOCK_1FS_TYPE:
898 new |= CPLD_EXT_WORDCLOCK_1FS;
900 case EXT_WORDCLOCK_256FS_TYPE:
901 new |= CPLD_EXT_WORDCLOCK_256FS;
914 static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
919 /* checking only rate/clock-related bits */
920 val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
921 if (!(val & CPLD_SYNC_SEL)) {
922 /* switched to internal clock, is not any external type */
926 case (CPLD_EXT_SPDIF):
927 result = EXT_SPDIF_TYPE;
929 case (CPLD_EXT_WORDCLOCK_1FS):
930 result = EXT_WORDCLOCK_1FS_TYPE;
932 case (CPLD_EXT_WORDCLOCK_256FS):
933 result = EXT_WORDCLOCK_256FS_TYPE;
936 /* undefined combination of external clock setup */
944 /* Called when ak4113 detects change in the input SPDIF stream */
945 static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
948 struct snd_ice1712 *ice = ak4113->change_callback_private;
950 if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
952 /* only for SPDIF master mode, rate was changed */
953 rate = snd_ak4113_external_rate(ak4113);
954 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
956 qtet_akm_set_rate_val(ice->akm, rate);
961 * If clock slaved to SPDIF-IN, setting runtime rate
962 * to the detected external rate
964 static void qtet_spdif_in_open(struct snd_ice1712 *ice,
965 struct snd_pcm_substream *substream)
967 struct qtet_spec *spec = ice->spec;
968 struct snd_pcm_runtime *runtime = substream->runtime;
971 if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
972 /* not external SPDIF, no rate limitation */
974 /* only external SPDIF can detect incoming sample rate */
975 rate = snd_ak4113_external_rate(spec->ak4113);
976 if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
977 runtime->hw.rate_min = rate;
978 runtime->hw.rate_max = rate;
983 * initialize the chip
985 static int qtet_init(struct snd_ice1712 *ice)
987 static const unsigned char ak4113_init_vals[] = {
988 /* AK4113_REG_PWRDN */ AK4113_RST | AK4113_PWN |
989 AK4113_OCKS0 | AK4113_OCKS1,
990 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
991 AK4113_DEM_OFF | AK4113_DEAU,
992 /* AK4113_REG_IO0 */ AK4113_OPS2 | AK4113_TXE |
994 /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK | AK4113_IPS(0),
995 /* AK4113_REG_INT0_MASK */ 0,
996 /* AK4113_REG_INT1_MASK */ 0,
997 /* AK4113_REG_DATDTS */ 0,
1000 struct qtet_spec *spec;
1001 struct snd_akm4xxx *ak;
1004 /* switching ice1724 to external clock - supplied by ext. circuits */
1005 val = inb(ICEMT1724(ice, RATE));
1006 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1008 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1011 /* qtet is clocked by Xilinx array */
1012 ice->hw_rates = &qtet_rates_info;
1013 ice->is_spdif_master = qtet_is_spdif_master;
1014 ice->get_rate = qtet_get_rate;
1015 ice->set_rate = qtet_set_rate;
1016 ice->set_mclk = qtet_set_mclk;
1017 ice->set_spdif_clock = qtet_set_spdif_clock;
1018 ice->get_spdif_master_type = qtet_get_spdif_master_type;
1019 ice->ext_clock_names = ext_clock_names;
1020 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
1021 /* since Qtet can detect correct SPDIF-in rate, all streams can be
1022 * limited to this specific rate */
1023 ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
1028 /* keep codec power down first */
1029 set_scr(ice, SCR_PHP);
1031 /* codec power up */
1032 set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
1034 /* MCR Initialize */
1037 /* CPLD Initialize */
1041 ice->num_total_dacs = 2;
1042 ice->num_total_adcs = 2;
1044 ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
1048 /* only one codec with two chips */
1049 ice->akm_codecs = 1;
1050 err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1053 err = snd_ak4113_create(ice->card,
1057 ice, &spec->ak4113);
1060 /* callback for codecs rate setting */
1061 spec->ak4113->change_callback = qtet_ak4113_change;
1062 spec->ak4113->change_callback_private = ice;
1063 /* AK41143 in Quartet can detect external rate correctly
1064 * (i.e. check_flags = 0) */
1065 spec->ak4113->check_flags = 0;
1069 qtet_set_rate(ice, 44100);
1073 static unsigned char qtet_eeprom[] = {
1074 [ICE_EEP2_SYSCONF] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,
1076 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
1077 [ICE_EEP2_I2S] = 0x78, /* 96k, 24bit, 192k */
1078 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, in, out-ext */
1079 [ICE_EEP2_GPIO_DIR] = 0x00, /* 0-7 inputs, switched to output
1080 only during output operations */
1081 [ICE_EEP2_GPIO_DIR1] = 0xff, /* 8-15 outputs */
1082 [ICE_EEP2_GPIO_DIR2] = 0x00,
1083 [ICE_EEP2_GPIO_MASK] = 0xff, /* changed only for OUT operations */
1084 [ICE_EEP2_GPIO_MASK1] = 0x00,
1085 [ICE_EEP2_GPIO_MASK2] = 0xff,
1087 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
1088 [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1089 and GPIO15 always zero */
1090 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1094 struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
1096 .subvendor = VT1724_SUBDEVICE_QTET,
1097 .name = "Infrasonic Quartet",
1099 .chip_init = qtet_init,
1100 .build_controls = qtet_add_controls,
1101 .eeprom_size = sizeof(qtet_eeprom),
1102 .eeprom_data = qtet_eeprom,
1104 { } /* terminator */