1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
13 * Wu Fengguang <wfg@linux.intel.com>
16 * Wu Fengguang <wfg@linux.intel.com>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
35 #include "hda_controller.h"
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
50 struct hdmi_spec_per_cvt {
53 unsigned int channels_min;
54 unsigned int channels_max;
60 /* max. connections to a widget */
61 #define HDA_MAX_CONNECTIONS 32
63 struct hdmi_spec_per_pin {
66 /* pin idx, different device entries on the same pin use the same idx */
69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
73 struct hda_codec *codec;
74 struct hdmi_eld sink_eld;
76 struct delayed_work work;
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
80 bool setup; /* the stream has been set up by prepare callback */
82 int channels; /* current number of channels */
84 bool chmap_set; /* channel-map override by ALSA API? */
85 unsigned char chmap[8]; /* ALSA API channel-map */
86 #ifdef CONFIG_SND_PROC_FS
87 struct snd_info_entry *proc_entry;
91 /* operations used by generic code that can be overridden by patches */
93 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
94 int dev_id, unsigned char *buf, int *eld_size);
96 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int ca, int active_channels, int conn_type);
100 /* enable/disable HBR (HD passthrough) */
101 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int dev_id, bool hbr);
104 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
105 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
108 void (*pin_cvt_fixup)(struct hda_codec *codec,
109 struct hdmi_spec_per_pin *per_pin,
115 struct snd_jack *jack;
116 struct snd_kcontrol *eld_ctl;
120 struct hda_codec *codec;
122 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
123 hda_nid_t cvt_nids[4]; /* only for haswell fix */
126 * num_pins is the number of virtual pins
127 * for example, there are 3 pins, and each pin
128 * has 4 device entries, then the num_pins is 12
132 * num_nids is the number of real pins
133 * In the above example, num_nids is 3
137 * dev_num is the number of device entries
139 * In the above example, dev_num is 4
142 struct snd_array pins; /* struct hdmi_spec_per_pin */
143 struct hdmi_pcm pcm_rec[16];
144 struct mutex pcm_lock;
145 struct mutex bind_lock; /* for audio component binding */
146 /* pcm_bitmap means which pcms have been assigned to pins*/
147 unsigned long pcm_bitmap;
148 int pcm_used; /* counter of pcm_rec[] */
149 /* bitmap shows whether the pcm is opened in user space
150 * bit 0 means the first playback PCM (PCM3);
151 * bit 1 means the second playback PCM, and so on.
153 unsigned long pcm_in_use;
155 struct hdmi_eld temp_eld;
160 bool dyn_pcm_no_legacy;
161 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
163 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
165 * Non-generic VIA/NVIDIA specific
167 struct hda_multi_out multiout;
168 struct hda_pcm_stream pcm_playback;
170 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
171 bool acomp_registered; /* audio component registered in this driver */
172 bool force_connect; /* force connectivity */
173 struct drm_audio_component_audio_ops drm_audio_ops;
174 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
176 struct hdac_chmap chmap;
177 hda_nid_t vendor_nid;
180 bool send_silent_stream; /* Flag to enable silent stream feature */
183 #ifdef CONFIG_SND_HDA_COMPONENT
184 static inline bool codec_has_acomp(struct hda_codec *codec)
186 struct hdmi_spec *spec = codec->spec;
187 return spec->use_acomp_notifier;
190 #define codec_has_acomp(codec) false
193 struct hdmi_audio_infoframe {
200 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
204 u8 LFEPBL01_LSV36_DM_INH7;
207 struct dp_audio_infoframe {
210 u8 ver; /* 0x11 << 2 */
212 u8 CC02_CT47; /* match with HDMI infoframe from this on */
216 u8 LFEPBL01_LSV36_DM_INH7;
219 union audio_infoframe {
220 struct hdmi_audio_infoframe hdmi;
221 struct dp_audio_infoframe dp;
229 #define get_pin(spec, idx) \
230 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
231 #define get_cvt(spec, idx) \
232 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
233 /* obtain hdmi_pcm object assigned to idx */
234 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
235 /* obtain hda_pcm object assigned to idx */
236 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
238 static int pin_id_to_pin_index(struct hda_codec *codec,
239 hda_nid_t pin_nid, int dev_id)
241 struct hdmi_spec *spec = codec->spec;
243 struct hdmi_spec_per_pin *per_pin;
246 * (dev_id == -1) means it is NON-MST pin
247 * return the first virtual pin on this port
252 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
253 per_pin = get_pin(spec, pin_idx);
254 if ((per_pin->pin_nid == pin_nid) &&
255 (per_pin->dev_id == dev_id))
259 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
263 static int hinfo_to_pcm_index(struct hda_codec *codec,
264 struct hda_pcm_stream *hinfo)
266 struct hdmi_spec *spec = codec->spec;
269 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
270 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
273 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
277 static int hinfo_to_pin_index(struct hda_codec *codec,
278 struct hda_pcm_stream *hinfo)
280 struct hdmi_spec *spec = codec->spec;
281 struct hdmi_spec_per_pin *per_pin;
284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
285 per_pin = get_pin(spec, pin_idx);
287 per_pin->pcm->pcm->stream == hinfo)
291 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
292 hinfo_to_pcm_index(codec, hinfo));
296 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
300 struct hdmi_spec_per_pin *per_pin;
302 for (i = 0; i < spec->num_pins; i++) {
303 per_pin = get_pin(spec, i);
304 if (per_pin->pcm_idx == pcm_idx)
310 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
312 struct hdmi_spec *spec = codec->spec;
315 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
316 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
319 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
323 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
324 struct snd_ctl_elem_info *uinfo)
326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
327 struct hdmi_spec *spec = codec->spec;
328 struct hdmi_spec_per_pin *per_pin;
329 struct hdmi_eld *eld;
332 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
334 pcm_idx = kcontrol->private_value;
335 mutex_lock(&spec->pcm_lock);
336 per_pin = pcm_idx_to_pin(spec, pcm_idx);
338 /* no pin is bound to the pcm */
342 eld = &per_pin->sink_eld;
343 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
346 mutex_unlock(&spec->pcm_lock);
350 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
353 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
354 struct hdmi_spec *spec = codec->spec;
355 struct hdmi_spec_per_pin *per_pin;
356 struct hdmi_eld *eld;
360 pcm_idx = kcontrol->private_value;
361 mutex_lock(&spec->pcm_lock);
362 per_pin = pcm_idx_to_pin(spec, pcm_idx);
364 /* no pin is bound to the pcm */
365 memset(ucontrol->value.bytes.data, 0,
366 ARRAY_SIZE(ucontrol->value.bytes.data));
370 eld = &per_pin->sink_eld;
371 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
372 eld->eld_size > ELD_MAX_SIZE) {
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
381 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
385 mutex_unlock(&spec->pcm_lock);
389 static const struct snd_kcontrol_new eld_bytes_ctl = {
390 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
391 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
392 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
394 .info = hdmi_eld_ctl_info,
395 .get = hdmi_eld_ctl_get,
398 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
401 struct snd_kcontrol *kctl;
402 struct hdmi_spec *spec = codec->spec;
405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
408 kctl->private_value = pcm_idx;
409 kctl->id.device = device;
411 /* no pin nid is associated with the kctl now
412 * tbd: associate pin nid to eld ctl later
414 err = snd_hda_ctl_add(codec, 0, kctl);
418 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
423 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
424 int *packet_index, int *byte_index)
428 val = snd_hda_codec_read(codec, pin_nid, 0,
429 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431 *packet_index = val >> 5;
432 *byte_index = val & 0x1f;
436 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
437 int packet_index, int byte_index)
441 val = (packet_index << 5) | (byte_index & 0x1f);
443 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
446 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
449 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
452 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
454 struct hdmi_spec *spec = codec->spec;
458 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
459 snd_hda_codec_write(codec, pin_nid, 0,
460 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
462 if (spec->dyn_pin_out)
463 /* Disable pin out until stream is active */
466 /* Enable pin out: some machines with GM965 gets broken output
467 * when the pin is disabled or changed while using with HDMI
471 snd_hda_codec_write(codec, pin_nid, 0,
472 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
479 #ifdef CONFIG_SND_PROC_FS
480 static void print_eld_info(struct snd_info_entry *entry,
481 struct snd_info_buffer *buffer)
483 struct hdmi_spec_per_pin *per_pin = entry->private_data;
485 mutex_lock(&per_pin->lock);
486 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
487 mutex_unlock(&per_pin->lock);
490 static void write_eld_info(struct snd_info_entry *entry,
491 struct snd_info_buffer *buffer)
493 struct hdmi_spec_per_pin *per_pin = entry->private_data;
495 mutex_lock(&per_pin->lock);
496 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
497 mutex_unlock(&per_pin->lock);
500 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
503 struct hda_codec *codec = per_pin->codec;
504 struct snd_info_entry *entry;
507 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
508 err = snd_card_proc_new(codec->card, name, &entry);
512 snd_info_set_text_ops(entry, per_pin, print_eld_info);
513 entry->c.text.write = write_eld_info;
515 per_pin->proc_entry = entry;
520 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
522 if (!per_pin->codec->bus->shutdown) {
523 snd_info_free_entry(per_pin->proc_entry);
524 per_pin->proc_entry = NULL;
528 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
533 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
539 * Audio InfoFrame routines
543 * Enable Audio InfoFrame Transmission
545 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
548 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
549 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
554 * Disable Audio InfoFrame Transmission
556 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
559 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
560 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
566 #ifdef CONFIG_SND_DEBUG_VERBOSE
570 size = snd_hdmi_get_eld_size(codec, pin_nid);
571 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
573 for (i = 0; i < 8; i++) {
574 size = snd_hda_codec_read(codec, pin_nid, 0,
575 AC_VERB_GET_HDMI_DIP_SIZE, i);
576 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
581 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
587 for (i = 0; i < 8; i++) {
588 size = snd_hda_codec_read(codec, pin_nid, 0,
589 AC_VERB_GET_HDMI_DIP_SIZE, i);
593 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
594 for (j = 1; j < 1000; j++) {
595 hdmi_write_dip_byte(codec, pin_nid, 0x0);
596 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
598 codec_dbg(codec, "dip index %d: %d != %d\n",
600 if (bi == 0) /* byte index wrapped around */
604 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
610 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
612 u8 *bytes = (u8 *)hdmi_ai;
616 hdmi_ai->checksum = 0;
618 for (i = 0; i < sizeof(*hdmi_ai); i++)
621 hdmi_ai->checksum = -sum;
624 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
630 hdmi_debug_dip_size(codec, pin_nid);
631 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
633 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
634 for (i = 0; i < size; i++)
635 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
638 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
644 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
648 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
649 for (i = 0; i < size; i++) {
650 val = snd_hda_codec_read(codec, pin_nid, 0,
651 AC_VERB_GET_HDMI_DIP_DATA, 0);
659 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
660 int dev_id, unsigned char *buf, int *eld_size)
662 snd_hda_set_dev_select(codec, nid, dev_id);
664 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
667 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
668 hda_nid_t pin_nid, int dev_id,
669 int ca, int active_channels,
672 struct hdmi_spec *spec = codec->spec;
673 union audio_infoframe ai;
675 memset(&ai, 0, sizeof(ai));
676 if ((conn_type == 0) || /* HDMI */
677 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
678 (conn_type == 1 && spec->nv_dp_workaround)) {
679 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
681 if (conn_type == 0) { /* HDMI */
682 hdmi_ai->type = 0x84;
685 } else {/* Nvidia DP */
686 hdmi_ai->type = 0x84;
688 hdmi_ai->len = 0x11 << 2;
690 hdmi_ai->CC02_CT47 = active_channels - 1;
692 hdmi_checksum_audio_infoframe(hdmi_ai);
693 } else if (conn_type == 1) { /* DisplayPort */
694 struct dp_audio_infoframe *dp_ai = &ai.dp;
698 dp_ai->ver = 0x11 << 2;
699 dp_ai->CC02_CT47 = active_channels - 1;
702 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
707 snd_hda_set_dev_select(codec, pin_nid, dev_id);
710 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
711 * sizeof(*dp_ai) to avoid partial match/update problems when
712 * the user switches between HDMI/DP monitors.
714 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
717 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
719 active_channels, ca);
720 hdmi_stop_infoframe_trans(codec, pin_nid);
721 hdmi_fill_audio_infoframe(codec, pin_nid,
722 ai.bytes, sizeof(ai));
723 hdmi_start_infoframe_trans(codec, pin_nid);
727 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
728 struct hdmi_spec_per_pin *per_pin,
731 struct hdmi_spec *spec = codec->spec;
732 struct hdac_chmap *chmap = &spec->chmap;
733 hda_nid_t pin_nid = per_pin->pin_nid;
734 int dev_id = per_pin->dev_id;
735 int channels = per_pin->channels;
737 struct hdmi_eld *eld;
743 snd_hda_set_dev_select(codec, pin_nid, dev_id);
745 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
746 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
747 snd_hda_codec_write(codec, pin_nid, 0,
748 AC_VERB_SET_AMP_GAIN_MUTE,
751 eld = &per_pin->sink_eld;
753 ca = snd_hdac_channel_allocation(&codec->core,
754 eld->info.spk_alloc, channels,
755 per_pin->chmap_set, non_pcm, per_pin->chmap);
757 active_channels = snd_hdac_get_active_channels(ca);
759 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
763 * always configure channel mapping, it may have been changed by the
764 * user in the meantime
766 snd_hdac_setup_channel_mapping(&spec->chmap,
767 pin_nid, non_pcm, ca, channels,
768 per_pin->chmap, per_pin->chmap_set);
770 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
771 ca, active_channels, eld->info.conn_type);
773 per_pin->non_pcm = non_pcm;
780 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
782 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
785 struct hdmi_spec *spec = codec->spec;
786 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
790 mutex_lock(&spec->pcm_lock);
791 hdmi_present_sense(get_pin(spec, pin_idx), 1);
792 mutex_unlock(&spec->pcm_lock);
795 static void jack_callback(struct hda_codec *codec,
796 struct hda_jack_callback *jack)
798 /* stop polling when notification is enabled */
799 if (codec_has_acomp(codec))
802 check_presence_and_report(codec, jack->nid, jack->dev_id);
805 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
806 struct hda_jack_tbl *jack)
808 jack->jack_dirty = 1;
811 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
812 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
813 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
815 check_presence_and_report(codec, jack->nid, jack->dev_id);
818 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
820 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
821 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
822 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
823 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
826 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
843 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
845 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
846 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
847 struct hda_jack_tbl *jack;
849 if (codec_has_acomp(codec))
854 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
856 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
858 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
862 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
867 hdmi_intrinsic_event(codec, res, jack);
869 hdmi_non_intrinsic_event(codec, res);
872 static void haswell_verify_D0(struct hda_codec *codec,
873 hda_nid_t cvt_nid, hda_nid_t nid)
877 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
878 * thus pins could only choose converter 0 for use. Make sure the
879 * converters are in correct power state */
880 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
881 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
883 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
884 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
887 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
888 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
889 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
897 /* HBR should be Non-PCM, 8 channels */
898 #define is_hbr_format(format) \
899 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
901 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
902 int dev_id, bool hbr)
904 int pinctl, new_pinctl;
906 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
907 snd_hda_set_dev_select(codec, pin_nid, dev_id);
908 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
909 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
912 return hbr ? -EINVAL : 0;
914 new_pinctl = pinctl & ~AC_PINCTL_EPT;
916 new_pinctl |= AC_PINCTL_EPT_HBR;
918 new_pinctl |= AC_PINCTL_EPT_NATIVE;
921 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
923 pinctl == new_pinctl ? "" : "new-",
926 if (pinctl != new_pinctl)
927 snd_hda_codec_write(codec, pin_nid, 0,
928 AC_VERB_SET_PIN_WIDGET_CONTROL,
936 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
937 hda_nid_t pin_nid, int dev_id,
938 u32 stream_tag, int format)
940 struct hdmi_spec *spec = codec->spec;
944 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
945 is_hbr_format(format));
948 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
952 if (spec->intel_hsw_fixup) {
955 * on recent platforms IEC Coding Type is required for HBR
956 * support, read current Digital Converter settings and set
957 * ICT bitfield if needed.
959 param = snd_hda_codec_read(codec, cvt_nid, 0,
960 AC_VERB_GET_DIGI_CONVERT_1, 0);
962 param = (param >> 16) & ~(AC_DIG3_ICT);
964 /* on recent platforms ICT mode is required for HBR support */
965 if (is_hbr_format(format))
968 snd_hda_codec_write(codec, cvt_nid, 0,
969 AC_VERB_SET_DIGI_CONVERT_3, param);
972 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
976 /* Try to find an available converter
977 * If pin_idx is less then zero, just try to find an available converter.
978 * Otherwise, try to find an available converter and get the cvt mux index
981 static int hdmi_choose_cvt(struct hda_codec *codec,
982 int pin_idx, int *cvt_id)
984 struct hdmi_spec *spec = codec->spec;
985 struct hdmi_spec_per_pin *per_pin;
986 struct hdmi_spec_per_cvt *per_cvt = NULL;
987 int cvt_idx, mux_idx = 0;
989 /* pin_idx < 0 means no pin will be bound to the converter */
993 per_pin = get_pin(spec, pin_idx);
995 if (per_pin && per_pin->silent_stream) {
996 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1002 /* Dynamically assign converter to stream */
1003 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1004 per_cvt = get_cvt(spec, cvt_idx);
1006 /* Must not already be assigned */
1007 if (per_cvt->assigned)
1009 if (per_pin == NULL)
1011 /* Must be in pin's mux's list of converters */
1012 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1013 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1015 /* Not in mux list */
1016 if (mux_idx == per_pin->num_mux_nids)
1021 /* No free converters */
1022 if (cvt_idx == spec->num_cvts)
1025 if (per_pin != NULL)
1026 per_pin->mux_idx = mux_idx;
1034 /* Assure the pin select the right convetor */
1035 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1036 struct hdmi_spec_per_pin *per_pin)
1038 hda_nid_t pin_nid = per_pin->pin_nid;
1041 mux_idx = per_pin->mux_idx;
1042 curr = snd_hda_codec_read(codec, pin_nid, 0,
1043 AC_VERB_GET_CONNECT_SEL, 0);
1044 if (curr != mux_idx)
1045 snd_hda_codec_write_cache(codec, pin_nid, 0,
1046 AC_VERB_SET_CONNECT_SEL,
1050 /* get the mux index for the converter of the pins
1051 * converter's mux index is the same for all pins on Intel platform
1053 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1058 for (i = 0; i < spec->num_cvts; i++)
1059 if (spec->cvt_nids[i] == cvt_nid)
1064 /* Intel HDMI workaround to fix audio routing issue:
1065 * For some Intel display codecs, pins share the same connection list.
1066 * So a conveter can be selected by multiple pins and playback on any of these
1067 * pins will generate sound on the external display, because audio flows from
1068 * the same converter to the display pipeline. Also muting one pin may make
1069 * other pins have no sound output.
1070 * So this function assures that an assigned converter for a pin is not selected
1071 * by any other pins.
1073 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1075 int dev_id, int mux_idx)
1077 struct hdmi_spec *spec = codec->spec;
1080 struct hdmi_spec_per_cvt *per_cvt;
1081 struct hdmi_spec_per_pin *per_pin;
1084 /* configure the pins connections */
1085 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1089 per_pin = get_pin(spec, pin_idx);
1091 * pin not connected to monitor
1092 * no need to operate on it
1097 if ((per_pin->pin_nid == pin_nid) &&
1098 (per_pin->dev_id == dev_id))
1102 * if per_pin->dev_id >= dev_num,
1103 * snd_hda_get_dev_select() will fail,
1104 * and the following operation is unpredictable.
1105 * So skip this situation.
1107 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1108 if (per_pin->dev_id >= dev_num)
1111 nid = per_pin->pin_nid;
1114 * Calling this function should not impact
1115 * on the device entry selection
1116 * So let's save the dev id for each pin,
1117 * and restore it when return
1119 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1120 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1121 curr = snd_hda_codec_read(codec, nid, 0,
1122 AC_VERB_GET_CONNECT_SEL, 0);
1123 if (curr != mux_idx) {
1124 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1129 /* choose an unassigned converter. The conveters in the
1130 * connection list are in the same order as in the codec.
1132 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1133 per_cvt = get_cvt(spec, cvt_idx);
1134 if (!per_cvt->assigned) {
1136 "choose cvt %d for pin nid %d\n",
1138 snd_hda_codec_write_cache(codec, nid, 0,
1139 AC_VERB_SET_CONNECT_SEL,
1144 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1148 /* A wrapper of intel_not_share_asigned_cvt() */
1149 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1150 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1153 struct hdmi_spec *spec = codec->spec;
1155 /* On Intel platform, the mapping of converter nid to
1156 * mux index of the pins are always the same.
1157 * The pin nid may be 0, this means all pins will not
1158 * share the converter.
1160 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1162 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1165 /* skeleton caller of pin_cvt_fixup ops */
1166 static void pin_cvt_fixup(struct hda_codec *codec,
1167 struct hdmi_spec_per_pin *per_pin,
1170 struct hdmi_spec *spec = codec->spec;
1172 if (spec->ops.pin_cvt_fixup)
1173 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1176 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1177 * in dyn_pcm_assign mode.
1179 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1180 struct hda_codec *codec,
1181 struct snd_pcm_substream *substream)
1183 struct hdmi_spec *spec = codec->spec;
1184 struct snd_pcm_runtime *runtime = substream->runtime;
1185 int cvt_idx, pcm_idx;
1186 struct hdmi_spec_per_cvt *per_cvt = NULL;
1189 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1193 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1197 per_cvt = get_cvt(spec, cvt_idx);
1198 per_cvt->assigned = 1;
1199 hinfo->nid = per_cvt->cvt_nid;
1201 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1203 set_bit(pcm_idx, &spec->pcm_in_use);
1204 /* todo: setup spdif ctls assign */
1206 /* Initially set the converter's capabilities */
1207 hinfo->channels_min = per_cvt->channels_min;
1208 hinfo->channels_max = per_cvt->channels_max;
1209 hinfo->rates = per_cvt->rates;
1210 hinfo->formats = per_cvt->formats;
1211 hinfo->maxbps = per_cvt->maxbps;
1213 /* Store the updated parameters */
1214 runtime->hw.channels_min = hinfo->channels_min;
1215 runtime->hw.channels_max = hinfo->channels_max;
1216 runtime->hw.formats = hinfo->formats;
1217 runtime->hw.rates = hinfo->rates;
1219 snd_pcm_hw_constraint_step(substream->runtime, 0,
1220 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1227 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1228 struct hda_codec *codec,
1229 struct snd_pcm_substream *substream)
1231 struct hdmi_spec *spec = codec->spec;
1232 struct snd_pcm_runtime *runtime = substream->runtime;
1233 int pin_idx, cvt_idx, pcm_idx;
1234 struct hdmi_spec_per_pin *per_pin;
1235 struct hdmi_eld *eld;
1236 struct hdmi_spec_per_cvt *per_cvt = NULL;
1239 /* Validate hinfo */
1240 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1244 mutex_lock(&spec->pcm_lock);
1245 pin_idx = hinfo_to_pin_index(codec, hinfo);
1246 if (!spec->dyn_pcm_assign) {
1247 if (snd_BUG_ON(pin_idx < 0)) {
1252 /* no pin is assigned to the PCM
1253 * PA need pcm open successfully when probe
1256 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1261 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1265 per_cvt = get_cvt(spec, cvt_idx);
1266 /* Claim converter */
1267 per_cvt->assigned = 1;
1269 set_bit(pcm_idx, &spec->pcm_in_use);
1270 per_pin = get_pin(spec, pin_idx);
1271 per_pin->cvt_nid = per_cvt->cvt_nid;
1272 per_pin->silent_stream = false;
1273 hinfo->nid = per_cvt->cvt_nid;
1275 /* flip stripe flag for the assigned stream if supported */
1276 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1277 azx_stream(get_azx_dev(substream))->stripe = 1;
1279 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1280 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1281 AC_VERB_SET_CONNECT_SEL,
1284 /* configure unused pins to choose other converters */
1285 pin_cvt_fixup(codec, per_pin, 0);
1287 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1289 /* Initially set the converter's capabilities */
1290 hinfo->channels_min = per_cvt->channels_min;
1291 hinfo->channels_max = per_cvt->channels_max;
1292 hinfo->rates = per_cvt->rates;
1293 hinfo->formats = per_cvt->formats;
1294 hinfo->maxbps = per_cvt->maxbps;
1296 eld = &per_pin->sink_eld;
1297 /* Restrict capabilities by ELD if this isn't disabled */
1298 if (!static_hdmi_pcm && eld->eld_valid) {
1299 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1300 if (hinfo->channels_min > hinfo->channels_max ||
1301 !hinfo->rates || !hinfo->formats) {
1302 per_cvt->assigned = 0;
1304 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1310 /* Store the updated parameters */
1311 runtime->hw.channels_min = hinfo->channels_min;
1312 runtime->hw.channels_max = hinfo->channels_max;
1313 runtime->hw.formats = hinfo->formats;
1314 runtime->hw.rates = hinfo->rates;
1316 snd_pcm_hw_constraint_step(substream->runtime, 0,
1317 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1319 mutex_unlock(&spec->pcm_lock);
1324 * HDA/HDMI auto parsing
1326 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1328 struct hdmi_spec *spec = codec->spec;
1329 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1330 hda_nid_t pin_nid = per_pin->pin_nid;
1331 int dev_id = per_pin->dev_id;
1334 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1336 "HDMI: pin %d wcaps %#x does not support connection list\n",
1337 pin_nid, get_wcaps(codec, pin_nid));
1341 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1343 if (spec->intel_hsw_fixup) {
1344 conns = spec->num_cvts;
1345 memcpy(per_pin->mux_nids, spec->cvt_nids,
1346 sizeof(hda_nid_t) * conns);
1348 conns = snd_hda_get_raw_connections(codec, pin_nid,
1350 HDA_MAX_CONNECTIONS);
1353 /* all the device entries on the same pin have the same conn list */
1354 per_pin->num_mux_nids = conns;
1359 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1360 struct hdmi_spec_per_pin *per_pin)
1364 /* on the new machines, try to assign the pcm slot dynamically,
1365 * not use the preferred fixed map (legacy way) anymore.
1367 if (spec->dyn_pcm_no_legacy)
1371 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1372 * platforms (with maximum of 'num_nids + dev_num - 1')
1374 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1375 * if m==0. This guarantees that dynamic pcm assignments are compatible
1376 * with the legacy static per_pin-pcm assignment that existed in the
1377 * days before DP-MST.
1379 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1381 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1384 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1385 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1386 return per_pin->pin_nid_idx;
1388 i = spec->num_nids + (per_pin->dev_id - 1);
1389 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1393 /* have a second try; check the area over num_nids */
1394 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1395 if (!test_bit(i, &spec->pcm_bitmap))
1400 /* the last try; check the empty slots in pins */
1401 for (i = 0; i < spec->pcm_used; i++) {
1402 if (!test_bit(i, &spec->pcm_bitmap))
1408 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1409 struct hdmi_spec_per_pin *per_pin)
1413 /* pcm already be attached to the pin */
1416 idx = hdmi_find_pcm_slot(spec, per_pin);
1419 per_pin->pcm_idx = idx;
1420 per_pin->pcm = get_hdmi_pcm(spec, idx);
1421 set_bit(idx, &spec->pcm_bitmap);
1424 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1425 struct hdmi_spec_per_pin *per_pin)
1429 /* pcm already be detached from the pin */
1432 idx = per_pin->pcm_idx;
1433 per_pin->pcm_idx = -1;
1434 per_pin->pcm = NULL;
1435 if (idx >= 0 && idx < spec->pcm_used)
1436 clear_bit(idx, &spec->pcm_bitmap);
1439 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1440 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1444 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1445 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1450 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1452 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1453 struct hdmi_spec_per_pin *per_pin)
1455 struct hda_codec *codec = per_pin->codec;
1456 struct hda_pcm *pcm;
1457 struct hda_pcm_stream *hinfo;
1458 struct snd_pcm_substream *substream;
1462 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1463 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1468 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1471 /* hdmi audio only uses playback and one substream */
1472 hinfo = pcm->stream;
1473 substream = pcm->pcm->streams[0].substream;
1475 per_pin->cvt_nid = hinfo->nid;
1477 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1478 if (mux_idx < per_pin->num_mux_nids) {
1479 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1481 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1482 AC_VERB_SET_CONNECT_SEL,
1485 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1487 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1488 if (substream->runtime)
1489 per_pin->channels = substream->runtime->channels;
1490 per_pin->setup = true;
1491 per_pin->mux_idx = mux_idx;
1493 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1496 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1497 struct hdmi_spec_per_pin *per_pin)
1499 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1500 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1502 per_pin->chmap_set = false;
1503 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1505 per_pin->setup = false;
1506 per_pin->channels = 0;
1509 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1510 struct hdmi_spec_per_pin *per_pin)
1512 struct hdmi_spec *spec = codec->spec;
1514 if (per_pin->pcm_idx >= 0)
1515 return spec->pcm_rec[per_pin->pcm_idx].jack;
1520 /* update per_pin ELD from the given new ELD;
1521 * setup info frame and notification accordingly
1522 * also notify ELD kctl and report jack status changes
1524 static void update_eld(struct hda_codec *codec,
1525 struct hdmi_spec_per_pin *per_pin,
1526 struct hdmi_eld *eld,
1529 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1530 struct hdmi_spec *spec = codec->spec;
1531 struct snd_jack *pcm_jack;
1532 bool old_eld_valid = pin_eld->eld_valid;
1536 if (eld->eld_valid) {
1537 if (eld->eld_size <= 0 ||
1538 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1539 eld->eld_size) < 0) {
1540 eld->eld_valid = false;
1542 schedule_delayed_work(&per_pin->work,
1543 msecs_to_jiffies(300));
1549 if (!eld->eld_valid || eld->eld_size <= 0) {
1550 eld->eld_valid = false;
1554 /* for monitor disconnection, save pcm_idx firstly */
1555 pcm_idx = per_pin->pcm_idx;
1558 * pcm_idx >=0 before update_eld() means it is in monitor
1559 * disconnected event. Jack must be fetched before update_eld().
1561 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1563 if (spec->dyn_pcm_assign) {
1564 if (eld->eld_valid) {
1565 hdmi_attach_hda_pcm(spec, per_pin);
1566 hdmi_pcm_setup_pin(spec, per_pin);
1568 hdmi_pcm_reset_pin(spec, per_pin);
1569 hdmi_detach_hda_pcm(spec, per_pin);
1572 /* if pcm_idx == -1, it means this is in monitor connection event
1573 * we can get the correct pcm_idx now.
1576 pcm_idx = per_pin->pcm_idx;
1578 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1581 snd_hdmi_show_eld(codec, &eld->info);
1583 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1584 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1585 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1586 if (pin_eld->eld_size != eld->eld_size ||
1587 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1588 eld->eld_size) != 0)
1592 pin_eld->monitor_present = eld->monitor_present;
1593 pin_eld->eld_valid = eld->eld_valid;
1594 pin_eld->eld_size = eld->eld_size;
1596 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1598 pin_eld->info = eld->info;
1602 * Re-setup pin and infoframe. This is needed e.g. when
1603 * - sink is first plugged-in
1604 * - transcoder can change during stream playback on Haswell
1605 * and this can make HW reset converter selection on a pin.
1607 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1608 pin_cvt_fixup(codec, per_pin, 0);
1609 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1612 if (eld_changed && pcm_idx >= 0)
1613 snd_ctl_notify(codec->card,
1614 SNDRV_CTL_EVENT_MASK_VALUE |
1615 SNDRV_CTL_EVENT_MASK_INFO,
1616 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1618 if (eld_changed && pcm_jack)
1619 snd_jack_report(pcm_jack,
1620 (eld->monitor_present && eld->eld_valid) ?
1621 SND_JACK_AVOUT : 0);
1624 /* update ELD and jack state via HD-audio verbs */
1625 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1628 struct hda_codec *codec = per_pin->codec;
1629 struct hdmi_spec *spec = codec->spec;
1630 struct hdmi_eld *eld = &spec->temp_eld;
1631 struct device *dev = hda_codec_dev(codec);
1632 hda_nid_t pin_nid = per_pin->pin_nid;
1633 int dev_id = per_pin->dev_id;
1635 * Always execute a GetPinSense verb here, even when called from
1636 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1637 * response's PD bit is not the real PD value, but indicates that
1638 * the real PD value changed. An older version of the HD-audio
1639 * specification worked this way. Hence, we just ignore the data in
1640 * the unsolicited response to avoid custom WARs.
1646 if (dev->power.runtime_status == RPM_SUSPENDING)
1650 ret = snd_hda_power_up_pm(codec);
1651 if (ret < 0 && pm_runtime_suspended(dev))
1654 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1656 mutex_lock(&per_pin->lock);
1657 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1658 if (eld->monitor_present)
1659 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1661 eld->eld_valid = false;
1664 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1665 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1667 if (eld->eld_valid) {
1668 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1669 eld->eld_buffer, &eld->eld_size) < 0)
1670 eld->eld_valid = false;
1673 update_eld(codec, per_pin, eld, repoll);
1674 mutex_unlock(&per_pin->lock);
1676 snd_hda_power_down_pm(codec);
1679 #define I915_SILENT_RATE 48000
1680 #define I915_SILENT_CHANNELS 2
1681 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
1682 #define I915_SILENT_FORMAT_BITS 16
1683 #define I915_SILENT_FMT_MASK 0xf
1685 static void silent_stream_enable(struct hda_codec *codec,
1686 struct hdmi_spec_per_pin *per_pin)
1688 struct hdmi_spec *spec = codec->spec;
1689 struct hdmi_spec_per_cvt *per_cvt;
1690 int cvt_idx, pin_idx, err;
1691 unsigned int format;
1693 mutex_lock(&per_pin->lock);
1695 if (per_pin->setup) {
1696 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1700 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1701 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1703 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1707 per_cvt = get_cvt(spec, cvt_idx);
1708 per_cvt->assigned = 1;
1709 per_pin->cvt_nid = per_cvt->cvt_nid;
1710 per_pin->silent_stream = true;
1712 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1713 per_pin->pin_nid, per_cvt->cvt_nid);
1715 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1716 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1717 AC_VERB_SET_CONNECT_SEL,
1720 /* configure unused pins to choose other converters */
1721 pin_cvt_fixup(codec, per_pin, 0);
1723 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1724 per_pin->dev_id, I915_SILENT_RATE);
1726 /* trigger silent stream generation in hw */
1727 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
1728 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
1729 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1730 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1731 usleep_range(100, 200);
1732 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1734 per_pin->channels = I915_SILENT_CHANNELS;
1735 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1738 mutex_unlock(&per_pin->lock);
1741 static void silent_stream_disable(struct hda_codec *codec,
1742 struct hdmi_spec_per_pin *per_pin)
1744 struct hdmi_spec *spec = codec->spec;
1745 struct hdmi_spec_per_cvt *per_cvt;
1748 mutex_lock(&per_pin->lock);
1749 if (!per_pin->silent_stream)
1752 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1753 per_pin->pin_nid, per_pin->cvt_nid);
1755 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1756 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1757 per_cvt = get_cvt(spec, cvt_idx);
1758 per_cvt->assigned = 0;
1761 per_pin->cvt_nid = 0;
1762 per_pin->silent_stream = false;
1765 mutex_unlock(&per_pin->lock);
1768 /* update ELD and jack state via audio component */
1769 static void sync_eld_via_acomp(struct hda_codec *codec,
1770 struct hdmi_spec_per_pin *per_pin)
1772 struct hdmi_spec *spec = codec->spec;
1773 struct hdmi_eld *eld = &spec->temp_eld;
1774 bool monitor_prev, monitor_next;
1776 mutex_lock(&per_pin->lock);
1777 eld->monitor_present = false;
1778 monitor_prev = per_pin->sink_eld.monitor_present;
1779 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1780 per_pin->dev_id, &eld->monitor_present,
1781 eld->eld_buffer, ELD_MAX_SIZE);
1782 eld->eld_valid = (eld->eld_size > 0);
1783 update_eld(codec, per_pin, eld, 0);
1784 monitor_next = per_pin->sink_eld.monitor_present;
1785 mutex_unlock(&per_pin->lock);
1788 * Power-up will call hdmi_present_sense, so the PM calls
1789 * have to be done without mutex held.
1792 if (spec->send_silent_stream) {
1795 if (!monitor_prev && monitor_next) {
1796 pm_ret = snd_hda_power_up_pm(codec);
1799 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1801 silent_stream_enable(codec, per_pin);
1802 } else if (monitor_prev && !monitor_next) {
1803 silent_stream_disable(codec, per_pin);
1804 pm_ret = snd_hda_power_down_pm(codec);
1807 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1813 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1815 struct hda_codec *codec = per_pin->codec;
1817 if (!codec_has_acomp(codec))
1818 hdmi_present_sense_via_verbs(per_pin, repoll);
1820 sync_eld_via_acomp(codec, per_pin);
1823 static void hdmi_repoll_eld(struct work_struct *work)
1825 struct hdmi_spec_per_pin *per_pin =
1826 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1827 struct hda_codec *codec = per_pin->codec;
1828 struct hdmi_spec *spec = codec->spec;
1829 struct hda_jack_tbl *jack;
1831 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1834 jack->jack_dirty = 1;
1836 if (per_pin->repoll_count++ > 6)
1837 per_pin->repoll_count = 0;
1839 mutex_lock(&spec->pcm_lock);
1840 hdmi_present_sense(per_pin, per_pin->repoll_count);
1841 mutex_unlock(&spec->pcm_lock);
1844 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1846 struct hdmi_spec *spec = codec->spec;
1847 unsigned int caps, config;
1849 struct hdmi_spec_per_pin *per_pin;
1853 caps = snd_hda_query_pin_caps(codec, pin_nid);
1854 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1858 * For DP MST audio, Configuration Default is the same for
1859 * all device entries on the same pin
1861 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1862 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1863 !spec->force_connect)
1867 * To simplify the implementation, malloc all
1868 * the virtual pins in the initialization statically
1870 if (spec->intel_hsw_fixup) {
1872 * On Intel platforms, device entries number is
1873 * changed dynamically. If there is a DP MST
1874 * hub connected, the device entries number is 3.
1875 * Otherwise, it is 1.
1876 * Here we manually set dev_num to 3, so that
1877 * we can initialize all the device entries when
1878 * bootup statically.
1882 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1883 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1885 * spec->dev_num is the maxinum number of device entries
1886 * among all the pins
1888 spec->dev_num = (spec->dev_num > dev_num) ?
1889 spec->dev_num : dev_num;
1892 * If the platform doesn't support DP MST,
1893 * manually set dev_num to 1. This means
1894 * the pin has only one device entry.
1900 for (i = 0; i < dev_num; i++) {
1901 pin_idx = spec->num_pins;
1902 per_pin = snd_array_new(&spec->pins);
1907 if (spec->dyn_pcm_assign) {
1908 per_pin->pcm = NULL;
1909 per_pin->pcm_idx = -1;
1911 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1912 per_pin->pcm_idx = pin_idx;
1914 per_pin->pin_nid = pin_nid;
1915 per_pin->pin_nid_idx = spec->num_nids;
1916 per_pin->dev_id = i;
1917 per_pin->non_pcm = false;
1918 snd_hda_set_dev_select(codec, pin_nid, i);
1919 err = hdmi_read_pin_conn(codec, pin_idx);
1929 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1931 struct hdmi_spec *spec = codec->spec;
1932 struct hdmi_spec_per_cvt *per_cvt;
1936 chans = get_wcaps(codec, cvt_nid);
1937 chans = get_wcaps_channels(chans);
1939 per_cvt = snd_array_new(&spec->cvts);
1943 per_cvt->cvt_nid = cvt_nid;
1944 per_cvt->channels_min = 2;
1946 per_cvt->channels_max = chans;
1947 if (chans > spec->chmap.channels_max)
1948 spec->chmap.channels_max = chans;
1951 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1958 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1959 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1965 static const struct snd_pci_quirk force_connect_list[] = {
1966 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1967 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1968 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1969 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1970 SND_PCI_QUIRK(0x1043, 0x86ae, "ASUS", 1), /* Z170 PRO */
1971 SND_PCI_QUIRK(0x1043, 0x86c7, "ASUS", 1), /* Z170M PLUS */
1972 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
1973 SND_PCI_QUIRK(0x8086, 0x2060, "Intel NUC5CPYB", 1),
1974 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
1978 static int hdmi_parse_codec(struct hda_codec *codec)
1980 struct hdmi_spec *spec = codec->spec;
1981 hda_nid_t start_nid;
1984 const struct snd_pci_quirk *q;
1986 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1987 if (!start_nid || nodes < 0) {
1988 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1992 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1995 spec->force_connect = true;
1998 * hdmi_add_pin() assumes total amount of converters to
1999 * be known, so first discover all converters
2001 for (i = 0; i < nodes; i++) {
2002 hda_nid_t nid = start_nid + i;
2004 caps = get_wcaps(codec, nid);
2006 if (!(caps & AC_WCAP_DIGITAL))
2009 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2010 hdmi_add_cvt(codec, nid);
2013 /* discover audio pins */
2014 for (i = 0; i < nodes; i++) {
2015 hda_nid_t nid = start_nid + i;
2017 caps = get_wcaps(codec, nid);
2019 if (!(caps & AC_WCAP_DIGITAL))
2022 if (get_wcaps_type(caps) == AC_WID_PIN)
2023 hdmi_add_pin(codec, nid);
2031 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2033 struct hda_spdif_out *spdif;
2036 mutex_lock(&codec->spdif_mutex);
2037 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2038 /* Add sanity check to pass klockwork check.
2039 * This should never happen.
2041 if (WARN_ON(spdif == NULL)) {
2042 mutex_unlock(&codec->spdif_mutex);
2045 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2046 mutex_unlock(&codec->spdif_mutex);
2054 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2055 struct hda_codec *codec,
2056 unsigned int stream_tag,
2057 unsigned int format,
2058 struct snd_pcm_substream *substream)
2060 hda_nid_t cvt_nid = hinfo->nid;
2061 struct hdmi_spec *spec = codec->spec;
2063 struct hdmi_spec_per_pin *per_pin;
2064 struct snd_pcm_runtime *runtime = substream->runtime;
2069 mutex_lock(&spec->pcm_lock);
2070 pin_idx = hinfo_to_pin_index(codec, hinfo);
2071 if (spec->dyn_pcm_assign && pin_idx < 0) {
2072 /* when dyn_pcm_assign and pcm is not bound to a pin
2073 * skip pin setup and return 0 to make audio playback
2076 pin_cvt_fixup(codec, NULL, cvt_nid);
2077 snd_hda_codec_setup_stream(codec, cvt_nid,
2078 stream_tag, 0, format);
2082 if (snd_BUG_ON(pin_idx < 0)) {
2086 per_pin = get_pin(spec, pin_idx);
2088 /* Verify pin:cvt selections to avoid silent audio after S3.
2089 * After S3, the audio driver restores pin:cvt selections
2090 * but this can happen before gfx is ready and such selection
2091 * is overlooked by HW. Thus multiple pins can share a same
2092 * default convertor and mute control will affect each other,
2093 * which can cause a resumed audio playback become silent
2096 pin_cvt_fixup(codec, per_pin, 0);
2098 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2099 /* Todo: add DP1.2 MST audio support later */
2100 if (codec_has_acomp(codec))
2101 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2102 per_pin->dev_id, runtime->rate);
2104 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2105 mutex_lock(&per_pin->lock);
2106 per_pin->channels = substream->runtime->channels;
2107 per_pin->setup = true;
2109 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2110 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2112 snd_hda_codec_write(codec, cvt_nid, 0,
2113 AC_VERB_SET_STRIPE_CONTROL,
2117 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2118 mutex_unlock(&per_pin->lock);
2119 if (spec->dyn_pin_out) {
2120 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2122 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2123 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2124 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2125 AC_VERB_SET_PIN_WIDGET_CONTROL,
2129 /* snd_hda_set_dev_select() has been called before */
2130 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2131 per_pin->dev_id, stream_tag, format);
2133 mutex_unlock(&spec->pcm_lock);
2137 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2138 struct hda_codec *codec,
2139 struct snd_pcm_substream *substream)
2141 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2145 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2146 struct hda_codec *codec,
2147 struct snd_pcm_substream *substream)
2149 struct hdmi_spec *spec = codec->spec;
2150 int cvt_idx, pin_idx, pcm_idx;
2151 struct hdmi_spec_per_cvt *per_cvt;
2152 struct hdmi_spec_per_pin *per_pin;
2156 mutex_lock(&spec->pcm_lock);
2158 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2159 if (snd_BUG_ON(pcm_idx < 0)) {
2163 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2164 if (snd_BUG_ON(cvt_idx < 0)) {
2168 per_cvt = get_cvt(spec, cvt_idx);
2169 per_cvt->assigned = 0;
2172 azx_stream(get_azx_dev(substream))->stripe = 0;
2174 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2175 clear_bit(pcm_idx, &spec->pcm_in_use);
2176 pin_idx = hinfo_to_pin_index(codec, hinfo);
2177 if (spec->dyn_pcm_assign && pin_idx < 0)
2180 if (snd_BUG_ON(pin_idx < 0)) {
2184 per_pin = get_pin(spec, pin_idx);
2186 if (spec->dyn_pin_out) {
2187 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2189 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2190 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2191 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2192 AC_VERB_SET_PIN_WIDGET_CONTROL,
2196 mutex_lock(&per_pin->lock);
2197 per_pin->chmap_set = false;
2198 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2200 per_pin->setup = false;
2201 per_pin->channels = 0;
2202 mutex_unlock(&per_pin->lock);
2206 mutex_unlock(&spec->pcm_lock);
2211 static const struct hda_pcm_ops generic_ops = {
2212 .open = hdmi_pcm_open,
2213 .close = hdmi_pcm_close,
2214 .prepare = generic_hdmi_playback_pcm_prepare,
2215 .cleanup = generic_hdmi_playback_pcm_cleanup,
2218 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2220 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2221 struct hdmi_spec *spec = codec->spec;
2222 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2227 return per_pin->sink_eld.info.spk_alloc;
2230 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2231 unsigned char *chmap)
2233 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2234 struct hdmi_spec *spec = codec->spec;
2235 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2237 /* chmap is already set to 0 in caller */
2241 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2244 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2245 unsigned char *chmap, int prepared)
2247 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2248 struct hdmi_spec *spec = codec->spec;
2249 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2253 mutex_lock(&per_pin->lock);
2254 per_pin->chmap_set = true;
2255 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2257 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2258 mutex_unlock(&per_pin->lock);
2261 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2263 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2264 struct hdmi_spec *spec = codec->spec;
2265 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2267 return per_pin ? true:false;
2270 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2272 struct hdmi_spec *spec = codec->spec;
2276 * for non-mst mode, pcm number is the same as before
2277 * for DP MST mode without extra PCM, pcm number is same
2278 * for DP MST mode with extra PCMs, pcm number is
2279 * (nid number + dev_num - 1)
2280 * dev_num is the device entry number in a pin
2283 if (spec->dyn_pcm_no_legacy && codec->mst_no_extra_pcms)
2284 pcm_num = spec->num_cvts;
2285 else if (codec->mst_no_extra_pcms)
2286 pcm_num = spec->num_nids;
2288 pcm_num = spec->num_nids + spec->dev_num - 1;
2290 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2292 for (idx = 0; idx < pcm_num; idx++) {
2293 struct hda_pcm *info;
2294 struct hda_pcm_stream *pstr;
2296 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2300 spec->pcm_rec[idx].pcm = info;
2302 info->pcm_type = HDA_PCM_TYPE_HDMI;
2303 info->own_chmap = true;
2305 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2306 pstr->substreams = 1;
2307 pstr->ops = generic_ops;
2308 /* pcm number is less than 16 */
2309 if (spec->pcm_used >= 16)
2311 /* other pstr fields are set in open */
2317 static void free_hdmi_jack_priv(struct snd_jack *jack)
2319 struct hdmi_pcm *pcm = jack->private_data;
2324 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2326 char hdmi_str[32] = "HDMI/DP";
2327 struct hdmi_spec *spec = codec->spec;
2328 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2329 struct snd_jack *jack;
2330 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2334 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2335 if (!spec->dyn_pcm_assign &&
2336 !is_jack_detectable(codec, per_pin->pin_nid))
2337 strncat(hdmi_str, " Phantom",
2338 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2340 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2345 spec->pcm_rec[pcm_idx].jack = jack;
2346 jack->private_data = &spec->pcm_rec[pcm_idx];
2347 jack->private_free = free_hdmi_jack_priv;
2351 static int generic_hdmi_build_controls(struct hda_codec *codec)
2353 struct hdmi_spec *spec = codec->spec;
2355 int pin_idx, pcm_idx;
2357 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2358 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2359 /* no PCM: mark this for skipping permanently */
2360 set_bit(pcm_idx, &spec->pcm_bitmap);
2364 err = generic_hdmi_build_jack(codec, pcm_idx);
2368 /* create the spdif for each pcm
2369 * pin will be bound when monitor is connected
2371 if (spec->dyn_pcm_assign)
2372 err = snd_hda_create_dig_out_ctls(codec,
2373 0, spec->cvt_nids[0],
2376 struct hdmi_spec_per_pin *per_pin =
2377 get_pin(spec, pcm_idx);
2378 err = snd_hda_create_dig_out_ctls(codec,
2380 per_pin->mux_nids[0],
2385 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2387 dev = get_pcm_rec(spec, pcm_idx)->device;
2388 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2389 /* add control for ELD Bytes */
2390 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2396 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2397 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2398 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2400 pin_eld->eld_valid = false;
2401 hdmi_present_sense(per_pin, 0);
2404 /* add channel maps */
2405 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2406 struct hda_pcm *pcm;
2408 pcm = get_pcm_rec(spec, pcm_idx);
2409 if (!pcm || !pcm->pcm)
2411 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2419 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2421 struct hdmi_spec *spec = codec->spec;
2424 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2425 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2427 per_pin->codec = codec;
2428 mutex_init(&per_pin->lock);
2429 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2430 eld_proc_new(per_pin, pin_idx);
2435 static int generic_hdmi_init(struct hda_codec *codec)
2437 struct hdmi_spec *spec = codec->spec;
2440 mutex_lock(&spec->bind_lock);
2441 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2442 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2443 hda_nid_t pin_nid = per_pin->pin_nid;
2444 int dev_id = per_pin->dev_id;
2446 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2447 hdmi_init_pin(codec, pin_nid);
2448 if (codec_has_acomp(codec))
2450 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2453 mutex_unlock(&spec->bind_lock);
2457 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2459 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2460 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2463 static void hdmi_array_free(struct hdmi_spec *spec)
2465 snd_array_free(&spec->pins);
2466 snd_array_free(&spec->cvts);
2469 static void generic_spec_free(struct hda_codec *codec)
2471 struct hdmi_spec *spec = codec->spec;
2474 hdmi_array_free(spec);
2478 codec->dp_mst = false;
2481 static void generic_hdmi_free(struct hda_codec *codec)
2483 struct hdmi_spec *spec = codec->spec;
2484 int pin_idx, pcm_idx;
2486 if (spec->acomp_registered) {
2487 snd_hdac_acomp_exit(&codec->bus->core);
2488 } else if (codec_has_acomp(codec)) {
2489 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2491 codec->relaxed_resume = 0;
2493 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2494 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2495 cancel_delayed_work_sync(&per_pin->work);
2496 eld_proc_free(per_pin);
2499 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2500 if (spec->pcm_rec[pcm_idx].jack == NULL)
2502 if (spec->dyn_pcm_assign)
2503 snd_device_free(codec->card,
2504 spec->pcm_rec[pcm_idx].jack);
2506 spec->pcm_rec[pcm_idx].jack = NULL;
2509 generic_spec_free(codec);
2513 static int generic_hdmi_suspend(struct hda_codec *codec)
2515 struct hdmi_spec *spec = codec->spec;
2518 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2519 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2520 cancel_delayed_work_sync(&per_pin->work);
2525 static int generic_hdmi_resume(struct hda_codec *codec)
2527 struct hdmi_spec *spec = codec->spec;
2530 codec->patch_ops.init(codec);
2531 snd_hda_regmap_sync(codec);
2533 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2534 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2535 hdmi_present_sense(per_pin, 1);
2541 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2542 .init = generic_hdmi_init,
2543 .free = generic_hdmi_free,
2544 .build_pcms = generic_hdmi_build_pcms,
2545 .build_controls = generic_hdmi_build_controls,
2546 .unsol_event = hdmi_unsol_event,
2548 .suspend = generic_hdmi_suspend,
2549 .resume = generic_hdmi_resume,
2553 static const struct hdmi_ops generic_standard_hdmi_ops = {
2554 .pin_get_eld = hdmi_pin_get_eld,
2555 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2556 .pin_hbr_setup = hdmi_pin_hbr_setup,
2557 .setup_stream = hdmi_setup_stream,
2560 /* allocate codec->spec and assign/initialize generic parser ops */
2561 static int alloc_generic_hdmi(struct hda_codec *codec)
2563 struct hdmi_spec *spec;
2565 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2569 spec->codec = codec;
2570 spec->ops = generic_standard_hdmi_ops;
2571 spec->dev_num = 1; /* initialize to 1 */
2572 mutex_init(&spec->pcm_lock);
2573 mutex_init(&spec->bind_lock);
2574 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2576 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2577 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2578 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2579 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2582 hdmi_array_init(spec, 4);
2584 codec->patch_ops = generic_hdmi_patch_ops;
2589 /* generic HDMI parser */
2590 static int patch_generic_hdmi(struct hda_codec *codec)
2594 err = alloc_generic_hdmi(codec);
2598 err = hdmi_parse_codec(codec);
2600 generic_spec_free(codec);
2604 generic_hdmi_init_per_pins(codec);
2609 * generic audio component binding
2612 /* turn on / off the unsol event jack detection dynamically */
2613 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2614 int dev_id, bool use_acomp)
2616 struct hda_jack_tbl *tbl;
2618 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2620 /* clear unsol even if component notifier is used, or re-enable
2621 * if notifier is cleared
2623 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2624 snd_hda_codec_write_cache(codec, nid, 0,
2625 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2629 /* set up / clear component notifier dynamically */
2630 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2633 struct hdmi_spec *spec;
2636 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2637 mutex_lock(&spec->bind_lock);
2638 spec->use_acomp_notifier = use_acomp;
2639 spec->codec->relaxed_resume = use_acomp;
2640 spec->codec->bus->keep_power = 0;
2641 /* reprogram each jack detection logic depending on the notifier */
2642 for (i = 0; i < spec->num_pins; i++)
2643 reprogram_jack_detect(spec->codec,
2644 get_pin(spec, i)->pin_nid,
2645 get_pin(spec, i)->dev_id,
2647 mutex_unlock(&spec->bind_lock);
2650 /* enable / disable the notifier via master bind / unbind */
2651 static int generic_acomp_master_bind(struct device *dev,
2652 struct drm_audio_component *acomp)
2654 generic_acomp_notifier_set(acomp, true);
2658 static void generic_acomp_master_unbind(struct device *dev,
2659 struct drm_audio_component *acomp)
2661 generic_acomp_notifier_set(acomp, false);
2664 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2665 static int match_bound_vga(struct device *dev, int subtype, void *data)
2667 struct hdac_bus *bus = data;
2668 struct pci_dev *pci, *master;
2670 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2672 master = to_pci_dev(bus->dev);
2673 pci = to_pci_dev(dev);
2674 return master->bus == pci->bus;
2677 /* audio component notifier for AMD/Nvidia HDMI codecs */
2678 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2680 struct hda_codec *codec = audio_ptr;
2681 struct hdmi_spec *spec = codec->spec;
2682 hda_nid_t pin_nid = spec->port2pin(codec, port);
2686 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2688 /* skip notification during system suspend (but not in runtime PM);
2689 * the state will be updated at resume
2691 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2694 check_presence_and_report(codec, pin_nid, dev_id);
2697 /* set up the private drm_audio_ops from the template */
2698 static void setup_drm_audio_ops(struct hda_codec *codec,
2699 const struct drm_audio_component_audio_ops *ops)
2701 struct hdmi_spec *spec = codec->spec;
2703 spec->drm_audio_ops.audio_ptr = codec;
2704 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2705 * will call pin_eld_notify with using audio_ptr pointer
2706 * We need make sure audio_ptr is really setup
2709 spec->drm_audio_ops.pin2port = ops->pin2port;
2710 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2711 spec->drm_audio_ops.master_bind = ops->master_bind;
2712 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2715 /* initialize the generic HDMI audio component */
2716 static void generic_acomp_init(struct hda_codec *codec,
2717 const struct drm_audio_component_audio_ops *ops,
2718 int (*port2pin)(struct hda_codec *, int))
2720 struct hdmi_spec *spec = codec->spec;
2722 if (!enable_acomp) {
2723 codec_info(codec, "audio component disabled by module option\n");
2727 spec->port2pin = port2pin;
2728 setup_drm_audio_ops(codec, ops);
2729 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2730 match_bound_vga, 0)) {
2731 spec->acomp_registered = true;
2736 * Intel codec parsers and helpers
2739 #define INTEL_GET_VENDOR_VERB 0xf81
2740 #define INTEL_SET_VENDOR_VERB 0x781
2741 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2742 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2744 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2747 unsigned int vendor_param;
2748 struct hdmi_spec *spec = codec->spec;
2750 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2751 INTEL_GET_VENDOR_VERB, 0);
2752 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2755 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2756 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2757 INTEL_SET_VENDOR_VERB, vendor_param);
2758 if (vendor_param == -1)
2762 snd_hda_codec_update_widgets(codec);
2765 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2767 unsigned int vendor_param;
2768 struct hdmi_spec *spec = codec->spec;
2770 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2771 INTEL_GET_VENDOR_VERB, 0);
2772 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2775 /* enable DP1.2 mode */
2776 vendor_param |= INTEL_EN_DP12;
2777 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2778 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2779 INTEL_SET_VENDOR_VERB, vendor_param);
2782 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2783 * Otherwise you may get severe h/w communication errors.
2785 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2786 unsigned int power_state)
2788 if (power_state == AC_PWRST_D0) {
2789 intel_haswell_enable_all_pins(codec, false);
2790 intel_haswell_fixup_enable_dp12(codec);
2793 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2794 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2797 /* There is a fixed mapping between audio pin node and display port.
2798 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2799 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2800 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2801 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2804 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2805 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2806 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2808 static int intel_base_nid(struct hda_codec *codec)
2810 switch (codec->core.vendor_id) {
2811 case 0x80860054: /* ILK */
2812 case 0x80862804: /* ILK */
2813 case 0x80862882: /* VLV */
2820 static int intel_pin2port(void *audio_ptr, int pin_nid)
2822 struct hda_codec *codec = audio_ptr;
2823 struct hdmi_spec *spec = codec->spec;
2826 if (!spec->port_num) {
2827 base_nid = intel_base_nid(codec);
2828 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2830 return pin_nid - base_nid + 1;
2834 * looking for the pin number in the mapping table and return
2835 * the index which indicate the port number
2837 for (i = 0; i < spec->port_num; i++) {
2838 if (pin_nid == spec->port_map[i])
2842 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2846 static int intel_port2pin(struct hda_codec *codec, int port)
2848 struct hdmi_spec *spec = codec->spec;
2850 if (!spec->port_num) {
2851 /* we assume only from port-B to port-D */
2852 if (port < 1 || port > 3)
2854 return port + intel_base_nid(codec) - 1;
2857 if (port < 0 || port >= spec->port_num)
2859 return spec->port_map[port];
2862 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2864 struct hda_codec *codec = audio_ptr;
2868 pin_nid = intel_port2pin(codec, port);
2871 /* skip notification during system suspend (but not in runtime PM);
2872 * the state will be updated at resume
2874 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2877 snd_hdac_i915_set_bclk(&codec->bus->core);
2878 check_presence_and_report(codec, pin_nid, dev_id);
2881 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2882 .pin2port = intel_pin2port,
2883 .pin_eld_notify = intel_pin_eld_notify,
2886 /* register i915 component pin_eld_notify callback */
2887 static void register_i915_notifier(struct hda_codec *codec)
2889 struct hdmi_spec *spec = codec->spec;
2891 spec->use_acomp_notifier = true;
2892 spec->port2pin = intel_port2pin;
2893 setup_drm_audio_ops(codec, &intel_audio_ops);
2894 snd_hdac_acomp_register_notifier(&codec->bus->core,
2895 &spec->drm_audio_ops);
2896 /* no need for forcible resume for jack check thanks to notifier */
2897 codec->relaxed_resume = 1;
2900 /* setup_stream ops override for HSW+ */
2901 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2902 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2905 haswell_verify_D0(codec, cvt_nid, pin_nid);
2906 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2907 stream_tag, format);
2910 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2911 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2912 struct hdmi_spec_per_pin *per_pin,
2916 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2917 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2919 intel_verify_pin_cvt_connect(codec, per_pin);
2920 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2921 per_pin->dev_id, per_pin->mux_idx);
2923 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2927 /* precondition and allocation for Intel codecs */
2928 static int alloc_intel_hdmi(struct hda_codec *codec)
2932 /* requires i915 binding */
2933 if (!codec->bus->core.audio_component) {
2934 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2935 /* set probe_id here to prevent generic fallback binding */
2936 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2940 err = alloc_generic_hdmi(codec);
2943 /* no need to handle unsol events */
2944 codec->patch_ops.unsol_event = NULL;
2948 /* parse and post-process for Intel codecs */
2949 static int parse_intel_hdmi(struct hda_codec *codec)
2951 int err, retries = 3;
2954 err = hdmi_parse_codec(codec);
2955 } while (err < 0 && retries--);
2958 generic_spec_free(codec);
2962 generic_hdmi_init_per_pins(codec);
2963 register_i915_notifier(codec);
2967 /* Intel Haswell and onwards; audio component with eld notifier */
2968 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2969 const int *port_map, int port_num)
2971 struct hdmi_spec *spec;
2974 err = alloc_intel_hdmi(codec);
2978 codec->dp_mst = true;
2979 spec->dyn_pcm_assign = true;
2980 spec->vendor_nid = vendor_nid;
2981 spec->port_map = port_map;
2982 spec->port_num = port_num;
2983 spec->intel_hsw_fixup = true;
2985 intel_haswell_enable_all_pins(codec, true);
2986 intel_haswell_fixup_enable_dp12(codec);
2988 codec->display_power_control = 1;
2990 codec->patch_ops.set_power_state = haswell_set_power_state;
2991 codec->depop_delay = 0;
2992 codec->auto_runtime_pm = 1;
2994 spec->ops.setup_stream = i915_hsw_setup_stream;
2995 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2998 * Enable silent stream feature, if it is enabled via
2999 * module param or Kconfig option
3001 if (enable_silent_stream)
3002 spec->send_silent_stream = true;
3004 return parse_intel_hdmi(codec);
3007 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3009 return intel_hsw_common_init(codec, 0x08, NULL, 0);
3012 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3014 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
3017 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3020 * pin to port mapping table where the value indicate the pin number and
3021 * the index indicate the port number.
3023 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3025 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
3028 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3031 * pin to port mapping table where the value indicate the pin number and
3032 * the index indicate the port number.
3034 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3037 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
3039 struct hdmi_spec *spec = codec->spec;
3041 spec->dyn_pcm_no_legacy = true;
3047 /* Intel Baytrail and Braswell; with eld notifier */
3048 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3050 struct hdmi_spec *spec;
3053 err = alloc_intel_hdmi(codec);
3058 /* For Valleyview/Cherryview, only the display codec is in the display
3059 * power well and can use link_power ops to request/release the power.
3061 codec->display_power_control = 1;
3063 codec->depop_delay = 0;
3064 codec->auto_runtime_pm = 1;
3066 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3068 return parse_intel_hdmi(codec);
3071 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3072 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3076 err = alloc_intel_hdmi(codec);
3079 return parse_intel_hdmi(codec);
3083 * Shared non-generic implementations
3086 static int simple_playback_build_pcms(struct hda_codec *codec)
3088 struct hdmi_spec *spec = codec->spec;
3089 struct hda_pcm *info;
3091 struct hda_pcm_stream *pstr;
3092 struct hdmi_spec_per_cvt *per_cvt;
3094 per_cvt = get_cvt(spec, 0);
3095 chans = get_wcaps(codec, per_cvt->cvt_nid);
3096 chans = get_wcaps_channels(chans);
3098 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3101 spec->pcm_rec[0].pcm = info;
3102 info->pcm_type = HDA_PCM_TYPE_HDMI;
3103 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3104 *pstr = spec->pcm_playback;
3105 pstr->nid = per_cvt->cvt_nid;
3106 if (pstr->channels_max <= 2 && chans && chans <= 16)
3107 pstr->channels_max = chans;
3112 /* unsolicited event for jack sensing */
3113 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3116 snd_hda_jack_set_dirty_all(codec);
3117 snd_hda_jack_report_sync(codec);
3120 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3121 * as long as spec->pins[] is set correctly
3123 #define simple_hdmi_build_jack generic_hdmi_build_jack
3125 static int simple_playback_build_controls(struct hda_codec *codec)
3127 struct hdmi_spec *spec = codec->spec;
3128 struct hdmi_spec_per_cvt *per_cvt;
3131 per_cvt = get_cvt(spec, 0);
3132 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3137 return simple_hdmi_build_jack(codec, 0);
3140 static int simple_playback_init(struct hda_codec *codec)
3142 struct hdmi_spec *spec = codec->spec;
3143 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3144 hda_nid_t pin = per_pin->pin_nid;
3146 snd_hda_codec_write(codec, pin, 0,
3147 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3148 /* some codecs require to unmute the pin */
3149 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3150 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3152 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3156 static void simple_playback_free(struct hda_codec *codec)
3158 struct hdmi_spec *spec = codec->spec;
3160 hdmi_array_free(spec);
3165 * Nvidia specific implementations
3168 #define Nv_VERB_SET_Channel_Allocation 0xF79
3169 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3170 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3171 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3173 #define nvhdmi_master_con_nid_7x 0x04
3174 #define nvhdmi_master_pin_nid_7x 0x05
3176 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3177 /*front, rear, clfe, rear_surr */
3181 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3182 /* set audio protect on */
3183 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3184 /* enable digital output on pin widget */
3185 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3189 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3190 /* set audio protect on */
3191 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3192 /* enable digital output on pin widget */
3193 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3194 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3195 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3196 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3197 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3201 #ifdef LIMITED_RATE_FMT_SUPPORT
3202 /* support only the safe format and rate */
3203 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3204 #define SUPPORTED_MAXBPS 16
3205 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3207 /* support all rates and formats */
3208 #define SUPPORTED_RATES \
3209 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3210 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3211 SNDRV_PCM_RATE_192000)
3212 #define SUPPORTED_MAXBPS 24
3213 #define SUPPORTED_FORMATS \
3214 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3217 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3219 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3223 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3225 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3229 static const unsigned int channels_2_6_8[] = {
3233 static const unsigned int channels_2_8[] = {
3237 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3238 .count = ARRAY_SIZE(channels_2_6_8),
3239 .list = channels_2_6_8,
3243 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3244 .count = ARRAY_SIZE(channels_2_8),
3245 .list = channels_2_8,
3249 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3250 struct hda_codec *codec,
3251 struct snd_pcm_substream *substream)
3253 struct hdmi_spec *spec = codec->spec;
3254 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3256 switch (codec->preset->vendor_id) {
3261 hw_constraints_channels = &hw_constraints_2_8_channels;
3264 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3270 if (hw_constraints_channels != NULL) {
3271 snd_pcm_hw_constraint_list(substream->runtime, 0,
3272 SNDRV_PCM_HW_PARAM_CHANNELS,
3273 hw_constraints_channels);
3275 snd_pcm_hw_constraint_step(substream->runtime, 0,
3276 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3279 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3282 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3283 struct hda_codec *codec,
3284 struct snd_pcm_substream *substream)
3286 struct hdmi_spec *spec = codec->spec;
3287 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3290 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3291 struct hda_codec *codec,
3292 unsigned int stream_tag,
3293 unsigned int format,
3294 struct snd_pcm_substream *substream)
3296 struct hdmi_spec *spec = codec->spec;
3297 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3298 stream_tag, format, substream);
3301 static const struct hda_pcm_stream simple_pcm_playback = {
3306 .open = simple_playback_pcm_open,
3307 .close = simple_playback_pcm_close,
3308 .prepare = simple_playback_pcm_prepare
3312 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3313 .build_controls = simple_playback_build_controls,
3314 .build_pcms = simple_playback_build_pcms,
3315 .init = simple_playback_init,
3316 .free = simple_playback_free,
3317 .unsol_event = simple_hdmi_unsol_event,
3320 static int patch_simple_hdmi(struct hda_codec *codec,
3321 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3323 struct hdmi_spec *spec;
3324 struct hdmi_spec_per_cvt *per_cvt;
3325 struct hdmi_spec_per_pin *per_pin;
3327 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3331 spec->codec = codec;
3333 hdmi_array_init(spec, 1);
3335 spec->multiout.num_dacs = 0; /* no analog */
3336 spec->multiout.max_channels = 2;
3337 spec->multiout.dig_out_nid = cvt_nid;
3340 per_pin = snd_array_new(&spec->pins);
3341 per_cvt = snd_array_new(&spec->cvts);
3342 if (!per_pin || !per_cvt) {
3343 simple_playback_free(codec);
3346 per_cvt->cvt_nid = cvt_nid;
3347 per_pin->pin_nid = pin_nid;
3348 spec->pcm_playback = simple_pcm_playback;
3350 codec->patch_ops = simple_hdmi_patch_ops;
3355 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3358 unsigned int chanmask;
3359 int chan = channels ? (channels - 1) : 1;
3378 /* Set the audio infoframe channel allocation and checksum fields. The
3379 * channel count is computed implicitly by the hardware. */
3380 snd_hda_codec_write(codec, 0x1, 0,
3381 Nv_VERB_SET_Channel_Allocation, chanmask);
3383 snd_hda_codec_write(codec, 0x1, 0,
3384 Nv_VERB_SET_Info_Frame_Checksum,
3385 (0x71 - chan - chanmask));
3388 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3389 struct hda_codec *codec,
3390 struct snd_pcm_substream *substream)
3392 struct hdmi_spec *spec = codec->spec;
3395 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3396 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3397 for (i = 0; i < 4; i++) {
3398 /* set the stream id */
3399 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3400 AC_VERB_SET_CHANNEL_STREAMID, 0);
3401 /* set the stream format */
3402 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3403 AC_VERB_SET_STREAM_FORMAT, 0);
3406 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3407 * streams are disabled. */
3408 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3410 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3413 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3414 struct hda_codec *codec,
3415 unsigned int stream_tag,
3416 unsigned int format,
3417 struct snd_pcm_substream *substream)
3420 unsigned int dataDCC2, channel_id;
3422 struct hdmi_spec *spec = codec->spec;
3423 struct hda_spdif_out *spdif;
3424 struct hdmi_spec_per_cvt *per_cvt;
3426 mutex_lock(&codec->spdif_mutex);
3427 per_cvt = get_cvt(spec, 0);
3428 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3430 chs = substream->runtime->channels;
3434 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3435 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3436 snd_hda_codec_write(codec,
3437 nvhdmi_master_con_nid_7x,
3439 AC_VERB_SET_DIGI_CONVERT_1,
3440 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3442 /* set the stream id */
3443 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3444 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3446 /* set the stream format */
3447 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3448 AC_VERB_SET_STREAM_FORMAT, format);
3450 /* turn on again (if needed) */
3451 /* enable and set the channel status audio/data flag */
3452 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3453 snd_hda_codec_write(codec,
3454 nvhdmi_master_con_nid_7x,
3456 AC_VERB_SET_DIGI_CONVERT_1,
3457 spdif->ctls & 0xff);
3458 snd_hda_codec_write(codec,
3459 nvhdmi_master_con_nid_7x,
3461 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3464 for (i = 0; i < 4; i++) {
3470 /* turn off SPDIF once;
3471 *otherwise the IEC958 bits won't be updated
3473 if (codec->spdif_status_reset &&
3474 (spdif->ctls & AC_DIG1_ENABLE))
3475 snd_hda_codec_write(codec,
3476 nvhdmi_con_nids_7x[i],
3478 AC_VERB_SET_DIGI_CONVERT_1,
3479 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3480 /* set the stream id */
3481 snd_hda_codec_write(codec,
3482 nvhdmi_con_nids_7x[i],
3484 AC_VERB_SET_CHANNEL_STREAMID,
3485 (stream_tag << 4) | channel_id);
3486 /* set the stream format */
3487 snd_hda_codec_write(codec,
3488 nvhdmi_con_nids_7x[i],
3490 AC_VERB_SET_STREAM_FORMAT,
3492 /* turn on again (if needed) */
3493 /* enable and set the channel status audio/data flag */
3494 if (codec->spdif_status_reset &&
3495 (spdif->ctls & AC_DIG1_ENABLE)) {
3496 snd_hda_codec_write(codec,
3497 nvhdmi_con_nids_7x[i],
3499 AC_VERB_SET_DIGI_CONVERT_1,
3500 spdif->ctls & 0xff);
3501 snd_hda_codec_write(codec,
3502 nvhdmi_con_nids_7x[i],
3504 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3508 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3510 mutex_unlock(&codec->spdif_mutex);
3514 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3518 .nid = nvhdmi_master_con_nid_7x,
3519 .rates = SUPPORTED_RATES,
3520 .maxbps = SUPPORTED_MAXBPS,
3521 .formats = SUPPORTED_FORMATS,
3523 .open = simple_playback_pcm_open,
3524 .close = nvhdmi_8ch_7x_pcm_close,
3525 .prepare = nvhdmi_8ch_7x_pcm_prepare
3529 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3531 struct hdmi_spec *spec;
3532 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3533 nvhdmi_master_pin_nid_7x);
3537 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3538 /* override the PCM rates, etc, as the codec doesn't give full list */
3540 spec->pcm_playback.rates = SUPPORTED_RATES;
3541 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3542 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3543 spec->nv_dp_workaround = true;
3547 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3549 struct hdmi_spec *spec = codec->spec;
3550 int err = simple_playback_build_pcms(codec);
3552 struct hda_pcm *info = get_pcm_rec(spec, 0);
3553 info->own_chmap = true;
3558 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3560 struct hdmi_spec *spec = codec->spec;
3561 struct hda_pcm *info;
3562 struct snd_pcm_chmap *chmap;
3565 err = simple_playback_build_controls(codec);
3569 /* add channel maps */
3570 info = get_pcm_rec(spec, 0);
3571 err = snd_pcm_add_chmap_ctls(info->pcm,
3572 SNDRV_PCM_STREAM_PLAYBACK,
3573 snd_pcm_alt_chmaps, 8, 0, &chmap);
3576 switch (codec->preset->vendor_id) {
3581 chmap->channel_mask = (1U << 2) | (1U << 8);
3584 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3589 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3591 struct hdmi_spec *spec;
3592 int err = patch_nvhdmi_2ch(codec);
3596 spec->multiout.max_channels = 8;
3597 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3598 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3599 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3600 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3602 /* Initialize the audio infoframe channel mask and checksum to something
3604 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3610 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3614 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3615 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3617 if (cap->ca_index == 0x00 && channels == 2)
3618 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3620 /* If the speaker allocation matches the channel count, it is OK. */
3621 if (cap->channels != channels)
3624 /* all channels are remappable freely */
3625 return SNDRV_CTL_TLVT_CHMAP_VAR;
3628 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3629 int ca, int chs, unsigned char *map)
3631 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3637 /* map from pin NID to port; port is 0-based */
3638 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3639 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3644 /* reverse-map from port to pin NID: see above */
3645 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3650 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3651 .pin2port = nvhdmi_pin2port,
3652 .pin_eld_notify = generic_acomp_pin_eld_notify,
3653 .master_bind = generic_acomp_master_bind,
3654 .master_unbind = generic_acomp_master_unbind,
3657 static int patch_nvhdmi(struct hda_codec *codec)
3659 struct hdmi_spec *spec;
3662 err = alloc_generic_hdmi(codec);
3665 codec->dp_mst = true;
3668 spec->dyn_pcm_assign = true;
3670 err = hdmi_parse_codec(codec);
3672 generic_spec_free(codec);
3676 generic_hdmi_init_per_pins(codec);
3678 spec->dyn_pin_out = true;
3680 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3681 nvhdmi_chmap_cea_alloc_validate_get_type;
3682 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3683 spec->nv_dp_workaround = true;
3685 codec->link_down_at_suspend = 1;
3687 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3692 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3694 struct hdmi_spec *spec;
3697 err = patch_generic_hdmi(codec);
3702 spec->dyn_pin_out = true;
3704 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3705 nvhdmi_chmap_cea_alloc_validate_get_type;
3706 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3707 spec->nv_dp_workaround = true;
3709 codec->link_down_at_suspend = 1;
3715 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3716 * accessed using vendor-defined verbs. These registers can be used for
3717 * interoperability between the HDA and HDMI drivers.
3720 /* Audio Function Group node */
3721 #define NVIDIA_AFG_NID 0x01
3724 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3725 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3726 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3727 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3728 * additional bit (at position 30) to signal the validity of the format.
3730 * | 31 | 30 | 29 16 | 15 0 |
3731 * +---------+-------+--------+--------+
3732 * | TRIGGER | VALID | UNUSED | FORMAT |
3733 * +-----------------------------------|
3735 * Note that for the trigger bit to take effect it needs to change value
3736 * (i.e. it needs to be toggled).
3738 #define NVIDIA_GET_SCRATCH0 0xfa6
3739 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3740 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3741 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3742 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3743 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3744 #define NVIDIA_SCRATCH_VALID (1 << 6)
3746 #define NVIDIA_GET_SCRATCH1 0xfab
3747 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3748 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3749 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3750 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3753 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3754 * the format is invalidated so that the HDMI codec can be disabled.
3756 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3760 /* bits [31:30] contain the trigger and valid bits */
3761 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3762 NVIDIA_GET_SCRATCH0, 0);
3763 value = (value >> 24) & 0xff;
3765 /* bits [15:0] are used to store the HDA format */
3766 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3767 NVIDIA_SET_SCRATCH0_BYTE0,
3768 (format >> 0) & 0xff);
3769 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3770 NVIDIA_SET_SCRATCH0_BYTE1,
3771 (format >> 8) & 0xff);
3773 /* bits [16:24] are unused */
3774 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3775 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3778 * Bit 30 signals that the data is valid and hence that HDMI audio can
3782 value &= ~NVIDIA_SCRATCH_VALID;
3784 value |= NVIDIA_SCRATCH_VALID;
3787 * Whenever the trigger bit is toggled, an interrupt is raised in the
3788 * HDMI codec. The HDMI driver will use that as trigger to update its
3791 value ^= NVIDIA_SCRATCH_TRIGGER;
3793 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3794 NVIDIA_SET_SCRATCH0_BYTE3, value);
3797 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3798 struct hda_codec *codec,
3799 unsigned int stream_tag,
3800 unsigned int format,
3801 struct snd_pcm_substream *substream)
3805 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3810 /* notify the HDMI codec of the format change */
3811 tegra_hdmi_set_format(codec, format);
3816 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3817 struct hda_codec *codec,
3818 struct snd_pcm_substream *substream)
3820 /* invalidate the format in the HDMI codec */
3821 tegra_hdmi_set_format(codec, 0);
3823 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3826 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3828 struct hdmi_spec *spec = codec->spec;
3831 for (i = 0; i < spec->num_pins; i++) {
3832 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3834 if (pcm->pcm_type == type)
3841 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3843 struct hda_pcm_stream *stream;
3844 struct hda_pcm *pcm;
3847 err = generic_hdmi_build_pcms(codec);
3851 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3856 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3857 * codec about format changes.
3859 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3860 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3861 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3866 static int patch_tegra_hdmi(struct hda_codec *codec)
3868 struct hdmi_spec *spec;
3871 err = patch_generic_hdmi(codec);
3875 codec->depop_delay = 10;
3876 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3878 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3879 nvhdmi_chmap_cea_alloc_validate_get_type;
3880 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3881 spec->nv_dp_workaround = true;
3887 * ATI/AMD-specific implementations
3890 #define is_amdhdmi_rev3_or_later(codec) \
3891 ((codec)->core.vendor_id == 0x1002aa01 && \
3892 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3893 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3895 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3896 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3897 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3898 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3899 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3900 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3901 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3902 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3903 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3904 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3905 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3906 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3907 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3908 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3909 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3910 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3911 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3912 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3913 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3914 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3915 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3916 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3917 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3918 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3919 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3921 /* AMD specific HDA cvt verbs */
3922 #define ATI_VERB_SET_RAMP_RATE 0x770
3923 #define ATI_VERB_GET_RAMP_RATE 0xf70
3925 #define ATI_OUT_ENABLE 0x1
3927 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3928 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3930 #define ATI_HBR_CAPABLE 0x01
3931 #define ATI_HBR_ENABLE 0x10
3933 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3934 int dev_id, unsigned char *buf, int *eld_size)
3936 WARN_ON(dev_id != 0);
3937 /* call hda_eld.c ATI/AMD-specific function */
3938 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3939 is_amdhdmi_rev3_or_later(codec));
3942 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3943 hda_nid_t pin_nid, int dev_id, int ca,
3944 int active_channels, int conn_type)
3946 WARN_ON(dev_id != 0);
3947 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3950 static int atihdmi_paired_swap_fc_lfe(int pos)
3953 * ATI/AMD have automatic FC/LFE swap built-in
3954 * when in pairwise mapping mode.
3958 /* see channel_allocations[].speakers[] */
3967 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3968 int ca, int chs, unsigned char *map)
3970 struct hdac_cea_channel_speaker_allocation *cap;
3973 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3975 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3976 for (i = 0; i < chs; ++i) {
3977 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3979 bool companion_ok = false;
3984 for (j = 0 + i % 2; j < 8; j += 2) {
3985 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3986 if (cap->speakers[chan_idx] == mask) {
3987 /* channel is in a supported position */
3990 if (i % 2 == 0 && i + 1 < chs) {
3991 /* even channel, check the odd companion */
3992 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3993 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3994 int comp_mask_act = cap->speakers[comp_chan_idx];
3996 if (comp_mask_req == comp_mask_act)
3997 companion_ok = true;
4009 i++; /* companion channel already checked */
4015 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4016 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4018 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4020 int ati_channel_setup = 0;
4025 if (!has_amd_full_remap_support(codec)) {
4026 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4028 /* In case this is an odd slot but without stream channel, do not
4029 * disable the slot since the corresponding even slot could have a
4030 * channel. In case neither have a channel, the slot pair will be
4031 * disabled when this function is called for the even slot. */
4032 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4035 hdmi_slot -= hdmi_slot % 2;
4037 if (stream_channel != 0xf)
4038 stream_channel -= stream_channel % 2;
4041 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4043 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4045 if (stream_channel != 0xf)
4046 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4048 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4051 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4052 hda_nid_t pin_nid, int asp_slot)
4054 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4055 bool was_odd = false;
4056 int ati_asp_slot = asp_slot;
4058 int ati_channel_setup;
4063 if (!has_amd_full_remap_support(codec)) {
4064 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4065 if (ati_asp_slot % 2 != 0) {
4071 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4073 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4075 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4078 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4081 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4082 struct hdac_chmap *chmap,
4083 struct hdac_cea_channel_speaker_allocation *cap,
4089 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4090 * we need to take that into account (a single channel may take 2
4091 * channel slots if we need to carry a silent channel next to it).
4092 * On Rev3+ AMD codecs this function is not used.
4096 /* We only produce even-numbered channel count TLVs */
4097 if ((channels % 2) != 0)
4100 for (c = 0; c < 7; c += 2) {
4101 if (cap->speakers[c] || cap->speakers[c+1])
4105 if (chanpairs * 2 != channels)
4108 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4111 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4112 struct hdac_cea_channel_speaker_allocation *cap,
4113 unsigned int *chmap, int channels)
4115 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4119 for (c = 7; c >= 0; c--) {
4120 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4121 int spk = cap->speakers[chan];
4123 /* add N/A channel if the companion channel is occupied */
4124 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4125 chmap[count++] = SNDRV_CHMAP_NA;
4130 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4133 WARN_ON(count != channels);
4136 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4137 int dev_id, bool hbr)
4139 int hbr_ctl, hbr_ctl_new;
4141 WARN_ON(dev_id != 0);
4143 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4144 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4146 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4148 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4151 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4153 hbr_ctl == hbr_ctl_new ? "" : "new-",
4156 if (hbr_ctl != hbr_ctl_new)
4157 snd_hda_codec_write(codec, pin_nid, 0,
4158 ATI_VERB_SET_HBR_CONTROL,
4167 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4168 hda_nid_t pin_nid, int dev_id,
4169 u32 stream_tag, int format)
4171 if (is_amdhdmi_rev3_or_later(codec)) {
4172 int ramp_rate = 180; /* default as per AMD spec */
4173 /* disable ramp-up/down for non-pcm as per AMD spec */
4174 if (format & AC_FMT_TYPE_NON_PCM)
4177 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4180 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4181 stream_tag, format);
4185 static int atihdmi_init(struct hda_codec *codec)
4187 struct hdmi_spec *spec = codec->spec;
4190 err = generic_hdmi_init(codec);
4195 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4196 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4198 /* make sure downmix information in infoframe is zero */
4199 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4201 /* enable channel-wise remap mode if supported */
4202 if (has_amd_full_remap_support(codec))
4203 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4204 ATI_VERB_SET_MULTICHANNEL_MODE,
4205 ATI_MULTICHANNEL_MODE_SINGLE);
4207 codec->auto_runtime_pm = 1;
4212 /* map from pin NID to port; port is 0-based */
4213 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4214 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4216 return pin_nid / 2 - 1;
4219 /* reverse-map from port to pin NID: see above */
4220 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4222 return port * 2 + 3;
4225 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4226 .pin2port = atihdmi_pin2port,
4227 .pin_eld_notify = generic_acomp_pin_eld_notify,
4228 .master_bind = generic_acomp_master_bind,
4229 .master_unbind = generic_acomp_master_unbind,
4232 static int patch_atihdmi(struct hda_codec *codec)
4234 struct hdmi_spec *spec;
4235 struct hdmi_spec_per_cvt *per_cvt;
4238 err = patch_generic_hdmi(codec);
4243 codec->patch_ops.init = atihdmi_init;
4247 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4248 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4249 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4250 spec->ops.setup_stream = atihdmi_setup_stream;
4252 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4253 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4255 if (!has_amd_full_remap_support(codec)) {
4256 /* override to ATI/AMD-specific versions with pairwise mapping */
4257 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4258 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4259 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4260 atihdmi_paired_cea_alloc_to_tlv_chmap;
4261 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4264 /* ATI/AMD converters do not advertise all of their capabilities */
4265 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4266 per_cvt = get_cvt(spec, cvt_idx);
4267 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4268 per_cvt->rates |= SUPPORTED_RATES;
4269 per_cvt->formats |= SUPPORTED_FORMATS;
4270 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4273 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4275 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4276 * the link-down as is. Tell the core to allow it.
4278 codec->link_down_at_suspend = 1;
4280 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4285 /* VIA HDMI Implementation */
4286 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4287 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4289 static int patch_via_hdmi(struct hda_codec *codec)
4291 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4294 static int patch_gf_hdmi(struct hda_codec *codec)
4298 err = patch_generic_hdmi(codec);
4303 * Glenfly GPUs have two codecs, stream switches from one codec to
4304 * another, need to do actual clean-ups in codec_cleanup_stream
4306 codec->no_sticky_stream = 1;
4313 static const struct hda_device_id snd_hda_id_hdmi[] = {
4314 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4315 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4316 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4317 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4318 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4319 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4320 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4321 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4322 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4323 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4324 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4325 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4326 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4327 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4328 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4329 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4330 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4331 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4332 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4333 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4334 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4335 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4336 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4337 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4338 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4339 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4340 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4341 /* 17 is known to be absent */
4342 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4343 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4344 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4345 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4346 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4347 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4348 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4349 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4350 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4351 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4352 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4353 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4354 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4355 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4356 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4357 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4358 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4359 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4360 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4361 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4362 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4363 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4364 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4365 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4366 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4367 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4368 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4369 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4370 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4371 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4372 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4373 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4374 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4375 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4376 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4377 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4378 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4379 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4380 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4381 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4382 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4383 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4384 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4385 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4386 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4387 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4388 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4389 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4390 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4391 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4392 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4393 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4394 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4395 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4396 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4397 HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi),
4398 HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi),
4399 HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi),
4400 HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi),
4401 HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi),
4402 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4403 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4404 HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
4405 HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi),
4406 HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi),
4407 HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi),
4408 HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi),
4409 HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi),
4410 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4411 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4412 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4413 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4414 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4415 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4416 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4417 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4418 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4419 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4420 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4421 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4422 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4423 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4424 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4425 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4426 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4427 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4428 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4429 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4430 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4431 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4432 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4433 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4434 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
4435 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4436 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4437 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_tgl_hdmi),
4438 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4439 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4440 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4441 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4442 /* special ID for generic HDMI */
4443 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4446 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4448 MODULE_LICENSE("GPL");
4449 MODULE_DESCRIPTION("HDMI HD-audio codec");
4450 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4451 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4452 MODULE_ALIAS("snd-hda-codec-atihdmi");
4454 static struct hda_codec_driver hdmi_driver = {
4455 .id = snd_hda_id_hdmi,
4458 module_hda_codec_driver(hdmi_driver);