sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <linux/pm_runtime.h>
  37 #include <sound/core.h>
  38 #include <sound/jack.h>
  39 #include <sound/asoundef.h>
  40 #include <sound/tlv.h>
  41 #include <sound/hdaudio.h>
  42 #include <sound/hda_i915.h>
  43 #include <sound/hda_chmap.h>
  44 #include "hda_codec.h"
  45 #include "hda_local.h"
  46 #include "hda_jack.h"
  47
  48 static bool static_hdmi_pcm;
  49 module_param(static_hdmi_pcm, bool, 0644);
  50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  51
  52 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  53 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  57 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  58                                 || is_skylake(codec) || is_broxton(codec) \
  59                                 || is_kabylake(codec))
  60
  61 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  62 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  63 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  64
  65 struct hdmi_spec_per_cvt {
  66         hda_nid_t cvt_nid;
  67         int assigned;
  68         unsigned int channels_min;
  69         unsigned int channels_max;
  70         u32 rates;
  71         u64 formats;
  72         unsigned int maxbps;
  73 };
  74
  75 /* max. connections to a widget */
  76 #define HDA_MAX_CONNECTIONS     32
  77
  78 struct hdmi_spec_per_pin {
  79         hda_nid_t pin_nid;
  80         /* pin idx, different device entries on the same pin use the same idx */
  81         int pin_nid_idx;
  82         int num_mux_nids;
  83         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  84         int mux_idx;
  85         hda_nid_t cvt_nid;
  86
  87         struct hda_codec *codec;
  88         struct hdmi_eld sink_eld;
  89         struct mutex lock;
  90         struct delayed_work work;
  91         struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
  92         int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
  93         int repoll_count;
  94         bool setup; /* the stream has been set up by prepare callback */
  95         int channels; /* current number of channels */
  96         bool non_pcm;
  97         bool chmap_set;         /* channel-map override by ALSA API? */
  98         unsigned char chmap[8]; /* ALSA API channel-map */
  99 #ifdef CONFIG_SND_PROC_FS
 100         struct snd_info_entry *proc_entry;
 101 #endif
 102 };
 103
 104 /* operations used by generic code that can be overridden by patches */
 105 struct hdmi_ops {
 106         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 107                            unsigned char *buf, int *eld_size);
 108
 109         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                                     int ca, int active_channels, int conn_type);
 111
 112         /* enable/disable HBR (HD passthrough) */
 113         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 114
 115         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 116                             hda_nid_t pin_nid, u32 stream_tag, int format);
 117
 118         void (*pin_cvt_fixup)(struct hda_codec *codec,
 119                               struct hdmi_spec_per_pin *per_pin,
 120                               hda_nid_t cvt_nid);
 121 };
 122
 123 struct hdmi_pcm {
 124         struct hda_pcm *pcm;
 125         struct snd_jack *jack;
 126         struct snd_kcontrol *eld_ctl;
 127 };
 128
 129 struct hdmi_spec {
 130         int num_cvts;
 131         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 132         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 133
 134         int num_pins;
 135         struct snd_array pins; /* struct hdmi_spec_per_pin */
 136         struct hdmi_pcm pcm_rec[16];
 137         struct mutex pcm_lock;
 138         /* pcm_bitmap means which pcms have been assigned to pins*/
 139         unsigned long pcm_bitmap;
 140         int pcm_used;   /* counter of pcm_rec[] */
 141         /* bitmap shows whether the pcm is opened in user space
 142          * bit 0 means the first playback PCM (PCM3);
 143          * bit 1 means the second playback PCM, and so on.
 144          */
 145         unsigned long pcm_in_use;
 146
 147         struct hdmi_eld temp_eld;
 148         struct hdmi_ops ops;
 149
 150         bool dyn_pin_out;
 151         bool dyn_pcm_assign;
 152         /*
 153          * Non-generic VIA/NVIDIA specific
 154          */
 155         struct hda_multi_out multiout;
 156         struct hda_pcm_stream pcm_playback;
 157
 158         /* i915/powerwell (Haswell+/Valleyview+) specific */
 159         bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
 160         struct i915_audio_component_audio_ops i915_audio_ops;
 161         bool i915_bound; /* was i915 bound in this driver? */
 162
 163         struct hdac_chmap chmap;
 164 };
 165
 166 #ifdef CONFIG_SND_HDA_I915
 167 static inline bool codec_has_acomp(struct hda_codec *codec)
 168 {
 169         struct hdmi_spec *spec = codec->spec;
 170         return spec->use_acomp_notifier;
 171 }
 172 #else
 173 #define codec_has_acomp(codec)  false
 174 #endif
 175
 176 struct hdmi_audio_infoframe {
 177         u8 type; /* 0x84 */
 178         u8 ver;  /* 0x01 */
 179         u8 len;  /* 0x0a */
 180
 181         u8 checksum;
 182
 183         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 184         u8 SS01_SF24;
 185         u8 CXT04;
 186         u8 CA;
 187         u8 LFEPBL01_LSV36_DM_INH7;
 188 };
 189
 190 struct dp_audio_infoframe {
 191         u8 type; /* 0x84 */
 192         u8 len;  /* 0x1b */
 193         u8 ver;  /* 0x11 << 2 */
 194
 195         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 196         u8 SS01_SF24;
 197         u8 CXT04;
 198         u8 CA;
 199         u8 LFEPBL01_LSV36_DM_INH7;
 200 };
 201
 202 union audio_infoframe {
 203         struct hdmi_audio_infoframe hdmi;
 204         struct dp_audio_infoframe dp;
 205         u8 bytes[0];
 206 };
 207
 208 /*
 209  * HDMI routines
 210  */
 211
 212 #define get_pin(spec, idx) \
 213         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 214 #define get_cvt(spec, idx) \
 215         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 216 /* obtain hdmi_pcm object assigned to idx */
 217 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
 218 /* obtain hda_pcm object assigned to idx */
 219 #define get_pcm_rec(spec, idx)  (get_hdmi_pcm(spec, idx)->pcm)
 220
 221 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
 222 {
 223         struct hdmi_spec *spec = codec->spec;
 224         int pin_idx;
 225
 226         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 227                 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
 228                         return pin_idx;
 229
 230         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 231         return -EINVAL;
 232 }
 233
 234 static int hinfo_to_pcm_index(struct hda_codec *codec,
 235                         struct hda_pcm_stream *hinfo)
 236 {
 237         struct hdmi_spec *spec = codec->spec;
 238         int pcm_idx;
 239
 240         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
 241                 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
 242                         return pcm_idx;
 243
 244         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 245         return -EINVAL;
 246 }
 247
 248 static int hinfo_to_pin_index(struct hda_codec *codec,
 249                               struct hda_pcm_stream *hinfo)
 250 {
 251         struct hdmi_spec *spec = codec->spec;
 252         struct hdmi_spec_per_pin *per_pin;
 253         int pin_idx;
 254
 255         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
 256                 per_pin = get_pin(spec, pin_idx);
 257                 if (per_pin->pcm &&
 258                         per_pin->pcm->pcm->stream == hinfo)
 259                         return pin_idx;
 260         }
 261
 262         codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
 263         return -EINVAL;
 264 }
 265
 266 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
 267                                                 int pcm_idx)
 268 {
 269         int i;
 270         struct hdmi_spec_per_pin *per_pin;
 271
 272         for (i = 0; i < spec->num_pins; i++) {
 273                 per_pin = get_pin(spec, i);
 274                 if (per_pin->pcm_idx == pcm_idx)
 275                         return per_pin;
 276         }
 277         return NULL;
 278 }
 279
 280 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 281 {
 282         struct hdmi_spec *spec = codec->spec;
 283         int cvt_idx;
 284
 285         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 286                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 287                         return cvt_idx;
 288
 289         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 290         return -EINVAL;
 291 }
 292
 293 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 294                         struct snd_ctl_elem_info *uinfo)
 295 {
 296         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 297         struct hdmi_spec *spec = codec->spec;
 298         struct hdmi_spec_per_pin *per_pin;
 299         struct hdmi_eld *eld;
 300         int pcm_idx;
 301
 302         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 303
 304         pcm_idx = kcontrol->private_value;
 305         mutex_lock(&spec->pcm_lock);
 306         per_pin = pcm_idx_to_pin(spec, pcm_idx);
 307         if (!per_pin) {
 308                 /* no pin is bound to the pcm */
 309                 uinfo->count = 0;
 310                 goto unlock;
 311         }
 312         eld = &per_pin->sink_eld;
 313         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 314
 315  unlock:
 316         mutex_unlock(&spec->pcm_lock);
 317         return 0;
 318 }
 319
 320 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 321                         struct snd_ctl_elem_value *ucontrol)
 322 {
 323         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 324         struct hdmi_spec *spec = codec->spec;
 325         struct hdmi_spec_per_pin *per_pin;
 326         struct hdmi_eld *eld;
 327         int pcm_idx;
 328         int err = 0;
 329
 330         pcm_idx = kcontrol->private_value;
 331         mutex_lock(&spec->pcm_lock);
 332         per_pin = pcm_idx_to_pin(spec, pcm_idx);
 333         if (!per_pin) {
 334                 /* no pin is bound to the pcm */
 335                 memset(ucontrol->value.bytes.data, 0,
 336                        ARRAY_SIZE(ucontrol->value.bytes.data));
 337                 goto unlock;
 338         }
 339
 340         eld = &per_pin->sink_eld;
 341         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
 342             eld->eld_size > ELD_MAX_SIZE) {
 343                 snd_BUG();
 344                 err = -EINVAL;
 345                 goto unlock;
 346         }
 347
 348         memset(ucontrol->value.bytes.data, 0,
 349                ARRAY_SIZE(ucontrol->value.bytes.data));
 350         if (eld->eld_valid)
 351                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 352                        eld->eld_size);
 353
 354  unlock:
 355         mutex_unlock(&spec->pcm_lock);
 356         return err;
 357 }
 358
 359 static struct snd_kcontrol_new eld_bytes_ctl = {
 360         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 361         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 362         .name = "ELD",
 363         .info = hdmi_eld_ctl_info,
 364         .get = hdmi_eld_ctl_get,
 365 };
 366
 367 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
 368                         int device)
 369 {
 370         struct snd_kcontrol *kctl;
 371         struct hdmi_spec *spec = codec->spec;
 372         int err;
 373
 374         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 375         if (!kctl)
 376                 return -ENOMEM;
 377         kctl->private_value = pcm_idx;
 378         kctl->id.device = device;
 379
 380         /* no pin nid is associated with the kctl now
 381          * tbd: associate pin nid to eld ctl later
 382          */
 383         err = snd_hda_ctl_add(codec, 0, kctl);
 384         if (err < 0)
 385                 return err;
 386
 387         get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
 388         return 0;
 389 }
 390
 391 #ifdef BE_PARANOID
 392 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 393                                 int *packet_index, int *byte_index)
 394 {
 395         int val;
 396
 397         val = snd_hda_codec_read(codec, pin_nid, 0,
 398                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 399
 400         *packet_index = val >> 5;
 401         *byte_index = val & 0x1f;
 402 }
 403 #endif
 404
 405 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 406                                 int packet_index, int byte_index)
 407 {
 408         int val;
 409
 410         val = (packet_index << 5) | (byte_index & 0x1f);
 411
 412         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 413 }
 414
 415 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 416                                 unsigned char val)
 417 {
 418         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 419 }
 420
 421 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 422 {
 423         struct hdmi_spec *spec = codec->spec;
 424         int pin_out;
 425
 426         /* Unmute */
 427         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 428                 snd_hda_codec_write(codec, pin_nid, 0,
 429                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 430
 431         if (spec->dyn_pin_out)
 432                 /* Disable pin out until stream is active */
 433                 pin_out = 0;
 434         else
 435                 /* Enable pin out: some machines with GM965 gets broken output
 436                  * when the pin is disabled or changed while using with HDMI
 437                  */
 438                 pin_out = PIN_OUT;
 439
 440         snd_hda_codec_write(codec, pin_nid, 0,
 441                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 442 }
 443
 444 /*
 445  * ELD proc files
 446  */
 447
 448 #ifdef CONFIG_SND_PROC_FS
 449 static void print_eld_info(struct snd_info_entry *entry,
 450                            struct snd_info_buffer *buffer)
 451 {
 452         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 453
 454         mutex_lock(&per_pin->lock);
 455         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 456         mutex_unlock(&per_pin->lock);
 457 }
 458
 459 static void write_eld_info(struct snd_info_entry *entry,
 460                            struct snd_info_buffer *buffer)
 461 {
 462         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 463
 464         mutex_lock(&per_pin->lock);
 465         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 466         mutex_unlock(&per_pin->lock);
 467 }
 468
 469 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 470 {
 471         char name[32];
 472         struct hda_codec *codec = per_pin->codec;
 473         struct snd_info_entry *entry;
 474         int err;
 475
 476         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 477         err = snd_card_proc_new(codec->card, name, &entry);
 478         if (err < 0)
 479                 return err;
 480
 481         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 482         entry->c.text.write = write_eld_info;
 483         entry->mode |= S_IWUSR;
 484         per_pin->proc_entry = entry;
 485
 486         return 0;
 487 }
 488
 489 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 490 {
 491         if (!per_pin->codec->bus->shutdown) {
 492                 snd_info_free_entry(per_pin->proc_entry);
 493                 per_pin->proc_entry = NULL;
 494         }
 495 }
 496 #else
 497 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 498                                int index)
 499 {
 500         return 0;
 501 }
 502 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 503 {
 504 }
 505 #endif
 506
 507 /*
 508  * Audio InfoFrame routines
 509  */
 510
 511 /*
 512  * Enable Audio InfoFrame Transmission
 513  */
 514 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 515                                        hda_nid_t pin_nid)
 516 {
 517         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 518         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 519                                                 AC_DIPXMIT_BEST);
 520 }
 521
 522 /*
 523  * Disable Audio InfoFrame Transmission
 524  */
 525 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 526                                       hda_nid_t pin_nid)
 527 {
 528         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 529         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 530                                                 AC_DIPXMIT_DISABLE);
 531 }
 532
 533 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 534 {
 535 #ifdef CONFIG_SND_DEBUG_VERBOSE
 536         int i;
 537         int size;
 538
 539         size = snd_hdmi_get_eld_size(codec, pin_nid);
 540         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 541
 542         for (i = 0; i < 8; i++) {
 543                 size = snd_hda_codec_read(codec, pin_nid, 0,
 544                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 545                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 546         }
 547 #endif
 548 }
 549
 550 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 551 {
 552 #ifdef BE_PARANOID
 553         int i, j;
 554         int size;
 555         int pi, bi;
 556         for (i = 0; i < 8; i++) {
 557                 size = snd_hda_codec_read(codec, pin_nid, 0,
 558                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 559                 if (size == 0)
 560                         continue;
 561
 562                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
 563                 for (j = 1; j < 1000; j++) {
 564                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
 565                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
 566                         if (pi != i)
 567                                 codec_dbg(codec, "dip index %d: %d != %d\n",
 568                                                 bi, pi, i);
 569                         if (bi == 0) /* byte index wrapped around */
 570                                 break;
 571                 }
 572                 codec_dbg(codec,
 573                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
 574                         i, size, j);
 575         }
 576 #endif
 577 }
 578
 579 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
 580 {
 581         u8 *bytes = (u8 *)hdmi_ai;
 582         u8 sum = 0;
 583         int i;
 584
 585         hdmi_ai->checksum = 0;
 586
 587         for (i = 0; i < sizeof(*hdmi_ai); i++)
 588                 sum += bytes[i];
 589
 590         hdmi_ai->checksum = -sum;
 591 }
 592
 593 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
 594                                       hda_nid_t pin_nid,
 595                                       u8 *dip, int size)
 596 {
 597         int i;
 598
 599         hdmi_debug_dip_size(codec, pin_nid);
 600         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
 601
 602         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 603         for (i = 0; i < size; i++)
 604                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
 605 }
 606
 607 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
 608                                     u8 *dip, int size)
 609 {
 610         u8 val;
 611         int i;
 612
 613         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
 614                                                             != AC_DIPXMIT_BEST)
 615                 return false;
 616
 617         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 618         for (i = 0; i < size; i++) {
 619                 val = snd_hda_codec_read(codec, pin_nid, 0,
 620                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
 621                 if (val != dip[i])
 622                         return false;
 623         }
 624
 625         return true;
 626 }
 627
 628 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
 629                                      hda_nid_t pin_nid,
 630                                      int ca, int active_channels,
 631                                      int conn_type)
 632 {
 633         union audio_infoframe ai;
 634
 635         memset(&ai, 0, sizeof(ai));
 636         if (conn_type == 0) { /* HDMI */
 637                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
 638
 639                 hdmi_ai->type           = 0x84;
 640                 hdmi_ai->ver            = 0x01;
 641                 hdmi_ai->len            = 0x0a;
 642                 hdmi_ai->CC02_CT47      = active_channels - 1;
 643                 hdmi_ai->CA             = ca;
 644                 hdmi_checksum_audio_infoframe(hdmi_ai);
 645         } else if (conn_type == 1) { /* DisplayPort */
 646                 struct dp_audio_infoframe *dp_ai = &ai.dp;
 647
 648                 dp_ai->type             = 0x84;
 649                 dp_ai->len              = 0x1b;
 650                 dp_ai->ver              = 0x11 << 2;
 651                 dp_ai->CC02_CT47        = active_channels - 1;
 652                 dp_ai->CA               = ca;
 653         } else {
 654                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
 655                             pin_nid);
 656                 return;
 657         }
 658
 659         /*
 660          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
 661          * sizeof(*dp_ai) to avoid partial match/update problems when
 662          * the user switches between HDMI/DP monitors.
 663          */
 664         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
 665                                         sizeof(ai))) {
 666                 codec_dbg(codec,
 667                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
 668                             pin_nid,
 669                             active_channels, ca);
 670                 hdmi_stop_infoframe_trans(codec, pin_nid);
 671                 hdmi_fill_audio_infoframe(codec, pin_nid,
 672                                             ai.bytes, sizeof(ai));
 673                 hdmi_start_infoframe_trans(codec, pin_nid);
 674         }
 675 }
 676
 677 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
 678                                        struct hdmi_spec_per_pin *per_pin,
 679                                        bool non_pcm)
 680 {
 681         struct hdmi_spec *spec = codec->spec;
 682         struct hdac_chmap *chmap = &spec->chmap;
 683         hda_nid_t pin_nid = per_pin->pin_nid;
 684         int channels = per_pin->channels;
 685         int active_channels;
 686         struct hdmi_eld *eld;
 687         int ca;
 688
 689         if (!channels)
 690                 return;
 691
 692         /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
 693         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 694                 snd_hda_codec_write(codec, pin_nid, 0,
 695                                             AC_VERB_SET_AMP_GAIN_MUTE,
 696                                             AMP_OUT_UNMUTE);
 697
 698         eld = &per_pin->sink_eld;
 699
 700         ca = snd_hdac_channel_allocation(&codec->core,
 701                         eld->info.spk_alloc, channels,
 702                         per_pin->chmap_set, non_pcm, per_pin->chmap);
 703
 704         active_channels = snd_hdac_get_active_channels(ca);
 705
 706         chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
 707                                                 active_channels);
 708
 709         /*
 710          * always configure channel mapping, it may have been changed by the
 711          * user in the meantime
 712          */
 713         snd_hdac_setup_channel_mapping(&spec->chmap,
 714                                 pin_nid, non_pcm, ca, channels,
 715                                 per_pin->chmap, per_pin->chmap_set);
 716
 717         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
 718                                       eld->info.conn_type);
 719
 720         per_pin->non_pcm = non_pcm;
 721 }
 722
 723 /*
 724  * Unsolicited events
 725  */
 726
 727 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
 728
 729 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
 730 {
 731         struct hdmi_spec *spec = codec->spec;
 732         int pin_idx = pin_nid_to_pin_index(codec, nid);
 733
 734         if (pin_idx < 0)
 735                 return;
 736         mutex_lock(&spec->pcm_lock);
 737         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
 738                 snd_hda_jack_report_sync(codec);
 739         mutex_unlock(&spec->pcm_lock);
 740 }
 741
 742 static void jack_callback(struct hda_codec *codec,
 743                           struct hda_jack_callback *jack)
 744 {
 745         check_presence_and_report(codec, jack->nid);
 746 }
 747
 748 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
 749 {
 750         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 751         struct hda_jack_tbl *jack;
 752         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
 753
 754         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
 755         if (!jack)
 756                 return;
 757         jack->jack_dirty = 1;
 758
 759         codec_dbg(codec,
 760                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
 761                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
 762                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
 763
 764         check_presence_and_report(codec, jack->nid);
 765 }
 766
 767 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
 768 {
 769         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 770         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 771         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
 772         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
 773
 774         codec_info(codec,
 775                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
 776                 codec->addr,
 777                 tag,
 778                 subtag,
 779                 cp_state,
 780                 cp_ready);
 781
 782         /* TODO */
 783         if (cp_state)
 784                 ;
 785         if (cp_ready)
 786                 ;
 787 }
 788
 789
 790 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
 791 {
 792         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 793         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 794
 795         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
 796                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
 797                 return;
 798         }
 799
 800         if (subtag == 0)
 801                 hdmi_intrinsic_event(codec, res);
 802         else
 803                 hdmi_non_intrinsic_event(codec, res);
 804 }
 805
 806 static void haswell_verify_D0(struct hda_codec *codec,
 807                 hda_nid_t cvt_nid, hda_nid_t nid)
 808 {
 809         int pwr;
 810
 811         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
 812          * thus pins could only choose converter 0 for use. Make sure the
 813          * converters are in correct power state */
 814         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
 815                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
 816
 817         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
 818                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
 819                                     AC_PWRST_D0);
 820                 msleep(40);
 821                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
 822                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
 823                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
 824         }
 825 }
 826
 827 /*
 828  * Callbacks
 829  */
 830
 831 /* HBR should be Non-PCM, 8 channels */
 832 #define is_hbr_format(format) \
 833         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
 834
 835 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
 836                               bool hbr)
 837 {
 838         int pinctl, new_pinctl;
 839
 840         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
 841                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
 842                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
 843
 844                 if (pinctl < 0)
 845                         return hbr ? -EINVAL : 0;
 846
 847                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
 848                 if (hbr)
 849                         new_pinctl |= AC_PINCTL_EPT_HBR;
 850                 else
 851                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
 852
 853                 codec_dbg(codec,
 854                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
 855                             pin_nid,
 856                             pinctl == new_pinctl ? "" : "new-",
 857                             new_pinctl);
 858
 859                 if (pinctl != new_pinctl)
 860                         snd_hda_codec_write(codec, pin_nid, 0,
 861                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
 862                                             new_pinctl);
 863         } else if (hbr)
 864                 return -EINVAL;
 865
 866         return 0;
 867 }
 868
 869 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
 870                               hda_nid_t pin_nid, u32 stream_tag, int format)
 871 {
 872         struct hdmi_spec *spec = codec->spec;
 873         int err;
 874
 875         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
 876
 877         if (err) {
 878                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
 879                 return err;
 880         }
 881
 882         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
 883         return 0;
 884 }
 885
 886 /* Try to find an available converter
 887  * If pin_idx is less then zero, just try to find an available converter.
 888  * Otherwise, try to find an available converter and get the cvt mux index
 889  * of the pin.
 890  */
 891 static int hdmi_choose_cvt(struct hda_codec *codec,
 892                            int pin_idx, int *cvt_id)
 893 {
 894         struct hdmi_spec *spec = codec->spec;
 895         struct hdmi_spec_per_pin *per_pin;
 896         struct hdmi_spec_per_cvt *per_cvt = NULL;
 897         int cvt_idx, mux_idx = 0;
 898
 899         /* pin_idx < 0 means no pin will be bound to the converter */
 900         if (pin_idx < 0)
 901                 per_pin = NULL;
 902         else
 903                 per_pin = get_pin(spec, pin_idx);
 904
 905         /* Dynamically assign converter to stream */
 906         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
 907                 per_cvt = get_cvt(spec, cvt_idx);
 908
 909                 /* Must not already be assigned */
 910                 if (per_cvt->assigned)
 911                         continue;
 912                 if (per_pin == NULL)
 913                         break;
 914                 /* Must be in pin's mux's list of converters */
 915                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
 916                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
 917                                 break;
 918                 /* Not in mux list */
 919                 if (mux_idx == per_pin->num_mux_nids)
 920                         continue;
 921                 break;
 922         }
 923
 924         /* No free converters */
 925         if (cvt_idx == spec->num_cvts)
 926                 return -EBUSY;
 927
 928         if (per_pin != NULL)
 929                 per_pin->mux_idx = mux_idx;
 930
 931         if (cvt_id)
 932                 *cvt_id = cvt_idx;
 933
 934         return 0;
 935 }
 936
 937 /* Assure the pin select the right convetor */
 938 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
 939                         struct hdmi_spec_per_pin *per_pin)
 940 {
 941         hda_nid_t pin_nid = per_pin->pin_nid;
 942         int mux_idx, curr;
 943
 944         mux_idx = per_pin->mux_idx;
 945         curr = snd_hda_codec_read(codec, pin_nid, 0,
 946                                           AC_VERB_GET_CONNECT_SEL, 0);
 947         if (curr != mux_idx)
 948                 snd_hda_codec_write_cache(codec, pin_nid, 0,
 949                                             AC_VERB_SET_CONNECT_SEL,
 950                                             mux_idx);
 951 }
 952
 953 /* get the mux index for the converter of the pins
 954  * converter's mux index is the same for all pins on Intel platform
 955  */
 956 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
 957                         hda_nid_t cvt_nid)
 958 {
 959         int i;
 960
 961         for (i = 0; i < spec->num_cvts; i++)
 962                 if (spec->cvt_nids[i] == cvt_nid)
 963                         return i;
 964         return -EINVAL;
 965 }
 966
 967 /* Intel HDMI workaround to fix audio routing issue:
 968  * For some Intel display codecs, pins share the same connection list.
 969  * So a conveter can be selected by multiple pins and playback on any of these
 970  * pins will generate sound on the external display, because audio flows from
 971  * the same converter to the display pipeline. Also muting one pin may make
 972  * other pins have no sound output.
 973  * So this function assures that an assigned converter for a pin is not selected
 974  * by any other pins.
 975  */
 976 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
 977                         hda_nid_t pin_nid, int mux_idx)
 978 {
 979         struct hdmi_spec *spec = codec->spec;
 980         hda_nid_t nid;
 981         int cvt_idx, curr;
 982         struct hdmi_spec_per_cvt *per_cvt;
 983
 984         /* configure all pins, including "no physical connection" ones */
 985         for_each_hda_codec_node(nid, codec) {
 986                 unsigned int wid_caps = get_wcaps(codec, nid);
 987                 unsigned int wid_type = get_wcaps_type(wid_caps);
 988
 989                 if (wid_type != AC_WID_PIN)
 990                         continue;
 991
 992                 if (nid == pin_nid)
 993                         continue;
 994
 995                 curr = snd_hda_codec_read(codec, nid, 0,
 996                                           AC_VERB_GET_CONNECT_SEL, 0);
 997                 if (curr != mux_idx)
 998                         continue;
 999
1000                 /* choose an unassigned converter. The conveters in the
1001                  * connection list are in the same order as in the codec.
1002                  */
1003                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1004                         per_cvt = get_cvt(spec, cvt_idx);
1005                         if (!per_cvt->assigned) {
1006                                 codec_dbg(codec,
1007                                           "choose cvt %d for pin nid %d\n",
1008                                         cvt_idx, nid);
1009                                 snd_hda_codec_write_cache(codec, nid, 0,
1010                                             AC_VERB_SET_CONNECT_SEL,
1011                                             cvt_idx);
1012                                 break;
1013                         }
1014                 }
1015         }
1016 }
1017
1018 /* A wrapper of intel_not_share_asigned_cvt() */
1019 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1020                         hda_nid_t pin_nid, hda_nid_t cvt_nid)
1021 {
1022         int mux_idx;
1023         struct hdmi_spec *spec = codec->spec;
1024
1025         /* On Intel platform, the mapping of converter nid to
1026          * mux index of the pins are always the same.
1027          * The pin nid may be 0, this means all pins will not
1028          * share the converter.
1029          */
1030         mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1031         if (mux_idx >= 0)
1032                 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1033 }
1034
1035 /* skeleton caller of pin_cvt_fixup ops */
1036 static void pin_cvt_fixup(struct hda_codec *codec,
1037                           struct hdmi_spec_per_pin *per_pin,
1038                           hda_nid_t cvt_nid)
1039 {
1040         struct hdmi_spec *spec = codec->spec;
1041
1042         if (spec->ops.pin_cvt_fixup)
1043                 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1044 }
1045
1046 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1047  * in dyn_pcm_assign mode.
1048  */
1049 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1050                          struct hda_codec *codec,
1051                          struct snd_pcm_substream *substream)
1052 {
1053         struct hdmi_spec *spec = codec->spec;
1054         struct snd_pcm_runtime *runtime = substream->runtime;
1055         int cvt_idx, pcm_idx;
1056         struct hdmi_spec_per_cvt *per_cvt = NULL;
1057         int err;
1058
1059         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1060         if (pcm_idx < 0)
1061                 return -EINVAL;
1062
1063         err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1064         if (err)
1065                 return err;
1066
1067         per_cvt = get_cvt(spec, cvt_idx);
1068         per_cvt->assigned = 1;
1069         hinfo->nid = per_cvt->cvt_nid;
1070
1071         pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1072
1073         set_bit(pcm_idx, &spec->pcm_in_use);
1074         /* todo: setup spdif ctls assign */
1075
1076         /* Initially set the converter's capabilities */
1077         hinfo->channels_min = per_cvt->channels_min;
1078         hinfo->channels_max = per_cvt->channels_max;
1079         hinfo->rates = per_cvt->rates;
1080         hinfo->formats = per_cvt->formats;
1081         hinfo->maxbps = per_cvt->maxbps;
1082
1083         /* Store the updated parameters */
1084         runtime->hw.channels_min = hinfo->channels_min;
1085         runtime->hw.channels_max = hinfo->channels_max;
1086         runtime->hw.formats = hinfo->formats;
1087         runtime->hw.rates = hinfo->rates;
1088
1089         snd_pcm_hw_constraint_step(substream->runtime, 0,
1090                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1091         return 0;
1092 }
1093
1094 /*
1095  * HDA PCM callbacks
1096  */
1097 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1098                          struct hda_codec *codec,
1099                          struct snd_pcm_substream *substream)
1100 {
1101         struct hdmi_spec *spec = codec->spec;
1102         struct snd_pcm_runtime *runtime = substream->runtime;
1103         int pin_idx, cvt_idx, pcm_idx;
1104         struct hdmi_spec_per_pin *per_pin;
1105         struct hdmi_eld *eld;
1106         struct hdmi_spec_per_cvt *per_cvt = NULL;
1107         int err;
1108
1109         /* Validate hinfo */
1110         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1111         if (pcm_idx < 0)
1112                 return -EINVAL;
1113
1114         mutex_lock(&spec->pcm_lock);
1115         pin_idx = hinfo_to_pin_index(codec, hinfo);
1116         if (!spec->dyn_pcm_assign) {
1117                 if (snd_BUG_ON(pin_idx < 0)) {
1118                         err = -EINVAL;
1119                         goto unlock;
1120                 }
1121         } else {
1122                 /* no pin is assigned to the PCM
1123                  * PA need pcm open successfully when probe
1124                  */
1125                 if (pin_idx < 0) {
1126                         err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1127                         goto unlock;
1128                 }
1129         }
1130
1131         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1132         if (err < 0)
1133                 goto unlock;
1134
1135         per_cvt = get_cvt(spec, cvt_idx);
1136         /* Claim converter */
1137         per_cvt->assigned = 1;
1138
1139         set_bit(pcm_idx, &spec->pcm_in_use);
1140         per_pin = get_pin(spec, pin_idx);
1141         per_pin->cvt_nid = per_cvt->cvt_nid;
1142         hinfo->nid = per_cvt->cvt_nid;
1143
1144         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1145                             AC_VERB_SET_CONNECT_SEL,
1146                             per_pin->mux_idx);
1147
1148         /* configure unused pins to choose other converters */
1149         pin_cvt_fixup(codec, per_pin, 0);
1150
1151         snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1152
1153         /* Initially set the converter's capabilities */
1154         hinfo->channels_min = per_cvt->channels_min;
1155         hinfo->channels_max = per_cvt->channels_max;
1156         hinfo->rates = per_cvt->rates;
1157         hinfo->formats = per_cvt->formats;
1158         hinfo->maxbps = per_cvt->maxbps;
1159
1160         eld = &per_pin->sink_eld;
1161         /* Restrict capabilities by ELD if this isn't disabled */
1162         if (!static_hdmi_pcm && eld->eld_valid) {
1163                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1164                 if (hinfo->channels_min > hinfo->channels_max ||
1165                     !hinfo->rates || !hinfo->formats) {
1166                         per_cvt->assigned = 0;
1167                         hinfo->nid = 0;
1168                         snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1169                         err = -ENODEV;
1170                         goto unlock;
1171                 }
1172         }
1173
1174         /* Store the updated parameters */
1175         runtime->hw.channels_min = hinfo->channels_min;
1176         runtime->hw.channels_max = hinfo->channels_max;
1177         runtime->hw.formats = hinfo->formats;
1178         runtime->hw.rates = hinfo->rates;
1179
1180         snd_pcm_hw_constraint_step(substream->runtime, 0,
1181                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182  unlock:
1183         mutex_unlock(&spec->pcm_lock);
1184         return err;
1185 }
1186
1187 /*
1188  * HDA/HDMI auto parsing
1189  */
1190 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1191 {
1192         struct hdmi_spec *spec = codec->spec;
1193         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1194         hda_nid_t pin_nid = per_pin->pin_nid;
1195
1196         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1197                 codec_warn(codec,
1198                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1199                            pin_nid, get_wcaps(codec, pin_nid));
1200                 return -EINVAL;
1201         }
1202
1203         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1204                                                         per_pin->mux_nids,
1205                                                         HDA_MAX_CONNECTIONS);
1206
1207         return 0;
1208 }
1209
1210 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1211                                 struct hdmi_spec_per_pin *per_pin)
1212 {
1213         int i;
1214
1215         /* try the prefer PCM */
1216         if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1217                 return per_pin->pin_nid_idx;
1218
1219         /* have a second try; check the "reserved area" over num_pins */
1220         for (i = spec->num_pins; i < spec->pcm_used; i++) {
1221                 if (!test_bit(i, &spec->pcm_bitmap))
1222                         return i;
1223         }
1224
1225         /* the last try; check the empty slots in pins */
1226         for (i = 0; i < spec->num_pins; i++) {
1227                 if (!test_bit(i, &spec->pcm_bitmap))
1228                         return i;
1229         }
1230         return -EBUSY;
1231 }
1232
1233 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1234                                 struct hdmi_spec_per_pin *per_pin)
1235 {
1236         int idx;
1237
1238         /* pcm already be attached to the pin */
1239         if (per_pin->pcm)
1240                 return;
1241         idx = hdmi_find_pcm_slot(spec, per_pin);
1242         if (idx == -EBUSY)
1243                 return;
1244         per_pin->pcm_idx = idx;
1245         per_pin->pcm = get_hdmi_pcm(spec, idx);
1246         set_bit(idx, &spec->pcm_bitmap);
1247 }
1248
1249 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1250                                 struct hdmi_spec_per_pin *per_pin)
1251 {
1252         int idx;
1253
1254         /* pcm already be detached from the pin */
1255         if (!per_pin->pcm)
1256                 return;
1257         idx = per_pin->pcm_idx;
1258         per_pin->pcm_idx = -1;
1259         per_pin->pcm = NULL;
1260         if (idx >= 0 && idx < spec->pcm_used)
1261                 clear_bit(idx, &spec->pcm_bitmap);
1262 }
1263
1264 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1265                 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1266 {
1267         int mux_idx;
1268
1269         for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1270                 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1271                         break;
1272         return mux_idx;
1273 }
1274
1275 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1276
1277 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1278                            struct hdmi_spec_per_pin *per_pin)
1279 {
1280         struct hda_codec *codec = per_pin->codec;
1281         struct hda_pcm *pcm;
1282         struct hda_pcm_stream *hinfo;
1283         struct snd_pcm_substream *substream;
1284         int mux_idx;
1285         bool non_pcm;
1286
1287         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1288                 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1289         else
1290                 return;
1291         if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1292                 return;
1293
1294         /* hdmi audio only uses playback and one substream */
1295         hinfo = pcm->stream;
1296         substream = pcm->pcm->streams[0].substream;
1297
1298         per_pin->cvt_nid = hinfo->nid;
1299
1300         mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1301         if (mux_idx < per_pin->num_mux_nids)
1302                 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1303                                 AC_VERB_SET_CONNECT_SEL,
1304                                 mux_idx);
1305         snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1306
1307         non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1308         if (substream->runtime)
1309                 per_pin->channels = substream->runtime->channels;
1310         per_pin->setup = true;
1311         per_pin->mux_idx = mux_idx;
1312
1313         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1314 }
1315
1316 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1317                            struct hdmi_spec_per_pin *per_pin)
1318 {
1319         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1320                 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1321
1322         per_pin->chmap_set = false;
1323         memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1324
1325         per_pin->setup = false;
1326         per_pin->channels = 0;
1327 }
1328
1329 /* update per_pin ELD from the given new ELD;
1330  * setup info frame and notification accordingly
1331  */
1332 static void update_eld(struct hda_codec *codec,
1333                        struct hdmi_spec_per_pin *per_pin,
1334                        struct hdmi_eld *eld)
1335 {
1336         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1337         struct hdmi_spec *spec = codec->spec;
1338         bool old_eld_valid = pin_eld->eld_valid;
1339         bool eld_changed;
1340         int pcm_idx = -1;
1341
1342         /* for monitor disconnection, save pcm_idx firstly */
1343         pcm_idx = per_pin->pcm_idx;
1344         if (spec->dyn_pcm_assign) {
1345                 if (eld->eld_valid) {
1346                         hdmi_attach_hda_pcm(spec, per_pin);
1347                         hdmi_pcm_setup_pin(spec, per_pin);
1348                 } else {
1349                         hdmi_pcm_reset_pin(spec, per_pin);
1350                         hdmi_detach_hda_pcm(spec, per_pin);
1351                 }
1352         }
1353         /* if pcm_idx == -1, it means this is in monitor connection event
1354          * we can get the correct pcm_idx now.
1355          */
1356         if (pcm_idx == -1)
1357                 pcm_idx = per_pin->pcm_idx;
1358
1359         if (eld->eld_valid)
1360                 snd_hdmi_show_eld(codec, &eld->info);
1361
1362         eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1363         if (eld->eld_valid && pin_eld->eld_valid)
1364                 if (pin_eld->eld_size != eld->eld_size ||
1365                     memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1366                            eld->eld_size) != 0)
1367                         eld_changed = true;
1368
1369         pin_eld->monitor_present = eld->monitor_present;
1370         pin_eld->eld_valid = eld->eld_valid;
1371         pin_eld->eld_size = eld->eld_size;
1372         if (eld->eld_valid)
1373                 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1374         pin_eld->info = eld->info;
1375
1376         /*
1377          * Re-setup pin and infoframe. This is needed e.g. when
1378          * - sink is first plugged-in
1379          * - transcoder can change during stream playback on Haswell
1380          *   and this can make HW reset converter selection on a pin.
1381          */
1382         if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1383                 pin_cvt_fixup(codec, per_pin, 0);
1384                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1385         }
1386
1387         if (eld_changed && pcm_idx >= 0)
1388                 snd_ctl_notify(codec->card,
1389                                SNDRV_CTL_EVENT_MASK_VALUE |
1390                                SNDRV_CTL_EVENT_MASK_INFO,
1391                                &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1392 }
1393
1394 /* update ELD and jack state via HD-audio verbs */
1395 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1396                                          int repoll)
1397 {
1398         struct hda_jack_tbl *jack;
1399         struct hda_codec *codec = per_pin->codec;
1400         struct hdmi_spec *spec = codec->spec;
1401         struct hdmi_eld *eld = &spec->temp_eld;
1402         hda_nid_t pin_nid = per_pin->pin_nid;
1403         /*
1404          * Always execute a GetPinSense verb here, even when called from
1405          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1406          * response's PD bit is not the real PD value, but indicates that
1407          * the real PD value changed. An older version of the HD-audio
1408          * specification worked this way. Hence, we just ignore the data in
1409          * the unsolicited response to avoid custom WARs.
1410          */
1411         int present;
1412         bool ret;
1413         bool do_repoll = false;
1414
1415         present = snd_hda_pin_sense(codec, pin_nid);
1416
1417         mutex_lock(&per_pin->lock);
1418         eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1419         if (eld->monitor_present)
1420                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1421         else
1422                 eld->eld_valid = false;
1423
1424         codec_dbg(codec,
1425                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1426                 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1427
1428         if (eld->eld_valid) {
1429                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1430                                                      &eld->eld_size) < 0)
1431                         eld->eld_valid = false;
1432                 else {
1433                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1434                                                     eld->eld_size) < 0)
1435                                 eld->eld_valid = false;
1436                 }
1437                 if (!eld->eld_valid && repoll)
1438                         do_repoll = true;
1439         }
1440
1441         if (do_repoll)
1442                 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1443         else
1444                 update_eld(codec, per_pin, eld);
1445
1446         ret = !repoll || !eld->monitor_present || eld->eld_valid;
1447
1448         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1449         if (jack) {
1450                 jack->block_report = !ret;
1451                 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1452                         AC_PINSENSE_PRESENCE : 0;
1453         }
1454         mutex_unlock(&per_pin->lock);
1455         return ret;
1456 }
1457
1458 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1459                                  struct hdmi_spec_per_pin *per_pin)
1460 {
1461         struct hdmi_spec *spec = codec->spec;
1462         struct snd_jack *jack = NULL;
1463         struct hda_jack_tbl *jack_tbl;
1464
1465         /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1466          * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1467          * NULL even after snd_hda_jack_tbl_clear() is called to
1468          * free snd_jack. This may cause access invalid memory
1469          * when calling snd_jack_report
1470          */
1471         if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1472                 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1473         else if (!spec->dyn_pcm_assign) {
1474                 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1475                 if (jack_tbl)
1476                         jack = jack_tbl->jack;
1477         }
1478         return jack;
1479 }
1480
1481 /* update ELD and jack state via audio component */
1482 static void sync_eld_via_acomp(struct hda_codec *codec,
1483                                struct hdmi_spec_per_pin *per_pin)
1484 {
1485         struct hdmi_spec *spec = codec->spec;
1486         struct hdmi_eld *eld = &spec->temp_eld;
1487         struct snd_jack *jack = NULL;
1488         int size;
1489
1490         mutex_lock(&per_pin->lock);
1491         eld->monitor_present = false;
1492         size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1493                                       &eld->monitor_present, eld->eld_buffer,
1494                                       ELD_MAX_SIZE);
1495         if (size > 0) {
1496                 size = min(size, ELD_MAX_SIZE);
1497                 if (snd_hdmi_parse_eld(codec, &eld->info,
1498                                        eld->eld_buffer, size) < 0)
1499                         size = -EINVAL;
1500         }
1501
1502         if (size > 0) {
1503                 eld->eld_valid = true;
1504                 eld->eld_size = size;
1505         } else {
1506                 eld->eld_valid = false;
1507                 eld->eld_size = 0;
1508         }
1509
1510         /* pcm_idx >=0 before update_eld() means it is in monitor
1511          * disconnected event. Jack must be fetched before update_eld()
1512          */
1513         jack = pin_idx_to_jack(codec, per_pin);
1514         update_eld(codec, per_pin, eld);
1515         if (jack == NULL)
1516                 jack = pin_idx_to_jack(codec, per_pin);
1517         if (jack == NULL)
1518                 goto unlock;
1519         snd_jack_report(jack,
1520                         eld->monitor_present ? SND_JACK_AVOUT : 0);
1521  unlock:
1522         mutex_unlock(&per_pin->lock);
1523 }
1524
1525 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1526 {
1527         struct hda_codec *codec = per_pin->codec;
1528         int ret;
1529
1530         /* no temporary power up/down needed for component notifier */
1531         if (!codec_has_acomp(codec)) {
1532                 ret = snd_hda_power_up_pm(codec);
1533                 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1534                         snd_hda_power_down_pm(codec);
1535                         return false;
1536                 }
1537         }
1538
1539         if (codec_has_acomp(codec)) {
1540                 sync_eld_via_acomp(codec, per_pin);
1541                 ret = false; /* don't call snd_hda_jack_report_sync() */
1542         } else {
1543                 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1544         }
1545
1546         if (!codec_has_acomp(codec))
1547                 snd_hda_power_down_pm(codec);
1548
1549         return ret;
1550 }
1551
1552 static void hdmi_repoll_eld(struct work_struct *work)
1553 {
1554         struct hdmi_spec_per_pin *per_pin =
1555         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1556         struct hda_codec *codec = per_pin->codec;
1557         struct hdmi_spec *spec = codec->spec;
1558         struct hda_jack_tbl *jack;
1559
1560         jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1561         if (jack)
1562                 jack->jack_dirty = 1;
1563
1564         if (per_pin->repoll_count++ > 6)
1565                 per_pin->repoll_count = 0;
1566
1567         mutex_lock(&spec->pcm_lock);
1568         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1569                 snd_hda_jack_report_sync(per_pin->codec);
1570         mutex_unlock(&spec->pcm_lock);
1571 }
1572
1573 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1574                                              hda_nid_t nid);
1575
1576 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1577 {
1578         struct hdmi_spec *spec = codec->spec;
1579         unsigned int caps, config;
1580         int pin_idx;
1581         struct hdmi_spec_per_pin *per_pin;
1582         int err;
1583
1584         caps = snd_hda_query_pin_caps(codec, pin_nid);
1585         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1586                 return 0;
1587
1588         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1589         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1590                 return 0;
1591
1592         if (is_haswell_plus(codec))
1593                 intel_haswell_fixup_connect_list(codec, pin_nid);
1594
1595         pin_idx = spec->num_pins;
1596         per_pin = snd_array_new(&spec->pins);
1597         if (!per_pin)
1598                 return -ENOMEM;
1599
1600         per_pin->pin_nid = pin_nid;
1601         per_pin->non_pcm = false;
1602         if (spec->dyn_pcm_assign)
1603                 per_pin->pcm_idx = -1;
1604         else {
1605                 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1606                 per_pin->pcm_idx = pin_idx;
1607         }
1608         per_pin->pin_nid_idx = pin_idx;
1609
1610         err = hdmi_read_pin_conn(codec, pin_idx);
1611         if (err < 0)
1612                 return err;
1613
1614         spec->num_pins++;
1615
1616         return 0;
1617 }
1618
1619 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1620 {
1621         struct hdmi_spec *spec = codec->spec;
1622         struct hdmi_spec_per_cvt *per_cvt;
1623         unsigned int chans;
1624         int err;
1625
1626         chans = get_wcaps(codec, cvt_nid);
1627         chans = get_wcaps_channels(chans);
1628
1629         per_cvt = snd_array_new(&spec->cvts);
1630         if (!per_cvt)
1631                 return -ENOMEM;
1632
1633         per_cvt->cvt_nid = cvt_nid;
1634         per_cvt->channels_min = 2;
1635         if (chans <= 16) {
1636                 per_cvt->channels_max = chans;
1637                 if (chans > spec->chmap.channels_max)
1638                         spec->chmap.channels_max = chans;
1639         }
1640
1641         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1642                                           &per_cvt->rates,
1643                                           &per_cvt->formats,
1644                                           &per_cvt->maxbps);
1645         if (err < 0)
1646                 return err;
1647
1648         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1649                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1650         spec->num_cvts++;
1651
1652         return 0;
1653 }
1654
1655 static int hdmi_parse_codec(struct hda_codec *codec)
1656 {
1657         hda_nid_t nid;
1658         int i, nodes;
1659
1660         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1661         if (!nid || nodes < 0) {
1662                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1663                 return -EINVAL;
1664         }
1665
1666         for (i = 0; i < nodes; i++, nid++) {
1667                 unsigned int caps;
1668                 unsigned int type;
1669
1670                 caps = get_wcaps(codec, nid);
1671                 type = get_wcaps_type(caps);
1672
1673                 if (!(caps & AC_WCAP_DIGITAL))
1674                         continue;
1675
1676                 switch (type) {
1677                 case AC_WID_AUD_OUT:
1678                         hdmi_add_cvt(codec, nid);
1679                         break;
1680                 case AC_WID_PIN:
1681                         hdmi_add_pin(codec, nid);
1682                         break;
1683                 }
1684         }
1685
1686         return 0;
1687 }
1688
1689 /*
1690  */
1691 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1692 {
1693         struct hda_spdif_out *spdif;
1694         bool non_pcm;
1695
1696         mutex_lock(&codec->spdif_mutex);
1697         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1698         /* Add sanity check to pass klockwork check.
1699          * This should never happen.
1700          */
1701         if (WARN_ON(spdif == NULL)) {
1702                 mutex_unlock(&codec->spdif_mutex);
1703                 return true;
1704         }
1705         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1706         mutex_unlock(&codec->spdif_mutex);
1707         return non_pcm;
1708 }
1709
1710 /*
1711  * HDMI callbacks
1712  */
1713
1714 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1715                                            struct hda_codec *codec,
1716                                            unsigned int stream_tag,
1717                                            unsigned int format,
1718                                            struct snd_pcm_substream *substream)
1719 {
1720         hda_nid_t cvt_nid = hinfo->nid;
1721         struct hdmi_spec *spec = codec->spec;
1722         int pin_idx;
1723         struct hdmi_spec_per_pin *per_pin;
1724         hda_nid_t pin_nid;
1725         struct snd_pcm_runtime *runtime = substream->runtime;
1726         bool non_pcm;
1727         int pinctl;
1728         int err = 0;
1729
1730         mutex_lock(&spec->pcm_lock);
1731         pin_idx = hinfo_to_pin_index(codec, hinfo);
1732         if (spec->dyn_pcm_assign && pin_idx < 0) {
1733                 /* when dyn_pcm_assign and pcm is not bound to a pin
1734                  * skip pin setup and return 0 to make audio playback
1735                  * be ongoing
1736                  */
1737                 pin_cvt_fixup(codec, NULL, cvt_nid);
1738                 snd_hda_codec_setup_stream(codec, cvt_nid,
1739                                         stream_tag, 0, format);
1740                 goto unlock;
1741         }
1742
1743         if (snd_BUG_ON(pin_idx < 0)) {
1744                 err = -EINVAL;
1745                 goto unlock;
1746         }
1747         per_pin = get_pin(spec, pin_idx);
1748         pin_nid = per_pin->pin_nid;
1749
1750         /* Verify pin:cvt selections to avoid silent audio after S3.
1751          * After S3, the audio driver restores pin:cvt selections
1752          * but this can happen before gfx is ready and such selection
1753          * is overlooked by HW. Thus multiple pins can share a same
1754          * default convertor and mute control will affect each other,
1755          * which can cause a resumed audio playback become silent
1756          * after S3.
1757          */
1758         pin_cvt_fixup(codec, per_pin, 0);
1759
1760         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1761         /* Todo: add DP1.2 MST audio support later */
1762         if (codec_has_acomp(codec))
1763                 snd_hdac_sync_audio_rate(&codec->core, pin_nid, runtime->rate);
1764
1765         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1766         mutex_lock(&per_pin->lock);
1767         per_pin->channels = substream->runtime->channels;
1768         per_pin->setup = true;
1769
1770         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1771         mutex_unlock(&per_pin->lock);
1772         if (spec->dyn_pin_out) {
1773                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1774                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1775                 snd_hda_codec_write(codec, pin_nid, 0,
1776                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1777                                     pinctl | PIN_OUT);
1778         }
1779
1780         err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1781                                  stream_tag, format);
1782  unlock:
1783         mutex_unlock(&spec->pcm_lock);
1784         return err;
1785 }
1786
1787 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1788                                              struct hda_codec *codec,
1789                                              struct snd_pcm_substream *substream)
1790 {
1791         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1792         return 0;
1793 }
1794
1795 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1796                           struct hda_codec *codec,
1797                           struct snd_pcm_substream *substream)
1798 {
1799         struct hdmi_spec *spec = codec->spec;
1800         int cvt_idx, pin_idx, pcm_idx;
1801         struct hdmi_spec_per_cvt *per_cvt;
1802         struct hdmi_spec_per_pin *per_pin;
1803         int pinctl;
1804         int err = 0;
1805
1806         mutex_lock(&spec->pcm_lock);
1807         if (hinfo->nid) {
1808                 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1809                 if (snd_BUG_ON(pcm_idx < 0)) {
1810                         err = -EINVAL;
1811                         goto unlock;
1812                 }
1813                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1814                 if (snd_BUG_ON(cvt_idx < 0)) {
1815                         err = -EINVAL;
1816                         goto unlock;
1817                 }
1818                 per_cvt = get_cvt(spec, cvt_idx);
1819                 snd_BUG_ON(!per_cvt->assigned);
1820                 per_cvt->assigned = 0;
1821                 hinfo->nid = 0;
1822
1823                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1824                 clear_bit(pcm_idx, &spec->pcm_in_use);
1825                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1826                 if (spec->dyn_pcm_assign && pin_idx < 0)
1827                         goto unlock;
1828
1829                 if (snd_BUG_ON(pin_idx < 0)) {
1830                         err = -EINVAL;
1831                         goto unlock;
1832                 }
1833                 per_pin = get_pin(spec, pin_idx);
1834
1835                 if (spec->dyn_pin_out) {
1836                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1837                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1838                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1839                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1840                                             pinctl & ~PIN_OUT);
1841                 }
1842
1843                 mutex_lock(&per_pin->lock);
1844                 per_pin->chmap_set = false;
1845                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1846
1847                 per_pin->setup = false;
1848                 per_pin->channels = 0;
1849                 mutex_unlock(&per_pin->lock);
1850         }
1851
1852 unlock:
1853         mutex_unlock(&spec->pcm_lock);
1854
1855         return err;
1856 }
1857
1858 static const struct hda_pcm_ops generic_ops = {
1859         .open = hdmi_pcm_open,
1860         .close = hdmi_pcm_close,
1861         .prepare = generic_hdmi_playback_pcm_prepare,
1862         .cleanup = generic_hdmi_playback_pcm_cleanup,
1863 };
1864
1865 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1866 {
1867         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1868         struct hdmi_spec *spec = codec->spec;
1869         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1870
1871         if (!per_pin)
1872                 return 0;
1873
1874         return per_pin->sink_eld.info.spk_alloc;
1875 }
1876
1877 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1878                                         unsigned char *chmap)
1879 {
1880         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1881         struct hdmi_spec *spec = codec->spec;
1882         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1883
1884         /* chmap is already set to 0 in caller */
1885         if (!per_pin)
1886                 return;
1887
1888         memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1889 }
1890
1891 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1892                                 unsigned char *chmap, int prepared)
1893 {
1894         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1895         struct hdmi_spec *spec = codec->spec;
1896         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1897
1898         if (!per_pin)
1899                 return;
1900         mutex_lock(&per_pin->lock);
1901         per_pin->chmap_set = true;
1902         memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1903         if (prepared)
1904                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1905         mutex_unlock(&per_pin->lock);
1906 }
1907
1908 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1909 {
1910         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1911         struct hdmi_spec *spec = codec->spec;
1912         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1913
1914         return per_pin ? true:false;
1915 }
1916
1917 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1918 {
1919         struct hdmi_spec *spec = codec->spec;
1920         int pin_idx;
1921
1922         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1923                 struct hda_pcm *info;
1924                 struct hda_pcm_stream *pstr;
1925
1926                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1927                 if (!info)
1928                         return -ENOMEM;
1929
1930                 spec->pcm_rec[pin_idx].pcm = info;
1931                 spec->pcm_used++;
1932                 info->pcm_type = HDA_PCM_TYPE_HDMI;
1933                 info->own_chmap = true;
1934
1935                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1936                 pstr->substreams = 1;
1937                 pstr->ops = generic_ops;
1938                 /* other pstr fields are set in open */
1939         }
1940
1941         return 0;
1942 }
1943
1944 static void free_hdmi_jack_priv(struct snd_jack *jack)
1945 {
1946         struct hdmi_pcm *pcm = jack->private_data;
1947
1948         pcm->jack = NULL;
1949 }
1950
1951 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1952                                struct hdmi_spec *spec,
1953                                int pcm_idx,
1954                                const char *name)
1955 {
1956         struct snd_jack *jack;
1957         int err;
1958
1959         err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1960                            true, false);
1961         if (err < 0)
1962                 return err;
1963
1964         spec->pcm_rec[pcm_idx].jack = jack;
1965         jack->private_data = &spec->pcm_rec[pcm_idx];
1966         jack->private_free = free_hdmi_jack_priv;
1967         return 0;
1968 }
1969
1970 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1971 {
1972         char hdmi_str[32] = "HDMI/DP";
1973         struct hdmi_spec *spec = codec->spec;
1974         struct hdmi_spec_per_pin *per_pin;
1975         struct hda_jack_tbl *jack;
1976         int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1977         bool phantom_jack;
1978         int ret;
1979
1980         if (pcmdev > 0)
1981                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1982
1983         if (spec->dyn_pcm_assign)
1984                 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1985
1986         /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1987         /* if !dyn_pcm_assign, it must be non-MST mode.
1988          * This means pcms and pins are statically mapped.
1989          * And pcm_idx is pin_idx.
1990          */
1991         per_pin = get_pin(spec, pcm_idx);
1992         phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1993         if (phantom_jack)
1994                 strncat(hdmi_str, " Phantom",
1995                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1996         ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1997                                     phantom_jack);
1998         if (ret < 0)
1999                 return ret;
2000         jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2001         if (jack == NULL)
2002                 return 0;
2003         /* assign jack->jack to pcm_rec[].jack to
2004          * align with dyn_pcm_assign mode
2005          */
2006         spec->pcm_rec[pcm_idx].jack = jack->jack;
2007         return 0;
2008 }
2009
2010 static int generic_hdmi_build_controls(struct hda_codec *codec)
2011 {
2012         struct hdmi_spec *spec = codec->spec;
2013         int err;
2014         int pin_idx, pcm_idx;
2015
2016
2017         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2018                 err = generic_hdmi_build_jack(codec, pcm_idx);
2019                 if (err < 0)
2020                         return err;
2021
2022                 /* create the spdif for each pcm
2023                  * pin will be bound when monitor is connected
2024                  */
2025                 if (spec->dyn_pcm_assign)
2026                         err = snd_hda_create_dig_out_ctls(codec,
2027                                           0, spec->cvt_nids[0],
2028                                           HDA_PCM_TYPE_HDMI);
2029                 else {
2030                         struct hdmi_spec_per_pin *per_pin =
2031                                 get_pin(spec, pcm_idx);
2032                         err = snd_hda_create_dig_out_ctls(codec,
2033                                                   per_pin->pin_nid,
2034                                                   per_pin->mux_nids[0],
2035                                                   HDA_PCM_TYPE_HDMI);
2036                 }
2037                 if (err < 0)
2038                         return err;
2039                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2040
2041                 /* add control for ELD Bytes */
2042                 err = hdmi_create_eld_ctl(codec, pcm_idx,
2043                                         get_pcm_rec(spec, pcm_idx)->device);
2044                 if (err < 0)
2045                         return err;
2046         }
2047
2048         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2049                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2050                 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2051
2052                 pin_eld->eld_valid = false;
2053                 hdmi_present_sense(per_pin, 0);
2054         }
2055
2056         /* add channel maps */
2057         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2058                 struct hda_pcm *pcm;
2059
2060                 pcm = get_pcm_rec(spec, pcm_idx);
2061                 if (!pcm || !pcm->pcm)
2062                         break;
2063                 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2064                 if (err < 0)
2065                         return err;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2072 {
2073         struct hdmi_spec *spec = codec->spec;
2074         int pin_idx;
2075
2076         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2077                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2078
2079                 per_pin->codec = codec;
2080                 mutex_init(&per_pin->lock);
2081                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2082                 eld_proc_new(per_pin, pin_idx);
2083         }
2084         return 0;
2085 }
2086
2087 static int generic_hdmi_init(struct hda_codec *codec)
2088 {
2089         struct hdmi_spec *spec = codec->spec;
2090         int pin_idx;
2091
2092         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2093                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2094                 hda_nid_t pin_nid = per_pin->pin_nid;
2095
2096                 hdmi_init_pin(codec, pin_nid);
2097                 if (!codec_has_acomp(codec))
2098                         snd_hda_jack_detect_enable_callback(codec, pin_nid,
2099                                 codec->jackpoll_interval > 0 ?
2100                                 jack_callback : NULL);
2101         }
2102         return 0;
2103 }
2104
2105 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2106 {
2107         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2108         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2109 }
2110
2111 static void hdmi_array_free(struct hdmi_spec *spec)
2112 {
2113         snd_array_free(&spec->pins);
2114         snd_array_free(&spec->cvts);
2115 }
2116
2117 static void generic_spec_free(struct hda_codec *codec)
2118 {
2119         struct hdmi_spec *spec = codec->spec;
2120
2121         if (spec) {
2122                 if (spec->i915_bound)
2123                         snd_hdac_i915_exit(&codec->bus->core);
2124                 hdmi_array_free(spec);
2125                 kfree(spec);
2126                 codec->spec = NULL;
2127         }
2128         codec->dp_mst = false;
2129 }
2130
2131 static void generic_hdmi_free(struct hda_codec *codec)
2132 {
2133         struct hdmi_spec *spec = codec->spec;
2134         int pin_idx, pcm_idx;
2135
2136         if (codec_has_acomp(codec))
2137                 snd_hdac_i915_register_notifier(NULL);
2138
2139         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2140                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2141                 cancel_delayed_work_sync(&per_pin->work);
2142                 eld_proc_free(per_pin);
2143         }
2144
2145         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2146                 if (spec->pcm_rec[pcm_idx].jack == NULL)
2147                         continue;
2148                 if (spec->dyn_pcm_assign)
2149                         snd_device_free(codec->card,
2150                                         spec->pcm_rec[pcm_idx].jack);
2151                 else
2152                         spec->pcm_rec[pcm_idx].jack = NULL;
2153         }
2154
2155         generic_spec_free(codec);
2156 }
2157
2158 #ifdef CONFIG_PM
2159 static int generic_hdmi_suspend(struct hda_codec *codec)
2160 {
2161         struct hdmi_spec *spec = codec->spec;
2162         int pin_idx;
2163
2164         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2165                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2166                 cancel_delayed_work_sync(&per_pin->work);
2167         }
2168         return 0;
2169 }
2170
2171 static int generic_hdmi_resume(struct hda_codec *codec)
2172 {
2173         struct hdmi_spec *spec = codec->spec;
2174         int pin_idx;
2175
2176         codec->patch_ops.init(codec);
2177         regcache_sync(codec->core.regmap);
2178
2179         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2180                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2181                 hdmi_present_sense(per_pin, 1);
2182         }
2183         return 0;
2184 }
2185 #endif
2186
2187 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2188         .init                   = generic_hdmi_init,
2189         .free                   = generic_hdmi_free,
2190         .build_pcms             = generic_hdmi_build_pcms,
2191         .build_controls         = generic_hdmi_build_controls,
2192         .unsol_event            = hdmi_unsol_event,
2193 #ifdef CONFIG_PM
2194         .suspend                = generic_hdmi_suspend,
2195         .resume                 = generic_hdmi_resume,
2196 #endif
2197 };
2198
2199 static const struct hdmi_ops generic_standard_hdmi_ops = {
2200         .pin_get_eld                            = snd_hdmi_get_eld,
2201         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2202         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2203         .setup_stream                           = hdmi_setup_stream,
2204 };
2205
2206 /* allocate codec->spec and assign/initialize generic parser ops */
2207 static int alloc_generic_hdmi(struct hda_codec *codec)
2208 {
2209         struct hdmi_spec *spec;
2210
2211         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2212         if (!spec)
2213                 return -ENOMEM;
2214
2215         spec->ops = generic_standard_hdmi_ops;
2216         mutex_init(&spec->pcm_lock);
2217         snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2218
2219         spec->chmap.ops.get_chmap = hdmi_get_chmap;
2220         spec->chmap.ops.set_chmap = hdmi_set_chmap;
2221         spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2222         spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2223
2224         codec->spec = spec;
2225         hdmi_array_init(spec, 4);
2226
2227         codec->patch_ops = generic_hdmi_patch_ops;
2228
2229         return 0;
2230 }
2231
2232 /* generic HDMI parser */
2233 static int patch_generic_hdmi(struct hda_codec *codec)
2234 {
2235         int err;
2236
2237         err = alloc_generic_hdmi(codec);
2238         if (err < 0)
2239                 return err;
2240
2241         err = hdmi_parse_codec(codec);
2242         if (err < 0) {
2243                 generic_spec_free(codec);
2244                 return err;
2245         }
2246
2247         generic_hdmi_init_per_pins(codec);
2248         return 0;
2249 }
2250
2251 /*
2252  * Intel codec parsers and helpers
2253  */
2254
2255 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2256                                              hda_nid_t nid)
2257 {
2258         struct hdmi_spec *spec = codec->spec;
2259         hda_nid_t conns[4];
2260         int nconns;
2261
2262         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2263         if (nconns == spec->num_cvts &&
2264             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2265                 return;
2266
2267         /* override pins connection list */
2268         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2269         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2270 }
2271
2272 #define INTEL_VENDOR_NID 0x08
2273 #define INTEL_GET_VENDOR_VERB 0xf81
2274 #define INTEL_SET_VENDOR_VERB 0x781
2275 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2276 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2277
2278 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2279                                           bool update_tree)
2280 {
2281         unsigned int vendor_param;
2282
2283         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2284                                 INTEL_GET_VENDOR_VERB, 0);
2285         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2286                 return;
2287
2288         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2289         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2290                                 INTEL_SET_VENDOR_VERB, vendor_param);
2291         if (vendor_param == -1)
2292                 return;
2293
2294         if (update_tree)
2295                 snd_hda_codec_update_widgets(codec);
2296 }
2297
2298 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2299 {
2300         unsigned int vendor_param;
2301
2302         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2303                                 INTEL_GET_VENDOR_VERB, 0);
2304         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2305                 return;
2306
2307         /* enable DP1.2 mode */
2308         vendor_param |= INTEL_EN_DP12;
2309         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2310         snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2311                                 INTEL_SET_VENDOR_VERB, vendor_param);
2312 }
2313
2314 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2315  * Otherwise you may get severe h/w communication errors.
2316  */
2317 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2318                                 unsigned int power_state)
2319 {
2320         if (power_state == AC_PWRST_D0) {
2321                 intel_haswell_enable_all_pins(codec, false);
2322                 intel_haswell_fixup_enable_dp12(codec);
2323         }
2324
2325         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2326         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2327 }
2328
2329 static void intel_pin_eld_notify(void *audio_ptr, int port)
2330 {
2331         struct hda_codec *codec = audio_ptr;
2332         int pin_nid;
2333
2334         /* we assume only from port-B to port-D */
2335         if (port < 1 || port > 3)
2336                 return;
2337
2338         switch (codec->core.vendor_id) {
2339         case 0x80860054: /* ILK */
2340         case 0x80862804: /* ILK */
2341         case 0x80862882: /* VLV */
2342                 pin_nid = port + 0x03;
2343                 break;
2344         default:
2345                 pin_nid = port + 0x04;
2346                 break;
2347         }
2348
2349         /* skip notification during system suspend (but not in runtime PM);
2350          * the state will be updated at resume
2351          */
2352         if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2353                 return;
2354         /* ditto during suspend/resume process itself */
2355         if (atomic_read(&(codec)->core.in_pm))
2356                 return;
2357
2358         snd_hdac_i915_set_bclk(&codec->bus->core);
2359         check_presence_and_report(codec, pin_nid);
2360 }
2361
2362 /* register i915 component pin_eld_notify callback */
2363 static void register_i915_notifier(struct hda_codec *codec)
2364 {
2365         struct hdmi_spec *spec = codec->spec;
2366
2367         spec->use_acomp_notifier = true;
2368         spec->i915_audio_ops.audio_ptr = codec;
2369         /* intel_audio_codec_enable() or intel_audio_codec_disable()
2370          * will call pin_eld_notify with using audio_ptr pointer
2371          * We need make sure audio_ptr is really setup
2372          */
2373         wmb();
2374         spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2375         snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2376 }
2377
2378 /* setup_stream ops override for HSW+ */
2379 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2380                                  hda_nid_t pin_nid, u32 stream_tag, int format)
2381 {
2382         haswell_verify_D0(codec, cvt_nid, pin_nid);
2383         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2384 }
2385
2386 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2387 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2388                                struct hdmi_spec_per_pin *per_pin,
2389                                hda_nid_t cvt_nid)
2390 {
2391         if (per_pin) {
2392                 intel_verify_pin_cvt_connect(codec, per_pin);
2393                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2394                                              per_pin->mux_idx);
2395         } else {
2396                 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2397         }
2398 }
2399
2400 /* Intel Haswell and onwards; audio component with eld notifier */
2401 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2402 {
2403         struct hdmi_spec *spec;
2404         int err;
2405
2406         /* HSW+ requires i915 binding */
2407         if (!codec->bus->core.audio_component) {
2408                 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2409                 return -ENODEV;
2410         }
2411
2412         err = alloc_generic_hdmi(codec);
2413         if (err < 0)
2414                 return err;
2415         spec = codec->spec;
2416
2417         intel_haswell_enable_all_pins(codec, true);
2418         intel_haswell_fixup_enable_dp12(codec);
2419
2420         /* For Haswell/Broadwell, the controller is also in the power well and
2421          * can cover the codec power request, and so need not set this flag.
2422          */
2423         if (!is_haswell(codec) && !is_broadwell(codec))
2424                 codec->core.link_power_control = 1;
2425
2426         codec->patch_ops.set_power_state = haswell_set_power_state;
2427         codec->dp_mst = true;
2428         codec->depop_delay = 0;
2429         codec->auto_runtime_pm = 1;
2430
2431         spec->ops.setup_stream = i915_hsw_setup_stream;
2432         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2433
2434         err = hdmi_parse_codec(codec);
2435         if (err < 0) {
2436                 generic_spec_free(codec);
2437                 return err;
2438         }
2439
2440         generic_hdmi_init_per_pins(codec);
2441         register_i915_notifier(codec);
2442         return 0;
2443 }
2444
2445 /* Intel Baytrail and Braswell; with eld notifier */
2446 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2447 {
2448         struct hdmi_spec *spec;
2449         int err;
2450
2451         /* requires i915 binding */
2452         if (!codec->bus->core.audio_component) {
2453                 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2454                 return -ENODEV;
2455         }
2456
2457         err = alloc_generic_hdmi(codec);
2458         if (err < 0)
2459                 return err;
2460         spec = codec->spec;
2461
2462         /* For Valleyview/Cherryview, only the display codec is in the display
2463          * power well and can use link_power ops to request/release the power.
2464          */
2465         codec->core.link_power_control = 1;
2466
2467         codec->depop_delay = 0;
2468         codec->auto_runtime_pm = 1;
2469
2470         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2471
2472         err = hdmi_parse_codec(codec);
2473         if (err < 0) {
2474                 generic_spec_free(codec);
2475                 return err;
2476         }
2477
2478         generic_hdmi_init_per_pins(codec);
2479         register_i915_notifier(codec);
2480         return 0;
2481 }
2482
2483 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2484 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2485 {
2486         struct hdmi_spec *spec;
2487         int err;
2488
2489         /* no i915 component should have been bound before this */
2490         if (WARN_ON(codec->bus->core.audio_component))
2491                 return -EBUSY;
2492
2493         err = alloc_generic_hdmi(codec);
2494         if (err < 0)
2495                 return err;
2496         spec = codec->spec;
2497
2498         /* Try to bind with i915 now */
2499         err = snd_hdac_i915_init(&codec->bus->core);
2500         if (err < 0)
2501                 goto error;
2502         spec->i915_bound = true;
2503
2504         err = hdmi_parse_codec(codec);
2505         if (err < 0)
2506                 goto error;
2507
2508         generic_hdmi_init_per_pins(codec);
2509         register_i915_notifier(codec);
2510         return 0;
2511
2512  error:
2513         generic_spec_free(codec);
2514         return err;
2515 }
2516
2517 /*
2518  * Shared non-generic implementations
2519  */
2520
2521 static int simple_playback_build_pcms(struct hda_codec *codec)
2522 {
2523         struct hdmi_spec *spec = codec->spec;
2524         struct hda_pcm *info;
2525         unsigned int chans;
2526         struct hda_pcm_stream *pstr;
2527         struct hdmi_spec_per_cvt *per_cvt;
2528
2529         per_cvt = get_cvt(spec, 0);
2530         chans = get_wcaps(codec, per_cvt->cvt_nid);
2531         chans = get_wcaps_channels(chans);
2532
2533         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2534         if (!info)
2535                 return -ENOMEM;
2536         spec->pcm_rec[0].pcm = info;
2537         info->pcm_type = HDA_PCM_TYPE_HDMI;
2538         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2539         *pstr = spec->pcm_playback;
2540         pstr->nid = per_cvt->cvt_nid;
2541         if (pstr->channels_max <= 2 && chans && chans <= 16)
2542                 pstr->channels_max = chans;
2543
2544         return 0;
2545 }
2546
2547 /* unsolicited event for jack sensing */
2548 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2549                                     unsigned int res)
2550 {
2551         snd_hda_jack_set_dirty_all(codec);
2552         snd_hda_jack_report_sync(codec);
2553 }
2554
2555 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2556  * as long as spec->pins[] is set correctly
2557  */
2558 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2559
2560 static int simple_playback_build_controls(struct hda_codec *codec)
2561 {
2562         struct hdmi_spec *spec = codec->spec;
2563         struct hdmi_spec_per_cvt *per_cvt;
2564         int err;
2565
2566         per_cvt = get_cvt(spec, 0);
2567         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2568                                           per_cvt->cvt_nid,
2569                                           HDA_PCM_TYPE_HDMI);
2570         if (err < 0)
2571                 return err;
2572         return simple_hdmi_build_jack(codec, 0);
2573 }
2574
2575 static int simple_playback_init(struct hda_codec *codec)
2576 {
2577         struct hdmi_spec *spec = codec->spec;
2578         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2579         hda_nid_t pin = per_pin->pin_nid;
2580
2581         snd_hda_codec_write(codec, pin, 0,
2582                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2583         /* some codecs require to unmute the pin */
2584         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2585                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2586                                     AMP_OUT_UNMUTE);
2587         snd_hda_jack_detect_enable(codec, pin);
2588         return 0;
2589 }
2590
2591 static void simple_playback_free(struct hda_codec *codec)
2592 {
2593         struct hdmi_spec *spec = codec->spec;
2594
2595         hdmi_array_free(spec);
2596         kfree(spec);
2597 }
2598
2599 /*
2600  * Nvidia specific implementations
2601  */
2602
2603 #define Nv_VERB_SET_Channel_Allocation          0xF79
2604 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2605 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2606 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2607
2608 #define nvhdmi_master_con_nid_7x        0x04
2609 #define nvhdmi_master_pin_nid_7x        0x05
2610
2611 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2612         /*front, rear, clfe, rear_surr */
2613         0x6, 0x8, 0xa, 0xc,
2614 };
2615
2616 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2617         /* set audio protect on */
2618         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2619         /* enable digital output on pin widget */
2620         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2621         {} /* terminator */
2622 };
2623
2624 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2625         /* set audio protect on */
2626         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2627         /* enable digital output on pin widget */
2628         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2629         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2630         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2631         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2632         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2633         {} /* terminator */
2634 };
2635
2636 #ifdef LIMITED_RATE_FMT_SUPPORT
2637 /* support only the safe format and rate */
2638 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2639 #define SUPPORTED_MAXBPS        16
2640 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2641 #else
2642 /* support all rates and formats */
2643 #define SUPPORTED_RATES \
2644         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2645         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2646          SNDRV_PCM_RATE_192000)
2647 #define SUPPORTED_MAXBPS        24
2648 #define SUPPORTED_FORMATS \
2649         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2650 #endif
2651
2652 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2653 {
2654         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2655         return 0;
2656 }
2657
2658 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2659 {
2660         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2661         return 0;
2662 }
2663
2664 static unsigned int channels_2_6_8[] = {
2665         2, 6, 8
2666 };
2667
2668 static unsigned int channels_2_8[] = {
2669         2, 8
2670 };
2671
2672 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2673         .count = ARRAY_SIZE(channels_2_6_8),
2674         .list = channels_2_6_8,
2675         .mask = 0,
2676 };
2677
2678 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2679         .count = ARRAY_SIZE(channels_2_8),
2680         .list = channels_2_8,
2681         .mask = 0,
2682 };
2683
2684 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2685                                     struct hda_codec *codec,
2686                                     struct snd_pcm_substream *substream)
2687 {
2688         struct hdmi_spec *spec = codec->spec;
2689         struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2690
2691         switch (codec->preset->vendor_id) {
2692         case 0x10de0002:
2693         case 0x10de0003:
2694         case 0x10de0005:
2695         case 0x10de0006:
2696                 hw_constraints_channels = &hw_constraints_2_8_channels;
2697                 break;
2698         case 0x10de0007:
2699                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2700                 break;
2701         default:
2702                 break;
2703         }
2704
2705         if (hw_constraints_channels != NULL) {
2706                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2707                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2708                                 hw_constraints_channels);
2709         } else {
2710                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2711                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2712         }
2713
2714         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2715 }
2716
2717 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2718                                      struct hda_codec *codec,
2719                                      struct snd_pcm_substream *substream)
2720 {
2721         struct hdmi_spec *spec = codec->spec;
2722         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2723 }
2724
2725 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2726                                        struct hda_codec *codec,
2727                                        unsigned int stream_tag,
2728                                        unsigned int format,
2729                                        struct snd_pcm_substream *substream)
2730 {
2731         struct hdmi_spec *spec = codec->spec;
2732         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2733                                              stream_tag, format, substream);
2734 }
2735
2736 static const struct hda_pcm_stream simple_pcm_playback = {
2737         .substreams = 1,
2738         .channels_min = 2,
2739         .channels_max = 2,
2740         .ops = {
2741                 .open = simple_playback_pcm_open,
2742                 .close = simple_playback_pcm_close,
2743                 .prepare = simple_playback_pcm_prepare
2744         },
2745 };
2746
2747 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2748         .build_controls = simple_playback_build_controls,
2749         .build_pcms = simple_playback_build_pcms,
2750         .init = simple_playback_init,
2751         .free = simple_playback_free,
2752         .unsol_event = simple_hdmi_unsol_event,
2753 };
2754
2755 static int patch_simple_hdmi(struct hda_codec *codec,
2756                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2757 {
2758         struct hdmi_spec *spec;
2759         struct hdmi_spec_per_cvt *per_cvt;
2760         struct hdmi_spec_per_pin *per_pin;
2761
2762         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2763         if (!spec)
2764                 return -ENOMEM;
2765
2766         codec->spec = spec;
2767         hdmi_array_init(spec, 1);
2768
2769         spec->multiout.num_dacs = 0;  /* no analog */
2770         spec->multiout.max_channels = 2;
2771         spec->multiout.dig_out_nid = cvt_nid;
2772         spec->num_cvts = 1;
2773         spec->num_pins = 1;
2774         per_pin = snd_array_new(&spec->pins);
2775         per_cvt = snd_array_new(&spec->cvts);
2776         if (!per_pin || !per_cvt) {
2777                 simple_playback_free(codec);
2778                 return -ENOMEM;
2779         }
2780         per_cvt->cvt_nid = cvt_nid;
2781         per_pin->pin_nid = pin_nid;
2782         spec->pcm_playback = simple_pcm_playback;
2783
2784         codec->patch_ops = simple_hdmi_patch_ops;
2785
2786         return 0;
2787 }
2788
2789 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2790                                                     int channels)
2791 {
2792         unsigned int chanmask;
2793         int chan = channels ? (channels - 1) : 1;
2794
2795         switch (channels) {
2796         default:
2797         case 0:
2798         case 2:
2799                 chanmask = 0x00;
2800                 break;
2801         case 4:
2802                 chanmask = 0x08;
2803                 break;
2804         case 6:
2805                 chanmask = 0x0b;
2806                 break;
2807         case 8:
2808                 chanmask = 0x13;
2809                 break;
2810         }
2811
2812         /* Set the audio infoframe channel allocation and checksum fields.  The
2813          * channel count is computed implicitly by the hardware. */
2814         snd_hda_codec_write(codec, 0x1, 0,
2815                         Nv_VERB_SET_Channel_Allocation, chanmask);
2816
2817         snd_hda_codec_write(codec, 0x1, 0,
2818                         Nv_VERB_SET_Info_Frame_Checksum,
2819                         (0x71 - chan - chanmask));
2820 }
2821
2822 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2823                                    struct hda_codec *codec,
2824                                    struct snd_pcm_substream *substream)
2825 {
2826         struct hdmi_spec *spec = codec->spec;
2827         int i;
2828
2829         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2830                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2831         for (i = 0; i < 4; i++) {
2832                 /* set the stream id */
2833                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2834                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2835                 /* set the stream format */
2836                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2837                                 AC_VERB_SET_STREAM_FORMAT, 0);
2838         }
2839
2840         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2841          * streams are disabled. */
2842         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2843
2844         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2845 }
2846
2847 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2848                                      struct hda_codec *codec,
2849                                      unsigned int stream_tag,
2850                                      unsigned int format,
2851                                      struct snd_pcm_substream *substream)
2852 {
2853         int chs;
2854         unsigned int dataDCC2, channel_id;
2855         int i;
2856         struct hdmi_spec *spec = codec->spec;
2857         struct hda_spdif_out *spdif;
2858         struct hdmi_spec_per_cvt *per_cvt;
2859
2860         mutex_lock(&codec->spdif_mutex);
2861         per_cvt = get_cvt(spec, 0);
2862         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2863
2864         chs = substream->runtime->channels;
2865
2866         dataDCC2 = 0x2;
2867
2868         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2869         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2870                 snd_hda_codec_write(codec,
2871                                 nvhdmi_master_con_nid_7x,
2872                                 0,
2873                                 AC_VERB_SET_DIGI_CONVERT_1,
2874                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2875
2876         /* set the stream id */
2877         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2878                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2879
2880         /* set the stream format */
2881         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2882                         AC_VERB_SET_STREAM_FORMAT, format);
2883
2884         /* turn on again (if needed) */
2885         /* enable and set the channel status audio/data flag */
2886         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2887                 snd_hda_codec_write(codec,
2888                                 nvhdmi_master_con_nid_7x,
2889                                 0,
2890                                 AC_VERB_SET_DIGI_CONVERT_1,
2891                                 spdif->ctls & 0xff);
2892                 snd_hda_codec_write(codec,
2893                                 nvhdmi_master_con_nid_7x,
2894                                 0,
2895                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2896         }
2897
2898         for (i = 0; i < 4; i++) {
2899                 if (chs == 2)
2900                         channel_id = 0;
2901                 else
2902                         channel_id = i * 2;
2903
2904                 /* turn off SPDIF once;
2905                  *otherwise the IEC958 bits won't be updated
2906                  */
2907                 if (codec->spdif_status_reset &&
2908                 (spdif->ctls & AC_DIG1_ENABLE))
2909                         snd_hda_codec_write(codec,
2910                                 nvhdmi_con_nids_7x[i],
2911                                 0,
2912                                 AC_VERB_SET_DIGI_CONVERT_1,
2913                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2914                 /* set the stream id */
2915                 snd_hda_codec_write(codec,
2916                                 nvhdmi_con_nids_7x[i],
2917                                 0,
2918                                 AC_VERB_SET_CHANNEL_STREAMID,
2919                                 (stream_tag << 4) | channel_id);
2920                 /* set the stream format */
2921                 snd_hda_codec_write(codec,
2922                                 nvhdmi_con_nids_7x[i],
2923                                 0,
2924                                 AC_VERB_SET_STREAM_FORMAT,
2925                                 format);
2926                 /* turn on again (if needed) */
2927                 /* enable and set the channel status audio/data flag */
2928                 if (codec->spdif_status_reset &&
2929                 (spdif->ctls & AC_DIG1_ENABLE)) {
2930                         snd_hda_codec_write(codec,
2931                                         nvhdmi_con_nids_7x[i],
2932                                         0,
2933                                         AC_VERB_SET_DIGI_CONVERT_1,
2934                                         spdif->ctls & 0xff);
2935                         snd_hda_codec_write(codec,
2936                                         nvhdmi_con_nids_7x[i],
2937                                         0,
2938                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2939                 }
2940         }
2941
2942         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2943
2944         mutex_unlock(&codec->spdif_mutex);
2945         return 0;
2946 }
2947
2948 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2949         .substreams = 1,
2950         .channels_min = 2,
2951         .channels_max = 8,
2952         .nid = nvhdmi_master_con_nid_7x,
2953         .rates = SUPPORTED_RATES,
2954         .maxbps = SUPPORTED_MAXBPS,
2955         .formats = SUPPORTED_FORMATS,
2956         .ops = {
2957                 .open = simple_playback_pcm_open,
2958                 .close = nvhdmi_8ch_7x_pcm_close,
2959                 .prepare = nvhdmi_8ch_7x_pcm_prepare
2960         },
2961 };
2962
2963 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2964 {
2965         struct hdmi_spec *spec;
2966         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2967                                     nvhdmi_master_pin_nid_7x);
2968         if (err < 0)
2969                 return err;
2970
2971         codec->patch_ops.init = nvhdmi_7x_init_2ch;
2972         /* override the PCM rates, etc, as the codec doesn't give full list */
2973         spec = codec->spec;
2974         spec->pcm_playback.rates = SUPPORTED_RATES;
2975         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2976         spec->pcm_playback.formats = SUPPORTED_FORMATS;
2977         return 0;
2978 }
2979
2980 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2981 {
2982         struct hdmi_spec *spec = codec->spec;
2983         int err = simple_playback_build_pcms(codec);
2984         if (!err) {
2985                 struct hda_pcm *info = get_pcm_rec(spec, 0);
2986                 info->own_chmap = true;
2987         }
2988         return err;
2989 }
2990
2991 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2992 {
2993         struct hdmi_spec *spec = codec->spec;
2994         struct hda_pcm *info;
2995         struct snd_pcm_chmap *chmap;
2996         int err;
2997
2998         err = simple_playback_build_controls(codec);
2999         if (err < 0)
3000                 return err;
3001
3002         /* add channel maps */
3003         info = get_pcm_rec(spec, 0);
3004         err = snd_pcm_add_chmap_ctls(info->pcm,
3005                                      SNDRV_PCM_STREAM_PLAYBACK,
3006                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
3007         if (err < 0)
3008                 return err;
3009         switch (codec->preset->vendor_id) {
3010         case 0x10de0002:
3011         case 0x10de0003:
3012         case 0x10de0005:
3013         case 0x10de0006:
3014                 chmap->channel_mask = (1U << 2) | (1U << 8);
3015                 break;
3016         case 0x10de0007:
3017                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3018         }
3019         return 0;
3020 }
3021
3022 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3023 {
3024         struct hdmi_spec *spec;
3025         int err = patch_nvhdmi_2ch(codec);
3026         if (err < 0)
3027                 return err;
3028         spec = codec->spec;
3029         spec->multiout.max_channels = 8;
3030         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3031         codec->patch_ops.init = nvhdmi_7x_init_8ch;
3032         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3033         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3034
3035         /* Initialize the audio infoframe channel mask and checksum to something
3036          * valid */
3037         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3038
3039         return 0;
3040 }
3041
3042 /*
3043  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3044  * - 0x10de0015
3045  * - 0x10de0040
3046  */
3047 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3048                 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3049 {
3050         if (cap->ca_index == 0x00 && channels == 2)
3051                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3052
3053         /* If the speaker allocation matches the channel count, it is OK. */
3054         if (cap->channels != channels)
3055                 return -1;
3056
3057         /* all channels are remappable freely */
3058         return SNDRV_CTL_TLVT_CHMAP_VAR;
3059 }
3060
3061 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3062                 int ca, int chs, unsigned char *map)
3063 {
3064         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3065                 return -EINVAL;
3066
3067         return 0;
3068 }
3069
3070 static int patch_nvhdmi(struct hda_codec *codec)
3071 {
3072         struct hdmi_spec *spec;
3073         int err;
3074
3075         err = patch_generic_hdmi(codec);
3076         if (err)
3077                 return err;
3078
3079         spec = codec->spec;
3080         spec->dyn_pin_out = true;
3081
3082         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3083                 nvhdmi_chmap_cea_alloc_validate_get_type;
3084         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3085
3086         return 0;
3087 }
3088
3089 /*
3090  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3091  * accessed using vendor-defined verbs. These registers can be used for
3092  * interoperability between the HDA and HDMI drivers.
3093  */
3094
3095 /* Audio Function Group node */
3096 #define NVIDIA_AFG_NID 0x01
3097
3098 /*
3099  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3100  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3101  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3102  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3103  * additional bit (at position 30) to signal the validity of the format.
3104  *
3105  * | 31      | 30    | 29  16 | 15   0 |
3106  * +---------+-------+--------+--------+
3107  * | TRIGGER | VALID | UNUSED | FORMAT |
3108  * +-----------------------------------|
3109  *
3110  * Note that for the trigger bit to take effect it needs to change value
3111  * (i.e. it needs to be toggled).
3112  */
3113 #define NVIDIA_GET_SCRATCH0             0xfa6
3114 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3115 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3116 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3117 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3118 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3119 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3120
3121 #define NVIDIA_GET_SCRATCH1             0xfab
3122 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3123 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3124 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3125 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3126
3127 /*
3128  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3129  * the format is invalidated so that the HDMI codec can be disabled.
3130  */
3131 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3132 {
3133         unsigned int value;
3134
3135         /* bits [31:30] contain the trigger and valid bits */
3136         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3137                                    NVIDIA_GET_SCRATCH0, 0);
3138         value = (value >> 24) & 0xff;
3139
3140         /* bits [15:0] are used to store the HDA format */
3141         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3142                             NVIDIA_SET_SCRATCH0_BYTE0,
3143                             (format >> 0) & 0xff);
3144         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3145                             NVIDIA_SET_SCRATCH0_BYTE1,
3146                             (format >> 8) & 0xff);
3147
3148         /* bits [16:24] are unused */
3149         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3150                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3151
3152         /*
3153          * Bit 30 signals that the data is valid and hence that HDMI audio can
3154          * be enabled.
3155          */
3156         if (format == 0)
3157                 value &= ~NVIDIA_SCRATCH_VALID;
3158         else
3159                 value |= NVIDIA_SCRATCH_VALID;
3160
3161         /*
3162          * Whenever the trigger bit is toggled, an interrupt is raised in the
3163          * HDMI codec. The HDMI driver will use that as trigger to update its
3164          * configuration.
3165          */
3166         value ^= NVIDIA_SCRATCH_TRIGGER;
3167
3168         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3169                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3170 }
3171
3172 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3173                                   struct hda_codec *codec,
3174                                   unsigned int stream_tag,
3175                                   unsigned int format,
3176                                   struct snd_pcm_substream *substream)
3177 {
3178         int err;
3179
3180         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3181                                                 format, substream);
3182         if (err < 0)
3183                 return err;
3184
3185         /* notify the HDMI codec of the format change */
3186         tegra_hdmi_set_format(codec, format);
3187
3188         return 0;
3189 }
3190
3191 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3192                                   struct hda_codec *codec,
3193                                   struct snd_pcm_substream *substream)
3194 {
3195         /* invalidate the format in the HDMI codec */
3196         tegra_hdmi_set_format(codec, 0);
3197
3198         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3199 }
3200
3201 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3202 {
3203         struct hdmi_spec *spec = codec->spec;
3204         unsigned int i;
3205
3206         for (i = 0; i < spec->num_pins; i++) {
3207                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3208
3209                 if (pcm->pcm_type == type)
3210                         return pcm;
3211         }
3212
3213         return NULL;
3214 }
3215
3216 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3217 {
3218         struct hda_pcm_stream *stream;
3219         struct hda_pcm *pcm;
3220         int err;
3221
3222         err = generic_hdmi_build_pcms(codec);
3223         if (err < 0)
3224                 return err;
3225
3226         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3227         if (!pcm)
3228                 return -ENODEV;
3229
3230         /*
3231          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3232          * codec about format changes.
3233          */
3234         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3235         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3236         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3237
3238         return 0;
3239 }
3240
3241 static int patch_tegra_hdmi(struct hda_codec *codec)
3242 {
3243         struct hdmi_spec *spec;
3244         int err;
3245
3246         err = patch_generic_hdmi(codec);
3247         if (err)
3248                 return err;
3249
3250         codec->depop_delay = 10;
3251         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3252         spec = codec->spec;
3253         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3254                 nvhdmi_chmap_cea_alloc_validate_get_type;
3255         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3256
3257         return 0;
3258 }
3259
3260 /*
3261  * ATI/AMD-specific implementations
3262  */
3263
3264 #define is_amdhdmi_rev3_or_later(codec) \
3265         ((codec)->core.vendor_id == 0x1002aa01 && \
3266          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3267 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3268
3269 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3270 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3271 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3272 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3273 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3274 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3275 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3276 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3277 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3278 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3279 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3280 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3281 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3282 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3283 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3284 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3285 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3286 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3287 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3288 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3289 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3290 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3291 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3292 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3293 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3294
3295 /* AMD specific HDA cvt verbs */
3296 #define ATI_VERB_SET_RAMP_RATE          0x770
3297 #define ATI_VERB_GET_RAMP_RATE          0xf70
3298
3299 #define ATI_OUT_ENABLE 0x1
3300
3301 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3302 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3303
3304 #define ATI_HBR_CAPABLE 0x01
3305 #define ATI_HBR_ENABLE 0x10
3306
3307 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3308                            unsigned char *buf, int *eld_size)
3309 {
3310         /* call hda_eld.c ATI/AMD-specific function */
3311         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3312                                     is_amdhdmi_rev3_or_later(codec));
3313 }
3314
3315 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3316                                         int active_channels, int conn_type)
3317 {
3318         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3319 }
3320
3321 static int atihdmi_paired_swap_fc_lfe(int pos)
3322 {
3323         /*
3324          * ATI/AMD have automatic FC/LFE swap built-in
3325          * when in pairwise mapping mode.
3326          */
3327
3328         switch (pos) {
3329                 /* see channel_allocations[].speakers[] */
3330                 case 2: return 3;
3331                 case 3: return 2;
3332                 default: break;
3333         }
3334
3335         return pos;
3336 }
3337
3338 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3339                         int ca, int chs, unsigned char *map)
3340 {
3341         struct hdac_cea_channel_speaker_allocation *cap;
3342         int i, j;
3343
3344         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3345
3346         cap = snd_hdac_get_ch_alloc_from_ca(ca);
3347         for (i = 0; i < chs; ++i) {
3348                 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3349                 bool ok = false;
3350                 bool companion_ok = false;
3351
3352                 if (!mask)
3353                         continue;
3354
3355                 for (j = 0 + i % 2; j < 8; j += 2) {
3356                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3357                         if (cap->speakers[chan_idx] == mask) {
3358                                 /* channel is in a supported position */
3359                                 ok = true;
3360
3361                                 if (i % 2 == 0 && i + 1 < chs) {
3362                                         /* even channel, check the odd companion */
3363                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3364                                         int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3365                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3366
3367                                         if (comp_mask_req == comp_mask_act)
3368                                                 companion_ok = true;
3369                                         else
3370                                                 return -EINVAL;
3371                                 }
3372                                 break;
3373                         }
3374                 }
3375
3376                 if (!ok)
3377                         return -EINVAL;
3378
3379                 if (companion_ok)
3380                         i++; /* companion channel already checked */
3381         }
3382
3383         return 0;
3384 }
3385
3386 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3387                 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3388 {
3389         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3390         int verb;
3391         int ati_channel_setup = 0;
3392
3393         if (hdmi_slot > 7)
3394                 return -EINVAL;
3395
3396         if (!has_amd_full_remap_support(codec)) {
3397                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3398
3399                 /* In case this is an odd slot but without stream channel, do not
3400                  * disable the slot since the corresponding even slot could have a
3401                  * channel. In case neither have a channel, the slot pair will be
3402                  * disabled when this function is called for the even slot. */
3403                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3404                         return 0;
3405
3406                 hdmi_slot -= hdmi_slot % 2;
3407
3408                 if (stream_channel != 0xf)
3409                         stream_channel -= stream_channel % 2;
3410         }
3411
3412         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3413
3414         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3415
3416         if (stream_channel != 0xf)
3417                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3418
3419         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3420 }
3421
3422 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3423                                 hda_nid_t pin_nid, int asp_slot)
3424 {
3425         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3426         bool was_odd = false;
3427         int ati_asp_slot = asp_slot;
3428         int verb;
3429         int ati_channel_setup;
3430
3431         if (asp_slot > 7)
3432                 return -EINVAL;
3433
3434         if (!has_amd_full_remap_support(codec)) {
3435                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3436                 if (ati_asp_slot % 2 != 0) {
3437                         ati_asp_slot -= 1;
3438                         was_odd = true;
3439                 }
3440         }
3441
3442         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3443
3444         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3445
3446         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3447                 return 0xf;
3448
3449         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3450 }
3451
3452 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3453                 struct hdac_chmap *chmap,
3454                 struct hdac_cea_channel_speaker_allocation *cap,
3455                 int channels)
3456 {
3457         int c;
3458
3459         /*
3460          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3461          * we need to take that into account (a single channel may take 2
3462          * channel slots if we need to carry a silent channel next to it).
3463          * On Rev3+ AMD codecs this function is not used.
3464          */
3465         int chanpairs = 0;
3466
3467         /* We only produce even-numbered channel count TLVs */
3468         if ((channels % 2) != 0)
3469                 return -1;
3470
3471         for (c = 0; c < 7; c += 2) {
3472                 if (cap->speakers[c] || cap->speakers[c+1])
3473                         chanpairs++;
3474         }
3475
3476         if (chanpairs * 2 != channels)
3477                 return -1;
3478
3479         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3480 }
3481
3482 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3483                 struct hdac_cea_channel_speaker_allocation *cap,
3484                 unsigned int *chmap, int channels)
3485 {
3486         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3487         int count = 0;
3488         int c;
3489
3490         for (c = 7; c >= 0; c--) {
3491                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3492                 int spk = cap->speakers[chan];
3493                 if (!spk) {
3494                         /* add N/A channel if the companion channel is occupied */
3495                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3496                                 chmap[count++] = SNDRV_CHMAP_NA;
3497
3498                         continue;
3499                 }
3500
3501                 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3502         }
3503
3504         WARN_ON(count != channels);
3505 }
3506
3507 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3508                                  bool hbr)
3509 {
3510         int hbr_ctl, hbr_ctl_new;
3511
3512         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3513         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3514                 if (hbr)
3515                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3516                 else
3517                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3518
3519                 codec_dbg(codec,
3520                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3521                                 pin_nid,
3522                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3523                                 hbr_ctl_new);
3524
3525                 if (hbr_ctl != hbr_ctl_new)
3526                         snd_hda_codec_write(codec, pin_nid, 0,
3527                                                 ATI_VERB_SET_HBR_CONTROL,
3528                                                 hbr_ctl_new);
3529
3530         } else if (hbr)
3531                 return -EINVAL;
3532
3533         return 0;
3534 }
3535
3536 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3537                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3538 {
3539
3540         if (is_amdhdmi_rev3_or_later(codec)) {
3541                 int ramp_rate = 180; /* default as per AMD spec */
3542                 /* disable ramp-up/down for non-pcm as per AMD spec */
3543                 if (format & AC_FMT_TYPE_NON_PCM)
3544                         ramp_rate = 0;
3545
3546                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3547         }
3548
3549         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3550 }
3551
3552
3553 static int atihdmi_init(struct hda_codec *codec)
3554 {
3555         struct hdmi_spec *spec = codec->spec;
3556         int pin_idx, err;
3557
3558         err = generic_hdmi_init(codec);
3559
3560         if (err)
3561                 return err;
3562
3563         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3564                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3565
3566                 /* make sure downmix information in infoframe is zero */
3567                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3568
3569                 /* enable channel-wise remap mode if supported */
3570                 if (has_amd_full_remap_support(codec))
3571                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3572                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3573                                             ATI_MULTICHANNEL_MODE_SINGLE);
3574         }
3575
3576         return 0;
3577 }
3578
3579 static int patch_atihdmi(struct hda_codec *codec)
3580 {
3581         struct hdmi_spec *spec;
3582         struct hdmi_spec_per_cvt *per_cvt;
3583         int err, cvt_idx;
3584
3585         err = patch_generic_hdmi(codec);
3586
3587         if (err)
3588                 return err;
3589
3590         codec->patch_ops.init = atihdmi_init;
3591
3592         spec = codec->spec;
3593
3594         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3595         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3596         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3597         spec->ops.setup_stream = atihdmi_setup_stream;
3598
3599         spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3600         spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3601
3602         if (!has_amd_full_remap_support(codec)) {
3603                 /* override to ATI/AMD-specific versions with pairwise mapping */
3604                 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3605                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3606                 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3607                                 atihdmi_paired_cea_alloc_to_tlv_chmap;
3608                 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3609         }
3610
3611         /* ATI/AMD converters do not advertise all of their capabilities */
3612         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3613                 per_cvt = get_cvt(spec, cvt_idx);
3614                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3615                 per_cvt->rates |= SUPPORTED_RATES;
3616                 per_cvt->formats |= SUPPORTED_FORMATS;
3617                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3618         }
3619
3620         spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3621
3622         return 0;
3623 }
3624
3625 /* VIA HDMI Implementation */
3626 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3627 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3628
3629 static int patch_via_hdmi(struct hda_codec *codec)
3630 {
3631         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3632 }
3633
3634 /*
3635  * patch entries
3636  */
3637 static const struct hda_device_id snd_hda_id_hdmi[] = {
3638 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3639 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3640 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3641 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3642 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3643 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3644 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3645 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3646 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3647 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3648 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",      patch_nvhdmi_8ch_7x),
3649 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3650 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3651 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3652 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",   patch_nvhdmi),
3653 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",   patch_nvhdmi),
3654 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3655 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3656 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3657 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3658 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3659 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3660 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3661 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3662 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3663 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3664 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3665 /* 17 is known to be absent */
3666 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3667 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3668 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3669 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3670 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3671 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3672 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3673 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3674 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3675 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3676 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3677 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3678 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3679 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3680 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",   patch_nvhdmi),
3681 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",   patch_nvhdmi),
3682 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3683 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",   patch_nvhdmi),
3684 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3685 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",   patch_nvhdmi),
3686 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",   patch_nvhdmi),
3687 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3688 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3689 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3690 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3691 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",   patch_nvhdmi),
3692 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",   patch_nvhdmi),
3693 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",   patch_nvhdmi),
3694 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",   patch_nvhdmi),
3695 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",   patch_nvhdmi),
3696 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3697 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",   patch_nvhdmi),
3698 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",   patch_nvhdmi),
3699 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",   patch_nvhdmi),
3700 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",   patch_nvhdmi),
3701 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",   patch_nvhdmi),
3702 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",   patch_nvhdmi),
3703 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",   patch_nvhdmi),
3704 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",   patch_nvhdmi),
3705 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",   patch_nvhdmi),
3706 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",   patch_nvhdmi),
3707 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",   patch_nvhdmi),
3708 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",   patch_nvhdmi),
3709 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",   patch_nvhdmi),
3710 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",   patch_nvhdmi),
3711 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",   patch_nvhdmi),
3712 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP",   patch_nvhdmi),
3713 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP",   patch_nvhdmi),
3714 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP",   patch_nvhdmi),
3715 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP",   patch_nvhdmi),
3716 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP",   patch_nvhdmi),
3717 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3718 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",    patch_nvhdmi_2ch),
3719 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3720 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3721 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3722 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3723 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3724 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3725 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3726 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3727 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3728 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3729 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3730 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_i915_hsw_hdmi),
3731 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_i915_hsw_hdmi),
3732 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_i915_hsw_hdmi),
3733 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_i915_hsw_hdmi),
3734 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_i915_hsw_hdmi),
3735 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",  patch_i915_hsw_hdmi),
3736 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3737 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3738 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_i915_byt_hdmi),
3739 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3740 /* special ID for generic HDMI */
3741 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3742 {} /* terminator */
3743 };
3744 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3745
3746 MODULE_LICENSE("GPL");
3747 MODULE_DESCRIPTION("HDMI HD-audio codec");
3748 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3749 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3750 MODULE_ALIAS("snd-hda-codec-atihdmi");
3751
3752 static struct hda_codec_driver hdmi_driver = {
3753         .id = snd_hda_id_hdmi,
3754 };
3755
3756 module_hda_codec_driver(hdmi_driver);