sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/jack.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/tlv.h>
  40 #include <sound/hdaudio.h>
  41 #include <sound/hda_i915.h>
  42 #include "hda_codec.h"
  43 #include "hda_local.h"
  44 #include "hda_jack.h"
  45
  46 static bool static_hdmi_pcm;
  47 module_param(static_hdmi_pcm, bool, 0644);
  48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  49
  50 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  51 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  53 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  54 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  55 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  56                                 || is_skylake(codec) || is_broxton(codec) \
  57                                 || is_kabylake(codec))
  58
  59 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  60 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  61 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  62
  63 struct hdmi_spec_per_cvt {
  64         hda_nid_t cvt_nid;
  65         int assigned;
  66         unsigned int channels_min;
  67         unsigned int channels_max;
  68         u32 rates;
  69         u64 formats;
  70         unsigned int maxbps;
  71 };
  72
  73 /* max. connections to a widget */
  74 #define HDA_MAX_CONNECTIONS     32
  75
  76 struct hdmi_spec_per_pin {
  77         hda_nid_t pin_nid;
  78         int num_mux_nids;
  79         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  80         int mux_idx;
  81         hda_nid_t cvt_nid;
  82
  83         struct hda_codec *codec;
  84         struct hdmi_eld sink_eld;
  85         struct mutex lock;
  86         struct delayed_work work;
  87         struct snd_kcontrol *eld_ctl;
  88         int repoll_count;
  89         bool setup; /* the stream has been set up by prepare callback */
  90         int channels; /* current number of channels */
  91         bool non_pcm;
  92         bool chmap_set;         /* channel-map override by ALSA API? */
  93         unsigned char chmap[8]; /* ALSA API channel-map */
  94 #ifdef CONFIG_SND_PROC_FS
  95         struct snd_info_entry *proc_entry;
  96 #endif
  97 };
  98
  99 struct cea_channel_speaker_allocation;
 100
 101 /* operations used by generic code that can be overridden by patches */
 102 struct hdmi_ops {
 103         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 104                            unsigned char *buf, int *eld_size);
 105
 106         /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
 107         int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 108                                     int asp_slot);
 109         int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                                     int asp_slot, int channel);
 111
 112         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 113                                     int ca, int active_channels, int conn_type);
 114
 115         /* enable/disable HBR (HD passthrough) */
 116         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 117
 118         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 119                             hda_nid_t pin_nid, u32 stream_tag, int format);
 120
 121         /* Helpers for producing the channel map TLVs. These can be overridden
 122          * for devices that have non-standard mapping requirements. */
 123         int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
 124                                                  int channels);
 125         void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
 126                                        unsigned int *chmap, int channels);
 127
 128         /* check that the user-given chmap is supported */
 129         int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
 130 };
 131
 132 struct hdmi_spec {
 133         int num_cvts;
 134         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 135         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 136
 137         int num_pins;
 138         struct snd_array pins; /* struct hdmi_spec_per_pin */
 139         struct hda_pcm *pcm_rec[16];
 140         unsigned int channels_max; /* max over all cvts */
 141
 142         struct hdmi_eld temp_eld;
 143         struct hdmi_ops ops;
 144
 145         bool dyn_pin_out;
 146
 147         /*
 148          * Non-generic VIA/NVIDIA specific
 149          */
 150         struct hda_multi_out multiout;
 151         struct hda_pcm_stream pcm_playback;
 152
 153         /* i915/powerwell (Haswell+/Valleyview+) specific */
 154         struct i915_audio_component_audio_ops i915_audio_ops;
 155 };
 156
 157
 158 struct hdmi_audio_infoframe {
 159         u8 type; /* 0x84 */
 160         u8 ver;  /* 0x01 */
 161         u8 len;  /* 0x0a */
 162
 163         u8 checksum;
 164
 165         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 166         u8 SS01_SF24;
 167         u8 CXT04;
 168         u8 CA;
 169         u8 LFEPBL01_LSV36_DM_INH7;
 170 };
 171
 172 struct dp_audio_infoframe {
 173         u8 type; /* 0x84 */
 174         u8 len;  /* 0x1b */
 175         u8 ver;  /* 0x11 << 2 */
 176
 177         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 178         u8 SS01_SF24;
 179         u8 CXT04;
 180         u8 CA;
 181         u8 LFEPBL01_LSV36_DM_INH7;
 182 };
 183
 184 union audio_infoframe {
 185         struct hdmi_audio_infoframe hdmi;
 186         struct dp_audio_infoframe dp;
 187         u8 bytes[0];
 188 };
 189
 190 /*
 191  * CEA speaker placement:
 192  *
 193  *        FLH       FCH        FRH
 194  *  FLW    FL  FLC   FC   FRC   FR   FRW
 195  *
 196  *                                  LFE
 197  *                     TC
 198  *
 199  *          RL  RLC   RC   RRC   RR
 200  *
 201  * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
 202  * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
 203  */
 204 enum cea_speaker_placement {
 205         FL  = (1 <<  0),        /* Front Left           */
 206         FC  = (1 <<  1),        /* Front Center         */
 207         FR  = (1 <<  2),        /* Front Right          */
 208         FLC = (1 <<  3),        /* Front Left Center    */
 209         FRC = (1 <<  4),        /* Front Right Center   */
 210         RL  = (1 <<  5),        /* Rear Left            */
 211         RC  = (1 <<  6),        /* Rear Center          */
 212         RR  = (1 <<  7),        /* Rear Right           */
 213         RLC = (1 <<  8),        /* Rear Left Center     */
 214         RRC = (1 <<  9),        /* Rear Right Center    */
 215         LFE = (1 << 10),        /* Low Frequency Effect */
 216         FLW = (1 << 11),        /* Front Left Wide      */
 217         FRW = (1 << 12),        /* Front Right Wide     */
 218         FLH = (1 << 13),        /* Front Left High      */
 219         FCH = (1 << 14),        /* Front Center High    */
 220         FRH = (1 << 15),        /* Front Right High     */
 221         TC  = (1 << 16),        /* Top Center           */
 222 };
 223
 224 /*
 225  * ELD SA bits in the CEA Speaker Allocation data block
 226  */
 227 static int eld_speaker_allocation_bits[] = {
 228         [0] = FL | FR,
 229         [1] = LFE,
 230         [2] = FC,
 231         [3] = RL | RR,
 232         [4] = RC,
 233         [5] = FLC | FRC,
 234         [6] = RLC | RRC,
 235         /* the following are not defined in ELD yet */
 236         [7] = FLW | FRW,
 237         [8] = FLH | FRH,
 238         [9] = TC,
 239         [10] = FCH,
 240 };
 241
 242 struct cea_channel_speaker_allocation {
 243         int ca_index;
 244         int speakers[8];
 245
 246         /* derived values, just for convenience */
 247         int channels;
 248         int spk_mask;
 249 };
 250
 251 /*
 252  * ALSA sequence is:
 253  *
 254  *       surround40   surround41   surround50   surround51   surround71
 255  * ch0   front left   =            =            =            =
 256  * ch1   front right  =            =            =            =
 257  * ch2   rear left    =            =            =            =
 258  * ch3   rear right   =            =            =            =
 259  * ch4                LFE          center       center       center
 260  * ch5                                          LFE          LFE
 261  * ch6                                                       side left
 262  * ch7                                                       side right
 263  *
 264  * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
 265  */
 266 static int hdmi_channel_mapping[0x32][8] = {
 267         /* stereo */
 268         [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 269         /* 2.1 */
 270         [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 271         /* Dolby Surround */
 272         [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
 273         /* surround40 */
 274         [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
 275         /* 4ch */
 276         [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
 277         /* surround41 */
 278         [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
 279         /* surround50 */
 280         [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
 281         /* surround51 */
 282         [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
 283         /* 7.1 */
 284         [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
 285 };
 286
 287 /*
 288  * This is an ordered list!
 289  *
 290  * The preceding ones have better chances to be selected by
 291  * hdmi_channel_allocation().
 292  */
 293 static struct cea_channel_speaker_allocation channel_allocations[] = {
 294 /*                        channel:   7     6    5    4    3     2    1    0  */
 295 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
 296                                  /* 2.1 */
 297 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
 298                                  /* Dolby Surround */
 299 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
 300                                  /* surround40 */
 301 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
 302                                  /* surround41 */
 303 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
 304                                  /* surround50 */
 305 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 306                                  /* surround51 */
 307 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 308                                  /* 6.1 */
 309 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 310                                  /* surround71 */
 311 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 312
 313 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
 314 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
 315 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
 316 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
 317 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 318 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 319 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 320 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 321 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 322 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 323 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 324 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 325 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 326 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 327 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 328 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 329 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 330 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 331 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 332 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 333 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 334 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 335 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 336 { .ca_index = 0x20,  .speakers = {   0,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 337 { .ca_index = 0x21,  .speakers = {   0,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 338 { .ca_index = 0x22,  .speakers = {  TC,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 339 { .ca_index = 0x23,  .speakers = {  TC,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 340 { .ca_index = 0x24,  .speakers = { FRH,  FLH,  RR,  RL,   0,    0,  FR,  FL } },
 341 { .ca_index = 0x25,  .speakers = { FRH,  FLH,  RR,  RL,   0,  LFE,  FR,  FL } },
 342 { .ca_index = 0x26,  .speakers = { FRW,  FLW,  RR,  RL,   0,    0,  FR,  FL } },
 343 { .ca_index = 0x27,  .speakers = { FRW,  FLW,  RR,  RL,   0,  LFE,  FR,  FL } },
 344 { .ca_index = 0x28,  .speakers = {  TC,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 345 { .ca_index = 0x29,  .speakers = {  TC,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 346 { .ca_index = 0x2a,  .speakers = { FCH,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 347 { .ca_index = 0x2b,  .speakers = { FCH,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 348 { .ca_index = 0x2c,  .speakers = {  TC,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 349 { .ca_index = 0x2d,  .speakers = {  TC,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 350 { .ca_index = 0x2e,  .speakers = { FRH,  FLH,  RR,  RL,  FC,    0,  FR,  FL } },
 351 { .ca_index = 0x2f,  .speakers = { FRH,  FLH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 352 { .ca_index = 0x30,  .speakers = { FRW,  FLW,  RR,  RL,  FC,    0,  FR,  FL } },
 353 { .ca_index = 0x31,  .speakers = { FRW,  FLW,  RR,  RL,  FC,  LFE,  FR,  FL } },
 354 };
 355
 356
 357 /*
 358  * HDMI routines
 359  */
 360
 361 #define get_pin(spec, idx) \
 362         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 363 #define get_cvt(spec, idx) \
 364         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 365 #define get_pcm_rec(spec, idx)  ((spec)->pcm_rec[idx])
 366
 367 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
 368 {
 369         struct hdmi_spec *spec = codec->spec;
 370         int pin_idx;
 371
 372         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 373                 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
 374                         return pin_idx;
 375
 376         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 377         return -EINVAL;
 378 }
 379
 380 static int hinfo_to_pin_index(struct hda_codec *codec,
 381                               struct hda_pcm_stream *hinfo)
 382 {
 383         struct hdmi_spec *spec = codec->spec;
 384         int pin_idx;
 385
 386         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 387                 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
 388                         return pin_idx;
 389
 390         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 391         return -EINVAL;
 392 }
 393
 394 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 395 {
 396         struct hdmi_spec *spec = codec->spec;
 397         int cvt_idx;
 398
 399         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 400                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 401                         return cvt_idx;
 402
 403         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 404         return -EINVAL;
 405 }
 406
 407 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 408                         struct snd_ctl_elem_info *uinfo)
 409 {
 410         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 411         struct hdmi_spec *spec = codec->spec;
 412         struct hdmi_spec_per_pin *per_pin;
 413         struct hdmi_eld *eld;
 414         int pin_idx;
 415
 416         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 417
 418         pin_idx = kcontrol->private_value;
 419         per_pin = get_pin(spec, pin_idx);
 420         eld = &per_pin->sink_eld;
 421
 422         mutex_lock(&per_pin->lock);
 423         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 424         mutex_unlock(&per_pin->lock);
 425
 426         return 0;
 427 }
 428
 429 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 430                         struct snd_ctl_elem_value *ucontrol)
 431 {
 432         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 433         struct hdmi_spec *spec = codec->spec;
 434         struct hdmi_spec_per_pin *per_pin;
 435         struct hdmi_eld *eld;
 436         int pin_idx;
 437
 438         pin_idx = kcontrol->private_value;
 439         per_pin = get_pin(spec, pin_idx);
 440         eld = &per_pin->sink_eld;
 441
 442         mutex_lock(&per_pin->lock);
 443         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
 444             eld->eld_size > ELD_MAX_SIZE) {
 445                 mutex_unlock(&per_pin->lock);
 446                 snd_BUG();
 447                 return -EINVAL;
 448         }
 449
 450         memset(ucontrol->value.bytes.data, 0,
 451                ARRAY_SIZE(ucontrol->value.bytes.data));
 452         if (eld->eld_valid)
 453                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 454                        eld->eld_size);
 455         mutex_unlock(&per_pin->lock);
 456
 457         return 0;
 458 }
 459
 460 static struct snd_kcontrol_new eld_bytes_ctl = {
 461         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 462         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 463         .name = "ELD",
 464         .info = hdmi_eld_ctl_info,
 465         .get = hdmi_eld_ctl_get,
 466 };
 467
 468 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
 469                         int device)
 470 {
 471         struct snd_kcontrol *kctl;
 472         struct hdmi_spec *spec = codec->spec;
 473         int err;
 474
 475         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 476         if (!kctl)
 477                 return -ENOMEM;
 478         kctl->private_value = pin_idx;
 479         kctl->id.device = device;
 480
 481         err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
 482         if (err < 0)
 483                 return err;
 484
 485         get_pin(spec, pin_idx)->eld_ctl = kctl;
 486         return 0;
 487 }
 488
 489 #ifdef BE_PARANOID
 490 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 491                                 int *packet_index, int *byte_index)
 492 {
 493         int val;
 494
 495         val = snd_hda_codec_read(codec, pin_nid, 0,
 496                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 497
 498         *packet_index = val >> 5;
 499         *byte_index = val & 0x1f;
 500 }
 501 #endif
 502
 503 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 504                                 int packet_index, int byte_index)
 505 {
 506         int val;
 507
 508         val = (packet_index << 5) | (byte_index & 0x1f);
 509
 510         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 511 }
 512
 513 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 514                                 unsigned char val)
 515 {
 516         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 517 }
 518
 519 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 520 {
 521         struct hdmi_spec *spec = codec->spec;
 522         int pin_out;
 523
 524         /* Unmute */
 525         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 526                 snd_hda_codec_write(codec, pin_nid, 0,
 527                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 528
 529         if (spec->dyn_pin_out)
 530                 /* Disable pin out until stream is active */
 531                 pin_out = 0;
 532         else
 533                 /* Enable pin out: some machines with GM965 gets broken output
 534                  * when the pin is disabled or changed while using with HDMI
 535                  */
 536                 pin_out = PIN_OUT;
 537
 538         snd_hda_codec_write(codec, pin_nid, 0,
 539                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 540 }
 541
 542 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
 543 {
 544         return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
 545                                         AC_VERB_GET_CVT_CHAN_COUNT, 0);
 546 }
 547
 548 static void hdmi_set_channel_count(struct hda_codec *codec,
 549                                    hda_nid_t cvt_nid, int chs)
 550 {
 551         if (chs != hdmi_get_channel_count(codec, cvt_nid))
 552                 snd_hda_codec_write(codec, cvt_nid, 0,
 553                                     AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
 554 }
 555
 556 /*
 557  * ELD proc files
 558  */
 559
 560 #ifdef CONFIG_SND_PROC_FS
 561 static void print_eld_info(struct snd_info_entry *entry,
 562                            struct snd_info_buffer *buffer)
 563 {
 564         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 565
 566         mutex_lock(&per_pin->lock);
 567         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 568         mutex_unlock(&per_pin->lock);
 569 }
 570
 571 static void write_eld_info(struct snd_info_entry *entry,
 572                            struct snd_info_buffer *buffer)
 573 {
 574         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 575
 576         mutex_lock(&per_pin->lock);
 577         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 578         mutex_unlock(&per_pin->lock);
 579 }
 580
 581 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 582 {
 583         char name[32];
 584         struct hda_codec *codec = per_pin->codec;
 585         struct snd_info_entry *entry;
 586         int err;
 587
 588         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 589         err = snd_card_proc_new(codec->card, name, &entry);
 590         if (err < 0)
 591                 return err;
 592
 593         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 594         entry->c.text.write = write_eld_info;
 595         entry->mode |= S_IWUSR;
 596         per_pin->proc_entry = entry;
 597
 598         return 0;
 599 }
 600
 601 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 602 {
 603         if (!per_pin->codec->bus->shutdown) {
 604                 snd_info_free_entry(per_pin->proc_entry);
 605                 per_pin->proc_entry = NULL;
 606         }
 607 }
 608 #else
 609 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 610                                int index)
 611 {
 612         return 0;
 613 }
 614 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 615 {
 616 }
 617 #endif
 618
 619 /*
 620  * Channel mapping routines
 621  */
 622
 623 /*
 624  * Compute derived values in channel_allocations[].
 625  */
 626 static void init_channel_allocations(void)
 627 {
 628         int i, j;
 629         struct cea_channel_speaker_allocation *p;
 630
 631         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 632                 p = channel_allocations + i;
 633                 p->channels = 0;
 634                 p->spk_mask = 0;
 635                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 636                         if (p->speakers[j]) {
 637                                 p->channels++;
 638                                 p->spk_mask |= p->speakers[j];
 639                         }
 640         }
 641 }
 642
 643 static int get_channel_allocation_order(int ca)
 644 {
 645         int i;
 646
 647         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 648                 if (channel_allocations[i].ca_index == ca)
 649                         break;
 650         }
 651         return i;
 652 }
 653
 654 /*
 655  * The transformation takes two steps:
 656  *
 657  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 658  *            spk_mask => (channel_allocations[])         => ai->CA
 659  *
 660  * TODO: it could select the wrong CA from multiple candidates.
 661 */
 662 static int hdmi_channel_allocation(struct hda_codec *codec,
 663                                    struct hdmi_eld *eld, int channels)
 664 {
 665         int i;
 666         int ca = 0;
 667         int spk_mask = 0;
 668         char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
 669
 670         /*
 671          * CA defaults to 0 for basic stereo audio
 672          */
 673         if (channels <= 2)
 674                 return 0;
 675
 676         /*
 677          * expand ELD's speaker allocation mask
 678          *
 679          * ELD tells the speaker mask in a compact(paired) form,
 680          * expand ELD's notions to match the ones used by Audio InfoFrame.
 681          */
 682         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 683                 if (eld->info.spk_alloc & (1 << i))
 684                         spk_mask |= eld_speaker_allocation_bits[i];
 685         }
 686
 687         /* search for the first working match in the CA table */
 688         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 689                 if (channels == channel_allocations[i].channels &&
 690                     (spk_mask & channel_allocations[i].spk_mask) ==
 691                                 channel_allocations[i].spk_mask) {
 692                         ca = channel_allocations[i].ca_index;
 693                         break;
 694                 }
 695         }
 696
 697         if (!ca) {
 698                 /* if there was no match, select the regular ALSA channel
 699                  * allocation with the matching number of channels */
 700                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 701                         if (channels == channel_allocations[i].channels) {
 702                                 ca = channel_allocations[i].ca_index;
 703                                 break;
 704                         }
 705                 }
 706         }
 707
 708         snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
 709         codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
 710                     ca, channels, buf);
 711
 712         return ca;
 713 }
 714
 715 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
 716                                        hda_nid_t pin_nid)
 717 {
 718 #ifdef CONFIG_SND_DEBUG_VERBOSE
 719         struct hdmi_spec *spec = codec->spec;
 720         int i;
 721         int channel;
 722
 723         for (i = 0; i < 8; i++) {
 724                 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
 725                 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
 726                                                 channel, i);
 727         }
 728 #endif
 729 }
 730
 731 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
 732                                        hda_nid_t pin_nid,
 733                                        bool non_pcm,
 734                                        int ca)
 735 {
 736         struct hdmi_spec *spec = codec->spec;
 737         struct cea_channel_speaker_allocation *ch_alloc;
 738         int i;
 739         int err;
 740         int order;
 741         int non_pcm_mapping[8];
 742
 743         order = get_channel_allocation_order(ca);
 744         ch_alloc = &channel_allocations[order];
 745
 746         if (hdmi_channel_mapping[ca][1] == 0) {
 747                 int hdmi_slot = 0;
 748                 /* fill actual channel mappings in ALSA channel (i) order */
 749                 for (i = 0; i < ch_alloc->channels; i++) {
 750                         while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
 751                                 hdmi_slot++; /* skip zero slots */
 752
 753                         hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
 754                 }
 755                 /* fill the rest of the slots with ALSA channel 0xf */
 756                 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
 757                         if (!ch_alloc->speakers[7 - hdmi_slot])
 758                                 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
 759         }
 760
 761         if (non_pcm) {
 762                 for (i = 0; i < ch_alloc->channels; i++)
 763                         non_pcm_mapping[i] = (i << 4) | i;
 764                 for (; i < 8; i++)
 765                         non_pcm_mapping[i] = (0xf << 4) | i;
 766         }
 767
 768         for (i = 0; i < 8; i++) {
 769                 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
 770                 int hdmi_slot = slotsetup & 0x0f;
 771                 int channel = (slotsetup & 0xf0) >> 4;
 772                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
 773                 if (err) {
 774                         codec_dbg(codec, "HDMI: channel mapping failed\n");
 775                         break;
 776                 }
 777         }
 778 }
 779
 780 struct channel_map_table {
 781         unsigned char map;              /* ALSA API channel map position */
 782         int spk_mask;                   /* speaker position bit mask */
 783 };
 784
 785 static struct channel_map_table map_tables[] = {
 786         { SNDRV_CHMAP_FL,       FL },
 787         { SNDRV_CHMAP_FR,       FR },
 788         { SNDRV_CHMAP_RL,       RL },
 789         { SNDRV_CHMAP_RR,       RR },
 790         { SNDRV_CHMAP_LFE,      LFE },
 791         { SNDRV_CHMAP_FC,       FC },
 792         { SNDRV_CHMAP_RLC,      RLC },
 793         { SNDRV_CHMAP_RRC,      RRC },
 794         { SNDRV_CHMAP_RC,       RC },
 795         { SNDRV_CHMAP_FLC,      FLC },
 796         { SNDRV_CHMAP_FRC,      FRC },
 797         { SNDRV_CHMAP_TFL,      FLH },
 798         { SNDRV_CHMAP_TFR,      FRH },
 799         { SNDRV_CHMAP_FLW,      FLW },
 800         { SNDRV_CHMAP_FRW,      FRW },
 801         { SNDRV_CHMAP_TC,       TC },
 802         { SNDRV_CHMAP_TFC,      FCH },
 803         {} /* terminator */
 804 };
 805
 806 /* from ALSA API channel position to speaker bit mask */
 807 static int to_spk_mask(unsigned char c)
 808 {
 809         struct channel_map_table *t = map_tables;
 810         for (; t->map; t++) {
 811                 if (t->map == c)
 812                         return t->spk_mask;
 813         }
 814         return 0;
 815 }
 816
 817 /* from ALSA API channel position to CEA slot */
 818 static int to_cea_slot(int ordered_ca, unsigned char pos)
 819 {
 820         int mask = to_spk_mask(pos);
 821         int i;
 822
 823         if (mask) {
 824                 for (i = 0; i < 8; i++) {
 825                         if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
 826                                 return i;
 827                 }
 828         }
 829
 830         return -1;
 831 }
 832
 833 /* from speaker bit mask to ALSA API channel position */
 834 static int spk_to_chmap(int spk)
 835 {
 836         struct channel_map_table *t = map_tables;
 837         for (; t->map; t++) {
 838                 if (t->spk_mask == spk)
 839                         return t->map;
 840         }
 841         return 0;
 842 }
 843
 844 /* from CEA slot to ALSA API channel position */
 845 static int from_cea_slot(int ordered_ca, unsigned char slot)
 846 {
 847         int mask = channel_allocations[ordered_ca].speakers[7 - slot];
 848
 849         return spk_to_chmap(mask);
 850 }
 851
 852 /* get the CA index corresponding to the given ALSA API channel map */
 853 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
 854 {
 855         int i, spks = 0, spk_mask = 0;
 856
 857         for (i = 0; i < chs; i++) {
 858                 int mask = to_spk_mask(map[i]);
 859                 if (mask) {
 860                         spk_mask |= mask;
 861                         spks++;
 862                 }
 863         }
 864
 865         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 866                 if ((chs == channel_allocations[i].channels ||
 867                      spks == channel_allocations[i].channels) &&
 868                     (spk_mask & channel_allocations[i].spk_mask) ==
 869                                 channel_allocations[i].spk_mask)
 870                         return channel_allocations[i].ca_index;
 871         }
 872         return -1;
 873 }
 874
 875 /* set up the channel slots for the given ALSA API channel map */
 876 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
 877                                              hda_nid_t pin_nid,
 878                                              int chs, unsigned char *map,
 879                                              int ca)
 880 {
 881         struct hdmi_spec *spec = codec->spec;
 882         int ordered_ca = get_channel_allocation_order(ca);
 883         int alsa_pos, hdmi_slot;
 884         int assignments[8] = {[0 ... 7] = 0xf};
 885
 886         for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
 887
 888                 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
 889
 890                 if (hdmi_slot < 0)
 891                         continue; /* unassigned channel */
 892
 893                 assignments[hdmi_slot] = alsa_pos;
 894         }
 895
 896         for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
 897                 int err;
 898
 899                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
 900                                                      assignments[hdmi_slot]);
 901                 if (err)
 902                         return -EINVAL;
 903         }
 904         return 0;
 905 }
 906
 907 /* store ALSA API channel map from the current default map */
 908 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
 909 {
 910         int i;
 911         int ordered_ca = get_channel_allocation_order(ca);
 912         for (i = 0; i < 8; i++) {
 913                 if (i < channel_allocations[ordered_ca].channels)
 914                         map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
 915                 else
 916                         map[i] = 0;
 917         }
 918 }
 919
 920 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
 921                                        hda_nid_t pin_nid, bool non_pcm, int ca,
 922                                        int channels, unsigned char *map,
 923                                        bool chmap_set)
 924 {
 925         if (!non_pcm && chmap_set) {
 926                 hdmi_manual_setup_channel_mapping(codec, pin_nid,
 927                                                   channels, map, ca);
 928         } else {
 929                 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
 930                 hdmi_setup_fake_chmap(map, ca);
 931         }
 932
 933         hdmi_debug_channel_mapping(codec, pin_nid);
 934 }
 935
 936 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 937                                      int asp_slot, int channel)
 938 {
 939         return snd_hda_codec_write(codec, pin_nid, 0,
 940                                    AC_VERB_SET_HDMI_CHAN_SLOT,
 941                                    (channel << 4) | asp_slot);
 942 }
 943
 944 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 945                                      int asp_slot)
 946 {
 947         return (snd_hda_codec_read(codec, pin_nid, 0,
 948                                    AC_VERB_GET_HDMI_CHAN_SLOT,
 949                                    asp_slot) & 0xf0) >> 4;
 950 }
 951
 952 /*
 953  * Audio InfoFrame routines
 954  */
 955
 956 /*
 957  * Enable Audio InfoFrame Transmission
 958  */
 959 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 960                                        hda_nid_t pin_nid)
 961 {
 962         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 963         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 964                                                 AC_DIPXMIT_BEST);
 965 }
 966
 967 /*
 968  * Disable Audio InfoFrame Transmission
 969  */
 970 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 971                                       hda_nid_t pin_nid)
 972 {
 973         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 974         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 975                                                 AC_DIPXMIT_DISABLE);
 976 }
 977
 978 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 979 {
 980 #ifdef CONFIG_SND_DEBUG_VERBOSE
 981         int i;
 982         int size;
 983
 984         size = snd_hdmi_get_eld_size(codec, pin_nid);
 985         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 986
 987         for (i = 0; i < 8; i++) {
 988                 size = snd_hda_codec_read(codec, pin_nid, 0,
 989                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 990                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 991         }
 992 #endif
 993 }
 994
 995 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 996 {
 997 #ifdef BE_PARANOID
 998         int i, j;
 999         int size;
1000         int pi, bi;
1001         for (i = 0; i < 8; i++) {
1002                 size = snd_hda_codec_read(codec, pin_nid, 0,
1003                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
1004                 if (size == 0)
1005                         continue;
1006
1007                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1008                 for (j = 1; j < 1000; j++) {
1009                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
1010                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1011                         if (pi != i)
1012                                 codec_dbg(codec, "dip index %d: %d != %d\n",
1013                                                 bi, pi, i);
1014                         if (bi == 0) /* byte index wrapped around */
1015                                 break;
1016                 }
1017                 codec_dbg(codec,
1018                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1019                         i, size, j);
1020         }
1021 #endif
1022 }
1023
1024 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1025 {
1026         u8 *bytes = (u8 *)hdmi_ai;
1027         u8 sum = 0;
1028         int i;
1029
1030         hdmi_ai->checksum = 0;
1031
1032         for (i = 0; i < sizeof(*hdmi_ai); i++)
1033                 sum += bytes[i];
1034
1035         hdmi_ai->checksum = -sum;
1036 }
1037
1038 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1039                                       hda_nid_t pin_nid,
1040                                       u8 *dip, int size)
1041 {
1042         int i;
1043
1044         hdmi_debug_dip_size(codec, pin_nid);
1045         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1046
1047         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1048         for (i = 0; i < size; i++)
1049                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1050 }
1051
1052 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1053                                     u8 *dip, int size)
1054 {
1055         u8 val;
1056         int i;
1057
1058         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1059                                                             != AC_DIPXMIT_BEST)
1060                 return false;
1061
1062         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1063         for (i = 0; i < size; i++) {
1064                 val = snd_hda_codec_read(codec, pin_nid, 0,
1065                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
1066                 if (val != dip[i])
1067                         return false;
1068         }
1069
1070         return true;
1071 }
1072
1073 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1074                                      hda_nid_t pin_nid,
1075                                      int ca, int active_channels,
1076                                      int conn_type)
1077 {
1078         union audio_infoframe ai;
1079
1080         memset(&ai, 0, sizeof(ai));
1081         if (conn_type == 0) { /* HDMI */
1082                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1083
1084                 hdmi_ai->type           = 0x84;
1085                 hdmi_ai->ver            = 0x01;
1086                 hdmi_ai->len            = 0x0a;
1087                 hdmi_ai->CC02_CT47      = active_channels - 1;
1088                 hdmi_ai->CA             = ca;
1089                 hdmi_checksum_audio_infoframe(hdmi_ai);
1090         } else if (conn_type == 1) { /* DisplayPort */
1091                 struct dp_audio_infoframe *dp_ai = &ai.dp;
1092
1093                 dp_ai->type             = 0x84;
1094                 dp_ai->len              = 0x1b;
1095                 dp_ai->ver              = 0x11 << 2;
1096                 dp_ai->CC02_CT47        = active_channels - 1;
1097                 dp_ai->CA               = ca;
1098         } else {
1099                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1100                             pin_nid);
1101                 return;
1102         }
1103
1104         /*
1105          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1106          * sizeof(*dp_ai) to avoid partial match/update problems when
1107          * the user switches between HDMI/DP monitors.
1108          */
1109         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1110                                         sizeof(ai))) {
1111                 codec_dbg(codec,
1112                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1113                             pin_nid,
1114                             active_channels, ca);
1115                 hdmi_stop_infoframe_trans(codec, pin_nid);
1116                 hdmi_fill_audio_infoframe(codec, pin_nid,
1117                                             ai.bytes, sizeof(ai));
1118                 hdmi_start_infoframe_trans(codec, pin_nid);
1119         }
1120 }
1121
1122 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1123                                        struct hdmi_spec_per_pin *per_pin,
1124                                        bool non_pcm)
1125 {
1126         struct hdmi_spec *spec = codec->spec;
1127         hda_nid_t pin_nid = per_pin->pin_nid;
1128         int channels = per_pin->channels;
1129         int active_channels;
1130         struct hdmi_eld *eld;
1131         int ca, ordered_ca;
1132
1133         if (!channels)
1134                 return;
1135
1136         if (is_haswell_plus(codec))
1137                 snd_hda_codec_write(codec, pin_nid, 0,
1138                                             AC_VERB_SET_AMP_GAIN_MUTE,
1139                                             AMP_OUT_UNMUTE);
1140
1141         eld = &per_pin->sink_eld;
1142
1143         if (!non_pcm && per_pin->chmap_set)
1144                 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1145         else
1146                 ca = hdmi_channel_allocation(codec, eld, channels);
1147         if (ca < 0)
1148                 ca = 0;
1149
1150         ordered_ca = get_channel_allocation_order(ca);
1151         active_channels = channel_allocations[ordered_ca].channels;
1152
1153         hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1154
1155         /*
1156          * always configure channel mapping, it may have been changed by the
1157          * user in the meantime
1158          */
1159         hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1160                                    channels, per_pin->chmap,
1161                                    per_pin->chmap_set);
1162
1163         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1164                                       eld->info.conn_type);
1165
1166         per_pin->non_pcm = non_pcm;
1167 }
1168
1169 /*
1170  * Unsolicited events
1171  */
1172
1173 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1174
1175 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1176 {
1177         struct hdmi_spec *spec = codec->spec;
1178         int pin_idx = pin_nid_to_pin_index(codec, nid);
1179
1180         if (pin_idx < 0)
1181                 return;
1182         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1183                 snd_hda_jack_report_sync(codec);
1184 }
1185
1186 static void jack_callback(struct hda_codec *codec,
1187                           struct hda_jack_callback *jack)
1188 {
1189         check_presence_and_report(codec, jack->nid);
1190 }
1191
1192 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1193 {
1194         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1195         struct hda_jack_tbl *jack;
1196         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1197
1198         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1199         if (!jack)
1200                 return;
1201         jack->jack_dirty = 1;
1202
1203         codec_dbg(codec,
1204                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1205                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1206                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1207
1208         check_presence_and_report(codec, jack->nid);
1209 }
1210
1211 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1212 {
1213         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1214         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1215         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1216         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1217
1218         codec_info(codec,
1219                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1220                 codec->addr,
1221                 tag,
1222                 subtag,
1223                 cp_state,
1224                 cp_ready);
1225
1226         /* TODO */
1227         if (cp_state)
1228                 ;
1229         if (cp_ready)
1230                 ;
1231 }
1232
1233
1234 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1235 {
1236         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1237         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1238
1239         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1240                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1241                 return;
1242         }
1243
1244         if (subtag == 0)
1245                 hdmi_intrinsic_event(codec, res);
1246         else
1247                 hdmi_non_intrinsic_event(codec, res);
1248 }
1249
1250 static void haswell_verify_D0(struct hda_codec *codec,
1251                 hda_nid_t cvt_nid, hda_nid_t nid)
1252 {
1253         int pwr;
1254
1255         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1256          * thus pins could only choose converter 0 for use. Make sure the
1257          * converters are in correct power state */
1258         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1259                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1260
1261         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1262                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1263                                     AC_PWRST_D0);
1264                 msleep(40);
1265                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1266                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1267                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1268         }
1269 }
1270
1271 /*
1272  * Callbacks
1273  */
1274
1275 /* HBR should be Non-PCM, 8 channels */
1276 #define is_hbr_format(format) \
1277         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1278
1279 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1280                               bool hbr)
1281 {
1282         int pinctl, new_pinctl;
1283
1284         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1285                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1286                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1287
1288                 if (pinctl < 0)
1289                         return hbr ? -EINVAL : 0;
1290
1291                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1292                 if (hbr)
1293                         new_pinctl |= AC_PINCTL_EPT_HBR;
1294                 else
1295                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
1296
1297                 codec_dbg(codec,
1298                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1299                             pin_nid,
1300                             pinctl == new_pinctl ? "" : "new-",
1301                             new_pinctl);
1302
1303                 if (pinctl != new_pinctl)
1304                         snd_hda_codec_write(codec, pin_nid, 0,
1305                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1306                                             new_pinctl);
1307         } else if (hbr)
1308                 return -EINVAL;
1309
1310         return 0;
1311 }
1312
1313 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1314                               hda_nid_t pin_nid, u32 stream_tag, int format)
1315 {
1316         struct hdmi_spec *spec = codec->spec;
1317         int err;
1318
1319         if (is_haswell_plus(codec))
1320                 haswell_verify_D0(codec, cvt_nid, pin_nid);
1321
1322         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1323
1324         if (err) {
1325                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1326                 return err;
1327         }
1328
1329         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1330         return 0;
1331 }
1332
1333 static int hdmi_choose_cvt(struct hda_codec *codec,
1334                         int pin_idx, int *cvt_id, int *mux_id)
1335 {
1336         struct hdmi_spec *spec = codec->spec;
1337         struct hdmi_spec_per_pin *per_pin;
1338         struct hdmi_spec_per_cvt *per_cvt = NULL;
1339         int cvt_idx, mux_idx = 0;
1340
1341         per_pin = get_pin(spec, pin_idx);
1342
1343         /* Dynamically assign converter to stream */
1344         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1345                 per_cvt = get_cvt(spec, cvt_idx);
1346
1347                 /* Must not already be assigned */
1348                 if (per_cvt->assigned)
1349                         continue;
1350                 /* Must be in pin's mux's list of converters */
1351                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1352                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1353                                 break;
1354                 /* Not in mux list */
1355                 if (mux_idx == per_pin->num_mux_nids)
1356                         continue;
1357                 break;
1358         }
1359
1360         /* No free converters */
1361         if (cvt_idx == spec->num_cvts)
1362                 return -ENODEV;
1363
1364         per_pin->mux_idx = mux_idx;
1365
1366         if (cvt_id)
1367                 *cvt_id = cvt_idx;
1368         if (mux_id)
1369                 *mux_id = mux_idx;
1370
1371         return 0;
1372 }
1373
1374 /* Assure the pin select the right convetor */
1375 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1376                         struct hdmi_spec_per_pin *per_pin)
1377 {
1378         hda_nid_t pin_nid = per_pin->pin_nid;
1379         int mux_idx, curr;
1380
1381         mux_idx = per_pin->mux_idx;
1382         curr = snd_hda_codec_read(codec, pin_nid, 0,
1383                                           AC_VERB_GET_CONNECT_SEL, 0);
1384         if (curr != mux_idx)
1385                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1386                                             AC_VERB_SET_CONNECT_SEL,
1387                                             mux_idx);
1388 }
1389
1390 /* Intel HDMI workaround to fix audio routing issue:
1391  * For some Intel display codecs, pins share the same connection list.
1392  * So a conveter can be selected by multiple pins and playback on any of these
1393  * pins will generate sound on the external display, because audio flows from
1394  * the same converter to the display pipeline. Also muting one pin may make
1395  * other pins have no sound output.
1396  * So this function assures that an assigned converter for a pin is not selected
1397  * by any other pins.
1398  */
1399 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1400                         hda_nid_t pin_nid, int mux_idx)
1401 {
1402         struct hdmi_spec *spec = codec->spec;
1403         hda_nid_t nid;
1404         int cvt_idx, curr;
1405         struct hdmi_spec_per_cvt *per_cvt;
1406
1407         /* configure all pins, including "no physical connection" ones */
1408         for_each_hda_codec_node(nid, codec) {
1409                 unsigned int wid_caps = get_wcaps(codec, nid);
1410                 unsigned int wid_type = get_wcaps_type(wid_caps);
1411
1412                 if (wid_type != AC_WID_PIN)
1413                         continue;
1414
1415                 if (nid == pin_nid)
1416                         continue;
1417
1418                 curr = snd_hda_codec_read(codec, nid, 0,
1419                                           AC_VERB_GET_CONNECT_SEL, 0);
1420                 if (curr != mux_idx)
1421                         continue;
1422
1423                 /* choose an unassigned converter. The conveters in the
1424                  * connection list are in the same order as in the codec.
1425                  */
1426                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1427                         per_cvt = get_cvt(spec, cvt_idx);
1428                         if (!per_cvt->assigned) {
1429                                 codec_dbg(codec,
1430                                           "choose cvt %d for pin nid %d\n",
1431                                         cvt_idx, nid);
1432                                 snd_hda_codec_write_cache(codec, nid, 0,
1433                                             AC_VERB_SET_CONNECT_SEL,
1434                                             cvt_idx);
1435                                 break;
1436                         }
1437                 }
1438         }
1439 }
1440
1441 /*
1442  * HDA PCM callbacks
1443  */
1444 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1445                          struct hda_codec *codec,
1446                          struct snd_pcm_substream *substream)
1447 {
1448         struct hdmi_spec *spec = codec->spec;
1449         struct snd_pcm_runtime *runtime = substream->runtime;
1450         int pin_idx, cvt_idx, mux_idx = 0;
1451         struct hdmi_spec_per_pin *per_pin;
1452         struct hdmi_eld *eld;
1453         struct hdmi_spec_per_cvt *per_cvt = NULL;
1454         int err;
1455
1456         /* Validate hinfo */
1457         pin_idx = hinfo_to_pin_index(codec, hinfo);
1458         if (snd_BUG_ON(pin_idx < 0))
1459                 return -EINVAL;
1460         per_pin = get_pin(spec, pin_idx);
1461         eld = &per_pin->sink_eld;
1462
1463         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1464         if (err < 0)
1465                 return err;
1466
1467         per_cvt = get_cvt(spec, cvt_idx);
1468         /* Claim converter */
1469         per_cvt->assigned = 1;
1470         per_pin->cvt_nid = per_cvt->cvt_nid;
1471         hinfo->nid = per_cvt->cvt_nid;
1472
1473         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1474                             AC_VERB_SET_CONNECT_SEL,
1475                             mux_idx);
1476
1477         /* configure unused pins to choose other converters */
1478         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1479                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1480
1481         snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1482
1483         /* Initially set the converter's capabilities */
1484         hinfo->channels_min = per_cvt->channels_min;
1485         hinfo->channels_max = per_cvt->channels_max;
1486         hinfo->rates = per_cvt->rates;
1487         hinfo->formats = per_cvt->formats;
1488         hinfo->maxbps = per_cvt->maxbps;
1489
1490         /* Restrict capabilities by ELD if this isn't disabled */
1491         if (!static_hdmi_pcm && eld->eld_valid) {
1492                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1493                 if (hinfo->channels_min > hinfo->channels_max ||
1494                     !hinfo->rates || !hinfo->formats) {
1495                         per_cvt->assigned = 0;
1496                         hinfo->nid = 0;
1497                         snd_hda_spdif_ctls_unassign(codec, pin_idx);
1498                         return -ENODEV;
1499                 }
1500         }
1501
1502         /* Store the updated parameters */
1503         runtime->hw.channels_min = hinfo->channels_min;
1504         runtime->hw.channels_max = hinfo->channels_max;
1505         runtime->hw.formats = hinfo->formats;
1506         runtime->hw.rates = hinfo->rates;
1507
1508         snd_pcm_hw_constraint_step(substream->runtime, 0,
1509                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1510         return 0;
1511 }
1512
1513 /*
1514  * HDA/HDMI auto parsing
1515  */
1516 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1517 {
1518         struct hdmi_spec *spec = codec->spec;
1519         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1520         hda_nid_t pin_nid = per_pin->pin_nid;
1521
1522         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1523                 codec_warn(codec,
1524                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1525                            pin_nid, get_wcaps(codec, pin_nid));
1526                 return -EINVAL;
1527         }
1528
1529         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1530                                                         per_pin->mux_nids,
1531                                                         HDA_MAX_CONNECTIONS);
1532
1533         return 0;
1534 }
1535
1536 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1537 {
1538         struct hda_jack_tbl *jack;
1539         struct hda_codec *codec = per_pin->codec;
1540         struct hdmi_spec *spec = codec->spec;
1541         struct hdmi_eld *eld = &spec->temp_eld;
1542         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1543         hda_nid_t pin_nid = per_pin->pin_nid;
1544         /*
1545          * Always execute a GetPinSense verb here, even when called from
1546          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1547          * response's PD bit is not the real PD value, but indicates that
1548          * the real PD value changed. An older version of the HD-audio
1549          * specification worked this way. Hence, we just ignore the data in
1550          * the unsolicited response to avoid custom WARs.
1551          */
1552         int present;
1553         bool update_eld = false;
1554         bool eld_changed = false;
1555         bool ret;
1556
1557         snd_hda_power_up_pm(codec);
1558         present = snd_hda_pin_sense(codec, pin_nid);
1559
1560         mutex_lock(&per_pin->lock);
1561         pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1562         if (pin_eld->monitor_present)
1563                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1564         else
1565                 eld->eld_valid = false;
1566
1567         codec_dbg(codec,
1568                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1569                 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1570
1571         if (eld->eld_valid) {
1572                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1573                                                      &eld->eld_size) < 0)
1574                         eld->eld_valid = false;
1575                 else {
1576                         memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1577                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1578                                                     eld->eld_size) < 0)
1579                                 eld->eld_valid = false;
1580                 }
1581
1582                 if (eld->eld_valid) {
1583                         snd_hdmi_show_eld(codec, &eld->info);
1584                         update_eld = true;
1585                 }
1586                 else if (repoll) {
1587                         schedule_delayed_work(&per_pin->work,
1588                                               msecs_to_jiffies(300));
1589                         goto unlock;
1590                 }
1591         }
1592
1593         if (pin_eld->eld_valid != eld->eld_valid)
1594                 eld_changed = true;
1595
1596         if (pin_eld->eld_valid && !eld->eld_valid)
1597                 update_eld = true;
1598
1599         if (update_eld) {
1600                 bool old_eld_valid = pin_eld->eld_valid;
1601                 pin_eld->eld_valid = eld->eld_valid;
1602                 if (pin_eld->eld_size != eld->eld_size ||
1603                               memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1604                                      eld->eld_size) != 0) {
1605                         memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1606                                eld->eld_size);
1607                         eld_changed = true;
1608                 }
1609                 pin_eld->eld_size = eld->eld_size;
1610                 pin_eld->info = eld->info;
1611
1612                 /*
1613                  * Re-setup pin and infoframe. This is needed e.g. when
1614                  * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1615                  * - transcoder can change during stream playback on Haswell
1616                  *   and this can make HW reset converter selection on a pin.
1617                  */
1618                 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1619                         if (is_haswell_plus(codec) ||
1620                                 is_valleyview_plus(codec)) {
1621                                 intel_verify_pin_cvt_connect(codec, per_pin);
1622                                 intel_not_share_assigned_cvt(codec, pin_nid,
1623                                                         per_pin->mux_idx);
1624                         }
1625
1626                         hdmi_setup_audio_infoframe(codec, per_pin,
1627                                                    per_pin->non_pcm);
1628                 }
1629         }
1630
1631         if (eld_changed)
1632                 snd_ctl_notify(codec->card,
1633                                SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1634                                &per_pin->eld_ctl->id);
1635  unlock:
1636         ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1637
1638         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1639         if (jack) {
1640                 jack->block_report = !ret;
1641                 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1642                         AC_PINSENSE_PRESENCE : 0;
1643         }
1644         mutex_unlock(&per_pin->lock);
1645         snd_hda_power_down_pm(codec);
1646         return ret;
1647 }
1648
1649 static void hdmi_repoll_eld(struct work_struct *work)
1650 {
1651         struct hdmi_spec_per_pin *per_pin =
1652         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1653
1654         if (per_pin->repoll_count++ > 6)
1655                 per_pin->repoll_count = 0;
1656
1657         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1658                 snd_hda_jack_report_sync(per_pin->codec);
1659 }
1660
1661 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1662                                              hda_nid_t nid);
1663
1664 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1665 {
1666         struct hdmi_spec *spec = codec->spec;
1667         unsigned int caps, config;
1668         int pin_idx;
1669         struct hdmi_spec_per_pin *per_pin;
1670         int err;
1671
1672         caps = snd_hda_query_pin_caps(codec, pin_nid);
1673         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1674                 return 0;
1675
1676         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1677         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1678                 return 0;
1679
1680         if (is_haswell_plus(codec))
1681                 intel_haswell_fixup_connect_list(codec, pin_nid);
1682
1683         pin_idx = spec->num_pins;
1684         per_pin = snd_array_new(&spec->pins);
1685         if (!per_pin)
1686                 return -ENOMEM;
1687
1688         per_pin->pin_nid = pin_nid;
1689         per_pin->non_pcm = false;
1690
1691         err = hdmi_read_pin_conn(codec, pin_idx);
1692         if (err < 0)
1693                 return err;
1694
1695         spec->num_pins++;
1696
1697         return 0;
1698 }
1699
1700 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1701 {
1702         struct hdmi_spec *spec = codec->spec;
1703         struct hdmi_spec_per_cvt *per_cvt;
1704         unsigned int chans;
1705         int err;
1706
1707         chans = get_wcaps(codec, cvt_nid);
1708         chans = get_wcaps_channels(chans);
1709
1710         per_cvt = snd_array_new(&spec->cvts);
1711         if (!per_cvt)
1712                 return -ENOMEM;
1713
1714         per_cvt->cvt_nid = cvt_nid;
1715         per_cvt->channels_min = 2;
1716         if (chans <= 16) {
1717                 per_cvt->channels_max = chans;
1718                 if (chans > spec->channels_max)
1719                         spec->channels_max = chans;
1720         }
1721
1722         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1723                                           &per_cvt->rates,
1724                                           &per_cvt->formats,
1725                                           &per_cvt->maxbps);
1726         if (err < 0)
1727                 return err;
1728
1729         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1730                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1731         spec->num_cvts++;
1732
1733         return 0;
1734 }
1735
1736 static int hdmi_parse_codec(struct hda_codec *codec)
1737 {
1738         hda_nid_t nid;
1739         int i, nodes;
1740
1741         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1742         if (!nid || nodes < 0) {
1743                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1744                 return -EINVAL;
1745         }
1746
1747         for (i = 0; i < nodes; i++, nid++) {
1748                 unsigned int caps;
1749                 unsigned int type;
1750
1751                 caps = get_wcaps(codec, nid);
1752                 type = get_wcaps_type(caps);
1753
1754                 if (!(caps & AC_WCAP_DIGITAL))
1755                         continue;
1756
1757                 switch (type) {
1758                 case AC_WID_AUD_OUT:
1759                         hdmi_add_cvt(codec, nid);
1760                         break;
1761                 case AC_WID_PIN:
1762                         hdmi_add_pin(codec, nid);
1763                         break;
1764                 }
1765         }
1766
1767         return 0;
1768 }
1769
1770 /*
1771  */
1772 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1773 {
1774         struct hda_spdif_out *spdif;
1775         bool non_pcm;
1776
1777         mutex_lock(&codec->spdif_mutex);
1778         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1779         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1780         mutex_unlock(&codec->spdif_mutex);
1781         return non_pcm;
1782 }
1783
1784 /* There is a fixed mapping between audio pin node and display port
1785  * on current Intel platforms:
1786  * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1787  * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1788  * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1789  */
1790 static int intel_pin2port(hda_nid_t pin_nid)
1791 {
1792         return pin_nid - 4;
1793 }
1794
1795 /*
1796  * HDMI callbacks
1797  */
1798
1799 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1800                                            struct hda_codec *codec,
1801                                            unsigned int stream_tag,
1802                                            unsigned int format,
1803                                            struct snd_pcm_substream *substream)
1804 {
1805         hda_nid_t cvt_nid = hinfo->nid;
1806         struct hdmi_spec *spec = codec->spec;
1807         int pin_idx = hinfo_to_pin_index(codec, hinfo);
1808         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1809         hda_nid_t pin_nid = per_pin->pin_nid;
1810         struct snd_pcm_runtime *runtime = substream->runtime;
1811         struct i915_audio_component *acomp = codec->bus->core.audio_component;
1812         bool non_pcm;
1813         int pinctl;
1814
1815         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1816                 /* Verify pin:cvt selections to avoid silent audio after S3.
1817                  * After S3, the audio driver restores pin:cvt selections
1818                  * but this can happen before gfx is ready and such selection
1819                  * is overlooked by HW. Thus multiple pins can share a same
1820                  * default convertor and mute control will affect each other,
1821                  * which can cause a resumed audio playback become silent
1822                  * after S3.
1823                  */
1824                 intel_verify_pin_cvt_connect(codec, per_pin);
1825                 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1826         }
1827
1828         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1829         /* Todo: add DP1.2 MST audio support later */
1830         if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1831                 acomp->ops->sync_audio_rate(acomp->dev,
1832                                 intel_pin2port(pin_nid),
1833                                 runtime->rate);
1834
1835         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1836         mutex_lock(&per_pin->lock);
1837         per_pin->channels = substream->runtime->channels;
1838         per_pin->setup = true;
1839
1840         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1841         mutex_unlock(&per_pin->lock);
1842
1843         if (spec->dyn_pin_out) {
1844                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1845                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1846                 snd_hda_codec_write(codec, pin_nid, 0,
1847                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1848                                     pinctl | PIN_OUT);
1849         }
1850
1851         return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1852 }
1853
1854 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1855                                              struct hda_codec *codec,
1856                                              struct snd_pcm_substream *substream)
1857 {
1858         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1859         return 0;
1860 }
1861
1862 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1863                           struct hda_codec *codec,
1864                           struct snd_pcm_substream *substream)
1865 {
1866         struct hdmi_spec *spec = codec->spec;
1867         int cvt_idx, pin_idx;
1868         struct hdmi_spec_per_cvt *per_cvt;
1869         struct hdmi_spec_per_pin *per_pin;
1870         int pinctl;
1871
1872         if (hinfo->nid) {
1873                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1874                 if (snd_BUG_ON(cvt_idx < 0))
1875                         return -EINVAL;
1876                 per_cvt = get_cvt(spec, cvt_idx);
1877
1878                 snd_BUG_ON(!per_cvt->assigned);
1879                 per_cvt->assigned = 0;
1880                 hinfo->nid = 0;
1881
1882                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1883                 if (snd_BUG_ON(pin_idx < 0))
1884                         return -EINVAL;
1885                 per_pin = get_pin(spec, pin_idx);
1886
1887                 if (spec->dyn_pin_out) {
1888                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1889                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1890                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1891                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1892                                             pinctl & ~PIN_OUT);
1893                 }
1894
1895                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1896
1897                 mutex_lock(&per_pin->lock);
1898                 per_pin->chmap_set = false;
1899                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1900
1901                 per_pin->setup = false;
1902                 per_pin->channels = 0;
1903                 mutex_unlock(&per_pin->lock);
1904         }
1905
1906         return 0;
1907 }
1908
1909 static const struct hda_pcm_ops generic_ops = {
1910         .open = hdmi_pcm_open,
1911         .close = hdmi_pcm_close,
1912         .prepare = generic_hdmi_playback_pcm_prepare,
1913         .cleanup = generic_hdmi_playback_pcm_cleanup,
1914 };
1915
1916 /*
1917  * ALSA API channel-map control callbacks
1918  */
1919 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1920                                struct snd_ctl_elem_info *uinfo)
1921 {
1922         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1923         struct hda_codec *codec = info->private_data;
1924         struct hdmi_spec *spec = codec->spec;
1925         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1926         uinfo->count = spec->channels_max;
1927         uinfo->value.integer.min = 0;
1928         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1929         return 0;
1930 }
1931
1932 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1933                                                   int channels)
1934 {
1935         /* If the speaker allocation matches the channel count, it is OK.*/
1936         if (cap->channels != channels)
1937                 return -1;
1938
1939         /* all channels are remappable freely */
1940         return SNDRV_CTL_TLVT_CHMAP_VAR;
1941 }
1942
1943 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1944                                         unsigned int *chmap, int channels)
1945 {
1946         int count = 0;
1947         int c;
1948
1949         for (c = 7; c >= 0; c--) {
1950                 int spk = cap->speakers[c];
1951                 if (!spk)
1952                         continue;
1953
1954                 chmap[count++] = spk_to_chmap(spk);
1955         }
1956
1957         WARN_ON(count != channels);
1958 }
1959
1960 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1961                               unsigned int size, unsigned int __user *tlv)
1962 {
1963         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1964         struct hda_codec *codec = info->private_data;
1965         struct hdmi_spec *spec = codec->spec;
1966         unsigned int __user *dst;
1967         int chs, count = 0;
1968
1969         if (size < 8)
1970                 return -ENOMEM;
1971         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1972                 return -EFAULT;
1973         size -= 8;
1974         dst = tlv + 2;
1975         for (chs = 2; chs <= spec->channels_max; chs++) {
1976                 int i;
1977                 struct cea_channel_speaker_allocation *cap;
1978                 cap = channel_allocations;
1979                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1980                         int chs_bytes = chs * 4;
1981                         int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1982                         unsigned int tlv_chmap[8];
1983
1984                         if (type < 0)
1985                                 continue;
1986                         if (size < 8)
1987                                 return -ENOMEM;
1988                         if (put_user(type, dst) ||
1989                             put_user(chs_bytes, dst + 1))
1990                                 return -EFAULT;
1991                         dst += 2;
1992                         size -= 8;
1993                         count += 8;
1994                         if (size < chs_bytes)
1995                                 return -ENOMEM;
1996                         size -= chs_bytes;
1997                         count += chs_bytes;
1998                         spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1999                         if (copy_to_user(dst, tlv_chmap, chs_bytes))
2000                                 return -EFAULT;
2001                         dst += chs;
2002                 }
2003         }
2004         if (put_user(count, tlv + 1))
2005                 return -EFAULT;
2006         return 0;
2007 }
2008
2009 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2010                               struct snd_ctl_elem_value *ucontrol)
2011 {
2012         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2013         struct hda_codec *codec = info->private_data;
2014         struct hdmi_spec *spec = codec->spec;
2015         int pin_idx = kcontrol->private_value;
2016         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2017         int i;
2018
2019         for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2020                 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2021         return 0;
2022 }
2023
2024 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2025                               struct snd_ctl_elem_value *ucontrol)
2026 {
2027         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2028         struct hda_codec *codec = info->private_data;
2029         struct hdmi_spec *spec = codec->spec;
2030         int pin_idx = kcontrol->private_value;
2031         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2032         unsigned int ctl_idx;
2033         struct snd_pcm_substream *substream;
2034         unsigned char chmap[8];
2035         int i, err, ca, prepared = 0;
2036
2037         ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2038         substream = snd_pcm_chmap_substream(info, ctl_idx);
2039         if (!substream || !substream->runtime)
2040                 return 0; /* just for avoiding error from alsactl restore */
2041         switch (substream->runtime->status->state) {
2042         case SNDRV_PCM_STATE_OPEN:
2043         case SNDRV_PCM_STATE_SETUP:
2044                 break;
2045         case SNDRV_PCM_STATE_PREPARED:
2046                 prepared = 1;
2047                 break;
2048         default:
2049                 return -EBUSY;
2050         }
2051         memset(chmap, 0, sizeof(chmap));
2052         for (i = 0; i < ARRAY_SIZE(chmap); i++)
2053                 chmap[i] = ucontrol->value.integer.value[i];
2054         if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2055                 return 0;
2056         ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2057         if (ca < 0)
2058                 return -EINVAL;
2059         if (spec->ops.chmap_validate) {
2060                 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2061                 if (err)
2062                         return err;
2063         }
2064         mutex_lock(&per_pin->lock);
2065         per_pin->chmap_set = true;
2066         memcpy(per_pin->chmap, chmap, sizeof(chmap));
2067         if (prepared)
2068                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2069         mutex_unlock(&per_pin->lock);
2070
2071         return 0;
2072 }
2073
2074 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2075 {
2076         struct hdmi_spec *spec = codec->spec;
2077         int pin_idx;
2078
2079         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2080                 struct hda_pcm *info;
2081                 struct hda_pcm_stream *pstr;
2082
2083                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2084                 if (!info)
2085                         return -ENOMEM;
2086                 spec->pcm_rec[pin_idx] = info;
2087                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2088                 info->own_chmap = true;
2089
2090                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2091                 pstr->substreams = 1;
2092                 pstr->ops = generic_ops;
2093                 /* other pstr fields are set in open */
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2100 {
2101         char hdmi_str[32] = "HDMI/DP";
2102         struct hdmi_spec *spec = codec->spec;
2103         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2104         int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2105         bool phantom_jack;
2106
2107         if (pcmdev > 0)
2108                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2109         phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2110         if (phantom_jack)
2111                 strncat(hdmi_str, " Phantom",
2112                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2113
2114         return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2115                                      phantom_jack);
2116 }
2117
2118 static int generic_hdmi_build_controls(struct hda_codec *codec)
2119 {
2120         struct hdmi_spec *spec = codec->spec;
2121         int err;
2122         int pin_idx;
2123
2124         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2125                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2126
2127                 err = generic_hdmi_build_jack(codec, pin_idx);
2128                 if (err < 0)
2129                         return err;
2130
2131                 err = snd_hda_create_dig_out_ctls(codec,
2132                                                   per_pin->pin_nid,
2133                                                   per_pin->mux_nids[0],
2134                                                   HDA_PCM_TYPE_HDMI);
2135                 if (err < 0)
2136                         return err;
2137                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2138
2139                 /* add control for ELD Bytes */
2140                 err = hdmi_create_eld_ctl(codec, pin_idx,
2141                                           get_pcm_rec(spec, pin_idx)->device);
2142
2143                 if (err < 0)
2144                         return err;
2145
2146                 hdmi_present_sense(per_pin, 0);
2147         }
2148
2149         /* add channel maps */
2150         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2151                 struct hda_pcm *pcm;
2152                 struct snd_pcm_chmap *chmap;
2153                 struct snd_kcontrol *kctl;
2154                 int i;
2155
2156                 pcm = spec->pcm_rec[pin_idx];
2157                 if (!pcm || !pcm->pcm)
2158                         break;
2159                 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2160                                              SNDRV_PCM_STREAM_PLAYBACK,
2161                                              NULL, 0, pin_idx, &chmap);
2162                 if (err < 0)
2163                         return err;
2164                 /* override handlers */
2165                 chmap->private_data = codec;
2166                 kctl = chmap->kctl;
2167                 for (i = 0; i < kctl->count; i++)
2168                         kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2169                 kctl->info = hdmi_chmap_ctl_info;
2170                 kctl->get = hdmi_chmap_ctl_get;
2171                 kctl->put = hdmi_chmap_ctl_put;
2172                 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2179 {
2180         struct hdmi_spec *spec = codec->spec;
2181         int pin_idx;
2182
2183         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2184                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2185
2186                 per_pin->codec = codec;
2187                 mutex_init(&per_pin->lock);
2188                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2189                 eld_proc_new(per_pin, pin_idx);
2190         }
2191         return 0;
2192 }
2193
2194 static int generic_hdmi_init(struct hda_codec *codec)
2195 {
2196         struct hdmi_spec *spec = codec->spec;
2197         int pin_idx;
2198
2199         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2200                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2201                 hda_nid_t pin_nid = per_pin->pin_nid;
2202
2203                 hdmi_init_pin(codec, pin_nid);
2204                 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2205                         codec->jackpoll_interval > 0 ? jack_callback : NULL);
2206         }
2207         return 0;
2208 }
2209
2210 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2211 {
2212         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2213         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2214 }
2215
2216 static void hdmi_array_free(struct hdmi_spec *spec)
2217 {
2218         snd_array_free(&spec->pins);
2219         snd_array_free(&spec->cvts);
2220 }
2221
2222 static void generic_hdmi_free(struct hda_codec *codec)
2223 {
2224         struct hdmi_spec *spec = codec->spec;
2225         int pin_idx;
2226
2227         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2228                 snd_hdac_i915_register_notifier(NULL);
2229
2230         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2231                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2232
2233                 cancel_delayed_work_sync(&per_pin->work);
2234                 eld_proc_free(per_pin);
2235         }
2236
2237         hdmi_array_free(spec);
2238         kfree(spec);
2239 }
2240
2241 #ifdef CONFIG_PM
2242 static int generic_hdmi_suspend(struct hda_codec *codec)
2243 {
2244         struct hdmi_spec *spec = codec->spec;
2245         int pin_idx;
2246
2247         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2248                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2249                 cancel_delayed_work_sync(&per_pin->work);
2250         }
2251         return 0;
2252 }
2253
2254 static int generic_hdmi_resume(struct hda_codec *codec)
2255 {
2256         struct hdmi_spec *spec = codec->spec;
2257         int pin_idx;
2258
2259         codec->patch_ops.init(codec);
2260         regcache_sync(codec->core.regmap);
2261
2262         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2263                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2264                 hdmi_present_sense(per_pin, 1);
2265         }
2266         return 0;
2267 }
2268 #endif
2269
2270 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2271         .init                   = generic_hdmi_init,
2272         .free                   = generic_hdmi_free,
2273         .build_pcms             = generic_hdmi_build_pcms,
2274         .build_controls         = generic_hdmi_build_controls,
2275         .unsol_event            = hdmi_unsol_event,
2276 #ifdef CONFIG_PM
2277         .suspend                = generic_hdmi_suspend,
2278         .resume                 = generic_hdmi_resume,
2279 #endif
2280 };
2281
2282 static const struct hdmi_ops generic_standard_hdmi_ops = {
2283         .pin_get_eld                            = snd_hdmi_get_eld,
2284         .pin_get_slot_channel                   = hdmi_pin_get_slot_channel,
2285         .pin_set_slot_channel                   = hdmi_pin_set_slot_channel,
2286         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2287         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2288         .setup_stream                           = hdmi_setup_stream,
2289         .chmap_cea_alloc_validate_get_type      = hdmi_chmap_cea_alloc_validate_get_type,
2290         .cea_alloc_to_tlv_chmap                 = hdmi_cea_alloc_to_tlv_chmap,
2291 };
2292
2293
2294 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2295                                              hda_nid_t nid)
2296 {
2297         struct hdmi_spec *spec = codec->spec;
2298         hda_nid_t conns[4];
2299         int nconns;
2300
2301         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2302         if (nconns == spec->num_cvts &&
2303             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2304                 return;
2305
2306         /* override pins connection list */
2307         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2308         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2309 }
2310
2311 #define INTEL_VENDOR_NID 0x08
2312 #define INTEL_GET_VENDOR_VERB 0xf81
2313 #define INTEL_SET_VENDOR_VERB 0x781
2314 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2315 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2316
2317 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2318                                           bool update_tree)
2319 {
2320         unsigned int vendor_param;
2321
2322         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2323                                 INTEL_GET_VENDOR_VERB, 0);
2324         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2325                 return;
2326
2327         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2328         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2329                                 INTEL_SET_VENDOR_VERB, vendor_param);
2330         if (vendor_param == -1)
2331                 return;
2332
2333         if (update_tree)
2334                 snd_hda_codec_update_widgets(codec);
2335 }
2336
2337 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2338 {
2339         unsigned int vendor_param;
2340
2341         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2342                                 INTEL_GET_VENDOR_VERB, 0);
2343         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2344                 return;
2345
2346         /* enable DP1.2 mode */
2347         vendor_param |= INTEL_EN_DP12;
2348         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2349         snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2350                                 INTEL_SET_VENDOR_VERB, vendor_param);
2351 }
2352
2353 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2354  * Otherwise you may get severe h/w communication errors.
2355  */
2356 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2357                                 unsigned int power_state)
2358 {
2359         if (power_state == AC_PWRST_D0) {
2360                 intel_haswell_enable_all_pins(codec, false);
2361                 intel_haswell_fixup_enable_dp12(codec);
2362         }
2363
2364         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2365         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2366 }
2367
2368 static void intel_pin_eld_notify(void *audio_ptr, int port)
2369 {
2370         struct hda_codec *codec = audio_ptr;
2371         int pin_nid = port + 0x04;
2372
2373         /* we assume only from port-B to port-D */
2374         if (port < 1 || port > 3)
2375                 return;
2376
2377         /* skip notification during system suspend (but not in runtime PM);
2378          * the state will be updated at resume
2379          */
2380         if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2381                 return;
2382
2383         check_presence_and_report(codec, pin_nid);
2384 }
2385
2386 static int patch_generic_hdmi(struct hda_codec *codec)
2387 {
2388         struct hdmi_spec *spec;
2389
2390         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2391         if (spec == NULL)
2392                 return -ENOMEM;
2393
2394         spec->ops = generic_standard_hdmi_ops;
2395         codec->spec = spec;
2396         hdmi_array_init(spec, 4);
2397
2398         if (is_haswell_plus(codec)) {
2399                 intel_haswell_enable_all_pins(codec, true);
2400                 intel_haswell_fixup_enable_dp12(codec);
2401         }
2402
2403         /* For Valleyview/Cherryview, only the display codec is in the display
2404          * power well and can use link_power ops to request/release the power.
2405          * For Haswell/Broadwell, the controller is also in the power well and
2406          * can cover the codec power request, and so need not set this flag.
2407          * For previous platforms, there is no such power well feature.
2408          */
2409         if (is_valleyview_plus(codec) || is_skylake(codec) ||
2410                         is_broxton(codec))
2411                 codec->core.link_power_control = 1;
2412
2413         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2414                 codec->depop_delay = 0;
2415                 spec->i915_audio_ops.audio_ptr = codec;
2416                 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2417                 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2418         }
2419
2420         if (hdmi_parse_codec(codec) < 0) {
2421                 codec->spec = NULL;
2422                 kfree(spec);
2423                 return -EINVAL;
2424         }
2425         codec->patch_ops = generic_hdmi_patch_ops;
2426         if (is_haswell_plus(codec)) {
2427                 codec->patch_ops.set_power_state = haswell_set_power_state;
2428                 codec->dp_mst = true;
2429         }
2430
2431         /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2432         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2433                 codec->auto_runtime_pm = 1;
2434
2435         generic_hdmi_init_per_pins(codec);
2436
2437         init_channel_allocations();
2438
2439         return 0;
2440 }
2441
2442 /*
2443  * Shared non-generic implementations
2444  */
2445
2446 static int simple_playback_build_pcms(struct hda_codec *codec)
2447 {
2448         struct hdmi_spec *spec = codec->spec;
2449         struct hda_pcm *info;
2450         unsigned int chans;
2451         struct hda_pcm_stream *pstr;
2452         struct hdmi_spec_per_cvt *per_cvt;
2453
2454         per_cvt = get_cvt(spec, 0);
2455         chans = get_wcaps(codec, per_cvt->cvt_nid);
2456         chans = get_wcaps_channels(chans);
2457
2458         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2459         if (!info)
2460                 return -ENOMEM;
2461         spec->pcm_rec[0] = info;
2462         info->pcm_type = HDA_PCM_TYPE_HDMI;
2463         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2464         *pstr = spec->pcm_playback;
2465         pstr->nid = per_cvt->cvt_nid;
2466         if (pstr->channels_max <= 2 && chans && chans <= 16)
2467                 pstr->channels_max = chans;
2468
2469         return 0;
2470 }
2471
2472 /* unsolicited event for jack sensing */
2473 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2474                                     unsigned int res)
2475 {
2476         snd_hda_jack_set_dirty_all(codec);
2477         snd_hda_jack_report_sync(codec);
2478 }
2479
2480 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2481  * as long as spec->pins[] is set correctly
2482  */
2483 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2484
2485 static int simple_playback_build_controls(struct hda_codec *codec)
2486 {
2487         struct hdmi_spec *spec = codec->spec;
2488         struct hdmi_spec_per_cvt *per_cvt;
2489         int err;
2490
2491         per_cvt = get_cvt(spec, 0);
2492         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2493                                           per_cvt->cvt_nid,
2494                                           HDA_PCM_TYPE_HDMI);
2495         if (err < 0)
2496                 return err;
2497         return simple_hdmi_build_jack(codec, 0);
2498 }
2499
2500 static int simple_playback_init(struct hda_codec *codec)
2501 {
2502         struct hdmi_spec *spec = codec->spec;
2503         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2504         hda_nid_t pin = per_pin->pin_nid;
2505
2506         snd_hda_codec_write(codec, pin, 0,
2507                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2508         /* some codecs require to unmute the pin */
2509         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2510                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2511                                     AMP_OUT_UNMUTE);
2512         snd_hda_jack_detect_enable(codec, pin);
2513         return 0;
2514 }
2515
2516 static void simple_playback_free(struct hda_codec *codec)
2517 {
2518         struct hdmi_spec *spec = codec->spec;
2519
2520         hdmi_array_free(spec);
2521         kfree(spec);
2522 }
2523
2524 /*
2525  * Nvidia specific implementations
2526  */
2527
2528 #define Nv_VERB_SET_Channel_Allocation          0xF79
2529 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2530 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2531 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2532
2533 #define nvhdmi_master_con_nid_7x        0x04
2534 #define nvhdmi_master_pin_nid_7x        0x05
2535
2536 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2537         /*front, rear, clfe, rear_surr */
2538         0x6, 0x8, 0xa, 0xc,
2539 };
2540
2541 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2542         /* set audio protect on */
2543         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2544         /* enable digital output on pin widget */
2545         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2546         {} /* terminator */
2547 };
2548
2549 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2550         /* set audio protect on */
2551         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2552         /* enable digital output on pin widget */
2553         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2554         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2555         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2556         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2557         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2558         {} /* terminator */
2559 };
2560
2561 #ifdef LIMITED_RATE_FMT_SUPPORT
2562 /* support only the safe format and rate */
2563 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2564 #define SUPPORTED_MAXBPS        16
2565 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2566 #else
2567 /* support all rates and formats */
2568 #define SUPPORTED_RATES \
2569         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2570         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2571          SNDRV_PCM_RATE_192000)
2572 #define SUPPORTED_MAXBPS        24
2573 #define SUPPORTED_FORMATS \
2574         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2575 #endif
2576
2577 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2578 {
2579         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2580         return 0;
2581 }
2582
2583 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2584 {
2585         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2586         return 0;
2587 }
2588
2589 static unsigned int channels_2_6_8[] = {
2590         2, 6, 8
2591 };
2592
2593 static unsigned int channels_2_8[] = {
2594         2, 8
2595 };
2596
2597 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2598         .count = ARRAY_SIZE(channels_2_6_8),
2599         .list = channels_2_6_8,
2600         .mask = 0,
2601 };
2602
2603 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2604         .count = ARRAY_SIZE(channels_2_8),
2605         .list = channels_2_8,
2606         .mask = 0,
2607 };
2608
2609 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2610                                     struct hda_codec *codec,
2611                                     struct snd_pcm_substream *substream)
2612 {
2613         struct hdmi_spec *spec = codec->spec;
2614         struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2615
2616         switch (codec->preset->vendor_id) {
2617         case 0x10de0002:
2618         case 0x10de0003:
2619         case 0x10de0005:
2620         case 0x10de0006:
2621                 hw_constraints_channels = &hw_constraints_2_8_channels;
2622                 break;
2623         case 0x10de0007:
2624                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2625                 break;
2626         default:
2627                 break;
2628         }
2629
2630         if (hw_constraints_channels != NULL) {
2631                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2632                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2633                                 hw_constraints_channels);
2634         } else {
2635                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2636                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2637         }
2638
2639         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2640 }
2641
2642 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2643                                      struct hda_codec *codec,
2644                                      struct snd_pcm_substream *substream)
2645 {
2646         struct hdmi_spec *spec = codec->spec;
2647         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2648 }
2649
2650 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2651                                        struct hda_codec *codec,
2652                                        unsigned int stream_tag,
2653                                        unsigned int format,
2654                                        struct snd_pcm_substream *substream)
2655 {
2656         struct hdmi_spec *spec = codec->spec;
2657         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2658                                              stream_tag, format, substream);
2659 }
2660
2661 static const struct hda_pcm_stream simple_pcm_playback = {
2662         .substreams = 1,
2663         .channels_min = 2,
2664         .channels_max = 2,
2665         .ops = {
2666                 .open = simple_playback_pcm_open,
2667                 .close = simple_playback_pcm_close,
2668                 .prepare = simple_playback_pcm_prepare
2669         },
2670 };
2671
2672 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2673         .build_controls = simple_playback_build_controls,
2674         .build_pcms = simple_playback_build_pcms,
2675         .init = simple_playback_init,
2676         .free = simple_playback_free,
2677         .unsol_event = simple_hdmi_unsol_event,
2678 };
2679
2680 static int patch_simple_hdmi(struct hda_codec *codec,
2681                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2682 {
2683         struct hdmi_spec *spec;
2684         struct hdmi_spec_per_cvt *per_cvt;
2685         struct hdmi_spec_per_pin *per_pin;
2686
2687         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2688         if (!spec)
2689                 return -ENOMEM;
2690
2691         codec->spec = spec;
2692         hdmi_array_init(spec, 1);
2693
2694         spec->multiout.num_dacs = 0;  /* no analog */
2695         spec->multiout.max_channels = 2;
2696         spec->multiout.dig_out_nid = cvt_nid;
2697         spec->num_cvts = 1;
2698         spec->num_pins = 1;
2699         per_pin = snd_array_new(&spec->pins);
2700         per_cvt = snd_array_new(&spec->cvts);
2701         if (!per_pin || !per_cvt) {
2702                 simple_playback_free(codec);
2703                 return -ENOMEM;
2704         }
2705         per_cvt->cvt_nid = cvt_nid;
2706         per_pin->pin_nid = pin_nid;
2707         spec->pcm_playback = simple_pcm_playback;
2708
2709         codec->patch_ops = simple_hdmi_patch_ops;
2710
2711         return 0;
2712 }
2713
2714 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2715                                                     int channels)
2716 {
2717         unsigned int chanmask;
2718         int chan = channels ? (channels - 1) : 1;
2719
2720         switch (channels) {
2721         default:
2722         case 0:
2723         case 2:
2724                 chanmask = 0x00;
2725                 break;
2726         case 4:
2727                 chanmask = 0x08;
2728                 break;
2729         case 6:
2730                 chanmask = 0x0b;
2731                 break;
2732         case 8:
2733                 chanmask = 0x13;
2734                 break;
2735         }
2736
2737         /* Set the audio infoframe channel allocation and checksum fields.  The
2738          * channel count is computed implicitly by the hardware. */
2739         snd_hda_codec_write(codec, 0x1, 0,
2740                         Nv_VERB_SET_Channel_Allocation, chanmask);
2741
2742         snd_hda_codec_write(codec, 0x1, 0,
2743                         Nv_VERB_SET_Info_Frame_Checksum,
2744                         (0x71 - chan - chanmask));
2745 }
2746
2747 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2748                                    struct hda_codec *codec,
2749                                    struct snd_pcm_substream *substream)
2750 {
2751         struct hdmi_spec *spec = codec->spec;
2752         int i;
2753
2754         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2755                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2756         for (i = 0; i < 4; i++) {
2757                 /* set the stream id */
2758                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2759                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2760                 /* set the stream format */
2761                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2762                                 AC_VERB_SET_STREAM_FORMAT, 0);
2763         }
2764
2765         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2766          * streams are disabled. */
2767         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2768
2769         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2770 }
2771
2772 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2773                                      struct hda_codec *codec,
2774                                      unsigned int stream_tag,
2775                                      unsigned int format,
2776                                      struct snd_pcm_substream *substream)
2777 {
2778         int chs;
2779         unsigned int dataDCC2, channel_id;
2780         int i;
2781         struct hdmi_spec *spec = codec->spec;
2782         struct hda_spdif_out *spdif;
2783         struct hdmi_spec_per_cvt *per_cvt;
2784
2785         mutex_lock(&codec->spdif_mutex);
2786         per_cvt = get_cvt(spec, 0);
2787         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2788
2789         chs = substream->runtime->channels;
2790
2791         dataDCC2 = 0x2;
2792
2793         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2794         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2795                 snd_hda_codec_write(codec,
2796                                 nvhdmi_master_con_nid_7x,
2797                                 0,
2798                                 AC_VERB_SET_DIGI_CONVERT_1,
2799                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2800
2801         /* set the stream id */
2802         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2803                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2804
2805         /* set the stream format */
2806         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2807                         AC_VERB_SET_STREAM_FORMAT, format);
2808
2809         /* turn on again (if needed) */
2810         /* enable and set the channel status audio/data flag */
2811         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2812                 snd_hda_codec_write(codec,
2813                                 nvhdmi_master_con_nid_7x,
2814                                 0,
2815                                 AC_VERB_SET_DIGI_CONVERT_1,
2816                                 spdif->ctls & 0xff);
2817                 snd_hda_codec_write(codec,
2818                                 nvhdmi_master_con_nid_7x,
2819                                 0,
2820                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2821         }
2822
2823         for (i = 0; i < 4; i++) {
2824                 if (chs == 2)
2825                         channel_id = 0;
2826                 else
2827                         channel_id = i * 2;
2828
2829                 /* turn off SPDIF once;
2830                  *otherwise the IEC958 bits won't be updated
2831                  */
2832                 if (codec->spdif_status_reset &&
2833                 (spdif->ctls & AC_DIG1_ENABLE))
2834                         snd_hda_codec_write(codec,
2835                                 nvhdmi_con_nids_7x[i],
2836                                 0,
2837                                 AC_VERB_SET_DIGI_CONVERT_1,
2838                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2839                 /* set the stream id */
2840                 snd_hda_codec_write(codec,
2841                                 nvhdmi_con_nids_7x[i],
2842                                 0,
2843                                 AC_VERB_SET_CHANNEL_STREAMID,
2844                                 (stream_tag << 4) | channel_id);
2845                 /* set the stream format */
2846                 snd_hda_codec_write(codec,
2847                                 nvhdmi_con_nids_7x[i],
2848                                 0,
2849                                 AC_VERB_SET_STREAM_FORMAT,
2850                                 format);
2851                 /* turn on again (if needed) */
2852                 /* enable and set the channel status audio/data flag */
2853                 if (codec->spdif_status_reset &&
2854                 (spdif->ctls & AC_DIG1_ENABLE)) {
2855                         snd_hda_codec_write(codec,
2856                                         nvhdmi_con_nids_7x[i],
2857                                         0,
2858                                         AC_VERB_SET_DIGI_CONVERT_1,
2859                                         spdif->ctls & 0xff);
2860                         snd_hda_codec_write(codec,
2861                                         nvhdmi_con_nids_7x[i],
2862                                         0,
2863                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2864                 }
2865         }
2866
2867         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2868
2869         mutex_unlock(&codec->spdif_mutex);
2870         return 0;
2871 }
2872
2873 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2874         .substreams = 1,
2875         .channels_min = 2,
2876         .channels_max = 8,
2877         .nid = nvhdmi_master_con_nid_7x,
2878         .rates = SUPPORTED_RATES,
2879         .maxbps = SUPPORTED_MAXBPS,
2880         .formats = SUPPORTED_FORMATS,
2881         .ops = {
2882                 .open = simple_playback_pcm_open,
2883                 .close = nvhdmi_8ch_7x_pcm_close,
2884                 .prepare = nvhdmi_8ch_7x_pcm_prepare
2885         },
2886 };
2887
2888 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2889 {
2890         struct hdmi_spec *spec;
2891         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2892                                     nvhdmi_master_pin_nid_7x);
2893         if (err < 0)
2894                 return err;
2895
2896         codec->patch_ops.init = nvhdmi_7x_init_2ch;
2897         /* override the PCM rates, etc, as the codec doesn't give full list */
2898         spec = codec->spec;
2899         spec->pcm_playback.rates = SUPPORTED_RATES;
2900         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2901         spec->pcm_playback.formats = SUPPORTED_FORMATS;
2902         return 0;
2903 }
2904
2905 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2906 {
2907         struct hdmi_spec *spec = codec->spec;
2908         int err = simple_playback_build_pcms(codec);
2909         if (!err) {
2910                 struct hda_pcm *info = get_pcm_rec(spec, 0);
2911                 info->own_chmap = true;
2912         }
2913         return err;
2914 }
2915
2916 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2917 {
2918         struct hdmi_spec *spec = codec->spec;
2919         struct hda_pcm *info;
2920         struct snd_pcm_chmap *chmap;
2921         int err;
2922
2923         err = simple_playback_build_controls(codec);
2924         if (err < 0)
2925                 return err;
2926
2927         /* add channel maps */
2928         info = get_pcm_rec(spec, 0);
2929         err = snd_pcm_add_chmap_ctls(info->pcm,
2930                                      SNDRV_PCM_STREAM_PLAYBACK,
2931                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
2932         if (err < 0)
2933                 return err;
2934         switch (codec->preset->vendor_id) {
2935         case 0x10de0002:
2936         case 0x10de0003:
2937         case 0x10de0005:
2938         case 0x10de0006:
2939                 chmap->channel_mask = (1U << 2) | (1U << 8);
2940                 break;
2941         case 0x10de0007:
2942                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2943         }
2944         return 0;
2945 }
2946
2947 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2948 {
2949         struct hdmi_spec *spec;
2950         int err = patch_nvhdmi_2ch(codec);
2951         if (err < 0)
2952                 return err;
2953         spec = codec->spec;
2954         spec->multiout.max_channels = 8;
2955         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2956         codec->patch_ops.init = nvhdmi_7x_init_8ch;
2957         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2958         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2959
2960         /* Initialize the audio infoframe channel mask and checksum to something
2961          * valid */
2962         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2963
2964         return 0;
2965 }
2966
2967 /*
2968  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2969  * - 0x10de0015
2970  * - 0x10de0040
2971  */
2972 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2973                                                     int channels)
2974 {
2975         if (cap->ca_index == 0x00 && channels == 2)
2976                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2977
2978         return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2979 }
2980
2981 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2982 {
2983         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2984                 return -EINVAL;
2985
2986         return 0;
2987 }
2988
2989 static int patch_nvhdmi(struct hda_codec *codec)
2990 {
2991         struct hdmi_spec *spec;
2992         int err;
2993
2994         err = patch_generic_hdmi(codec);
2995         if (err)
2996                 return err;
2997
2998         spec = codec->spec;
2999         spec->dyn_pin_out = true;
3000
3001         spec->ops.chmap_cea_alloc_validate_get_type =
3002                 nvhdmi_chmap_cea_alloc_validate_get_type;
3003         spec->ops.chmap_validate = nvhdmi_chmap_validate;
3004
3005         return 0;
3006 }
3007
3008 /*
3009  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3010  * accessed using vendor-defined verbs. These registers can be used for
3011  * interoperability between the HDA and HDMI drivers.
3012  */
3013
3014 /* Audio Function Group node */
3015 #define NVIDIA_AFG_NID 0x01
3016
3017 /*
3018  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3019  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3020  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3021  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3022  * additional bit (at position 30) to signal the validity of the format.
3023  *
3024  * | 31      | 30    | 29  16 | 15   0 |
3025  * +---------+-------+--------+--------+
3026  * | TRIGGER | VALID | UNUSED | FORMAT |
3027  * +-----------------------------------|
3028  *
3029  * Note that for the trigger bit to take effect it needs to change value
3030  * (i.e. it needs to be toggled).
3031  */
3032 #define NVIDIA_GET_SCRATCH0             0xfa6
3033 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3034 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3035 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3036 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3037 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3038 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3039
3040 #define NVIDIA_GET_SCRATCH1             0xfab
3041 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3042 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3043 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3044 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3045
3046 /*
3047  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3048  * the format is invalidated so that the HDMI codec can be disabled.
3049  */
3050 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3051 {
3052         unsigned int value;
3053
3054         /* bits [31:30] contain the trigger and valid bits */
3055         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3056                                    NVIDIA_GET_SCRATCH0, 0);
3057         value = (value >> 24) & 0xff;
3058
3059         /* bits [15:0] are used to store the HDA format */
3060         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3061                             NVIDIA_SET_SCRATCH0_BYTE0,
3062                             (format >> 0) & 0xff);
3063         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3064                             NVIDIA_SET_SCRATCH0_BYTE1,
3065                             (format >> 8) & 0xff);
3066
3067         /* bits [16:24] are unused */
3068         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3069                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3070
3071         /*
3072          * Bit 30 signals that the data is valid and hence that HDMI audio can
3073          * be enabled.
3074          */
3075         if (format == 0)
3076                 value &= ~NVIDIA_SCRATCH_VALID;
3077         else
3078                 value |= NVIDIA_SCRATCH_VALID;
3079
3080         /*
3081          * Whenever the trigger bit is toggled, an interrupt is raised in the
3082          * HDMI codec. The HDMI driver will use that as trigger to update its
3083          * configuration.
3084          */
3085         value ^= NVIDIA_SCRATCH_TRIGGER;
3086
3087         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3088                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3089 }
3090
3091 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3092                                   struct hda_codec *codec,
3093                                   unsigned int stream_tag,
3094                                   unsigned int format,
3095                                   struct snd_pcm_substream *substream)
3096 {
3097         int err;
3098
3099         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3100                                                 format, substream);
3101         if (err < 0)
3102                 return err;
3103
3104         /* notify the HDMI codec of the format change */
3105         tegra_hdmi_set_format(codec, format);
3106
3107         return 0;
3108 }
3109
3110 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3111                                   struct hda_codec *codec,
3112                                   struct snd_pcm_substream *substream)
3113 {
3114         /* invalidate the format in the HDMI codec */
3115         tegra_hdmi_set_format(codec, 0);
3116
3117         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3118 }
3119
3120 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3121 {
3122         struct hdmi_spec *spec = codec->spec;
3123         unsigned int i;
3124
3125         for (i = 0; i < spec->num_pins; i++) {
3126                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3127
3128                 if (pcm->pcm_type == type)
3129                         return pcm;
3130         }
3131
3132         return NULL;
3133 }
3134
3135 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3136 {
3137         struct hda_pcm_stream *stream;
3138         struct hda_pcm *pcm;
3139         int err;
3140
3141         err = generic_hdmi_build_pcms(codec);
3142         if (err < 0)
3143                 return err;
3144
3145         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3146         if (!pcm)
3147                 return -ENODEV;
3148
3149         /*
3150          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3151          * codec about format changes.
3152          */
3153         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3154         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3155         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3156
3157         return 0;
3158 }
3159
3160 static int patch_tegra_hdmi(struct hda_codec *codec)
3161 {
3162         int err;
3163
3164         err = patch_generic_hdmi(codec);
3165         if (err)
3166                 return err;
3167
3168         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3169
3170         return 0;
3171 }
3172
3173 /*
3174  * ATI/AMD-specific implementations
3175  */
3176
3177 #define is_amdhdmi_rev3_or_later(codec) \
3178         ((codec)->core.vendor_id == 0x1002aa01 && \
3179          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3180 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3181
3182 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3183 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3184 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3185 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3186 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3187 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3188 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3189 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3190 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3191 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3192 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3193 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3194 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3195 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3196 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3197 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3198 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3199 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3200 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3201 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3202 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3203 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3204 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3205 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3206 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3207
3208 /* AMD specific HDA cvt verbs */
3209 #define ATI_VERB_SET_RAMP_RATE          0x770
3210 #define ATI_VERB_GET_RAMP_RATE          0xf70
3211
3212 #define ATI_OUT_ENABLE 0x1
3213
3214 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3215 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3216
3217 #define ATI_HBR_CAPABLE 0x01
3218 #define ATI_HBR_ENABLE 0x10
3219
3220 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3221                            unsigned char *buf, int *eld_size)
3222 {
3223         /* call hda_eld.c ATI/AMD-specific function */
3224         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3225                                     is_amdhdmi_rev3_or_later(codec));
3226 }
3227
3228 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3229                                         int active_channels, int conn_type)
3230 {
3231         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3232 }
3233
3234 static int atihdmi_paired_swap_fc_lfe(int pos)
3235 {
3236         /*
3237          * ATI/AMD have automatic FC/LFE swap built-in
3238          * when in pairwise mapping mode.
3239          */
3240
3241         switch (pos) {
3242                 /* see channel_allocations[].speakers[] */
3243                 case 2: return 3;
3244                 case 3: return 2;
3245                 default: break;
3246         }
3247
3248         return pos;
3249 }
3250
3251 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3252 {
3253         struct cea_channel_speaker_allocation *cap;
3254         int i, j;
3255
3256         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3257
3258         cap = &channel_allocations[get_channel_allocation_order(ca)];
3259         for (i = 0; i < chs; ++i) {
3260                 int mask = to_spk_mask(map[i]);
3261                 bool ok = false;
3262                 bool companion_ok = false;
3263
3264                 if (!mask)
3265                         continue;
3266
3267                 for (j = 0 + i % 2; j < 8; j += 2) {
3268                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3269                         if (cap->speakers[chan_idx] == mask) {
3270                                 /* channel is in a supported position */
3271                                 ok = true;
3272
3273                                 if (i % 2 == 0 && i + 1 < chs) {
3274                                         /* even channel, check the odd companion */
3275                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3276                                         int comp_mask_req = to_spk_mask(map[i+1]);
3277                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3278
3279                                         if (comp_mask_req == comp_mask_act)
3280                                                 companion_ok = true;
3281                                         else
3282                                                 return -EINVAL;
3283                                 }
3284                                 break;
3285                         }
3286                 }
3287
3288                 if (!ok)
3289                         return -EINVAL;
3290
3291                 if (companion_ok)
3292                         i++; /* companion channel already checked */
3293         }
3294
3295         return 0;
3296 }
3297
3298 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3299                                         int hdmi_slot, int stream_channel)
3300 {
3301         int verb;
3302         int ati_channel_setup = 0;
3303
3304         if (hdmi_slot > 7)
3305                 return -EINVAL;
3306
3307         if (!has_amd_full_remap_support(codec)) {
3308                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3309
3310                 /* In case this is an odd slot but without stream channel, do not
3311                  * disable the slot since the corresponding even slot could have a
3312                  * channel. In case neither have a channel, the slot pair will be
3313                  * disabled when this function is called for the even slot. */
3314                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3315                         return 0;
3316
3317                 hdmi_slot -= hdmi_slot % 2;
3318
3319                 if (stream_channel != 0xf)
3320                         stream_channel -= stream_channel % 2;
3321         }
3322
3323         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3324
3325         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3326
3327         if (stream_channel != 0xf)
3328                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3329
3330         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3331 }
3332
3333 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3334                                         int asp_slot)
3335 {
3336         bool was_odd = false;
3337         int ati_asp_slot = asp_slot;
3338         int verb;
3339         int ati_channel_setup;
3340
3341         if (asp_slot > 7)
3342                 return -EINVAL;
3343
3344         if (!has_amd_full_remap_support(codec)) {
3345                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3346                 if (ati_asp_slot % 2 != 0) {
3347                         ati_asp_slot -= 1;
3348                         was_odd = true;
3349                 }
3350         }
3351
3352         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3353
3354         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3355
3356         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3357                 return 0xf;
3358
3359         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3360 }
3361
3362 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3363                                                             int channels)
3364 {
3365         int c;
3366
3367         /*
3368          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3369          * we need to take that into account (a single channel may take 2
3370          * channel slots if we need to carry a silent channel next to it).
3371          * On Rev3+ AMD codecs this function is not used.
3372          */
3373         int chanpairs = 0;
3374
3375         /* We only produce even-numbered channel count TLVs */
3376         if ((channels % 2) != 0)
3377                 return -1;
3378
3379         for (c = 0; c < 7; c += 2) {
3380                 if (cap->speakers[c] || cap->speakers[c+1])
3381                         chanpairs++;
3382         }
3383
3384         if (chanpairs * 2 != channels)
3385                 return -1;
3386
3387         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3388 }
3389
3390 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3391                                                   unsigned int *chmap, int channels)
3392 {
3393         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3394         int count = 0;
3395         int c;
3396
3397         for (c = 7; c >= 0; c--) {
3398                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3399                 int spk = cap->speakers[chan];
3400                 if (!spk) {
3401                         /* add N/A channel if the companion channel is occupied */
3402                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3403                                 chmap[count++] = SNDRV_CHMAP_NA;
3404
3405                         continue;
3406                 }
3407
3408                 chmap[count++] = spk_to_chmap(spk);
3409         }
3410
3411         WARN_ON(count != channels);
3412 }
3413
3414 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3415                                  bool hbr)
3416 {
3417         int hbr_ctl, hbr_ctl_new;
3418
3419         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3420         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3421                 if (hbr)
3422                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3423                 else
3424                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3425
3426                 codec_dbg(codec,
3427                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3428                                 pin_nid,
3429                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3430                                 hbr_ctl_new);
3431
3432                 if (hbr_ctl != hbr_ctl_new)
3433                         snd_hda_codec_write(codec, pin_nid, 0,
3434                                                 ATI_VERB_SET_HBR_CONTROL,
3435                                                 hbr_ctl_new);
3436
3437         } else if (hbr)
3438                 return -EINVAL;
3439
3440         return 0;
3441 }
3442
3443 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3444                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3445 {
3446
3447         if (is_amdhdmi_rev3_or_later(codec)) {
3448                 int ramp_rate = 180; /* default as per AMD spec */
3449                 /* disable ramp-up/down for non-pcm as per AMD spec */
3450                 if (format & AC_FMT_TYPE_NON_PCM)
3451                         ramp_rate = 0;
3452
3453                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3454         }
3455
3456         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3457 }
3458
3459
3460 static int atihdmi_init(struct hda_codec *codec)
3461 {
3462         struct hdmi_spec *spec = codec->spec;
3463         int pin_idx, err;
3464
3465         err = generic_hdmi_init(codec);
3466
3467         if (err)
3468                 return err;
3469
3470         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3471                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3472
3473                 /* make sure downmix information in infoframe is zero */
3474                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3475
3476                 /* enable channel-wise remap mode if supported */
3477                 if (has_amd_full_remap_support(codec))
3478                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3479                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3480                                             ATI_MULTICHANNEL_MODE_SINGLE);
3481         }
3482
3483         return 0;
3484 }
3485
3486 static int patch_atihdmi(struct hda_codec *codec)
3487 {
3488         struct hdmi_spec *spec;
3489         struct hdmi_spec_per_cvt *per_cvt;
3490         int err, cvt_idx;
3491
3492         err = patch_generic_hdmi(codec);
3493
3494         if (err)
3495                 return err;
3496
3497         codec->patch_ops.init = atihdmi_init;
3498
3499         spec = codec->spec;
3500
3501         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3502         spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3503         spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3504         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3505         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3506         spec->ops.setup_stream = atihdmi_setup_stream;
3507
3508         if (!has_amd_full_remap_support(codec)) {
3509                 /* override to ATI/AMD-specific versions with pairwise mapping */
3510                 spec->ops.chmap_cea_alloc_validate_get_type =
3511                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3512                 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3513                 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3514         }
3515
3516         /* ATI/AMD converters do not advertise all of their capabilities */
3517         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3518                 per_cvt = get_cvt(spec, cvt_idx);
3519                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3520                 per_cvt->rates |= SUPPORTED_RATES;
3521                 per_cvt->formats |= SUPPORTED_FORMATS;
3522                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3523         }
3524
3525         spec->channels_max = max(spec->channels_max, 8u);
3526
3527         return 0;
3528 }
3529
3530 /* VIA HDMI Implementation */
3531 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3532 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3533
3534 static int patch_via_hdmi(struct hda_codec *codec)
3535 {
3536         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3537 }
3538
3539 /*
3540  * patch entries
3541  */
3542 static const struct hda_device_id snd_hda_id_hdmi[] = {
3543 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3544 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3545 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3546 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3547 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3548 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3549 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3550 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3551 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3552 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3553 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3554 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3555 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3556 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3557 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3558 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3559 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3560 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3561 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3562 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3563 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3564 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3565 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3566 /* 17 is known to be absent */
3567 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3568 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3569 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3570 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3571 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3572 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3573 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3574 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3575 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3576 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3577 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3578 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3579 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3580 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3581 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3582 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3583 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3584 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3585 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3586 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3587 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3588 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3589 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3590 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3591 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3592 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3593 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_generic_hdmi),
3594 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3595 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3596 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3597 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_generic_hdmi),
3598 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3599 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3600 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_generic_hdmi),
3601 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_generic_hdmi),
3602 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_generic_hdmi),
3603 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_generic_hdmi),
3604 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_generic_hdmi),
3605 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3606 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3607 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_generic_hdmi),
3608 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3609 /* special ID for generic HDMI */
3610 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3611 {} /* terminator */
3612 };
3613 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3614
3615 MODULE_LICENSE("GPL");
3616 MODULE_DESCRIPTION("HDMI HD-audio codec");
3617 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3618 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3619 MODULE_ALIAS("snd-hda-codec-atihdmi");
3620
3621 static struct hda_codec_driver hdmi_driver = {
3622         .id = snd_hda_id_hdmi,
3623 };
3624
3625 module_hda_codec_driver(hdmi_driver);