sound/pci/hda/patch_cs8409.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
   4  *
   5  * Copyright (C) 2021 Cirrus Logic, Inc. and
   6  *                    Cirrus Logic International Semiconductor Ltd.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <sound/core.h>
  13 #include <linux/mutex.h>
  14 #include <linux/iopoll.h>
  15
  16 #include "patch_cs8409.h"
  17
  18 /******************************************************************************
  19  *                        CS8409 Specific Functions
  20  ******************************************************************************/
  21
  22 static int cs8409_parse_auto_config(struct hda_codec *codec)
  23 {
  24         struct cs8409_spec *spec = codec->spec;
  25         int err;
  26         int i;
  27
  28         err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
  29         if (err < 0)
  30                 return err;
  31
  32         err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
  33         if (err < 0)
  34                 return err;
  35
  36         /* keep the ADCs powered up when it's dynamically switchable */
  37         if (spec->gen.dyn_adc_switch) {
  38                 unsigned int done = 0;
  39
  40                 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
  41                         int idx = spec->gen.dyn_adc_idx[i];
  42
  43                         if (done & (1 << idx))
  44                                 continue;
  45                         snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
  46                         done |= 1 << idx;
  47                 }
  48         }
  49
  50         return 0;
  51 }
  52
  53 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
  54
  55 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
  56 {
  57         struct cs8409_spec *spec;
  58
  59         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  60         if (!spec)
  61                 return NULL;
  62         codec->spec = spec;
  63         spec->codec = codec;
  64         codec->power_save_node = 1;
  65         mutex_init(&spec->i2c_mux);
  66         INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
  67         snd_hda_gen_spec_init(&spec->gen);
  68
  69         return spec;
  70 }
  71
  72 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
  73 {
  74         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  75         return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
  76 }
  77
  78 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
  79                                           unsigned int coef)
  80 {
  81         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  82         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
  83 }
  84
  85 /*
  86  * cs8409_enable_i2c_clock - Disable I2C clocks
  87  * @codec: the codec instance
  88  * Disable I2C clocks.
  89  * This must be called when the i2c mutex is unlocked.
  90  */
  91 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
  92 {
  93         struct cs8409_spec *spec = codec->spec;
  94
  95         mutex_lock(&spec->i2c_mux);
  96         if (spec->i2c_clck_enabled) {
  97                 cs8409_vendor_coef_set(spec->codec, 0x0,
  98                                cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
  99                 spec->i2c_clck_enabled = 0;
 100         }
 101         mutex_unlock(&spec->i2c_mux);
 102 }
 103
 104 /*
 105  * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
 106  */
 107 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
 108 {
 109         struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
 110
 111         cs8409_disable_i2c_clock(spec->codec);
 112 }
 113
 114 /*
 115  * cs8409_enable_i2c_clock - Enable I2C clocks
 116  * @codec: the codec instance
 117  * Enable I2C clocks.
 118  * This must be called when the i2c mutex is locked.
 119  */
 120 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
 121 {
 122         struct cs8409_spec *spec = codec->spec;
 123
 124         /* Cancel the disable timer, but do not wait for any running disable functions to finish.
 125          * If the disable timer runs out before cancel, the delayed work thread will be blocked,
 126          * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
 127          * any i2c transaction, so the disable function will run to completion immediately
 128          * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
 129          */
 130         cancel_delayed_work(&spec->i2c_clk_work);
 131
 132         if (!spec->i2c_clck_enabled) {
 133                 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
 134                 spec->i2c_clck_enabled = 1;
 135         }
 136         queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
 137 }
 138
 139 /**
 140  * cs8409_i2c_wait_complete - Wait for I2C transaction
 141  * @codec: the codec instance
 142  *
 143  * Wait for I2C transaction to complete.
 144  * Return -ETIMEDOUT if transaction wait times out.
 145  */
 146 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
 147 {
 148         unsigned int retval;
 149
 150         return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
 151                 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
 152 }
 153
 154 /**
 155  * cs8409_set_i2c_dev_addr - Set i2c address for transaction
 156  * @codec: the codec instance
 157  * @addr: I2C Address
 158  */
 159 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
 160 {
 161         struct cs8409_spec *spec = codec->spec;
 162
 163         if (spec->dev_addr != addr) {
 164                 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
 165                 spec->dev_addr = addr;
 166         }
 167 }
 168
 169 /**
 170  * cs8409_i2c_set_page - CS8409 I2C set page register.
 171  * @scodec: the codec instance
 172  * @i2c_reg: Page register
 173  *
 174  * Returns negative on error.
 175  */
 176 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
 177 {
 178         struct hda_codec *codec = scodec->codec;
 179
 180         if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
 181                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
 182                 if (cs8409_i2c_wait_complete(codec) < 0)
 183                         return -EIO;
 184                 scodec->last_page = i2c_reg >> 8;
 185         }
 186
 187         return 0;
 188 }
 189
 190 /**
 191  * cs8409_i2c_read - CS8409 I2C Read.
 192  * @scodec: the codec instance
 193  * @addr: Register to read
 194  *
 195  * Returns negative on error, otherwise returns read value in bits 0-7.
 196  */
 197 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
 198 {
 199         struct hda_codec *codec = scodec->codec;
 200         struct cs8409_spec *spec = codec->spec;
 201         unsigned int i2c_reg_data;
 202         unsigned int read_data;
 203
 204         if (scodec->suspended)
 205                 return -EPERM;
 206
 207         mutex_lock(&spec->i2c_mux);
 208         cs8409_enable_i2c_clock(codec);
 209         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 210
 211         if (cs8409_i2c_set_page(scodec, addr))
 212                 goto error;
 213
 214         i2c_reg_data = (addr << 8) & 0x0ffff;
 215         cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 216         if (cs8409_i2c_wait_complete(codec) < 0)
 217                 goto error;
 218
 219         /* Register in bits 15-8 and the data in 7-0 */
 220         read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
 221
 222         mutex_unlock(&spec->i2c_mux);
 223
 224         return read_data & 0x0ff;
 225
 226 error:
 227         mutex_unlock(&spec->i2c_mux);
 228         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 229         return -EIO;
 230 }
 231
 232 /**
 233  * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
 234  * @scodec: the codec instance
 235  * @seq: Register Sequence to read
 236  * @count: Number of registeres to read
 237  *
 238  * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
 239  */
 240 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
 241 {
 242         struct hda_codec *codec = scodec->codec;
 243         struct cs8409_spec *spec = codec->spec;
 244         unsigned int i2c_reg_data;
 245         int i;
 246
 247         if (scodec->suspended)
 248                 return -EPERM;
 249
 250         mutex_lock(&spec->i2c_mux);
 251         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 252
 253         for (i = 0; i < count; i++) {
 254                 cs8409_enable_i2c_clock(codec);
 255                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 256                         goto error;
 257
 258                 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
 259                 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 260
 261                 if (cs8409_i2c_wait_complete(codec) < 0)
 262                         goto error;
 263
 264                 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
 265         }
 266
 267         mutex_unlock(&spec->i2c_mux);
 268
 269         return 0;
 270
 271 error:
 272         mutex_unlock(&spec->i2c_mux);
 273         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 274         return -EIO;
 275 }
 276
 277 /**
 278  * cs8409_i2c_write - CS8409 I2C Write.
 279  * @scodec: the codec instance
 280  * @addr: Register to write to
 281  * @value: Data to write
 282  *
 283  * Returns negative on error, otherwise returns 0.
 284  */
 285 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
 286 {
 287         struct hda_codec *codec = scodec->codec;
 288         struct cs8409_spec *spec = codec->spec;
 289         unsigned int i2c_reg_data;
 290
 291         if (scodec->suspended)
 292                 return -EPERM;
 293
 294         mutex_lock(&spec->i2c_mux);
 295
 296         cs8409_enable_i2c_clock(codec);
 297         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 298
 299         if (cs8409_i2c_set_page(scodec, addr))
 300                 goto error;
 301
 302         i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
 303         cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 304
 305         if (cs8409_i2c_wait_complete(codec) < 0)
 306                 goto error;
 307
 308         mutex_unlock(&spec->i2c_mux);
 309         return 0;
 310
 311 error:
 312         mutex_unlock(&spec->i2c_mux);
 313         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 314         return -EIO;
 315 }
 316
 317 /**
 318  * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
 319  * @scodec: the codec instance
 320  * @seq: Register Sequence to write
 321  * @count: Number of registeres to write
 322  *
 323  * Returns negative on error.
 324  */
 325 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
 326                                  int count)
 327 {
 328         struct hda_codec *codec = scodec->codec;
 329         struct cs8409_spec *spec = codec->spec;
 330         unsigned int i2c_reg_data;
 331         int i;
 332
 333         if (scodec->suspended)
 334                 return -EPERM;
 335
 336         mutex_lock(&spec->i2c_mux);
 337         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 338
 339         for (i = 0; i < count; i++) {
 340                 cs8409_enable_i2c_clock(codec);
 341                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 342                         goto error;
 343
 344                 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
 345                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 346
 347                 if (cs8409_i2c_wait_complete(codec) < 0)
 348                         goto error;
 349         }
 350
 351         mutex_unlock(&spec->i2c_mux);
 352
 353         return 0;
 354
 355 error:
 356         mutex_unlock(&spec->i2c_mux);
 357         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 358         return -EIO;
 359 }
 360
 361 static int cs8409_init(struct hda_codec *codec)
 362 {
 363         int ret = snd_hda_gen_init(codec);
 364
 365         if (!ret)
 366                 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
 367
 368         return ret;
 369 }
 370
 371 static int cs8409_build_controls(struct hda_codec *codec)
 372 {
 373         int err;
 374
 375         err = snd_hda_gen_build_controls(codec);
 376         if (err < 0)
 377                 return err;
 378         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
 379
 380         return 0;
 381 }
 382
 383 /* Enable/Disable Unsolicited Response */
 384 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
 385 {
 386         struct cs8409_spec *spec = codec->spec;
 387         unsigned int ur_gpios = 0;
 388         int i;
 389
 390         for (i = 0; i < spec->num_scodecs; i++)
 391                 ur_gpios |= spec->scodecs[i]->irq_mask;
 392
 393         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
 394                             flag ? ur_gpios : 0);
 395
 396         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
 397                             flag ? AC_UNSOL_ENABLED : 0);
 398 }
 399
 400 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
 401 {
 402         int caps;
 403
 404         /* CS8409 is simple HDA bridge and intended to be used with a remote
 405          * companion codec. Most of input/output PIN(s) have only basic
 406          * capabilities. Receive and Transmit NID(s) have only OUTC and INC
 407          * capabilities and no presence detect capable (PDC) and call to
 408          * snd_hda_gen_build_controls() will mark them as non detectable
 409          * phantom jacks. However, a companion codec may be
 410          * connected to these pins which supports jack detect
 411          * capabilities. We have to override pin capabilities,
 412          * otherwise they will not be created as input devices.
 413          */
 414         caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
 415         if (caps >= 0)
 416                 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
 417                                        (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
 418
 419         snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
 420 }
 421
 422 /******************************************************************************
 423  *                        CS42L42 Specific Functions
 424  ******************************************************************************/
 425
 426 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
 427 {
 428         unsigned int ofs = get_amp_offset(kctrl);
 429         u8 chs = get_amp_channels(kctrl);
 430
 431         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 432         uinfo->value.integer.step = 1;
 433         uinfo->count = chs == 3 ? 2 : 1;
 434
 435         switch (ofs) {
 436         case CS42L42_VOL_DAC:
 437                 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
 438                 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
 439                 break;
 440         case CS42L42_VOL_ADC:
 441                 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
 442                 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
 443                 break;
 444         default:
 445                 break;
 446         }
 447
 448         return 0;
 449 }
 450
 451 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 452 {
 453         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 454         struct cs8409_spec *spec = codec->spec;
 455         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 456         int chs = get_amp_channels(kctrl);
 457         unsigned int ofs = get_amp_offset(kctrl);
 458         long *valp = uctrl->value.integer.value;
 459
 460         switch (ofs) {
 461         case CS42L42_VOL_DAC:
 462                 if (chs & BIT(0))
 463                         *valp++ = cs42l42->vol[ofs];
 464                 if (chs & BIT(1))
 465                         *valp = cs42l42->vol[ofs+1];
 466                 break;
 467         case CS42L42_VOL_ADC:
 468                 if (chs & BIT(0))
 469                         *valp = cs42l42->vol[ofs];
 470                 break;
 471         default:
 472                 break;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
 479         unsigned int chs, bool mute)
 480 {
 481         if (mute) {
 482                 if (vol_type == CS42L42_VOL_DAC) {
 483                         if (chs & BIT(0))
 484                                 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA, 0x3f);
 485                         if (chs & BIT(1))
 486                                 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB, 0x3f);
 487                 } else if (vol_type == CS42L42_VOL_ADC) {
 488                         if (chs & BIT(0))
 489                                 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL, 0x9f);
 490                 }
 491         } else {
 492                 if (vol_type == CS42L42_VOL_DAC) {
 493                         if (chs & BIT(0))
 494                                 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA,
 495                                         -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
 496                                         & CS42L42_REG_HS_VOL_MASK);
 497                         if (chs & BIT(1))
 498                                 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB,
 499                                         -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
 500                                         & CS42L42_REG_HS_VOL_MASK);
 501                 } else if (vol_type == CS42L42_VOL_ADC) {
 502                         if (chs & BIT(0))
 503                                 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL,
 504                                         cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
 505                                         & CS42L42_REG_AMIC_VOL_MASK);
 506                 }
 507         }
 508 }
 509
 510 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 511 {
 512         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 513         struct cs8409_spec *spec = codec->spec;
 514         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 515         int chs = get_amp_channels(kctrl);
 516         unsigned int ofs = get_amp_offset(kctrl);
 517         long *valp = uctrl->value.integer.value;
 518
 519         switch (ofs) {
 520         case CS42L42_VOL_DAC:
 521                 if (chs & BIT(0))
 522                         cs42l42->vol[ofs] = *valp;
 523                 if (chs & BIT(1)) {
 524                         valp++;
 525                         cs42l42->vol[ofs + 1] = *valp;
 526                 }
 527                 if (spec->playback_started)
 528                         cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
 529                 break;
 530         case CS42L42_VOL_ADC:
 531                 if (chs & BIT(0))
 532                         cs42l42->vol[ofs] = *valp;
 533                 if (spec->capture_started)
 534                         cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
 535                 break;
 536         default:
 537                 break;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
 544                                    struct hda_codec *codec,
 545                                    struct snd_pcm_substream *substream,
 546                                    int action)
 547 {
 548         struct cs8409_spec *spec = codec->spec;
 549         struct sub_codec *cs42l42;
 550         int i;
 551         bool mute;
 552
 553         switch (action) {
 554         case HDA_GEN_PCM_ACT_PREPARE:
 555                 mute = false;
 556                 spec->playback_started = 1;
 557                 break;
 558         case HDA_GEN_PCM_ACT_CLEANUP:
 559                 mute = true;
 560                 spec->playback_started = 0;
 561                 break;
 562         default:
 563                 return;
 564         }
 565
 566         for (i = 0; i < spec->num_scodecs; i++) {
 567                 cs42l42 = spec->scodecs[i];
 568                 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
 569         }
 570 }
 571
 572 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
 573                                    struct hda_codec *codec,
 574                                    struct snd_pcm_substream *substream,
 575                                    int action)
 576 {
 577         struct cs8409_spec *spec = codec->spec;
 578         struct sub_codec *cs42l42;
 579         int i;
 580         bool mute;
 581
 582         switch (action) {
 583         case HDA_GEN_PCM_ACT_PREPARE:
 584                 mute = false;
 585                 spec->capture_started = 1;
 586                 break;
 587         case HDA_GEN_PCM_ACT_CLEANUP:
 588                 mute = true;
 589                 spec->capture_started = 0;
 590                 break;
 591         default:
 592                 return;
 593         }
 594
 595         for (i = 0; i < spec->num_scodecs; i++) {
 596                 cs42l42 = spec->scodecs[i];
 597                 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
 598         }
 599 }
 600
 601 /* Configure CS42L42 slave codec for jack autodetect */
 602 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
 603 {
 604         cs8409_i2c_write(cs42l42, 0x1b70, cs42l42->hsbias_hiz);
 605         /* Clear WAKE# */
 606         cs8409_i2c_write(cs42l42, 0x1b71, 0x00C1);
 607         /* Wait ~2.5ms */
 608         usleep_range(2500, 3000);
 609         /* Set mode WAKE# output follows the combination logic directly */
 610         cs8409_i2c_write(cs42l42, 0x1b71, 0x00C0);
 611         /* Clear interrupts status */
 612         cs8409_i2c_read(cs42l42, 0x130f);
 613         /* Enable interrupt */
 614         cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
 615 }
 616
 617 /* Enable and run CS42L42 slave codec jack auto detect */
 618 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
 619 {
 620         /* Clear interrupts */
 621         cs8409_i2c_read(cs42l42, 0x1308);
 622         cs8409_i2c_read(cs42l42, 0x1b77);
 623         cs8409_i2c_write(cs42l42, 0x1320, 0xFF);
 624         cs8409_i2c_read(cs42l42, 0x130f);
 625
 626         cs8409_i2c_write(cs42l42, 0x1102, 0x87);
 627         cs8409_i2c_write(cs42l42, 0x1f06, 0x86);
 628         cs8409_i2c_write(cs42l42, 0x1b74, 0x07);
 629         cs8409_i2c_write(cs42l42, 0x131b, 0xFD);
 630         cs8409_i2c_write(cs42l42, 0x1120, 0x80);
 631         /* Wait ~20ms*/
 632         usleep_range(20000, 25000);
 633         cs8409_i2c_write(cs42l42, 0x111f, 0x77);
 634         cs8409_i2c_write(cs42l42, 0x1120, 0xc0);
 635 }
 636
 637 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
 638 {
 639         int status_changed = cs42l42->force_status_change;
 640
 641         cs42l42->force_status_change = 0;
 642
 643         /* TIP_SENSE INSERT/REMOVE */
 644         switch (reg_ts_status) {
 645         case CS42L42_JACK_INSERTED:
 646                 if (!cs42l42->hp_jack_in) {
 647                         if (cs42l42->no_type_dect) {
 648                                 status_changed = 1;
 649                                 cs42l42->hp_jack_in = 1;
 650                                 cs42l42->mic_jack_in = 0;
 651                         } else {
 652                                 cs42l42_run_jack_detect(cs42l42);
 653                         }
 654                 }
 655                 break;
 656
 657         case CS42L42_JACK_REMOVED:
 658                 if (cs42l42->hp_jack_in || cs42l42->mic_jack_in) {
 659                         status_changed = 1;
 660                         cs42l42->hp_jack_in = 0;
 661                         cs42l42->mic_jack_in = 0;
 662                 }
 663                 break;
 664         default:
 665                 /* jack in transition */
 666                 break;
 667         }
 668
 669         return status_changed;
 670 }
 671
 672 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
 673 {
 674         int status_changed = 0;
 675         int reg_cdc_status;
 676         int reg_hs_status;
 677         int reg_ts_status;
 678         int type;
 679
 680         /* Read jack detect status registers */
 681         reg_cdc_status = cs8409_i2c_read(cs42l42, 0x1308);
 682         reg_hs_status = cs8409_i2c_read(cs42l42, 0x1124);
 683         reg_ts_status = cs8409_i2c_read(cs42l42, 0x130f);
 684
 685         /* If status values are < 0, read error has occurred. */
 686         if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
 687                 return -EIO;
 688
 689         /* HSDET_AUTO_DONE */
 690         if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE) {
 691
 692                 /* Disable HSDET_AUTO_DONE */
 693                 cs8409_i2c_write(cs42l42, 0x131b, 0xFF);
 694
 695                 type = ((reg_hs_status & CS42L42_HSTYPE_MASK) + 1);
 696
 697                 if (cs42l42->no_type_dect) {
 698                         status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
 699                 } else if (type == 4) {
 700                         /* Type 4 not supported */
 701                         status_changed = cs42l42_handle_tip_sense(cs42l42, CS42L42_JACK_REMOVED);
 702                 } else {
 703                         if (!cs42l42->hp_jack_in) {
 704                                 status_changed = 1;
 705                                 cs42l42->hp_jack_in = 1;
 706                         }
 707                         /* type = 3 has no mic */
 708                         if ((!cs42l42->mic_jack_in) && (type != 3)) {
 709                                 status_changed = 1;
 710                                 cs42l42->mic_jack_in = 1;
 711                         }
 712                 }
 713                 /* Configure the HSDET mode. */
 714                 cs8409_i2c_write(cs42l42, 0x1120, 0x80);
 715                 /* Enable the HPOUT ground clamp and configure the HP pull-down */
 716                 cs8409_i2c_write(cs42l42, 0x1F06, 0x02);
 717                 /* Re-Enable Tip Sense Interrupt */
 718                 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
 719         } else {
 720                 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
 721         }
 722
 723         return status_changed;
 724 }
 725
 726 static void cs42l42_resume(struct sub_codec *cs42l42)
 727 {
 728         struct hda_codec *codec = cs42l42->codec;
 729         unsigned int gpio_data;
 730         struct cs8409_i2c_param irq_regs[] = {
 731                 { 0x1308, 0x00 },
 732                 { 0x1309, 0x00 },
 733                 { 0x130A, 0x00 },
 734                 { 0x130F, 0x00 },
 735         };
 736
 737         /* Bring CS42L42 out of Reset */
 738         gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 739         gpio_data |= cs42l42->reset_gpio;
 740         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
 741         usleep_range(10000, 15000);
 742
 743         cs42l42->suspended = 0;
 744
 745         /* Initialize CS42L42 companion codec */
 746         cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
 747         usleep_range(20000, 25000);
 748
 749         /* Clear interrupts, by reading interrupt status registers */
 750         cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
 751
 752         if (cs42l42->full_scale_vol)
 753                 cs8409_i2c_write(cs42l42, 0x2001, 0x01);
 754
 755         /* we have to explicitly allow unsol event handling even during the
 756          * resume phase so that the jack event is processed properly
 757          */
 758         snd_hda_codec_allow_unsol_events(cs42l42->codec);
 759
 760         cs42l42_enable_jack_detect(cs42l42);
 761 }
 762
 763 #ifdef CONFIG_PM
 764 static void cs42l42_suspend(struct sub_codec *cs42l42)
 765 {
 766         struct hda_codec *codec = cs42l42->codec;
 767         unsigned int gpio_data;
 768         int reg_cdc_status = 0;
 769         const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
 770                 { 0x1F06, 0x02 },
 771                 { 0x1129, 0x00 },
 772                 { 0x2301, 0x3F },
 773                 { 0x2302, 0x3F },
 774                 { 0x2303, 0x3F },
 775                 { 0x2001, 0x0F },
 776                 { 0x2A01, 0x00 },
 777                 { 0x1207, 0x00 },
 778                 { 0x1101, 0xFE },
 779                 { 0x1102, 0x8C },
 780                 { 0x1101, 0xFF },
 781         };
 782
 783         cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
 784
 785         if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
 786                         (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
 787                         true, cs42l42, 0x1308) < 0)
 788                 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
 789
 790         /* Power down CS42L42 ASP/EQ/MIX/HP */
 791         cs8409_i2c_write(cs42l42, 0x1102, 0x9C);
 792         cs42l42->suspended = 1;
 793         cs42l42->last_page = 0;
 794         cs42l42->hp_jack_in = 0;
 795         cs42l42->mic_jack_in = 0;
 796         cs42l42->force_status_change = 1;
 797
 798         /* Put CS42L42 into Reset */
 799         gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 800         gpio_data &= ~cs42l42->reset_gpio;
 801         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
 802 }
 803 #endif
 804
 805 static void cs8409_free(struct hda_codec *codec)
 806 {
 807         struct cs8409_spec *spec = codec->spec;
 808
 809         /* Cancel i2c clock disable timer, and disable clock if left enabled */
 810         cancel_delayed_work_sync(&spec->i2c_clk_work);
 811         cs8409_disable_i2c_clock(codec);
 812
 813         snd_hda_gen_free(codec);
 814 }
 815
 816 /******************************************************************************
 817  *                   BULLSEYE / WARLOCK / CYBORG Specific Functions
 818  *                               CS8409/CS42L42
 819  ******************************************************************************/
 820
 821 /*
 822  * In the case of CS8409 we do not have unsolicited events from NID's 0x24
 823  * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
 824  * generate interrupt via gpio 4 to notify jack events. We have to overwrite
 825  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
 826  * and then notify status via generic snd_hda_jack_unsol_event() call.
 827  */
 828 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
 829 {
 830         struct cs8409_spec *spec = codec->spec;
 831         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 832         struct hda_jack_tbl *jk;
 833
 834         /* jack_unsol_event() will be called every time gpio line changing state.
 835          * In this case gpio4 line goes up as a result of reading interrupt status
 836          * registers in previous cs8409_jack_unsol_event() call.
 837          * We don't need to handle this event, ignoring...
 838          */
 839         if (res & cs42l42->irq_mask)
 840                 return;
 841
 842         if (cs42l42_jack_unsol_event(cs42l42)) {
 843                 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
 844                                     cs42l42->hp_jack_in ? 0 : PIN_OUT);
 845                 /* Report jack*/
 846                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
 847                 if (jk)
 848                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 849                                                         AC_UNSOL_RES_TAG);
 850                 /* Report jack*/
 851                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
 852                 if (jk)
 853                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 854                                                          AC_UNSOL_RES_TAG);
 855         }
 856 }
 857
 858 #ifdef CONFIG_PM
 859 /* Manage PDREF, when transition to D3hot */
 860 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
 861 {
 862         struct cs8409_spec *spec = codec->spec;
 863         int i;
 864
 865         spec->init_done = 0;
 866
 867         cs8409_enable_ur(codec, 0);
 868
 869         for (i = 0; i < spec->num_scodecs; i++)
 870                 cs42l42_suspend(spec->scodecs[i]);
 871
 872         /* Cancel i2c clock disable timer, and disable clock if left enabled */
 873         cancel_delayed_work_sync(&spec->i2c_clk_work);
 874         cs8409_disable_i2c_clock(codec);
 875
 876         snd_hda_shutup_pins(codec);
 877
 878         return 0;
 879 }
 880 #endif
 881
 882 /* Vendor specific HW configuration
 883  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
 884  */
 885 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
 886 {
 887         const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
 888         const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
 889         struct cs8409_spec *spec = codec->spec;
 890         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 891
 892         if (spec->gpio_mask) {
 893                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
 894                         spec->gpio_mask);
 895                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
 896                         spec->gpio_dir);
 897                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
 898                         spec->gpio_data);
 899         }
 900
 901         for (; seq->nid; seq++)
 902                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
 903
 904         if (codec->fixup_id == CS8409_BULLSEYE) {
 905                 for (; seq_bullseye->nid; seq_bullseye++)
 906                         cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
 907         }
 908
 909         /* DMIC1_MO=00b, DMIC1/2_SR=1 */
 910         if (codec->fixup_id == CS8409_WARLOCK || codec->fixup_id == CS8409_CYBORG)
 911                 cs8409_vendor_coef_set(codec, 0x09, 0x0003);
 912
 913         cs42l42_resume(cs42l42);
 914
 915         /* Enable Unsolicited Response */
 916         cs8409_enable_ur(codec, 1);
 917 }
 918
 919 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
 920         .build_controls = cs8409_build_controls,
 921         .build_pcms = snd_hda_gen_build_pcms,
 922         .init = cs8409_init,
 923         .free = cs8409_free,
 924         .unsol_event = cs8409_cs42l42_jack_unsol_event,
 925 #ifdef CONFIG_PM
 926         .suspend = cs8409_cs42l42_suspend,
 927 #endif
 928 };
 929
 930 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
 931                                     unsigned int *res)
 932 {
 933         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
 934         struct cs8409_spec *spec = codec->spec;
 935         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 936
 937         unsigned int nid = ((cmd >> 20) & 0x07f);
 938         unsigned int verb = ((cmd >> 8) & 0x0fff);
 939
 940         /* CS8409 pins have no AC_PINSENSE_PRESENCE
 941          * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
 942          * and return correct pin sense values for read_pin_sense() call from
 943          * hda_jack based on CS42L42 jack detect status.
 944          */
 945         switch (nid) {
 946         case CS8409_CS42L42_HP_PIN_NID:
 947                 if (verb == AC_VERB_GET_PIN_SENSE) {
 948                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
 949                         return 0;
 950                 }
 951                 break;
 952         case CS8409_CS42L42_AMIC_PIN_NID:
 953                 if (verb == AC_VERB_GET_PIN_SENSE) {
 954                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
 955                         return 0;
 956                 }
 957                 break;
 958         default:
 959                 break;
 960         }
 961
 962         return spec->exec_verb(dev, cmd, flags, res);
 963 }
 964
 965 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
 966 {
 967         struct cs8409_spec *spec = codec->spec;
 968
 969         switch (action) {
 970         case HDA_FIXUP_ACT_PRE_PROBE:
 971                 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
 972                 /* verb exec op override */
 973                 spec->exec_verb = codec->core.exec_verb;
 974                 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
 975
 976                 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
 977                 spec->num_scodecs = 1;
 978                 spec->scodecs[CS8409_CODEC0]->codec = codec;
 979                 codec->patch_ops = cs8409_cs42l42_patch_ops;
 980
 981                 spec->gen.suppress_auto_mute = 1;
 982                 spec->gen.no_primary_hp = 1;
 983                 spec->gen.suppress_vmaster = 1;
 984
 985                 /* GPIO 5 out, 3,4 in */
 986                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
 987                 spec->gpio_data = 0;
 988                 spec->gpio_mask = 0x03f;
 989
 990                 /* Basic initial sequence for specific hw configuration */
 991                 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
 992
 993                 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
 994                 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
 995
 996                 /* Set TIP_SENSE_EN for analog front-end of tip sense.
 997                  * Additionally set HSBIAS_SENSE_EN and Full Scale volume for some variants.
 998                  */
 999                 switch (codec->fixup_id) {
1000                 case CS8409_WARLOCK:
1001                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1002                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
1003                         break;
1004                 case CS8409_BULLSEYE:
1005                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1006                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 0;
1007                         break;
1008                 case CS8409_CYBORG:
1009                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x00a0;
1010                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
1011                         break;
1012                 default:
1013                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0003;
1014                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
1015                         break;
1016                 }
1017
1018                 break;
1019         case HDA_FIXUP_ACT_PROBE:
1020                 /* Fix Sample Rate to 48kHz */
1021                 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1022                 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1023                 /* add hooks */
1024                 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1025                 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1026                 /* Set initial DMIC volume to -26 dB */
1027                 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1028                                               HDA_INPUT, 0, 0xff, 0x19);
1029                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1030                                 &cs42l42_dac_volume_mixer);
1031                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1032                                 &cs42l42_adc_volume_mixer);
1033                 /* Disable Unsolicited Response during boot */
1034                 cs8409_enable_ur(codec, 0);
1035                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1036                 break;
1037         case HDA_FIXUP_ACT_INIT:
1038                 cs8409_cs42l42_hw_init(codec);
1039                 spec->init_done = 1;
1040                 if (spec->init_done && spec->build_ctrl_done
1041                         && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1042                         cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1043                 break;
1044         case HDA_FIXUP_ACT_BUILD:
1045                 spec->build_ctrl_done = 1;
1046                 /* Run jack auto detect first time on boot
1047                  * after controls have been added, to check if jack has
1048                  * been already plugged in.
1049                  * Run immediately after init.
1050                  */
1051                 if (spec->init_done && spec->build_ctrl_done
1052                         && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1053                         cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1054                 break;
1055         default:
1056                 break;
1057         }
1058 }
1059
1060 /******************************************************************************
1061  *                          Dolphin Specific Functions
1062  *                               CS8409/ 2 X CS42L42
1063  ******************************************************************************/
1064
1065 /*
1066  * In the case of CS8409 we do not have unsolicited events when
1067  * hs mic and hp are connected. Companion codec CS42L42 will
1068  * generate interrupt via irq_mask to notify jack events. We have to overwrite
1069  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1070  * and then notify status via generic snd_hda_jack_unsol_event() call.
1071  */
1072 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1073 {
1074         struct cs8409_spec *spec = codec->spec;
1075         struct sub_codec *cs42l42;
1076         struct hda_jack_tbl *jk;
1077
1078         cs42l42 = spec->scodecs[CS8409_CODEC0];
1079         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1080             cs42l42_jack_unsol_event(cs42l42)) {
1081                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1082                 if (jk)
1083                         snd_hda_jack_unsol_event(codec,
1084                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1085                                                   AC_UNSOL_RES_TAG);
1086
1087                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1088                 if (jk)
1089                         snd_hda_jack_unsol_event(codec,
1090                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1091                                                   AC_UNSOL_RES_TAG);
1092         }
1093
1094         cs42l42 = spec->scodecs[CS8409_CODEC1];
1095         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1096             cs42l42_jack_unsol_event(cs42l42)) {
1097                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1098                 if (jk)
1099                         snd_hda_jack_unsol_event(codec,
1100                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1101                                                   AC_UNSOL_RES_TAG);
1102         }
1103 }
1104
1105 /* Vendor specific HW configuration
1106  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1107  */
1108 static void dolphin_hw_init(struct hda_codec *codec)
1109 {
1110         const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1111         struct cs8409_spec *spec = codec->spec;
1112         struct sub_codec *cs42l42;
1113         int i;
1114
1115         if (spec->gpio_mask) {
1116                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1117                                     spec->gpio_mask);
1118                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1119                                     spec->gpio_dir);
1120                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1121                                     spec->gpio_data);
1122         }
1123
1124         for (; seq->nid; seq++)
1125                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1126
1127         for (i = 0; i < spec->num_scodecs; i++) {
1128                 cs42l42 = spec->scodecs[i];
1129                 cs42l42_resume(cs42l42);
1130         }
1131
1132         /* Enable Unsolicited Response */
1133         cs8409_enable_ur(codec, 1);
1134 }
1135
1136 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1137         .build_controls = cs8409_build_controls,
1138         .build_pcms = snd_hda_gen_build_pcms,
1139         .init = cs8409_init,
1140         .free = cs8409_free,
1141         .unsol_event = dolphin_jack_unsol_event,
1142 #ifdef CONFIG_PM
1143         .suspend = cs8409_cs42l42_suspend,
1144 #endif
1145 };
1146
1147 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1148                              unsigned int *res)
1149 {
1150         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1151         struct cs8409_spec *spec = codec->spec;
1152         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1153
1154         unsigned int nid = ((cmd >> 20) & 0x07f);
1155         unsigned int verb = ((cmd >> 8) & 0x0fff);
1156
1157         /* CS8409 pins have no AC_PINSENSE_PRESENCE
1158          * capabilities. We have to intercept calls for CS42L42 pins
1159          * and return correct pin sense values for read_pin_sense() call from
1160          * hda_jack based on CS42L42 jack detect status.
1161          */
1162         switch (nid) {
1163         case DOLPHIN_HP_PIN_NID:
1164         case DOLPHIN_LO_PIN_NID:
1165                 if (nid == DOLPHIN_LO_PIN_NID)
1166                         cs42l42 = spec->scodecs[CS8409_CODEC1];
1167                 if (verb == AC_VERB_GET_PIN_SENSE) {
1168                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1169                         return 0;
1170                 }
1171                 break;
1172         case DOLPHIN_AMIC_PIN_NID:
1173                 if (verb == AC_VERB_GET_PIN_SENSE) {
1174                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1175                         return 0;
1176                 }
1177                 break;
1178         default:
1179                 break;
1180         }
1181
1182         return spec->exec_verb(dev, cmd, flags, res);
1183 }
1184
1185 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1186 {
1187         struct cs8409_spec *spec = codec->spec;
1188         struct snd_kcontrol_new *kctrl;
1189         int i;
1190
1191         switch (action) {
1192         case HDA_FIXUP_ACT_PRE_PROBE:
1193                 snd_hda_add_verbs(codec, dolphin_init_verbs);
1194                 /* verb exec op override */
1195                 spec->exec_verb = codec->core.exec_verb;
1196                 codec->core.exec_verb = dolphin_exec_verb;
1197
1198                 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1199                 spec->scodecs[CS8409_CODEC0]->codec = codec;
1200                 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1201                 spec->scodecs[CS8409_CODEC1]->codec = codec;
1202                 spec->num_scodecs = 2;
1203
1204                 codec->patch_ops = cs8409_dolphin_patch_ops;
1205
1206                 /* GPIO 1,5 out, 0,4 in */
1207                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1208                                  spec->scodecs[CS8409_CODEC1]->reset_gpio;
1209                 spec->gpio_data = 0;
1210                 spec->gpio_mask = 0x03f;
1211
1212                 /* Basic initial sequence for specific hw configuration */
1213                 snd_hda_sequence_write(codec, dolphin_init_verbs);
1214
1215                 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1216                                       SND_JACK_HEADPHONE, NULL);
1217
1218                 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1219                                       SND_JACK_MICROPHONE, NULL);
1220
1221                 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1222                 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1223                 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1224
1225                 break;
1226         case HDA_FIXUP_ACT_PROBE:
1227                 /* Fix Sample Rate to 48kHz */
1228                 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1229                 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1230                 /* add hooks */
1231                 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1232                 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1233                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1234                                      &cs42l42_dac_volume_mixer);
1235                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1236                 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1237                                              &cs42l42_dac_volume_mixer);
1238                 /* Update Line Out kcontrol template */
1239                 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1240                                        HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1241                 cs8409_enable_ur(codec, 0);
1242                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1243                 break;
1244         case HDA_FIXUP_ACT_INIT:
1245                 dolphin_hw_init(codec);
1246                 spec->init_done = 1;
1247                 if (spec->init_done && spec->build_ctrl_done) {
1248                         for (i = 0; i < spec->num_scodecs; i++) {
1249                                 if (!spec->scodecs[i]->hp_jack_in)
1250                                         cs42l42_run_jack_detect(spec->scodecs[i]);
1251                         }
1252                 }
1253                 break;
1254         case HDA_FIXUP_ACT_BUILD:
1255                 spec->build_ctrl_done = 1;
1256                 /* Run jack auto detect first time on boot
1257                  * after controls have been added, to check if jack has
1258                  * been already plugged in.
1259                  * Run immediately after init.
1260                  */
1261                 if (spec->init_done && spec->build_ctrl_done) {
1262                         for (i = 0; i < spec->num_scodecs; i++) {
1263                                 if (!spec->scodecs[i]->hp_jack_in)
1264                                         cs42l42_run_jack_detect(spec->scodecs[i]);
1265                         }
1266                 }
1267                 break;
1268         default:
1269                 break;
1270         }
1271 }
1272
1273 static int patch_cs8409(struct hda_codec *codec)
1274 {
1275         int err;
1276
1277         if (!cs8409_alloc_spec(codec))
1278                 return -ENOMEM;
1279
1280         snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1281
1282         codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1283                          codec->bus->pci->subsystem_vendor,
1284                          codec->bus->pci->subsystem_device);
1285
1286         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1287
1288         err = cs8409_parse_auto_config(codec);
1289         if (err < 0) {
1290                 cs8409_free(codec);
1291                 return err;
1292         }
1293
1294         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1295         return 0;
1296 }
1297
1298 static const struct hda_device_id snd_hda_id_cs8409[] = {
1299         HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1300         {} /* terminator */
1301 };
1302 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1303
1304 static struct hda_codec_driver cs8409_driver = {
1305         .id = snd_hda_id_cs8409,
1306 };
1307 module_hda_codec_driver(cs8409_driver);
1308
1309 MODULE_LICENSE("GPL");
1310 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");