1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HD audio interface patch for Creative CA0132 chip
5 * Copyright (c) 2011, Creative Technology Ltd.
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
20 #include <linux/pci.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
28 #include "ca0132_regs.h"
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
73 #define EFX_FILE "/*(DEBLOBBED)*/"
74 #define DESKTOP_EFX_FILE "/*(DEBLOBBED)*/"
75 #define R3DI_EFX_FILE "/*(DEBLOBBED)*/"
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
81 static const char *const dirstr[2] = { "Playback", "Capture" };
83 #define NUM_OF_OUTPUTS 2
84 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
95 /* Strings for Input Source Enum Control */
96 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
97 #define IN_SRC_NUM_OF_INPUTS 3
105 #define VNODE_START_NID 0x80
106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
115 #define EFFECT_START_NID 0x90
116 #define OUT_EFFECT_START_NID EFFECT_START_NID
117 SURROUND = OUT_EFFECT_START_NID,
124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
127 ECHO_CANCELLATION = IN_EFFECT_START_NID,
132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
134 VOICEFX = IN_EFFECT_END_NID,
144 AE5_HEADPHONE_GAIN_ENUM,
145 AE5_SOUND_FILTER_ENUM,
147 SPEAKER_CHANNEL_CFG_ENUM,
148 SPEAKER_FULL_RANGE_FRONT,
149 SPEAKER_FULL_RANGE_REAR,
151 BASS_REDIRECTION_XOVER,
152 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 /* Effects values size*/
156 #define EFFECT_VALS_MAX_COUNT 12
159 * Default values for the effect slider controls, they are in order of their
160 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
164 /* Amount of effect level sliders for ca0132_alt controls. */
165 #define EFFECT_LEVEL_SLIDERS 5
167 /* Latency introduced by DSP blocks in milliseconds. */
168 #define DSP_CAPTURE_INIT_LATENCY 0
169 #define DSP_CRYSTAL_VOICE_LATENCY 124
170 #define DSP_PLAYBACK_INIT_LATENCY 13
171 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
172 #define DSP_SPEAKER_OUT_LATENCY 7
175 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
177 int mid; /*effect module ID*/
178 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
179 int direct; /* 0:output; 1:input*/
180 int params; /* number of default non-on/off params */
181 /*effect default values, 1st is on/off. */
182 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 #define EFX_DIR_OUT 0
188 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
189 { .name = "Surround",
193 .direct = EFX_DIR_OUT,
195 .def_vals = {0x3F800000, 0x3F2B851F}
197 { .name = "Crystalizer",
201 .direct = EFX_DIR_OUT,
203 .def_vals = {0x3F800000, 0x3F266666}
205 { .name = "Dialog Plus",
209 .direct = EFX_DIR_OUT,
211 .def_vals = {0x00000000, 0x3F000000}
213 { .name = "Smart Volume",
217 .direct = EFX_DIR_OUT,
219 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 .reqs = {24, 23, 25},
225 .direct = EFX_DIR_OUT,
227 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
229 { .name = "Equalizer",
232 .reqs = {9, 10, 11, 12, 13, 14,
233 15, 16, 17, 18, 19, 20},
234 .direct = EFX_DIR_OUT,
236 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
237 0x00000000, 0x00000000, 0x00000000, 0x00000000,
238 0x00000000, 0x00000000, 0x00000000, 0x00000000}
240 { .name = "Echo Cancellation",
241 .nid = ECHO_CANCELLATION,
243 .reqs = {0, 1, 2, 3},
244 .direct = EFX_DIR_IN,
246 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
248 { .name = "Voice Focus",
251 .reqs = {6, 7, 8, 9},
252 .direct = EFX_DIR_IN,
254 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
260 .direct = EFX_DIR_IN,
262 .def_vals = {0x00000000, 0x3F3D70A4}
264 { .name = "Noise Reduction",
265 .nid = NOISE_REDUCTION,
268 .direct = EFX_DIR_IN,
270 .def_vals = {0x3F800000, 0x3F000000}
275 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
276 .direct = EFX_DIR_IN,
278 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
279 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 /* Tuning controls */
285 #ifdef ENABLE_TUNING_CONTROLS
288 #define TUNING_CTL_START_NID 0xC0
289 WEDGE_ANGLE = TUNING_CTL_START_NID,
302 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 struct ct_tuning_ctl {
306 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
307 hda_nid_t parent_nid;
309 int mid; /*effect module ID*/
310 int req; /*effect module request*/
311 int direct; /* 0:output; 1:input*/
312 unsigned int def_val;/*effect default values*/
315 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
316 { .name = "Wedge Angle",
317 .parent_nid = VOICE_FOCUS,
321 .direct = EFX_DIR_IN,
322 .def_val = 0x41F00000
324 { .name = "SVM Level",
325 .parent_nid = MIC_SVM,
329 .direct = EFX_DIR_IN,
330 .def_val = 0x3F3D70A4
332 { .name = "EQ Band0",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_0,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
340 { .name = "EQ Band1",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_1,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
348 { .name = "EQ Band2",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_2,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
356 { .name = "EQ Band3",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_3,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
364 { .name = "EQ Band4",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_4,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
372 { .name = "EQ Band5",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_5,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
380 { .name = "EQ Band6",
381 .parent_nid = EQUALIZER,
382 .nid = EQUALIZER_BAND_6,
385 .direct = EFX_DIR_OUT,
386 .def_val = 0x00000000
388 { .name = "EQ Band7",
389 .parent_nid = EQUALIZER,
390 .nid = EQUALIZER_BAND_7,
393 .direct = EFX_DIR_OUT,
394 .def_val = 0x00000000
396 { .name = "EQ Band8",
397 .parent_nid = EQUALIZER,
398 .nid = EQUALIZER_BAND_8,
401 .direct = EFX_DIR_OUT,
402 .def_val = 0x00000000
404 { .name = "EQ Band9",
405 .parent_nid = EQUALIZER,
406 .nid = EQUALIZER_BAND_9,
409 .direct = EFX_DIR_OUT,
410 .def_val = 0x00000000
415 /* Voice FX Presets */
416 #define VOICEFX_MAX_PARAM_COUNT 9
422 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 struct ct_voicefx_preset {
426 char *name; /*preset name*/
427 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 static const struct ct_voicefx ca0132_voicefx = {
431 .name = "VoiceFX Capture Switch",
434 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
439 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
440 0x44FA0000, 0x3F800000, 0x3F800000,
441 0x3F800000, 0x00000000, 0x00000000 }
443 { .name = "Female2Male",
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x44FA0000, 0x3F19999A, 0x3F866666,
446 0x3F800000, 0x00000000, 0x00000000 }
448 { .name = "Male2Female",
449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
450 0x450AC000, 0x4017AE14, 0x3F6B851F,
451 0x3F800000, 0x00000000, 0x00000000 }
453 { .name = "ScrappyKid",
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x44FA0000, 0x40400000, 0x3F28F5C3,
456 0x3F800000, 0x00000000, 0x00000000 }
459 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
460 0x44E10000, 0x3FB33333, 0x3FB9999A,
461 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
465 0x45098000, 0x3F266666, 0x3FC00000,
466 0x3F800000, 0x00000000, 0x00000000 }
469 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
470 0x45193000, 0x3F8E147B, 0x3F75C28F,
471 0x3F800000, 0x00000000, 0x00000000 }
474 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
475 0x45007000, 0x3F451EB8, 0x3F7851EC,
476 0x3F800000, 0x00000000, 0x00000000 }
478 { .name = "AlienBrute",
479 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
480 0x451F6000, 0x3F266666, 0x3FA7D945,
481 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
485 0x44FA0000, 0x3FB2718B, 0x3F800000,
486 0xBC07010E, 0x00000000, 0x00000000 }
489 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
490 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
491 0x3F0A3D71, 0x00000000, 0x00000000 }
494 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
495 0x44FA0000, 0x3F800000, 0x3F800000,
496 0x3E4CCCCD, 0x00000000, 0x00000000 }
498 { .name = "DeepVoice",
499 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
500 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
501 0x3F800000, 0x00000000, 0x00000000 }
503 { .name = "Munchkin",
504 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
505 0x44FA0000, 0x3F800000, 0x3F1A043C,
506 0x3F800000, 0x00000000, 0x00000000 }
510 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
512 #define EQ_PRESET_MAX_PARAM_COUNT 11
518 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 struct ct_eq_preset {
522 char *name; /*preset name*/
523 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 static const struct ct_eq ca0132_alt_eq_enum = {
527 .name = "FX: Equalizer Preset Switch",
528 .nid = EQ_PRESET_ENUM,
530 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
534 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
536 .vals = { 0x00000000, 0x00000000, 0x00000000,
537 0x00000000, 0x00000000, 0x00000000,
538 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000 }
541 { .name = "Acoustic",
542 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
543 0x40000000, 0x00000000, 0x00000000,
544 0x00000000, 0x00000000, 0x40000000,
545 0x40000000, 0x40000000 }
547 { .name = "Classical",
548 .vals = { 0x00000000, 0x00000000, 0x40C00000,
549 0x40C00000, 0x40466666, 0x00000000,
550 0x00000000, 0x00000000, 0x00000000,
551 0x40466666, 0x40466666 }
554 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
555 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
556 0x00000000, 0x00000000, 0x40000000,
557 0x40466666, 0x40800000 }
560 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
561 0x40466666, 0x40866666, 0xBF99999A,
562 0xBF99999A, 0x00000000, 0x00000000,
563 0x40800000, 0x40800000 }
566 .vals = { 0x00000000, 0x00000000, 0x00000000,
567 0x3F8CCCCD, 0x40800000, 0x40800000,
568 0x40800000, 0x00000000, 0x3F8CCCCD,
569 0x40466666, 0x40466666 }
572 .vals = { 0x00000000, 0x00000000, 0x40000000,
573 0x40000000, 0x00000000, 0x00000000,
574 0x00000000, 0x3F8CCCCD, 0x40000000,
575 0x40000000, 0x40000000 }
578 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
579 0x40000000, 0x40000000, 0x00000000,
580 0xBF99999A, 0xBF99999A, 0x00000000,
581 0x40466666, 0x40C00000 }
584 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
585 0x3F8CCCCD, 0x40000000, 0xBF99999A,
586 0xBF99999A, 0x00000000, 0x00000000,
587 0x40800000, 0x40800000 }
590 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
591 0xBF99999A, 0x00000000, 0x40466666,
592 0x40800000, 0x40466666, 0x00000000,
593 0x00000000, 0x3F8CCCCD }
598 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
599 * set as not being full range, and bass redirection is enabled, all
600 * frequencies below the crossover frequency are redirected to the LFE
601 * channel. If the surround configuration has no LFE channel, this can't be
602 * enabled. X-Bass must be disabled when using these.
604 enum speaker_range_reqs {
605 SPEAKER_BASS_REDIRECT = 0x15,
606 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
607 /* Between 0x16-0x1a are the X-Bass reqs. */
608 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
609 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
610 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
611 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
612 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
616 * Definitions for the DSP req's to handle speaker tuning. These all belong to
617 * module ID 0x96, the output effects module.
619 enum speaker_tuning_reqs {
621 * Currently, this value is always set to 0.0f. However, on Windows,
622 * when selecting certain headphone profiles on the new Sound Blaster
623 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
624 * sent. This gets the speaker EQ address area, which is then used to
625 * send over (presumably) an equalizer profile for the specific
626 * headphone setup. It is sent using the same method the DSP
627 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
628 * file exists in linux firmware tree but goes unused. It would also
629 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
630 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
634 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
635 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
636 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
637 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
638 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
639 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
640 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
641 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
642 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
644 * Inversion is used when setting headphone virtualization to line
645 * out. Not sure why this is, but it's the only place it's ever used.
647 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
648 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
649 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
650 SPEAKER_TUNING_LFE_INVERT = 0x2c,
651 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
652 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
653 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
654 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
655 /* Delay is used when setting surround speaker distance in Windows. */
656 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
657 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
658 SPEAKER_TUNING_CENTER_DELAY = 0x33,
659 SPEAKER_TUNING_LFE_DELAY = 0x34,
660 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
661 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
662 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
663 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
664 /* Of these two, only mute seems to ever be used. */
665 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
666 SPEAKER_TUNING_MUTE = 0x3a,
669 /* Surround output channel count configuration structures. */
670 #define SPEAKER_CHANNEL_CFG_COUNT 5
672 SPEAKER_CHANNELS_2_0,
673 SPEAKER_CHANNELS_2_1,
674 SPEAKER_CHANNELS_4_0,
675 SPEAKER_CHANNELS_4_1,
676 SPEAKER_CHANNELS_5_1,
679 struct ca0132_alt_speaker_channel_cfg {
684 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
703 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
704 * and I don't know what the third req is, but it's always zero. I assume it's
705 * some sort of update or set command to tell the DSP there's new volume info.
707 #define DSP_VOL_OUT 0
710 struct ct_dsp_volume_ctl {
712 int mid; /* module ID*/
713 unsigned int reqs[3]; /* scp req ID */
716 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
727 /* Values for ca0113_mmio_command_set for selecting output. */
728 #define AE_CA0113_OUT_SET_COMMANDS 6
729 struct ae_ca0113_output_set {
730 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
731 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
732 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
736 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
737 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
739 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
741 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
745 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
746 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
748 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
750 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 /* ae5 ca0113 command sequences to set headphone gain levels. */
754 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
755 struct ae5_headphone_gain_set {
757 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
761 { .name = "Low (16-31",
762 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
764 { .name = "Medium (32-149",
765 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
767 { .name = "High (150-600",
768 .vals = { 0xff, 0xff, 0xff, 0x7f }
772 struct ae5_filter_set {
777 static const struct ae5_filter_set ae5_filter_presets[] = {
778 { .name = "Slow Roll Off",
781 { .name = "Minimum Phase",
784 { .name = "Fast Roll Off",
789 enum hda_cmd_vendor_io {
791 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
792 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
794 VENDOR_DSPIO_STATUS = 0xF01,
795 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
796 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
797 VENDOR_DSPIO_DSP_INIT = 0x703,
798 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
799 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
801 /* for ChipIO node */
802 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
803 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
804 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
805 VENDOR_CHIPIO_DATA_LOW = 0x300,
806 VENDOR_CHIPIO_DATA_HIGH = 0x400,
808 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
809 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
811 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
812 VENDOR_CHIPIO_STATUS = 0xF01,
813 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
814 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
816 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
817 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
818 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
819 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
820 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
822 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
823 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
825 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
826 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
827 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
828 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
829 VENDOR_CHIPIO_FLAG_SET = 0x70F,
830 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
831 VENDOR_CHIPIO_PARAM_SET = 0x710,
832 VENDOR_CHIPIO_PARAM_GET = 0xF10,
834 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
835 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
836 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
837 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
839 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
840 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
841 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
842 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
844 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
845 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
846 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
847 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
848 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
849 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
851 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
857 enum control_flag_id {
858 /* Connection manager stream setup is bypassed/enabled */
859 CONTROL_FLAG_C_MGR = 0,
860 /* DSP DMA is bypassed/enabled */
861 CONTROL_FLAG_DMA = 1,
862 /* 8051 'idle' mode is disabled/enabled */
863 CONTROL_FLAG_IDLE_ENABLE = 2,
864 /* Tracker for the SPDIF-in path is bypassed/enabled */
865 CONTROL_FLAG_TRACKER = 3,
866 /* DigitalOut to Spdif2Out connection is disabled/enabled */
867 CONTROL_FLAG_SPDIF2OUT = 4,
868 /* Digital Microphone is disabled/enabled */
869 CONTROL_FLAG_DMIC = 5,
870 /* ADC_B rate is 48 kHz/96 kHz */
871 CONTROL_FLAG_ADC_B_96KHZ = 6,
872 /* ADC_C rate is 48 kHz/96 kHz */
873 CONTROL_FLAG_ADC_C_96KHZ = 7,
874 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
875 CONTROL_FLAG_DAC_96KHZ = 8,
876 /* DSP rate is 48 kHz/96 kHz */
877 CONTROL_FLAG_DSP_96KHZ = 9,
878 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
879 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
880 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
881 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
882 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
883 CONTROL_FLAG_DECODE_LOOP = 12,
884 /* De-emphasis filter on DAC-1 disabled/enabled */
885 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
886 /* De-emphasis filter on DAC-2 disabled/enabled */
887 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
888 /* De-emphasis filter on DAC-3 disabled/enabled */
889 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
890 /* High-pass filter on ADC_B disabled/enabled */
891 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
892 /* High-pass filter on ADC_C disabled/enabled */
893 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
894 /* Common mode on Port_A disabled/enabled */
895 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
896 /* Common mode on Port_D disabled/enabled */
897 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
898 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
899 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
900 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
901 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
902 /* ASI rate is 48kHz/96kHz */
903 CONTROL_FLAG_ASI_96KHZ = 22,
904 /* DAC power settings able to control attached ports no/yes */
905 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
906 /* Clock Stop OK reporting is disabled/enabled */
907 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
908 /* Number of control flags */
909 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
913 * Control parameter IDs
915 enum control_param_id {
916 /* 0: None, 1: Mic1In*/
917 CONTROL_PARAM_VIP_SOURCE = 1,
918 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
919 CONTROL_PARAM_SPDIF1_SOURCE = 2,
920 /* Port A output stage gain setting to use when 16 Ohm output
921 * impedance is selected*/
922 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
923 /* Port D output stage gain setting to use when 16 Ohm output
924 * impedance is selected*/
925 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
928 * This control param name was found in the 8051 memory, and makes
929 * sense given the fact the AE-5 uses it and has the ASI flag set.
931 CONTROL_PARAM_ASI = 23,
935 /* Select stream with the given ID */
936 CONTROL_PARAM_STREAM_ID = 24,
937 /* Source connection point for the selected stream */
938 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
939 /* Destination connection point for the selected stream */
940 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
941 /* Number of audio channels in the selected stream */
942 CONTROL_PARAM_STREAMS_CHANNELS = 27,
943 /*Enable control for the selected stream */
944 CONTROL_PARAM_STREAM_CONTROL = 28,
946 /* Connection Point Control */
948 /* Select connection point with the given ID */
949 CONTROL_PARAM_CONN_POINT_ID = 29,
950 /* Connection point sample rate */
951 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
955 /* Select HDA node with the given ID */
956 CONTROL_PARAM_NODE_ID = 31
960 * Dsp Io Status codes
962 enum hda_vendor_status_dspio {
964 VENDOR_STATUS_DSPIO_OK = 0x00,
965 /* Busy, unable to accept new command, the host must retry */
966 VENDOR_STATUS_DSPIO_BUSY = 0x01,
967 /* SCP command queue is full */
968 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
969 /* SCP response queue is empty */
970 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
974 * Chip Io Status codes
976 enum hda_vendor_status_chipio {
978 VENDOR_STATUS_CHIPIO_OK = 0x00,
979 /* Busy, unable to accept new command, the host must retry */
980 VENDOR_STATUS_CHIPIO_BUSY = 0x01
986 enum ca0132_sample_rate {
1006 SR_RATE_UNKNOWN = 0x1F
1009 enum dsp_download_state {
1010 DSP_DOWNLOAD_FAILED = -1,
1011 DSP_DOWNLOAD_INIT = 0,
1012 DSP_DOWNLOADING = 1,
1016 /* retrieve parameters from hda format */
1017 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1018 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1019 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1020 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1026 struct ca0132_spec {
1027 const struct snd_kcontrol_new *mixers[5];
1028 unsigned int num_mixers;
1029 const struct hda_verb *base_init_verbs;
1030 const struct hda_verb *base_exit_verbs;
1031 const struct hda_verb *chip_init_verbs;
1032 const struct hda_verb *desktop_init_verbs;
1033 struct hda_verb *spec_init_verbs;
1034 struct auto_pin_cfg autocfg;
1036 /* Nodes configurations */
1037 struct hda_multi_out multiout;
1038 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1039 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1040 unsigned int num_outputs;
1041 hda_nid_t input_pins[AUTO_PIN_LAST];
1042 hda_nid_t adcs[AUTO_PIN_LAST];
1045 unsigned int num_inputs;
1046 hda_nid_t shared_mic_nid;
1047 hda_nid_t shared_out_nid;
1048 hda_nid_t unsol_tag_hp;
1049 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1050 hda_nid_t unsol_tag_amic1;
1053 struct mutex chipio_mutex; /* chip access mutex */
1056 /* DSP download related */
1057 enum dsp_download_state dsp_state;
1058 unsigned int dsp_stream_id;
1059 unsigned int wait_scp;
1060 unsigned int wait_scp_header;
1061 unsigned int wait_num_data;
1062 unsigned int scp_resp_header;
1063 unsigned int scp_resp_data[4];
1064 unsigned int scp_resp_count;
1065 bool startup_check_entered;
1068 /* mixer and effects related */
1069 unsigned char dmic_ctl;
1072 long vnode_lvol[VNODES_COUNT];
1073 long vnode_rvol[VNODES_COUNT];
1074 long vnode_lswitch[VNODES_COUNT];
1075 long vnode_rswitch[VNODES_COUNT];
1076 long effects_switch[EFFECTS_COUNT];
1079 /* ca0132_alt control related values */
1080 unsigned char in_enum_val;
1081 unsigned char out_enum_val;
1082 unsigned char channel_cfg_val;
1083 unsigned char speaker_range_val[2];
1084 unsigned char mic_boost_enum_val;
1085 unsigned char smart_volume_setting;
1086 unsigned char bass_redirection_val;
1087 long bass_redirect_xover_freq;
1088 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1089 long xbass_xover_freq;
1091 unsigned int tlv[4];
1092 struct hda_vmaster_mute_hook vmaster_mute;
1093 /* AE-5 Control values */
1094 unsigned char ae5_headphone_gain_val;
1095 unsigned char ae5_filter_val;
1096 /* ZxR Control Values */
1097 unsigned char zxr_gain_set;
1099 struct hda_codec *codec;
1100 struct delayed_work unsol_hp_work;
1103 #ifdef ENABLE_TUNING_CONTROLS
1104 long cur_ctl_vals[TUNING_CTLS_COUNT];
1107 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1108 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1112 void __iomem *mem_base;
1115 * Whether or not to use the alt functions like alt_select_out,
1116 * alt_select_in, etc. Only used on desktop codecs for now, because of
1117 * surround sound support.
1119 bool use_alt_functions;
1122 * Whether or not to use alt controls: volume effect sliders, EQ
1123 * presets, smart volume presets, and new control names with FX prefix.
1124 * Renames PlayEnhancement and CrystalVoice too.
1126 bool use_alt_controls;
1130 * CA0132 quirks table
1135 QUIRK_ALIENWARE_M17XR4,
1146 #define ca0132_quirk(spec) ((spec)->quirk)
1147 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1148 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1149 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1151 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1152 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1153 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1154 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1157 static const struct hda_pintbl alienware_pincfgs[] = {
1158 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1159 { 0x0c, 0x411111f0 }, /* N/A */
1160 { 0x0d, 0x411111f0 }, /* N/A */
1161 { 0x0e, 0x411111f0 }, /* N/A */
1162 { 0x0f, 0x0321101f }, /* HP */
1163 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1164 { 0x11, 0x03a11021 }, /* Mic */
1165 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1166 { 0x13, 0x411111f0 }, /* N/A */
1167 { 0x18, 0x411111f0 }, /* N/A */
1171 /* Sound Blaster Z pin configs taken from Windows Driver */
1172 static const struct hda_pintbl sbz_pincfgs[] = {
1173 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1174 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1175 { 0x0d, 0x014510f0 }, /* Digital Out */
1176 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1177 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1178 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1179 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1180 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1181 { 0x13, 0x908700f0 }, /* What U Hear In*/
1182 { 0x18, 0x50d000f0 }, /* N/A */
1186 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1187 static const struct hda_pintbl zxr_pincfgs[] = {
1188 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1189 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1190 { 0x0d, 0x014510f0 }, /* Digital Out */
1191 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1192 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1193 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1194 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1195 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1196 { 0x13, 0x908700f0 }, /* What U Hear In*/
1197 { 0x18, 0x50d000f0 }, /* N/A */
1201 /* Recon3D pin configs taken from Windows Driver */
1202 static const struct hda_pintbl r3d_pincfgs[] = {
1203 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1204 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1205 { 0x0d, 0x014510f0 }, /* Digital Out */
1206 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1207 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1208 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1209 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1210 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1211 { 0x13, 0x908700f0 }, /* What U Hear In*/
1212 { 0x18, 0x50d000f0 }, /* N/A */
1216 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1217 static const struct hda_pintbl ae5_pincfgs[] = {
1218 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1219 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1220 { 0x0d, 0x014510f0 }, /* Digital Out */
1221 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1222 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1223 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1224 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1225 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1226 { 0x13, 0x908700f0 }, /* What U Hear In*/
1227 { 0x18, 0x50d000f0 }, /* N/A */
1231 /* Recon3D integrated pin configs taken from Windows Driver */
1232 static const struct hda_pintbl r3di_pincfgs[] = {
1233 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1234 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1235 { 0x0d, 0x014510f0 }, /* Digital Out */
1236 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1237 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1238 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1239 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1240 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1241 { 0x13, 0x908700f0 }, /* What U Hear In*/
1242 { 0x18, 0x500000f0 }, /* N/A */
1246 static const struct hda_pintbl ae7_pincfgs[] = {
1247 { 0x0b, 0x01017010 },
1248 { 0x0c, 0x014510f0 },
1249 { 0x0d, 0x414510f0 },
1250 { 0x0e, 0x01c520f0 },
1251 { 0x0f, 0x01017114 },
1252 { 0x10, 0x01017011 },
1253 { 0x11, 0x018170ff },
1254 { 0x12, 0x01a170f0 },
1255 { 0x13, 0x908700f0 },
1256 { 0x18, 0x500000f0 },
1260 static const struct snd_pci_quirk ca0132_quirks[] = {
1261 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1262 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1263 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1264 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1265 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1266 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1267 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1268 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1269 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1270 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1271 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1272 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1273 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1274 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1275 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1276 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1277 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1278 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1279 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1283 /* Output selection quirk info structures. */
1284 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1285 #define MAX_QUIRK_SCP_SET_VALS 2
1286 struct ca0132_alt_out_set_info {
1287 unsigned int dac2port; /* ParamID 0x0d value. */
1293 unsigned int mmio_gpio_count;
1294 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1295 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1297 unsigned int scp_cmds_count;
1298 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1299 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1300 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1302 bool has_chipio_write;
1303 unsigned int chipio_write_addr;
1304 unsigned int chipio_write_data;
1307 struct ca0132_alt_out_set_quirk_data {
1310 bool has_headphone_gain;
1313 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1316 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1317 { .quirk_id = QUIRK_R3DI,
1318 .has_headphone_gain = false,
1319 .is_ae_series = false,
1323 .has_hda_gpio = true,
1326 .mmio_gpio_count = 0,
1327 .scp_cmds_count = 0,
1328 .has_chipio_write = false,
1332 .has_hda_gpio = true,
1335 .mmio_gpio_count = 0,
1336 .scp_cmds_count = 0,
1337 .has_chipio_write = false,
1340 { .quirk_id = QUIRK_R3D,
1341 .has_headphone_gain = false,
1342 .is_ae_series = false,
1346 .has_hda_gpio = false,
1347 .mmio_gpio_count = 1,
1348 .mmio_gpio_pin = { 1 },
1349 .mmio_gpio_set = { 1 },
1350 .scp_cmds_count = 0,
1351 .has_chipio_write = false,
1355 .has_hda_gpio = false,
1356 .mmio_gpio_count = 1,
1357 .mmio_gpio_pin = { 1 },
1358 .mmio_gpio_set = { 0 },
1359 .scp_cmds_count = 0,
1360 .has_chipio_write = false,
1363 { .quirk_id = QUIRK_SBZ,
1364 .has_headphone_gain = false,
1365 .is_ae_series = false,
1369 .has_hda_gpio = false,
1370 .mmio_gpio_count = 3,
1371 .mmio_gpio_pin = { 7, 4, 1 },
1372 .mmio_gpio_set = { 0, 1, 1 },
1373 .scp_cmds_count = 0,
1374 .has_chipio_write = false, },
1377 .has_hda_gpio = false,
1378 .mmio_gpio_count = 3,
1379 .mmio_gpio_pin = { 7, 4, 1 },
1380 .mmio_gpio_set = { 1, 1, 0 },
1381 .scp_cmds_count = 0,
1382 .has_chipio_write = false,
1385 { .quirk_id = QUIRK_ZXR,
1386 .has_headphone_gain = true,
1387 .is_ae_series = false,
1391 .has_hda_gpio = false,
1392 .mmio_gpio_count = 3,
1393 .mmio_gpio_pin = { 2, 3, 5 },
1394 .mmio_gpio_set = { 1, 1, 0 },
1395 .scp_cmds_count = 0,
1396 .has_chipio_write = false,
1400 .has_hda_gpio = false,
1401 .mmio_gpio_count = 3,
1402 .mmio_gpio_pin = { 2, 3, 5 },
1403 .mmio_gpio_set = { 0, 1, 1 },
1404 .scp_cmds_count = 0,
1405 .has_chipio_write = false,
1408 { .quirk_id = QUIRK_AE5,
1409 .has_headphone_gain = true,
1410 .is_ae_series = true,
1414 .has_hda_gpio = false,
1415 .mmio_gpio_count = 0,
1416 .scp_cmds_count = 2,
1417 .scp_cmd_mid = { 0x96, 0x96 },
1418 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1419 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1420 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1421 .has_chipio_write = true,
1422 .chipio_write_addr = 0x0018b03c,
1423 .chipio_write_data = 0x00000012
1427 .has_hda_gpio = false,
1428 .mmio_gpio_count = 0,
1429 .scp_cmds_count = 2,
1430 .scp_cmd_mid = { 0x96, 0x96 },
1431 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1432 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1433 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1434 .has_chipio_write = true,
1435 .chipio_write_addr = 0x0018b03c,
1436 .chipio_write_data = 0x00000012
1439 { .quirk_id = QUIRK_AE7,
1440 .has_headphone_gain = true,
1441 .is_ae_series = true,
1445 .has_hda_gpio = false,
1446 .mmio_gpio_count = 1,
1447 .mmio_gpio_pin = { 0 },
1448 .mmio_gpio_set = { 1 },
1449 .scp_cmds_count = 2,
1450 .scp_cmd_mid = { 0x96, 0x96 },
1451 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1452 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1453 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1454 .has_chipio_write = true,
1455 .chipio_write_addr = 0x0018b03c,
1456 .chipio_write_data = 0x00000000
1460 .has_hda_gpio = false,
1461 .mmio_gpio_count = 1,
1462 .mmio_gpio_pin = { 0 },
1463 .mmio_gpio_set = { 1 },
1464 .scp_cmds_count = 2,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1468 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1469 .has_chipio_write = true,
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000010
1477 * CA0132 codec access
1479 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1480 unsigned int verb, unsigned int parm, unsigned int *res)
1482 unsigned int response;
1483 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1486 return ((response == -1) ? -1 : 0);
1489 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1490 unsigned short converter_format, unsigned int *res)
1492 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1493 converter_format & 0xffff, res);
1496 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1497 hda_nid_t nid, unsigned char stream,
1498 unsigned char channel, unsigned int *res)
1500 unsigned char converter_stream_channel = 0;
1502 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1503 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1504 converter_stream_channel, res);
1507 /* Chip access helper function */
1508 static int chipio_send(struct hda_codec *codec,
1513 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1515 /* send bits of data specified by reg */
1517 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1519 if (res == VENDOR_STATUS_CHIPIO_OK)
1522 } while (time_before(jiffies, timeout));
1528 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1530 static int chipio_write_address(struct hda_codec *codec,
1531 unsigned int chip_addx)
1533 struct ca0132_spec *spec = codec->spec;
1536 if (spec->curr_chip_addx == chip_addx)
1539 /* send low 16 bits of the address */
1540 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1541 chip_addx & 0xffff);
1544 /* send high 16 bits of the address */
1545 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1549 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1555 * Write data through the vendor widget -- NOT protected by the Mutex!
1557 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1559 struct ca0132_spec *spec = codec->spec;
1562 /* send low 16 bits of the data */
1563 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1566 /* send high 16 bits of the data */
1567 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1571 /*If no error encountered, automatically increment the address
1572 as per chip behaviour*/
1573 spec->curr_chip_addx = (res != -EIO) ?
1574 (spec->curr_chip_addx + 4) : ~0U;
1579 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1581 static int chipio_write_data_multiple(struct hda_codec *codec,
1588 codec_dbg(codec, "chipio_write_data null ptr\n");
1592 while ((count-- != 0) && (status == 0))
1593 status = chipio_write_data(codec, *data++);
1600 * Read data through the vendor widget -- NOT protected by the Mutex!
1602 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1604 struct ca0132_spec *spec = codec->spec;
1608 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1612 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1617 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1618 VENDOR_CHIPIO_HIC_READ_DATA,
1622 /*If no error encountered, automatically increment the address
1623 as per chip behaviour*/
1624 spec->curr_chip_addx = (res != -EIO) ?
1625 (spec->curr_chip_addx + 4) : ~0U;
1630 * Write given value to the given address through the chip I/O widget.
1631 * protected by the Mutex
1633 static int chipio_write(struct hda_codec *codec,
1634 unsigned int chip_addx, const unsigned int data)
1636 struct ca0132_spec *spec = codec->spec;
1639 mutex_lock(&spec->chipio_mutex);
1641 /* write the address, and if successful proceed to write data */
1642 err = chipio_write_address(codec, chip_addx);
1646 err = chipio_write_data(codec, data);
1651 mutex_unlock(&spec->chipio_mutex);
1656 * Write given value to the given address through the chip I/O widget.
1657 * not protected by the Mutex
1659 static int chipio_write_no_mutex(struct hda_codec *codec,
1660 unsigned int chip_addx, const unsigned int data)
1665 /* write the address, and if successful proceed to write data */
1666 err = chipio_write_address(codec, chip_addx);
1670 err = chipio_write_data(codec, data);
1679 * Write multiple values to the given address through the chip I/O widget.
1680 * protected by the Mutex
1682 static int chipio_write_multiple(struct hda_codec *codec,
1687 struct ca0132_spec *spec = codec->spec;
1690 mutex_lock(&spec->chipio_mutex);
1691 status = chipio_write_address(codec, chip_addx);
1695 status = chipio_write_data_multiple(codec, data, count);
1697 mutex_unlock(&spec->chipio_mutex);
1703 * Read the given address through the chip I/O widget
1704 * protected by the Mutex
1706 static int chipio_read(struct hda_codec *codec,
1707 unsigned int chip_addx, unsigned int *data)
1709 struct ca0132_spec *spec = codec->spec;
1712 mutex_lock(&spec->chipio_mutex);
1714 /* write the address, and if successful proceed to write data */
1715 err = chipio_write_address(codec, chip_addx);
1719 err = chipio_read_data(codec, data);
1724 mutex_unlock(&spec->chipio_mutex);
1729 * Set chip control flags through the chip I/O widget.
1731 static void chipio_set_control_flag(struct hda_codec *codec,
1732 enum control_flag_id flag_id,
1736 unsigned int flag_bit;
1738 flag_bit = (flag_state ? 1 : 0);
1739 val = (flag_bit << 7) | (flag_id);
1740 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1741 VENDOR_CHIPIO_FLAG_SET, val);
1745 * Set chip parameters through the chip I/O widget.
1747 static void chipio_set_control_param(struct hda_codec *codec,
1748 enum control_param_id param_id, int param_val)
1750 struct ca0132_spec *spec = codec->spec;
1753 if ((param_id < 32) && (param_val < 8)) {
1754 val = (param_val << 5) | (param_id);
1755 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1756 VENDOR_CHIPIO_PARAM_SET, val);
1758 mutex_lock(&spec->chipio_mutex);
1759 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1760 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1761 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1763 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1764 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1767 mutex_unlock(&spec->chipio_mutex);
1772 * Set chip parameters through the chip I/O widget. NO MUTEX.
1774 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1775 enum control_param_id param_id, int param_val)
1779 if ((param_id < 32) && (param_val < 8)) {
1780 val = (param_val << 5) | (param_id);
1781 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1782 VENDOR_CHIPIO_PARAM_SET, val);
1784 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1785 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1786 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1789 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1795 * Connect stream to a source point, and then connect
1796 * that source point to a destination point.
1798 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1799 int streamid, int source_point, int dest_point)
1801 chipio_set_control_param_no_mutex(codec,
1802 CONTROL_PARAM_STREAM_ID, streamid);
1803 chipio_set_control_param_no_mutex(codec,
1804 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1805 chipio_set_control_param_no_mutex(codec,
1806 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1810 * Set number of channels in the selected stream.
1812 static void chipio_set_stream_channels(struct hda_codec *codec,
1813 int streamid, unsigned int channels)
1815 chipio_set_control_param_no_mutex(codec,
1816 CONTROL_PARAM_STREAM_ID, streamid);
1817 chipio_set_control_param_no_mutex(codec,
1818 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1822 * Enable/Disable audio stream.
1824 static void chipio_set_stream_control(struct hda_codec *codec,
1825 int streamid, int enable)
1827 chipio_set_control_param_no_mutex(codec,
1828 CONTROL_PARAM_STREAM_ID, streamid);
1829 chipio_set_control_param_no_mutex(codec,
1830 CONTROL_PARAM_STREAM_CONTROL, enable);
1835 * Set sampling rate of the connection point. NO MUTEX.
1837 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1838 int connid, enum ca0132_sample_rate rate)
1840 chipio_set_control_param_no_mutex(codec,
1841 CONTROL_PARAM_CONN_POINT_ID, connid);
1842 chipio_set_control_param_no_mutex(codec,
1843 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1847 * Set sampling rate of the connection point.
1849 static void chipio_set_conn_rate(struct hda_codec *codec,
1850 int connid, enum ca0132_sample_rate rate)
1852 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1853 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1858 * Writes to the 8051's internal address space directly instead of indirectly,
1859 * giving access to the special function registers located at addresses
1862 static void chipio_8051_write_direct(struct hda_codec *codec,
1863 unsigned int addr, unsigned int data)
1867 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1868 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1874 static void chipio_enable_clocks(struct hda_codec *codec)
1876 struct ca0132_spec *spec = codec->spec;
1878 mutex_lock(&spec->chipio_mutex);
1879 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1880 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1881 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1882 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1883 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1884 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1885 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1886 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1887 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1888 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1889 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1890 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1891 mutex_unlock(&spec->chipio_mutex);
1895 * CA0132 DSP IO stuffs
1897 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1901 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1903 /* send bits of data specified by reg to dsp */
1905 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1906 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1909 } while (time_before(jiffies, timeout));
1915 * Wait for DSP to be ready for commands
1917 static void dspio_write_wait(struct hda_codec *codec)
1920 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1923 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1924 VENDOR_DSPIO_STATUS, 0);
1925 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1926 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1929 } while (time_before(jiffies, timeout));
1933 * Write SCP data to DSP
1935 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1937 struct ca0132_spec *spec = codec->spec;
1940 dspio_write_wait(codec);
1942 mutex_lock(&spec->chipio_mutex);
1943 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1948 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1953 /* OK, now check if the write itself has executed*/
1954 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1955 VENDOR_DSPIO_STATUS, 0);
1957 mutex_unlock(&spec->chipio_mutex);
1959 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1964 * Write multiple SCP data to DSP
1966 static int dspio_write_multiple(struct hda_codec *codec,
1967 unsigned int *buffer, unsigned int size)
1976 while (count < size) {
1977 status = dspio_write(codec, *buffer++);
1986 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1990 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1994 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1995 if (status == -EIO ||
1996 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1999 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2000 VENDOR_DSPIO_SCP_READ_DATA, 0);
2005 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2006 unsigned int *buf_size, unsigned int size_count)
2009 unsigned int size = *buf_size;
2011 unsigned int skip_count;
2018 while (count < size && count < size_count) {
2019 status = dspio_read(codec, buffer++);
2027 while (skip_count < size) {
2028 status = dspio_read(codec, &dummy);
2040 * Construct the SCP header using corresponding fields
2042 static inline unsigned int
2043 make_scp_header(unsigned int target_id, unsigned int source_id,
2044 unsigned int get_flag, unsigned int req,
2045 unsigned int device_flag, unsigned int resp_flag,
2046 unsigned int error_flag, unsigned int data_size)
2048 unsigned int header = 0;
2050 header = (data_size & 0x1f) << 27;
2051 header |= (error_flag & 0x01) << 26;
2052 header |= (resp_flag & 0x01) << 25;
2053 header |= (device_flag & 0x01) << 24;
2054 header |= (req & 0x7f) << 17;
2055 header |= (get_flag & 0x01) << 16;
2056 header |= (source_id & 0xff) << 8;
2057 header |= target_id & 0xff;
2063 * Extract corresponding fields from SCP header
2066 extract_scp_header(unsigned int header,
2067 unsigned int *target_id, unsigned int *source_id,
2068 unsigned int *get_flag, unsigned int *req,
2069 unsigned int *device_flag, unsigned int *resp_flag,
2070 unsigned int *error_flag, unsigned int *data_size)
2073 *data_size = (header >> 27) & 0x1f;
2075 *error_flag = (header >> 26) & 0x01;
2077 *resp_flag = (header >> 25) & 0x01;
2079 *device_flag = (header >> 24) & 0x01;
2081 *req = (header >> 17) & 0x7f;
2083 *get_flag = (header >> 16) & 0x01;
2085 *source_id = (header >> 8) & 0xff;
2087 *target_id = header & 0xff;
2090 #define SCP_MAX_DATA_WORDS (16)
2092 /* Structure to contain any SCP message */
2095 unsigned int data[SCP_MAX_DATA_WORDS];
2098 static void dspio_clear_response_queue(struct hda_codec *codec)
2100 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2101 unsigned int dummy = 0;
2104 /* clear all from the response queue */
2106 status = dspio_read(codec, &dummy);
2107 } while (status == 0 && time_before(jiffies, timeout));
2110 static int dspio_get_response_data(struct hda_codec *codec)
2112 struct ca0132_spec *spec = codec->spec;
2113 unsigned int data = 0;
2116 if (dspio_read(codec, &data) < 0)
2119 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2120 spec->scp_resp_header = data;
2121 spec->scp_resp_count = data >> 27;
2122 count = spec->wait_num_data;
2123 dspio_read_multiple(codec, spec->scp_resp_data,
2124 &spec->scp_resp_count, count);
2132 * Send SCP message to DSP
2134 static int dspio_send_scp_message(struct hda_codec *codec,
2135 unsigned char *send_buf,
2136 unsigned int send_buf_size,
2137 unsigned char *return_buf,
2138 unsigned int return_buf_size,
2139 unsigned int *bytes_returned)
2141 struct ca0132_spec *spec = codec->spec;
2143 unsigned int scp_send_size = 0;
2144 unsigned int total_size;
2145 bool waiting_for_resp = false;
2146 unsigned int header;
2147 struct scp_msg *ret_msg;
2148 unsigned int resp_src_id, resp_target_id;
2149 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2152 *bytes_returned = 0;
2154 /* get scp header from buffer */
2155 header = *((unsigned int *)send_buf);
2156 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2157 &device_flag, NULL, NULL, &data_size);
2158 scp_send_size = data_size + 1;
2159 total_size = (scp_send_size * 4);
2161 if (send_buf_size < total_size)
2164 if (get_flag || device_flag) {
2165 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2168 spec->wait_scp_header = *((unsigned int *)send_buf);
2170 /* swap source id with target id */
2171 resp_target_id = src_id;
2172 resp_src_id = target_id;
2173 spec->wait_scp_header &= 0xffff0000;
2174 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2175 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2177 waiting_for_resp = true;
2180 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2187 if (waiting_for_resp) {
2188 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2189 memset(return_buf, 0, return_buf_size);
2192 } while (spec->wait_scp && time_before(jiffies, timeout));
2193 waiting_for_resp = false;
2194 if (!spec->wait_scp) {
2195 ret_msg = (struct scp_msg *)return_buf;
2196 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2197 memcpy(&ret_msg->data, spec->scp_resp_data,
2198 spec->wait_num_data);
2199 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2211 * Prepare and send the SCP message to DSP
2212 * @codec: the HDA codec
2213 * @mod_id: ID of the DSP module to send the command
2214 * @src_id: ID of the source
2215 * @req: ID of request to send to the DSP module
2217 * @data: pointer to the data to send with the request, request specific
2218 * @len: length of the data, in bytes
2219 * @reply: point to the buffer to hold data returned for a reply
2220 * @reply_len: length of the reply buffer returned from GET
2222 * Returns zero or a negative error code.
2224 static int dspio_scp(struct hda_codec *codec,
2225 int mod_id, int src_id, int req, int dir, const void *data,
2226 unsigned int len, void *reply, unsigned int *reply_len)
2229 struct scp_msg scp_send, scp_reply;
2230 unsigned int ret_bytes, send_size, ret_size;
2231 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2232 unsigned int reply_data_size;
2234 memset(&scp_send, 0, sizeof(scp_send));
2235 memset(&scp_reply, 0, sizeof(scp_reply));
2237 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2240 if (dir == SCP_GET && reply == NULL) {
2241 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2245 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2246 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2250 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2251 0, 0, 0, len/sizeof(unsigned int));
2252 if (data != NULL && len > 0) {
2253 len = min((unsigned int)(sizeof(scp_send.data)), len);
2254 memcpy(scp_send.data, data, len);
2258 send_size = sizeof(unsigned int) + len;
2259 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2260 send_size, (unsigned char *)&scp_reply,
2261 sizeof(scp_reply), &ret_bytes);
2264 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2268 /* extract send and reply headers members */
2269 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2270 NULL, NULL, NULL, NULL, NULL);
2271 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2272 &reply_resp_flag, &reply_error_flag,
2278 if (reply_resp_flag && !reply_error_flag) {
2279 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2280 / sizeof(unsigned int);
2282 if (*reply_len < ret_size*sizeof(unsigned int)) {
2283 codec_dbg(codec, "reply too long for buf\n");
2285 } else if (ret_size != reply_data_size) {
2286 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2288 } else if (!reply) {
2289 codec_dbg(codec, "NULL reply\n");
2292 *reply_len = ret_size*sizeof(unsigned int);
2293 memcpy(reply, scp_reply.data, *reply_len);
2296 codec_dbg(codec, "reply ill-formed or errflag set\n");
2304 * Set DSP parameters
2306 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2307 int src_id, int req, const void *data, unsigned int len)
2309 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2313 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2314 int req, const unsigned int data)
2316 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2317 sizeof(unsigned int));
2320 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2321 int req, const unsigned int data)
2323 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2324 sizeof(unsigned int));
2328 * Allocate a DSP DMA channel via an SCP message
2330 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2333 unsigned int size = sizeof(*dma_chan);
2335 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2336 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2337 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2341 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2345 if ((*dma_chan + 1) == 0) {
2346 codec_dbg(codec, "no free dma channels to allocate\n");
2350 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2351 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2357 * Free a DSP DMA via an SCP message
2359 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2362 unsigned int dummy = 0;
2364 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2365 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2367 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2368 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2369 sizeof(dma_chan), NULL, &dummy);
2372 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2376 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2384 static int dsp_set_run_state(struct hda_codec *codec)
2386 unsigned int dbg_ctrl_reg;
2387 unsigned int halt_state;
2390 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2394 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2395 DSP_DBGCNTL_STATE_LOBIT;
2397 if (halt_state != 0) {
2398 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2399 DSP_DBGCNTL_SS_MASK);
2400 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2405 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2406 DSP_DBGCNTL_EXEC_MASK;
2407 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2419 static int dsp_reset(struct hda_codec *codec)
2424 codec_dbg(codec, "dsp_reset\n");
2426 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2428 } while (res == -EIO && retry);
2431 codec_dbg(codec, "dsp_reset timeout\n");
2439 * Convert chip address to DSP address
2441 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2442 bool *code, bool *yram)
2444 *code = *yram = false;
2446 if (UC_RANGE(chip_addx, 1)) {
2448 return UC_OFF(chip_addx);
2449 } else if (X_RANGE_ALL(chip_addx, 1)) {
2450 return X_OFF(chip_addx);
2451 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2453 return Y_OFF(chip_addx);
2456 return INVALID_CHIP_ADDRESS;
2460 * Check if the DSP DMA is active
2462 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2464 unsigned int dma_chnlstart_reg;
2466 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2468 return ((dma_chnlstart_reg & (1 <<
2469 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2472 static int dsp_dma_setup_common(struct hda_codec *codec,
2473 unsigned int chip_addx,
2474 unsigned int dma_chan,
2475 unsigned int port_map_mask,
2479 unsigned int chnl_prop;
2480 unsigned int dsp_addx;
2481 unsigned int active;
2484 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2486 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2487 codec_dbg(codec, "dma chan num invalid\n");
2491 if (dsp_is_dma_active(codec, dma_chan)) {
2492 codec_dbg(codec, "dma already active\n");
2496 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2498 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2499 codec_dbg(codec, "invalid chip addr\n");
2503 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2506 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2509 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2513 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2516 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2520 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2522 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2524 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2526 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2528 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2531 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2534 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2538 codec_dbg(codec, "read ACTIVE Reg fail\n");
2541 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2544 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2545 DSPDMAC_ACTIVE_AAR_MASK;
2547 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2549 codec_dbg(codec, "write ACTIVE Reg fail\n");
2553 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2555 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2558 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2561 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2563 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2564 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2566 codec_dbg(codec, "write IRQCNT Reg fail\n");
2569 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2572 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2573 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2574 chip_addx, dsp_addx, dma_chan,
2575 port_map_mask, chnl_prop, active);
2577 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2583 * Setup the DSP DMA per-transfer-specific registers
2585 static int dsp_dma_setup(struct hda_codec *codec,
2586 unsigned int chip_addx,
2588 unsigned int dma_chan)
2592 unsigned int dsp_addx;
2593 unsigned int addr_field;
2594 unsigned int incr_field;
2595 unsigned int base_cnt;
2596 unsigned int cur_cnt;
2597 unsigned int dma_cfg = 0;
2598 unsigned int adr_ofs = 0;
2599 unsigned int xfr_cnt = 0;
2600 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2601 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2603 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2605 if (count > max_dma_count) {
2606 codec_dbg(codec, "count too big\n");
2610 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2611 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2612 codec_dbg(codec, "invalid chip addr\n");
2616 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2618 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2624 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2626 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2629 dma_cfg = addr_field + incr_field;
2630 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2633 codec_dbg(codec, "write DMACFG Reg fail\n");
2636 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2638 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2641 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2644 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2647 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2649 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2651 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2653 xfr_cnt = base_cnt | cur_cnt;
2655 status = chipio_write(codec,
2656 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2658 codec_dbg(codec, "write XFRCNT Reg fail\n");
2661 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2664 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2665 "ADROFS=0x%x, XFRCNT=0x%x\n",
2666 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2668 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2676 static int dsp_dma_start(struct hda_codec *codec,
2677 unsigned int dma_chan, bool ovly)
2679 unsigned int reg = 0;
2682 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2685 status = chipio_read(codec,
2686 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2689 codec_dbg(codec, "read CHNLSTART reg fail\n");
2692 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2694 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2695 DSPDMAC_CHNLSTART_DIS_MASK);
2698 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2699 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2701 codec_dbg(codec, "write CHNLSTART reg fail\n");
2704 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2712 static int dsp_dma_stop(struct hda_codec *codec,
2713 unsigned int dma_chan, bool ovly)
2715 unsigned int reg = 0;
2718 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2721 status = chipio_read(codec,
2722 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2725 codec_dbg(codec, "read CHNLSTART reg fail\n");
2728 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2729 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2730 DSPDMAC_CHNLSTART_DIS_MASK);
2733 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2734 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2736 codec_dbg(codec, "write CHNLSTART reg fail\n");
2739 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2745 * Allocate router ports
2747 * @codec: the HDA codec
2748 * @num_chans: number of channels in the stream
2749 * @ports_per_channel: number of ports per channel
2750 * @start_device: start device
2751 * @port_map: pointer to the port list to hold the allocated ports
2753 * Returns zero or a negative error code.
2755 static int dsp_allocate_router_ports(struct hda_codec *codec,
2756 unsigned int num_chans,
2757 unsigned int ports_per_channel,
2758 unsigned int start_device,
2759 unsigned int *port_map)
2765 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2769 val = start_device << 6;
2770 val |= (ports_per_channel - 1) << 4;
2771 val |= num_chans - 1;
2773 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2774 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2777 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2778 VENDOR_CHIPIO_PORT_ALLOC_SET,
2781 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2785 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2786 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2790 return (res < 0) ? res : 0;
2796 static int dsp_free_router_ports(struct hda_codec *codec)
2800 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2804 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2805 VENDOR_CHIPIO_PORT_FREE_SET,
2808 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2814 * Allocate DSP ports for the download stream
2816 static int dsp_allocate_ports(struct hda_codec *codec,
2817 unsigned int num_chans,
2818 unsigned int rate_multi, unsigned int *port_map)
2822 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2824 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2825 codec_dbg(codec, "bad rate multiple\n");
2829 status = dsp_allocate_router_ports(codec, num_chans,
2830 rate_multi, 0, port_map);
2832 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2837 static int dsp_allocate_ports_format(struct hda_codec *codec,
2838 const unsigned short fmt,
2839 unsigned int *port_map)
2842 unsigned int num_chans;
2844 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2845 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2846 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2848 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2849 codec_dbg(codec, "bad rate multiple\n");
2853 num_chans = get_hdafmt_chs(fmt) + 1;
2855 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2863 static int dsp_free_ports(struct hda_codec *codec)
2867 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2869 status = dsp_free_router_ports(codec);
2871 codec_dbg(codec, "free router ports fail\n");
2874 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2880 * HDA DMA engine stuffs for DSP code download
2883 struct hda_codec *codec;
2884 unsigned short m_converter_format;
2885 struct snd_dma_buffer *dmab;
2886 unsigned int buf_size;
2895 static int dma_convert_to_hda_format(struct hda_codec *codec,
2896 unsigned int sample_rate,
2897 unsigned short channels,
2898 unsigned short *hda_format)
2900 unsigned int format_val;
2902 format_val = snd_hdac_calc_stream_format(sample_rate,
2903 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2906 *hda_format = (unsigned short)format_val;
2912 * Reset DMA for DSP download
2914 static int dma_reset(struct dma_engine *dma)
2916 struct hda_codec *codec = dma->codec;
2917 struct ca0132_spec *spec = codec->spec;
2920 if (dma->dmab->area)
2921 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2923 status = snd_hda_codec_load_dsp_prepare(codec,
2924 dma->m_converter_format,
2929 spec->dsp_stream_id = status;
2933 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2938 case DMA_STATE_STOP:
2948 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2952 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2954 return dma->dmab->bytes;
2957 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2959 return dma->dmab->area;
2962 static int dma_xfer(struct dma_engine *dma,
2963 const unsigned int *data,
2966 memcpy(dma->dmab->area, data, count);
2970 static void dma_get_converter_format(
2971 struct dma_engine *dma,
2972 unsigned short *format)
2975 *format = dma->m_converter_format;
2978 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2980 struct ca0132_spec *spec = dma->codec->spec;
2982 return spec->dsp_stream_id;
2985 struct dsp_image_seg {
2992 static const u32 g_magic_value = 0x4c46584d;
2993 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2995 static bool is_valid(const struct dsp_image_seg *p)
2997 return p->magic == g_magic_value;
3000 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3002 return g_chip_addr_magic_value == p->chip_addr;
3005 static bool is_last(const struct dsp_image_seg *p)
3007 return p->count == 0;
3010 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3012 return struct_size(p, data, p->count);
3015 static const struct dsp_image_seg *get_next_seg_ptr(
3016 const struct dsp_image_seg *p)
3018 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3022 * CA0132 chip DSP transfer stuffs. For DSP download.
3024 #define INVALID_DMA_CHANNEL (~0U)
3027 * Program a list of address/data pairs via the ChipIO widget.
3028 * The segment data is in the format of successive pairs of words.
3029 * These are repeated as indicated by the segment's count field.
3031 static int dspxfr_hci_write(struct hda_codec *codec,
3032 const struct dsp_image_seg *fls)
3038 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3039 codec_dbg(codec, "hci_write invalid params\n");
3044 data = (u32 *)(fls->data);
3045 while (count >= 2) {
3046 status = chipio_write(codec, data[0], data[1]);
3048 codec_dbg(codec, "hci_write chipio failed\n");
3058 * Write a block of data into DSP code or data RAM using pre-allocated
3061 * @codec: the HDA codec
3062 * @fls: pointer to a fast load image
3063 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3065 * @dma_engine: pointer to DMA engine to be used for DSP download
3066 * @dma_chan: The number of DMA channels used for DSP download
3067 * @port_map_mask: port mapping
3068 * @ovly: TRUE if overlay format is required
3070 * Returns zero or a negative error code.
3072 static int dspxfr_one_seg(struct hda_codec *codec,
3073 const struct dsp_image_seg *fls,
3075 struct dma_engine *dma_engine,
3076 unsigned int dma_chan,
3077 unsigned int port_map_mask,
3081 bool comm_dma_setup_done = false;
3082 const unsigned int *data;
3083 unsigned int chip_addx;
3084 unsigned int words_to_write;
3085 unsigned int buffer_size_words;
3086 unsigned char *buffer_addx;
3087 unsigned short hda_format;
3088 unsigned int sample_rate_div;
3089 unsigned int sample_rate_mul;
3090 unsigned int num_chans;
3091 unsigned int hda_frame_size_words;
3092 unsigned int remainder_words;
3093 const u32 *data_remainder;
3094 u32 chip_addx_remainder;
3095 unsigned int run_size_words;
3096 const struct dsp_image_seg *hci_write = NULL;
3097 unsigned long timeout;
3102 if (is_hci_prog_list_seg(fls)) {
3104 fls = get_next_seg_ptr(fls);
3107 if (hci_write && (!fls || is_last(fls))) {
3108 codec_dbg(codec, "hci_write\n");
3109 return dspxfr_hci_write(codec, hci_write);
3112 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3113 codec_dbg(codec, "Invalid Params\n");
3118 chip_addx = fls->chip_addr;
3119 words_to_write = fls->count;
3121 if (!words_to_write)
3122 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3124 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3126 if (!UC_RANGE(chip_addx, words_to_write) &&
3127 !X_RANGE_ALL(chip_addx, words_to_write) &&
3128 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3129 codec_dbg(codec, "Invalid chip_addx Params\n");
3133 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3136 buffer_addx = dma_get_buffer_addr(dma_engine);
3138 if (buffer_addx == NULL) {
3139 codec_dbg(codec, "dma_engine buffer NULL\n");
3143 dma_get_converter_format(dma_engine, &hda_format);
3144 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3145 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3146 num_chans = get_hdafmt_chs(hda_format) + 1;
3148 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3149 (num_chans * sample_rate_mul / sample_rate_div));
3151 if (hda_frame_size_words == 0) {
3152 codec_dbg(codec, "frmsz zero\n");
3156 buffer_size_words = min(buffer_size_words,
3157 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3159 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3161 "chpadr=0x%08x frmsz=%u nchan=%u "
3162 "rate_mul=%u div=%u bufsz=%u\n",
3163 chip_addx, hda_frame_size_words, num_chans,
3164 sample_rate_mul, sample_rate_div, buffer_size_words);
3166 if (buffer_size_words < hda_frame_size_words) {
3167 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3171 remainder_words = words_to_write % hda_frame_size_words;
3172 data_remainder = data;
3173 chip_addx_remainder = chip_addx;
3175 data += remainder_words;
3176 chip_addx += remainder_words*sizeof(u32);
3177 words_to_write -= remainder_words;
3179 while (words_to_write != 0) {
3180 run_size_words = min(buffer_size_words, words_to_write);
3181 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3182 words_to_write, run_size_words, remainder_words);
3183 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3184 if (!comm_dma_setup_done) {
3185 status = dsp_dma_stop(codec, dma_chan, ovly);
3188 status = dsp_dma_setup_common(codec, chip_addx,
3189 dma_chan, port_map_mask, ovly);
3192 comm_dma_setup_done = true;
3195 status = dsp_dma_setup(codec, chip_addx,
3196 run_size_words, dma_chan);
3199 status = dsp_dma_start(codec, dma_chan, ovly);
3202 if (!dsp_is_dma_active(codec, dma_chan)) {
3203 codec_dbg(codec, "dspxfr:DMA did not start\n");
3206 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3209 if (remainder_words != 0) {
3210 status = chipio_write_multiple(codec,
3211 chip_addx_remainder,
3216 remainder_words = 0;
3219 status = dspxfr_hci_write(codec, hci_write);
3225 timeout = jiffies + msecs_to_jiffies(2000);
3227 dma_active = dsp_is_dma_active(codec, dma_chan);
3231 } while (time_before(jiffies, timeout));
3235 codec_dbg(codec, "+++++ DMA complete\n");
3236 dma_set_state(dma_engine, DMA_STATE_STOP);
3237 status = dma_reset(dma_engine);
3242 data += run_size_words;
3243 chip_addx += run_size_words*sizeof(u32);
3244 words_to_write -= run_size_words;
3247 if (remainder_words != 0) {
3248 status = chipio_write_multiple(codec, chip_addx_remainder,
3249 data_remainder, remainder_words);
3256 * Write the entire DSP image of a DSP code/data overlay to DSP memories
3258 * @codec: the HDA codec
3259 * @fls_data: pointer to a fast load image
3260 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3262 * @sample_rate: sampling rate of the stream used for DSP download
3263 * @channels: channels of the stream used for DSP download
3264 * @ovly: TRUE if overlay format is required
3266 * Returns zero or a negative error code.
3268 static int dspxfr_image(struct hda_codec *codec,
3269 const struct dsp_image_seg *fls_data,
3271 unsigned int sample_rate,
3272 unsigned short channels,
3275 struct ca0132_spec *spec = codec->spec;
3277 unsigned short hda_format = 0;
3278 unsigned int response;
3279 unsigned char stream_id = 0;
3280 struct dma_engine *dma_engine;
3281 unsigned int dma_chan;
3282 unsigned int port_map_mask;
3284 if (fls_data == NULL)
3287 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3291 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3292 if (!dma_engine->dmab) {
3297 dma_engine->codec = codec;
3298 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3299 dma_engine->m_converter_format = hda_format;
3300 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3301 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3303 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3305 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3306 hda_format, &response);
3309 codec_dbg(codec, "set converter format fail\n");
3313 status = snd_hda_codec_load_dsp_prepare(codec,
3314 dma_engine->m_converter_format,
3315 dma_engine->buf_size,
3319 spec->dsp_stream_id = status;
3322 status = dspio_alloc_dma_chan(codec, &dma_chan);
3324 codec_dbg(codec, "alloc dmachan fail\n");
3325 dma_chan = INVALID_DMA_CHANNEL;
3331 status = dsp_allocate_ports_format(codec, hda_format,
3334 codec_dbg(codec, "alloc ports fail\n");
3338 stream_id = dma_get_stream_id(dma_engine);
3339 status = codec_set_converter_stream_channel(codec,
3340 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3342 codec_dbg(codec, "set stream chan fail\n");
3346 while ((fls_data != NULL) && !is_last(fls_data)) {
3347 if (!is_valid(fls_data)) {
3348 codec_dbg(codec, "FLS check fail\n");
3352 status = dspxfr_one_seg(codec, fls_data, reloc,
3353 dma_engine, dma_chan,
3354 port_map_mask, ovly);
3358 if (is_hci_prog_list_seg(fls_data))
3359 fls_data = get_next_seg_ptr(fls_data);
3361 if ((fls_data != NULL) && !is_last(fls_data))
3362 fls_data = get_next_seg_ptr(fls_data);
3365 if (port_map_mask != 0)
3366 status = dsp_free_ports(codec);
3371 status = codec_set_converter_stream_channel(codec,
3372 WIDGET_CHIP_CTRL, 0, 0, &response);
3375 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3376 dspio_free_dma_chan(codec, dma_chan);
3378 if (dma_engine->dmab->area)
3379 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3380 kfree(dma_engine->dmab);
3387 * CA0132 DSP download stuffs.
3389 static void dspload_post_setup(struct hda_codec *codec)
3391 struct ca0132_spec *spec = codec->spec;
3392 codec_dbg(codec, "---- dspload_post_setup ------\n");
3393 if (!ca0132_use_alt_functions(spec)) {
3394 /*set DSP speaker to 2.0 configuration*/
3395 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3396 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3398 /*update write pointer*/
3399 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3404 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3406 * @codec: the HDA codec
3407 * @fls: pointer to a fast load image
3408 * @ovly: TRUE if overlay format is required
3409 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3411 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3412 * @router_chans: number of audio router channels to be allocated (0 means use
3413 * internal defaults; max is 32)
3415 * Download DSP from a DSP Image Fast Load structure. This structure is a
3416 * linear, non-constant sized element array of structures, each of which
3417 * contain the count of the data to be loaded, the data itself, and the
3418 * corresponding starting chip address of the starting data location.
3419 * Returns zero or a negative error code.
3421 static int dspload_image(struct hda_codec *codec,
3422 const struct dsp_image_seg *fls,
3429 unsigned int sample_rate;
3430 unsigned short channels;
3432 codec_dbg(codec, "---- dspload_image begin ------\n");
3433 if (router_chans == 0) {
3435 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3437 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3440 sample_rate = 48000;
3441 channels = (unsigned short)router_chans;
3443 while (channels > 16) {
3449 codec_dbg(codec, "Ready to program DMA\n");
3451 status = dsp_reset(codec);
3456 codec_dbg(codec, "dsp_reset() complete\n");
3457 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3463 codec_dbg(codec, "dspxfr_image() complete\n");
3464 if (autostart && !ovly) {
3465 dspload_post_setup(codec);
3466 status = dsp_set_run_state(codec);
3469 codec_dbg(codec, "LOAD FINISHED\n");
3475 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3476 static bool dspload_is_loaded(struct hda_codec *codec)
3478 unsigned int data = 0;
3481 status = chipio_read(codec, 0x40004, &data);
3482 if ((status < 0) || (data != 1))
3488 #define dspload_is_loaded(codec) false
3491 static bool dspload_wait_loaded(struct hda_codec *codec)
3493 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3496 if (dspload_is_loaded(codec)) {
3497 codec_info(codec, "ca0132 DSP downloaded and running\n");
3501 } while (time_before(jiffies, timeout));
3503 codec_err(codec, "ca0132 failed to download DSP\n");
3508 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3509 * based cards, and has a second mmio region, region2, that's used for special
3514 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3515 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3516 * The first eight bits are just the number of the pin. So far, I've only seen
3517 * this number go to 7.
3518 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3519 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3520 * then off to send that bit.
3522 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3525 struct ca0132_spec *spec = codec->spec;
3526 unsigned short gpio_data;
3528 gpio_data = gpio_pin & 0xF;
3529 gpio_data |= ((enable << 8) & 0x100);
3531 writew(gpio_data, spec->mem_base + 0x320);
3535 * Special pci region2 commands that are only used by the AE-5. They follow
3536 * a set format, and require reads at certain points to seemingly 'clear'
3537 * the response data. My first tests didn't do these reads, and would cause
3538 * the card to get locked up until the memory was read. These commands
3539 * seem to work with three distinct values that I've taken to calling group,
3540 * target-id, and value.
3542 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3543 unsigned int target, unsigned int value)
3545 struct ca0132_spec *spec = codec->spec;
3546 unsigned int write_val;
3548 writel(0x0000007e, spec->mem_base + 0x210);
3549 readl(spec->mem_base + 0x210);
3550 writel(0x0000005a, spec->mem_base + 0x210);
3551 readl(spec->mem_base + 0x210);
3552 readl(spec->mem_base + 0x210);
3554 writel(0x00800005, spec->mem_base + 0x20c);
3555 writel(group, spec->mem_base + 0x804);
3557 writel(0x00800005, spec->mem_base + 0x20c);
3558 write_val = (target & 0xff);
3559 write_val |= (value << 8);
3562 writel(write_val, spec->mem_base + 0x204);
3564 * Need delay here or else it goes too fast and works inconsistently.
3568 readl(spec->mem_base + 0x860);
3569 readl(spec->mem_base + 0x854);
3570 readl(spec->mem_base + 0x840);
3572 writel(0x00800004, spec->mem_base + 0x20c);
3573 writel(0x00000000, spec->mem_base + 0x210);
3574 readl(spec->mem_base + 0x210);
3575 readl(spec->mem_base + 0x210);
3579 * This second type of command is used for setting the sound filter type.
3581 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3582 unsigned int group, unsigned int target, unsigned int value)
3584 struct ca0132_spec *spec = codec->spec;
3585 unsigned int write_val;
3587 writel(0x0000007e, spec->mem_base + 0x210);
3588 readl(spec->mem_base + 0x210);
3589 writel(0x0000005a, spec->mem_base + 0x210);
3590 readl(spec->mem_base + 0x210);
3591 readl(spec->mem_base + 0x210);
3593 writel(0x00800003, spec->mem_base + 0x20c);
3594 writel(group, spec->mem_base + 0x804);
3596 writel(0x00800005, spec->mem_base + 0x20c);
3597 write_val = (target & 0xff);
3598 write_val |= (value << 8);
3601 writel(write_val, spec->mem_base + 0x204);
3603 readl(spec->mem_base + 0x860);
3604 readl(spec->mem_base + 0x854);
3605 readl(spec->mem_base + 0x840);
3607 writel(0x00800004, spec->mem_base + 0x20c);
3608 writel(0x00000000, spec->mem_base + 0x210);
3609 readl(spec->mem_base + 0x210);
3610 readl(spec->mem_base + 0x210);
3614 * Setup GPIO for the other variants of Core3D.
3618 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3619 * the card shows as having no GPIO pins.
3621 static void ca0132_gpio_init(struct hda_codec *codec)
3623 struct ca0132_spec *spec = codec->spec;
3625 switch (ca0132_quirk(spec)) {
3629 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3630 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3631 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3634 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3635 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3643 /* Sets the GPIO for audio output. */
3644 static void ca0132_gpio_setup(struct hda_codec *codec)
3646 struct ca0132_spec *spec = codec->spec;
3648 switch (ca0132_quirk(spec)) {
3650 snd_hda_codec_write(codec, 0x01, 0,
3651 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3652 snd_hda_codec_write(codec, 0x01, 0,
3653 AC_VERB_SET_GPIO_MASK, 0x07);
3654 snd_hda_codec_write(codec, 0x01, 0,
3655 AC_VERB_SET_GPIO_DATA, 0x04);
3656 snd_hda_codec_write(codec, 0x01, 0,
3657 AC_VERB_SET_GPIO_DATA, 0x06);
3660 snd_hda_codec_write(codec, 0x01, 0,
3661 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3662 snd_hda_codec_write(codec, 0x01, 0,
3663 AC_VERB_SET_GPIO_MASK, 0x1F);
3664 snd_hda_codec_write(codec, 0x01, 0,
3665 AC_VERB_SET_GPIO_DATA, 0x0C);
3673 * GPIO control functions for the Recon3D integrated.
3676 enum r3di_gpio_bit {
3677 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3678 R3DI_MIC_SELECT_BIT = 1,
3679 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3680 R3DI_OUT_SELECT_BIT = 2,
3682 * I dunno what this actually does, but it stays on until the dsp
3685 R3DI_GPIO_DSP_DOWNLOADING = 3,
3687 * Same as above, no clue what it does, but it comes on after the dsp
3690 R3DI_GPIO_DSP_DOWNLOADED = 4
3693 enum r3di_mic_select {
3694 /* Set GPIO bit 1 to 0 for rear mic */
3696 /* Set GPIO bit 1 to 1 for front microphone*/
3700 enum r3di_out_select {
3701 /* Set GPIO bit 2 to 0 for headphone */
3702 R3DI_HEADPHONE_OUT = 0,
3703 /* Set GPIO bit 2 to 1 for speaker */
3706 enum r3di_dsp_status {
3707 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3708 R3DI_DSP_DOWNLOADING = 0,
3709 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3710 R3DI_DSP_DOWNLOADED = 1
3714 static void r3di_gpio_mic_set(struct hda_codec *codec,
3715 enum r3di_mic_select cur_mic)
3717 unsigned int cur_gpio;
3719 /* Get the current GPIO Data setup */
3720 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3724 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3726 case R3DI_FRONT_MIC:
3727 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3730 snd_hda_codec_write(codec, codec->core.afg, 0,
3731 AC_VERB_SET_GPIO_DATA, cur_gpio);
3734 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3735 enum r3di_dsp_status dsp_status)
3737 unsigned int cur_gpio;
3739 /* Get the current GPIO Data setup */
3740 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3742 switch (dsp_status) {
3743 case R3DI_DSP_DOWNLOADING:
3744 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3745 snd_hda_codec_write(codec, codec->core.afg, 0,
3746 AC_VERB_SET_GPIO_DATA, cur_gpio);
3748 case R3DI_DSP_DOWNLOADED:
3749 /* Set DOWNLOADING bit to 0. */
3750 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3752 snd_hda_codec_write(codec, codec->core.afg, 0,
3753 AC_VERB_SET_GPIO_DATA, cur_gpio);
3755 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3759 snd_hda_codec_write(codec, codec->core.afg, 0,
3760 AC_VERB_SET_GPIO_DATA, cur_gpio);
3766 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3767 struct hda_codec *codec,
3768 unsigned int stream_tag,
3769 unsigned int format,
3770 struct snd_pcm_substream *substream)
3772 struct ca0132_spec *spec = codec->spec;
3774 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3779 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3780 struct hda_codec *codec,
3781 struct snd_pcm_substream *substream)
3783 struct ca0132_spec *spec = codec->spec;
3785 if (spec->dsp_state == DSP_DOWNLOADING)
3788 /*If Playback effects are on, allow stream some time to flush
3790 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3793 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3798 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3799 struct hda_codec *codec,
3800 struct snd_pcm_substream *substream)
3802 struct ca0132_spec *spec = codec->spec;
3803 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3804 struct snd_pcm_runtime *runtime = substream->runtime;
3806 if (spec->dsp_state != DSP_DOWNLOADED)
3809 /* Add latency if playback enhancement and either effect is enabled. */
3810 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3811 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3812 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3813 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3816 /* Applying Speaker EQ adds latency as well. */
3817 if (spec->cur_out_type == SPEAKER_OUT)
3818 latency += DSP_SPEAKER_OUT_LATENCY;
3820 return (latency * runtime->rate) / 1000;
3826 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3827 struct hda_codec *codec,
3828 struct snd_pcm_substream *substream)
3830 struct ca0132_spec *spec = codec->spec;
3831 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3834 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3835 struct hda_codec *codec,
3836 unsigned int stream_tag,
3837 unsigned int format,
3838 struct snd_pcm_substream *substream)
3840 struct ca0132_spec *spec = codec->spec;
3841 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3842 stream_tag, format, substream);
3845 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3846 struct hda_codec *codec,
3847 struct snd_pcm_substream *substream)
3849 struct ca0132_spec *spec = codec->spec;
3850 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3853 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3854 struct hda_codec *codec,
3855 struct snd_pcm_substream *substream)
3857 struct ca0132_spec *spec = codec->spec;
3858 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3864 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3865 struct hda_codec *codec,
3866 unsigned int stream_tag,
3867 unsigned int format,
3868 struct snd_pcm_substream *substream)
3870 snd_hda_codec_setup_stream(codec, hinfo->nid,
3871 stream_tag, 0, format);
3876 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3877 struct hda_codec *codec,
3878 struct snd_pcm_substream *substream)
3880 struct ca0132_spec *spec = codec->spec;
3882 if (spec->dsp_state == DSP_DOWNLOADING)
3885 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3889 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3890 struct hda_codec *codec,
3891 struct snd_pcm_substream *substream)
3893 struct ca0132_spec *spec = codec->spec;
3894 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3895 struct snd_pcm_runtime *runtime = substream->runtime;
3897 if (spec->dsp_state != DSP_DOWNLOADED)
3900 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3901 latency += DSP_CRYSTAL_VOICE_LATENCY;
3903 return (latency * runtime->rate) / 1000;
3911 * Mixer controls helpers.
3913 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3914 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3916 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3917 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3918 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3919 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3920 .info = ca0132_volume_info, \
3921 .get = ca0132_volume_get, \
3922 .put = ca0132_volume_put, \
3923 .tlv = { .c = ca0132_volume_tlv }, \
3924 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3927 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3928 * volume put, which is used for setting the DSP volume. This was done because
3929 * the ca0132 functions were taking too much time and causing lag.
3931 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3932 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3934 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3935 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3936 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3937 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3938 .info = snd_hda_mixer_amp_volume_info, \
3939 .get = snd_hda_mixer_amp_volume_get, \
3940 .put = ca0132_alt_volume_put, \
3941 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3942 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3944 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3945 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3947 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3948 .info = snd_hda_mixer_amp_switch_info, \
3949 .get = ca0132_switch_get, \
3950 .put = ca0132_switch_put, \
3951 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3954 #define CA0132_CODEC_VOL(xname, nid, dir) \
3955 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3956 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3957 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3958 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3959 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3963 * Lookup table with decibel values for the DSP. When volume is changed in
3964 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3965 * these values have decimal points, probably because the Windows driver
3966 * actually uses floating point. We can't here, so I made a lookup table of
3967 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3968 * DAC's, and 9 is the maximum.
3970 static const unsigned int float_vol_db_lookup[] = {
3971 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3972 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3973 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3974 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3975 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3976 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3977 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3978 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3979 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3980 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3981 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3982 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3983 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3984 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3985 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3986 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3987 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3991 * This table counts from float 0 to 1 in increments of .01, which is
3992 * useful for a few different sliders.
3994 static const unsigned int float_zero_to_one_lookup[] = {
3995 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3996 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3997 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3998 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3999 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4000 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4001 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4002 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4003 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4004 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4005 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4006 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4007 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4008 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4009 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4010 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4011 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4015 * This table counts from float 10 to 1000, which is the range of the x-bass
4016 * crossover slider in Windows.
4018 static const unsigned int float_xbass_xover_lookup[] = {
4019 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4020 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4021 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4022 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4023 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4024 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4025 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4026 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4027 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4028 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4029 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4030 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4031 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4032 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4033 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4034 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4035 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4038 /* The following are for tuning of products */
4039 #ifdef ENABLE_TUNING_CONTROLS
4041 static const unsigned int voice_focus_vals_lookup[] = {
4042 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4043 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4044 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4045 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4046 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4047 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4048 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4049 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4050 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4051 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4052 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4053 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4054 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4055 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4056 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4057 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4058 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4059 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4060 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4061 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4062 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4063 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4064 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4065 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4066 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4067 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4068 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4071 static const unsigned int mic_svm_vals_lookup[] = {
4072 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4073 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4074 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4075 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4076 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4077 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4078 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4079 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4080 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4081 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4082 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4083 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4084 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4085 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4086 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4087 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4088 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4091 static const unsigned int equalizer_vals_lookup[] = {
4092 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4093 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4094 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4095 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4096 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4097 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4098 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4099 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4103 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4104 const unsigned int *lookup, int idx)
4108 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4109 if (nid == ca0132_tuning_ctls[i].nid)
4114 snd_hda_power_up(codec);
4115 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4116 ca0132_tuning_ctls[i].req,
4117 &(lookup[idx]), sizeof(unsigned int));
4118 snd_hda_power_down(codec);
4123 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4124 struct snd_ctl_elem_value *ucontrol)
4126 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4127 struct ca0132_spec *spec = codec->spec;
4128 hda_nid_t nid = get_amp_nid(kcontrol);
4129 long *valp = ucontrol->value.integer.value;
4130 int idx = nid - TUNING_CTL_START_NID;
4132 *valp = spec->cur_ctl_vals[idx];
4136 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4137 struct snd_ctl_elem_info *uinfo)
4139 int chs = get_amp_channels(kcontrol);
4140 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4141 uinfo->count = chs == 3 ? 2 : 1;
4142 uinfo->value.integer.min = 20;
4143 uinfo->value.integer.max = 180;
4144 uinfo->value.integer.step = 1;
4149 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4150 struct snd_ctl_elem_value *ucontrol)
4152 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4153 struct ca0132_spec *spec = codec->spec;
4154 hda_nid_t nid = get_amp_nid(kcontrol);
4155 long *valp = ucontrol->value.integer.value;
4158 idx = nid - TUNING_CTL_START_NID;
4160 if (spec->cur_ctl_vals[idx] == *valp)
4163 spec->cur_ctl_vals[idx] = *valp;
4166 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4171 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4172 struct snd_ctl_elem_info *uinfo)
4174 int chs = get_amp_channels(kcontrol);
4175 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4176 uinfo->count = chs == 3 ? 2 : 1;
4177 uinfo->value.integer.min = 0;
4178 uinfo->value.integer.max = 100;
4179 uinfo->value.integer.step = 1;
4184 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4185 struct snd_ctl_elem_value *ucontrol)
4187 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4188 struct ca0132_spec *spec = codec->spec;
4189 hda_nid_t nid = get_amp_nid(kcontrol);
4190 long *valp = ucontrol->value.integer.value;
4193 idx = nid - TUNING_CTL_START_NID;
4195 if (spec->cur_ctl_vals[idx] == *valp)
4198 spec->cur_ctl_vals[idx] = *valp;
4201 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4206 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4207 struct snd_ctl_elem_info *uinfo)
4209 int chs = get_amp_channels(kcontrol);
4210 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4211 uinfo->count = chs == 3 ? 2 : 1;
4212 uinfo->value.integer.min = 0;
4213 uinfo->value.integer.max = 48;
4214 uinfo->value.integer.step = 1;
4219 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4220 struct snd_ctl_elem_value *ucontrol)
4222 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4223 struct ca0132_spec *spec = codec->spec;
4224 hda_nid_t nid = get_amp_nid(kcontrol);
4225 long *valp = ucontrol->value.integer.value;
4228 idx = nid - TUNING_CTL_START_NID;
4230 if (spec->cur_ctl_vals[idx] == *valp)
4233 spec->cur_ctl_vals[idx] = *valp;
4236 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4241 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4242 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4244 static int add_tuning_control(struct hda_codec *codec,
4245 hda_nid_t pnid, hda_nid_t nid,
4246 const char *name, int dir)
4248 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4249 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4250 struct snd_kcontrol_new knew =
4251 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4253 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4254 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4259 knew.info = voice_focus_ctl_info;
4260 knew.get = tuning_ctl_get;
4261 knew.put = voice_focus_ctl_put;
4262 knew.tlv.p = voice_focus_db_scale;
4265 knew.info = mic_svm_ctl_info;
4266 knew.get = tuning_ctl_get;
4267 knew.put = mic_svm_ctl_put;
4270 knew.info = equalizer_ctl_info;
4271 knew.get = tuning_ctl_get;
4272 knew.put = equalizer_ctl_put;
4273 knew.tlv.p = eq_db_scale;
4278 knew.private_value =
4279 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4280 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4281 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4284 static int add_tuning_ctls(struct hda_codec *codec)
4289 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4290 err = add_tuning_control(codec,
4291 ca0132_tuning_ctls[i].parent_nid,
4292 ca0132_tuning_ctls[i].nid,
4293 ca0132_tuning_ctls[i].name,
4294 ca0132_tuning_ctls[i].direct);
4302 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4304 struct ca0132_spec *spec = codec->spec;
4307 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4308 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4309 /* SVM level defaults to 0.74. */
4310 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4312 /* EQ defaults to 0dB. */
4313 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4314 spec->cur_ctl_vals[i] = 24;
4316 #endif /*ENABLE_TUNING_CONTROLS*/
4319 * Select the active output.
4320 * If autodetect is enabled, output will be selected based on jack detection.
4321 * If jack inserted, headphone will be selected, else built-in speakers
4322 * If autodetect is disabled, output will be selected based on selection.
4324 static int ca0132_select_out(struct hda_codec *codec)
4326 struct ca0132_spec *spec = codec->spec;
4327 unsigned int pin_ctl;
4333 codec_dbg(codec, "ca0132_select_out\n");
4335 snd_hda_power_up_pm(codec);
4337 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4340 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4343 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4346 spec->cur_out_type = HEADPHONE_OUT;
4348 spec->cur_out_type = SPEAKER_OUT;
4350 if (spec->cur_out_type == SPEAKER_OUT) {
4351 codec_dbg(codec, "ca0132_select_out speaker\n");
4352 /*speaker out config*/
4354 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4357 /*enable speaker EQ*/
4359 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4364 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4365 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4366 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4367 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4368 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4369 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4370 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4371 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4373 /* disable headphone node */
4374 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4375 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4376 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4378 /* enable speaker node */
4379 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4380 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4381 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4384 codec_dbg(codec, "ca0132_select_out hp\n");
4385 /*headphone out config*/
4387 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4390 /*disable speaker EQ*/
4392 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4397 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4398 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4399 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4400 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4401 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4402 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4403 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4404 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4406 /* disable speaker*/
4407 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4408 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4409 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4411 /* enable headphone*/
4412 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4413 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4414 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4419 snd_hda_power_down_pm(codec);
4421 return err < 0 ? err : 0;
4424 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4425 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4426 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4428 static void ae5_mmio_select_out(struct hda_codec *codec)
4430 struct ca0132_spec *spec = codec->spec;
4431 const struct ae_ca0113_output_set *out_cmds;
4434 if (ca0132_quirk(spec) == QUIRK_AE5)
4435 out_cmds = &ae5_ca0113_output_presets;
4437 out_cmds = &ae7_ca0113_output_presets;
4439 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4440 ca0113_mmio_command_set(codec, out_cmds->group[i],
4441 out_cmds->target[i],
4442 out_cmds->vals[spec->cur_out_type][i]);
4445 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4447 struct ca0132_spec *spec = codec->spec;
4448 int quirk = ca0132_quirk(spec);
4452 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4453 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4454 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4457 /* Set front L/R full range. Zero for full-range, one for redirection. */
4458 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4459 err = dspio_set_uint_param(codec, 0x96,
4460 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4464 /* When setting full-range rear, both rear and center/lfe are set. */
4465 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4466 err = dspio_set_uint_param(codec, 0x96,
4467 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4471 err = dspio_set_uint_param(codec, 0x96,
4472 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4477 * Only the AE series cards set this value when setting full-range,
4478 * and it's always 1.0f.
4480 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4481 err = dspio_set_uint_param(codec, 0x96,
4482 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4490 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4493 struct ca0132_spec *spec = codec->spec;
4497 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4498 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4503 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4507 /* If it is enabled, make sure to set the crossover frequency. */
4509 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4510 err = dspio_set_uint_param(codec, 0x96,
4511 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4520 * These are the commands needed to setup output on each of the different card
4523 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4524 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4526 struct ca0132_spec *spec = codec->spec;
4527 int quirk = ca0132_quirk(spec);
4531 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4532 if (quirk_out_set_data[i].quirk_id == quirk) {
4533 *quirk_data = &quirk_out_set_data[i];
4539 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4541 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4542 const struct ca0132_alt_out_set_info *out_info;
4543 struct ca0132_spec *spec = codec->spec;
4544 unsigned int i, gpio_data;
4547 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4551 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4552 if (quirk_data->is_ae_series)
4553 ae5_mmio_select_out(codec);
4555 if (out_info->has_hda_gpio) {
4556 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4557 AC_VERB_GET_GPIO_DATA, 0);
4559 if (out_info->hda_gpio_set)
4560 gpio_data |= (1 << out_info->hda_gpio_pin);
4562 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4564 snd_hda_codec_write(codec, codec->core.afg, 0,
4565 AC_VERB_SET_GPIO_DATA, gpio_data);
4568 if (out_info->mmio_gpio_count) {
4569 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4570 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4571 out_info->mmio_gpio_set[i]);
4575 if (out_info->scp_cmds_count) {
4576 for (i = 0; i < out_info->scp_cmds_count; i++) {
4577 err = dspio_set_uint_param(codec,
4578 out_info->scp_cmd_mid[i],
4579 out_info->scp_cmd_req[i],
4580 out_info->scp_cmd_val[i]);
4586 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4588 if (out_info->has_chipio_write) {
4589 chipio_write(codec, out_info->chipio_write_addr,
4590 out_info->chipio_write_data);
4593 if (quirk_data->has_headphone_gain) {
4594 if (spec->cur_out_type != HEADPHONE_OUT) {
4595 if (quirk_data->is_ae_series)
4596 ae5_headphone_gain_set(codec, 2);
4598 zxr_headphone_gain_set(codec, 0);
4600 if (quirk_data->is_ae_series)
4601 ae5_headphone_gain_set(codec,
4602 spec->ae5_headphone_gain_val);
4604 zxr_headphone_gain_set(codec,
4605 spec->zxr_gain_set);
4612 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4613 bool out_enable, bool hp_enable)
4615 unsigned int pin_ctl;
4617 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4618 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4620 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4621 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4622 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4626 * This function behaves similarly to the ca0132_select_out funciton above,
4627 * except with a few differences. It adds the ability to select the current
4628 * output with an enumerated control "output source" if the auto detect
4629 * mute switch is set to off. If the auto detect mute switch is enabled, it
4630 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4631 * It also adds the ability to auto-detect the front headphone port.
4633 static int ca0132_alt_select_out(struct hda_codec *codec)
4635 struct ca0132_spec *spec = codec->spec;
4636 unsigned int tmp, outfx_set;
4640 /* Default Headphone is rear headphone */
4641 hda_nid_t headphone_nid = spec->out_pins[1];
4643 codec_dbg(codec, "%s\n", __func__);
4645 snd_hda_power_up_pm(codec);
4647 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4650 * If headphone rear or front is plugged in, set to headphone.
4651 * If neither is plugged in, set to rear line out. Only if
4652 * hp/speaker auto detect is enabled.
4655 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4656 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4659 spec->cur_out_type = HEADPHONE_OUT;
4661 spec->cur_out_type = SPEAKER_OUT;
4663 spec->cur_out_type = spec->out_enum_val;
4665 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4667 /* Begin DSP output switch, mute DSP volume. */
4668 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4672 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4675 switch (spec->cur_out_type) {
4677 codec_dbg(codec, "%s speaker\n", __func__);
4680 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4681 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4683 /* Disable headphone node. */
4684 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4685 /* Set front L-R to output. */
4686 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4687 /* Set Center/LFE to output. */
4688 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4689 /* Set rear surround to output. */
4690 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4693 * Without PlayEnhancement being enabled, if we've got a 2.0
4694 * setup, set it to floating point eight to disable any DSP
4695 * processing effects.
4697 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4700 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4702 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4708 codec_dbg(codec, "%s hp\n", __func__);
4709 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4710 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4712 /* Disable all speaker nodes. */
4713 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4714 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4715 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4717 /* enable headphone, either front or rear */
4718 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4719 headphone_nid = spec->out_pins[2];
4720 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4721 headphone_nid = spec->out_pins[1];
4723 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4726 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4728 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4735 * If output effects are enabled, set the X-Bass effect value again to
4736 * make sure that it's properly enabled/disabled for speaker
4737 * configurations with an LFE channel.
4740 ca0132_effects_set(codec, X_BASS,
4741 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4743 /* Set speaker EQ bypass attenuation to 0. */
4744 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4749 * Although unused on all cards but the AE series, this is always set
4750 * to zero when setting the output.
4752 err = dspio_set_uint_param(codec, 0x96,
4753 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4757 if (spec->cur_out_type == SPEAKER_OUT)
4758 err = ca0132_alt_surround_set_bass_redirection(codec,
4759 spec->bass_redirection_val);
4761 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4763 /* Unmute DSP now that we're done with output selection. */
4764 err = dspio_set_uint_param(codec, 0x96,
4765 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4769 if (spec->cur_out_type == SPEAKER_OUT) {
4770 err = ca0132_alt_set_full_range_speaker(codec);
4776 snd_hda_power_down_pm(codec);
4778 return err < 0 ? err : 0;
4781 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4783 struct ca0132_spec *spec = container_of(
4784 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4785 struct hda_jack_tbl *jack;
4787 if (ca0132_use_alt_functions(spec))
4788 ca0132_alt_select_out(spec->codec);
4790 ca0132_select_out(spec->codec);
4792 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4794 jack->block_report = 0;
4795 snd_hda_jack_report_sync(spec->codec);
4799 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4800 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4801 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4802 static int stop_mic1(struct hda_codec *codec);
4803 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4804 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4807 * Select the active VIP source
4809 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4811 struct ca0132_spec *spec = codec->spec;
4814 if (spec->dsp_state != DSP_DOWNLOADED)
4817 /* if CrystalVoice if off, vipsource should be 0 */
4818 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4820 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4821 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4822 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4823 if (spec->cur_mic_type == DIGITAL_MIC)
4827 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4829 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4831 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4832 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4833 if (spec->cur_mic_type == DIGITAL_MIC)
4837 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4839 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4841 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4847 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4849 struct ca0132_spec *spec = codec->spec;
4852 if (spec->dsp_state != DSP_DOWNLOADED)
4855 codec_dbg(codec, "%s\n", __func__);
4857 chipio_set_stream_control(codec, 0x03, 0);
4858 chipio_set_stream_control(codec, 0x04, 0);
4860 /* if CrystalVoice is off, vipsource should be 0 */
4861 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4862 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4863 codec_dbg(codec, "%s: off.", __func__);
4864 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4867 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4869 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4870 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4871 if (ca0132_quirk(spec) == QUIRK_R3DI)
4872 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4875 if (spec->in_enum_val == REAR_LINE_IN)
4878 if (ca0132_quirk(spec) == QUIRK_SBZ)
4884 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4887 codec_dbg(codec, "%s: on.", __func__);
4888 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4889 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4890 if (ca0132_quirk(spec) == QUIRK_R3DI)
4891 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4893 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4897 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4900 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4903 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4906 chipio_set_stream_control(codec, 0x03, 1);
4907 chipio_set_stream_control(codec, 0x04, 1);
4913 * Select the active microphone.
4914 * If autodetect is enabled, mic will be selected based on jack detection.
4915 * If jack inserted, ext.mic will be selected, else built-in mic
4916 * If autodetect is disabled, mic will be selected based on selection.
4918 static int ca0132_select_mic(struct hda_codec *codec)
4920 struct ca0132_spec *spec = codec->spec;
4924 codec_dbg(codec, "ca0132_select_mic\n");
4926 snd_hda_power_up_pm(codec);
4928 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4931 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4934 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4937 spec->cur_mic_type = LINE_MIC_IN;
4939 spec->cur_mic_type = DIGITAL_MIC;
4941 if (spec->cur_mic_type == DIGITAL_MIC) {
4942 /* enable digital Mic */
4943 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4944 ca0132_set_dmic(codec, 1);
4945 ca0132_mic_boost_set(codec, 0);
4946 /* set voice focus */
4947 ca0132_effects_set(codec, VOICE_FOCUS,
4948 spec->effects_switch
4949 [VOICE_FOCUS - EFFECT_START_NID]);
4951 /* disable digital Mic */
4952 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4953 ca0132_set_dmic(codec, 0);
4954 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4955 /* disable voice focus */
4956 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4959 snd_hda_power_down_pm(codec);
4965 * Select the active input.
4966 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4967 * The front mic has no jack-detection, so the only way to switch to it
4968 * is to do it manually in alsamixer.
4970 static int ca0132_alt_select_in(struct hda_codec *codec)
4972 struct ca0132_spec *spec = codec->spec;
4975 codec_dbg(codec, "%s\n", __func__);
4977 snd_hda_power_up_pm(codec);
4979 chipio_set_stream_control(codec, 0x03, 0);
4980 chipio_set_stream_control(codec, 0x04, 0);
4982 spec->cur_mic_type = spec->in_enum_val;
4984 switch (spec->cur_mic_type) {
4986 switch (ca0132_quirk(spec)) {
4989 ca0113_mmio_gpio_set(codec, 0, false);
4996 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5000 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5004 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5006 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5008 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5010 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5017 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5018 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5019 if (ca0132_quirk(spec) == QUIRK_R3DI)
5020 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5022 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5024 chipio_set_stream_control(codec, 0x03, 1);
5025 chipio_set_stream_control(codec, 0x04, 1);
5026 switch (ca0132_quirk(spec)) {
5028 chipio_write(codec, 0x18B098, 0x0000000C);
5029 chipio_write(codec, 0x18B09C, 0x0000000C);
5032 chipio_write(codec, 0x18B098, 0x0000000C);
5033 chipio_write(codec, 0x18B09C, 0x000000CC);
5036 chipio_write(codec, 0x18B098, 0x0000000C);
5037 chipio_write(codec, 0x18B09C, 0x0000004C);
5042 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5045 ca0132_mic_boost_set(codec, 0);
5046 switch (ca0132_quirk(spec)) {
5049 ca0113_mmio_gpio_set(codec, 0, false);
5052 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5055 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5058 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5059 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5061 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5063 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5069 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5070 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5071 if (ca0132_quirk(spec) == QUIRK_R3DI)
5072 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5074 if (ca0132_quirk(spec) == QUIRK_AE7)
5078 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5080 switch (ca0132_quirk(spec)) {
5083 chipio_write(codec, 0x18B098, 0x00000000);
5084 chipio_write(codec, 0x18B09C, 0x00000000);
5089 chipio_set_stream_control(codec, 0x03, 1);
5090 chipio_set_stream_control(codec, 0x04, 1);
5093 switch (ca0132_quirk(spec)) {
5096 ca0113_mmio_gpio_set(codec, 0, true);
5097 ca0113_mmio_gpio_set(codec, 5, false);
5101 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5105 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5113 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5114 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5115 if (ca0132_quirk(spec) == QUIRK_R3DI)
5116 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5118 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5120 chipio_set_stream_control(codec, 0x03, 1);
5121 chipio_set_stream_control(codec, 0x04, 1);
5123 switch (ca0132_quirk(spec)) {
5125 chipio_write(codec, 0x18B098, 0x0000000C);
5126 chipio_write(codec, 0x18B09C, 0x000000CC);
5129 chipio_write(codec, 0x18B098, 0x0000000C);
5130 chipio_write(codec, 0x18B09C, 0x0000004C);
5135 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5138 ca0132_cvoice_switch_set(codec);
5140 snd_hda_power_down_pm(codec);
5145 * Check if VNODE settings take effect immediately.
5147 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5149 hda_nid_t *shared_nid)
5151 struct ca0132_spec *spec = codec->spec;
5156 nid = spec->shared_out_nid;
5159 nid = spec->shared_mic_nid;
5172 * The following functions are control change helpers.
5173 * They return 0 if no changed. Return 1 if changed.
5175 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5177 struct ca0132_spec *spec = codec->spec;
5180 /* based on CrystalVoice state to enable VoiceFX. */
5182 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5183 FLOAT_ONE : FLOAT_ZERO;
5188 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5189 ca0132_voicefx.reqs[0], tmp);
5195 * Set the effects parameters
5197 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5199 struct ca0132_spec *spec = codec->spec;
5200 unsigned int on, tmp, channel_cfg;
5201 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5203 int idx = nid - EFFECT_START_NID;
5205 if ((idx < 0) || (idx >= num_fx))
5206 return 0; /* no changed */
5208 /* for out effect, qualify with PE */
5209 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5210 /* if PE if off, turn off out effects. */
5211 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5213 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5214 channel_cfg = spec->channel_cfg_val;
5215 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5216 channel_cfg != SPEAKER_CHANNELS_4_0)
5221 /* for in effect, qualify with CrystalVoice */
5222 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5223 /* if CrystalVoice if off, turn off in effects. */
5224 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5227 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5228 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5231 /* If Voice Focus on SBZ, set to two channel. */
5232 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5233 && (spec->cur_mic_type != REAR_LINE_IN)) {
5234 if (spec->effects_switch[CRYSTAL_VOICE -
5235 EFFECT_START_NID]) {
5237 if (spec->effects_switch[VOICE_FOCUS -
5238 EFFECT_START_NID]) {
5244 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5248 * For SBZ noise reduction, there's an extra command
5249 * to module ID 0x47. No clue why.
5251 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5252 && (spec->cur_mic_type != REAR_LINE_IN)) {
5253 if (spec->effects_switch[CRYSTAL_VOICE -
5254 EFFECT_START_NID]) {
5255 if (spec->effects_switch[NOISE_REDUCTION -
5263 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5266 /* If rear line in disable effects. */
5267 if (ca0132_use_alt_functions(spec) &&
5268 spec->in_enum_val == REAR_LINE_IN)
5272 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5275 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5276 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5277 ca0132_effects[idx].reqs[0], on);
5280 return 0; /* no changed */
5286 * Turn on/off Playback Enhancements
5288 static int ca0132_pe_switch_set(struct hda_codec *codec)
5290 struct ca0132_spec *spec = codec->spec;
5294 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5295 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5297 if (ca0132_use_alt_functions(spec))
5298 ca0132_alt_select_out(codec);
5300 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5301 nid = OUT_EFFECT_START_NID;
5302 /* PE affects all out effects */
5303 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5304 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5309 /* Check if Mic1 is streaming, if so, stop streaming */
5310 static int stop_mic1(struct hda_codec *codec)
5312 struct ca0132_spec *spec = codec->spec;
5313 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5314 AC_VERB_GET_CONV, 0);
5316 snd_hda_codec_write(codec, spec->adcs[0], 0,
5317 AC_VERB_SET_CHANNEL_STREAMID,
5322 /* Resume Mic1 streaming if it was stopped. */
5323 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5325 struct ca0132_spec *spec = codec->spec;
5326 /* Restore the previous stream and channel */
5328 snd_hda_codec_write(codec, spec->adcs[0], 0,
5329 AC_VERB_SET_CHANNEL_STREAMID,
5334 * Turn on/off CrystalVoice
5336 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5338 struct ca0132_spec *spec = codec->spec;
5341 unsigned int oldval;
5343 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5344 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5346 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5347 nid = IN_EFFECT_START_NID;
5348 /* CrystalVoice affects all in effects */
5349 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5350 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5352 /* including VoiceFX */
5353 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5355 /* set correct vipsource */
5356 oldval = stop_mic1(codec);
5357 if (ca0132_use_alt_functions(spec))
5358 ret |= ca0132_alt_set_vipsource(codec, 1);
5360 ret |= ca0132_set_vipsource(codec, 1);
5361 resume_mic1(codec, oldval);
5365 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5367 struct ca0132_spec *spec = codec->spec;
5371 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5372 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5374 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5375 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5380 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5382 struct ca0132_spec *spec = codec->spec;
5385 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5386 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5390 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5394 for (i = 0; i < 4; i++)
5395 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5396 ae5_headphone_gain_presets[val].vals[i]);
5401 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5402 * amplifier to handle a 600 ohm load.
5404 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5406 ca0113_mmio_gpio_set(codec, 1, val);
5411 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5412 struct snd_ctl_elem_value *ucontrol)
5414 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5415 hda_nid_t nid = get_amp_nid(kcontrol);
5416 hda_nid_t shared_nid = 0;
5419 struct ca0132_spec *spec = codec->spec;
5422 if (nid == VNID_HP_SEL) {
5424 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5426 if (ca0132_use_alt_functions(spec))
5427 ca0132_alt_select_out(codec);
5429 ca0132_select_out(codec);
5434 if (nid == VNID_AMIC1_SEL) {
5436 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5438 ca0132_select_mic(codec);
5442 if (nid == VNID_HP_ASEL) {
5443 if (ca0132_use_alt_functions(spec))
5444 ca0132_alt_select_out(codec);
5446 ca0132_select_out(codec);
5450 if (nid == VNID_AMIC1_ASEL) {
5451 ca0132_select_mic(codec);
5455 /* if effective conditions, then update hw immediately. */
5456 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5458 int dir = get_amp_direction(kcontrol);
5459 int ch = get_amp_channels(kcontrol);
5462 mutex_lock(&codec->control_mutex);
5463 pval = kcontrol->private_value;
5464 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5466 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5467 kcontrol->private_value = pval;
5468 mutex_unlock(&codec->control_mutex);
5473 /* End of control change helpers. */
5475 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5478 snd_hda_power_up(codec);
5480 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5481 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5483 snd_hda_power_down(codec);
5487 * Below I've added controls to mess with the effect levels, I've only enabled
5488 * them on the Sound Blaster Z, but they would probably also work on the
5489 * Chromebook. I figured they were probably tuned specifically for it, and left
5493 /* Sets DSP effect level from the sliders above the controls */
5495 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5496 const unsigned int *lookup, int idx)
5501 * For X_BASS, req 2 is actually crossover freq instead of
5509 snd_hda_power_up(codec);
5510 if (nid == XBASS_XOVER) {
5511 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5512 if (ca0132_effects[i].nid == X_BASS)
5515 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5516 ca0132_effects[i].reqs[1],
5517 &(lookup[idx - 1]), sizeof(unsigned int));
5519 /* Find the actual effect structure */
5520 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5521 if (nid == ca0132_effects[i].nid)
5524 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5525 ca0132_effects[i].reqs[y],
5526 &(lookup[idx]), sizeof(unsigned int));
5529 snd_hda_power_down(codec);
5534 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5535 struct snd_ctl_elem_value *ucontrol)
5537 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5538 struct ca0132_spec *spec = codec->spec;
5539 long *valp = ucontrol->value.integer.value;
5540 hda_nid_t nid = get_amp_nid(kcontrol);
5542 if (nid == BASS_REDIRECTION_XOVER)
5543 *valp = spec->bass_redirect_xover_freq;
5545 *valp = spec->xbass_xover_freq;
5550 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5551 struct snd_ctl_elem_value *ucontrol)
5553 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5554 struct ca0132_spec *spec = codec->spec;
5555 hda_nid_t nid = get_amp_nid(kcontrol);
5556 long *valp = ucontrol->value.integer.value;
5557 int idx = nid - OUT_EFFECT_START_NID;
5559 *valp = spec->fx_ctl_val[idx];
5564 * The X-bass crossover starts at 10hz, so the min is 1. The
5565 * frequency is set in multiples of 10.
5567 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5568 struct snd_ctl_elem_info *uinfo)
5570 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5572 uinfo->value.integer.min = 1;
5573 uinfo->value.integer.max = 100;
5574 uinfo->value.integer.step = 1;
5579 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5580 struct snd_ctl_elem_info *uinfo)
5582 int chs = get_amp_channels(kcontrol);
5584 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5585 uinfo->count = chs == 3 ? 2 : 1;
5586 uinfo->value.integer.min = 0;
5587 uinfo->value.integer.max = 100;
5588 uinfo->value.integer.step = 1;
5593 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5594 struct snd_ctl_elem_value *ucontrol)
5596 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5597 struct ca0132_spec *spec = codec->spec;
5598 hda_nid_t nid = get_amp_nid(kcontrol);
5599 long *valp = ucontrol->value.integer.value;
5603 if (nid == BASS_REDIRECTION_XOVER)
5604 cur_val = &spec->bass_redirect_xover_freq;
5606 cur_val = &spec->xbass_xover_freq;
5609 if (*cur_val == *valp)
5615 if (nid == BASS_REDIRECTION_XOVER)
5616 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5618 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5623 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5624 struct snd_ctl_elem_value *ucontrol)
5626 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5627 struct ca0132_spec *spec = codec->spec;
5628 hda_nid_t nid = get_amp_nid(kcontrol);
5629 long *valp = ucontrol->value.integer.value;
5632 idx = nid - EFFECT_START_NID;
5634 if (spec->fx_ctl_val[idx] == *valp)
5637 spec->fx_ctl_val[idx] = *valp;
5640 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5647 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5648 * only has off or full 30 dB, and didn't like making a volume slider that has
5649 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5651 #define MIC_BOOST_NUM_OF_STEPS 4
5652 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5654 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5655 struct snd_ctl_elem_info *uinfo)
5658 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5660 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5662 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5663 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5664 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5665 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5666 strcpy(uinfo->value.enumerated.name, namestr);
5670 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5671 struct snd_ctl_elem_value *ucontrol)
5673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5674 struct ca0132_spec *spec = codec->spec;
5676 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5680 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5681 struct snd_ctl_elem_value *ucontrol)
5683 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5684 struct ca0132_spec *spec = codec->spec;
5685 int sel = ucontrol->value.enumerated.item[0];
5686 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5691 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5694 spec->mic_boost_enum_val = sel;
5696 if (spec->in_enum_val != REAR_LINE_IN)
5697 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5703 * Sound BlasterX AE-5 Headphone Gain Controls.
5705 #define AE5_HEADPHONE_GAIN_MAX 3
5706 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5707 struct snd_ctl_elem_info *uinfo)
5709 char *sfx = " Ohms)";
5710 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5712 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5714 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5715 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5716 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5717 sprintf(namestr, "%s %s",
5718 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5720 strcpy(uinfo->value.enumerated.name, namestr);
5724 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5725 struct snd_ctl_elem_value *ucontrol)
5727 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5728 struct ca0132_spec *spec = codec->spec;
5730 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5734 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5735 struct snd_ctl_elem_value *ucontrol)
5737 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5738 struct ca0132_spec *spec = codec->spec;
5739 int sel = ucontrol->value.enumerated.item[0];
5740 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5745 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5748 spec->ae5_headphone_gain_val = sel;
5750 if (spec->out_enum_val == HEADPHONE_OUT)
5751 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5757 * Sound BlasterX AE-5 sound filter enumerated control.
5759 #define AE5_SOUND_FILTER_MAX 3
5761 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5762 struct snd_ctl_elem_info *uinfo)
5764 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5766 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5768 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5769 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5770 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5771 sprintf(namestr, "%s",
5772 ae5_filter_presets[uinfo->value.enumerated.item].name);
5773 strcpy(uinfo->value.enumerated.name, namestr);
5777 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5778 struct snd_ctl_elem_value *ucontrol)
5780 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5781 struct ca0132_spec *spec = codec->spec;
5783 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5787 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5788 struct snd_ctl_elem_value *ucontrol)
5790 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5791 struct ca0132_spec *spec = codec->spec;
5792 int sel = ucontrol->value.enumerated.item[0];
5793 unsigned int items = AE5_SOUND_FILTER_MAX;
5798 codec_dbg(codec, "ae5_sound_filter: %s\n",
5799 ae5_filter_presets[sel].name);
5801 spec->ae5_filter_val = sel;
5803 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5804 ae5_filter_presets[sel].val);
5810 * Input Select Control for alternative ca0132 codecs. This exists because
5811 * front microphone has no auto-detect, and we need a way to set the rear
5814 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5815 struct snd_ctl_elem_info *uinfo)
5817 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5819 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5820 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5821 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5822 strcpy(uinfo->value.enumerated.name,
5823 in_src_str[uinfo->value.enumerated.item]);
5827 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5828 struct snd_ctl_elem_value *ucontrol)
5830 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5831 struct ca0132_spec *spec = codec->spec;
5833 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5837 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5838 struct snd_ctl_elem_value *ucontrol)
5840 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5841 struct ca0132_spec *spec = codec->spec;
5842 int sel = ucontrol->value.enumerated.item[0];
5843 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5846 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5849 if (ca0132_quirk(spec) == QUIRK_AE7)
5855 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5856 sel, in_src_str[sel]);
5858 spec->in_enum_val = sel;
5860 ca0132_alt_select_in(codec);
5865 /* Sound Blaster Z Output Select Control */
5866 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5867 struct snd_ctl_elem_info *uinfo)
5869 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5871 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5872 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5873 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5874 strcpy(uinfo->value.enumerated.name,
5875 out_type_str[uinfo->value.enumerated.item]);
5879 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5880 struct snd_ctl_elem_value *ucontrol)
5882 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5883 struct ca0132_spec *spec = codec->spec;
5885 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5889 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5890 struct snd_ctl_elem_value *ucontrol)
5892 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5893 struct ca0132_spec *spec = codec->spec;
5894 int sel = ucontrol->value.enumerated.item[0];
5895 unsigned int items = NUM_OF_OUTPUTS;
5896 unsigned int auto_jack;
5901 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5902 sel, out_type_str[sel]);
5904 spec->out_enum_val = sel;
5906 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5909 ca0132_alt_select_out(codec);
5914 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
5915 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
5916 struct snd_ctl_elem_info *uinfo)
5918 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5920 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5922 uinfo->value.enumerated.items = items;
5923 if (uinfo->value.enumerated.item >= items)
5924 uinfo->value.enumerated.item = items - 1;
5925 strcpy(uinfo->value.enumerated.name,
5926 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
5930 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
5931 struct snd_ctl_elem_value *ucontrol)
5933 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5934 struct ca0132_spec *spec = codec->spec;
5936 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
5940 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
5941 struct snd_ctl_elem_value *ucontrol)
5943 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5944 struct ca0132_spec *spec = codec->spec;
5945 int sel = ucontrol->value.enumerated.item[0];
5946 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5951 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
5952 sel, speaker_channel_cfgs[sel].name);
5954 spec->channel_cfg_val = sel;
5956 if (spec->out_enum_val == SPEAKER_OUT)
5957 ca0132_alt_select_out(codec);
5963 * Smart Volume output setting control. Three different settings, Normal,
5964 * which takes the value from the smart volume slider. The two others, loud
5965 * and night, disregard the slider value and have uneditable values.
5967 #define NUM_OF_SVM_SETTINGS 3
5968 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5970 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5971 struct snd_ctl_elem_info *uinfo)
5973 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5975 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5976 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5977 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5978 strcpy(uinfo->value.enumerated.name,
5979 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5983 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5984 struct snd_ctl_elem_value *ucontrol)
5986 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5987 struct ca0132_spec *spec = codec->spec;
5989 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5993 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5994 struct snd_ctl_elem_value *ucontrol)
5996 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5997 struct ca0132_spec *spec = codec->spec;
5998 int sel = ucontrol->value.enumerated.item[0];
5999 unsigned int items = NUM_OF_SVM_SETTINGS;
6000 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6006 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6007 sel, out_svm_set_enum_str[sel]);
6009 spec->smart_volume_setting = sel;
6025 /* Req 2 is the Smart Volume Setting req. */
6026 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6027 ca0132_effects[idx].reqs[2], tmp);
6031 /* Sound Blaster Z EQ preset controls */
6032 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6033 struct snd_ctl_elem_info *uinfo)
6035 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6037 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6039 uinfo->value.enumerated.items = items;
6040 if (uinfo->value.enumerated.item >= items)
6041 uinfo->value.enumerated.item = items - 1;
6042 strcpy(uinfo->value.enumerated.name,
6043 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6047 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6048 struct snd_ctl_elem_value *ucontrol)
6050 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6051 struct ca0132_spec *spec = codec->spec;
6053 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6057 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6058 struct snd_ctl_elem_value *ucontrol)
6060 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6061 struct ca0132_spec *spec = codec->spec;
6063 int sel = ucontrol->value.enumerated.item[0];
6064 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6069 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6070 ca0132_alt_eq_presets[sel].name);
6073 * Default needs to qualify with CrystalVoice state.
6075 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6076 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6077 ca0132_alt_eq_enum.reqs[i],
6078 ca0132_alt_eq_presets[sel].vals[i]);
6084 spec->eq_preset_val = sel;
6089 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6090 struct snd_ctl_elem_info *uinfo)
6092 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6094 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6096 uinfo->value.enumerated.items = items;
6097 if (uinfo->value.enumerated.item >= items)
6098 uinfo->value.enumerated.item = items - 1;
6099 strcpy(uinfo->value.enumerated.name,
6100 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6104 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6105 struct snd_ctl_elem_value *ucontrol)
6107 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6108 struct ca0132_spec *spec = codec->spec;
6110 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6114 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6115 struct snd_ctl_elem_value *ucontrol)
6117 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6118 struct ca0132_spec *spec = codec->spec;
6120 int sel = ucontrol->value.enumerated.item[0];
6122 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6125 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6126 sel, ca0132_voicefx_presets[sel].name);
6130 * Default needs to qualify with CrystalVoice state.
6132 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6133 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6134 ca0132_voicefx.reqs[i],
6135 ca0132_voicefx_presets[sel].vals[i]);
6141 spec->voicefx_val = sel;
6142 /* enable voice fx */
6143 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6149 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6150 struct snd_ctl_elem_value *ucontrol)
6152 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6153 struct ca0132_spec *spec = codec->spec;
6154 hda_nid_t nid = get_amp_nid(kcontrol);
6155 int ch = get_amp_channels(kcontrol);
6156 long *valp = ucontrol->value.integer.value;
6159 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6161 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6165 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6171 /* effects, include PE and CrystalVoice */
6172 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6173 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6178 if (nid == spec->input_pins[0]) {
6179 *valp = spec->cur_mic_boost;
6183 if (nid == ZXR_HEADPHONE_GAIN) {
6184 *valp = spec->zxr_gain_set;
6188 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6189 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6193 if (nid == BASS_REDIRECTION) {
6194 *valp = spec->bass_redirection_val;
6201 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6202 struct snd_ctl_elem_value *ucontrol)
6204 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6205 struct ca0132_spec *spec = codec->spec;
6206 hda_nid_t nid = get_amp_nid(kcontrol);
6207 int ch = get_amp_channels(kcontrol);
6208 long *valp = ucontrol->value.integer.value;
6211 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6214 snd_hda_power_up(codec);
6216 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6218 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6222 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6225 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6230 if (nid == PLAY_ENHANCEMENT) {
6231 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6232 changed = ca0132_pe_switch_set(codec);
6237 if (nid == CRYSTAL_VOICE) {
6238 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6239 changed = ca0132_cvoice_switch_set(codec);
6243 /* out and in effects */
6244 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6245 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6246 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6247 changed = ca0132_effects_set(codec, nid, *valp);
6252 if (nid == spec->input_pins[0]) {
6253 spec->cur_mic_boost = *valp;
6254 if (ca0132_use_alt_functions(spec)) {
6255 if (spec->in_enum_val != REAR_LINE_IN)
6256 changed = ca0132_mic_boost_set(codec, *valp);
6258 /* Mic boost does not apply to Digital Mic */
6259 if (spec->cur_mic_type != DIGITAL_MIC)
6260 changed = ca0132_mic_boost_set(codec, *valp);
6266 if (nid == ZXR_HEADPHONE_GAIN) {
6267 spec->zxr_gain_set = *valp;
6268 if (spec->cur_out_type == HEADPHONE_OUT)
6269 changed = zxr_headphone_gain_set(codec, *valp);
6276 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6277 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6278 if (spec->cur_out_type == SPEAKER_OUT)
6279 ca0132_alt_set_full_range_speaker(codec);
6284 if (nid == BASS_REDIRECTION) {
6285 spec->bass_redirection_val = *valp;
6286 if (spec->cur_out_type == SPEAKER_OUT)
6287 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6293 snd_hda_power_down(codec);
6301 * Sets the internal DSP decibel level to match the DAC for output, and the
6302 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6303 * all alternative codecs set DSP playback volume.
6305 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6307 struct ca0132_spec *spec = codec->spec;
6308 unsigned int dsp_dir;
6309 unsigned int lookup_val;
6311 if (nid == VNID_SPK)
6312 dsp_dir = DSP_VOL_OUT;
6314 dsp_dir = DSP_VOL_IN;
6316 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6318 dspio_set_uint_param(codec,
6319 ca0132_alt_vol_ctls[dsp_dir].mid,
6320 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6321 float_vol_db_lookup[lookup_val]);
6323 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6325 dspio_set_uint_param(codec,
6326 ca0132_alt_vol_ctls[dsp_dir].mid,
6327 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6328 float_vol_db_lookup[lookup_val]);
6330 dspio_set_uint_param(codec,
6331 ca0132_alt_vol_ctls[dsp_dir].mid,
6332 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6335 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6336 struct snd_ctl_elem_info *uinfo)
6338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6339 struct ca0132_spec *spec = codec->spec;
6340 hda_nid_t nid = get_amp_nid(kcontrol);
6341 int ch = get_amp_channels(kcontrol);
6342 int dir = get_amp_direction(kcontrol);
6348 /* follow shared_out info */
6349 nid = spec->shared_out_nid;
6350 mutex_lock(&codec->control_mutex);
6351 pval = kcontrol->private_value;
6352 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6353 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6354 kcontrol->private_value = pval;
6355 mutex_unlock(&codec->control_mutex);
6358 /* follow shared_mic info */
6359 nid = spec->shared_mic_nid;
6360 mutex_lock(&codec->control_mutex);
6361 pval = kcontrol->private_value;
6362 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6363 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6364 kcontrol->private_value = pval;
6365 mutex_unlock(&codec->control_mutex);
6368 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6373 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6374 struct snd_ctl_elem_value *ucontrol)
6376 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6377 struct ca0132_spec *spec = codec->spec;
6378 hda_nid_t nid = get_amp_nid(kcontrol);
6379 int ch = get_amp_channels(kcontrol);
6380 long *valp = ucontrol->value.integer.value;
6382 /* store the left and right volume */
6384 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6388 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6394 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6395 struct snd_ctl_elem_value *ucontrol)
6397 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6398 struct ca0132_spec *spec = codec->spec;
6399 hda_nid_t nid = get_amp_nid(kcontrol);
6400 int ch = get_amp_channels(kcontrol);
6401 long *valp = ucontrol->value.integer.value;
6402 hda_nid_t shared_nid = 0;
6406 /* store the left and right volume */
6408 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6412 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6416 /* if effective conditions, then update hw immediately. */
6417 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6419 int dir = get_amp_direction(kcontrol);
6422 snd_hda_power_up(codec);
6423 mutex_lock(&codec->control_mutex);
6424 pval = kcontrol->private_value;
6425 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6427 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6428 kcontrol->private_value = pval;
6429 mutex_unlock(&codec->control_mutex);
6430 snd_hda_power_down(codec);
6437 * This function is the same as the one above, because using an if statement
6438 * inside of the above volume control for the DSP volume would cause too much
6439 * lag. This is a lot more smooth.
6441 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6442 struct snd_ctl_elem_value *ucontrol)
6444 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6445 struct ca0132_spec *spec = codec->spec;
6446 hda_nid_t nid = get_amp_nid(kcontrol);
6447 int ch = get_amp_channels(kcontrol);
6448 long *valp = ucontrol->value.integer.value;
6461 /* store the left and right volume */
6463 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6467 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6471 snd_hda_power_up(codec);
6472 ca0132_alt_dsp_volume_put(codec, vnid);
6473 mutex_lock(&codec->control_mutex);
6474 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6475 mutex_unlock(&codec->control_mutex);
6476 snd_hda_power_down(codec);
6481 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6482 unsigned int size, unsigned int __user *tlv)
6484 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6485 struct ca0132_spec *spec = codec->spec;
6486 hda_nid_t nid = get_amp_nid(kcontrol);
6487 int ch = get_amp_channels(kcontrol);
6488 int dir = get_amp_direction(kcontrol);
6494 /* follow shared_out tlv */
6495 nid = spec->shared_out_nid;
6496 mutex_lock(&codec->control_mutex);
6497 pval = kcontrol->private_value;
6498 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6499 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6500 kcontrol->private_value = pval;
6501 mutex_unlock(&codec->control_mutex);
6504 /* follow shared_mic tlv */
6505 nid = spec->shared_mic_nid;
6506 mutex_lock(&codec->control_mutex);
6507 pval = kcontrol->private_value;
6508 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6509 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6510 kcontrol->private_value = pval;
6511 mutex_unlock(&codec->control_mutex);
6514 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6519 /* Add volume slider control for effect level */
6520 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6521 const char *pfx, int dir)
6523 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6524 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6525 struct snd_kcontrol_new knew =
6526 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6528 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6534 knew.info = ca0132_alt_xbass_xover_slider_info;
6535 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6536 knew.put = ca0132_alt_xbass_xover_slider_put;
6539 knew.info = ca0132_alt_effect_slider_info;
6540 knew.get = ca0132_alt_slider_ctl_get;
6541 knew.put = ca0132_alt_effect_slider_put;
6542 knew.private_value =
6543 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6547 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6551 * Added FX: prefix for the alternative codecs, because otherwise the surround
6552 * effect would conflict with the Surround sound volume control. Also seems more
6553 * clear as to what the switches do. Left alone for others.
6555 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6556 const char *pfx, int dir)
6558 struct ca0132_spec *spec = codec->spec;
6559 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6560 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6561 struct snd_kcontrol_new knew =
6562 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6563 /* If using alt_controls, add FX: prefix. But, don't add FX:
6564 * prefix to OutFX or InFX enable controls.
6566 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6567 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6569 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6571 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6574 static int add_voicefx(struct hda_codec *codec)
6576 struct snd_kcontrol_new knew =
6577 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6578 VOICEFX, 1, 0, HDA_INPUT);
6579 knew.info = ca0132_voicefx_info;
6580 knew.get = ca0132_voicefx_get;
6581 knew.put = ca0132_voicefx_put;
6582 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6585 /* Create the EQ Preset control */
6586 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6588 struct snd_kcontrol_new knew =
6589 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6590 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6591 knew.info = ca0132_alt_eq_preset_info;
6592 knew.get = ca0132_alt_eq_preset_get;
6593 knew.put = ca0132_alt_eq_preset_put;
6594 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6595 snd_ctl_new1(&knew, codec));
6599 * Add enumerated control for the three different settings of the smart volume
6600 * output effect. Normal just uses the slider value, and loud and night are
6601 * their own things that ignore that value.
6603 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6605 struct snd_kcontrol_new knew =
6606 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6607 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6608 knew.info = ca0132_alt_svm_setting_info;
6609 knew.get = ca0132_alt_svm_setting_get;
6610 knew.put = ca0132_alt_svm_setting_put;
6611 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6612 snd_ctl_new1(&knew, codec));
6617 * Create an Output Select enumerated control for codecs with surround
6620 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6622 struct snd_kcontrol_new knew =
6623 HDA_CODEC_MUTE_MONO("Output Select",
6624 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6625 knew.info = ca0132_alt_output_select_get_info;
6626 knew.get = ca0132_alt_output_select_get;
6627 knew.put = ca0132_alt_output_select_put;
6628 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6629 snd_ctl_new1(&knew, codec));
6633 * Add a control for selecting channel count on speaker output. Setting this
6634 * allows the DSP to do bass redirection and channel upmixing on surround
6637 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6639 struct snd_kcontrol_new knew =
6640 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6641 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6642 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6643 knew.get = ca0132_alt_speaker_channel_cfg_get;
6644 knew.put = ca0132_alt_speaker_channel_cfg_put;
6645 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6646 snd_ctl_new1(&knew, codec));
6650 * Full range front stereo and rear surround switches. When these are set to
6651 * full range, the lower frequencies from these channels are no longer
6652 * redirected to the LFE channel.
6654 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6656 struct snd_kcontrol_new knew =
6657 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6658 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6660 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6661 snd_ctl_new1(&knew, codec));
6664 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6666 struct snd_kcontrol_new knew =
6667 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6668 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6670 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6671 snd_ctl_new1(&knew, codec));
6675 * Bass redirection redirects audio below the crossover frequency to the LFE
6676 * channel on speakers that are set as not being full-range. On configurations
6677 * without an LFE channel, it does nothing. Bass redirection seems to be the
6678 * replacement for X-Bass on configurations with an LFE channel.
6680 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6682 const char *namestr = "Bass Redirection Crossover";
6683 struct snd_kcontrol_new knew =
6684 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6688 knew.info = ca0132_alt_xbass_xover_slider_info;
6689 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6690 knew.put = ca0132_alt_xbass_xover_slider_put;
6692 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6693 snd_ctl_new1(&knew, codec));
6696 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6698 const char *namestr = "Bass Redirection";
6699 struct snd_kcontrol_new knew =
6700 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6703 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6704 snd_ctl_new1(&knew, codec));
6708 * Create an Input Source enumerated control for the alternate ca0132 codecs
6709 * because the front microphone has no auto-detect, and Line-in has to be set
6712 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6714 struct snd_kcontrol_new knew =
6715 HDA_CODEC_MUTE_MONO("Input Source",
6716 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6717 knew.info = ca0132_alt_input_source_info;
6718 knew.get = ca0132_alt_input_source_get;
6719 knew.put = ca0132_alt_input_source_put;
6720 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6721 snd_ctl_new1(&knew, codec));
6725 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6726 * more control than the original mic boost, which is either full 30dB or off.
6728 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6730 struct snd_kcontrol_new knew =
6731 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6732 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6733 knew.info = ca0132_alt_mic_boost_info;
6734 knew.get = ca0132_alt_mic_boost_get;
6735 knew.put = ca0132_alt_mic_boost_put;
6736 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6737 snd_ctl_new1(&knew, codec));
6742 * Add headphone gain enumerated control for the AE-5. This switches between
6743 * three modes, low, medium, and high. When non-headphone outputs are selected,
6744 * it is automatically set to high. This is the same behavior as Windows.
6746 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6748 struct snd_kcontrol_new knew =
6749 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6750 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6751 knew.info = ae5_headphone_gain_info;
6752 knew.get = ae5_headphone_gain_get;
6753 knew.put = ae5_headphone_gain_put;
6754 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6755 snd_ctl_new1(&knew, codec));
6759 * Add sound filter enumerated control for the AE-5. This adds three different
6760 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6761 * read into it, it changes the DAC's interpolation filter.
6763 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6765 struct snd_kcontrol_new knew =
6766 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6767 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6768 knew.info = ae5_sound_filter_info;
6769 knew.get = ae5_sound_filter_get;
6770 knew.put = ae5_sound_filter_put;
6771 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6772 snd_ctl_new1(&knew, codec));
6775 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6777 struct snd_kcontrol_new knew =
6778 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6779 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6781 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6782 snd_ctl_new1(&knew, codec));
6786 * Need to create follower controls for the alternate codecs that have surround
6789 static const char * const ca0132_alt_follower_pfxs[] = {
6790 "Front", "Surround", "Center", "LFE", NULL,
6794 * Also need special channel map, because the default one is incorrect.
6795 * I think this has to do with the pin for rear surround being 0x11,
6796 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6798 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6800 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6802 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6803 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6805 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6806 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6807 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6811 /* Add the correct chmap for streams with 6 channels. */
6812 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6815 struct hda_pcm *pcm;
6817 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6818 struct hda_pcm_stream *hinfo =
6819 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6820 struct snd_pcm_chmap *chmap;
6821 const struct snd_pcm_chmap_elem *elem;
6823 elem = ca0132_alt_chmaps;
6824 if (hinfo->channels_max == 6) {
6825 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6826 SNDRV_PCM_STREAM_PLAYBACK,
6827 elem, hinfo->channels_max, 0, &chmap);
6829 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6835 * When changing Node IDs for Mixer Controls below, make sure to update
6836 * Node IDs in ca0132_config() as well.
6838 static const struct snd_kcontrol_new ca0132_mixer[] = {
6839 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6840 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6841 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6842 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6843 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6844 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6845 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6846 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6847 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6848 0x12, 1, HDA_INPUT),
6849 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6850 VNID_HP_SEL, 1, HDA_OUTPUT),
6851 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6852 VNID_AMIC1_SEL, 1, HDA_INPUT),
6853 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6854 VNID_HP_ASEL, 1, HDA_OUTPUT),
6855 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6856 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6861 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6862 * surround controls. Also sets both the Front Playback and Capture Volume
6863 * controls to alt so they set the DSP's decibel level.
6865 static const struct snd_kcontrol_new desktop_mixer[] = {
6866 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6867 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6868 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6869 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6870 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6871 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6872 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6873 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6874 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6875 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6876 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6877 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6878 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6879 VNID_HP_ASEL, 1, HDA_OUTPUT),
6884 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6885 * because it doesn't set decibel levels for the DSP for capture.
6887 static const struct snd_kcontrol_new r3di_mixer[] = {
6888 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6889 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6890 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6891 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6892 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6893 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6894 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6895 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6896 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6897 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6898 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6899 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6900 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6901 VNID_HP_ASEL, 1, HDA_OUTPUT),
6905 static int ca0132_build_controls(struct hda_codec *codec)
6907 struct ca0132_spec *spec = codec->spec;
6908 int i, num_fx, num_sliders;
6911 /* Add Mixer controls */
6912 for (i = 0; i < spec->num_mixers; i++) {
6913 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6917 /* Setup vmaster with surround followers for desktop ca0132 devices */
6918 if (ca0132_use_alt_functions(spec)) {
6919 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6921 snd_hda_add_vmaster(codec, "Master Playback Volume",
6922 spec->tlv, ca0132_alt_follower_pfxs,
6924 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6925 NULL, ca0132_alt_follower_pfxs,
6927 true, &spec->vmaster_mute.sw_kctl);
6932 /* Add in and out effects controls.
6933 * VoiceFX, PE and CrystalVoice are added separately.
6935 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6936 for (i = 0; i < num_fx; i++) {
6937 /* Desktop cards break if Echo Cancellation is used. */
6938 if (ca0132_use_pci_mmio(spec)) {
6939 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6944 err = add_fx_switch(codec, ca0132_effects[i].nid,
6945 ca0132_effects[i].name,
6946 ca0132_effects[i].direct);
6951 * If codec has use_alt_controls set to true, add effect level sliders,
6952 * EQ presets, and Smart Volume presets. Also, change names to add FX
6953 * prefix, and change PlayEnhancement and CrystalVoice to match.
6955 if (ca0132_use_alt_controls(spec)) {
6956 err = ca0132_alt_add_svm_enum(codec);
6960 err = add_ca0132_alt_eq_presets(codec);
6964 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6969 err = add_fx_switch(codec, CRYSTAL_VOICE,
6974 num_sliders = OUT_EFFECTS_COUNT - 1;
6975 for (i = 0; i < num_sliders; i++) {
6976 err = ca0132_alt_add_effect_slider(codec,
6977 ca0132_effects[i].nid,
6978 ca0132_effects[i].name,
6979 ca0132_effects[i].direct);
6984 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6985 "X-Bass Crossover", EFX_DIR_OUT);
6990 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6991 "PlayEnhancement", 0);
6995 err = add_fx_switch(codec, CRYSTAL_VOICE,
7000 err = add_voicefx(codec);
7005 * If the codec uses alt_functions, you need the enumerated controls
7006 * to select the new outputs and inputs, plus add the new mic boost
7009 if (ca0132_use_alt_functions(spec)) {
7010 err = ca0132_alt_add_output_enum(codec);
7013 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7016 err = ca0132_alt_add_front_full_range_switch(codec);
7019 err = ca0132_alt_add_rear_full_range_switch(codec);
7022 err = ca0132_alt_add_bass_redirection_crossover(codec);
7025 err = ca0132_alt_add_bass_redirection_switch(codec);
7028 err = ca0132_alt_add_mic_boost_enum(codec);
7032 * ZxR only has microphone input, there is no front panel
7033 * header on the card, and aux-in is handled by the DBPro board.
7035 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7036 err = ca0132_alt_add_input_enum(codec);
7042 switch (ca0132_quirk(spec)) {
7045 err = ae5_add_headphone_gain_enum(codec);
7048 err = ae5_add_sound_filter_enum(codec);
7053 err = zxr_add_headphone_gain_switch(codec);
7061 #ifdef ENABLE_TUNING_CONTROLS
7062 add_tuning_ctls(codec);
7065 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7069 if (spec->dig_out) {
7070 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7074 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7077 /* spec->multiout.share_spdif = 1; */
7081 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7086 if (ca0132_use_alt_functions(spec))
7087 ca0132_alt_add_chmap_ctls(codec);
7092 static int dbpro_build_controls(struct hda_codec *codec)
7094 struct ca0132_spec *spec = codec->spec;
7097 if (spec->dig_out) {
7098 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7105 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7116 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7121 .prepare = ca0132_playback_pcm_prepare,
7122 .cleanup = ca0132_playback_pcm_cleanup,
7123 .get_delay = ca0132_playback_pcm_delay,
7127 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7132 .prepare = ca0132_capture_pcm_prepare,
7133 .cleanup = ca0132_capture_pcm_cleanup,
7134 .get_delay = ca0132_capture_pcm_delay,
7138 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7143 .open = ca0132_dig_playback_pcm_open,
7144 .close = ca0132_dig_playback_pcm_close,
7145 .prepare = ca0132_dig_playback_pcm_prepare,
7146 .cleanup = ca0132_dig_playback_pcm_cleanup
7150 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7156 static int ca0132_build_pcms(struct hda_codec *codec)
7158 struct ca0132_spec *spec = codec->spec;
7159 struct hda_pcm *info;
7161 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7164 if (ca0132_use_alt_functions(spec)) {
7165 info->own_chmap = true;
7166 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7167 = ca0132_alt_chmaps;
7169 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7170 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7171 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7172 spec->multiout.max_channels;
7173 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7174 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7175 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7177 /* With the DSP enabled, desktops don't use this ADC. */
7178 if (!ca0132_use_alt_functions(spec)) {
7179 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7182 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7183 ca0132_pcm_analog_capture;
7184 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7185 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7188 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7191 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7192 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7193 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7195 if (!spec->dig_out && !spec->dig_in)
7198 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7201 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7202 if (spec->dig_out) {
7203 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7204 ca0132_pcm_digital_playback;
7205 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7208 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7209 ca0132_pcm_digital_capture;
7210 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7216 static int dbpro_build_pcms(struct hda_codec *codec)
7218 struct ca0132_spec *spec = codec->spec;
7219 struct hda_pcm *info;
7221 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7224 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7225 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7226 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7229 if (!spec->dig_out && !spec->dig_in)
7232 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7235 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7236 if (spec->dig_out) {
7237 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7238 ca0132_pcm_digital_playback;
7239 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7242 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7243 ca0132_pcm_digital_capture;
7244 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7250 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7253 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7254 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7255 snd_hda_codec_write(codec, pin, 0,
7256 AC_VERB_SET_AMP_GAIN_MUTE,
7259 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7260 snd_hda_codec_write(codec, dac, 0,
7261 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7264 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7267 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7268 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7269 snd_hda_codec_write(codec, pin, 0,
7270 AC_VERB_SET_AMP_GAIN_MUTE,
7273 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7274 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7277 /* init to 0 dB and unmute. */
7278 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7279 HDA_AMP_VOLMASK, 0x5a);
7280 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7285 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7289 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7290 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7291 snd_hda_override_amp_caps(codec, nid, dir, caps);
7295 * Switch between Digital built-in mic and analog mic.
7297 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7299 struct ca0132_spec *spec = codec->spec;
7302 unsigned int oldval;
7304 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7306 oldval = stop_mic1(codec);
7307 ca0132_set_vipsource(codec, 0);
7309 /* set DMic input as 2-ch */
7311 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7313 val = spec->dmic_ctl;
7315 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7316 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7318 if (!(spec->dmic_ctl & 0x20))
7319 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7321 /* set AMic input as mono */
7323 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7325 val = spec->dmic_ctl;
7326 /* clear bit7 and bit5 to disable dmic */
7328 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7329 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7331 if (!(spec->dmic_ctl & 0x20))
7332 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7334 ca0132_set_vipsource(codec, 1);
7335 resume_mic1(codec, oldval);
7339 * Initialization for Digital Mic.
7341 static void ca0132_init_dmic(struct hda_codec *codec)
7343 struct ca0132_spec *spec = codec->spec;
7346 /* Setup Digital Mic here, but don't enable.
7347 * Enable based on jack detect.
7350 /* MCLK uses MPIO1, set to enable.
7351 * Bit 2-0: MPIO select
7352 * Bit 3: set to disable
7356 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7357 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7359 /* Data1 uses MPIO3. Data2 not use
7360 * Bit 2-0: Data1 MPIO select
7361 * Bit 3: set disable Data1
7362 * Bit 6-4: Data2 MPIO select
7363 * Bit 7: set disable Data2
7366 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7367 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7369 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7370 * Bit 3-0: Channel mask
7371 * Bit 4: set for 48KHz, clear for 32KHz
7373 * Bit 6: set to select Data2, clear for Data1
7374 * Bit 7: set to enable DMic, clear for AMic
7376 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7380 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7381 spec->dmic_ctl = val;
7382 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7383 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7387 * Initialization for Analog Mic 2
7389 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7391 struct ca0132_spec *spec = codec->spec;
7393 mutex_lock(&spec->chipio_mutex);
7394 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7395 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7396 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7397 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7398 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7399 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7401 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
7402 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7403 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7404 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7405 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7406 mutex_unlock(&spec->chipio_mutex);
7409 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7411 struct ca0132_spec *spec = codec->spec;
7414 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7415 snd_hda_codec_update_widgets(codec);
7417 for (i = 0; i < spec->multiout.num_dacs; i++)
7418 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7420 for (i = 0; i < spec->num_outputs; i++)
7421 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7423 for (i = 0; i < spec->num_inputs; i++) {
7424 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7425 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7430 * Default speaker tuning values setup for alternative codecs.
7432 static const unsigned int sbz_default_delay_values[] = {
7433 /* Non-zero values are floating point 0.000198. */
7434 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7437 static const unsigned int zxr_default_delay_values[] = {
7438 /* Non-zero values are floating point 0.000220. */
7439 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7442 static const unsigned int ae5_default_delay_values[] = {
7443 /* Non-zero values are floating point 0.000100. */
7444 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7448 * If we never change these, probably only need them on initialization.
7450 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7452 struct ca0132_spec *spec = codec->spec;
7453 unsigned int i, tmp, start_req, end_req;
7454 const unsigned int *values;
7456 switch (ca0132_quirk(spec)) {
7458 values = sbz_default_delay_values;
7461 values = zxr_default_delay_values;
7465 values = ae5_default_delay_values;
7468 values = sbz_default_delay_values;
7473 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7475 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7476 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7477 for (i = start_req; i < end_req + 1; i++)
7478 dspio_set_uint_param(codec, 0x96, i, tmp);
7480 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7481 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7482 for (i = start_req; i < end_req + 1; i++)
7483 dspio_set_uint_param(codec, 0x96, i, tmp);
7486 for (i = 0; i < 6; i++)
7487 dspio_set_uint_param(codec, 0x96,
7488 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7492 * Creates a dummy stream to bind the output to. This seems to have to be done
7493 * after changing the main outputs source and destination streams.
7495 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
7497 struct ca0132_spec *spec = codec->spec;
7498 unsigned int stream_format;
7500 stream_format = snd_hdac_calc_stream_format(48000, 2,
7501 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7503 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
7506 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7510 * Initialize mic for non-chromebook ca0132 implementations.
7512 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7514 struct ca0132_spec *spec = codec->spec;
7518 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7519 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7520 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7521 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7525 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7527 /* Mic 2 setup (not present on desktop cards) */
7528 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7529 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7530 if (ca0132_quirk(spec) == QUIRK_R3DI)
7531 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7533 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7537 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7538 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7539 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7540 * having an updated DAC, which changes the destination to that DAC.
7542 static void sbz_connect_streams(struct hda_codec *codec)
7544 struct ca0132_spec *spec = codec->spec;
7546 mutex_lock(&spec->chipio_mutex);
7548 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7550 chipio_set_stream_channels(codec, 0x0C, 6);
7551 chipio_set_stream_control(codec, 0x0C, 1);
7553 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7554 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7556 /* Setup stream 0x14 with it's source and destination points */
7557 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7558 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7559 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7560 chipio_set_stream_channels(codec, 0x14, 2);
7561 chipio_set_stream_control(codec, 0x14, 1);
7563 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7565 mutex_unlock(&spec->chipio_mutex);
7569 * Write data through ChipIO to setup proper stream destinations.
7570 * Not sure how it exactly works, but it seems to direct data
7571 * to different destinations. Example is f8 to c0, e0 to c0.
7572 * All I know is, if you don't set these, you get no sound.
7574 static void sbz_chipio_startup_data(struct hda_codec *codec)
7576 struct ca0132_spec *spec = codec->spec;
7578 mutex_lock(&spec->chipio_mutex);
7579 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7581 /* These control audio output */
7582 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
7583 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
7584 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
7585 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
7586 /* Signal to update I think */
7587 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7589 chipio_set_stream_channels(codec, 0x0C, 6);
7590 chipio_set_stream_control(codec, 0x0C, 1);
7591 /* No clue what these control */
7592 if (ca0132_quirk(spec) == QUIRK_SBZ) {
7593 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
7594 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
7595 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
7596 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
7597 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
7598 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
7599 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
7600 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
7601 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
7602 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
7603 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
7604 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
7605 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
7606 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
7607 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
7608 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
7609 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
7610 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7611 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7612 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7613 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7615 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7617 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7618 mutex_unlock(&spec->chipio_mutex);
7622 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7623 * done after the DSP is loaded.
7625 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
7627 struct ca0132_spec *spec = codec->spec;
7628 unsigned int tmp, i;
7631 * Gotta run these twice, or else mic works inconsistently. Not clear
7632 * why this is, but multiple tests have confirmed it.
7634 for (i = 0; i < 2; i++) {
7635 switch (ca0132_quirk(spec)) {
7640 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7642 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7644 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7646 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7648 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7650 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7655 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7657 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7659 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7661 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7663 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7672 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7674 struct ca0132_spec *spec = codec->spec;
7677 chipio_set_stream_control(codec, 0x03, 0);
7678 chipio_set_stream_control(codec, 0x04, 0);
7680 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7681 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7684 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7686 chipio_set_stream_control(codec, 0x03, 1);
7687 chipio_set_stream_control(codec, 0x04, 1);
7689 switch (ca0132_quirk(spec)) {
7691 chipio_write(codec, 0x18b098, 0x0000000c);
7692 chipio_write(codec, 0x18b09C, 0x0000000c);
7695 chipio_write(codec, 0x18b098, 0x0000000c);
7696 chipio_write(codec, 0x18b09c, 0x0000004c);
7703 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7705 struct ca0132_spec *spec = codec->spec;
7707 chipio_8051_write_direct(codec, 0x93, 0x10);
7708 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7709 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7710 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7711 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7713 writeb(0xff, spec->mem_base + 0x304);
7714 writeb(0xff, spec->mem_base + 0x304);
7715 writeb(0xff, spec->mem_base + 0x304);
7716 writeb(0xff, spec->mem_base + 0x304);
7717 writeb(0x00, spec->mem_base + 0x100);
7718 writeb(0xff, spec->mem_base + 0x304);
7719 writeb(0x00, spec->mem_base + 0x100);
7720 writeb(0xff, spec->mem_base + 0x304);
7721 writeb(0x00, spec->mem_base + 0x100);
7722 writeb(0xff, spec->mem_base + 0x304);
7723 writeb(0x00, spec->mem_base + 0x100);
7724 writeb(0xff, spec->mem_base + 0x304);
7726 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7727 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7728 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7731 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7734 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7735 * which seems to be 'multichannel'. This is also mentioned in the
7736 * AE-5's registry values in Windows.
7738 chipio_set_control_param(codec, 3, 0);
7740 * I believe ASI is 'audio serial interface' and that it's used to
7741 * change colors on the external LED strip connected to the AE-5.
7743 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7745 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7746 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7748 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7749 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7750 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7751 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7752 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7753 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7756 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7758 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7759 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7760 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7761 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7763 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7764 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7765 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7766 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7768 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7769 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7770 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7771 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7773 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7774 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7776 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7778 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7779 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7780 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7781 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7784 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7786 struct ca0132_spec *spec = codec->spec;
7788 mutex_lock(&spec->chipio_mutex);
7790 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7792 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7794 chipio_set_stream_channels(codec, 0x0C, 6);
7795 chipio_set_stream_control(codec, 0x0C, 1);
7797 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7799 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7800 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7801 chipio_set_stream_channels(codec, 0x18, 6);
7802 chipio_set_stream_control(codec, 0x18, 1);
7804 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7806 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7807 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7809 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7811 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7813 mutex_unlock(&spec->chipio_mutex);
7816 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7818 struct ca0132_spec *spec = codec->spec;
7820 mutex_lock(&spec->chipio_mutex);
7822 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7823 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7824 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7825 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7827 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7828 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7829 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7830 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7831 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7832 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7833 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7834 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7835 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7836 ca0113_mmio_gpio_set(codec, 0, true);
7837 ca0113_mmio_gpio_set(codec, 1, true);
7838 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7840 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7842 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7843 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7845 mutex_unlock(&spec->chipio_mutex);
7848 static const unsigned int ae7_port_set_data[] = {
7849 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5,
7850 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb
7853 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7855 struct ca0132_spec *spec = codec->spec;
7856 unsigned int i, count, addr;
7858 mutex_lock(&spec->chipio_mutex);
7860 chipio_set_stream_channels(codec, 0x0c, 6);
7861 chipio_set_stream_control(codec, 0x0c, 1);
7863 count = ARRAY_SIZE(ae7_port_set_data);
7865 for (i = 0; i < count; i++) {
7866 chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]);
7868 /* Addresses are incremented by 4-bytes. */
7873 * Port setting always ends with a write of 0x1 to address 0x19042c.
7875 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7877 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7878 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7879 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7880 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7881 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7882 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7883 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7884 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7886 mutex_unlock(&spec->chipio_mutex);
7889 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
7891 struct ca0132_spec *spec = codec->spec;
7893 mutex_lock(&spec->chipio_mutex);
7895 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7896 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7898 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7899 chipio_set_stream_channels(codec, 0x0c, 6);
7900 chipio_set_stream_control(codec, 0x0c, 1);
7902 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7903 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7905 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7906 chipio_set_stream_channels(codec, 0x18, 6);
7907 chipio_set_stream_control(codec, 0x18, 1);
7909 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7911 mutex_unlock(&spec->chipio_mutex);
7914 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
7916 static const unsigned int addr[] = {
7917 0x41, 0x45, 0x40, 0x43, 0x51
7919 static const unsigned int data[] = {
7920 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
7924 for (i = 0; i < ARRAY_SIZE(addr); i++) {
7925 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7926 VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]);
7927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7928 VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]);
7932 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
7934 struct ca0132_spec *spec = codec->spec;
7935 static const unsigned int target[] = {
7936 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
7938 static const unsigned int data[] = {
7939 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
7943 mutex_lock(&spec->chipio_mutex);
7945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7946 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7947 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7948 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7950 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7951 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7952 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7953 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7955 ae7_post_dsp_pll_setup(codec);
7956 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7958 for (i = 0; i < ARRAY_SIZE(target); i++)
7959 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
7961 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7962 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7963 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7965 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
7966 chipio_set_stream_channels(codec, 0x21, 2);
7967 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
7969 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
7971 * In the 8051's memory, this param is referred to as 'n2sid', which I
7972 * believe is 'node to streamID'. It seems to be a way to assign a
7973 * stream to a given HDA node.
7975 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
7977 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
7980 * Now, at this point on Windows, an actual stream is setup and
7981 * seemingly sends data to the HDA node 0x09, which is the digital
7982 * audio input node. This is left out here, because obviously I don't
7983 * know what data is being sent. Interestingly, the AE-5 seems to go
7984 * through the motions of getting here and never actually takes this
7985 * step, but the AE-7 does.
7988 ca0113_mmio_gpio_set(codec, 0, 1);
7989 ca0113_mmio_gpio_set(codec, 1, 1);
7991 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7992 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
7993 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7994 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7996 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7997 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7999 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8000 chipio_set_stream_channels(codec, 0x18, 6);
8003 * Runs again, this has been repeated a few times, but I'm just
8004 * following what the Windows driver does.
8006 ae7_post_dsp_pll_setup(codec);
8007 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8009 mutex_unlock(&spec->chipio_mutex);
8013 * The Windows driver has commands that seem to setup ASI, which I believe to
8014 * be some sort of audio serial interface. My current speculation is that it's
8015 * related to communicating with the new DAC.
8017 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8019 chipio_8051_write_direct(codec, 0x93, 0x10);
8021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8022 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8024 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8026 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8027 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8029 chipio_set_control_param(codec, 3, 3);
8030 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8032 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8033 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8034 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8037 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
8038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8039 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
8040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8041 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
8043 ae7_post_dsp_pll_setup(codec);
8044 ae7_post_dsp_asi_stream_setup(codec);
8046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8047 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
8048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8049 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
8051 ae7_post_dsp_asi_setup_ports(codec);
8055 * Setup default parameters for DSP
8057 static void ca0132_setup_defaults(struct hda_codec *codec)
8059 struct ca0132_spec *spec = codec->spec;
8064 if (spec->dsp_state != DSP_DOWNLOADED)
8067 /* out, in effects + voicefx */
8068 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8069 for (idx = 0; idx < num_fx; idx++) {
8070 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8071 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8072 ca0132_effects[idx].reqs[i],
8073 ca0132_effects[idx].def_vals[i]);
8077 /*remove DSP headroom*/
8079 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8081 /*set speaker EQ bypass attenuation*/
8082 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8084 /* set AMic1 and AMic2 as mono mic */
8086 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8087 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8089 /* set AMic1 as CrystalVoice input */
8091 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8093 /* set WUH source */
8095 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8099 * Setup default parameters for Recon3D/Recon3Di DSP.
8102 static void r3d_setup_defaults(struct hda_codec *codec)
8104 struct ca0132_spec *spec = codec->spec;
8109 if (spec->dsp_state != DSP_DOWNLOADED)
8112 ca0132_alt_dsp_scp_startup(codec);
8113 ca0132_alt_init_analog_mics(codec);
8115 /*remove DSP headroom*/
8117 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8119 /* set WUH source */
8121 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8122 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8124 /* Set speaker source? */
8125 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8127 if (ca0132_quirk(spec) == QUIRK_R3DI)
8128 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8130 /* Disable mute on Center/LFE. */
8131 if (ca0132_quirk(spec) == QUIRK_R3D) {
8132 ca0113_mmio_gpio_set(codec, 2, false);
8133 ca0113_mmio_gpio_set(codec, 4, true);
8136 /* Setup effect defaults */
8137 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8138 for (idx = 0; idx < num_fx; idx++) {
8139 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8140 dspio_set_uint_param(codec,
8141 ca0132_effects[idx].mid,
8142 ca0132_effects[idx].reqs[i],
8143 ca0132_effects[idx].def_vals[i]);
8149 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8150 * than the Chromebook setup.
8152 static void sbz_setup_defaults(struct hda_codec *codec)
8154 struct ca0132_spec *spec = codec->spec;
8159 if (spec->dsp_state != DSP_DOWNLOADED)
8162 ca0132_alt_dsp_scp_startup(codec);
8163 ca0132_alt_init_analog_mics(codec);
8164 sbz_connect_streams(codec);
8165 sbz_chipio_startup_data(codec);
8167 chipio_set_stream_control(codec, 0x03, 1);
8168 chipio_set_stream_control(codec, 0x04, 1);
8171 * Sets internal input loopback to off, used to have a switch to
8172 * enable input loopback, but turned out to be way too buggy.
8175 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8176 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8178 /*remove DSP headroom*/
8180 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8182 /* set WUH source */
8184 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8185 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8187 /* Set speaker source? */
8188 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8190 ca0132_alt_dsp_initial_mic_setup(codec);
8192 /* out, in effects + voicefx */
8193 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8194 for (idx = 0; idx < num_fx; idx++) {
8195 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8196 dspio_set_uint_param(codec,
8197 ca0132_effects[idx].mid,
8198 ca0132_effects[idx].reqs[i],
8199 ca0132_effects[idx].def_vals[i]);
8203 ca0132_alt_init_speaker_tuning(codec);
8205 ca0132_alt_create_dummy_stream(codec);
8209 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8211 static void ae5_setup_defaults(struct hda_codec *codec)
8213 struct ca0132_spec *spec = codec->spec;
8218 if (spec->dsp_state != DSP_DOWNLOADED)
8221 ca0132_alt_dsp_scp_startup(codec);
8222 ca0132_alt_init_analog_mics(codec);
8223 chipio_set_stream_control(codec, 0x03, 1);
8224 chipio_set_stream_control(codec, 0x04, 1);
8226 /* New, unknown SCP req's */
8228 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8229 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8230 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8231 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8233 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8234 ca0113_mmio_gpio_set(codec, 0, false);
8235 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8237 /* Internal loopback off */
8239 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8240 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8242 /*remove DSP headroom*/
8244 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8246 /* set WUH source */
8248 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8249 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8251 /* Set speaker source? */
8252 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8254 ca0132_alt_dsp_initial_mic_setup(codec);
8255 ae5_post_dsp_register_set(codec);
8256 ae5_post_dsp_param_setup(codec);
8257 ae5_post_dsp_pll_setup(codec);
8258 ae5_post_dsp_stream_setup(codec);
8259 ae5_post_dsp_startup_data(codec);
8261 /* out, in effects + voicefx */
8262 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8263 for (idx = 0; idx < num_fx; idx++) {
8264 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8265 dspio_set_uint_param(codec,
8266 ca0132_effects[idx].mid,
8267 ca0132_effects[idx].reqs[i],
8268 ca0132_effects[idx].def_vals[i]);
8272 ca0132_alt_init_speaker_tuning(codec);
8274 ca0132_alt_create_dummy_stream(codec);
8278 * Setup default parameters for the Sound Blaster AE-7 DSP.
8280 static void ae7_setup_defaults(struct hda_codec *codec)
8282 struct ca0132_spec *spec = codec->spec;
8287 if (spec->dsp_state != DSP_DOWNLOADED)
8290 ca0132_alt_dsp_scp_startup(codec);
8291 ca0132_alt_init_analog_mics(codec);
8292 ae7_post_dsp_setup_ports(codec);
8295 dspio_set_uint_param(codec, 0x96,
8296 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8297 dspio_set_uint_param(codec, 0x96,
8298 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8300 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8302 /* New, unknown SCP req's */
8303 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8304 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8306 ca0113_mmio_gpio_set(codec, 0, false);
8308 /* Internal loopback off */
8310 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8311 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8313 /*remove DSP headroom*/
8315 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8317 /* set WUH source */
8319 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8320 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8322 /* Set speaker source? */
8323 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8324 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8327 * This is the second time we've called this, but this is seemingly
8328 * what Windows does.
8330 ca0132_alt_init_analog_mics(codec);
8332 ae7_post_dsp_asi_setup(codec);
8335 * Not sure why, but these are both set to 1. They're only set to 0
8338 ca0113_mmio_gpio_set(codec, 0, true);
8339 ca0113_mmio_gpio_set(codec, 1, true);
8341 /* Volume control related. */
8342 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8343 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8344 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8346 /* out, in effects + voicefx */
8347 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8348 for (idx = 0; idx < num_fx; idx++) {
8349 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8350 dspio_set_uint_param(codec,
8351 ca0132_effects[idx].mid,
8352 ca0132_effects[idx].reqs[i],
8353 ca0132_effects[idx].def_vals[i]);
8357 ca0132_alt_init_speaker_tuning(codec);
8359 ca0132_alt_create_dummy_stream(codec);
8363 * Initialization of flags in chip
8365 static void ca0132_init_flags(struct hda_codec *codec)
8367 struct ca0132_spec *spec = codec->spec;
8369 if (ca0132_use_alt_functions(spec)) {
8370 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8371 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8372 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8373 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8374 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8375 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8376 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8377 chipio_set_control_flag(codec,
8378 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8379 chipio_set_control_flag(codec,
8380 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8382 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8383 chipio_set_control_flag(codec,
8384 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8385 chipio_set_control_flag(codec,
8386 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8387 chipio_set_control_flag(codec,
8388 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8389 chipio_set_control_flag(codec,
8390 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8391 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8396 * Initialization of parameters in chip
8398 static void ca0132_init_params(struct hda_codec *codec)
8400 struct ca0132_spec *spec = codec->spec;
8402 if (ca0132_use_alt_functions(spec)) {
8403 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8404 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8405 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8406 chipio_set_control_param(codec, 0, 0);
8407 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8410 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8411 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8414 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8416 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8417 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8418 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8419 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8420 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8421 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8423 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8424 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8425 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8428 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8430 bool dsp_loaded = false;
8431 struct ca0132_spec *spec = codec->spec;
8432 const struct dsp_image_seg *dsp_os_image;
8433 const struct firmware *fw_entry = NULL;
8435 * Alternate firmwares for different variants. The Recon3Di apparently
8436 * can use the default firmware, but I'll leave the option in case
8437 * it needs it again.
8439 switch (ca0132_quirk(spec)) {
8443 if (reject_firmware(&fw_entry, DESKTOP_EFX_FILE,
8444 codec->card->dev) != 0)
8445 codec_dbg(codec, "Desktop firmware not found.");
8447 codec_dbg(codec, "Desktop firmware selected.");
8450 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
8451 codec->card->dev) != 0)
8452 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8454 codec_dbg(codec, "Recon3Di firmware selected.");
8461 codec_dbg(codec, "Default firmware selected.");
8462 if (reject_firmware(&fw_entry, EFX_FILE,
8463 codec->card->dev) != 0)
8467 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8468 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8469 codec_err(codec, "ca0132 DSP load image failed\n");
8473 dsp_loaded = dspload_wait_loaded(codec);
8476 release_firmware(fw_entry);
8481 static void ca0132_download_dsp(struct hda_codec *codec)
8483 struct ca0132_spec *spec = codec->spec;
8485 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8489 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8490 return; /* don't retry failures */
8492 chipio_enable_clocks(codec);
8493 if (spec->dsp_state != DSP_DOWNLOADED) {
8494 spec->dsp_state = DSP_DOWNLOADING;
8496 if (!ca0132_download_dsp_images(codec))
8497 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8499 spec->dsp_state = DSP_DOWNLOADED;
8502 /* For codecs using alt functions, this is already done earlier */
8503 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8504 ca0132_set_dsp_msr(codec, true);
8507 static void ca0132_process_dsp_response(struct hda_codec *codec,
8508 struct hda_jack_callback *callback)
8510 struct ca0132_spec *spec = codec->spec;
8512 codec_dbg(codec, "ca0132_process_dsp_response\n");
8513 snd_hda_power_up_pm(codec);
8514 if (spec->wait_scp) {
8515 if (dspio_get_response_data(codec) >= 0)
8519 dspio_clear_response_queue(codec);
8520 snd_hda_power_down_pm(codec);
8523 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8525 struct ca0132_spec *spec = codec->spec;
8526 struct hda_jack_tbl *tbl;
8528 /* Delay enabling the HP amp, to let the mic-detection
8529 * state machine run.
8531 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8533 tbl->block_report = 1;
8534 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8537 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8539 struct ca0132_spec *spec = codec->spec;
8541 if (ca0132_use_alt_functions(spec))
8542 ca0132_alt_select_in(codec);
8544 ca0132_select_mic(codec);
8547 static void ca0132_init_unsol(struct hda_codec *codec)
8549 struct ca0132_spec *spec = codec->spec;
8550 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8551 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8553 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8554 ca0132_process_dsp_response);
8555 /* Front headphone jack detection */
8556 if (ca0132_use_alt_functions(spec))
8557 snd_hda_jack_detect_enable_callback(codec,
8558 spec->unsol_tag_front_hp, hp_callback);
8565 /* Sends before DSP download. */
8566 static const struct hda_verb ca0132_base_init_verbs[] = {
8567 /*enable ct extension*/
8568 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8573 static const struct hda_verb ca0132_base_exit_verbs[] = {
8575 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8576 /*disable ct extension*/
8577 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8581 /* Other verbs tables. Sends after DSP download. */
8583 static const struct hda_verb ca0132_init_verbs0[] = {
8584 /* chip init verbs */
8585 {0x15, 0x70D, 0xF0},
8586 {0x15, 0x70E, 0xFE},
8587 {0x15, 0x707, 0x75},
8588 {0x15, 0x707, 0xD3},
8589 {0x15, 0x707, 0x09},
8590 {0x15, 0x707, 0x53},
8591 {0x15, 0x707, 0xD4},
8592 {0x15, 0x707, 0xEF},
8593 {0x15, 0x707, 0x75},
8594 {0x15, 0x707, 0xD3},
8595 {0x15, 0x707, 0x09},
8596 {0x15, 0x707, 0x02},
8597 {0x15, 0x707, 0x37},
8598 {0x15, 0x707, 0x78},
8599 {0x15, 0x53C, 0xCE},
8600 {0x15, 0x575, 0xC9},
8601 {0x15, 0x53D, 0xCE},
8602 {0x15, 0x5B7, 0xC9},
8603 {0x15, 0x70D, 0xE8},
8604 {0x15, 0x70E, 0xFE},
8605 {0x15, 0x707, 0x02},
8606 {0x15, 0x707, 0x68},
8607 {0x15, 0x707, 0x62},
8608 {0x15, 0x53A, 0xCE},
8609 {0x15, 0x546, 0xC9},
8610 {0x15, 0x53B, 0xCE},
8611 {0x15, 0x5E8, 0xC9},
8615 /* Extra init verbs for desktop cards. */
8616 static const struct hda_verb ca0132_init_verbs1[] = {
8617 {0x15, 0x70D, 0x20},
8618 {0x15, 0x70E, 0x19},
8619 {0x15, 0x707, 0x00},
8620 {0x15, 0x539, 0xCE},
8621 {0x15, 0x546, 0xC9},
8622 {0x15, 0x70D, 0xB7},
8623 {0x15, 0x70E, 0x09},
8624 {0x15, 0x707, 0x10},
8625 {0x15, 0x70D, 0xAF},
8626 {0x15, 0x70E, 0x09},
8627 {0x15, 0x707, 0x01},
8628 {0x15, 0x707, 0x05},
8629 {0x15, 0x70D, 0x73},
8630 {0x15, 0x70E, 0x09},
8631 {0x15, 0x707, 0x14},
8632 {0x15, 0x6FF, 0xC4},
8636 static void ca0132_init_chip(struct hda_codec *codec)
8638 struct ca0132_spec *spec = codec->spec;
8643 mutex_init(&spec->chipio_mutex);
8645 spec->cur_out_type = SPEAKER_OUT;
8646 if (!ca0132_use_alt_functions(spec))
8647 spec->cur_mic_type = DIGITAL_MIC;
8649 spec->cur_mic_type = REAR_MIC;
8651 spec->cur_mic_boost = 0;
8653 for (i = 0; i < VNODES_COUNT; i++) {
8654 spec->vnode_lvol[i] = 0x5a;
8655 spec->vnode_rvol[i] = 0x5a;
8656 spec->vnode_lswitch[i] = 0;
8657 spec->vnode_rswitch[i] = 0;
8661 * Default states for effects are in ca0132_effects[].
8663 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8664 for (i = 0; i < num_fx; i++) {
8665 on = (unsigned int)ca0132_effects[i].reqs[0];
8666 spec->effects_switch[i] = on ? 1 : 0;
8669 * Sets defaults for the effect slider controls, only for alternative
8670 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8672 if (ca0132_use_alt_controls(spec)) {
8673 /* Set speakers to default to full range. */
8674 spec->speaker_range_val[0] = 1;
8675 spec->speaker_range_val[1] = 1;
8677 spec->xbass_xover_freq = 8;
8678 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8679 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8681 spec->bass_redirect_xover_freq = 8;
8684 spec->voicefx_val = 0;
8685 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8686 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8689 * The ZxR doesn't have a front panel header, and it's line-in is on
8690 * the daughter board. So, there is no input enum control, and we need
8691 * to make sure that spec->in_enum_val is set properly.
8693 if (ca0132_quirk(spec) == QUIRK_ZXR)
8694 spec->in_enum_val = REAR_MIC;
8696 #ifdef ENABLE_TUNING_CONTROLS
8697 ca0132_init_tuning_defaults(codec);
8702 * Recon3Di exit specific commands.
8704 /* prevents popping noise on shutdown */
8705 static void r3di_gpio_shutdown(struct hda_codec *codec)
8707 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8711 * Sound Blaster Z exit specific commands.
8713 static void sbz_region2_exit(struct hda_codec *codec)
8715 struct ca0132_spec *spec = codec->spec;
8718 for (i = 0; i < 4; i++)
8719 writeb(0x0, spec->mem_base + 0x100);
8720 for (i = 0; i < 8; i++)
8721 writeb(0xb3, spec->mem_base + 0x304);
8723 ca0113_mmio_gpio_set(codec, 0, false);
8724 ca0113_mmio_gpio_set(codec, 1, false);
8725 ca0113_mmio_gpio_set(codec, 4, true);
8726 ca0113_mmio_gpio_set(codec, 5, false);
8727 ca0113_mmio_gpio_set(codec, 7, false);
8730 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8732 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8735 snd_hda_codec_write(codec, 0x11, 0,
8736 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8738 for (i = 0; i < ARRAY_SIZE(pins); i++)
8739 snd_hda_codec_write(codec, pins[i], 0,
8740 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8743 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8745 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8748 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8749 snd_hda_codec_write(codec, pins[i], 0,
8750 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8754 /* On shutdown, sends commands in sets of three */
8755 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8759 snd_hda_codec_write(codec, 0x01, 0,
8760 AC_VERB_SET_GPIO_DIRECTION, dir);
8762 snd_hda_codec_write(codec, 0x01, 0,
8763 AC_VERB_SET_GPIO_MASK, mask);
8766 snd_hda_codec_write(codec, 0x01, 0,
8767 AC_VERB_SET_GPIO_DATA, data);
8770 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8772 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8775 for (i = 0; i < ARRAY_SIZE(pins); i++)
8776 snd_hda_codec_write(codec, pins[i], 0,
8777 AC_VERB_SET_POWER_STATE, 0x03);
8780 static void sbz_exit_chip(struct hda_codec *codec)
8782 chipio_set_stream_control(codec, 0x03, 0);
8783 chipio_set_stream_control(codec, 0x04, 0);
8785 /* Mess with GPIO */
8786 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8787 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8788 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8790 chipio_set_stream_control(codec, 0x14, 0);
8791 chipio_set_stream_control(codec, 0x0C, 0);
8793 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8794 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8796 chipio_write(codec, 0x18a020, 0x00000083);
8798 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8799 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8800 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8802 chipio_set_stream_control(codec, 0x0C, 0);
8804 chipio_set_control_param(codec, 0x0D, 0x24);
8806 ca0132_clear_unsolicited(codec);
8807 sbz_set_pin_ctl_default(codec);
8809 snd_hda_codec_write(codec, 0x0B, 0,
8810 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8812 sbz_region2_exit(codec);
8815 static void r3d_exit_chip(struct hda_codec *codec)
8817 ca0132_clear_unsolicited(codec);
8818 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8819 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8822 static void ae5_exit_chip(struct hda_codec *codec)
8824 chipio_set_stream_control(codec, 0x03, 0);
8825 chipio_set_stream_control(codec, 0x04, 0);
8827 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8828 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8829 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8830 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8831 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8832 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8833 ca0113_mmio_gpio_set(codec, 0, false);
8834 ca0113_mmio_gpio_set(codec, 1, false);
8836 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8837 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8839 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8841 chipio_set_stream_control(codec, 0x18, 0);
8842 chipio_set_stream_control(codec, 0x0c, 0);
8844 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8847 static void ae7_exit_chip(struct hda_codec *codec)
8849 chipio_set_stream_control(codec, 0x18, 0);
8850 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8851 chipio_set_stream_channels(codec, 0x21, 0);
8852 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8853 chipio_set_control_param(codec, 0x20, 0x01);
8855 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8857 chipio_set_stream_control(codec, 0x18, 0);
8858 chipio_set_stream_control(codec, 0x0c, 0);
8860 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8861 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8862 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8863 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8864 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8865 ca0113_mmio_gpio_set(codec, 0, false);
8866 ca0113_mmio_gpio_set(codec, 1, false);
8867 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8869 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8870 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8873 static void zxr_exit_chip(struct hda_codec *codec)
8875 chipio_set_stream_control(codec, 0x03, 0);
8876 chipio_set_stream_control(codec, 0x04, 0);
8877 chipio_set_stream_control(codec, 0x14, 0);
8878 chipio_set_stream_control(codec, 0x0C, 0);
8880 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8881 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8883 chipio_write(codec, 0x18a020, 0x00000083);
8885 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8886 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8888 ca0132_clear_unsolicited(codec);
8889 sbz_set_pin_ctl_default(codec);
8890 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8892 ca0113_mmio_gpio_set(codec, 5, false);
8893 ca0113_mmio_gpio_set(codec, 2, false);
8894 ca0113_mmio_gpio_set(codec, 3, false);
8895 ca0113_mmio_gpio_set(codec, 0, false);
8896 ca0113_mmio_gpio_set(codec, 4, true);
8897 ca0113_mmio_gpio_set(codec, 0, true);
8898 ca0113_mmio_gpio_set(codec, 5, true);
8899 ca0113_mmio_gpio_set(codec, 2, false);
8900 ca0113_mmio_gpio_set(codec, 3, false);
8903 static void ca0132_exit_chip(struct hda_codec *codec)
8905 /* put any chip cleanup stuffs here. */
8907 if (dspload_is_loaded(codec))
8912 * This fixes a problem that was hard to reproduce. Very rarely, I would
8913 * boot up, and there would be no sound, but the DSP indicated it had loaded
8914 * properly. I did a few memory dumps to see if anything was different, and
8915 * there were a few areas of memory uninitialized with a1a2a3a4. This function
8916 * checks if those areas are uninitialized, and if they are, it'll attempt to
8917 * reload the card 3 times. Usually it fixes by the second.
8919 static void sbz_dsp_startup_check(struct hda_codec *codec)
8921 struct ca0132_spec *spec = codec->spec;
8922 unsigned int dsp_data_check[4];
8923 unsigned int cur_address = 0x390;
8925 unsigned int failure = 0;
8926 unsigned int reload = 3;
8928 if (spec->startup_check_entered)
8931 spec->startup_check_entered = true;
8933 for (i = 0; i < 4; i++) {
8934 chipio_read(codec, cur_address, &dsp_data_check[i]);
8937 for (i = 0; i < 4; i++) {
8938 if (dsp_data_check[i] == 0xa1a2a3a4)
8942 codec_dbg(codec, "Startup Check: %d ", failure);
8944 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8946 * While the failure condition is true, and we haven't reached our
8947 * three reload limit, continue trying to reload the driver and
8950 while (failure && (reload != 0)) {
8951 codec_info(codec, "Reloading... Tries left: %d", reload);
8952 sbz_exit_chip(codec);
8953 spec->dsp_state = DSP_DOWNLOAD_INIT;
8954 codec->patch_ops.init(codec);
8956 for (i = 0; i < 4; i++) {
8957 chipio_read(codec, cur_address, &dsp_data_check[i]);
8960 for (i = 0; i < 4; i++) {
8961 if (dsp_data_check[i] == 0xa1a2a3a4)
8967 if (!failure && reload < 3)
8968 codec_info(codec, "DSP fixed.");
8973 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8977 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8978 * extra precision for decibel values. If you had the dB value in floating point
8979 * you would take the value after the decimal point, multiply by 64, and divide
8980 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8981 * implement fixed point or floating point dB volumes. For now, I'll set them
8982 * to 0 just incase a value has lingered from a boot into Windows.
8984 static void ca0132_alt_vol_setup(struct hda_codec *codec)
8986 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8987 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8988 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8989 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8990 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8991 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8992 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8993 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8997 * Extra commands that don't really fit anywhere else.
8999 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9001 struct ca0132_spec *spec = codec->spec;
9003 writel(0x00820680, spec->mem_base + 0x01C);
9004 writel(0x00820680, spec->mem_base + 0x01C);
9006 chipio_write(codec, 0x18b0a4, 0x000000c2);
9008 snd_hda_codec_write(codec, 0x11, 0,
9009 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9012 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9014 chipio_write(codec, 0x18b0a4, 0x000000c2);
9016 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9017 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9019 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9021 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9023 snd_hda_codec_write(codec, 0x11, 0,
9024 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9027 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9029 chipio_write(codec, 0x18b0a4, 0x000000c2);
9031 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9032 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9034 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9036 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9039 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
9040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9041 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
9042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9043 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
9044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9045 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
9047 snd_hda_codec_write(codec, 0x11, 0,
9048 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9052 * These are sent before the DSP is downloaded. Not sure
9053 * what they do, or if they're necessary. Could possibly
9054 * be removed. Figure they're better to leave in.
9056 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9057 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9058 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9061 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9062 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9063 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9064 0x000000c1, 0x00000080
9067 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9068 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9069 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9070 0x000000c1, 0x00000080
9073 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9074 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9075 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9076 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9077 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9080 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9081 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9083 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9084 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9085 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9086 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9087 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9088 0x00000080, 0x00880680
9091 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9093 struct ca0132_spec *spec = codec->spec;
9094 unsigned int tmp[2], i, count, cur_addr;
9095 const unsigned int *addr, *data;
9097 addr = ca0113_mmio_init_address_sbz;
9098 for (i = 0; i < 3; i++)
9099 writel(0x00000000, spec->mem_base + addr[i]);
9102 switch (ca0132_quirk(spec)) {
9104 tmp[0] = 0x00880480;
9105 tmp[1] = 0x00000080;
9108 tmp[0] = 0x00820680;
9109 tmp[1] = 0x00000083;
9112 tmp[0] = 0x00880680;
9113 tmp[1] = 0x00000083;
9116 tmp[0] = 0x00000000;
9117 tmp[1] = 0x00000000;
9121 for (i = 0; i < 2; i++)
9122 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9126 switch (ca0132_quirk(spec)) {
9128 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9129 data = ca0113_mmio_init_data_zxr;
9132 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9133 data = ca0113_mmio_init_data_sbz;
9137 for (i = 0; i < count; i++)
9138 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9141 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9143 struct ca0132_spec *spec = codec->spec;
9144 const unsigned int *addr, *data;
9145 unsigned int i, count;
9147 addr = ca0113_mmio_init_address_ae5;
9148 data = ca0113_mmio_init_data_ae5;
9149 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9151 if (ca0132_quirk(spec) == QUIRK_AE7) {
9152 writel(0x00000680, spec->mem_base + 0x1c);
9153 writel(0x00880680, spec->mem_base + 0x1c);
9156 for (i = 0; i < count; i++) {
9158 * AE-7 shares all writes with the AE-5, except that it writes
9159 * a different value to 0x20c.
9161 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9162 writel(0x00800001, spec->mem_base + addr[i]);
9166 writel(data[i], spec->mem_base + addr[i]);
9169 if (ca0132_quirk(spec) == QUIRK_AE5)
9170 writel(0x00880680, spec->mem_base + 0x1c);
9173 static void ca0132_mmio_init(struct hda_codec *codec)
9175 struct ca0132_spec *spec = codec->spec;
9177 switch (ca0132_quirk(spec)) {
9181 ca0132_mmio_init_sbz(codec);
9184 ca0132_mmio_init_ae5(codec);
9191 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9192 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9193 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9196 static const unsigned char ca0132_ae5_register_set_data[] = {
9197 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9202 * This function writes to some SFR's, does some region2 writes, and then
9203 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9206 static void ae5_register_set(struct hda_codec *codec)
9208 struct ca0132_spec *spec = codec->spec;
9209 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9210 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9211 const unsigned char *data = ca0132_ae5_register_set_data;
9212 unsigned int i, cur_addr;
9213 unsigned char tmp[3];
9215 if (ca0132_quirk(spec) == QUIRK_AE7) {
9216 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9217 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
9218 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9219 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
9222 chipio_8051_write_direct(codec, 0x93, 0x10);
9223 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9224 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
9225 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9226 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
9228 if (ca0132_quirk(spec) == QUIRK_AE7) {
9238 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9239 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9242 * First writes are in single bytes, final are in 4 bytes. So, we use
9243 * writeb, then writel.
9245 for (i = 0; cur_addr < 12; i++, cur_addr++)
9246 writeb(data[i], spec->mem_base + addr[cur_addr]);
9248 for (; cur_addr < count; i++, cur_addr++)
9249 writel(data[i], spec->mem_base + addr[cur_addr]);
9251 writel(0x00800001, spec->mem_base + 0x20c);
9253 if (ca0132_quirk(spec) == QUIRK_AE7) {
9254 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9255 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9257 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9260 chipio_8051_write_direct(codec, 0x90, 0x00);
9261 chipio_8051_write_direct(codec, 0x90, 0x10);
9263 if (ca0132_quirk(spec) == QUIRK_AE5)
9264 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9266 chipio_write(codec, 0x18b0a4, 0x000000c2);
9268 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9269 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9273 * Extra init functions for alternative ca0132 codecs. Done
9274 * here so they don't clutter up the main ca0132_init function
9275 * anymore than they have to.
9277 static void ca0132_alt_init(struct hda_codec *codec)
9279 struct ca0132_spec *spec = codec->spec;
9281 ca0132_alt_vol_setup(codec);
9283 switch (ca0132_quirk(spec)) {
9285 codec_dbg(codec, "SBZ alt_init");
9286 ca0132_gpio_init(codec);
9287 sbz_pre_dsp_setup(codec);
9288 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9289 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9292 codec_dbg(codec, "R3DI alt_init");
9293 ca0132_gpio_init(codec);
9294 ca0132_gpio_setup(codec);
9295 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9296 r3di_pre_dsp_setup(codec);
9297 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9298 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9301 r3d_pre_dsp_setup(codec);
9302 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9303 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9306 ca0132_gpio_init(codec);
9307 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9308 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9309 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9310 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9311 chipio_write(codec, 0x18b030, 0x00000020);
9312 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9313 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9314 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9317 ca0132_gpio_init(codec);
9318 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9319 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9320 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9321 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9322 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9323 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9324 chipio_write(codec, 0x18b008, 0x000000f8);
9325 chipio_write(codec, 0x18b008, 0x000000f0);
9326 chipio_write(codec, 0x18b030, 0x00000020);
9327 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9330 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9331 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9338 static int ca0132_init(struct hda_codec *codec)
9340 struct ca0132_spec *spec = codec->spec;
9341 struct auto_pin_cfg *cfg = &spec->autocfg;
9346 * If the DSP is already downloaded, and init has been entered again,
9347 * there's only two reasons for it. One, the codec has awaken from a
9348 * suspended state, and in that case dspload_is_loaded will return
9349 * false, and the init will be ran again. The other reason it gets
9350 * re entered is on startup for some reason it triggers a suspend and
9351 * resume state. In this case, it will check if the DSP is downloaded,
9352 * and not run the init function again. For codecs using alt_functions,
9353 * it will check if the DSP is loaded properly.
9355 if (spec->dsp_state == DSP_DOWNLOADED) {
9356 dsp_loaded = dspload_is_loaded(codec);
9358 spec->dsp_reload = true;
9359 spec->dsp_state = DSP_DOWNLOAD_INIT;
9361 if (ca0132_quirk(spec) == QUIRK_SBZ)
9362 sbz_dsp_startup_check(codec);
9367 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9368 spec->dsp_state = DSP_DOWNLOAD_INIT;
9369 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9371 if (ca0132_use_pci_mmio(spec))
9372 ca0132_mmio_init(codec);
9374 snd_hda_power_up_pm(codec);
9376 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9377 ae5_register_set(codec);
9379 ca0132_init_unsol(codec);
9380 ca0132_init_params(codec);
9381 ca0132_init_flags(codec);
9383 snd_hda_sequence_write(codec, spec->base_init_verbs);
9385 if (ca0132_use_alt_functions(spec))
9386 ca0132_alt_init(codec);
9388 ca0132_download_dsp(codec);
9390 ca0132_refresh_widget_caps(codec);
9392 switch (ca0132_quirk(spec)) {
9395 r3d_setup_defaults(codec);
9399 sbz_setup_defaults(codec);
9402 ae5_setup_defaults(codec);
9405 ae7_setup_defaults(codec);
9408 ca0132_setup_defaults(codec);
9409 ca0132_init_analog_mic2(codec);
9410 ca0132_init_dmic(codec);
9414 for (i = 0; i < spec->num_outputs; i++)
9415 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9417 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9419 for (i = 0; i < spec->num_inputs; i++)
9420 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9422 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9424 if (!ca0132_use_alt_functions(spec)) {
9425 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9426 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9427 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9428 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9429 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9432 if (ca0132_quirk(spec) == QUIRK_SBZ)
9433 ca0132_gpio_setup(codec);
9435 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9436 if (ca0132_use_alt_functions(spec)) {
9437 ca0132_alt_select_out(codec);
9438 ca0132_alt_select_in(codec);
9440 ca0132_select_out(codec);
9441 ca0132_select_mic(codec);
9444 snd_hda_jack_report_sync(codec);
9447 * Re set the PlayEnhancement switch on a resume event, because the
9448 * controls will not be reloaded.
9450 if (spec->dsp_reload) {
9451 spec->dsp_reload = false;
9452 ca0132_pe_switch_set(codec);
9455 snd_hda_power_down_pm(codec);
9460 static int dbpro_init(struct hda_codec *codec)
9462 struct ca0132_spec *spec = codec->spec;
9463 struct auto_pin_cfg *cfg = &spec->autocfg;
9466 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9467 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9469 for (i = 0; i < spec->num_inputs; i++)
9470 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9475 static void ca0132_free(struct hda_codec *codec)
9477 struct ca0132_spec *spec = codec->spec;
9479 cancel_delayed_work_sync(&spec->unsol_hp_work);
9480 snd_hda_power_up(codec);
9481 switch (ca0132_quirk(spec)) {
9483 sbz_exit_chip(codec);
9486 zxr_exit_chip(codec);
9489 r3d_exit_chip(codec);
9492 ae5_exit_chip(codec);
9495 ae7_exit_chip(codec);
9498 r3di_gpio_shutdown(codec);
9504 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9505 ca0132_exit_chip(codec);
9507 snd_hda_power_down(codec);
9510 pci_iounmap(codec->bus->pci, spec->mem_base);
9512 kfree(spec->spec_init_verbs);
9516 static void dbpro_free(struct hda_codec *codec)
9518 struct ca0132_spec *spec = codec->spec;
9520 zxr_dbpro_power_state_shutdown(codec);
9522 kfree(spec->spec_init_verbs);
9526 static void ca0132_reboot_notify(struct hda_codec *codec)
9528 codec->patch_ops.free(codec);
9532 static int ca0132_suspend(struct hda_codec *codec)
9534 struct ca0132_spec *spec = codec->spec;
9536 cancel_delayed_work_sync(&spec->unsol_hp_work);
9541 static const struct hda_codec_ops ca0132_patch_ops = {
9542 .build_controls = ca0132_build_controls,
9543 .build_pcms = ca0132_build_pcms,
9544 .init = ca0132_init,
9545 .free = ca0132_free,
9546 .unsol_event = snd_hda_jack_unsol_event,
9548 .suspend = ca0132_suspend,
9550 .reboot_notify = ca0132_reboot_notify,
9553 static const struct hda_codec_ops dbpro_patch_ops = {
9554 .build_controls = dbpro_build_controls,
9555 .build_pcms = dbpro_build_pcms,
9560 static void ca0132_config(struct hda_codec *codec)
9562 struct ca0132_spec *spec = codec->spec;
9564 spec->dacs[0] = 0x2;
9565 spec->dacs[1] = 0x3;
9566 spec->dacs[2] = 0x4;
9568 spec->multiout.dac_nids = spec->dacs;
9569 spec->multiout.num_dacs = 3;
9571 if (!ca0132_use_alt_functions(spec))
9572 spec->multiout.max_channels = 2;
9574 spec->multiout.max_channels = 6;
9576 switch (ca0132_quirk(spec)) {
9577 case QUIRK_ALIENWARE:
9578 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9579 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9582 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9583 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9586 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9587 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9590 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9591 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9594 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9595 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9598 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9599 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9602 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9603 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9609 switch (ca0132_quirk(spec)) {
9610 case QUIRK_ALIENWARE:
9611 spec->num_outputs = 2;
9612 spec->out_pins[0] = 0x0b; /* speaker out */
9613 spec->out_pins[1] = 0x0f;
9614 spec->shared_out_nid = 0x2;
9615 spec->unsol_tag_hp = 0x0f;
9617 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9618 spec->adcs[1] = 0x8; /* analog mic2 */
9619 spec->adcs[2] = 0xa; /* what u hear */
9621 spec->num_inputs = 3;
9622 spec->input_pins[0] = 0x12;
9623 spec->input_pins[1] = 0x11;
9624 spec->input_pins[2] = 0x13;
9625 spec->shared_mic_nid = 0x7;
9626 spec->unsol_tag_amic1 = 0x11;
9630 spec->num_outputs = 2;
9631 spec->out_pins[0] = 0x0B; /* Line out */
9632 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9633 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9634 spec->out_pins[3] = 0x11; /* Rear surround */
9635 spec->shared_out_nid = 0x2;
9636 spec->unsol_tag_hp = spec->out_pins[1];
9637 spec->unsol_tag_front_hp = spec->out_pins[2];
9639 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9640 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9641 spec->adcs[2] = 0xa; /* what u hear */
9643 spec->num_inputs = 2;
9644 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9645 spec->input_pins[1] = 0x13; /* What U Hear */
9646 spec->shared_mic_nid = 0x7;
9647 spec->unsol_tag_amic1 = spec->input_pins[0];
9650 spec->dig_out = 0x05;
9651 spec->multiout.dig_out_nid = spec->dig_out;
9652 spec->dig_in = 0x09;
9655 spec->num_outputs = 2;
9656 spec->out_pins[0] = 0x0B; /* Line out */
9657 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9658 spec->out_pins[2] = 0x10; /* Center/LFE */
9659 spec->out_pins[3] = 0x11; /* Rear surround */
9660 spec->shared_out_nid = 0x2;
9661 spec->unsol_tag_hp = spec->out_pins[1];
9662 spec->unsol_tag_front_hp = spec->out_pins[2];
9664 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9665 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9666 spec->adcs[2] = 0xa; /* what u hear */
9668 spec->num_inputs = 2;
9669 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9670 spec->input_pins[1] = 0x13; /* What U Hear */
9671 spec->shared_mic_nid = 0x7;
9672 spec->unsol_tag_amic1 = spec->input_pins[0];
9674 case QUIRK_ZXR_DBPRO:
9675 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9677 spec->num_inputs = 1;
9678 spec->input_pins[0] = 0x11; /* RCA Line-in */
9680 spec->dig_out = 0x05;
9681 spec->multiout.dig_out_nid = spec->dig_out;
9683 spec->dig_in = 0x09;
9687 spec->num_outputs = 2;
9688 spec->out_pins[0] = 0x0B; /* Line out */
9689 spec->out_pins[1] = 0x11; /* Rear headphone out */
9690 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9691 spec->out_pins[3] = 0x0F; /* Rear surround */
9692 spec->shared_out_nid = 0x2;
9693 spec->unsol_tag_hp = spec->out_pins[1];
9694 spec->unsol_tag_front_hp = spec->out_pins[2];
9696 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9697 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9698 spec->adcs[2] = 0xa; /* what u hear */
9700 spec->num_inputs = 2;
9701 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9702 spec->input_pins[1] = 0x13; /* What U Hear */
9703 spec->shared_mic_nid = 0x7;
9704 spec->unsol_tag_amic1 = spec->input_pins[0];
9707 spec->dig_out = 0x05;
9708 spec->multiout.dig_out_nid = spec->dig_out;
9711 spec->num_outputs = 2;
9712 spec->out_pins[0] = 0x0B; /* Line out */
9713 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9714 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9715 spec->out_pins[3] = 0x11; /* Rear surround */
9716 spec->shared_out_nid = 0x2;
9717 spec->unsol_tag_hp = spec->out_pins[1];
9718 spec->unsol_tag_front_hp = spec->out_pins[2];
9720 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9721 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9722 spec->adcs[2] = 0x0a; /* what u hear */
9724 spec->num_inputs = 2;
9725 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9726 spec->input_pins[1] = 0x13; /* What U Hear */
9727 spec->shared_mic_nid = 0x7;
9728 spec->unsol_tag_amic1 = spec->input_pins[0];
9731 spec->dig_out = 0x05;
9732 spec->multiout.dig_out_nid = spec->dig_out;
9735 spec->num_outputs = 2;
9736 spec->out_pins[0] = 0x0b; /* speaker out */
9737 spec->out_pins[1] = 0x10; /* headphone out */
9738 spec->shared_out_nid = 0x2;
9739 spec->unsol_tag_hp = spec->out_pins[1];
9741 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9742 spec->adcs[1] = 0x8; /* analog mic2 */
9743 spec->adcs[2] = 0xa; /* what u hear */
9745 spec->num_inputs = 3;
9746 spec->input_pins[0] = 0x12;
9747 spec->input_pins[1] = 0x11;
9748 spec->input_pins[2] = 0x13;
9749 spec->shared_mic_nid = 0x7;
9750 spec->unsol_tag_amic1 = spec->input_pins[0];
9753 spec->dig_out = 0x05;
9754 spec->multiout.dig_out_nid = spec->dig_out;
9755 spec->dig_in = 0x09;
9760 static int ca0132_prepare_verbs(struct hda_codec *codec)
9762 /* Verbs + terminator (an empty element) */
9763 #define NUM_SPEC_VERBS 2
9764 struct ca0132_spec *spec = codec->spec;
9766 spec->chip_init_verbs = ca0132_init_verbs0;
9768 * Since desktop cards use pci_mmio, this can be used to determine
9769 * whether or not to use these verbs instead of a separate bool.
9771 if (ca0132_use_pci_mmio(spec))
9772 spec->desktop_init_verbs = ca0132_init_verbs1;
9773 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9774 sizeof(struct hda_verb),
9776 if (!spec->spec_init_verbs)
9780 spec->spec_init_verbs[0].nid = 0x0b;
9781 spec->spec_init_verbs[0].param = 0x78D;
9782 spec->spec_init_verbs[0].verb = 0x00;
9784 /* Previously commented configuration */
9786 spec->spec_init_verbs[2].nid = 0x0b;
9787 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9788 spec->spec_init_verbs[2].verb = 0x02;
9790 spec->spec_init_verbs[3].nid = 0x10;
9791 spec->spec_init_verbs[3].param = 0x78D;
9792 spec->spec_init_verbs[3].verb = 0x02;
9794 spec->spec_init_verbs[4].nid = 0x10;
9795 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9796 spec->spec_init_verbs[4].verb = 0x02;
9799 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9804 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9805 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9806 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9807 * daughter boards ID.
9809 static void sbz_detect_quirk(struct hda_codec *codec)
9811 struct ca0132_spec *spec = codec->spec;
9813 switch (codec->core.subsystem_id) {
9815 spec->quirk = QUIRK_ZXR;
9818 spec->quirk = QUIRK_ZXR_DBPRO;
9821 spec->quirk = QUIRK_SBZ;
9826 static int patch_ca0132(struct hda_codec *codec)
9828 struct ca0132_spec *spec;
9830 const struct snd_pci_quirk *quirk;
9832 codec_dbg(codec, "patch_ca0132\n");
9834 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9838 spec->codec = codec;
9840 /* Detect codec quirk */
9841 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9843 spec->quirk = quirk->value;
9845 spec->quirk = QUIRK_NONE;
9846 if (ca0132_quirk(spec) == QUIRK_SBZ)
9847 sbz_detect_quirk(codec);
9849 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9850 codec->patch_ops = dbpro_patch_ops;
9852 codec->patch_ops = ca0132_patch_ops;
9854 codec->pcm_format_first = 1;
9855 codec->no_sticky_stream = 1;
9858 spec->dsp_state = DSP_DOWNLOAD_INIT;
9859 spec->num_mixers = 1;
9861 /* Set which mixers each quirk uses. */
9862 switch (ca0132_quirk(spec)) {
9864 spec->mixers[0] = desktop_mixer;
9865 snd_hda_codec_set_name(codec, "Sound Blaster Z");
9868 spec->mixers[0] = desktop_mixer;
9869 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9871 case QUIRK_ZXR_DBPRO:
9874 spec->mixers[0] = desktop_mixer;
9875 snd_hda_codec_set_name(codec, "Recon3D");
9878 spec->mixers[0] = r3di_mixer;
9879 snd_hda_codec_set_name(codec, "Recon3Di");
9882 spec->mixers[0] = desktop_mixer;
9883 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9886 spec->mixers[0] = desktop_mixer;
9887 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9890 spec->mixers[0] = ca0132_mixer;
9894 /* Setup whether or not to use alt functions/controls/pci_mmio */
9895 switch (ca0132_quirk(spec)) {
9901 spec->use_alt_controls = true;
9902 spec->use_alt_functions = true;
9903 spec->use_pci_mmio = true;
9906 spec->use_alt_controls = true;
9907 spec->use_alt_functions = true;
9908 spec->use_pci_mmio = false;
9911 spec->use_alt_controls = false;
9912 spec->use_alt_functions = false;
9913 spec->use_pci_mmio = false;
9918 if (spec->use_pci_mmio) {
9919 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9920 if (spec->mem_base == NULL) {
9921 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9922 spec->quirk = QUIRK_NONE;
9927 spec->base_init_verbs = ca0132_base_init_verbs;
9928 spec->base_exit_verbs = ca0132_base_exit_verbs;
9930 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9932 ca0132_init_chip(codec);
9934 ca0132_config(codec);
9936 err = ca0132_prepare_verbs(codec);
9940 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
9954 static const struct hda_device_id snd_hda_id_ca0132[] = {
9955 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
9958 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
9960 MODULE_LICENSE("GPL");
9961 MODULE_DESCRIPTION("Creative Sound Core3D codec");
9963 static struct hda_codec_driver ca0132_driver = {
9964 .id = snd_hda_id_ca0132,
9967 module_hda_codec_driver(ca0132_driver);