sound/pci/hda/patch_ca0132.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Creative CA0132 chip
   4  *
   5  * Copyright (c) 2011, Creative Technology Ltd.
   6  *
   7  * Based on patch_ca0110.c
   8  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/module.h>
  16 #include <linux/firmware.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <asm/io.h>
  22 #include <sound/core.h>
  23 #include <sound/hda_codec.h>
  24 #include "hda_local.h"
  25 #include "hda_auto_parser.h"
  26 #include "hda_jack.h"
  27
  28 #include "ca0132_regs.h"
  29
  30 /* Enable this to see controls for tuning purpose. */
  31 /*#define ENABLE_TUNING_CONTROLS*/
  32
  33 #ifdef ENABLE_TUNING_CONTROLS
  34 #include <sound/tlv.h>
  35 #endif
  36
  37 #define FLOAT_ZERO      0x00000000
  38 #define FLOAT_ONE       0x3f800000
  39 #define FLOAT_TWO       0x40000000
  40 #define FLOAT_THREE     0x40400000
  41 #define FLOAT_FIVE      0x40a00000
  42 #define FLOAT_SIX       0x40c00000
  43 #define FLOAT_EIGHT     0x41000000
  44 #define FLOAT_MINUS_5   0xc0a00000
  45
  46 #define UNSOL_TAG_DSP   0x16
  47
  48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  50
  51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  54
  55 #define MASTERCONTROL                           0x80
  56 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  58
  59 #define WIDGET_CHIP_CTRL      0x15
  60 #define WIDGET_DSP_CTRL       0x16
  61
  62 #define MEM_CONNID_MICIN1     3
  63 #define MEM_CONNID_MICIN2     5
  64 #define MEM_CONNID_MICOUT1    12
  65 #define MEM_CONNID_MICOUT2    14
  66 #define MEM_CONNID_WUH        10
  67 #define MEM_CONNID_DSP        16
  68 #define MEM_CONNID_DMIC       100
  69
  70 #define SCP_SET    0
  71 #define SCP_GET    1
  72
  73 #define EFX_FILE   "/*(DEBLOBBED)*/"
  74 #define DESKTOP_EFX_FILE   "/*(DEBLOBBED)*/"
  75 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  76
  77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  78 /*(DEBLOBBED)*/
  79 #endif
  80
  81 static const char *const dirstr[2] = { "Playback", "Capture" };
  82
  83 #define NUM_OF_OUTPUTS 2
  84 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
  85 enum {
  86         SPEAKER_OUT,
  87         HEADPHONE_OUT,
  88 };
  89
  90 enum {
  91         DIGITAL_MIC,
  92         LINE_MIC_IN
  93 };
  94
  95 /* Strings for Input Source Enum Control */
  96 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
  97 #define IN_SRC_NUM_OF_INPUTS 3
  98 enum {
  99         REAR_MIC,
 100         REAR_LINE_IN,
 101         FRONT_MIC,
 102 };
 103
 104 enum {
 105 #define VNODE_START_NID    0x80
 106         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 107         VNID_MIC,
 108         VNID_HP_SEL,
 109         VNID_AMIC1_SEL,
 110         VNID_HP_ASEL,
 111         VNID_AMIC1_ASEL,
 112         VNODE_END_NID,
 113 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 114
 115 #define EFFECT_START_NID    0x90
 116 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 117         SURROUND = OUT_EFFECT_START_NID,
 118         CRYSTALIZER,
 119         DIALOG_PLUS,
 120         SMART_VOLUME,
 121         X_BASS,
 122         EQUALIZER,
 123         OUT_EFFECT_END_NID,
 124 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 125
 126 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 127         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 128         VOICE_FOCUS,
 129         MIC_SVM,
 130         NOISE_REDUCTION,
 131         IN_EFFECT_END_NID,
 132 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 133
 134         VOICEFX = IN_EFFECT_END_NID,
 135         PLAY_ENHANCEMENT,
 136         CRYSTAL_VOICE,
 137         EFFECT_END_NID,
 138         OUTPUT_SOURCE_ENUM,
 139         INPUT_SOURCE_ENUM,
 140         XBASS_XOVER,
 141         EQ_PRESET_ENUM,
 142         SMART_VOLUME_ENUM,
 143         MIC_BOOST_ENUM,
 144         AE5_HEADPHONE_GAIN_ENUM,
 145         AE5_SOUND_FILTER_ENUM,
 146         ZXR_HEADPHONE_GAIN,
 147         SPEAKER_CHANNEL_CFG_ENUM,
 148         SPEAKER_FULL_RANGE_FRONT,
 149         SPEAKER_FULL_RANGE_REAR,
 150         BASS_REDIRECTION,
 151         BASS_REDIRECTION_XOVER,
 152 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 153 };
 154
 155 /* Effects values size*/
 156 #define EFFECT_VALS_MAX_COUNT 12
 157
 158 /*
 159  * Default values for the effect slider controls, they are in order of their
 160  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 161  * X-bass.
 162  */
 163 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 164 /* Amount of effect level sliders for ca0132_alt controls. */
 165 #define EFFECT_LEVEL_SLIDERS 5
 166
 167 /* Latency introduced by DSP blocks in milliseconds. */
 168 #define DSP_CAPTURE_INIT_LATENCY        0
 169 #define DSP_CRYSTAL_VOICE_LATENCY       124
 170 #define DSP_PLAYBACK_INIT_LATENCY       13
 171 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 172 #define DSP_SPEAKER_OUT_LATENCY         7
 173
 174 struct ct_effect {
 175         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 176         hda_nid_t nid;
 177         int mid; /*effect module ID*/
 178         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 179         int direct; /* 0:output; 1:input*/
 180         int params; /* number of default non-on/off params */
 181         /*effect default values, 1st is on/off. */
 182         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 183 };
 184
 185 #define EFX_DIR_OUT 0
 186 #define EFX_DIR_IN  1
 187
 188 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 189         { .name = "Surround",
 190           .nid = SURROUND,
 191           .mid = 0x96,
 192           .reqs = {0, 1},
 193           .direct = EFX_DIR_OUT,
 194           .params = 1,
 195           .def_vals = {0x3F800000, 0x3F2B851F}
 196         },
 197         { .name = "Crystalizer",
 198           .nid = CRYSTALIZER,
 199           .mid = 0x96,
 200           .reqs = {7, 8},
 201           .direct = EFX_DIR_OUT,
 202           .params = 1,
 203           .def_vals = {0x3F800000, 0x3F266666}
 204         },
 205         { .name = "Dialog Plus",
 206           .nid = DIALOG_PLUS,
 207           .mid = 0x96,
 208           .reqs = {2, 3},
 209           .direct = EFX_DIR_OUT,
 210           .params = 1,
 211           .def_vals = {0x00000000, 0x3F000000}
 212         },
 213         { .name = "Smart Volume",
 214           .nid = SMART_VOLUME,
 215           .mid = 0x96,
 216           .reqs = {4, 5, 6},
 217           .direct = EFX_DIR_OUT,
 218           .params = 2,
 219           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 220         },
 221         { .name = "X-Bass",
 222           .nid = X_BASS,
 223           .mid = 0x96,
 224           .reqs = {24, 23, 25},
 225           .direct = EFX_DIR_OUT,
 226           .params = 2,
 227           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 228         },
 229         { .name = "Equalizer",
 230           .nid = EQUALIZER,
 231           .mid = 0x96,
 232           .reqs = {9, 10, 11, 12, 13, 14,
 233                         15, 16, 17, 18, 19, 20},
 234           .direct = EFX_DIR_OUT,
 235           .params = 11,
 236           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 237                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 238                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 239         },
 240         { .name = "Echo Cancellation",
 241           .nid = ECHO_CANCELLATION,
 242           .mid = 0x95,
 243           .reqs = {0, 1, 2, 3},
 244           .direct = EFX_DIR_IN,
 245           .params = 3,
 246           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 247         },
 248         { .name = "Voice Focus",
 249           .nid = VOICE_FOCUS,
 250           .mid = 0x95,
 251           .reqs = {6, 7, 8, 9},
 252           .direct = EFX_DIR_IN,
 253           .params = 3,
 254           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 255         },
 256         { .name = "Mic SVM",
 257           .nid = MIC_SVM,
 258           .mid = 0x95,
 259           .reqs = {44, 45},
 260           .direct = EFX_DIR_IN,
 261           .params = 1,
 262           .def_vals = {0x00000000, 0x3F3D70A4}
 263         },
 264         { .name = "Noise Reduction",
 265           .nid = NOISE_REDUCTION,
 266           .mid = 0x95,
 267           .reqs = {4, 5},
 268           .direct = EFX_DIR_IN,
 269           .params = 1,
 270           .def_vals = {0x3F800000, 0x3F000000}
 271         },
 272         { .name = "VoiceFX",
 273           .nid = VOICEFX,
 274           .mid = 0x95,
 275           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 276           .direct = EFX_DIR_IN,
 277           .params = 8,
 278           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 279                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 280                        0x00000000}
 281         }
 282 };
 283
 284 /* Tuning controls */
 285 #ifdef ENABLE_TUNING_CONTROLS
 286
 287 enum {
 288 #define TUNING_CTL_START_NID  0xC0
 289         WEDGE_ANGLE = TUNING_CTL_START_NID,
 290         SVM_LEVEL,
 291         EQUALIZER_BAND_0,
 292         EQUALIZER_BAND_1,
 293         EQUALIZER_BAND_2,
 294         EQUALIZER_BAND_3,
 295         EQUALIZER_BAND_4,
 296         EQUALIZER_BAND_5,
 297         EQUALIZER_BAND_6,
 298         EQUALIZER_BAND_7,
 299         EQUALIZER_BAND_8,
 300         EQUALIZER_BAND_9,
 301         TUNING_CTL_END_NID
 302 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 303 };
 304
 305 struct ct_tuning_ctl {
 306         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 307         hda_nid_t parent_nid;
 308         hda_nid_t nid;
 309         int mid; /*effect module ID*/
 310         int req; /*effect module request*/
 311         int direct; /* 0:output; 1:input*/
 312         unsigned int def_val;/*effect default values*/
 313 };
 314
 315 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 316         { .name = "Wedge Angle",
 317           .parent_nid = VOICE_FOCUS,
 318           .nid = WEDGE_ANGLE,
 319           .mid = 0x95,
 320           .req = 8,
 321           .direct = EFX_DIR_IN,
 322           .def_val = 0x41F00000
 323         },
 324         { .name = "SVM Level",
 325           .parent_nid = MIC_SVM,
 326           .nid = SVM_LEVEL,
 327           .mid = 0x95,
 328           .req = 45,
 329           .direct = EFX_DIR_IN,
 330           .def_val = 0x3F3D70A4
 331         },
 332         { .name = "EQ Band0",
 333           .parent_nid = EQUALIZER,
 334           .nid = EQUALIZER_BAND_0,
 335           .mid = 0x96,
 336           .req = 11,
 337           .direct = EFX_DIR_OUT,
 338           .def_val = 0x00000000
 339         },
 340         { .name = "EQ Band1",
 341           .parent_nid = EQUALIZER,
 342           .nid = EQUALIZER_BAND_1,
 343           .mid = 0x96,
 344           .req = 12,
 345           .direct = EFX_DIR_OUT,
 346           .def_val = 0x00000000
 347         },
 348         { .name = "EQ Band2",
 349           .parent_nid = EQUALIZER,
 350           .nid = EQUALIZER_BAND_2,
 351           .mid = 0x96,
 352           .req = 13,
 353           .direct = EFX_DIR_OUT,
 354           .def_val = 0x00000000
 355         },
 356         { .name = "EQ Band3",
 357           .parent_nid = EQUALIZER,
 358           .nid = EQUALIZER_BAND_3,
 359           .mid = 0x96,
 360           .req = 14,
 361           .direct = EFX_DIR_OUT,
 362           .def_val = 0x00000000
 363         },
 364         { .name = "EQ Band4",
 365           .parent_nid = EQUALIZER,
 366           .nid = EQUALIZER_BAND_4,
 367           .mid = 0x96,
 368           .req = 15,
 369           .direct = EFX_DIR_OUT,
 370           .def_val = 0x00000000
 371         },
 372         { .name = "EQ Band5",
 373           .parent_nid = EQUALIZER,
 374           .nid = EQUALIZER_BAND_5,
 375           .mid = 0x96,
 376           .req = 16,
 377           .direct = EFX_DIR_OUT,
 378           .def_val = 0x00000000
 379         },
 380         { .name = "EQ Band6",
 381           .parent_nid = EQUALIZER,
 382           .nid = EQUALIZER_BAND_6,
 383           .mid = 0x96,
 384           .req = 17,
 385           .direct = EFX_DIR_OUT,
 386           .def_val = 0x00000000
 387         },
 388         { .name = "EQ Band7",
 389           .parent_nid = EQUALIZER,
 390           .nid = EQUALIZER_BAND_7,
 391           .mid = 0x96,
 392           .req = 18,
 393           .direct = EFX_DIR_OUT,
 394           .def_val = 0x00000000
 395         },
 396         { .name = "EQ Band8",
 397           .parent_nid = EQUALIZER,
 398           .nid = EQUALIZER_BAND_8,
 399           .mid = 0x96,
 400           .req = 19,
 401           .direct = EFX_DIR_OUT,
 402           .def_val = 0x00000000
 403         },
 404         { .name = "EQ Band9",
 405           .parent_nid = EQUALIZER,
 406           .nid = EQUALIZER_BAND_9,
 407           .mid = 0x96,
 408           .req = 20,
 409           .direct = EFX_DIR_OUT,
 410           .def_val = 0x00000000
 411         }
 412 };
 413 #endif
 414
 415 /* Voice FX Presets */
 416 #define VOICEFX_MAX_PARAM_COUNT 9
 417
 418 struct ct_voicefx {
 419         char *name;
 420         hda_nid_t nid;
 421         int mid;
 422         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 423 };
 424
 425 struct ct_voicefx_preset {
 426         char *name; /*preset name*/
 427         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 428 };
 429
 430 static const struct ct_voicefx ca0132_voicefx = {
 431         .name = "VoiceFX Capture Switch",
 432         .nid = VOICEFX,
 433         .mid = 0x95,
 434         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 435 };
 436
 437 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 438         { .name = "Neutral",
 439           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 440                     0x44FA0000, 0x3F800000, 0x3F800000,
 441                     0x3F800000, 0x00000000, 0x00000000 }
 442         },
 443         { .name = "Female2Male",
 444           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 445                     0x44FA0000, 0x3F19999A, 0x3F866666,
 446                     0x3F800000, 0x00000000, 0x00000000 }
 447         },
 448         { .name = "Male2Female",
 449           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 450                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 451                     0x3F800000, 0x00000000, 0x00000000 }
 452         },
 453         { .name = "ScrappyKid",
 454           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 455                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 456                     0x3F800000, 0x00000000, 0x00000000 }
 457         },
 458         { .name = "Elderly",
 459           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 460                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 461                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 462         },
 463         { .name = "Orc",
 464           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 465                     0x45098000, 0x3F266666, 0x3FC00000,
 466                     0x3F800000, 0x00000000, 0x00000000 }
 467         },
 468         { .name = "Elf",
 469           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 470                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 471                     0x3F800000, 0x00000000, 0x00000000 }
 472         },
 473         { .name = "Dwarf",
 474           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 475                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 476                     0x3F800000, 0x00000000, 0x00000000 }
 477         },
 478         { .name = "AlienBrute",
 479           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 480                     0x451F6000, 0x3F266666, 0x3FA7D945,
 481                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 482         },
 483         { .name = "Robot",
 484           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 485                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 486                     0xBC07010E, 0x00000000, 0x00000000 }
 487         },
 488         { .name = "Marine",
 489           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 490                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 491                     0x3F0A3D71, 0x00000000, 0x00000000 }
 492         },
 493         { .name = "Emo",
 494           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 495                     0x44FA0000, 0x3F800000, 0x3F800000,
 496                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 497         },
 498         { .name = "DeepVoice",
 499           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 500                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 501                     0x3F800000, 0x00000000, 0x00000000 }
 502         },
 503         { .name = "Munchkin",
 504           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 505                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 506                     0x3F800000, 0x00000000, 0x00000000 }
 507         }
 508 };
 509
 510 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 511
 512 #define EQ_PRESET_MAX_PARAM_COUNT 11
 513
 514 struct ct_eq {
 515         char *name;
 516         hda_nid_t nid;
 517         int mid;
 518         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 519 };
 520
 521 struct ct_eq_preset {
 522         char *name; /*preset name*/
 523         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 524 };
 525
 526 static const struct ct_eq ca0132_alt_eq_enum = {
 527         .name = "FX: Equalizer Preset Switch",
 528         .nid = EQ_PRESET_ENUM,
 529         .mid = 0x96,
 530         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 531 };
 532
 533
 534 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 535         { .name = "Flat",
 536          .vals = { 0x00000000, 0x00000000, 0x00000000,
 537                    0x00000000, 0x00000000, 0x00000000,
 538                    0x00000000, 0x00000000, 0x00000000,
 539                    0x00000000, 0x00000000            }
 540         },
 541         { .name = "Acoustic",
 542          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 543                    0x40000000, 0x00000000, 0x00000000,
 544                    0x00000000, 0x00000000, 0x40000000,
 545                    0x40000000, 0x40000000            }
 546         },
 547         { .name = "Classical",
 548          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 549                    0x40C00000, 0x40466666, 0x00000000,
 550                    0x00000000, 0x00000000, 0x00000000,
 551                    0x40466666, 0x40466666            }
 552         },
 553         { .name = "Country",
 554          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 555                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 556                    0x00000000, 0x00000000, 0x40000000,
 557                    0x40466666, 0x40800000            }
 558         },
 559         { .name = "Dance",
 560          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 561                    0x40466666, 0x40866666, 0xBF99999A,
 562                    0xBF99999A, 0x00000000, 0x00000000,
 563                    0x40800000, 0x40800000            }
 564         },
 565         { .name = "Jazz",
 566          .vals = { 0x00000000, 0x00000000, 0x00000000,
 567                    0x3F8CCCCD, 0x40800000, 0x40800000,
 568                    0x40800000, 0x00000000, 0x3F8CCCCD,
 569                    0x40466666, 0x40466666            }
 570         },
 571         { .name = "New Age",
 572          .vals = { 0x00000000, 0x00000000, 0x40000000,
 573                    0x40000000, 0x00000000, 0x00000000,
 574                    0x00000000, 0x3F8CCCCD, 0x40000000,
 575                    0x40000000, 0x40000000            }
 576         },
 577         { .name = "Pop",
 578          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 579                    0x40000000, 0x40000000, 0x00000000,
 580                    0xBF99999A, 0xBF99999A, 0x00000000,
 581                    0x40466666, 0x40C00000            }
 582         },
 583         { .name = "Rock",
 584          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 585                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 586                    0xBF99999A, 0x00000000, 0x00000000,
 587                    0x40800000, 0x40800000            }
 588         },
 589         { .name = "Vocal",
 590          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 591                    0xBF99999A, 0x00000000, 0x40466666,
 592                    0x40800000, 0x40466666, 0x00000000,
 593                    0x00000000, 0x3F8CCCCD            }
 594         }
 595 };
 596
 597 /*
 598  * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
 599  * set as not being full range, and bass redirection is enabled, all
 600  * frequencies below the crossover frequency are redirected to the LFE
 601  * channel. If the surround configuration has no LFE channel, this can't be
 602  * enabled. X-Bass must be disabled when using these.
 603  */
 604 enum speaker_range_reqs {
 605         SPEAKER_BASS_REDIRECT            = 0x15,
 606         SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
 607         /* Between 0x16-0x1a are the X-Bass reqs. */
 608         SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
 609         SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
 610         SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
 611         SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
 612         SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
 613 };
 614
 615 /*
 616  * Definitions for the DSP req's to handle speaker tuning. These all belong to
 617  * module ID 0x96, the output effects module.
 618  */
 619 enum speaker_tuning_reqs {
 620         /*
 621          * Currently, this value is always set to 0.0f. However, on Windows,
 622          * when selecting certain headphone profiles on the new Sound Blaster
 623          * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
 624          * sent. This gets the speaker EQ address area, which is then used to
 625          * send over (presumably) an equalizer profile for the specific
 626          * headphone setup. It is sent using the same method the DSP
 627          * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
 628          * file exists in linux firmware tree but goes unused. It would also
 629          * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
 630          * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
 631          * set to 1.0f.
 632          */
 633         SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
 634         SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
 635         SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
 636         SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
 637         SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
 638         SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
 639         SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
 640         SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
 641         SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
 642         SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
 643         /*
 644          * Inversion is used when setting headphone virtualization to line
 645          * out. Not sure why this is, but it's the only place it's ever used.
 646          */
 647         SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
 648         SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
 649         SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
 650         SPEAKER_TUNING_LFE_INVERT               = 0x2c,
 651         SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
 652         SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
 653         SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
 654         SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
 655         /* Delay is used when setting surround speaker distance in Windows. */
 656         SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
 657         SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
 658         SPEAKER_TUNING_CENTER_DELAY             = 0x33,
 659         SPEAKER_TUNING_LFE_DELAY                = 0x34,
 660         SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
 661         SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
 662         SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
 663         SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
 664         /* Of these two, only mute seems to ever be used. */
 665         SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
 666         SPEAKER_TUNING_MUTE                     = 0x3a,
 667 };
 668
 669 /* Surround output channel count configuration structures. */
 670 #define SPEAKER_CHANNEL_CFG_COUNT 5
 671 enum {
 672         SPEAKER_CHANNELS_2_0,
 673         SPEAKER_CHANNELS_2_1,
 674         SPEAKER_CHANNELS_4_0,
 675         SPEAKER_CHANNELS_4_1,
 676         SPEAKER_CHANNELS_5_1,
 677 };
 678
 679 struct ca0132_alt_speaker_channel_cfg {
 680         char *name;
 681         unsigned int val;
 682 };
 683
 684 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
 685         { .name = "2.0",
 686           .val = FLOAT_ONE
 687         },
 688         { .name = "2.1",
 689           .val = FLOAT_TWO
 690         },
 691         { .name = "4.0",
 692           .val = FLOAT_FIVE
 693         },
 694         { .name = "4.1",
 695           .val = FLOAT_SIX
 696         },
 697         { .name = "5.1",
 698           .val = FLOAT_EIGHT
 699         }
 700 };
 701
 702 /*
 703  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 704  * and I don't know what the third req is, but it's always zero. I assume it's
 705  * some sort of update or set command to tell the DSP there's new volume info.
 706  */
 707 #define DSP_VOL_OUT 0
 708 #define DSP_VOL_IN  1
 709
 710 struct ct_dsp_volume_ctl {
 711         hda_nid_t vnid;
 712         int mid; /* module ID*/
 713         unsigned int reqs[3]; /* scp req ID */
 714 };
 715
 716 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 717         { .vnid = VNID_SPK,
 718           .mid = 0x32,
 719           .reqs = {3, 4, 2}
 720         },
 721         { .vnid = VNID_MIC,
 722           .mid = 0x37,
 723           .reqs = {2, 3, 1}
 724         }
 725 };
 726
 727 /* Values for ca0113_mmio_command_set for selecting output. */
 728 #define AE_CA0113_OUT_SET_COMMANDS 6
 729 struct ae_ca0113_output_set {
 730         unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
 731         unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
 732         unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
 733 };
 734
 735 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
 736         .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 737         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 738                     /* Speakers. */
 739         .vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 740                     /* Headphones. */
 741                     { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
 742 };
 743
 744 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
 745         .group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 746         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 747                     /* Speakers. */
 748         .vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 749                     /* Headphones. */
 750                     { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
 751 };
 752
 753 /* ae5 ca0113 command sequences to set headphone gain levels. */
 754 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
 755 struct ae5_headphone_gain_set {
 756         char *name;
 757         unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
 758 };
 759
 760 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
 761         { .name = "Low (16-31",
 762           .vals = { 0xff, 0x2c, 0xf5, 0x32 }
 763         },
 764         { .name = "Medium (32-149",
 765           .vals = { 0x38, 0xa8, 0x3e, 0x4c }
 766         },
 767         { .name = "High (150-600",
 768           .vals = { 0xff, 0xff, 0xff, 0x7f }
 769         }
 770 };
 771
 772 struct ae5_filter_set {
 773         char *name;
 774         unsigned int val;
 775 };
 776
 777 static const struct ae5_filter_set ae5_filter_presets[] = {
 778         { .name = "Slow Roll Off",
 779           .val = 0xa0
 780         },
 781         { .name = "Minimum Phase",
 782           .val = 0xc0
 783         },
 784         { .name = "Fast Roll Off",
 785           .val = 0x80
 786         }
 787 };
 788
 789 /*
 790  * Data structures for storing audio router remapping data. These are used to
 791  * remap a currently active streams ports.
 792  */
 793 struct chipio_stream_remap_data {
 794         unsigned int stream_id;
 795         unsigned int count;
 796
 797         unsigned int offset[16];
 798         unsigned int value[16];
 799 };
 800
 801 static const struct chipio_stream_remap_data stream_remap_data[] = {
 802         { .stream_id = 0x14,
 803           .count     = 0x04,
 804           .offset    = { 0x00, 0x04, 0x08, 0x0c },
 805           .value     = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
 806         },
 807         { .stream_id = 0x0c,
 808           .count     = 0x0c,
 809           .offset    = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
 810                          0x20, 0x24, 0x28, 0x2c },
 811           .value     = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
 812                          0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
 813                          0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
 814         },
 815         { .stream_id = 0x0c,
 816           .count     = 0x08,
 817           .offset    = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
 818           .value     = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
 819                          0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
 820         }
 821 };
 822
 823 enum hda_cmd_vendor_io {
 824         /* for DspIO node */
 825         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 826         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 827
 828         VENDOR_DSPIO_STATUS                  = 0xF01,
 829         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 830         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 831         VENDOR_DSPIO_DSP_INIT                = 0x703,
 832         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 833         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 834
 835         /* for ChipIO node */
 836         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 837         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 838         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 839         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 840         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 841
 842         VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
 843         VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
 844
 845         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 846         VENDOR_CHIPIO_STATUS                 = 0xF01,
 847         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 848         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 849
 850         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 851         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 852         VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
 853         VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
 854         VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
 855
 856         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 857         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 858
 859         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 860         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 861         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 862         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 863         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 864         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 865         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 866         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 867
 868         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 869         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 870         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 871         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 872
 873         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 874         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 875         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 876         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 877
 878         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 879         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 880         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 881         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 882         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 883         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 884
 885         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 886 };
 887
 888 /*
 889  *  Control flag IDs
 890  */
 891 enum control_flag_id {
 892         /* Connection manager stream setup is bypassed/enabled */
 893         CONTROL_FLAG_C_MGR                  = 0,
 894         /* DSP DMA is bypassed/enabled */
 895         CONTROL_FLAG_DMA                    = 1,
 896         /* 8051 'idle' mode is disabled/enabled */
 897         CONTROL_FLAG_IDLE_ENABLE            = 2,
 898         /* Tracker for the SPDIF-in path is bypassed/enabled */
 899         CONTROL_FLAG_TRACKER                = 3,
 900         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 901         CONTROL_FLAG_SPDIF2OUT              = 4,
 902         /* Digital Microphone is disabled/enabled */
 903         CONTROL_FLAG_DMIC                   = 5,
 904         /* ADC_B rate is 48 kHz/96 kHz */
 905         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 906         /* ADC_C rate is 48 kHz/96 kHz */
 907         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 908         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 909         CONTROL_FLAG_DAC_96KHZ              = 8,
 910         /* DSP rate is 48 kHz/96 kHz */
 911         CONTROL_FLAG_DSP_96KHZ              = 9,
 912         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 913         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 914         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 915         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 916         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 917         CONTROL_FLAG_DECODE_LOOP            = 12,
 918         /* De-emphasis filter on DAC-1 disabled/enabled */
 919         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 920         /* De-emphasis filter on DAC-2 disabled/enabled */
 921         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 922         /* De-emphasis filter on DAC-3 disabled/enabled */
 923         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 924         /* High-pass filter on ADC_B disabled/enabled */
 925         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 926         /* High-pass filter on ADC_C disabled/enabled */
 927         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 928         /* Common mode on Port_A disabled/enabled */
 929         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 930         /* Common mode on Port_D disabled/enabled */
 931         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 932         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 933         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 934         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 935         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 936         /* ASI rate is 48kHz/96kHz */
 937         CONTROL_FLAG_ASI_96KHZ              = 22,
 938         /* DAC power settings able to control attached ports no/yes */
 939         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 940         /* Clock Stop OK reporting is disabled/enabled */
 941         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 942         /* Number of control flags */
 943         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 944 };
 945
 946 /*
 947  * Control parameter IDs
 948  */
 949 enum control_param_id {
 950         /* 0: None, 1: Mic1In*/
 951         CONTROL_PARAM_VIP_SOURCE               = 1,
 952         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 953         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 954         /* Port A output stage gain setting to use when 16 Ohm output
 955          * impedance is selected*/
 956         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 957         /* Port D output stage gain setting to use when 16 Ohm output
 958          * impedance is selected*/
 959         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 960
 961         /*
 962          * This control param name was found in the 8051 memory, and makes
 963          * sense given the fact the AE-5 uses it and has the ASI flag set.
 964          */
 965         CONTROL_PARAM_ASI                      = 23,
 966
 967         /* Stream Control */
 968
 969         /* Select stream with the given ID */
 970         CONTROL_PARAM_STREAM_ID                = 24,
 971         /* Source connection point for the selected stream */
 972         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 973         /* Destination connection point for the selected stream */
 974         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 975         /* Number of audio channels in the selected stream */
 976         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 977         /*Enable control for the selected stream */
 978         CONTROL_PARAM_STREAM_CONTROL           = 28,
 979
 980         /* Connection Point Control */
 981
 982         /* Select connection point with the given ID */
 983         CONTROL_PARAM_CONN_POINT_ID            = 29,
 984         /* Connection point sample rate */
 985         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 986
 987         /* Node Control */
 988
 989         /* Select HDA node with the given ID */
 990         CONTROL_PARAM_NODE_ID                  = 31
 991 };
 992
 993 /*
 994  *  Dsp Io Status codes
 995  */
 996 enum hda_vendor_status_dspio {
 997         /* Success */
 998         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 999         /* Busy, unable to accept new command, the host must retry */
1000         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
1001         /* SCP command queue is full */
1002         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
1003         /* SCP response queue is empty */
1004         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1005 };
1006
1007 /*
1008  *  Chip Io Status codes
1009  */
1010 enum hda_vendor_status_chipio {
1011         /* Success */
1012         VENDOR_STATUS_CHIPIO_OK   = 0x00,
1013         /* Busy, unable to accept new command, the host must retry */
1014         VENDOR_STATUS_CHIPIO_BUSY = 0x01
1015 };
1016
1017 /*
1018  *  CA0132 sample rate
1019  */
1020 enum ca0132_sample_rate {
1021         SR_6_000        = 0x00,
1022         SR_8_000        = 0x01,
1023         SR_9_600        = 0x02,
1024         SR_11_025       = 0x03,
1025         SR_16_000       = 0x04,
1026         SR_22_050       = 0x05,
1027         SR_24_000       = 0x06,
1028         SR_32_000       = 0x07,
1029         SR_44_100       = 0x08,
1030         SR_48_000       = 0x09,
1031         SR_88_200       = 0x0A,
1032         SR_96_000       = 0x0B,
1033         SR_144_000      = 0x0C,
1034         SR_176_400      = 0x0D,
1035         SR_192_000      = 0x0E,
1036         SR_384_000      = 0x0F,
1037
1038         SR_COUNT        = 0x10,
1039
1040         SR_RATE_UNKNOWN = 0x1F
1041 };
1042
1043 enum dsp_download_state {
1044         DSP_DOWNLOAD_FAILED = -1,
1045         DSP_DOWNLOAD_INIT   = 0,
1046         DSP_DOWNLOADING     = 1,
1047         DSP_DOWNLOADED      = 2
1048 };
1049
1050 /* retrieve parameters from hda format */
1051 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
1052 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
1053 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
1054 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
1055
1056 /*
1057  * CA0132 specific
1058  */
1059
1060 struct ca0132_spec {
1061         const struct snd_kcontrol_new *mixers[5];
1062         unsigned int num_mixers;
1063         const struct hda_verb *base_init_verbs;
1064         const struct hda_verb *base_exit_verbs;
1065         const struct hda_verb *chip_init_verbs;
1066         const struct hda_verb *desktop_init_verbs;
1067         struct hda_verb *spec_init_verbs;
1068         struct auto_pin_cfg autocfg;
1069
1070         /* Nodes configurations */
1071         struct hda_multi_out multiout;
1072         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1073         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1074         unsigned int num_outputs;
1075         hda_nid_t input_pins[AUTO_PIN_LAST];
1076         hda_nid_t adcs[AUTO_PIN_LAST];
1077         hda_nid_t dig_out;
1078         hda_nid_t dig_in;
1079         unsigned int num_inputs;
1080         hda_nid_t shared_mic_nid;
1081         hda_nid_t shared_out_nid;
1082         hda_nid_t unsol_tag_hp;
1083         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1084         hda_nid_t unsol_tag_amic1;
1085
1086         /* chip access */
1087         struct mutex chipio_mutex; /* chip access mutex */
1088         u32 curr_chip_addx;
1089
1090         /* DSP download related */
1091         enum dsp_download_state dsp_state;
1092         unsigned int dsp_stream_id;
1093         unsigned int wait_scp;
1094         unsigned int wait_scp_header;
1095         unsigned int wait_num_data;
1096         unsigned int scp_resp_header;
1097         unsigned int scp_resp_data[4];
1098         unsigned int scp_resp_count;
1099         bool startup_check_entered;
1100         bool dsp_reload;
1101
1102         /* mixer and effects related */
1103         unsigned char dmic_ctl;
1104         int cur_out_type;
1105         int cur_mic_type;
1106         long vnode_lvol[VNODES_COUNT];
1107         long vnode_rvol[VNODES_COUNT];
1108         long vnode_lswitch[VNODES_COUNT];
1109         long vnode_rswitch[VNODES_COUNT];
1110         long effects_switch[EFFECTS_COUNT];
1111         long voicefx_val;
1112         long cur_mic_boost;
1113         /* ca0132_alt control related values */
1114         unsigned char in_enum_val;
1115         unsigned char out_enum_val;
1116         unsigned char channel_cfg_val;
1117         unsigned char speaker_range_val[2];
1118         unsigned char mic_boost_enum_val;
1119         unsigned char smart_volume_setting;
1120         unsigned char bass_redirection_val;
1121         long bass_redirect_xover_freq;
1122         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1123         long xbass_xover_freq;
1124         long eq_preset_val;
1125         unsigned int tlv[4];
1126         struct hda_vmaster_mute_hook vmaster_mute;
1127         /* AE-5 Control values */
1128         unsigned char ae5_headphone_gain_val;
1129         unsigned char ae5_filter_val;
1130         /* ZxR Control Values */
1131         unsigned char zxr_gain_set;
1132
1133         struct hda_codec *codec;
1134         struct delayed_work unsol_hp_work;
1135         int quirk;
1136
1137 #ifdef ENABLE_TUNING_CONTROLS
1138         long cur_ctl_vals[TUNING_CTLS_COUNT];
1139 #endif
1140         /*
1141          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1142          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1143          * things.
1144          */
1145         bool use_pci_mmio;
1146         void __iomem *mem_base;
1147
1148         /*
1149          * Whether or not to use the alt functions like alt_select_out,
1150          * alt_select_in, etc. Only used on desktop codecs for now, because of
1151          * surround sound support.
1152          */
1153         bool use_alt_functions;
1154
1155         /*
1156          * Whether or not to use alt controls:  volume effect sliders, EQ
1157          * presets, smart volume presets, and new control names with FX prefix.
1158          * Renames PlayEnhancement and CrystalVoice too.
1159          */
1160         bool use_alt_controls;
1161 };
1162
1163 /*
1164  * CA0132 quirks table
1165  */
1166 enum {
1167         QUIRK_NONE,
1168         QUIRK_ALIENWARE,
1169         QUIRK_ALIENWARE_M17XR4,
1170         QUIRK_SBZ,
1171         QUIRK_ZXR,
1172         QUIRK_ZXR_DBPRO,
1173         QUIRK_R3DI,
1174         QUIRK_R3D,
1175         QUIRK_AE5,
1176         QUIRK_AE7,
1177 };
1178
1179 #ifdef CONFIG_PCI
1180 #define ca0132_quirk(spec)              ((spec)->quirk)
1181 #define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
1182 #define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
1183 #define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
1184 #else
1185 #define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
1186 #define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
1187 #define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
1188 #define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
1189 #endif
1190
1191 static const struct hda_pintbl alienware_pincfgs[] = {
1192         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1193         { 0x0c, 0x411111f0 }, /* N/A */
1194         { 0x0d, 0x411111f0 }, /* N/A */
1195         { 0x0e, 0x411111f0 }, /* N/A */
1196         { 0x0f, 0x0321101f }, /* HP */
1197         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1198         { 0x11, 0x03a11021 }, /* Mic */
1199         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1200         { 0x13, 0x411111f0 }, /* N/A */
1201         { 0x18, 0x411111f0 }, /* N/A */
1202         {}
1203 };
1204
1205 /* Sound Blaster Z pin configs taken from Windows Driver */
1206 static const struct hda_pintbl sbz_pincfgs[] = {
1207         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1208         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1209         { 0x0d, 0x014510f0 }, /* Digital Out */
1210         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1211         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1212         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1213         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1214         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1215         { 0x13, 0x908700f0 }, /* What U Hear In*/
1216         { 0x18, 0x50d000f0 }, /* N/A */
1217         {}
1218 };
1219
1220 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1221 static const struct hda_pintbl zxr_pincfgs[] = {
1222         { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1223         { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1224         { 0x0d, 0x014510f0 }, /* Digital Out */
1225         { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1226         { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1227         { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1228         { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1229         { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1230         { 0x13, 0x908700f0 }, /* What U Hear In*/
1231         { 0x18, 0x50d000f0 }, /* N/A */
1232         {}
1233 };
1234
1235 /* Recon3D pin configs taken from Windows Driver */
1236 static const struct hda_pintbl r3d_pincfgs[] = {
1237         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1238         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1239         { 0x0d, 0x014510f0 }, /* Digital Out */
1240         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1241         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1242         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1243         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1244         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1245         { 0x13, 0x908700f0 }, /* What U Hear In*/
1246         { 0x18, 0x50d000f0 }, /* N/A */
1247         {}
1248 };
1249
1250 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1251 static const struct hda_pintbl ae5_pincfgs[] = {
1252         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1253         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1254         { 0x0d, 0x014510f0 }, /* Digital Out */
1255         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1256         { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1257         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1258         { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1259         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1260         { 0x13, 0x908700f0 }, /* What U Hear In*/
1261         { 0x18, 0x50d000f0 }, /* N/A */
1262         {}
1263 };
1264
1265 /* Recon3D integrated pin configs taken from Windows Driver */
1266 static const struct hda_pintbl r3di_pincfgs[] = {
1267         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1268         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1269         { 0x0d, 0x014510f0 }, /* Digital Out */
1270         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1271         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1272         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1273         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1274         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1275         { 0x13, 0x908700f0 }, /* What U Hear In*/
1276         { 0x18, 0x500000f0 }, /* N/A */
1277         {}
1278 };
1279
1280 static const struct hda_pintbl ae7_pincfgs[] = {
1281         { 0x0b, 0x01017010 },
1282         { 0x0c, 0x014510f0 },
1283         { 0x0d, 0x414510f0 },
1284         { 0x0e, 0x01c520f0 },
1285         { 0x0f, 0x01017114 },
1286         { 0x10, 0x01017011 },
1287         { 0x11, 0x018170ff },
1288         { 0x12, 0x01a170f0 },
1289         { 0x13, 0x908700f0 },
1290         { 0x18, 0x500000f0 },
1291         {}
1292 };
1293
1294 static const struct snd_pci_quirk ca0132_quirks[] = {
1295         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1296         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1297         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1298         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1299         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1300         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1301         SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1302         SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1303         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1304         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1305         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1306         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1307         SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1308         SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1309         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1310         SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1311         SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1312         SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1313         SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1314         {}
1315 };
1316
1317 /* Output selection quirk info structures. */
1318 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1319 #define MAX_QUIRK_SCP_SET_VALS 2
1320 struct ca0132_alt_out_set_info {
1321         unsigned int dac2port; /* ParamID 0x0d value. */
1322
1323         bool has_hda_gpio;
1324         char hda_gpio_pin;
1325         char hda_gpio_set;
1326
1327         unsigned int mmio_gpio_count;
1328         char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1329         char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1330
1331         unsigned int scp_cmds_count;
1332         unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1333         unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1334         unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1335
1336         bool has_chipio_write;
1337         unsigned int chipio_write_addr;
1338         unsigned int chipio_write_data;
1339 };
1340
1341 struct ca0132_alt_out_set_quirk_data {
1342         int quirk_id;
1343
1344         bool has_headphone_gain;
1345         bool is_ae_series;
1346
1347         struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1348 };
1349
1350 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1351         { .quirk_id = QUIRK_R3DI,
1352           .has_headphone_gain = false,
1353           .is_ae_series       = false,
1354           .out_set_info = {
1355                 /* Speakers. */
1356                 { .dac2port         = 0x24,
1357                   .has_hda_gpio     = true,
1358                   .hda_gpio_pin     = 2,
1359                   .hda_gpio_set     = 1,
1360                   .mmio_gpio_count  = 0,
1361                   .scp_cmds_count   = 0,
1362                   .has_chipio_write = false,
1363                 },
1364                 /* Headphones. */
1365                 { .dac2port         = 0x21,
1366                   .has_hda_gpio     = true,
1367                   .hda_gpio_pin     = 2,
1368                   .hda_gpio_set     = 0,
1369                   .mmio_gpio_count  = 0,
1370                   .scp_cmds_count   = 0,
1371                   .has_chipio_write = false,
1372                 } },
1373         },
1374         { .quirk_id = QUIRK_R3D,
1375           .has_headphone_gain = false,
1376           .is_ae_series       = false,
1377           .out_set_info = {
1378                 /* Speakers. */
1379                 { .dac2port         = 0x24,
1380                   .has_hda_gpio     = false,
1381                   .mmio_gpio_count  = 1,
1382                   .mmio_gpio_pin    = { 1 },
1383                   .mmio_gpio_set    = { 1 },
1384                   .scp_cmds_count   = 0,
1385                   .has_chipio_write = false,
1386                 },
1387                 /* Headphones. */
1388                 { .dac2port         = 0x21,
1389                   .has_hda_gpio     = false,
1390                   .mmio_gpio_count  = 1,
1391                   .mmio_gpio_pin    = { 1 },
1392                   .mmio_gpio_set    = { 0 },
1393                   .scp_cmds_count   = 0,
1394                   .has_chipio_write = false,
1395                 } },
1396         },
1397         { .quirk_id = QUIRK_SBZ,
1398           .has_headphone_gain = false,
1399           .is_ae_series       = false,
1400           .out_set_info = {
1401                 /* Speakers. */
1402                 { .dac2port         = 0x18,
1403                   .has_hda_gpio     = false,
1404                   .mmio_gpio_count  = 3,
1405                   .mmio_gpio_pin    = { 7, 4, 1 },
1406                   .mmio_gpio_set    = { 0, 1, 1 },
1407                   .scp_cmds_count   = 0,
1408                   .has_chipio_write = false, },
1409                 /* Headphones. */
1410                 { .dac2port         = 0x12,
1411                   .has_hda_gpio     = false,
1412                   .mmio_gpio_count  = 3,
1413                   .mmio_gpio_pin    = { 7, 4, 1 },
1414                   .mmio_gpio_set    = { 1, 1, 0 },
1415                   .scp_cmds_count   = 0,
1416                   .has_chipio_write = false,
1417                 } },
1418         },
1419         { .quirk_id = QUIRK_ZXR,
1420           .has_headphone_gain = true,
1421           .is_ae_series       = false,
1422           .out_set_info = {
1423                 /* Speakers. */
1424                 { .dac2port         = 0x24,
1425                   .has_hda_gpio     = false,
1426                   .mmio_gpio_count  = 3,
1427                   .mmio_gpio_pin    = { 2, 3, 5 },
1428                   .mmio_gpio_set    = { 1, 1, 0 },
1429                   .scp_cmds_count   = 0,
1430                   .has_chipio_write = false,
1431                 },
1432                 /* Headphones. */
1433                 { .dac2port         = 0x21,
1434                   .has_hda_gpio     = false,
1435                   .mmio_gpio_count  = 3,
1436                   .mmio_gpio_pin    = { 2, 3, 5 },
1437                   .mmio_gpio_set    = { 0, 1, 1 },
1438                   .scp_cmds_count   = 0,
1439                   .has_chipio_write = false,
1440                 } },
1441         },
1442         { .quirk_id = QUIRK_AE5,
1443           .has_headphone_gain = true,
1444           .is_ae_series       = true,
1445           .out_set_info = {
1446                 /* Speakers. */
1447                 { .dac2port          = 0xa4,
1448                   .has_hda_gpio      = false,
1449                   .mmio_gpio_count   = 0,
1450                   .scp_cmds_count    = 2,
1451                   .scp_cmd_mid       = { 0x96, 0x96 },
1452                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1453                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1454                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1455                   .has_chipio_write  = true,
1456                   .chipio_write_addr = 0x0018b03c,
1457                   .chipio_write_data = 0x00000012
1458                 },
1459                 /* Headphones. */
1460                 { .dac2port          = 0xa1,
1461                   .has_hda_gpio      = false,
1462                   .mmio_gpio_count   = 0,
1463                   .scp_cmds_count    = 2,
1464                   .scp_cmd_mid       = { 0x96, 0x96 },
1465                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1466                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1467                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1468                   .has_chipio_write  = true,
1469                   .chipio_write_addr = 0x0018b03c,
1470                   .chipio_write_data = 0x00000012
1471                 } },
1472         },
1473         { .quirk_id = QUIRK_AE7,
1474           .has_headphone_gain = true,
1475           .is_ae_series       = true,
1476           .out_set_info = {
1477                 /* Speakers. */
1478                 { .dac2port          = 0x58,
1479                   .has_hda_gpio      = false,
1480                   .mmio_gpio_count   = 1,
1481                   .mmio_gpio_pin     = { 0 },
1482                   .mmio_gpio_set     = { 1 },
1483                   .scp_cmds_count    = 2,
1484                   .scp_cmd_mid       = { 0x96, 0x96 },
1485                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1486                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1487                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1488                   .has_chipio_write  = true,
1489                   .chipio_write_addr = 0x0018b03c,
1490                   .chipio_write_data = 0x00000000
1491                 },
1492                 /* Headphones. */
1493                 { .dac2port          = 0x58,
1494                   .has_hda_gpio      = false,
1495                   .mmio_gpio_count   = 1,
1496                   .mmio_gpio_pin     = { 0 },
1497                   .mmio_gpio_set     = { 1 },
1498                   .scp_cmds_count    = 2,
1499                   .scp_cmd_mid       = { 0x96, 0x96 },
1500                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1501                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1502                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1503                   .has_chipio_write  = true,
1504                   .chipio_write_addr = 0x0018b03c,
1505                   .chipio_write_data = 0x00000010
1506                 } },
1507         }
1508 };
1509
1510 /*
1511  * CA0132 codec access
1512  */
1513 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1514                 unsigned int verb, unsigned int parm, unsigned int *res)
1515 {
1516         unsigned int response;
1517         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1518         *res = response;
1519
1520         return ((response == -1) ? -1 : 0);
1521 }
1522
1523 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1524                 unsigned short converter_format, unsigned int *res)
1525 {
1526         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1527                                 converter_format & 0xffff, res);
1528 }
1529
1530 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1531                                 hda_nid_t nid, unsigned char stream,
1532                                 unsigned char channel, unsigned int *res)
1533 {
1534         unsigned char converter_stream_channel = 0;
1535
1536         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1537         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1538                                 converter_stream_channel, res);
1539 }
1540
1541 /* Chip access helper function */
1542 static int chipio_send(struct hda_codec *codec,
1543                        unsigned int reg,
1544                        unsigned int data)
1545 {
1546         unsigned int res;
1547         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1548
1549         /* send bits of data specified by reg */
1550         do {
1551                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1552                                          reg, data);
1553                 if (res == VENDOR_STATUS_CHIPIO_OK)
1554                         return 0;
1555                 msleep(20);
1556         } while (time_before(jiffies, timeout));
1557
1558         return -EIO;
1559 }
1560
1561 /*
1562  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1563  */
1564 static int chipio_write_address(struct hda_codec *codec,
1565                                 unsigned int chip_addx)
1566 {
1567         struct ca0132_spec *spec = codec->spec;
1568         int res;
1569
1570         if (spec->curr_chip_addx == chip_addx)
1571                         return 0;
1572
1573         /* send low 16 bits of the address */
1574         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1575                           chip_addx & 0xffff);
1576
1577         if (res != -EIO) {
1578                 /* send high 16 bits of the address */
1579                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1580                                   chip_addx >> 16);
1581         }
1582
1583         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1584
1585         return res;
1586 }
1587
1588 /*
1589  * Write data through the vendor widget -- NOT protected by the Mutex!
1590  */
1591 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1592 {
1593         struct ca0132_spec *spec = codec->spec;
1594         int res;
1595
1596         /* send low 16 bits of the data */
1597         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1598
1599         if (res != -EIO) {
1600                 /* send high 16 bits of the data */
1601                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1602                                   data >> 16);
1603         }
1604
1605         /*If no error encountered, automatically increment the address
1606         as per chip behaviour*/
1607         spec->curr_chip_addx = (res != -EIO) ?
1608                                         (spec->curr_chip_addx + 4) : ~0U;
1609         return res;
1610 }
1611
1612 /*
1613  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1614  */
1615 static int chipio_write_data_multiple(struct hda_codec *codec,
1616                                       const u32 *data,
1617                                       unsigned int count)
1618 {
1619         int status = 0;
1620
1621         if (data == NULL) {
1622                 codec_dbg(codec, "chipio_write_data null ptr\n");
1623                 return -EINVAL;
1624         }
1625
1626         while ((count-- != 0) && (status == 0))
1627                 status = chipio_write_data(codec, *data++);
1628
1629         return status;
1630 }
1631
1632
1633 /*
1634  * Read data through the vendor widget -- NOT protected by the Mutex!
1635  */
1636 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1637 {
1638         struct ca0132_spec *spec = codec->spec;
1639         int res;
1640
1641         /* post read */
1642         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1643
1644         if (res != -EIO) {
1645                 /* read status */
1646                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1647         }
1648
1649         if (res != -EIO) {
1650                 /* read data */
1651                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1652                                            VENDOR_CHIPIO_HIC_READ_DATA,
1653                                            0);
1654         }
1655
1656         /*If no error encountered, automatically increment the address
1657         as per chip behaviour*/
1658         spec->curr_chip_addx = (res != -EIO) ?
1659                                         (spec->curr_chip_addx + 4) : ~0U;
1660         return res;
1661 }
1662
1663 /*
1664  * Write given value to the given address through the chip I/O widget.
1665  * protected by the Mutex
1666  */
1667 static int chipio_write(struct hda_codec *codec,
1668                 unsigned int chip_addx, const unsigned int data)
1669 {
1670         struct ca0132_spec *spec = codec->spec;
1671         int err;
1672
1673         mutex_lock(&spec->chipio_mutex);
1674
1675         /* write the address, and if successful proceed to write data */
1676         err = chipio_write_address(codec, chip_addx);
1677         if (err < 0)
1678                 goto exit;
1679
1680         err = chipio_write_data(codec, data);
1681         if (err < 0)
1682                 goto exit;
1683
1684 exit:
1685         mutex_unlock(&spec->chipio_mutex);
1686         return err;
1687 }
1688
1689 /*
1690  * Write given value to the given address through the chip I/O widget.
1691  * not protected by the Mutex
1692  */
1693 static int chipio_write_no_mutex(struct hda_codec *codec,
1694                 unsigned int chip_addx, const unsigned int data)
1695 {
1696         int err;
1697
1698
1699         /* write the address, and if successful proceed to write data */
1700         err = chipio_write_address(codec, chip_addx);
1701         if (err < 0)
1702                 goto exit;
1703
1704         err = chipio_write_data(codec, data);
1705         if (err < 0)
1706                 goto exit;
1707
1708 exit:
1709         return err;
1710 }
1711
1712 /*
1713  * Write multiple values to the given address through the chip I/O widget.
1714  * protected by the Mutex
1715  */
1716 static int chipio_write_multiple(struct hda_codec *codec,
1717                                  u32 chip_addx,
1718                                  const u32 *data,
1719                                  unsigned int count)
1720 {
1721         struct ca0132_spec *spec = codec->spec;
1722         int status;
1723
1724         mutex_lock(&spec->chipio_mutex);
1725         status = chipio_write_address(codec, chip_addx);
1726         if (status < 0)
1727                 goto error;
1728
1729         status = chipio_write_data_multiple(codec, data, count);
1730 error:
1731         mutex_unlock(&spec->chipio_mutex);
1732
1733         return status;
1734 }
1735
1736 /*
1737  * Read the given address through the chip I/O widget
1738  * protected by the Mutex
1739  */
1740 static int chipio_read(struct hda_codec *codec,
1741                 unsigned int chip_addx, unsigned int *data)
1742 {
1743         struct ca0132_spec *spec = codec->spec;
1744         int err;
1745
1746         mutex_lock(&spec->chipio_mutex);
1747
1748         /* write the address, and if successful proceed to write data */
1749         err = chipio_write_address(codec, chip_addx);
1750         if (err < 0)
1751                 goto exit;
1752
1753         err = chipio_read_data(codec, data);
1754         if (err < 0)
1755                 goto exit;
1756
1757 exit:
1758         mutex_unlock(&spec->chipio_mutex);
1759         return err;
1760 }
1761
1762 /*
1763  * Set chip control flags through the chip I/O widget.
1764  */
1765 static void chipio_set_control_flag(struct hda_codec *codec,
1766                                     enum control_flag_id flag_id,
1767                                     bool flag_state)
1768 {
1769         unsigned int val;
1770         unsigned int flag_bit;
1771
1772         flag_bit = (flag_state ? 1 : 0);
1773         val = (flag_bit << 7) | (flag_id);
1774         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1775                             VENDOR_CHIPIO_FLAG_SET, val);
1776 }
1777
1778 /*
1779  * Set chip parameters through the chip I/O widget.
1780  */
1781 static void chipio_set_control_param(struct hda_codec *codec,
1782                 enum control_param_id param_id, int param_val)
1783 {
1784         struct ca0132_spec *spec = codec->spec;
1785         int val;
1786
1787         if ((param_id < 32) && (param_val < 8)) {
1788                 val = (param_val << 5) | (param_id);
1789                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790                                     VENDOR_CHIPIO_PARAM_SET, val);
1791         } else {
1792                 mutex_lock(&spec->chipio_mutex);
1793                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1794                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1796                                             param_id);
1797                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1798                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1799                                             param_val);
1800                 }
1801                 mutex_unlock(&spec->chipio_mutex);
1802         }
1803 }
1804
1805 /*
1806  * Set chip parameters through the chip I/O widget. NO MUTEX.
1807  */
1808 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1809                 enum control_param_id param_id, int param_val)
1810 {
1811         int val;
1812
1813         if ((param_id < 32) && (param_val < 8)) {
1814                 val = (param_val << 5) | (param_id);
1815                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1816                                     VENDOR_CHIPIO_PARAM_SET, val);
1817         } else {
1818                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1819                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1820                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1821                                             param_id);
1822                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1823                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1824                                             param_val);
1825                 }
1826         }
1827 }
1828 /*
1829  * Connect stream to a source point, and then connect
1830  * that source point to a destination point.
1831  */
1832 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1833                                 int streamid, int source_point, int dest_point)
1834 {
1835         chipio_set_control_param_no_mutex(codec,
1836                         CONTROL_PARAM_STREAM_ID, streamid);
1837         chipio_set_control_param_no_mutex(codec,
1838                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1839         chipio_set_control_param_no_mutex(codec,
1840                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1841 }
1842
1843 /*
1844  * Set number of channels in the selected stream.
1845  */
1846 static void chipio_set_stream_channels(struct hda_codec *codec,
1847                                 int streamid, unsigned int channels)
1848 {
1849         chipio_set_control_param_no_mutex(codec,
1850                         CONTROL_PARAM_STREAM_ID, streamid);
1851         chipio_set_control_param_no_mutex(codec,
1852                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1853 }
1854
1855 /*
1856  * Enable/Disable audio stream.
1857  */
1858 static void chipio_set_stream_control(struct hda_codec *codec,
1859                                 int streamid, int enable)
1860 {
1861         chipio_set_control_param_no_mutex(codec,
1862                         CONTROL_PARAM_STREAM_ID, streamid);
1863         chipio_set_control_param_no_mutex(codec,
1864                         CONTROL_PARAM_STREAM_CONTROL, enable);
1865 }
1866
1867 /*
1868  * Get ChipIO audio stream's status.
1869  */
1870 static void chipio_get_stream_control(struct hda_codec *codec,
1871                                 int streamid, unsigned int *enable)
1872 {
1873         chipio_set_control_param_no_mutex(codec,
1874                         CONTROL_PARAM_STREAM_ID, streamid);
1875         *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1876                            VENDOR_CHIPIO_PARAM_GET,
1877                            CONTROL_PARAM_STREAM_CONTROL);
1878 }
1879
1880 /*
1881  * Set sampling rate of the connection point. NO MUTEX.
1882  */
1883 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1884                                 int connid, enum ca0132_sample_rate rate)
1885 {
1886         chipio_set_control_param_no_mutex(codec,
1887                         CONTROL_PARAM_CONN_POINT_ID, connid);
1888         chipio_set_control_param_no_mutex(codec,
1889                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1890 }
1891
1892 /*
1893  * Set sampling rate of the connection point.
1894  */
1895 static void chipio_set_conn_rate(struct hda_codec *codec,
1896                                 int connid, enum ca0132_sample_rate rate)
1897 {
1898         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1899         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1900                                  rate);
1901 }
1902
1903 /*
1904  * Writes to the 8051's internal address space directly instead of indirectly,
1905  * giving access to the special function registers located at addresses
1906  * 0x80-0xFF.
1907  */
1908 static void chipio_8051_write_direct(struct hda_codec *codec,
1909                 unsigned int addr, unsigned int data)
1910 {
1911         unsigned int verb;
1912
1913         verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1914         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1915 }
1916
1917 /*
1918  * Writes to the 8051's exram, which has 16-bits of address space.
1919  * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1920  * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1921  * setting the pmem bank selection SFR.
1922  * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1923  * being writable.
1924  */
1925 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1926 {
1927         unsigned int tmp;
1928
1929         /* Lower 8-bits. */
1930         tmp = addr & 0xff;
1931         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1932                             VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1933
1934         /* Upper 8-bits. */
1935         tmp = (addr >> 8) & 0xff;
1936         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1937                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1938 }
1939
1940 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1941 {
1942         /* 8-bits of data. */
1943         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1944                             VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1945 }
1946
1947 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1948 {
1949         return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1950                                    VENDOR_CHIPIO_8051_DATA_READ, 0);
1951 }
1952
1953 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
1954 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1955 {
1956         /* 8-bits of data. */
1957         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958                             VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1959 }
1960
1961 static void chipio_8051_write_exram(struct hda_codec *codec,
1962                 unsigned int addr, unsigned int data)
1963 {
1964         struct ca0132_spec *spec = codec->spec;
1965
1966         mutex_lock(&spec->chipio_mutex);
1967
1968         chipio_8051_set_address(codec, addr);
1969         chipio_8051_set_data(codec, data);
1970
1971         mutex_unlock(&spec->chipio_mutex);
1972 }
1973
1974 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1975                 unsigned int addr, unsigned int data)
1976 {
1977         chipio_8051_set_address(codec, addr);
1978         chipio_8051_set_data(codec, data);
1979 }
1980
1981 /* Readback data from the 8051's exram. No mutex. */
1982 static void chipio_8051_read_exram(struct hda_codec *codec,
1983                 unsigned int addr, unsigned int *data)
1984 {
1985         chipio_8051_set_address(codec, addr);
1986         *data = chipio_8051_get_data(codec);
1987 }
1988
1989 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1990                 unsigned int addr, unsigned int data)
1991 {
1992         struct ca0132_spec *spec = codec->spec;
1993
1994         mutex_lock(&spec->chipio_mutex);
1995
1996         chipio_8051_set_address(codec, addr & 0xff);
1997         chipio_8051_set_data_pll(codec, data);
1998
1999         mutex_unlock(&spec->chipio_mutex);
2000 }
2001
2002 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2003                 unsigned int addr, unsigned int data)
2004 {
2005         chipio_8051_set_address(codec, addr & 0xff);
2006         chipio_8051_set_data_pll(codec, data);
2007 }
2008
2009 /*
2010  * Enable clocks.
2011  */
2012 static void chipio_enable_clocks(struct hda_codec *codec)
2013 {
2014         struct ca0132_spec *spec = codec->spec;
2015
2016         mutex_lock(&spec->chipio_mutex);
2017
2018         chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2019         chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2020         chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2021
2022         mutex_unlock(&spec->chipio_mutex);
2023 }
2024
2025 /*
2026  * CA0132 DSP IO stuffs
2027  */
2028 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2029                       unsigned int data)
2030 {
2031         int res;
2032         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2033
2034         /* send bits of data specified by reg to dsp */
2035         do {
2036                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2037                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2038                         return res;
2039                 msleep(20);
2040         } while (time_before(jiffies, timeout));
2041
2042         return -EIO;
2043 }
2044
2045 /*
2046  * Wait for DSP to be ready for commands
2047  */
2048 static void dspio_write_wait(struct hda_codec *codec)
2049 {
2050         int status;
2051         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2052
2053         do {
2054                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2055                                                 VENDOR_DSPIO_STATUS, 0);
2056                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2057                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2058                         break;
2059                 msleep(1);
2060         } while (time_before(jiffies, timeout));
2061 }
2062
2063 /*
2064  * Write SCP data to DSP
2065  */
2066 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2067 {
2068         struct ca0132_spec *spec = codec->spec;
2069         int status;
2070
2071         dspio_write_wait(codec);
2072
2073         mutex_lock(&spec->chipio_mutex);
2074         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2075                             scp_data & 0xffff);
2076         if (status < 0)
2077                 goto error;
2078
2079         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2080                                     scp_data >> 16);
2081         if (status < 0)
2082                 goto error;
2083
2084         /* OK, now check if the write itself has executed*/
2085         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2086                                     VENDOR_DSPIO_STATUS, 0);
2087 error:
2088         mutex_unlock(&spec->chipio_mutex);
2089
2090         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2091                         -EIO : 0;
2092 }
2093
2094 /*
2095  * Write multiple SCP data to DSP
2096  */
2097 static int dspio_write_multiple(struct hda_codec *codec,
2098                                 unsigned int *buffer, unsigned int size)
2099 {
2100         int status = 0;
2101         unsigned int count;
2102
2103         if (buffer == NULL)
2104                 return -EINVAL;
2105
2106         count = 0;
2107         while (count < size) {
2108                 status = dspio_write(codec, *buffer++);
2109                 if (status != 0)
2110                         break;
2111                 count++;
2112         }
2113
2114         return status;
2115 }
2116
2117 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2118 {
2119         int status;
2120
2121         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2122         if (status == -EIO)
2123                 return status;
2124
2125         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2126         if (status == -EIO ||
2127             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2128                 return -EIO;
2129
2130         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2131                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
2132
2133         return 0;
2134 }
2135
2136 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2137                                unsigned int *buf_size, unsigned int size_count)
2138 {
2139         int status = 0;
2140         unsigned int size = *buf_size;
2141         unsigned int count;
2142         unsigned int skip_count;
2143         unsigned int dummy;
2144
2145         if (buffer == NULL)
2146                 return -1;
2147
2148         count = 0;
2149         while (count < size && count < size_count) {
2150                 status = dspio_read(codec, buffer++);
2151                 if (status != 0)
2152                         break;
2153                 count++;
2154         }
2155
2156         skip_count = count;
2157         if (status == 0) {
2158                 while (skip_count < size) {
2159                         status = dspio_read(codec, &dummy);
2160                         if (status != 0)
2161                                 break;
2162                         skip_count++;
2163                 }
2164         }
2165         *buf_size = count;
2166
2167         return status;
2168 }
2169
2170 /*
2171  * Construct the SCP header using corresponding fields
2172  */
2173 static inline unsigned int
2174 make_scp_header(unsigned int target_id, unsigned int source_id,
2175                 unsigned int get_flag, unsigned int req,
2176                 unsigned int device_flag, unsigned int resp_flag,
2177                 unsigned int error_flag, unsigned int data_size)
2178 {
2179         unsigned int header = 0;
2180
2181         header = (data_size & 0x1f) << 27;
2182         header |= (error_flag & 0x01) << 26;
2183         header |= (resp_flag & 0x01) << 25;
2184         header |= (device_flag & 0x01) << 24;
2185         header |= (req & 0x7f) << 17;
2186         header |= (get_flag & 0x01) << 16;
2187         header |= (source_id & 0xff) << 8;
2188         header |= target_id & 0xff;
2189
2190         return header;
2191 }
2192
2193 /*
2194  * Extract corresponding fields from SCP header
2195  */
2196 static inline void
2197 extract_scp_header(unsigned int header,
2198                    unsigned int *target_id, unsigned int *source_id,
2199                    unsigned int *get_flag, unsigned int *req,
2200                    unsigned int *device_flag, unsigned int *resp_flag,
2201                    unsigned int *error_flag, unsigned int *data_size)
2202 {
2203         if (data_size)
2204                 *data_size = (header >> 27) & 0x1f;
2205         if (error_flag)
2206                 *error_flag = (header >> 26) & 0x01;
2207         if (resp_flag)
2208                 *resp_flag = (header >> 25) & 0x01;
2209         if (device_flag)
2210                 *device_flag = (header >> 24) & 0x01;
2211         if (req)
2212                 *req = (header >> 17) & 0x7f;
2213         if (get_flag)
2214                 *get_flag = (header >> 16) & 0x01;
2215         if (source_id)
2216                 *source_id = (header >> 8) & 0xff;
2217         if (target_id)
2218                 *target_id = header & 0xff;
2219 }
2220
2221 #define SCP_MAX_DATA_WORDS  (16)
2222
2223 /* Structure to contain any SCP message */
2224 struct scp_msg {
2225         unsigned int hdr;
2226         unsigned int data[SCP_MAX_DATA_WORDS];
2227 };
2228
2229 static void dspio_clear_response_queue(struct hda_codec *codec)
2230 {
2231         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2232         unsigned int dummy = 0;
2233         int status;
2234
2235         /* clear all from the response queue */
2236         do {
2237                 status = dspio_read(codec, &dummy);
2238         } while (status == 0 && time_before(jiffies, timeout));
2239 }
2240
2241 static int dspio_get_response_data(struct hda_codec *codec)
2242 {
2243         struct ca0132_spec *spec = codec->spec;
2244         unsigned int data = 0;
2245         unsigned int count;
2246
2247         if (dspio_read(codec, &data) < 0)
2248                 return -EIO;
2249
2250         if ((data & 0x00ffffff) == spec->wait_scp_header) {
2251                 spec->scp_resp_header = data;
2252                 spec->scp_resp_count = data >> 27;
2253                 count = spec->wait_num_data;
2254                 dspio_read_multiple(codec, spec->scp_resp_data,
2255                                     &spec->scp_resp_count, count);
2256                 return 0;
2257         }
2258
2259         return -EIO;
2260 }
2261
2262 /*
2263  * Send SCP message to DSP
2264  */
2265 static int dspio_send_scp_message(struct hda_codec *codec,
2266                                   unsigned char *send_buf,
2267                                   unsigned int send_buf_size,
2268                                   unsigned char *return_buf,
2269                                   unsigned int return_buf_size,
2270                                   unsigned int *bytes_returned)
2271 {
2272         struct ca0132_spec *spec = codec->spec;
2273         int status;
2274         unsigned int scp_send_size = 0;
2275         unsigned int total_size;
2276         bool waiting_for_resp = false;
2277         unsigned int header;
2278         struct scp_msg *ret_msg;
2279         unsigned int resp_src_id, resp_target_id;
2280         unsigned int data_size, src_id, target_id, get_flag, device_flag;
2281
2282         if (bytes_returned)
2283                 *bytes_returned = 0;
2284
2285         /* get scp header from buffer */
2286         header = *((unsigned int *)send_buf);
2287         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2288                            &device_flag, NULL, NULL, &data_size);
2289         scp_send_size = data_size + 1;
2290         total_size = (scp_send_size * 4);
2291
2292         if (send_buf_size < total_size)
2293                 return -EINVAL;
2294
2295         if (get_flag || device_flag) {
2296                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2297                         return -EINVAL;
2298
2299                 spec->wait_scp_header = *((unsigned int *)send_buf);
2300
2301                 /* swap source id with target id */
2302                 resp_target_id = src_id;
2303                 resp_src_id = target_id;
2304                 spec->wait_scp_header &= 0xffff0000;
2305                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2306                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2307                 spec->wait_scp = 1;
2308                 waiting_for_resp = true;
2309         }
2310
2311         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2312                                       scp_send_size);
2313         if (status < 0) {
2314                 spec->wait_scp = 0;
2315                 return status;
2316         }
2317
2318         if (waiting_for_resp) {
2319                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2320                 memset(return_buf, 0, return_buf_size);
2321                 do {
2322                         msleep(20);
2323                 } while (spec->wait_scp && time_before(jiffies, timeout));
2324                 waiting_for_resp = false;
2325                 if (!spec->wait_scp) {
2326                         ret_msg = (struct scp_msg *)return_buf;
2327                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2328                         memcpy(&ret_msg->data, spec->scp_resp_data,
2329                                spec->wait_num_data);
2330                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
2331                         status = 0;
2332                 } else {
2333                         status = -EIO;
2334                 }
2335                 spec->wait_scp = 0;
2336         }
2337
2338         return status;
2339 }
2340
2341 /**
2342  * dspio_scp - Prepare and send the SCP message to DSP
2343  * @codec: the HDA codec
2344  * @mod_id: ID of the DSP module to send the command
2345  * @src_id: ID of the source
2346  * @req: ID of request to send to the DSP module
2347  * @dir: SET or GET
2348  * @data: pointer to the data to send with the request, request specific
2349  * @len: length of the data, in bytes
2350  * @reply: point to the buffer to hold data returned for a reply
2351  * @reply_len: length of the reply buffer returned from GET
2352  *
2353  * Returns zero or a negative error code.
2354  */
2355 static int dspio_scp(struct hda_codec *codec,
2356                 int mod_id, int src_id, int req, int dir, const void *data,
2357                 unsigned int len, void *reply, unsigned int *reply_len)
2358 {
2359         int status = 0;
2360         struct scp_msg scp_send, scp_reply;
2361         unsigned int ret_bytes, send_size, ret_size;
2362         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2363         unsigned int reply_data_size;
2364
2365         memset(&scp_send, 0, sizeof(scp_send));
2366         memset(&scp_reply, 0, sizeof(scp_reply));
2367
2368         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2369                 return -EINVAL;
2370
2371         if (dir == SCP_GET && reply == NULL) {
2372                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2373                 return -EINVAL;
2374         }
2375
2376         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2377                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2378                 return -EINVAL;
2379         }
2380
2381         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2382                                        0, 0, 0, len/sizeof(unsigned int));
2383         if (data != NULL && len > 0) {
2384                 len = min((unsigned int)(sizeof(scp_send.data)), len);
2385                 memcpy(scp_send.data, data, len);
2386         }
2387
2388         ret_bytes = 0;
2389         send_size = sizeof(unsigned int) + len;
2390         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2391                                         send_size, (unsigned char *)&scp_reply,
2392                                         sizeof(scp_reply), &ret_bytes);
2393
2394         if (status < 0) {
2395                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2396                 return status;
2397         }
2398
2399         /* extract send and reply headers members */
2400         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2401                            NULL, NULL, NULL, NULL, NULL);
2402         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2403                            &reply_resp_flag, &reply_error_flag,
2404                            &reply_data_size);
2405
2406         if (!send_get_flag)
2407                 return 0;
2408
2409         if (reply_resp_flag && !reply_error_flag) {
2410                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2411                                         / sizeof(unsigned int);
2412
2413                 if (*reply_len < ret_size*sizeof(unsigned int)) {
2414                         codec_dbg(codec, "reply too long for buf\n");
2415                         return -EINVAL;
2416                 } else if (ret_size != reply_data_size) {
2417                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2418                         return -EINVAL;
2419                 } else if (!reply) {
2420                         codec_dbg(codec, "NULL reply\n");
2421                         return -EINVAL;
2422                 } else {
2423                         *reply_len = ret_size*sizeof(unsigned int);
2424                         memcpy(reply, scp_reply.data, *reply_len);
2425                 }
2426         } else {
2427                 codec_dbg(codec, "reply ill-formed or errflag set\n");
2428                 return -EIO;
2429         }
2430
2431         return status;
2432 }
2433
2434 /*
2435  * Set DSP parameters
2436  */
2437 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2438                         int src_id, int req, const void *data, unsigned int len)
2439 {
2440         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2441                         NULL);
2442 }
2443
2444 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2445                         int req, const unsigned int data)
2446 {
2447         return dspio_set_param(codec, mod_id, 0x20, req, &data,
2448                         sizeof(unsigned int));
2449 }
2450
2451 /*
2452  * Allocate a DSP DMA channel via an SCP message
2453  */
2454 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2455 {
2456         int status = 0;
2457         unsigned int size = sizeof(*dma_chan);
2458
2459         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2460         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2461                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2462                         dma_chan, &size);
2463
2464         if (status < 0) {
2465                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2466                 return status;
2467         }
2468
2469         if ((*dma_chan + 1) == 0) {
2470                 codec_dbg(codec, "no free dma channels to allocate\n");
2471                 return -EBUSY;
2472         }
2473
2474         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2475         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2476
2477         return status;
2478 }
2479
2480 /*
2481  * Free a DSP DMA via an SCP message
2482  */
2483 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2484 {
2485         int status = 0;
2486         unsigned int dummy = 0;
2487
2488         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2489         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2490
2491         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2492                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2493                         sizeof(dma_chan), NULL, &dummy);
2494
2495         if (status < 0) {
2496                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2497                 return status;
2498         }
2499
2500         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2501
2502         return status;
2503 }
2504
2505 /*
2506  * (Re)start the DSP
2507  */
2508 static int dsp_set_run_state(struct hda_codec *codec)
2509 {
2510         unsigned int dbg_ctrl_reg;
2511         unsigned int halt_state;
2512         int err;
2513
2514         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2515         if (err < 0)
2516                 return err;
2517
2518         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2519                       DSP_DBGCNTL_STATE_LOBIT;
2520
2521         if (halt_state != 0) {
2522                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2523                                   DSP_DBGCNTL_SS_MASK);
2524                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2525                                    dbg_ctrl_reg);
2526                 if (err < 0)
2527                         return err;
2528
2529                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2530                                 DSP_DBGCNTL_EXEC_MASK;
2531                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2532                                    dbg_ctrl_reg);
2533                 if (err < 0)
2534                         return err;
2535         }
2536
2537         return 0;
2538 }
2539
2540 /*
2541  * Reset the DSP
2542  */
2543 static int dsp_reset(struct hda_codec *codec)
2544 {
2545         unsigned int res;
2546         int retry = 20;
2547
2548         codec_dbg(codec, "dsp_reset\n");
2549         do {
2550                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2551                 retry--;
2552         } while (res == -EIO && retry);
2553
2554         if (!retry) {
2555                 codec_dbg(codec, "dsp_reset timeout\n");
2556                 return -EIO;
2557         }
2558
2559         return 0;
2560 }
2561
2562 /*
2563  * Convert chip address to DSP address
2564  */
2565 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2566                                         bool *code, bool *yram)
2567 {
2568         *code = *yram = false;
2569
2570         if (UC_RANGE(chip_addx, 1)) {
2571                 *code = true;
2572                 return UC_OFF(chip_addx);
2573         } else if (X_RANGE_ALL(chip_addx, 1)) {
2574                 return X_OFF(chip_addx);
2575         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2576                 *yram = true;
2577                 return Y_OFF(chip_addx);
2578         }
2579
2580         return INVALID_CHIP_ADDRESS;
2581 }
2582
2583 /*
2584  * Check if the DSP DMA is active
2585  */
2586 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2587 {
2588         unsigned int dma_chnlstart_reg;
2589
2590         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2591
2592         return ((dma_chnlstart_reg & (1 <<
2593                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2594 }
2595
2596 static int dsp_dma_setup_common(struct hda_codec *codec,
2597                                 unsigned int chip_addx,
2598                                 unsigned int dma_chan,
2599                                 unsigned int port_map_mask,
2600                                 bool ovly)
2601 {
2602         int status = 0;
2603         unsigned int chnl_prop;
2604         unsigned int dsp_addx;
2605         unsigned int active;
2606         bool code, yram;
2607
2608         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2609
2610         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2611                 codec_dbg(codec, "dma chan num invalid\n");
2612                 return -EINVAL;
2613         }
2614
2615         if (dsp_is_dma_active(codec, dma_chan)) {
2616                 codec_dbg(codec, "dma already active\n");
2617                 return -EBUSY;
2618         }
2619
2620         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2621
2622         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2623                 codec_dbg(codec, "invalid chip addr\n");
2624                 return -ENXIO;
2625         }
2626
2627         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2628         active = 0;
2629
2630         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2631
2632         if (ovly) {
2633                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2634                                      &chnl_prop);
2635
2636                 if (status < 0) {
2637                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2638                         return status;
2639                 }
2640                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2641         }
2642
2643         if (!code)
2644                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2645         else
2646                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2647
2648         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2649
2650         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2651         if (status < 0) {
2652                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2653                 return status;
2654         }
2655         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2656
2657         if (ovly) {
2658                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2659                                      &active);
2660
2661                 if (status < 0) {
2662                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2663                         return status;
2664                 }
2665                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2666         }
2667
2668         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2669                 DSPDMAC_ACTIVE_AAR_MASK;
2670
2671         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2672         if (status < 0) {
2673                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2674                 return status;
2675         }
2676
2677         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2678
2679         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2680                               port_map_mask);
2681         if (status < 0) {
2682                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2683                 return status;
2684         }
2685         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2686
2687         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2688                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2689         if (status < 0) {
2690                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2691                 return status;
2692         }
2693         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2694
2695         codec_dbg(codec,
2696                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2697                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2698                    chip_addx, dsp_addx, dma_chan,
2699                    port_map_mask, chnl_prop, active);
2700
2701         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2702
2703         return 0;
2704 }
2705
2706 /*
2707  * Setup the DSP DMA per-transfer-specific registers
2708  */
2709 static int dsp_dma_setup(struct hda_codec *codec,
2710                         unsigned int chip_addx,
2711                         unsigned int count,
2712                         unsigned int dma_chan)
2713 {
2714         int status = 0;
2715         bool code, yram;
2716         unsigned int dsp_addx;
2717         unsigned int addr_field;
2718         unsigned int incr_field;
2719         unsigned int base_cnt;
2720         unsigned int cur_cnt;
2721         unsigned int dma_cfg = 0;
2722         unsigned int adr_ofs = 0;
2723         unsigned int xfr_cnt = 0;
2724         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2725                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2726
2727         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2728
2729         if (count > max_dma_count) {
2730                 codec_dbg(codec, "count too big\n");
2731                 return -EINVAL;
2732         }
2733
2734         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2735         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2736                 codec_dbg(codec, "invalid chip addr\n");
2737                 return -ENXIO;
2738         }
2739
2740         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2741
2742         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2743         incr_field   = 0;
2744
2745         if (!code) {
2746                 addr_field <<= 1;
2747                 if (yram)
2748                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2749
2750                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2751         }
2752
2753         dma_cfg = addr_field + incr_field;
2754         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2755                                 dma_cfg);
2756         if (status < 0) {
2757                 codec_dbg(codec, "write DMACFG Reg fail\n");
2758                 return status;
2759         }
2760         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2761
2762         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2763                                                         (code ? 0 : 1));
2764
2765         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2766                                 adr_ofs);
2767         if (status < 0) {
2768                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2769                 return status;
2770         }
2771         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2772
2773         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2774
2775         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2776
2777         xfr_cnt = base_cnt | cur_cnt;
2778
2779         status = chipio_write(codec,
2780                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2781         if (status < 0) {
2782                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2783                 return status;
2784         }
2785         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2786
2787         codec_dbg(codec,
2788                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2789                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2790                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2791
2792         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2793
2794         return 0;
2795 }
2796
2797 /*
2798  * Start the DSP DMA
2799  */
2800 static int dsp_dma_start(struct hda_codec *codec,
2801                          unsigned int dma_chan, bool ovly)
2802 {
2803         unsigned int reg = 0;
2804         int status = 0;
2805
2806         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2807
2808         if (ovly) {
2809                 status = chipio_read(codec,
2810                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2811
2812                 if (status < 0) {
2813                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2814                         return status;
2815                 }
2816                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2817
2818                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2819                                 DSPDMAC_CHNLSTART_DIS_MASK);
2820         }
2821
2822         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2823                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2824         if (status < 0) {
2825                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2826                 return status;
2827         }
2828         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2829
2830         return status;
2831 }
2832
2833 /*
2834  * Stop the DSP DMA
2835  */
2836 static int dsp_dma_stop(struct hda_codec *codec,
2837                         unsigned int dma_chan, bool ovly)
2838 {
2839         unsigned int reg = 0;
2840         int status = 0;
2841
2842         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2843
2844         if (ovly) {
2845                 status = chipio_read(codec,
2846                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2847
2848                 if (status < 0) {
2849                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2850                         return status;
2851                 }
2852                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2853                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2854                                 DSPDMAC_CHNLSTART_DIS_MASK);
2855         }
2856
2857         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2858                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2859         if (status < 0) {
2860                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2861                 return status;
2862         }
2863         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2864
2865         return status;
2866 }
2867
2868 /**
2869  * dsp_allocate_router_ports - Allocate router ports
2870  *
2871  * @codec: the HDA codec
2872  * @num_chans: number of channels in the stream
2873  * @ports_per_channel: number of ports per channel
2874  * @start_device: start device
2875  * @port_map: pointer to the port list to hold the allocated ports
2876  *
2877  * Returns zero or a negative error code.
2878  */
2879 static int dsp_allocate_router_ports(struct hda_codec *codec,
2880                                      unsigned int num_chans,
2881                                      unsigned int ports_per_channel,
2882                                      unsigned int start_device,
2883                                      unsigned int *port_map)
2884 {
2885         int status = 0;
2886         int res;
2887         u8 val;
2888
2889         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2890         if (status < 0)
2891                 return status;
2892
2893         val = start_device << 6;
2894         val |= (ports_per_channel - 1) << 4;
2895         val |= num_chans - 1;
2896
2897         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2898                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2899                             val);
2900
2901         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2902                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2903                             MEM_CONNID_DSP);
2904
2905         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2906         if (status < 0)
2907                 return status;
2908
2909         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2910                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2911
2912         *port_map = res;
2913
2914         return (res < 0) ? res : 0;
2915 }
2916
2917 /*
2918  * Free router ports
2919  */
2920 static int dsp_free_router_ports(struct hda_codec *codec)
2921 {
2922         int status = 0;
2923
2924         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2925         if (status < 0)
2926                 return status;
2927
2928         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2929                             VENDOR_CHIPIO_PORT_FREE_SET,
2930                             MEM_CONNID_DSP);
2931
2932         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2933
2934         return status;
2935 }
2936
2937 /*
2938  * Allocate DSP ports for the download stream
2939  */
2940 static int dsp_allocate_ports(struct hda_codec *codec,
2941                         unsigned int num_chans,
2942                         unsigned int rate_multi, unsigned int *port_map)
2943 {
2944         int status;
2945
2946         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2947
2948         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2949                 codec_dbg(codec, "bad rate multiple\n");
2950                 return -EINVAL;
2951         }
2952
2953         status = dsp_allocate_router_ports(codec, num_chans,
2954                                            rate_multi, 0, port_map);
2955
2956         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2957
2958         return status;
2959 }
2960
2961 static int dsp_allocate_ports_format(struct hda_codec *codec,
2962                         const unsigned short fmt,
2963                         unsigned int *port_map)
2964 {
2965         unsigned int num_chans;
2966
2967         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2968         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2969         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2970
2971         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2972                 codec_dbg(codec, "bad rate multiple\n");
2973                 return -EINVAL;
2974         }
2975
2976         num_chans = get_hdafmt_chs(fmt) + 1;
2977
2978         return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2979 }
2980
2981 /*
2982  * free DSP ports
2983  */
2984 static int dsp_free_ports(struct hda_codec *codec)
2985 {
2986         int status;
2987
2988         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2989
2990         status = dsp_free_router_ports(codec);
2991         if (status < 0) {
2992                 codec_dbg(codec, "free router ports fail\n");
2993                 return status;
2994         }
2995         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2996
2997         return status;
2998 }
2999
3000 /*
3001  *  HDA DMA engine stuffs for DSP code download
3002  */
3003 struct dma_engine {
3004         struct hda_codec *codec;
3005         unsigned short m_converter_format;
3006         struct snd_dma_buffer *dmab;
3007         unsigned int buf_size;
3008 };
3009
3010
3011 enum dma_state {
3012         DMA_STATE_STOP  = 0,
3013         DMA_STATE_RUN   = 1
3014 };
3015
3016 static int dma_convert_to_hda_format(struct hda_codec *codec,
3017                 unsigned int sample_rate,
3018                 unsigned short channels,
3019                 unsigned short *hda_format)
3020 {
3021         unsigned int format_val;
3022
3023         format_val = snd_hdac_calc_stream_format(sample_rate,
3024                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3025
3026         if (hda_format)
3027                 *hda_format = (unsigned short)format_val;
3028
3029         return 0;
3030 }
3031
3032 /*
3033  *  Reset DMA for DSP download
3034  */
3035 static int dma_reset(struct dma_engine *dma)
3036 {
3037         struct hda_codec *codec = dma->codec;
3038         struct ca0132_spec *spec = codec->spec;
3039         int status;
3040
3041         if (dma->dmab->area)
3042                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3043
3044         status = snd_hda_codec_load_dsp_prepare(codec,
3045                         dma->m_converter_format,
3046                         dma->buf_size,
3047                         dma->dmab);
3048         if (status < 0)
3049                 return status;
3050         spec->dsp_stream_id = status;
3051         return 0;
3052 }
3053
3054 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3055 {
3056         bool cmd;
3057
3058         switch (state) {
3059         case DMA_STATE_STOP:
3060                 cmd = false;
3061                 break;
3062         case DMA_STATE_RUN:
3063                 cmd = true;
3064                 break;
3065         default:
3066                 return 0;
3067         }
3068
3069         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3070         return 0;
3071 }
3072
3073 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3074 {
3075         return dma->dmab->bytes;
3076 }
3077
3078 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3079 {
3080         return dma->dmab->area;
3081 }
3082
3083 static int dma_xfer(struct dma_engine *dma,
3084                 const unsigned int *data,
3085                 unsigned int count)
3086 {
3087         memcpy(dma->dmab->area, data, count);
3088         return 0;
3089 }
3090
3091 static void dma_get_converter_format(
3092                 struct dma_engine *dma,
3093                 unsigned short *format)
3094 {
3095         if (format)
3096                 *format = dma->m_converter_format;
3097 }
3098
3099 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3100 {
3101         struct ca0132_spec *spec = dma->codec->spec;
3102
3103         return spec->dsp_stream_id;
3104 }
3105
3106 struct dsp_image_seg {
3107         u32 magic;
3108         u32 chip_addr;
3109         u32 count;
3110         u32 data[];
3111 };
3112
3113 static const u32 g_magic_value = 0x4c46584d;
3114 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3115
3116 static bool is_valid(const struct dsp_image_seg *p)
3117 {
3118         return p->magic == g_magic_value;
3119 }
3120
3121 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3122 {
3123         return g_chip_addr_magic_value == p->chip_addr;
3124 }
3125
3126 static bool is_last(const struct dsp_image_seg *p)
3127 {
3128         return p->count == 0;
3129 }
3130
3131 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3132 {
3133         return struct_size(p, data, p->count);
3134 }
3135
3136 static const struct dsp_image_seg *get_next_seg_ptr(
3137                                 const struct dsp_image_seg *p)
3138 {
3139         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3140 }
3141
3142 /*
3143  * CA0132 chip DSP transfer stuffs.  For DSP download.
3144  */
3145 #define INVALID_DMA_CHANNEL (~0U)
3146
3147 /*
3148  * Program a list of address/data pairs via the ChipIO widget.
3149  * The segment data is in the format of successive pairs of words.
3150  * These are repeated as indicated by the segment's count field.
3151  */
3152 static int dspxfr_hci_write(struct hda_codec *codec,
3153                         const struct dsp_image_seg *fls)
3154 {
3155         int status;
3156         const u32 *data;
3157         unsigned int count;
3158
3159         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3160                 codec_dbg(codec, "hci_write invalid params\n");
3161                 return -EINVAL;
3162         }
3163
3164         count = fls->count;
3165         data = (u32 *)(fls->data);
3166         while (count >= 2) {
3167                 status = chipio_write(codec, data[0], data[1]);
3168                 if (status < 0) {
3169                         codec_dbg(codec, "hci_write chipio failed\n");
3170                         return status;
3171                 }
3172                 count -= 2;
3173                 data  += 2;
3174         }
3175         return 0;
3176 }
3177
3178 /**
3179  * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3180  *
3181  * @codec: the HDA codec
3182  * @fls: pointer to a fast load image
3183  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3184  *         no relocation
3185  * @dma_engine: pointer to DMA engine to be used for DSP download
3186  * @dma_chan: The number of DMA channels used for DSP download
3187  * @port_map_mask: port mapping
3188  * @ovly: TRUE if overlay format is required
3189  *
3190  * Returns zero or a negative error code.
3191  */
3192 static int dspxfr_one_seg(struct hda_codec *codec,
3193                         const struct dsp_image_seg *fls,
3194                         unsigned int reloc,
3195                         struct dma_engine *dma_engine,
3196                         unsigned int dma_chan,
3197                         unsigned int port_map_mask,
3198                         bool ovly)
3199 {
3200         int status = 0;
3201         bool comm_dma_setup_done = false;
3202         const unsigned int *data;
3203         unsigned int chip_addx;
3204         unsigned int words_to_write;
3205         unsigned int buffer_size_words;
3206         unsigned char *buffer_addx;
3207         unsigned short hda_format;
3208         unsigned int sample_rate_div;
3209         unsigned int sample_rate_mul;
3210         unsigned int num_chans;
3211         unsigned int hda_frame_size_words;
3212         unsigned int remainder_words;
3213         const u32 *data_remainder;
3214         u32 chip_addx_remainder;
3215         unsigned int run_size_words;
3216         const struct dsp_image_seg *hci_write = NULL;
3217         unsigned long timeout;
3218         bool dma_active;
3219
3220         if (fls == NULL)
3221                 return -EINVAL;
3222         if (is_hci_prog_list_seg(fls)) {
3223                 hci_write = fls;
3224                 fls = get_next_seg_ptr(fls);
3225         }
3226
3227         if (hci_write && (!fls || is_last(fls))) {
3228                 codec_dbg(codec, "hci_write\n");
3229                 return dspxfr_hci_write(codec, hci_write);
3230         }
3231
3232         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3233                 codec_dbg(codec, "Invalid Params\n");
3234                 return -EINVAL;
3235         }
3236
3237         data = fls->data;
3238         chip_addx = fls->chip_addr;
3239         words_to_write = fls->count;
3240
3241         if (!words_to_write)
3242                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3243         if (reloc)
3244                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3245
3246         if (!UC_RANGE(chip_addx, words_to_write) &&
3247             !X_RANGE_ALL(chip_addx, words_to_write) &&
3248             !Y_RANGE_ALL(chip_addx, words_to_write)) {
3249                 codec_dbg(codec, "Invalid chip_addx Params\n");
3250                 return -EINVAL;
3251         }
3252
3253         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3254                                         sizeof(u32);
3255
3256         buffer_addx = dma_get_buffer_addr(dma_engine);
3257
3258         if (buffer_addx == NULL) {
3259                 codec_dbg(codec, "dma_engine buffer NULL\n");
3260                 return -EINVAL;
3261         }
3262
3263         dma_get_converter_format(dma_engine, &hda_format);
3264         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3265         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3266         num_chans = get_hdafmt_chs(hda_format) + 1;
3267
3268         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3269                         (num_chans * sample_rate_mul / sample_rate_div));
3270
3271         if (hda_frame_size_words == 0) {
3272                 codec_dbg(codec, "frmsz zero\n");
3273                 return -EINVAL;
3274         }
3275
3276         buffer_size_words = min(buffer_size_words,
3277                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3278                                 65536 : 32768));
3279         buffer_size_words -= buffer_size_words % hda_frame_size_words;
3280         codec_dbg(codec,
3281                    "chpadr=0x%08x frmsz=%u nchan=%u "
3282                    "rate_mul=%u div=%u bufsz=%u\n",
3283                    chip_addx, hda_frame_size_words, num_chans,
3284                    sample_rate_mul, sample_rate_div, buffer_size_words);
3285
3286         if (buffer_size_words < hda_frame_size_words) {
3287                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3288                 return -EINVAL;
3289         }
3290
3291         remainder_words = words_to_write % hda_frame_size_words;
3292         data_remainder = data;
3293         chip_addx_remainder = chip_addx;
3294
3295         data += remainder_words;
3296         chip_addx += remainder_words*sizeof(u32);
3297         words_to_write -= remainder_words;
3298
3299         while (words_to_write != 0) {
3300                 run_size_words = min(buffer_size_words, words_to_write);
3301                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3302                             words_to_write, run_size_words, remainder_words);
3303                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3304                 if (!comm_dma_setup_done) {
3305                         status = dsp_dma_stop(codec, dma_chan, ovly);
3306                         if (status < 0)
3307                                 return status;
3308                         status = dsp_dma_setup_common(codec, chip_addx,
3309                                                 dma_chan, port_map_mask, ovly);
3310                         if (status < 0)
3311                                 return status;
3312                         comm_dma_setup_done = true;
3313                 }
3314
3315                 status = dsp_dma_setup(codec, chip_addx,
3316                                                 run_size_words, dma_chan);
3317                 if (status < 0)
3318                         return status;
3319                 status = dsp_dma_start(codec, dma_chan, ovly);
3320                 if (status < 0)
3321                         return status;
3322                 if (!dsp_is_dma_active(codec, dma_chan)) {
3323                         codec_dbg(codec, "dspxfr:DMA did not start\n");
3324                         return -EIO;
3325                 }
3326                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3327                 if (status < 0)
3328                         return status;
3329                 if (remainder_words != 0) {
3330                         status = chipio_write_multiple(codec,
3331                                                 chip_addx_remainder,
3332                                                 data_remainder,
3333                                                 remainder_words);
3334                         if (status < 0)
3335                                 return status;
3336                         remainder_words = 0;
3337                 }
3338                 if (hci_write) {
3339                         status = dspxfr_hci_write(codec, hci_write);
3340                         if (status < 0)
3341                                 return status;
3342                         hci_write = NULL;
3343                 }
3344
3345                 timeout = jiffies + msecs_to_jiffies(2000);
3346                 do {
3347                         dma_active = dsp_is_dma_active(codec, dma_chan);
3348                         if (!dma_active)
3349                                 break;
3350                         msleep(20);
3351                 } while (time_before(jiffies, timeout));
3352                 if (dma_active)
3353                         break;
3354
3355                 codec_dbg(codec, "+++++ DMA complete\n");
3356                 dma_set_state(dma_engine, DMA_STATE_STOP);
3357                 status = dma_reset(dma_engine);
3358
3359                 if (status < 0)
3360                         return status;
3361
3362                 data += run_size_words;
3363                 chip_addx += run_size_words*sizeof(u32);
3364                 words_to_write -= run_size_words;
3365         }
3366
3367         if (remainder_words != 0) {
3368                 status = chipio_write_multiple(codec, chip_addx_remainder,
3369                                         data_remainder, remainder_words);
3370         }
3371
3372         return status;
3373 }
3374
3375 /**
3376  * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3377  *
3378  * @codec: the HDA codec
3379  * @fls_data: pointer to a fast load image
3380  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3381  *         no relocation
3382  * @sample_rate: sampling rate of the stream used for DSP download
3383  * @channels: channels of the stream used for DSP download
3384  * @ovly: TRUE if overlay format is required
3385  *
3386  * Returns zero or a negative error code.
3387  */
3388 static int dspxfr_image(struct hda_codec *codec,
3389                         const struct dsp_image_seg *fls_data,
3390                         unsigned int reloc,
3391                         unsigned int sample_rate,
3392                         unsigned short channels,
3393                         bool ovly)
3394 {
3395         struct ca0132_spec *spec = codec->spec;
3396         int status;
3397         unsigned short hda_format = 0;
3398         unsigned int response;
3399         unsigned char stream_id = 0;
3400         struct dma_engine *dma_engine;
3401         unsigned int dma_chan;
3402         unsigned int port_map_mask;
3403
3404         if (fls_data == NULL)
3405                 return -EINVAL;
3406
3407         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3408         if (!dma_engine)
3409                 return -ENOMEM;
3410
3411         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3412         if (!dma_engine->dmab) {
3413                 kfree(dma_engine);
3414                 return -ENOMEM;
3415         }
3416
3417         dma_engine->codec = codec;
3418         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3419         dma_engine->m_converter_format = hda_format;
3420         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3421                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3422
3423         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3424
3425         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3426                                         hda_format, &response);
3427
3428         if (status < 0) {
3429                 codec_dbg(codec, "set converter format fail\n");
3430                 goto exit;
3431         }
3432
3433         status = snd_hda_codec_load_dsp_prepare(codec,
3434                                 dma_engine->m_converter_format,
3435                                 dma_engine->buf_size,
3436                                 dma_engine->dmab);
3437         if (status < 0)
3438                 goto exit;
3439         spec->dsp_stream_id = status;
3440
3441         if (ovly) {
3442                 status = dspio_alloc_dma_chan(codec, &dma_chan);
3443                 if (status < 0) {
3444                         codec_dbg(codec, "alloc dmachan fail\n");
3445                         dma_chan = INVALID_DMA_CHANNEL;
3446                         goto exit;
3447                 }
3448         }
3449
3450         port_map_mask = 0;
3451         status = dsp_allocate_ports_format(codec, hda_format,
3452                                         &port_map_mask);
3453         if (status < 0) {
3454                 codec_dbg(codec, "alloc ports fail\n");
3455                 goto exit;
3456         }
3457
3458         stream_id = dma_get_stream_id(dma_engine);
3459         status = codec_set_converter_stream_channel(codec,
3460                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
3461         if (status < 0) {
3462                 codec_dbg(codec, "set stream chan fail\n");
3463                 goto exit;
3464         }
3465
3466         while ((fls_data != NULL) && !is_last(fls_data)) {
3467                 if (!is_valid(fls_data)) {
3468                         codec_dbg(codec, "FLS check fail\n");
3469                         status = -EINVAL;
3470                         goto exit;
3471                 }
3472                 status = dspxfr_one_seg(codec, fls_data, reloc,
3473                                         dma_engine, dma_chan,
3474                                         port_map_mask, ovly);
3475                 if (status < 0)
3476                         break;
3477
3478                 if (is_hci_prog_list_seg(fls_data))
3479                         fls_data = get_next_seg_ptr(fls_data);
3480
3481                 if ((fls_data != NULL) && !is_last(fls_data))
3482                         fls_data = get_next_seg_ptr(fls_data);
3483         }
3484
3485         if (port_map_mask != 0)
3486                 status = dsp_free_ports(codec);
3487
3488         if (status < 0)
3489                 goto exit;
3490
3491         status = codec_set_converter_stream_channel(codec,
3492                                 WIDGET_CHIP_CTRL, 0, 0, &response);
3493
3494 exit:
3495         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3496                 dspio_free_dma_chan(codec, dma_chan);
3497
3498         if (dma_engine->dmab->area)
3499                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3500         kfree(dma_engine->dmab);
3501         kfree(dma_engine);
3502
3503         return status;
3504 }
3505
3506 /*
3507  * CA0132 DSP download stuffs.
3508  */
3509 static void dspload_post_setup(struct hda_codec *codec)
3510 {
3511         struct ca0132_spec *spec = codec->spec;
3512         codec_dbg(codec, "---- dspload_post_setup ------\n");
3513         if (!ca0132_use_alt_functions(spec)) {
3514                 /*set DSP speaker to 2.0 configuration*/
3515                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3516                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3517
3518                 /*update write pointer*/
3519                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3520         }
3521 }
3522
3523 /**
3524  * dspload_image - Download DSP from a DSP Image Fast Load structure.
3525  *
3526  * @codec: the HDA codec
3527  * @fls: pointer to a fast load image
3528  * @ovly: TRUE if overlay format is required
3529  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3530  *         no relocation
3531  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3532  * @router_chans: number of audio router channels to be allocated (0 means use
3533  *                internal defaults; max is 32)
3534  *
3535  * Download DSP from a DSP Image Fast Load structure. This structure is a
3536  * linear, non-constant sized element array of structures, each of which
3537  * contain the count of the data to be loaded, the data itself, and the
3538  * corresponding starting chip address of the starting data location.
3539  * Returns zero or a negative error code.
3540  */
3541 static int dspload_image(struct hda_codec *codec,
3542                         const struct dsp_image_seg *fls,
3543                         bool ovly,
3544                         unsigned int reloc,
3545                         bool autostart,
3546                         int router_chans)
3547 {
3548         int status = 0;
3549         unsigned int sample_rate;
3550         unsigned short channels;
3551
3552         codec_dbg(codec, "---- dspload_image begin ------\n");
3553         if (router_chans == 0) {
3554                 if (!ovly)
3555                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3556                 else
3557                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3558         }
3559
3560         sample_rate = 48000;
3561         channels = (unsigned short)router_chans;
3562
3563         while (channels > 16) {
3564                 sample_rate *= 2;
3565                 channels /= 2;
3566         }
3567
3568         do {
3569                 codec_dbg(codec, "Ready to program DMA\n");
3570                 if (!ovly)
3571                         status = dsp_reset(codec);
3572
3573                 if (status < 0)
3574                         break;
3575
3576                 codec_dbg(codec, "dsp_reset() complete\n");
3577                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3578                                       ovly);
3579
3580                 if (status < 0)
3581                         break;
3582
3583                 codec_dbg(codec, "dspxfr_image() complete\n");
3584                 if (autostart && !ovly) {
3585                         dspload_post_setup(codec);
3586                         status = dsp_set_run_state(codec);
3587                 }
3588
3589                 codec_dbg(codec, "LOAD FINISHED\n");
3590         } while (0);
3591
3592         return status;
3593 }
3594
3595 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3596 static bool dspload_is_loaded(struct hda_codec *codec)
3597 {
3598         unsigned int data = 0;
3599         int status = 0;
3600
3601         status = chipio_read(codec, 0x40004, &data);
3602         if ((status < 0) || (data != 1))
3603                 return false;
3604
3605         return true;
3606 }
3607 #else
3608 #define dspload_is_loaded(codec)        false
3609 #endif
3610
3611 static bool dspload_wait_loaded(struct hda_codec *codec)
3612 {
3613         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3614
3615         do {
3616                 if (dspload_is_loaded(codec)) {
3617                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3618                         return true;
3619                 }
3620                 msleep(20);
3621         } while (time_before(jiffies, timeout));
3622
3623         codec_err(codec, "ca0132 failed to download DSP\n");
3624         return false;
3625 }
3626
3627 /*
3628  * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3629  * based cards, and has a second mmio region, region2, that's used for special
3630  * commands.
3631  */
3632
3633 /*
3634  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3635  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3636  * The first eight bits are just the number of the pin. So far, I've only seen
3637  * this number go to 7.
3638  * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3639  * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3640  * then off to send that bit.
3641  */
3642 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3643                 bool enable)
3644 {
3645         struct ca0132_spec *spec = codec->spec;
3646         unsigned short gpio_data;
3647
3648         gpio_data = gpio_pin & 0xF;
3649         gpio_data |= ((enable << 8) & 0x100);
3650
3651         writew(gpio_data, spec->mem_base + 0x320);
3652 }
3653
3654 /*
3655  * Special pci region2 commands that are only used by the AE-5. They follow
3656  * a set format, and require reads at certain points to seemingly 'clear'
3657  * the response data. My first tests didn't do these reads, and would cause
3658  * the card to get locked up until the memory was read. These commands
3659  * seem to work with three distinct values that I've taken to calling group,
3660  * target-id, and value.
3661  */
3662 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3663                 unsigned int target, unsigned int value)
3664 {
3665         struct ca0132_spec *spec = codec->spec;
3666         unsigned int write_val;
3667
3668         writel(0x0000007e, spec->mem_base + 0x210);
3669         readl(spec->mem_base + 0x210);
3670         writel(0x0000005a, spec->mem_base + 0x210);
3671         readl(spec->mem_base + 0x210);
3672         readl(spec->mem_base + 0x210);
3673
3674         writel(0x00800005, spec->mem_base + 0x20c);
3675         writel(group, spec->mem_base + 0x804);
3676
3677         writel(0x00800005, spec->mem_base + 0x20c);
3678         write_val = (target & 0xff);
3679         write_val |= (value << 8);
3680
3681
3682         writel(write_val, spec->mem_base + 0x204);
3683         /*
3684          * Need delay here or else it goes too fast and works inconsistently.
3685          */
3686         msleep(20);
3687
3688         readl(spec->mem_base + 0x860);
3689         readl(spec->mem_base + 0x854);
3690         readl(spec->mem_base + 0x840);
3691
3692         writel(0x00800004, spec->mem_base + 0x20c);
3693         writel(0x00000000, spec->mem_base + 0x210);
3694         readl(spec->mem_base + 0x210);
3695         readl(spec->mem_base + 0x210);
3696 }
3697
3698 /*
3699  * This second type of command is used for setting the sound filter type.
3700  */
3701 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3702                 unsigned int group, unsigned int target, unsigned int value)
3703 {
3704         struct ca0132_spec *spec = codec->spec;
3705         unsigned int write_val;
3706
3707         writel(0x0000007e, spec->mem_base + 0x210);
3708         readl(spec->mem_base + 0x210);
3709         writel(0x0000005a, spec->mem_base + 0x210);
3710         readl(spec->mem_base + 0x210);
3711         readl(spec->mem_base + 0x210);
3712
3713         writel(0x00800003, spec->mem_base + 0x20c);
3714         writel(group, spec->mem_base + 0x804);
3715
3716         writel(0x00800005, spec->mem_base + 0x20c);
3717         write_val = (target & 0xff);
3718         write_val |= (value << 8);
3719
3720
3721         writel(write_val, spec->mem_base + 0x204);
3722         msleep(20);
3723         readl(spec->mem_base + 0x860);
3724         readl(spec->mem_base + 0x854);
3725         readl(spec->mem_base + 0x840);
3726
3727         writel(0x00800004, spec->mem_base + 0x20c);
3728         writel(0x00000000, spec->mem_base + 0x210);
3729         readl(spec->mem_base + 0x210);
3730         readl(spec->mem_base + 0x210);
3731 }
3732
3733 /*
3734  * Setup GPIO for the other variants of Core3D.
3735  */
3736
3737 /*
3738  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3739  * the card shows as having no GPIO pins.
3740  */
3741 static void ca0132_gpio_init(struct hda_codec *codec)
3742 {
3743         struct ca0132_spec *spec = codec->spec;
3744
3745         switch (ca0132_quirk(spec)) {
3746         case QUIRK_SBZ:
3747         case QUIRK_AE5:
3748         case QUIRK_AE7:
3749                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3750                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3751                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3752                 break;
3753         case QUIRK_R3DI:
3754                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3755                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3756                 break;
3757         default:
3758                 break;
3759         }
3760
3761 }
3762
3763 /* Sets the GPIO for audio output. */
3764 static void ca0132_gpio_setup(struct hda_codec *codec)
3765 {
3766         struct ca0132_spec *spec = codec->spec;
3767
3768         switch (ca0132_quirk(spec)) {
3769         case QUIRK_SBZ:
3770                 snd_hda_codec_write(codec, 0x01, 0,
3771                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3772                 snd_hda_codec_write(codec, 0x01, 0,
3773                                 AC_VERB_SET_GPIO_MASK, 0x07);
3774                 snd_hda_codec_write(codec, 0x01, 0,
3775                                 AC_VERB_SET_GPIO_DATA, 0x04);
3776                 snd_hda_codec_write(codec, 0x01, 0,
3777                                 AC_VERB_SET_GPIO_DATA, 0x06);
3778                 break;
3779         case QUIRK_R3DI:
3780                 snd_hda_codec_write(codec, 0x01, 0,
3781                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3782                 snd_hda_codec_write(codec, 0x01, 0,
3783                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3784                 snd_hda_codec_write(codec, 0x01, 0,
3785                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3786                 break;
3787         default:
3788                 break;
3789         }
3790 }
3791
3792 /*
3793  * GPIO control functions for the Recon3D integrated.
3794  */
3795
3796 enum r3di_gpio_bit {
3797         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3798         R3DI_MIC_SELECT_BIT = 1,
3799         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3800         R3DI_OUT_SELECT_BIT = 2,
3801         /*
3802          * I dunno what this actually does, but it stays on until the dsp
3803          * is downloaded.
3804          */
3805         R3DI_GPIO_DSP_DOWNLOADING = 3,
3806         /*
3807          * Same as above, no clue what it does, but it comes on after the dsp
3808          * is downloaded.
3809          */
3810         R3DI_GPIO_DSP_DOWNLOADED = 4
3811 };
3812
3813 enum r3di_mic_select {
3814         /* Set GPIO bit 1 to 0 for rear mic */
3815         R3DI_REAR_MIC = 0,
3816         /* Set GPIO bit 1 to 1 for front microphone*/
3817         R3DI_FRONT_MIC = 1
3818 };
3819
3820 enum r3di_out_select {
3821         /* Set GPIO bit 2 to 0 for headphone */
3822         R3DI_HEADPHONE_OUT = 0,
3823         /* Set GPIO bit 2 to 1 for speaker */
3824         R3DI_LINE_OUT = 1
3825 };
3826 enum r3di_dsp_status {
3827         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3828         R3DI_DSP_DOWNLOADING = 0,
3829         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3830         R3DI_DSP_DOWNLOADED = 1
3831 };
3832
3833
3834 static void r3di_gpio_mic_set(struct hda_codec *codec,
3835                 enum r3di_mic_select cur_mic)
3836 {
3837         unsigned int cur_gpio;
3838
3839         /* Get the current GPIO Data setup */
3840         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3841
3842         switch (cur_mic) {
3843         case R3DI_REAR_MIC:
3844                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3845                 break;
3846         case R3DI_FRONT_MIC:
3847                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3848                 break;
3849         }
3850         snd_hda_codec_write(codec, codec->core.afg, 0,
3851                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3852 }
3853
3854 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3855                 enum r3di_dsp_status dsp_status)
3856 {
3857         unsigned int cur_gpio;
3858
3859         /* Get the current GPIO Data setup */
3860         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3861
3862         switch (dsp_status) {
3863         case R3DI_DSP_DOWNLOADING:
3864                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3865                 snd_hda_codec_write(codec, codec->core.afg, 0,
3866                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3867                 break;
3868         case R3DI_DSP_DOWNLOADED:
3869                 /* Set DOWNLOADING bit to 0. */
3870                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3871
3872                 snd_hda_codec_write(codec, codec->core.afg, 0,
3873                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3874
3875                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3876                 break;
3877         }
3878
3879         snd_hda_codec_write(codec, codec->core.afg, 0,
3880                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3881 }
3882
3883 /*
3884  * PCM callbacks
3885  */
3886 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3887                         struct hda_codec *codec,
3888                         unsigned int stream_tag,
3889                         unsigned int format,
3890                         struct snd_pcm_substream *substream)
3891 {
3892         struct ca0132_spec *spec = codec->spec;
3893
3894         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3895
3896         return 0;
3897 }
3898
3899 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3900                         struct hda_codec *codec,
3901                         struct snd_pcm_substream *substream)
3902 {
3903         struct ca0132_spec *spec = codec->spec;
3904
3905         if (spec->dsp_state == DSP_DOWNLOADING)
3906                 return 0;
3907
3908         /*If Playback effects are on, allow stream some time to flush
3909          *effects tail*/
3910         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3911                 msleep(50);
3912
3913         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3914
3915         return 0;
3916 }
3917
3918 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3919                         struct hda_codec *codec,
3920                         struct snd_pcm_substream *substream)
3921 {
3922         struct ca0132_spec *spec = codec->spec;
3923         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3924         struct snd_pcm_runtime *runtime = substream->runtime;
3925
3926         if (spec->dsp_state != DSP_DOWNLOADED)
3927                 return 0;
3928
3929         /* Add latency if playback enhancement and either effect is enabled. */
3930         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3931                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3932                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3933                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3934         }
3935
3936         /* Applying Speaker EQ adds latency as well. */
3937         if (spec->cur_out_type == SPEAKER_OUT)
3938                 latency += DSP_SPEAKER_OUT_LATENCY;
3939
3940         return (latency * runtime->rate) / 1000;
3941 }
3942
3943 /*
3944  * Digital out
3945  */
3946 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3947                                         struct hda_codec *codec,
3948                                         struct snd_pcm_substream *substream)
3949 {
3950         struct ca0132_spec *spec = codec->spec;
3951         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3952 }
3953
3954 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3955                         struct hda_codec *codec,
3956                         unsigned int stream_tag,
3957                         unsigned int format,
3958                         struct snd_pcm_substream *substream)
3959 {
3960         struct ca0132_spec *spec = codec->spec;
3961         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3962                                              stream_tag, format, substream);
3963 }
3964
3965 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3966                         struct hda_codec *codec,
3967                         struct snd_pcm_substream *substream)
3968 {
3969         struct ca0132_spec *spec = codec->spec;
3970         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3971 }
3972
3973 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3974                                          struct hda_codec *codec,
3975                                          struct snd_pcm_substream *substream)
3976 {
3977         struct ca0132_spec *spec = codec->spec;
3978         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3979 }
3980
3981 /*
3982  * Analog capture
3983  */
3984 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3985                                         struct hda_codec *codec,
3986                                         unsigned int stream_tag,
3987                                         unsigned int format,
3988                                         struct snd_pcm_substream *substream)
3989 {
3990         snd_hda_codec_setup_stream(codec, hinfo->nid,
3991                                    stream_tag, 0, format);
3992
3993         return 0;
3994 }
3995
3996 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3997                         struct hda_codec *codec,
3998                         struct snd_pcm_substream *substream)
3999 {
4000         struct ca0132_spec *spec = codec->spec;
4001
4002         if (spec->dsp_state == DSP_DOWNLOADING)
4003                 return 0;
4004
4005         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4006         return 0;
4007 }
4008
4009 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4010                         struct hda_codec *codec,
4011                         struct snd_pcm_substream *substream)
4012 {
4013         struct ca0132_spec *spec = codec->spec;
4014         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4015         struct snd_pcm_runtime *runtime = substream->runtime;
4016
4017         if (spec->dsp_state != DSP_DOWNLOADED)
4018                 return 0;
4019
4020         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4021                 latency += DSP_CRYSTAL_VOICE_LATENCY;
4022
4023         return (latency * runtime->rate) / 1000;
4024 }
4025
4026 /*
4027  * Controls stuffs.
4028  */
4029
4030 /*
4031  * Mixer controls helpers.
4032  */
4033 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4034         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4035           .name = xname, \
4036           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4037           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4038                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4039                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4040           .info = ca0132_volume_info, \
4041           .get = ca0132_volume_get, \
4042           .put = ca0132_volume_put, \
4043           .tlv = { .c = ca0132_volume_tlv }, \
4044           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4045
4046 /*
4047  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4048  * volume put, which is used for setting the DSP volume. This was done because
4049  * the ca0132 functions were taking too much time and causing lag.
4050  */
4051 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4052         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4053           .name = xname, \
4054           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4055           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4056                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4057                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4058           .info = snd_hda_mixer_amp_volume_info, \
4059           .get = snd_hda_mixer_amp_volume_get, \
4060           .put = ca0132_alt_volume_put, \
4061           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4062           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4063
4064 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4065         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4066           .name = xname, \
4067           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4068           .info = snd_hda_mixer_amp_switch_info, \
4069           .get = ca0132_switch_get, \
4070           .put = ca0132_switch_put, \
4071           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4072
4073 /* stereo */
4074 #define CA0132_CODEC_VOL(xname, nid, dir) \
4075         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4076 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4077         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4078 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4079         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4080
4081 /* lookup tables */
4082 /*
4083  * Lookup table with decibel values for the DSP. When volume is changed in
4084  * Windows, the DSP is also sent the dB value in floating point. In Windows,
4085  * these values have decimal points, probably because the Windows driver
4086  * actually uses floating point. We can't here, so I made a lookup table of
4087  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4088  * DAC's, and 9 is the maximum.
4089  */
4090 static const unsigned int float_vol_db_lookup[] = {
4091 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4092 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4093 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4094 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4095 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4096 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4097 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4098 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4099 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4100 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4101 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4102 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4103 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4104 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4105 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4106 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4107 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4108 };
4109
4110 /*
4111  * This table counts from float 0 to 1 in increments of .01, which is
4112  * useful for a few different sliders.
4113  */
4114 static const unsigned int float_zero_to_one_lookup[] = {
4115 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4116 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4117 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4118 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4119 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4120 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4121 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4122 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4123 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4124 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4125 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4126 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4127 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4128 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4129 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4130 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4131 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4132 };
4133
4134 /*
4135  * This table counts from float 10 to 1000, which is the range of the x-bass
4136  * crossover slider in Windows.
4137  */
4138 static const unsigned int float_xbass_xover_lookup[] = {
4139 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4140 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4141 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4142 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4143 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4144 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4145 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4146 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4147 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4148 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4149 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4150 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4151 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4152 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4153 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4154 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4155 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4156 };
4157
4158 /* The following are for tuning of products */
4159 #ifdef ENABLE_TUNING_CONTROLS
4160
4161 static const unsigned int voice_focus_vals_lookup[] = {
4162 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4163 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4164 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4165 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4166 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4167 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4168 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4169 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4170 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4171 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4172 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4173 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4174 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4175 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4176 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4177 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4178 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4179 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4180 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4181 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4182 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4183 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4184 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4185 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4186 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4187 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4188 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4189 };
4190
4191 static const unsigned int mic_svm_vals_lookup[] = {
4192 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4193 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4194 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4195 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4196 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4197 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4198 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4199 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4200 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4201 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4202 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4203 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4204 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4205 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4206 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4207 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4208 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4209 };
4210
4211 static const unsigned int equalizer_vals_lookup[] = {
4212 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4213 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4214 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4215 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4216 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4217 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4218 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4219 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4220 0x41C00000
4221 };
4222
4223 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4224                           const unsigned int *lookup, int idx)
4225 {
4226         int i = 0;
4227
4228         for (i = 0; i < TUNING_CTLS_COUNT; i++)
4229                 if (nid == ca0132_tuning_ctls[i].nid)
4230                         goto found;
4231
4232         return -EINVAL;
4233 found:
4234         snd_hda_power_up(codec);
4235         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4236                         ca0132_tuning_ctls[i].req,
4237                         &(lookup[idx]), sizeof(unsigned int));
4238         snd_hda_power_down(codec);
4239
4240         return 1;
4241 }
4242
4243 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4244                           struct snd_ctl_elem_value *ucontrol)
4245 {
4246         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4247         struct ca0132_spec *spec = codec->spec;
4248         hda_nid_t nid = get_amp_nid(kcontrol);
4249         long *valp = ucontrol->value.integer.value;
4250         int idx = nid - TUNING_CTL_START_NID;
4251
4252         *valp = spec->cur_ctl_vals[idx];
4253         return 0;
4254 }
4255
4256 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4257                               struct snd_ctl_elem_info *uinfo)
4258 {
4259         int chs = get_amp_channels(kcontrol);
4260         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4261         uinfo->count = chs == 3 ? 2 : 1;
4262         uinfo->value.integer.min = 20;
4263         uinfo->value.integer.max = 180;
4264         uinfo->value.integer.step = 1;
4265
4266         return 0;
4267 }
4268
4269 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4270                                 struct snd_ctl_elem_value *ucontrol)
4271 {
4272         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4273         struct ca0132_spec *spec = codec->spec;
4274         hda_nid_t nid = get_amp_nid(kcontrol);
4275         long *valp = ucontrol->value.integer.value;
4276         int idx;
4277
4278         idx = nid - TUNING_CTL_START_NID;
4279         /* any change? */
4280         if (spec->cur_ctl_vals[idx] == *valp)
4281                 return 0;
4282
4283         spec->cur_ctl_vals[idx] = *valp;
4284
4285         idx = *valp - 20;
4286         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4287
4288         return 1;
4289 }
4290
4291 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4292                               struct snd_ctl_elem_info *uinfo)
4293 {
4294         int chs = get_amp_channels(kcontrol);
4295         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4296         uinfo->count = chs == 3 ? 2 : 1;
4297         uinfo->value.integer.min = 0;
4298         uinfo->value.integer.max = 100;
4299         uinfo->value.integer.step = 1;
4300
4301         return 0;
4302 }
4303
4304 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4305                                 struct snd_ctl_elem_value *ucontrol)
4306 {
4307         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4308         struct ca0132_spec *spec = codec->spec;
4309         hda_nid_t nid = get_amp_nid(kcontrol);
4310         long *valp = ucontrol->value.integer.value;
4311         int idx;
4312
4313         idx = nid - TUNING_CTL_START_NID;
4314         /* any change? */
4315         if (spec->cur_ctl_vals[idx] == *valp)
4316                 return 0;
4317
4318         spec->cur_ctl_vals[idx] = *valp;
4319
4320         idx = *valp;
4321         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4322
4323         return 0;
4324 }
4325
4326 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4327                               struct snd_ctl_elem_info *uinfo)
4328 {
4329         int chs = get_amp_channels(kcontrol);
4330         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4331         uinfo->count = chs == 3 ? 2 : 1;
4332         uinfo->value.integer.min = 0;
4333         uinfo->value.integer.max = 48;
4334         uinfo->value.integer.step = 1;
4335
4336         return 0;
4337 }
4338
4339 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4340                                 struct snd_ctl_elem_value *ucontrol)
4341 {
4342         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4343         struct ca0132_spec *spec = codec->spec;
4344         hda_nid_t nid = get_amp_nid(kcontrol);
4345         long *valp = ucontrol->value.integer.value;
4346         int idx;
4347
4348         idx = nid - TUNING_CTL_START_NID;
4349         /* any change? */
4350         if (spec->cur_ctl_vals[idx] == *valp)
4351                 return 0;
4352
4353         spec->cur_ctl_vals[idx] = *valp;
4354
4355         idx = *valp;
4356         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4357
4358         return 1;
4359 }
4360
4361 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4362 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4363
4364 static int add_tuning_control(struct hda_codec *codec,
4365                                 hda_nid_t pnid, hda_nid_t nid,
4366                                 const char *name, int dir)
4367 {
4368         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4369         int type = dir ? HDA_INPUT : HDA_OUTPUT;
4370         struct snd_kcontrol_new knew =
4371                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4372
4373         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4374                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4375         knew.tlv.c = 0;
4376         knew.tlv.p = 0;
4377         switch (pnid) {
4378         case VOICE_FOCUS:
4379                 knew.info = voice_focus_ctl_info;
4380                 knew.get = tuning_ctl_get;
4381                 knew.put = voice_focus_ctl_put;
4382                 knew.tlv.p = voice_focus_db_scale;
4383                 break;
4384         case MIC_SVM:
4385                 knew.info = mic_svm_ctl_info;
4386                 knew.get = tuning_ctl_get;
4387                 knew.put = mic_svm_ctl_put;
4388                 break;
4389         case EQUALIZER:
4390                 knew.info = equalizer_ctl_info;
4391                 knew.get = tuning_ctl_get;
4392                 knew.put = equalizer_ctl_put;
4393                 knew.tlv.p = eq_db_scale;
4394                 break;
4395         default:
4396                 return 0;
4397         }
4398         knew.private_value =
4399                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4400         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4401         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4402 }
4403
4404 static int add_tuning_ctls(struct hda_codec *codec)
4405 {
4406         int i;
4407         int err;
4408
4409         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4410                 err = add_tuning_control(codec,
4411                                         ca0132_tuning_ctls[i].parent_nid,
4412                                         ca0132_tuning_ctls[i].nid,
4413                                         ca0132_tuning_ctls[i].name,
4414                                         ca0132_tuning_ctls[i].direct);
4415                 if (err < 0)
4416                         return err;
4417         }
4418
4419         return 0;
4420 }
4421
4422 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4423 {
4424         struct ca0132_spec *spec = codec->spec;
4425         int i;
4426
4427         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4428         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4429         /* SVM level defaults to 0.74. */
4430         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4431
4432         /* EQ defaults to 0dB. */
4433         for (i = 2; i < TUNING_CTLS_COUNT; i++)
4434                 spec->cur_ctl_vals[i] = 24;
4435 }
4436 #endif /*ENABLE_TUNING_CONTROLS*/
4437
4438 /*
4439  * Select the active output.
4440  * If autodetect is enabled, output will be selected based on jack detection.
4441  * If jack inserted, headphone will be selected, else built-in speakers
4442  * If autodetect is disabled, output will be selected based on selection.
4443  */
4444 static int ca0132_select_out(struct hda_codec *codec)
4445 {
4446         struct ca0132_spec *spec = codec->spec;
4447         unsigned int pin_ctl;
4448         int jack_present;
4449         int auto_jack;
4450         unsigned int tmp;
4451         int err;
4452
4453         codec_dbg(codec, "ca0132_select_out\n");
4454
4455         snd_hda_power_up_pm(codec);
4456
4457         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4458
4459         if (auto_jack)
4460                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4461         else
4462                 jack_present =
4463                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4464
4465         if (jack_present)
4466                 spec->cur_out_type = HEADPHONE_OUT;
4467         else
4468                 spec->cur_out_type = SPEAKER_OUT;
4469
4470         if (spec->cur_out_type == SPEAKER_OUT) {
4471                 codec_dbg(codec, "ca0132_select_out speaker\n");
4472                 /*speaker out config*/
4473                 tmp = FLOAT_ONE;
4474                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4475                 if (err < 0)
4476                         goto exit;
4477                 /*enable speaker EQ*/
4478                 tmp = FLOAT_ONE;
4479                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4480                 if (err < 0)
4481                         goto exit;
4482
4483                 /* Setup EAPD */
4484                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4485                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4486                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4487                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4488                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4489                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4490                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4491                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4492
4493                 /* disable headphone node */
4494                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4495                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4496                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4497                                     pin_ctl & ~PIN_HP);
4498                 /* enable speaker node */
4499                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4500                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4501                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4502                                     pin_ctl | PIN_OUT);
4503         } else {
4504                 codec_dbg(codec, "ca0132_select_out hp\n");
4505                 /*headphone out config*/
4506                 tmp = FLOAT_ZERO;
4507                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4508                 if (err < 0)
4509                         goto exit;
4510                 /*disable speaker EQ*/
4511                 tmp = FLOAT_ZERO;
4512                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4513                 if (err < 0)
4514                         goto exit;
4515
4516                 /* Setup EAPD */
4517                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4518                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4519                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4520                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4521                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4522                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4523                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4524                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4525
4526                 /* disable speaker*/
4527                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4528                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4529                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4530                                     pin_ctl & ~PIN_HP);
4531                 /* enable headphone*/
4532                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4533                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4534                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4535                                     pin_ctl | PIN_HP);
4536         }
4537
4538 exit:
4539         snd_hda_power_down_pm(codec);
4540
4541         return err < 0 ? err : 0;
4542 }
4543
4544 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4545 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4546 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4547
4548 static void ae5_mmio_select_out(struct hda_codec *codec)
4549 {
4550         struct ca0132_spec *spec = codec->spec;
4551         const struct ae_ca0113_output_set *out_cmds;
4552         unsigned int i;
4553
4554         if (ca0132_quirk(spec) == QUIRK_AE5)
4555                 out_cmds = &ae5_ca0113_output_presets;
4556         else
4557                 out_cmds = &ae7_ca0113_output_presets;
4558
4559         for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4560                 ca0113_mmio_command_set(codec, out_cmds->group[i],
4561                                 out_cmds->target[i],
4562                                 out_cmds->vals[spec->cur_out_type][i]);
4563 }
4564
4565 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4566 {
4567         struct ca0132_spec *spec = codec->spec;
4568         int quirk = ca0132_quirk(spec);
4569         unsigned int tmp;
4570         int err;
4571
4572         /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4573         if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4574                         || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4575                 return 0;
4576
4577         /* Set front L/R full range. Zero for full-range, one for redirection. */
4578         tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4579         err = dspio_set_uint_param(codec, 0x96,
4580                         SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4581         if (err < 0)
4582                 return err;
4583
4584         /* When setting full-range rear, both rear and center/lfe are set. */
4585         tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4586         err = dspio_set_uint_param(codec, 0x96,
4587                         SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4588         if (err < 0)
4589                 return err;
4590
4591         err = dspio_set_uint_param(codec, 0x96,
4592                         SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4593         if (err < 0)
4594                 return err;
4595
4596         /*
4597          * Only the AE series cards set this value when setting full-range,
4598          * and it's always 1.0f.
4599          */
4600         if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4601                 err = dspio_set_uint_param(codec, 0x96,
4602                                 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4603                 if (err < 0)
4604                         return err;
4605         }
4606
4607         return 0;
4608 }
4609
4610 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4611                 bool val)
4612 {
4613         struct ca0132_spec *spec = codec->spec;
4614         unsigned int tmp;
4615         int err;
4616
4617         if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4618                         spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4619                 tmp = FLOAT_ONE;
4620         else
4621                 tmp = FLOAT_ZERO;
4622
4623         err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4624         if (err < 0)
4625                 return err;
4626
4627         /* If it is enabled, make sure to set the crossover frequency. */
4628         if (tmp) {
4629                 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4630                 err = dspio_set_uint_param(codec, 0x96,
4631                                 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4632                 if (err < 0)
4633                         return err;
4634         }
4635
4636         return 0;
4637 }
4638
4639 /*
4640  * These are the commands needed to setup output on each of the different card
4641  * types.
4642  */
4643 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4644                 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4645 {
4646         struct ca0132_spec *spec = codec->spec;
4647         int quirk = ca0132_quirk(spec);
4648         unsigned int i;
4649
4650         *quirk_data = NULL;
4651         for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4652                 if (quirk_out_set_data[i].quirk_id == quirk) {
4653                         *quirk_data = &quirk_out_set_data[i];
4654                         return;
4655                 }
4656         }
4657 }
4658
4659 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4660 {
4661         const struct ca0132_alt_out_set_quirk_data *quirk_data;
4662         const struct ca0132_alt_out_set_info *out_info;
4663         struct ca0132_spec *spec = codec->spec;
4664         unsigned int i, gpio_data;
4665         int err;
4666
4667         ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4668         if (!quirk_data)
4669                 return 0;
4670
4671         out_info = &quirk_data->out_set_info[spec->cur_out_type];
4672         if (quirk_data->is_ae_series)
4673                 ae5_mmio_select_out(codec);
4674
4675         if (out_info->has_hda_gpio) {
4676                 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4677                                 AC_VERB_GET_GPIO_DATA, 0);
4678
4679                 if (out_info->hda_gpio_set)
4680                         gpio_data |= (1 << out_info->hda_gpio_pin);
4681                 else
4682                         gpio_data &= ~(1 << out_info->hda_gpio_pin);
4683
4684                 snd_hda_codec_write(codec, codec->core.afg, 0,
4685                                     AC_VERB_SET_GPIO_DATA, gpio_data);
4686         }
4687
4688         if (out_info->mmio_gpio_count) {
4689                 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4690                         ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4691                                         out_info->mmio_gpio_set[i]);
4692                 }
4693         }
4694
4695         if (out_info->scp_cmds_count) {
4696                 for (i = 0; i < out_info->scp_cmds_count; i++) {
4697                         err = dspio_set_uint_param(codec,
4698                                         out_info->scp_cmd_mid[i],
4699                                         out_info->scp_cmd_req[i],
4700                                         out_info->scp_cmd_val[i]);
4701                         if (err < 0)
4702                                 return err;
4703                 }
4704         }
4705
4706         chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4707
4708         if (out_info->has_chipio_write) {
4709                 chipio_write(codec, out_info->chipio_write_addr,
4710                                 out_info->chipio_write_data);
4711         }
4712
4713         if (quirk_data->has_headphone_gain) {
4714                 if (spec->cur_out_type != HEADPHONE_OUT) {
4715                         if (quirk_data->is_ae_series)
4716                                 ae5_headphone_gain_set(codec, 2);
4717                         else
4718                                 zxr_headphone_gain_set(codec, 0);
4719                 } else {
4720                         if (quirk_data->is_ae_series)
4721                                 ae5_headphone_gain_set(codec,
4722                                                 spec->ae5_headphone_gain_val);
4723                         else
4724                                 zxr_headphone_gain_set(codec,
4725                                                 spec->zxr_gain_set);
4726                 }
4727         }
4728
4729         return 0;
4730 }
4731
4732 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4733                 bool out_enable, bool hp_enable)
4734 {
4735         unsigned int pin_ctl;
4736
4737         pin_ctl = snd_hda_codec_read(codec, nid, 0,
4738                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4739
4740         pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4741         pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4742         snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4743 }
4744
4745 /*
4746  * This function behaves similarly to the ca0132_select_out funciton above,
4747  * except with a few differences. It adds the ability to select the current
4748  * output with an enumerated control "output source" if the auto detect
4749  * mute switch is set to off. If the auto detect mute switch is enabled, it
4750  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4751  * It also adds the ability to auto-detect the front headphone port.
4752  */
4753 static int ca0132_alt_select_out(struct hda_codec *codec)
4754 {
4755         struct ca0132_spec *spec = codec->spec;
4756         unsigned int tmp, outfx_set;
4757         int jack_present;
4758         int auto_jack;
4759         int err;
4760         /* Default Headphone is rear headphone */
4761         hda_nid_t headphone_nid = spec->out_pins[1];
4762
4763         codec_dbg(codec, "%s\n", __func__);
4764
4765         snd_hda_power_up_pm(codec);
4766
4767         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4768
4769         /*
4770          * If headphone rear or front is plugged in, set to headphone.
4771          * If neither is plugged in, set to rear line out. Only if
4772          * hp/speaker auto detect is enabled.
4773          */
4774         if (auto_jack) {
4775                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4776                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4777
4778                 if (jack_present)
4779                         spec->cur_out_type = HEADPHONE_OUT;
4780                 else
4781                         spec->cur_out_type = SPEAKER_OUT;
4782         } else
4783                 spec->cur_out_type = spec->out_enum_val;
4784
4785         outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4786
4787         /* Begin DSP output switch, mute DSP volume. */
4788         err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4789         if (err < 0)
4790                 goto exit;
4791
4792         if (ca0132_alt_select_out_quirk_set(codec) < 0)
4793                 goto exit;
4794
4795         switch (spec->cur_out_type) {
4796         case SPEAKER_OUT:
4797                 codec_dbg(codec, "%s speaker\n", __func__);
4798
4799                 /* Enable EAPD */
4800                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4801                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4802
4803                 /* Disable headphone node. */
4804                 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4805                 /* Set front L-R to output. */
4806                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4807                 /* Set Center/LFE to output. */
4808                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4809                 /* Set rear surround to output. */
4810                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4811
4812                 /*
4813                  * Without PlayEnhancement being enabled, if we've got a 2.0
4814                  * setup, set it to floating point eight to disable any DSP
4815                  * processing effects.
4816                  */
4817                 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4818                         tmp = FLOAT_EIGHT;
4819                 else
4820                         tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4821
4822                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4823                 if (err < 0)
4824                         goto exit;
4825
4826                 break;
4827         case HEADPHONE_OUT:
4828                 codec_dbg(codec, "%s hp\n", __func__);
4829                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4830                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4831
4832                 /* Disable all speaker nodes. */
4833                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4834                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4835                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4836
4837                 /* enable headphone, either front or rear */
4838                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4839                         headphone_nid = spec->out_pins[2];
4840                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4841                         headphone_nid = spec->out_pins[1];
4842
4843                 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4844
4845                 if (outfx_set)
4846                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4847                 else
4848                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4849
4850                 if (err < 0)
4851                         goto exit;
4852                 break;
4853         }
4854         /*
4855          * If output effects are enabled, set the X-Bass effect value again to
4856          * make sure that it's properly enabled/disabled for speaker
4857          * configurations with an LFE channel.
4858          */
4859         if (outfx_set)
4860                 ca0132_effects_set(codec, X_BASS,
4861                         spec->effects_switch[X_BASS - EFFECT_START_NID]);
4862
4863         /* Set speaker EQ bypass attenuation to 0. */
4864         err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4865         if (err < 0)
4866                 goto exit;
4867
4868         /*
4869          * Although unused on all cards but the AE series, this is always set
4870          * to zero when setting the output.
4871          */
4872         err = dspio_set_uint_param(codec, 0x96,
4873                         SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4874         if (err < 0)
4875                 goto exit;
4876
4877         if (spec->cur_out_type == SPEAKER_OUT)
4878                 err = ca0132_alt_surround_set_bass_redirection(codec,
4879                                 spec->bass_redirection_val);
4880         else
4881                 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4882
4883         /* Unmute DSP now that we're done with output selection. */
4884         err = dspio_set_uint_param(codec, 0x96,
4885                         SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4886         if (err < 0)
4887                 goto exit;
4888
4889         if (spec->cur_out_type == SPEAKER_OUT) {
4890                 err = ca0132_alt_set_full_range_speaker(codec);
4891                 if (err < 0)
4892                         goto exit;
4893         }
4894
4895 exit:
4896         snd_hda_power_down_pm(codec);
4897
4898         return err < 0 ? err : 0;
4899 }
4900
4901 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4902 {
4903         struct ca0132_spec *spec = container_of(
4904                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4905         struct hda_jack_tbl *jack;
4906
4907         if (ca0132_use_alt_functions(spec))
4908                 ca0132_alt_select_out(spec->codec);
4909         else
4910                 ca0132_select_out(spec->codec);
4911
4912         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4913         if (jack) {
4914                 jack->block_report = 0;
4915                 snd_hda_jack_report_sync(spec->codec);
4916         }
4917 }
4918
4919 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4920 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4921 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4922 static int stop_mic1(struct hda_codec *codec);
4923 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4924 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4925
4926 /*
4927  * Select the active VIP source
4928  */
4929 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4930 {
4931         struct ca0132_spec *spec = codec->spec;
4932         unsigned int tmp;
4933
4934         if (spec->dsp_state != DSP_DOWNLOADED)
4935                 return 0;
4936
4937         /* if CrystalVoice if off, vipsource should be 0 */
4938         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4939             (val == 0)) {
4940                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4941                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4942                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4943                 if (spec->cur_mic_type == DIGITAL_MIC)
4944                         tmp = FLOAT_TWO;
4945                 else
4946                         tmp = FLOAT_ONE;
4947                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4948                 tmp = FLOAT_ZERO;
4949                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4950         } else {
4951                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4952                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4953                 if (spec->cur_mic_type == DIGITAL_MIC)
4954                         tmp = FLOAT_TWO;
4955                 else
4956                         tmp = FLOAT_ONE;
4957                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4958                 tmp = FLOAT_ONE;
4959                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4960                 msleep(20);
4961                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4962         }
4963
4964         return 1;
4965 }
4966
4967 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4968 {
4969         struct ca0132_spec *spec = codec->spec;
4970         unsigned int tmp;
4971
4972         if (spec->dsp_state != DSP_DOWNLOADED)
4973                 return 0;
4974
4975         codec_dbg(codec, "%s\n", __func__);
4976
4977         chipio_set_stream_control(codec, 0x03, 0);
4978         chipio_set_stream_control(codec, 0x04, 0);
4979
4980         /* if CrystalVoice is off, vipsource should be 0 */
4981         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4982             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4983                 codec_dbg(codec, "%s: off.", __func__);
4984                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4985
4986                 tmp = FLOAT_ZERO;
4987                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4988
4989                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4990                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4991                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4992                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4993
4994
4995                 if (spec->in_enum_val == REAR_LINE_IN)
4996                         tmp = FLOAT_ZERO;
4997                 else {
4998                         if (ca0132_quirk(spec) == QUIRK_SBZ)
4999                                 tmp = FLOAT_THREE;
5000                         else
5001                                 tmp = FLOAT_ONE;
5002                 }
5003
5004                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5005
5006         } else {
5007                 codec_dbg(codec, "%s: on.", __func__);
5008                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5009                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5010                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5011                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5012
5013                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5014                         tmp = FLOAT_TWO;
5015                 else
5016                         tmp = FLOAT_ONE;
5017                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5018
5019                 tmp = FLOAT_ONE;
5020                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5021
5022                 msleep(20);
5023                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5024         }
5025
5026         chipio_set_stream_control(codec, 0x03, 1);
5027         chipio_set_stream_control(codec, 0x04, 1);
5028
5029         return 1;
5030 }
5031
5032 /*
5033  * Select the active microphone.
5034  * If autodetect is enabled, mic will be selected based on jack detection.
5035  * If jack inserted, ext.mic will be selected, else built-in mic
5036  * If autodetect is disabled, mic will be selected based on selection.
5037  */
5038 static int ca0132_select_mic(struct hda_codec *codec)
5039 {
5040         struct ca0132_spec *spec = codec->spec;
5041         int jack_present;
5042         int auto_jack;
5043
5044         codec_dbg(codec, "ca0132_select_mic\n");
5045
5046         snd_hda_power_up_pm(codec);
5047
5048         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5049
5050         if (auto_jack)
5051                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5052         else
5053                 jack_present =
5054                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5055
5056         if (jack_present)
5057                 spec->cur_mic_type = LINE_MIC_IN;
5058         else
5059                 spec->cur_mic_type = DIGITAL_MIC;
5060
5061         if (spec->cur_mic_type == DIGITAL_MIC) {
5062                 /* enable digital Mic */
5063                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5064                 ca0132_set_dmic(codec, 1);
5065                 ca0132_mic_boost_set(codec, 0);
5066                 /* set voice focus */
5067                 ca0132_effects_set(codec, VOICE_FOCUS,
5068                                    spec->effects_switch
5069                                    [VOICE_FOCUS - EFFECT_START_NID]);
5070         } else {
5071                 /* disable digital Mic */
5072                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5073                 ca0132_set_dmic(codec, 0);
5074                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5075                 /* disable voice focus */
5076                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5077         }
5078
5079         snd_hda_power_down_pm(codec);
5080
5081         return 0;
5082 }
5083
5084 /*
5085  * Select the active input.
5086  * Mic detection isn't used, because it's kind of pointless on the SBZ.
5087  * The front mic has no jack-detection, so the only way to switch to it
5088  * is to do it manually in alsamixer.
5089  */
5090 static int ca0132_alt_select_in(struct hda_codec *codec)
5091 {
5092         struct ca0132_spec *spec = codec->spec;
5093         unsigned int tmp;
5094
5095         codec_dbg(codec, "%s\n", __func__);
5096
5097         snd_hda_power_up_pm(codec);
5098
5099         chipio_set_stream_control(codec, 0x03, 0);
5100         chipio_set_stream_control(codec, 0x04, 0);
5101
5102         spec->cur_mic_type = spec->in_enum_val;
5103
5104         switch (spec->cur_mic_type) {
5105         case REAR_MIC:
5106                 switch (ca0132_quirk(spec)) {
5107                 case QUIRK_SBZ:
5108                 case QUIRK_R3D:
5109                         ca0113_mmio_gpio_set(codec, 0, false);
5110                         tmp = FLOAT_THREE;
5111                         break;
5112                 case QUIRK_ZXR:
5113                         tmp = FLOAT_THREE;
5114                         break;
5115                 case QUIRK_R3DI:
5116                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5117                         tmp = FLOAT_ONE;
5118                         break;
5119                 case QUIRK_AE5:
5120                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5121                         tmp = FLOAT_THREE;
5122                         break;
5123                 case QUIRK_AE7:
5124                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5125                         tmp = FLOAT_THREE;
5126                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5127                                         SR_96_000);
5128                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5129                                         SR_96_000);
5130                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5131                         break;
5132                 default:
5133                         tmp = FLOAT_ONE;
5134                         break;
5135                 }
5136
5137                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5138                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5139                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5140                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5141
5142                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5143
5144                 chipio_set_stream_control(codec, 0x03, 1);
5145                 chipio_set_stream_control(codec, 0x04, 1);
5146                 switch (ca0132_quirk(spec)) {
5147                 case QUIRK_SBZ:
5148                         chipio_write(codec, 0x18B098, 0x0000000C);
5149                         chipio_write(codec, 0x18B09C, 0x0000000C);
5150                         break;
5151                 case QUIRK_ZXR:
5152                         chipio_write(codec, 0x18B098, 0x0000000C);
5153                         chipio_write(codec, 0x18B09C, 0x000000CC);
5154                         break;
5155                 case QUIRK_AE5:
5156                         chipio_write(codec, 0x18B098, 0x0000000C);
5157                         chipio_write(codec, 0x18B09C, 0x0000004C);
5158                         break;
5159                 default:
5160                         break;
5161                 }
5162                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5163                 break;
5164         case REAR_LINE_IN:
5165                 ca0132_mic_boost_set(codec, 0);
5166                 switch (ca0132_quirk(spec)) {
5167                 case QUIRK_SBZ:
5168                 case QUIRK_R3D:
5169                         ca0113_mmio_gpio_set(codec, 0, false);
5170                         break;
5171                 case QUIRK_R3DI:
5172                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5173                         break;
5174                 case QUIRK_AE5:
5175                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5176                         break;
5177                 case QUIRK_AE7:
5178                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5179                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5180                                         SR_96_000);
5181                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5182                                         SR_96_000);
5183                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5184                         break;
5185                 default:
5186                         break;
5187                 }
5188
5189                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5190                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5191                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5192                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5193
5194                 if (ca0132_quirk(spec) == QUIRK_AE7)
5195                         tmp = FLOAT_THREE;
5196                 else
5197                         tmp = FLOAT_ZERO;
5198                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5199
5200                 switch (ca0132_quirk(spec)) {
5201                 case QUIRK_SBZ:
5202                 case QUIRK_AE5:
5203                         chipio_write(codec, 0x18B098, 0x00000000);
5204                         chipio_write(codec, 0x18B09C, 0x00000000);
5205                         break;
5206                 default:
5207                         break;
5208                 }
5209                 chipio_set_stream_control(codec, 0x03, 1);
5210                 chipio_set_stream_control(codec, 0x04, 1);
5211                 break;
5212         case FRONT_MIC:
5213                 switch (ca0132_quirk(spec)) {
5214                 case QUIRK_SBZ:
5215                 case QUIRK_R3D:
5216                         ca0113_mmio_gpio_set(codec, 0, true);
5217                         ca0113_mmio_gpio_set(codec, 5, false);
5218                         tmp = FLOAT_THREE;
5219                         break;
5220                 case QUIRK_R3DI:
5221                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5222                         tmp = FLOAT_ONE;
5223                         break;
5224                 case QUIRK_AE5:
5225                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5226                         tmp = FLOAT_THREE;
5227                         break;
5228                 default:
5229                         tmp = FLOAT_ONE;
5230                         break;
5231                 }
5232
5233                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5234                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5235                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5236                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5237
5238                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5239
5240                 chipio_set_stream_control(codec, 0x03, 1);
5241                 chipio_set_stream_control(codec, 0x04, 1);
5242
5243                 switch (ca0132_quirk(spec)) {
5244                 case QUIRK_SBZ:
5245                         chipio_write(codec, 0x18B098, 0x0000000C);
5246                         chipio_write(codec, 0x18B09C, 0x000000CC);
5247                         break;
5248                 case QUIRK_AE5:
5249                         chipio_write(codec, 0x18B098, 0x0000000C);
5250                         chipio_write(codec, 0x18B09C, 0x0000004C);
5251                         break;
5252                 default:
5253                         break;
5254                 }
5255                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5256                 break;
5257         }
5258         ca0132_cvoice_switch_set(codec);
5259
5260         snd_hda_power_down_pm(codec);
5261         return 0;
5262 }
5263
5264 /*
5265  * Check if VNODE settings take effect immediately.
5266  */
5267 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5268                                      hda_nid_t vnid,
5269                                      hda_nid_t *shared_nid)
5270 {
5271         struct ca0132_spec *spec = codec->spec;
5272         hda_nid_t nid;
5273
5274         switch (vnid) {
5275         case VNID_SPK:
5276                 nid = spec->shared_out_nid;
5277                 break;
5278         case VNID_MIC:
5279                 nid = spec->shared_mic_nid;
5280                 break;
5281         default:
5282                 return false;
5283         }
5284
5285         if (shared_nid)
5286                 *shared_nid = nid;
5287
5288         return true;
5289 }
5290
5291 /*
5292 * The following functions are control change helpers.
5293 * They return 0 if no changed.  Return 1 if changed.
5294 */
5295 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5296 {
5297         struct ca0132_spec *spec = codec->spec;
5298         unsigned int tmp;
5299
5300         /* based on CrystalVoice state to enable VoiceFX. */
5301         if (enable) {
5302                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5303                         FLOAT_ONE : FLOAT_ZERO;
5304         } else {
5305                 tmp = FLOAT_ZERO;
5306         }
5307
5308         dspio_set_uint_param(codec, ca0132_voicefx.mid,
5309                              ca0132_voicefx.reqs[0], tmp);
5310
5311         return 1;
5312 }
5313
5314 /*
5315  * Set the effects parameters
5316  */
5317 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5318 {
5319         struct ca0132_spec *spec = codec->spec;
5320         unsigned int on, tmp, channel_cfg;
5321         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5322         int err = 0;
5323         int idx = nid - EFFECT_START_NID;
5324
5325         if ((idx < 0) || (idx >= num_fx))
5326                 return 0; /* no changed */
5327
5328         /* for out effect, qualify with PE */
5329         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5330                 /* if PE if off, turn off out effects. */
5331                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5332                         val = 0;
5333                 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5334                         channel_cfg = spec->channel_cfg_val;
5335                         if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5336                                         channel_cfg != SPEAKER_CHANNELS_4_0)
5337                                 val = 0;
5338                 }
5339         }
5340
5341         /* for in effect, qualify with CrystalVoice */
5342         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5343                 /* if CrystalVoice if off, turn off in effects. */
5344                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5345                         val = 0;
5346
5347                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5348                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5349                         val = 0;
5350
5351                 /* If Voice Focus on SBZ, set to two channel. */
5352                 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5353                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5354                         if (spec->effects_switch[CRYSTAL_VOICE -
5355                                                  EFFECT_START_NID]) {
5356
5357                                 if (spec->effects_switch[VOICE_FOCUS -
5358                                                          EFFECT_START_NID]) {
5359                                         tmp = FLOAT_TWO;
5360                                         val = 1;
5361                                 } else
5362                                         tmp = FLOAT_ONE;
5363
5364                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5365                         }
5366                 }
5367                 /*
5368                  * For SBZ noise reduction, there's an extra command
5369                  * to module ID 0x47. No clue why.
5370                  */
5371                 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5372                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5373                         if (spec->effects_switch[CRYSTAL_VOICE -
5374                                                  EFFECT_START_NID]) {
5375                                 if (spec->effects_switch[NOISE_REDUCTION -
5376                                                          EFFECT_START_NID])
5377                                         tmp = FLOAT_ONE;
5378                                 else
5379                                         tmp = FLOAT_ZERO;
5380                         } else
5381                                 tmp = FLOAT_ZERO;
5382
5383                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5384                 }
5385
5386                 /* If rear line in disable effects. */
5387                 if (ca0132_use_alt_functions(spec) &&
5388                                 spec->in_enum_val == REAR_LINE_IN)
5389                         val = 0;
5390         }
5391
5392         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5393                     nid, val);
5394
5395         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5396         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5397                                    ca0132_effects[idx].reqs[0], on);
5398
5399         if (err < 0)
5400                 return 0; /* no changed */
5401
5402         return 1;
5403 }
5404
5405 /*
5406  * Turn on/off Playback Enhancements
5407  */
5408 static int ca0132_pe_switch_set(struct hda_codec *codec)
5409 {
5410         struct ca0132_spec *spec = codec->spec;
5411         hda_nid_t nid;
5412         int i, ret = 0;
5413
5414         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5415                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5416
5417         if (ca0132_use_alt_functions(spec))
5418                 ca0132_alt_select_out(codec);
5419
5420         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5421         nid = OUT_EFFECT_START_NID;
5422         /* PE affects all out effects */
5423         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5424                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5425
5426         return ret;
5427 }
5428
5429 /* Check if Mic1 is streaming, if so, stop streaming */
5430 static int stop_mic1(struct hda_codec *codec)
5431 {
5432         struct ca0132_spec *spec = codec->spec;
5433         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5434                                                  AC_VERB_GET_CONV, 0);
5435         if (oldval != 0)
5436                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5437                                     AC_VERB_SET_CHANNEL_STREAMID,
5438                                     0);
5439         return oldval;
5440 }
5441
5442 /* Resume Mic1 streaming if it was stopped. */
5443 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5444 {
5445         struct ca0132_spec *spec = codec->spec;
5446         /* Restore the previous stream and channel */
5447         if (oldval != 0)
5448                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5449                                     AC_VERB_SET_CHANNEL_STREAMID,
5450                                     oldval);
5451 }
5452
5453 /*
5454  * Turn on/off CrystalVoice
5455  */
5456 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5457 {
5458         struct ca0132_spec *spec = codec->spec;
5459         hda_nid_t nid;
5460         int i, ret = 0;
5461         unsigned int oldval;
5462
5463         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5464                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5465
5466         i = IN_EFFECT_START_NID - EFFECT_START_NID;
5467         nid = IN_EFFECT_START_NID;
5468         /* CrystalVoice affects all in effects */
5469         for (; nid < IN_EFFECT_END_NID; nid++, i++)
5470                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5471
5472         /* including VoiceFX */
5473         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5474
5475         /* set correct vipsource */
5476         oldval = stop_mic1(codec);
5477         if (ca0132_use_alt_functions(spec))
5478                 ret |= ca0132_alt_set_vipsource(codec, 1);
5479         else
5480                 ret |= ca0132_set_vipsource(codec, 1);
5481         resume_mic1(codec, oldval);
5482         return ret;
5483 }
5484
5485 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5486 {
5487         struct ca0132_spec *spec = codec->spec;
5488         int ret = 0;
5489
5490         if (val) /* on */
5491                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5492                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5493         else /* off */
5494                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5495                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5496
5497         return ret;
5498 }
5499
5500 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5501 {
5502         struct ca0132_spec *spec = codec->spec;
5503         int ret = 0;
5504
5505         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5506                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5507         return ret;
5508 }
5509
5510 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5511 {
5512         unsigned int i;
5513
5514         for (i = 0; i < 4; i++)
5515                 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5516                                 ae5_headphone_gain_presets[val].vals[i]);
5517         return 0;
5518 }
5519
5520 /*
5521  * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5522  * amplifier to handle a 600 ohm load.
5523  */
5524 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5525 {
5526         ca0113_mmio_gpio_set(codec, 1, val);
5527
5528         return 0;
5529 }
5530
5531 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5532                                 struct snd_ctl_elem_value *ucontrol)
5533 {
5534         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5535         hda_nid_t nid = get_amp_nid(kcontrol);
5536         hda_nid_t shared_nid = 0;
5537         bool effective;
5538         int ret = 0;
5539         struct ca0132_spec *spec = codec->spec;
5540         int auto_jack;
5541
5542         if (nid == VNID_HP_SEL) {
5543                 auto_jack =
5544                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5545                 if (!auto_jack) {
5546                         if (ca0132_use_alt_functions(spec))
5547                                 ca0132_alt_select_out(codec);
5548                         else
5549                                 ca0132_select_out(codec);
5550                 }
5551                 return 1;
5552         }
5553
5554         if (nid == VNID_AMIC1_SEL) {
5555                 auto_jack =
5556                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5557                 if (!auto_jack)
5558                         ca0132_select_mic(codec);
5559                 return 1;
5560         }
5561
5562         if (nid == VNID_HP_ASEL) {
5563                 if (ca0132_use_alt_functions(spec))
5564                         ca0132_alt_select_out(codec);
5565                 else
5566                         ca0132_select_out(codec);
5567                 return 1;
5568         }
5569
5570         if (nid == VNID_AMIC1_ASEL) {
5571                 ca0132_select_mic(codec);
5572                 return 1;
5573         }
5574
5575         /* if effective conditions, then update hw immediately. */
5576         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5577         if (effective) {
5578                 int dir = get_amp_direction(kcontrol);
5579                 int ch = get_amp_channels(kcontrol);
5580                 unsigned long pval;
5581
5582                 mutex_lock(&codec->control_mutex);
5583                 pval = kcontrol->private_value;
5584                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5585                                                                 0, dir);
5586                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5587                 kcontrol->private_value = pval;
5588                 mutex_unlock(&codec->control_mutex);
5589         }
5590
5591         return ret;
5592 }
5593 /* End of control change helpers. */
5594
5595 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5596                 long idx)
5597 {
5598         snd_hda_power_up(codec);
5599
5600         dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5601                         &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5602
5603         snd_hda_power_down(codec);
5604 }
5605
5606 /*
5607  * Below I've added controls to mess with the effect levels, I've only enabled
5608  * them on the Sound Blaster Z, but they would probably also work on the
5609  * Chromebook. I figured they were probably tuned specifically for it, and left
5610  * out for a reason.
5611  */
5612
5613 /* Sets DSP effect level from the sliders above the controls */
5614
5615 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5616                           const unsigned int *lookup, int idx)
5617 {
5618         int i = 0;
5619         unsigned int y;
5620         /*
5621          * For X_BASS, req 2 is actually crossover freq instead of
5622          * effect level
5623          */
5624         if (nid == X_BASS)
5625                 y = 2;
5626         else
5627                 y = 1;
5628
5629         snd_hda_power_up(codec);
5630         if (nid == XBASS_XOVER) {
5631                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5632                         if (ca0132_effects[i].nid == X_BASS)
5633                                 break;
5634
5635                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5636                                 ca0132_effects[i].reqs[1],
5637                                 &(lookup[idx - 1]), sizeof(unsigned int));
5638         } else {
5639                 /* Find the actual effect structure */
5640                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5641                         if (nid == ca0132_effects[i].nid)
5642                                 break;
5643
5644                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5645                                 ca0132_effects[i].reqs[y],
5646                                 &(lookup[idx]), sizeof(unsigned int));
5647         }
5648
5649         snd_hda_power_down(codec);
5650
5651         return 0;
5652 }
5653
5654 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5655                           struct snd_ctl_elem_value *ucontrol)
5656 {
5657         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5658         struct ca0132_spec *spec = codec->spec;
5659         long *valp = ucontrol->value.integer.value;
5660         hda_nid_t nid = get_amp_nid(kcontrol);
5661
5662         if (nid == BASS_REDIRECTION_XOVER)
5663                 *valp = spec->bass_redirect_xover_freq;
5664         else
5665                 *valp = spec->xbass_xover_freq;
5666
5667         return 0;
5668 }
5669
5670 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5671                           struct snd_ctl_elem_value *ucontrol)
5672 {
5673         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5674         struct ca0132_spec *spec = codec->spec;
5675         hda_nid_t nid = get_amp_nid(kcontrol);
5676         long *valp = ucontrol->value.integer.value;
5677         int idx = nid - OUT_EFFECT_START_NID;
5678
5679         *valp = spec->fx_ctl_val[idx];
5680         return 0;
5681 }
5682
5683 /*
5684  * The X-bass crossover starts at 10hz, so the min is 1. The
5685  * frequency is set in multiples of 10.
5686  */
5687 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5688                 struct snd_ctl_elem_info *uinfo)
5689 {
5690         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5691         uinfo->count = 1;
5692         uinfo->value.integer.min = 1;
5693         uinfo->value.integer.max = 100;
5694         uinfo->value.integer.step = 1;
5695
5696         return 0;
5697 }
5698
5699 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5700                 struct snd_ctl_elem_info *uinfo)
5701 {
5702         int chs = get_amp_channels(kcontrol);
5703
5704         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5705         uinfo->count = chs == 3 ? 2 : 1;
5706         uinfo->value.integer.min = 0;
5707         uinfo->value.integer.max = 100;
5708         uinfo->value.integer.step = 1;
5709
5710         return 0;
5711 }
5712
5713 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5714                                 struct snd_ctl_elem_value *ucontrol)
5715 {
5716         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5717         struct ca0132_spec *spec = codec->spec;
5718         hda_nid_t nid = get_amp_nid(kcontrol);
5719         long *valp = ucontrol->value.integer.value;
5720         long *cur_val;
5721         int idx;
5722
5723         if (nid == BASS_REDIRECTION_XOVER)
5724                 cur_val = &spec->bass_redirect_xover_freq;
5725         else
5726                 cur_val = &spec->xbass_xover_freq;
5727
5728         /* any change? */
5729         if (*cur_val == *valp)
5730                 return 0;
5731
5732         *cur_val = *valp;
5733
5734         idx = *valp;
5735         if (nid == BASS_REDIRECTION_XOVER)
5736                 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5737         else
5738                 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5739
5740         return 0;
5741 }
5742
5743 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5744                                 struct snd_ctl_elem_value *ucontrol)
5745 {
5746         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5747         struct ca0132_spec *spec = codec->spec;
5748         hda_nid_t nid = get_amp_nid(kcontrol);
5749         long *valp = ucontrol->value.integer.value;
5750         int idx;
5751
5752         idx = nid - EFFECT_START_NID;
5753         /* any change? */
5754         if (spec->fx_ctl_val[idx] == *valp)
5755                 return 0;
5756
5757         spec->fx_ctl_val[idx] = *valp;
5758
5759         idx = *valp;
5760         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5761
5762         return 0;
5763 }
5764
5765
5766 /*
5767  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5768  * only has off or full 30 dB, and didn't like making a volume slider that has
5769  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5770  */
5771 #define MIC_BOOST_NUM_OF_STEPS 4
5772 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5773
5774 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5775                                  struct snd_ctl_elem_info *uinfo)
5776 {
5777         char *sfx = "dB";
5778         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5779
5780         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5781         uinfo->count = 1;
5782         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5783         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5784                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5785         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5786         strcpy(uinfo->value.enumerated.name, namestr);
5787         return 0;
5788 }
5789
5790 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5791                                 struct snd_ctl_elem_value *ucontrol)
5792 {
5793         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5794         struct ca0132_spec *spec = codec->spec;
5795
5796         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5797         return 0;
5798 }
5799
5800 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5801                                 struct snd_ctl_elem_value *ucontrol)
5802 {
5803         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5804         struct ca0132_spec *spec = codec->spec;
5805         int sel = ucontrol->value.enumerated.item[0];
5806         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5807
5808         if (sel >= items)
5809                 return 0;
5810
5811         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5812                     sel);
5813
5814         spec->mic_boost_enum_val = sel;
5815
5816         if (spec->in_enum_val != REAR_LINE_IN)
5817                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5818
5819         return 1;
5820 }
5821
5822 /*
5823  * Sound BlasterX AE-5 Headphone Gain Controls.
5824  */
5825 #define AE5_HEADPHONE_GAIN_MAX 3
5826 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5827                                  struct snd_ctl_elem_info *uinfo)
5828 {
5829         char *sfx = " Ohms)";
5830         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5831
5832         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5833         uinfo->count = 1;
5834         uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5835         if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5836                 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5837         sprintf(namestr, "%s %s",
5838                 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5839                 sfx);
5840         strcpy(uinfo->value.enumerated.name, namestr);
5841         return 0;
5842 }
5843
5844 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5845                                 struct snd_ctl_elem_value *ucontrol)
5846 {
5847         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5848         struct ca0132_spec *spec = codec->spec;
5849
5850         ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5851         return 0;
5852 }
5853
5854 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5855                                 struct snd_ctl_elem_value *ucontrol)
5856 {
5857         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5858         struct ca0132_spec *spec = codec->spec;
5859         int sel = ucontrol->value.enumerated.item[0];
5860         unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5861
5862         if (sel >= items)
5863                 return 0;
5864
5865         codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5866                     sel);
5867
5868         spec->ae5_headphone_gain_val = sel;
5869
5870         if (spec->out_enum_val == HEADPHONE_OUT)
5871                 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5872
5873         return 1;
5874 }
5875
5876 /*
5877  * Sound BlasterX AE-5 sound filter enumerated control.
5878  */
5879 #define AE5_SOUND_FILTER_MAX 3
5880
5881 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5882                                  struct snd_ctl_elem_info *uinfo)
5883 {
5884         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5885
5886         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5887         uinfo->count = 1;
5888         uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5889         if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5890                 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5891         sprintf(namestr, "%s",
5892                         ae5_filter_presets[uinfo->value.enumerated.item].name);
5893         strcpy(uinfo->value.enumerated.name, namestr);
5894         return 0;
5895 }
5896
5897 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5898                                 struct snd_ctl_elem_value *ucontrol)
5899 {
5900         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5901         struct ca0132_spec *spec = codec->spec;
5902
5903         ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5904         return 0;
5905 }
5906
5907 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5908                                 struct snd_ctl_elem_value *ucontrol)
5909 {
5910         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5911         struct ca0132_spec *spec = codec->spec;
5912         int sel = ucontrol->value.enumerated.item[0];
5913         unsigned int items = AE5_SOUND_FILTER_MAX;
5914
5915         if (sel >= items)
5916                 return 0;
5917
5918         codec_dbg(codec, "ae5_sound_filter: %s\n",
5919                         ae5_filter_presets[sel].name);
5920
5921         spec->ae5_filter_val = sel;
5922
5923         ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5924                         ae5_filter_presets[sel].val);
5925
5926         return 1;
5927 }
5928
5929 /*
5930  * Input Select Control for alternative ca0132 codecs. This exists because
5931  * front microphone has no auto-detect, and we need a way to set the rear
5932  * as line-in
5933  */
5934 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5935                                  struct snd_ctl_elem_info *uinfo)
5936 {
5937         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5938         uinfo->count = 1;
5939         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5940         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5941                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5942         strcpy(uinfo->value.enumerated.name,
5943                         in_src_str[uinfo->value.enumerated.item]);
5944         return 0;
5945 }
5946
5947 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5948                                 struct snd_ctl_elem_value *ucontrol)
5949 {
5950         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5951         struct ca0132_spec *spec = codec->spec;
5952
5953         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5954         return 0;
5955 }
5956
5957 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5958                                 struct snd_ctl_elem_value *ucontrol)
5959 {
5960         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5961         struct ca0132_spec *spec = codec->spec;
5962         int sel = ucontrol->value.enumerated.item[0];
5963         unsigned int items = IN_SRC_NUM_OF_INPUTS;
5964
5965         /*
5966          * The AE-7 has no front microphone, so limit items to 2: rear mic and
5967          * line-in.
5968          */
5969         if (ca0132_quirk(spec) == QUIRK_AE7)
5970                 items = 2;
5971
5972         if (sel >= items)
5973                 return 0;
5974
5975         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5976                     sel, in_src_str[sel]);
5977
5978         spec->in_enum_val = sel;
5979
5980         ca0132_alt_select_in(codec);
5981
5982         return 1;
5983 }
5984
5985 /* Sound Blaster Z Output Select Control */
5986 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5987                                  struct snd_ctl_elem_info *uinfo)
5988 {
5989         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5990         uinfo->count = 1;
5991         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5992         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5993                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5994         strcpy(uinfo->value.enumerated.name,
5995                         out_type_str[uinfo->value.enumerated.item]);
5996         return 0;
5997 }
5998
5999 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
6000                                 struct snd_ctl_elem_value *ucontrol)
6001 {
6002         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6003         struct ca0132_spec *spec = codec->spec;
6004
6005         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6006         return 0;
6007 }
6008
6009 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6010                                 struct snd_ctl_elem_value *ucontrol)
6011 {
6012         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6013         struct ca0132_spec *spec = codec->spec;
6014         int sel = ucontrol->value.enumerated.item[0];
6015         unsigned int items = NUM_OF_OUTPUTS;
6016         unsigned int auto_jack;
6017
6018         if (sel >= items)
6019                 return 0;
6020
6021         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6022                     sel, out_type_str[sel]);
6023
6024         spec->out_enum_val = sel;
6025
6026         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6027
6028         if (!auto_jack)
6029                 ca0132_alt_select_out(codec);
6030
6031         return 1;
6032 }
6033
6034 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
6035 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6036                                  struct snd_ctl_elem_info *uinfo)
6037 {
6038         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6039
6040         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6041         uinfo->count = 1;
6042         uinfo->value.enumerated.items = items;
6043         if (uinfo->value.enumerated.item >= items)
6044                 uinfo->value.enumerated.item = items - 1;
6045         strcpy(uinfo->value.enumerated.name,
6046                         speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6047         return 0;
6048 }
6049
6050 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6051                                 struct snd_ctl_elem_value *ucontrol)
6052 {
6053         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6054         struct ca0132_spec *spec = codec->spec;
6055
6056         ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6057         return 0;
6058 }
6059
6060 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6061                                 struct snd_ctl_elem_value *ucontrol)
6062 {
6063         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6064         struct ca0132_spec *spec = codec->spec;
6065         int sel = ucontrol->value.enumerated.item[0];
6066         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6067
6068         if (sel >= items)
6069                 return 0;
6070
6071         codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6072                     sel, speaker_channel_cfgs[sel].name);
6073
6074         spec->channel_cfg_val = sel;
6075
6076         if (spec->out_enum_val == SPEAKER_OUT)
6077                 ca0132_alt_select_out(codec);
6078
6079         return 1;
6080 }
6081
6082 /*
6083  * Smart Volume output setting control. Three different settings, Normal,
6084  * which takes the value from the smart volume slider. The two others, loud
6085  * and night, disregard the slider value and have uneditable values.
6086  */
6087 #define NUM_OF_SVM_SETTINGS 3
6088 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6089
6090 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6091                                  struct snd_ctl_elem_info *uinfo)
6092 {
6093         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6094         uinfo->count = 1;
6095         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6096         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6097                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6098         strcpy(uinfo->value.enumerated.name,
6099                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
6100         return 0;
6101 }
6102
6103 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6104                                 struct snd_ctl_elem_value *ucontrol)
6105 {
6106         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6107         struct ca0132_spec *spec = codec->spec;
6108
6109         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6110         return 0;
6111 }
6112
6113 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6114                                 struct snd_ctl_elem_value *ucontrol)
6115 {
6116         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6117         struct ca0132_spec *spec = codec->spec;
6118         int sel = ucontrol->value.enumerated.item[0];
6119         unsigned int items = NUM_OF_SVM_SETTINGS;
6120         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6121         unsigned int tmp;
6122
6123         if (sel >= items)
6124                 return 0;
6125
6126         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6127                     sel, out_svm_set_enum_str[sel]);
6128
6129         spec->smart_volume_setting = sel;
6130
6131         switch (sel) {
6132         case 0:
6133                 tmp = FLOAT_ZERO;
6134                 break;
6135         case 1:
6136                 tmp = FLOAT_ONE;
6137                 break;
6138         case 2:
6139                 tmp = FLOAT_TWO;
6140                 break;
6141         default:
6142                 tmp = FLOAT_ZERO;
6143                 break;
6144         }
6145         /* Req 2 is the Smart Volume Setting req. */
6146         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6147                         ca0132_effects[idx].reqs[2], tmp);
6148         return 1;
6149 }
6150
6151 /* Sound Blaster Z EQ preset controls */
6152 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6153                                  struct snd_ctl_elem_info *uinfo)
6154 {
6155         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6156
6157         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6158         uinfo->count = 1;
6159         uinfo->value.enumerated.items = items;
6160         if (uinfo->value.enumerated.item >= items)
6161                 uinfo->value.enumerated.item = items - 1;
6162         strcpy(uinfo->value.enumerated.name,
6163                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6164         return 0;
6165 }
6166
6167 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6168                                 struct snd_ctl_elem_value *ucontrol)
6169 {
6170         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6171         struct ca0132_spec *spec = codec->spec;
6172
6173         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6174         return 0;
6175 }
6176
6177 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6178                                 struct snd_ctl_elem_value *ucontrol)
6179 {
6180         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6181         struct ca0132_spec *spec = codec->spec;
6182         int i, err = 0;
6183         int sel = ucontrol->value.enumerated.item[0];
6184         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6185
6186         if (sel >= items)
6187                 return 0;
6188
6189         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6190                         ca0132_alt_eq_presets[sel].name);
6191         /*
6192          * Idx 0 is default.
6193          * Default needs to qualify with CrystalVoice state.
6194          */
6195         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6196                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6197                                 ca0132_alt_eq_enum.reqs[i],
6198                                 ca0132_alt_eq_presets[sel].vals[i]);
6199                 if (err < 0)
6200                         break;
6201         }
6202
6203         if (err >= 0)
6204                 spec->eq_preset_val = sel;
6205
6206         return 1;
6207 }
6208
6209 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6210                                  struct snd_ctl_elem_info *uinfo)
6211 {
6212         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6213
6214         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6215         uinfo->count = 1;
6216         uinfo->value.enumerated.items = items;
6217         if (uinfo->value.enumerated.item >= items)
6218                 uinfo->value.enumerated.item = items - 1;
6219         strcpy(uinfo->value.enumerated.name,
6220                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6221         return 0;
6222 }
6223
6224 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6225                                 struct snd_ctl_elem_value *ucontrol)
6226 {
6227         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6228         struct ca0132_spec *spec = codec->spec;
6229
6230         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6231         return 0;
6232 }
6233
6234 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6235                                 struct snd_ctl_elem_value *ucontrol)
6236 {
6237         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6238         struct ca0132_spec *spec = codec->spec;
6239         int i, err = 0;
6240         int sel = ucontrol->value.enumerated.item[0];
6241
6242         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6243                 return 0;
6244
6245         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6246                     sel, ca0132_voicefx_presets[sel].name);
6247
6248         /*
6249          * Idx 0 is default.
6250          * Default needs to qualify with CrystalVoice state.
6251          */
6252         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6253                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6254                                 ca0132_voicefx.reqs[i],
6255                                 ca0132_voicefx_presets[sel].vals[i]);
6256                 if (err < 0)
6257                         break;
6258         }
6259
6260         if (err >= 0) {
6261                 spec->voicefx_val = sel;
6262                 /* enable voice fx */
6263                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6264         }
6265
6266         return 1;
6267 }
6268
6269 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6270                                 struct snd_ctl_elem_value *ucontrol)
6271 {
6272         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6273         struct ca0132_spec *spec = codec->spec;
6274         hda_nid_t nid = get_amp_nid(kcontrol);
6275         int ch = get_amp_channels(kcontrol);
6276         long *valp = ucontrol->value.integer.value;
6277
6278         /* vnode */
6279         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6280                 if (ch & 1) {
6281                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6282                         valp++;
6283                 }
6284                 if (ch & 2) {
6285                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6286                         valp++;
6287                 }
6288                 return 0;
6289         }
6290
6291         /* effects, include PE and CrystalVoice */
6292         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6293                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6294                 return 0;
6295         }
6296
6297         /* mic boost */
6298         if (nid == spec->input_pins[0]) {
6299                 *valp = spec->cur_mic_boost;
6300                 return 0;
6301         }
6302
6303         if (nid == ZXR_HEADPHONE_GAIN) {
6304                 *valp = spec->zxr_gain_set;
6305                 return 0;
6306         }
6307
6308         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6309                 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6310                 return 0;
6311         }
6312
6313         if (nid == BASS_REDIRECTION) {
6314                 *valp = spec->bass_redirection_val;
6315                 return 0;
6316         }
6317
6318         return 0;
6319 }
6320
6321 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6322                              struct snd_ctl_elem_value *ucontrol)
6323 {
6324         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6325         struct ca0132_spec *spec = codec->spec;
6326         hda_nid_t nid = get_amp_nid(kcontrol);
6327         int ch = get_amp_channels(kcontrol);
6328         long *valp = ucontrol->value.integer.value;
6329         int changed = 1;
6330
6331         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6332                     nid, *valp);
6333
6334         snd_hda_power_up(codec);
6335         /* vnode */
6336         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6337                 if (ch & 1) {
6338                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6339                         valp++;
6340                 }
6341                 if (ch & 2) {
6342                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6343                         valp++;
6344                 }
6345                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6346                 goto exit;
6347         }
6348
6349         /* PE */
6350         if (nid == PLAY_ENHANCEMENT) {
6351                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6352                 changed = ca0132_pe_switch_set(codec);
6353                 goto exit;
6354         }
6355
6356         /* CrystalVoice */
6357         if (nid == CRYSTAL_VOICE) {
6358                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6359                 changed = ca0132_cvoice_switch_set(codec);
6360                 goto exit;
6361         }
6362
6363         /* out and in effects */
6364         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6365             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6366                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6367                 changed = ca0132_effects_set(codec, nid, *valp);
6368                 goto exit;
6369         }
6370
6371         /* mic boost */
6372         if (nid == spec->input_pins[0]) {
6373                 spec->cur_mic_boost = *valp;
6374                 if (ca0132_use_alt_functions(spec)) {
6375                         if (spec->in_enum_val != REAR_LINE_IN)
6376                                 changed = ca0132_mic_boost_set(codec, *valp);
6377                 } else {
6378                         /* Mic boost does not apply to Digital Mic */
6379                         if (spec->cur_mic_type != DIGITAL_MIC)
6380                                 changed = ca0132_mic_boost_set(codec, *valp);
6381                 }
6382
6383                 goto exit;
6384         }
6385
6386         if (nid == ZXR_HEADPHONE_GAIN) {
6387                 spec->zxr_gain_set = *valp;
6388                 if (spec->cur_out_type == HEADPHONE_OUT)
6389                         changed = zxr_headphone_gain_set(codec, *valp);
6390                 else
6391                         changed = 0;
6392
6393                 goto exit;
6394         }
6395
6396         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6397                 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6398                 if (spec->cur_out_type == SPEAKER_OUT)
6399                         ca0132_alt_set_full_range_speaker(codec);
6400
6401                 changed = 0;
6402         }
6403
6404         if (nid == BASS_REDIRECTION) {
6405                 spec->bass_redirection_val = *valp;
6406                 if (spec->cur_out_type == SPEAKER_OUT)
6407                         ca0132_alt_surround_set_bass_redirection(codec, *valp);
6408
6409                 changed = 0;
6410         }
6411
6412 exit:
6413         snd_hda_power_down(codec);
6414         return changed;
6415 }
6416
6417 /*
6418  * Volume related
6419  */
6420 /*
6421  * Sets the internal DSP decibel level to match the DAC for output, and the
6422  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6423  * all alternative codecs set DSP playback volume.
6424  */
6425 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6426 {
6427         struct ca0132_spec *spec = codec->spec;
6428         unsigned int dsp_dir;
6429         unsigned int lookup_val;
6430
6431         if (nid == VNID_SPK)
6432                 dsp_dir = DSP_VOL_OUT;
6433         else
6434                 dsp_dir = DSP_VOL_IN;
6435
6436         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6437
6438         dspio_set_uint_param(codec,
6439                 ca0132_alt_vol_ctls[dsp_dir].mid,
6440                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6441                 float_vol_db_lookup[lookup_val]);
6442
6443         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6444
6445         dspio_set_uint_param(codec,
6446                 ca0132_alt_vol_ctls[dsp_dir].mid,
6447                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6448                 float_vol_db_lookup[lookup_val]);
6449
6450         dspio_set_uint_param(codec,
6451                 ca0132_alt_vol_ctls[dsp_dir].mid,
6452                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6453 }
6454
6455 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6456                               struct snd_ctl_elem_info *uinfo)
6457 {
6458         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6459         struct ca0132_spec *spec = codec->spec;
6460         hda_nid_t nid = get_amp_nid(kcontrol);
6461         int ch = get_amp_channels(kcontrol);
6462         int dir = get_amp_direction(kcontrol);
6463         unsigned long pval;
6464         int err;
6465
6466         switch (nid) {
6467         case VNID_SPK:
6468                 /* follow shared_out info */
6469                 nid = spec->shared_out_nid;
6470                 mutex_lock(&codec->control_mutex);
6471                 pval = kcontrol->private_value;
6472                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6473                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6474                 kcontrol->private_value = pval;
6475                 mutex_unlock(&codec->control_mutex);
6476                 break;
6477         case VNID_MIC:
6478                 /* follow shared_mic info */
6479                 nid = spec->shared_mic_nid;
6480                 mutex_lock(&codec->control_mutex);
6481                 pval = kcontrol->private_value;
6482                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6483                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6484                 kcontrol->private_value = pval;
6485                 mutex_unlock(&codec->control_mutex);
6486                 break;
6487         default:
6488                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6489         }
6490         return err;
6491 }
6492
6493 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6494                                 struct snd_ctl_elem_value *ucontrol)
6495 {
6496         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6497         struct ca0132_spec *spec = codec->spec;
6498         hda_nid_t nid = get_amp_nid(kcontrol);
6499         int ch = get_amp_channels(kcontrol);
6500         long *valp = ucontrol->value.integer.value;
6501
6502         /* store the left and right volume */
6503         if (ch & 1) {
6504                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6505                 valp++;
6506         }
6507         if (ch & 2) {
6508                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6509                 valp++;
6510         }
6511         return 0;
6512 }
6513
6514 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6515                                 struct snd_ctl_elem_value *ucontrol)
6516 {
6517         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6518         struct ca0132_spec *spec = codec->spec;
6519         hda_nid_t nid = get_amp_nid(kcontrol);
6520         int ch = get_amp_channels(kcontrol);
6521         long *valp = ucontrol->value.integer.value;
6522         hda_nid_t shared_nid = 0;
6523         bool effective;
6524         int changed = 1;
6525
6526         /* store the left and right volume */
6527         if (ch & 1) {
6528                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6529                 valp++;
6530         }
6531         if (ch & 2) {
6532                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6533                 valp++;
6534         }
6535
6536         /* if effective conditions, then update hw immediately. */
6537         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6538         if (effective) {
6539                 int dir = get_amp_direction(kcontrol);
6540                 unsigned long pval;
6541
6542                 snd_hda_power_up(codec);
6543                 mutex_lock(&codec->control_mutex);
6544                 pval = kcontrol->private_value;
6545                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6546                                                                 0, dir);
6547                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6548                 kcontrol->private_value = pval;
6549                 mutex_unlock(&codec->control_mutex);
6550                 snd_hda_power_down(codec);
6551         }
6552
6553         return changed;
6554 }
6555
6556 /*
6557  * This function is the same as the one above, because using an if statement
6558  * inside of the above volume control for the DSP volume would cause too much
6559  * lag. This is a lot more smooth.
6560  */
6561 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6562                                 struct snd_ctl_elem_value *ucontrol)
6563 {
6564         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6565         struct ca0132_spec *spec = codec->spec;
6566         hda_nid_t nid = get_amp_nid(kcontrol);
6567         int ch = get_amp_channels(kcontrol);
6568         long *valp = ucontrol->value.integer.value;
6569         hda_nid_t vnid = 0;
6570         int changed;
6571
6572         switch (nid) {
6573         case 0x02:
6574                 vnid = VNID_SPK;
6575                 break;
6576         case 0x07:
6577                 vnid = VNID_MIC;
6578                 break;
6579         }
6580
6581         /* store the left and right volume */
6582         if (ch & 1) {
6583                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6584                 valp++;
6585         }
6586         if (ch & 2) {
6587                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6588                 valp++;
6589         }
6590
6591         snd_hda_power_up(codec);
6592         ca0132_alt_dsp_volume_put(codec, vnid);
6593         mutex_lock(&codec->control_mutex);
6594         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6595         mutex_unlock(&codec->control_mutex);
6596         snd_hda_power_down(codec);
6597
6598         return changed;
6599 }
6600
6601 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6602                              unsigned int size, unsigned int __user *tlv)
6603 {
6604         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6605         struct ca0132_spec *spec = codec->spec;
6606         hda_nid_t nid = get_amp_nid(kcontrol);
6607         int ch = get_amp_channels(kcontrol);
6608         int dir = get_amp_direction(kcontrol);
6609         unsigned long pval;
6610         int err;
6611
6612         switch (nid) {
6613         case VNID_SPK:
6614                 /* follow shared_out tlv */
6615                 nid = spec->shared_out_nid;
6616                 mutex_lock(&codec->control_mutex);
6617                 pval = kcontrol->private_value;
6618                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6619                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6620                 kcontrol->private_value = pval;
6621                 mutex_unlock(&codec->control_mutex);
6622                 break;
6623         case VNID_MIC:
6624                 /* follow shared_mic tlv */
6625                 nid = spec->shared_mic_nid;
6626                 mutex_lock(&codec->control_mutex);
6627                 pval = kcontrol->private_value;
6628                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6629                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6630                 kcontrol->private_value = pval;
6631                 mutex_unlock(&codec->control_mutex);
6632                 break;
6633         default:
6634                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6635         }
6636         return err;
6637 }
6638
6639 /* Add volume slider control for effect level */
6640 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6641                                         const char *pfx, int dir)
6642 {
6643         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6644         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6645         struct snd_kcontrol_new knew =
6646                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6647
6648         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6649
6650         knew.tlv.c = NULL;
6651
6652         switch (nid) {
6653         case XBASS_XOVER:
6654                 knew.info = ca0132_alt_xbass_xover_slider_info;
6655                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6656                 knew.put = ca0132_alt_xbass_xover_slider_put;
6657                 break;
6658         default:
6659                 knew.info = ca0132_alt_effect_slider_info;
6660                 knew.get = ca0132_alt_slider_ctl_get;
6661                 knew.put = ca0132_alt_effect_slider_put;
6662                 knew.private_value =
6663                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6664                 break;
6665         }
6666
6667         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6668 }
6669
6670 /*
6671  * Added FX: prefix for the alternative codecs, because otherwise the surround
6672  * effect would conflict with the Surround sound volume control. Also seems more
6673  * clear as to what the switches do. Left alone for others.
6674  */
6675 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6676                          const char *pfx, int dir)
6677 {
6678         struct ca0132_spec *spec = codec->spec;
6679         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6680         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6681         struct snd_kcontrol_new knew =
6682                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6683         /* If using alt_controls, add FX: prefix. But, don't add FX:
6684          * prefix to OutFX or InFX enable controls.
6685          */
6686         if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6687                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6688         else
6689                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6690
6691         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6692 }
6693
6694 static int add_voicefx(struct hda_codec *codec)
6695 {
6696         struct snd_kcontrol_new knew =
6697                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6698                                     VOICEFX, 1, 0, HDA_INPUT);
6699         knew.info = ca0132_voicefx_info;
6700         knew.get = ca0132_voicefx_get;
6701         knew.put = ca0132_voicefx_put;
6702         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6703 }
6704
6705 /* Create the EQ Preset control */
6706 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6707 {
6708         struct snd_kcontrol_new knew =
6709                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6710                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6711         knew.info = ca0132_alt_eq_preset_info;
6712         knew.get = ca0132_alt_eq_preset_get;
6713         knew.put = ca0132_alt_eq_preset_put;
6714         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6715                                 snd_ctl_new1(&knew, codec));
6716 }
6717
6718 /*
6719  * Add enumerated control for the three different settings of the smart volume
6720  * output effect. Normal just uses the slider value, and loud and night are
6721  * their own things that ignore that value.
6722  */
6723 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6724 {
6725         struct snd_kcontrol_new knew =
6726                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6727                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6728         knew.info = ca0132_alt_svm_setting_info;
6729         knew.get = ca0132_alt_svm_setting_get;
6730         knew.put = ca0132_alt_svm_setting_put;
6731         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6732                                 snd_ctl_new1(&knew, codec));
6733
6734 }
6735
6736 /*
6737  * Create an Output Select enumerated control for codecs with surround
6738  * out capabilities.
6739  */
6740 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6741 {
6742         struct snd_kcontrol_new knew =
6743                 HDA_CODEC_MUTE_MONO("Output Select",
6744                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6745         knew.info = ca0132_alt_output_select_get_info;
6746         knew.get = ca0132_alt_output_select_get;
6747         knew.put = ca0132_alt_output_select_put;
6748         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6749                                 snd_ctl_new1(&knew, codec));
6750 }
6751
6752 /*
6753  * Add a control for selecting channel count on speaker output. Setting this
6754  * allows the DSP to do bass redirection and channel upmixing on surround
6755  * configurations.
6756  */
6757 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6758 {
6759         struct snd_kcontrol_new knew =
6760                 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6761                                     SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6762         knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6763         knew.get = ca0132_alt_speaker_channel_cfg_get;
6764         knew.put = ca0132_alt_speaker_channel_cfg_put;
6765         return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6766                                 snd_ctl_new1(&knew, codec));
6767 }
6768
6769 /*
6770  * Full range front stereo and rear surround switches. When these are set to
6771  * full range, the lower frequencies from these channels are no longer
6772  * redirected to the LFE channel.
6773  */
6774 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6775 {
6776         struct snd_kcontrol_new knew =
6777                 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6778                                     SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6779
6780         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6781                                 snd_ctl_new1(&knew, codec));
6782 }
6783
6784 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6785 {
6786         struct snd_kcontrol_new knew =
6787                 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6788                                     SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6789
6790         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6791                                 snd_ctl_new1(&knew, codec));
6792 }
6793
6794 /*
6795  * Bass redirection redirects audio below the crossover frequency to the LFE
6796  * channel on speakers that are set as not being full-range. On configurations
6797  * without an LFE channel, it does nothing. Bass redirection seems to be the
6798  * replacement for X-Bass on configurations with an LFE channel.
6799  */
6800 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6801 {
6802         const char *namestr = "Bass Redirection Crossover";
6803         struct snd_kcontrol_new knew =
6804                 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6805                                 HDA_OUTPUT);
6806
6807         knew.tlv.c = NULL;
6808         knew.info = ca0132_alt_xbass_xover_slider_info;
6809         knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6810         knew.put = ca0132_alt_xbass_xover_slider_put;
6811
6812         return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6813                         snd_ctl_new1(&knew, codec));
6814 }
6815
6816 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6817 {
6818         const char *namestr = "Bass Redirection";
6819         struct snd_kcontrol_new knew =
6820                 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6821                                 HDA_OUTPUT);
6822
6823         return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6824                         snd_ctl_new1(&knew, codec));
6825 }
6826
6827 /*
6828  * Create an Input Source enumerated control for the alternate ca0132 codecs
6829  * because the front microphone has no auto-detect, and Line-in has to be set
6830  * somehow.
6831  */
6832 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6833 {
6834         struct snd_kcontrol_new knew =
6835                 HDA_CODEC_MUTE_MONO("Input Source",
6836                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6837         knew.info = ca0132_alt_input_source_info;
6838         knew.get = ca0132_alt_input_source_get;
6839         knew.put = ca0132_alt_input_source_put;
6840         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6841                                 snd_ctl_new1(&knew, codec));
6842 }
6843
6844 /*
6845  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6846  * more control than the original mic boost, which is either full 30dB or off.
6847  */
6848 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6849 {
6850         struct snd_kcontrol_new knew =
6851                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6852                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6853         knew.info = ca0132_alt_mic_boost_info;
6854         knew.get = ca0132_alt_mic_boost_get;
6855         knew.put = ca0132_alt_mic_boost_put;
6856         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6857                                 snd_ctl_new1(&knew, codec));
6858
6859 }
6860
6861 /*
6862  * Add headphone gain enumerated control for the AE-5. This switches between
6863  * three modes, low, medium, and high. When non-headphone outputs are selected,
6864  * it is automatically set to high. This is the same behavior as Windows.
6865  */
6866 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6867 {
6868         struct snd_kcontrol_new knew =
6869                 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6870                                     AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6871         knew.info = ae5_headphone_gain_info;
6872         knew.get = ae5_headphone_gain_get;
6873         knew.put = ae5_headphone_gain_put;
6874         return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6875                                 snd_ctl_new1(&knew, codec));
6876 }
6877
6878 /*
6879  * Add sound filter enumerated control for the AE-5. This adds three different
6880  * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6881  * read into it, it changes the DAC's interpolation filter.
6882  */
6883 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6884 {
6885         struct snd_kcontrol_new knew =
6886                 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6887                                     AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6888         knew.info = ae5_sound_filter_info;
6889         knew.get = ae5_sound_filter_get;
6890         knew.put = ae5_sound_filter_put;
6891         return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6892                                 snd_ctl_new1(&knew, codec));
6893 }
6894
6895 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6896 {
6897         struct snd_kcontrol_new knew =
6898                 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6899                                     ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6900
6901         return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6902                                 snd_ctl_new1(&knew, codec));
6903 }
6904
6905 /*
6906  * Need to create follower controls for the alternate codecs that have surround
6907  * capabilities.
6908  */
6909 static const char * const ca0132_alt_follower_pfxs[] = {
6910         "Front", "Surround", "Center", "LFE", NULL,
6911 };
6912
6913 /*
6914  * Also need special channel map, because the default one is incorrect.
6915  * I think this has to do with the pin for rear surround being 0x11,
6916  * and the center/lfe being 0x10. Usually the pin order is the opposite.
6917  */
6918 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6919         { .channels = 2,
6920           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6921         { .channels = 4,
6922           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6923                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6924         { .channels = 6,
6925           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6926                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6927                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6928         { }
6929 };
6930
6931 /* Add the correct chmap for streams with 6 channels. */
6932 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6933 {
6934         int err = 0;
6935         struct hda_pcm *pcm;
6936
6937         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6938                 struct hda_pcm_stream *hinfo =
6939                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6940                 struct snd_pcm_chmap *chmap;
6941                 const struct snd_pcm_chmap_elem *elem;
6942
6943                 elem = ca0132_alt_chmaps;
6944                 if (hinfo->channels_max == 6) {
6945                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
6946                                         SNDRV_PCM_STREAM_PLAYBACK,
6947                                         elem, hinfo->channels_max, 0, &chmap);
6948                         if (err < 0)
6949                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6950                 }
6951         }
6952 }
6953
6954 /*
6955  * When changing Node IDs for Mixer Controls below, make sure to update
6956  * Node IDs in ca0132_config() as well.
6957  */
6958 static const struct snd_kcontrol_new ca0132_mixer[] = {
6959         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6960         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6961         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6962         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6963         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6964         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6965         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6966         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6967         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6968                                0x12, 1, HDA_INPUT),
6969         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6970                                VNID_HP_SEL, 1, HDA_OUTPUT),
6971         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6972                                VNID_AMIC1_SEL, 1, HDA_INPUT),
6973         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6974                                VNID_HP_ASEL, 1, HDA_OUTPUT),
6975         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6976                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
6977         { } /* end */
6978 };
6979
6980 /*
6981  * Desktop specific control mixer. Removes auto-detect for mic, and adds
6982  * surround controls. Also sets both the Front Playback and Capture Volume
6983  * controls to alt so they set the DSP's decibel level.
6984  */
6985 static const struct snd_kcontrol_new desktop_mixer[] = {
6986         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6987         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6988         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6989         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6990         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6991         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6992         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6993         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6994         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6995         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6996         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6997         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6998         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6999                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
7000         { } /* end */
7001 };
7002
7003 /*
7004  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7005  * because it doesn't set decibel levels for the DSP for capture.
7006  */
7007 static const struct snd_kcontrol_new r3di_mixer[] = {
7008         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7009         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7010         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7011         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7012         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7013         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7014         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7015         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7016         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7017         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7018         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7019         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7020         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7021                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
7022         { } /* end */
7023 };
7024
7025 static int ca0132_build_controls(struct hda_codec *codec)
7026 {
7027         struct ca0132_spec *spec = codec->spec;
7028         int i, num_fx, num_sliders;
7029         int err = 0;
7030
7031         /* Add Mixer controls */
7032         for (i = 0; i < spec->num_mixers; i++) {
7033                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7034                 if (err < 0)
7035                         return err;
7036         }
7037         /* Setup vmaster with surround followers for desktop ca0132 devices */
7038         if (ca0132_use_alt_functions(spec)) {
7039                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7040                                         spec->tlv);
7041                 snd_hda_add_vmaster(codec, "Master Playback Volume",
7042                                         spec->tlv, ca0132_alt_follower_pfxs,
7043                                         "Playback Volume", 0);
7044                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7045                                             NULL, ca0132_alt_follower_pfxs,
7046                                             "Playback Switch",
7047                                             true, 0, &spec->vmaster_mute.sw_kctl);
7048                 if (err < 0)
7049                         return err;
7050         }
7051
7052         /* Add in and out effects controls.
7053          * VoiceFX, PE and CrystalVoice are added separately.
7054          */
7055         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7056         for (i = 0; i < num_fx; i++) {
7057                 /* Desktop cards break if Echo Cancellation is used. */
7058                 if (ca0132_use_pci_mmio(spec)) {
7059                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7060                                                 OUT_EFFECTS_COUNT))
7061                                 continue;
7062                 }
7063
7064                 err = add_fx_switch(codec, ca0132_effects[i].nid,
7065                                     ca0132_effects[i].name,
7066                                     ca0132_effects[i].direct);
7067                 if (err < 0)
7068                         return err;
7069         }
7070         /*
7071          * If codec has use_alt_controls set to true, add effect level sliders,
7072          * EQ presets, and Smart Volume presets. Also, change names to add FX
7073          * prefix, and change PlayEnhancement and CrystalVoice to match.
7074          */
7075         if (ca0132_use_alt_controls(spec)) {
7076                 err = ca0132_alt_add_svm_enum(codec);
7077                 if (err < 0)
7078                         return err;
7079
7080                 err = add_ca0132_alt_eq_presets(codec);
7081                 if (err < 0)
7082                         return err;
7083
7084                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7085                                         "Enable OutFX", 0);
7086                 if (err < 0)
7087                         return err;
7088
7089                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7090                                         "Enable InFX", 1);
7091                 if (err < 0)
7092                         return err;
7093
7094                 num_sliders = OUT_EFFECTS_COUNT - 1;
7095                 for (i = 0; i < num_sliders; i++) {
7096                         err = ca0132_alt_add_effect_slider(codec,
7097                                             ca0132_effects[i].nid,
7098                                             ca0132_effects[i].name,
7099                                             ca0132_effects[i].direct);
7100                         if (err < 0)
7101                                 return err;
7102                 }
7103
7104                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7105                                         "X-Bass Crossover", EFX_DIR_OUT);
7106
7107                 if (err < 0)
7108                         return err;
7109         } else {
7110                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7111                                         "PlayEnhancement", 0);
7112                 if (err < 0)
7113                         return err;
7114
7115                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7116                                         "CrystalVoice", 1);
7117                 if (err < 0)
7118                         return err;
7119         }
7120         err = add_voicefx(codec);
7121         if (err < 0)
7122                 return err;
7123
7124         /*
7125          * If the codec uses alt_functions, you need the enumerated controls
7126          * to select the new outputs and inputs, plus add the new mic boost
7127          * setting control.
7128          */
7129         if (ca0132_use_alt_functions(spec)) {
7130                 err = ca0132_alt_add_output_enum(codec);
7131                 if (err < 0)
7132                         return err;
7133                 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7134                 if (err < 0)
7135                         return err;
7136                 err = ca0132_alt_add_front_full_range_switch(codec);
7137                 if (err < 0)
7138                         return err;
7139                 err = ca0132_alt_add_rear_full_range_switch(codec);
7140                 if (err < 0)
7141                         return err;
7142                 err = ca0132_alt_add_bass_redirection_crossover(codec);
7143                 if (err < 0)
7144                         return err;
7145                 err = ca0132_alt_add_bass_redirection_switch(codec);
7146                 if (err < 0)
7147                         return err;
7148                 err = ca0132_alt_add_mic_boost_enum(codec);
7149                 if (err < 0)
7150                         return err;
7151                 /*
7152                  * ZxR only has microphone input, there is no front panel
7153                  * header on the card, and aux-in is handled by the DBPro board.
7154                  */
7155                 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7156                         err = ca0132_alt_add_input_enum(codec);
7157                         if (err < 0)
7158                                 return err;
7159                 }
7160         }
7161
7162         switch (ca0132_quirk(spec)) {
7163         case QUIRK_AE5:
7164         case QUIRK_AE7:
7165                 err = ae5_add_headphone_gain_enum(codec);
7166                 if (err < 0)
7167                         return err;
7168                 err = ae5_add_sound_filter_enum(codec);
7169                 if (err < 0)
7170                         return err;
7171                 break;
7172         case QUIRK_ZXR:
7173                 err = zxr_add_headphone_gain_switch(codec);
7174                 if (err < 0)
7175                         return err;
7176                 break;
7177         default:
7178                 break;
7179         }
7180
7181 #ifdef ENABLE_TUNING_CONTROLS
7182         add_tuning_ctls(codec);
7183 #endif
7184
7185         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7186         if (err < 0)
7187                 return err;
7188
7189         if (spec->dig_out) {
7190                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7191                                                     spec->dig_out);
7192                 if (err < 0)
7193                         return err;
7194                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7195                 if (err < 0)
7196                         return err;
7197                 /* spec->multiout.share_spdif = 1; */
7198         }
7199
7200         if (spec->dig_in) {
7201                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7202                 if (err < 0)
7203                         return err;
7204         }
7205
7206         if (ca0132_use_alt_functions(spec))
7207                 ca0132_alt_add_chmap_ctls(codec);
7208
7209         return 0;
7210 }
7211
7212 static int dbpro_build_controls(struct hda_codec *codec)
7213 {
7214         struct ca0132_spec *spec = codec->spec;
7215         int err = 0;
7216
7217         if (spec->dig_out) {
7218                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7219                                 spec->dig_out);
7220                 if (err < 0)
7221                         return err;
7222         }
7223
7224         if (spec->dig_in) {
7225                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7226                 if (err < 0)
7227                         return err;
7228         }
7229
7230         return 0;
7231 }
7232
7233 /*
7234  * PCM
7235  */
7236 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7237         .substreams = 1,
7238         .channels_min = 2,
7239         .channels_max = 6,
7240         .ops = {
7241                 .prepare = ca0132_playback_pcm_prepare,
7242                 .cleanup = ca0132_playback_pcm_cleanup,
7243                 .get_delay = ca0132_playback_pcm_delay,
7244         },
7245 };
7246
7247 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7248         .substreams = 1,
7249         .channels_min = 2,
7250         .channels_max = 2,
7251         .ops = {
7252                 .prepare = ca0132_capture_pcm_prepare,
7253                 .cleanup = ca0132_capture_pcm_cleanup,
7254                 .get_delay = ca0132_capture_pcm_delay,
7255         },
7256 };
7257
7258 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7259         .substreams = 1,
7260         .channels_min = 2,
7261         .channels_max = 2,
7262         .ops = {
7263                 .open = ca0132_dig_playback_pcm_open,
7264                 .close = ca0132_dig_playback_pcm_close,
7265                 .prepare = ca0132_dig_playback_pcm_prepare,
7266                 .cleanup = ca0132_dig_playback_pcm_cleanup
7267         },
7268 };
7269
7270 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7271         .substreams = 1,
7272         .channels_min = 2,
7273         .channels_max = 2,
7274 };
7275
7276 static int ca0132_build_pcms(struct hda_codec *codec)
7277 {
7278         struct ca0132_spec *spec = codec->spec;
7279         struct hda_pcm *info;
7280
7281         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7282         if (!info)
7283                 return -ENOMEM;
7284         if (ca0132_use_alt_functions(spec)) {
7285                 info->own_chmap = true;
7286                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7287                         = ca0132_alt_chmaps;
7288         }
7289         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7290         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7291         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7292                 spec->multiout.max_channels;
7293         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7294         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7295         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7296
7297         /* With the DSP enabled, desktops don't use this ADC. */
7298         if (!ca0132_use_alt_functions(spec)) {
7299                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7300                 if (!info)
7301                         return -ENOMEM;
7302                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7303                         ca0132_pcm_analog_capture;
7304                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7305                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7306         }
7307
7308         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7309         if (!info)
7310                 return -ENOMEM;
7311         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7312         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7313         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7314
7315         if (!spec->dig_out && !spec->dig_in)
7316                 return 0;
7317
7318         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7319         if (!info)
7320                 return -ENOMEM;
7321         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7322         if (spec->dig_out) {
7323                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7324                         ca0132_pcm_digital_playback;
7325                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7326         }
7327         if (spec->dig_in) {
7328                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7329                         ca0132_pcm_digital_capture;
7330                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7331         }
7332
7333         return 0;
7334 }
7335
7336 static int dbpro_build_pcms(struct hda_codec *codec)
7337 {
7338         struct ca0132_spec *spec = codec->spec;
7339         struct hda_pcm *info;
7340
7341         info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7342         if (!info)
7343                 return -ENOMEM;
7344         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7345         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7346         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7347
7348
7349         if (!spec->dig_out && !spec->dig_in)
7350                 return 0;
7351
7352         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7353         if (!info)
7354                 return -ENOMEM;
7355         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7356         if (spec->dig_out) {
7357                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7358                         ca0132_pcm_digital_playback;
7359                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7360         }
7361         if (spec->dig_in) {
7362                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7363                         ca0132_pcm_digital_capture;
7364                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7365         }
7366
7367         return 0;
7368 }
7369
7370 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7371 {
7372         if (pin) {
7373                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7374                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7375                         snd_hda_codec_write(codec, pin, 0,
7376                                             AC_VERB_SET_AMP_GAIN_MUTE,
7377                                             AMP_OUT_UNMUTE);
7378         }
7379         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7380                 snd_hda_codec_write(codec, dac, 0,
7381                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7382 }
7383
7384 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7385 {
7386         if (pin) {
7387                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7388                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7389                         snd_hda_codec_write(codec, pin, 0,
7390                                             AC_VERB_SET_AMP_GAIN_MUTE,
7391                                             AMP_IN_UNMUTE(0));
7392         }
7393         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7394                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7395                                     AMP_IN_UNMUTE(0));
7396
7397                 /* init to 0 dB and unmute. */
7398                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7399                                          HDA_AMP_VOLMASK, 0x5a);
7400                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7401                                          HDA_AMP_MUTE, 0);
7402         }
7403 }
7404
7405 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7406 {
7407         unsigned int caps;
7408
7409         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7410                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7411         snd_hda_override_amp_caps(codec, nid, dir, caps);
7412 }
7413
7414 /*
7415  * Switch between Digital built-in mic and analog mic.
7416  */
7417 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7418 {
7419         struct ca0132_spec *spec = codec->spec;
7420         unsigned int tmp;
7421         u8 val;
7422         unsigned int oldval;
7423
7424         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7425
7426         oldval = stop_mic1(codec);
7427         ca0132_set_vipsource(codec, 0);
7428         if (enable) {
7429                 /* set DMic input as 2-ch */
7430                 tmp = FLOAT_TWO;
7431                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7432
7433                 val = spec->dmic_ctl;
7434                 val |= 0x80;
7435                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7436                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7437
7438                 if (!(spec->dmic_ctl & 0x20))
7439                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7440         } else {
7441                 /* set AMic input as mono */
7442                 tmp = FLOAT_ONE;
7443                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7444
7445                 val = spec->dmic_ctl;
7446                 /* clear bit7 and bit5 to disable dmic */
7447                 val &= 0x5f;
7448                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7449                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7450
7451                 if (!(spec->dmic_ctl & 0x20))
7452                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7453         }
7454         ca0132_set_vipsource(codec, 1);
7455         resume_mic1(codec, oldval);
7456 }
7457
7458 /*
7459  * Initialization for Digital Mic.
7460  */
7461 static void ca0132_init_dmic(struct hda_codec *codec)
7462 {
7463         struct ca0132_spec *spec = codec->spec;
7464         u8 val;
7465
7466         /* Setup Digital Mic here, but don't enable.
7467          * Enable based on jack detect.
7468          */
7469
7470         /* MCLK uses MPIO1, set to enable.
7471          * Bit 2-0: MPIO select
7472          * Bit   3: set to disable
7473          * Bit 7-4: reserved
7474          */
7475         val = 0x01;
7476         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7477                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7478
7479         /* Data1 uses MPIO3. Data2 not use
7480          * Bit 2-0: Data1 MPIO select
7481          * Bit   3: set disable Data1
7482          * Bit 6-4: Data2 MPIO select
7483          * Bit   7: set disable Data2
7484          */
7485         val = 0x83;
7486         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7487                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
7488
7489         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7490          * Bit 3-0: Channel mask
7491          * Bit   4: set for 48KHz, clear for 32KHz
7492          * Bit   5: mode
7493          * Bit   6: set to select Data2, clear for Data1
7494          * Bit   7: set to enable DMic, clear for AMic
7495          */
7496         if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7497                 val = 0x33;
7498         else
7499                 val = 0x23;
7500         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7501         spec->dmic_ctl = val;
7502         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7503                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
7504 }
7505
7506 /*
7507  * Initialization for Analog Mic 2
7508  */
7509 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7510 {
7511         struct ca0132_spec *spec = codec->spec;
7512
7513         mutex_lock(&spec->chipio_mutex);
7514
7515         chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7516         chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7517
7518         mutex_unlock(&spec->chipio_mutex);
7519 }
7520
7521 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7522 {
7523         struct ca0132_spec *spec = codec->spec;
7524         int i;
7525
7526         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7527         snd_hda_codec_update_widgets(codec);
7528
7529         for (i = 0; i < spec->multiout.num_dacs; i++)
7530                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7531
7532         for (i = 0; i < spec->num_outputs; i++)
7533                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7534
7535         for (i = 0; i < spec->num_inputs; i++) {
7536                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7537                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7538         }
7539 }
7540
7541
7542 /* If there is an active channel for some reason, find it and free it. */
7543 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7544 {
7545         unsigned int i, tmp;
7546         int status;
7547
7548         /* Read active DSPDMAC channel register. */
7549         status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7550         if (status >= 0) {
7551                 /* AND against 0xfff to get the active channel bits. */
7552                 tmp = tmp & 0xfff;
7553
7554                 /* If there are no active channels, nothing to free. */
7555                 if (!tmp)
7556                         return;
7557         } else {
7558                 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7559                                 __func__);
7560                 return;
7561         }
7562
7563         /*
7564          * Check each DSP DMA channel for activity, and if the channel is
7565          * active, free it.
7566          */
7567         for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7568                 if (dsp_is_dma_active(codec, i)) {
7569                         status = dspio_free_dma_chan(codec, i);
7570                         if (status < 0)
7571                                 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7572                                                 __func__, i);
7573                 }
7574         }
7575 }
7576
7577 /*
7578  * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7579  * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7580  * Instead, audio is now routed through the DSP's DMA controllers, which
7581  * the DSP is tasked with setting up itself. Through debugging, it seems the
7582  * cause of most of the no-audio on startup issues were due to improperly
7583  * configured DSP DMA channels.
7584  *
7585  * Normally, the DSP configures these the first time an HDA audio stream is
7586  * started post DSP firmware download. That is why creating a 'dummy' stream
7587  * worked in fixing the audio in some cases. This works most of the time, but
7588  * sometimes if a stream is started/stopped before the DSP can setup the DMA
7589  * configuration registers, it ends up in a broken state. Issues can also
7590  * arise if streams are started in an unusual order, i.e the audio output dma
7591  * channel being sandwiched between the mic1 and mic2 dma channels.
7592  *
7593  * The solution to this is to make sure that the DSP has no DMA channels
7594  * in use post DSP firmware download, and then to manually start each default
7595  * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7596  * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7597  */
7598 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7599 {
7600         static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7601         struct ca0132_spec *spec = codec->spec;
7602         unsigned int i, tmp;
7603
7604         /*
7605          * Check if any of the default streams are active, and if they are,
7606          * stop them.
7607          */
7608         mutex_lock(&spec->chipio_mutex);
7609
7610         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7611                 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7612
7613                 if (tmp) {
7614                         chipio_set_stream_control(codec,
7615                                         dsp_dma_stream_ids[i], 0);
7616                 }
7617         }
7618
7619         mutex_unlock(&spec->chipio_mutex);
7620
7621         /*
7622          * If all DSP streams are inactive, there should be no active DSP DMA
7623          * channels. Check and make sure this is the case, and if it isn't,
7624          * free any active channels.
7625          */
7626         ca0132_alt_free_active_dma_channels(codec);
7627
7628         mutex_lock(&spec->chipio_mutex);
7629
7630         /* Make sure stream 0x0c is six channels. */
7631         chipio_set_stream_channels(codec, 0x0c, 6);
7632
7633         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7634                 chipio_set_stream_control(codec,
7635                                 dsp_dma_stream_ids[i], 1);
7636
7637                 /* Give the DSP some time to setup the DMA channel. */
7638                 msleep(75);
7639         }
7640
7641         mutex_unlock(&spec->chipio_mutex);
7642 }
7643
7644 /*
7645  * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7646  * router', where each entry represents a 48khz audio channel, with a format
7647  * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7648  * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7649  * and 3 if it's using Sample Rate Converter ports.
7650  * An example is:
7651  * 0x0001f8c0
7652  * In this case, f8 is the destination, and c0 is the source. The number value
7653  * is 1.
7654  * This region of memory is normally managed internally by the 8051, where
7655  * the region of exram memory from 0x1477-0x1575 has each byte represent an
7656  * entry within the 0x190000 range, and when a range of entries is in use, the
7657  * ending value is overwritten with 0xff.
7658  * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7659  * streamID's, where each entry is a starting 0x190000 port offset.
7660  * 0x159d in exram is the same as 0x1578, except it contains the ending port
7661  * offset for the corresponding streamID.
7662  *
7663  * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7664  * the 8051, then manually overwritten to remap the ports to work with the
7665  * new DACs.
7666  *
7667  * Currently known portID's:
7668  * 0x00-0x1f: HDA audio stream input/output ports.
7669  * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7670  *            have the lower-nibble set to 0x1, 0x2, and 0x9.
7671  * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7672  * 0xe0-0xff: DAC/ADC audio input/output ports.
7673  *
7674  * Currently known streamID's:
7675  * 0x03: Mic1 ADC to DSP.
7676  * 0x04: Mic2 ADC to DSP.
7677  * 0x05: HDA node 0x02 audio stream to DSP.
7678  * 0x0f: DSP Mic exit to HDA node 0x07.
7679  * 0x0c: DSP processed audio to DACs.
7680  * 0x14: DAC0, front L/R.
7681  *
7682  * It is possible to route the HDA audio streams directly to the DAC and
7683  * bypass the DSP entirely, with the only downside being that since the DSP
7684  * does volume control, the only volume control you'll get is through PCM on
7685  * the PC side, in the same way volume is handled for optical out. This may be
7686  * useful for debugging.
7687  */
7688 static void chipio_remap_stream(struct hda_codec *codec,
7689                 const struct chipio_stream_remap_data *remap_data)
7690 {
7691         unsigned int i, stream_offset;
7692
7693         /* Get the starting port for the stream to be remapped. */
7694         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7695                         &stream_offset);
7696
7697         /*
7698          * Check if the stream's port value is 0xff, because the 8051 may not
7699          * have gotten around to setting up the stream yet. Wait until it's
7700          * setup to remap it's ports.
7701          */
7702         if (stream_offset == 0xff) {
7703                 for (i = 0; i < 5; i++) {
7704                         msleep(25);
7705
7706                         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7707                                         &stream_offset);
7708
7709                         if (stream_offset != 0xff)
7710                                 break;
7711                 }
7712         }
7713
7714         if (stream_offset == 0xff) {
7715                 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7716                                 __func__, remap_data->stream_id);
7717                 return;
7718         }
7719
7720         /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7721         stream_offset *= 0x04;
7722         stream_offset += 0x190000;
7723
7724         for (i = 0; i < remap_data->count; i++) {
7725                 chipio_write_no_mutex(codec,
7726                                 stream_offset + remap_data->offset[i],
7727                                 remap_data->value[i]);
7728         }
7729
7730         /* Update stream map configuration. */
7731         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7732 }
7733
7734 /*
7735  * Default speaker tuning values setup for alternative codecs.
7736  */
7737 static const unsigned int sbz_default_delay_values[] = {
7738         /* Non-zero values are floating point 0.000198. */
7739         0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7740 };
7741
7742 static const unsigned int zxr_default_delay_values[] = {
7743         /* Non-zero values are floating point 0.000220. */
7744         0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7745 };
7746
7747 static const unsigned int ae5_default_delay_values[] = {
7748         /* Non-zero values are floating point 0.000100. */
7749         0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7750 };
7751
7752 /*
7753  * If we never change these, probably only need them on initialization.
7754  */
7755 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7756 {
7757         struct ca0132_spec *spec = codec->spec;
7758         unsigned int i, tmp, start_req, end_req;
7759         const unsigned int *values;
7760
7761         switch (ca0132_quirk(spec)) {
7762         case QUIRK_SBZ:
7763                 values = sbz_default_delay_values;
7764                 break;
7765         case QUIRK_ZXR:
7766                 values = zxr_default_delay_values;
7767                 break;
7768         case QUIRK_AE5:
7769         case QUIRK_AE7:
7770                 values = ae5_default_delay_values;
7771                 break;
7772         default:
7773                 values = sbz_default_delay_values;
7774                 break;
7775         }
7776
7777         tmp = FLOAT_ZERO;
7778         dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7779
7780         start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7781         end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7782         for (i = start_req; i < end_req + 1; i++)
7783                 dspio_set_uint_param(codec, 0x96, i, tmp);
7784
7785         start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7786         end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7787         for (i = start_req; i < end_req + 1; i++)
7788                 dspio_set_uint_param(codec, 0x96, i, tmp);
7789
7790
7791         for (i = 0; i < 6; i++)
7792                 dspio_set_uint_param(codec, 0x96,
7793                                 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7794 }
7795
7796 /*
7797  * Initialize mic for non-chromebook ca0132 implementations.
7798  */
7799 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7800 {
7801         struct ca0132_spec *spec = codec->spec;
7802         unsigned int tmp;
7803
7804         /* Mic 1 Setup */
7805         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7806         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7807         if (ca0132_quirk(spec) == QUIRK_R3DI) {
7808                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7809                 tmp = FLOAT_ONE;
7810         } else
7811                 tmp = FLOAT_THREE;
7812         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7813
7814         /* Mic 2 setup (not present on desktop cards) */
7815         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7816         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7817         if (ca0132_quirk(spec) == QUIRK_R3DI)
7818                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7819         tmp = FLOAT_ZERO;
7820         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7821 }
7822
7823 /*
7824  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7825  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7826  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7827  * having an updated DAC, which changes the destination to that DAC.
7828  */
7829 static void sbz_connect_streams(struct hda_codec *codec)
7830 {
7831         struct ca0132_spec *spec = codec->spec;
7832
7833         mutex_lock(&spec->chipio_mutex);
7834
7835         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7836
7837         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7838         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7839
7840         /* Setup stream 0x14 with it's source and destination points */
7841         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7842         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7843         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7844         chipio_set_stream_channels(codec, 0x14, 2);
7845         chipio_set_stream_control(codec, 0x14, 1);
7846
7847         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7848
7849         mutex_unlock(&spec->chipio_mutex);
7850 }
7851
7852 /*
7853  * Write data through ChipIO to setup proper stream destinations.
7854  * Not sure how it exactly works, but it seems to direct data
7855  * to different destinations. Example is f8 to c0, e0 to c0.
7856  * All I know is, if you don't set these, you get no sound.
7857  */
7858 static void sbz_chipio_startup_data(struct hda_codec *codec)
7859 {
7860         const struct chipio_stream_remap_data *dsp_out_remap_data;
7861         struct ca0132_spec *spec = codec->spec;
7862
7863         mutex_lock(&spec->chipio_mutex);
7864         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7865
7866         /* Remap DAC0's output ports. */
7867         chipio_remap_stream(codec, &stream_remap_data[0]);
7868
7869         /* Remap DSP audio output stream ports. */
7870         switch (ca0132_quirk(spec)) {
7871         case QUIRK_SBZ:
7872                 dsp_out_remap_data = &stream_remap_data[1];
7873                 break;
7874
7875         case QUIRK_ZXR:
7876                 dsp_out_remap_data = &stream_remap_data[2];
7877                 break;
7878
7879         default:
7880                 dsp_out_remap_data = NULL;
7881                 break;
7882         }
7883
7884         if (dsp_out_remap_data)
7885                 chipio_remap_stream(codec, dsp_out_remap_data);
7886
7887         codec_dbg(codec, "Startup Data exited, mutex released.\n");
7888         mutex_unlock(&spec->chipio_mutex);
7889 }
7890
7891 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7892 {
7893         struct ca0132_spec *spec = codec->spec;
7894         unsigned int tmp;
7895
7896         chipio_set_stream_control(codec, 0x03, 0);
7897         chipio_set_stream_control(codec, 0x04, 0);
7898
7899         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7900         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7901
7902         tmp = FLOAT_THREE;
7903         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7904
7905         chipio_set_stream_control(codec, 0x03, 1);
7906         chipio_set_stream_control(codec, 0x04, 1);
7907
7908         switch (ca0132_quirk(spec)) {
7909         case QUIRK_SBZ:
7910                 chipio_write(codec, 0x18b098, 0x0000000c);
7911                 chipio_write(codec, 0x18b09C, 0x0000000c);
7912                 break;
7913         case QUIRK_AE5:
7914                 chipio_write(codec, 0x18b098, 0x0000000c);
7915                 chipio_write(codec, 0x18b09c, 0x0000004c);
7916                 break;
7917         default:
7918                 break;
7919         }
7920 }
7921
7922 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7923 {
7924         struct ca0132_spec *spec = codec->spec;
7925
7926         chipio_8051_write_direct(codec, 0x93, 0x10);
7927         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7928
7929         writeb(0xff, spec->mem_base + 0x304);
7930         writeb(0xff, spec->mem_base + 0x304);
7931         writeb(0xff, spec->mem_base + 0x304);
7932         writeb(0xff, spec->mem_base + 0x304);
7933         writeb(0x00, spec->mem_base + 0x100);
7934         writeb(0xff, spec->mem_base + 0x304);
7935         writeb(0x00, spec->mem_base + 0x100);
7936         writeb(0xff, spec->mem_base + 0x304);
7937         writeb(0x00, spec->mem_base + 0x100);
7938         writeb(0xff, spec->mem_base + 0x304);
7939         writeb(0x00, spec->mem_base + 0x100);
7940         writeb(0xff, spec->mem_base + 0x304);
7941
7942         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7943         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7944         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7945 }
7946
7947 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7948 {
7949         /*
7950          * Param3 in the 8051's memory is represented by the ascii string 'mch'
7951          * which seems to be 'multichannel'. This is also mentioned in the
7952          * AE-5's registry values in Windows.
7953          */
7954         chipio_set_control_param(codec, 3, 0);
7955         /*
7956          * I believe ASI is 'audio serial interface' and that it's used to
7957          * change colors on the external LED strip connected to the AE-5.
7958          */
7959         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7960
7961         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7962         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7963
7964         chipio_8051_write_exram(codec, 0xfa92, 0x22);
7965 }
7966
7967 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7968 {
7969         chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7970         chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7971         chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7972         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7973         chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7974 }
7975
7976 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7977 {
7978         struct ca0132_spec *spec = codec->spec;
7979
7980         mutex_lock(&spec->chipio_mutex);
7981
7982         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7983
7984         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7985
7986         chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7987
7988         chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7989         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7990         chipio_set_stream_channels(codec, 0x18, 6);
7991         chipio_set_stream_control(codec, 0x18, 1);
7992
7993         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7994
7995         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7996
7997         ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7998
7999         mutex_unlock(&spec->chipio_mutex);
8000 }
8001
8002 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8003 {
8004         struct ca0132_spec *spec = codec->spec;
8005
8006         mutex_lock(&spec->chipio_mutex);
8007
8008         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8009         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8010         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8011         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8012
8013         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8014         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8015         ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8016         ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8017         ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8018         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8019         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8020         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8021         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8022         ca0113_mmio_gpio_set(codec, 0, true);
8023         ca0113_mmio_gpio_set(codec, 1, true);
8024         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8025
8026         chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8027
8028         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8029         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8030
8031         mutex_unlock(&spec->chipio_mutex);
8032 }
8033
8034 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8035 {
8036         struct ca0132_spec *spec = codec->spec;
8037
8038         mutex_lock(&spec->chipio_mutex);
8039
8040         /* Seems to share the same port remapping as the SBZ. */
8041         chipio_remap_stream(codec, &stream_remap_data[1]);
8042
8043         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8044         ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8045         ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8046         ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8047         ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8048         ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8049         ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8050         ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8051
8052         mutex_unlock(&spec->chipio_mutex);
8053 }
8054
8055 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8056 {
8057         struct ca0132_spec *spec = codec->spec;
8058
8059         mutex_lock(&spec->chipio_mutex);
8060
8061         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8062         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8063
8064         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8065
8066         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8067         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8068
8069         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8070         chipio_set_stream_channels(codec, 0x18, 6);
8071         chipio_set_stream_control(codec, 0x18, 1);
8072
8073         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8074
8075         mutex_unlock(&spec->chipio_mutex);
8076 }
8077
8078 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8079 {
8080         static const unsigned int addr[] = {
8081                 0x41, 0x45, 0x40, 0x43, 0x51
8082         };
8083         static const unsigned int data[] = {
8084                 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8085         };
8086         unsigned int i;
8087
8088         for (i = 0; i < ARRAY_SIZE(addr); i++)
8089                 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8090 }
8091
8092 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8093 {
8094         struct ca0132_spec *spec = codec->spec;
8095         static const unsigned int target[] = {
8096                 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8097         };
8098         static const unsigned int data[] = {
8099                 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8100         };
8101         unsigned int i;
8102
8103         mutex_lock(&spec->chipio_mutex);
8104
8105         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8106
8107         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8108         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8109         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8110         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8111
8112         ae7_post_dsp_pll_setup(codec);
8113         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8114
8115         for (i = 0; i < ARRAY_SIZE(target); i++)
8116                 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8117
8118         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8119         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8120         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8121
8122         chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8123         chipio_set_stream_channels(codec, 0x21, 2);
8124         chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8125
8126         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8127         /*
8128          * In the 8051's memory, this param is referred to as 'n2sid', which I
8129          * believe is 'node to streamID'. It seems to be a way to assign a
8130          * stream to a given HDA node.
8131          */
8132         chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8133
8134         chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8135
8136         /*
8137          * Now, at this point on Windows, an actual stream is setup and
8138          * seemingly sends data to the HDA node 0x09, which is the digital
8139          * audio input node. This is left out here, because obviously I don't
8140          * know what data is being sent. Interestingly, the AE-5 seems to go
8141          * through the motions of getting here and never actually takes this
8142          * step, but the AE-7 does.
8143          */
8144
8145         ca0113_mmio_gpio_set(codec, 0, 1);
8146         ca0113_mmio_gpio_set(codec, 1, 1);
8147
8148         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8149         chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8150         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8151         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8152
8153         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8154         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8155
8156         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8157         chipio_set_stream_channels(codec, 0x18, 6);
8158
8159         /*
8160          * Runs again, this has been repeated a few times, but I'm just
8161          * following what the Windows driver does.
8162          */
8163         ae7_post_dsp_pll_setup(codec);
8164         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8165
8166         mutex_unlock(&spec->chipio_mutex);
8167 }
8168
8169 /*
8170  * The Windows driver has commands that seem to setup ASI, which I believe to
8171  * be some sort of audio serial interface. My current speculation is that it's
8172  * related to communicating with the new DAC.
8173  */
8174 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8175 {
8176         chipio_8051_write_direct(codec, 0x93, 0x10);
8177
8178         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8179
8180         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8181         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8182
8183         chipio_set_control_param(codec, 3, 3);
8184         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8185
8186         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8187         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8188         snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8189
8190         chipio_8051_write_exram(codec, 0xfa92, 0x22);
8191
8192         ae7_post_dsp_pll_setup(codec);
8193         ae7_post_dsp_asi_stream_setup(codec);
8194
8195         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8196
8197         ae7_post_dsp_asi_setup_ports(codec);
8198 }
8199
8200 /*
8201  * Setup default parameters for DSP
8202  */
8203 static void ca0132_setup_defaults(struct hda_codec *codec)
8204 {
8205         struct ca0132_spec *spec = codec->spec;
8206         unsigned int tmp;
8207         int num_fx;
8208         int idx, i;
8209
8210         if (spec->dsp_state != DSP_DOWNLOADED)
8211                 return;
8212
8213         /* out, in effects + voicefx */
8214         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8215         for (idx = 0; idx < num_fx; idx++) {
8216                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8217                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8218                                              ca0132_effects[idx].reqs[i],
8219                                              ca0132_effects[idx].def_vals[i]);
8220                 }
8221         }
8222
8223         /*remove DSP headroom*/
8224         tmp = FLOAT_ZERO;
8225         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8226
8227         /*set speaker EQ bypass attenuation*/
8228         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8229
8230         /* set AMic1 and AMic2 as mono mic */
8231         tmp = FLOAT_ONE;
8232         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8233         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8234
8235         /* set AMic1 as CrystalVoice input */
8236         tmp = FLOAT_ONE;
8237         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8238
8239         /* set WUH source */
8240         tmp = FLOAT_TWO;
8241         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8242 }
8243
8244 /*
8245  * Setup default parameters for Recon3D/Recon3Di DSP.
8246  */
8247
8248 static void r3d_setup_defaults(struct hda_codec *codec)
8249 {
8250         struct ca0132_spec *spec = codec->spec;
8251         unsigned int tmp;
8252         int num_fx;
8253         int idx, i;
8254
8255         if (spec->dsp_state != DSP_DOWNLOADED)
8256                 return;
8257
8258         ca0132_alt_init_analog_mics(codec);
8259         ca0132_alt_start_dsp_audio_streams(codec);
8260
8261         /*remove DSP headroom*/
8262         tmp = FLOAT_ZERO;
8263         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8264
8265         /* set WUH source */
8266         tmp = FLOAT_TWO;
8267         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8268         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8269
8270         /* Set speaker source? */
8271         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8272
8273         if (ca0132_quirk(spec) == QUIRK_R3DI)
8274                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8275
8276         /* Disable mute on Center/LFE. */
8277         if (ca0132_quirk(spec) == QUIRK_R3D) {
8278                 ca0113_mmio_gpio_set(codec, 2, false);
8279                 ca0113_mmio_gpio_set(codec, 4, true);
8280         }
8281
8282         /* Setup effect defaults */
8283         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8284         for (idx = 0; idx < num_fx; idx++) {
8285                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8286                         dspio_set_uint_param(codec,
8287                                         ca0132_effects[idx].mid,
8288                                         ca0132_effects[idx].reqs[i],
8289                                         ca0132_effects[idx].def_vals[i]);
8290                 }
8291         }
8292 }
8293
8294 /*
8295  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8296  * than the Chromebook setup.
8297  */
8298 static void sbz_setup_defaults(struct hda_codec *codec)
8299 {
8300         struct ca0132_spec *spec = codec->spec;
8301         unsigned int tmp;
8302         int num_fx;
8303         int idx, i;
8304
8305         if (spec->dsp_state != DSP_DOWNLOADED)
8306                 return;
8307
8308         ca0132_alt_init_analog_mics(codec);
8309         ca0132_alt_start_dsp_audio_streams(codec);
8310         sbz_connect_streams(codec);
8311         sbz_chipio_startup_data(codec);
8312
8313         /*
8314          * Sets internal input loopback to off, used to have a switch to
8315          * enable input loopback, but turned out to be way too buggy.
8316          */
8317         tmp = FLOAT_ONE;
8318         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8319         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8320
8321         /*remove DSP headroom*/
8322         tmp = FLOAT_ZERO;
8323         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8324
8325         /* set WUH source */
8326         tmp = FLOAT_TWO;
8327         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8328         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8329
8330         /* Set speaker source? */
8331         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8332
8333         ca0132_alt_dsp_initial_mic_setup(codec);
8334
8335         /* out, in effects + voicefx */
8336         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8337         for (idx = 0; idx < num_fx; idx++) {
8338                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8339                         dspio_set_uint_param(codec,
8340                                         ca0132_effects[idx].mid,
8341                                         ca0132_effects[idx].reqs[i],
8342                                         ca0132_effects[idx].def_vals[i]);
8343                 }
8344         }
8345
8346         ca0132_alt_init_speaker_tuning(codec);
8347 }
8348
8349 /*
8350  * Setup default parameters for the Sound BlasterX AE-5 DSP.
8351  */
8352 static void ae5_setup_defaults(struct hda_codec *codec)
8353 {
8354         struct ca0132_spec *spec = codec->spec;
8355         unsigned int tmp;
8356         int num_fx;
8357         int idx, i;
8358
8359         if (spec->dsp_state != DSP_DOWNLOADED)
8360                 return;
8361
8362         ca0132_alt_init_analog_mics(codec);
8363         ca0132_alt_start_dsp_audio_streams(codec);
8364
8365         /* New, unknown SCP req's */
8366         tmp = FLOAT_ZERO;
8367         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8368         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8369         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8370         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8371
8372         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8373         ca0113_mmio_gpio_set(codec, 0, false);
8374         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8375
8376         /* Internal loopback off */
8377         tmp = FLOAT_ONE;
8378         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8379         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8380
8381         /*remove DSP headroom*/
8382         tmp = FLOAT_ZERO;
8383         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8384
8385         /* set WUH source */
8386         tmp = FLOAT_TWO;
8387         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8388         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8389
8390         /* Set speaker source? */
8391         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8392
8393         ca0132_alt_dsp_initial_mic_setup(codec);
8394         ae5_post_dsp_register_set(codec);
8395         ae5_post_dsp_param_setup(codec);
8396         ae5_post_dsp_pll_setup(codec);
8397         ae5_post_dsp_stream_setup(codec);
8398         ae5_post_dsp_startup_data(codec);
8399
8400         /* out, in effects + voicefx */
8401         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8402         for (idx = 0; idx < num_fx; idx++) {
8403                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8404                         dspio_set_uint_param(codec,
8405                                         ca0132_effects[idx].mid,
8406                                         ca0132_effects[idx].reqs[i],
8407                                         ca0132_effects[idx].def_vals[i]);
8408                 }
8409         }
8410
8411         ca0132_alt_init_speaker_tuning(codec);
8412 }
8413
8414 /*
8415  * Setup default parameters for the Sound Blaster AE-7 DSP.
8416  */
8417 static void ae7_setup_defaults(struct hda_codec *codec)
8418 {
8419         struct ca0132_spec *spec = codec->spec;
8420         unsigned int tmp;
8421         int num_fx;
8422         int idx, i;
8423
8424         if (spec->dsp_state != DSP_DOWNLOADED)
8425                 return;
8426
8427         ca0132_alt_init_analog_mics(codec);
8428         ca0132_alt_start_dsp_audio_streams(codec);
8429         ae7_post_dsp_setup_ports(codec);
8430
8431         tmp = FLOAT_ZERO;
8432         dspio_set_uint_param(codec, 0x96,
8433                         SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8434         dspio_set_uint_param(codec, 0x96,
8435                         SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8436
8437         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8438
8439         /* New, unknown SCP req's */
8440         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8441         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8442
8443         ca0113_mmio_gpio_set(codec, 0, false);
8444
8445         /* Internal loopback off */
8446         tmp = FLOAT_ONE;
8447         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8448         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8449
8450         /*remove DSP headroom*/
8451         tmp = FLOAT_ZERO;
8452         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8453
8454         /* set WUH source */
8455         tmp = FLOAT_TWO;
8456         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8457         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8458
8459         /* Set speaker source? */
8460         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8461         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8462
8463         /*
8464          * This is the second time we've called this, but this is seemingly
8465          * what Windows does.
8466          */
8467         ca0132_alt_init_analog_mics(codec);
8468
8469         ae7_post_dsp_asi_setup(codec);
8470
8471         /*
8472          * Not sure why, but these are both set to 1. They're only set to 0
8473          * upon shutdown.
8474          */
8475         ca0113_mmio_gpio_set(codec, 0, true);
8476         ca0113_mmio_gpio_set(codec, 1, true);
8477
8478         /* Volume control related. */
8479         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8480         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8481         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8482
8483         /* out, in effects + voicefx */
8484         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8485         for (idx = 0; idx < num_fx; idx++) {
8486                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8487                         dspio_set_uint_param(codec,
8488                                         ca0132_effects[idx].mid,
8489                                         ca0132_effects[idx].reqs[i],
8490                                         ca0132_effects[idx].def_vals[i]);
8491                 }
8492         }
8493
8494         ca0132_alt_init_speaker_tuning(codec);
8495 }
8496
8497 /*
8498  * Initialization of flags in chip
8499  */
8500 static void ca0132_init_flags(struct hda_codec *codec)
8501 {
8502         struct ca0132_spec *spec = codec->spec;
8503
8504         if (ca0132_use_alt_functions(spec)) {
8505                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8506                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8507                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8508                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8509                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8510                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8511                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8512                 chipio_set_control_flag(codec,
8513                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8514                 chipio_set_control_flag(codec,
8515                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8516         } else {
8517                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8518                 chipio_set_control_flag(codec,
8519                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8520                 chipio_set_control_flag(codec,
8521                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8522                 chipio_set_control_flag(codec,
8523                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8524                 chipio_set_control_flag(codec,
8525                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8526                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8527         }
8528 }
8529
8530 /*
8531  * Initialization of parameters in chip
8532  */
8533 static void ca0132_init_params(struct hda_codec *codec)
8534 {
8535         struct ca0132_spec *spec = codec->spec;
8536
8537         if (ca0132_use_alt_functions(spec)) {
8538                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8539                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8540                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8541                 chipio_set_control_param(codec, 0, 0);
8542                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8543         }
8544
8545         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8546         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8547 }
8548
8549 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8550 {
8551         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8552         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8553         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8554         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8555         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8556         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8557
8558         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8559         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8560         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8561 }
8562
8563 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8564 {
8565         bool dsp_loaded = false;
8566         struct ca0132_spec *spec = codec->spec;
8567         const struct dsp_image_seg *dsp_os_image;
8568         const struct firmware *fw_entry = NULL;
8569         /*
8570          * Alternate firmwares for different variants. The Recon3Di apparently
8571          * can use the default firmware, but I'll leave the option in case
8572          * it needs it again.
8573          */
8574         switch (ca0132_quirk(spec)) {
8575         case QUIRK_SBZ:
8576         case QUIRK_R3D:
8577         case QUIRK_AE5:
8578                 if (reject_firmware(&fw_entry, DESKTOP_EFX_FILE,
8579                                         codec->card->dev) != 0)
8580                         codec_dbg(codec, "Desktop firmware not found.");
8581                 else
8582                         codec_dbg(codec, "Desktop firmware selected.");
8583                 break;
8584         case QUIRK_R3DI:
8585                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
8586                                         codec->card->dev) != 0)
8587                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
8588                 else
8589                         codec_dbg(codec, "Recon3Di firmware selected.");
8590                 break;
8591         default:
8592                 break;
8593         }
8594 /*(DEBLOBBED)*/
8595         if (!fw_entry) {
8596                 codec_dbg(codec, "Default firmware selected.");
8597                 if (reject_firmware(&fw_entry, EFX_FILE,
8598                                         codec->card->dev) != 0)
8599                         return false;
8600         }
8601
8602         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8603         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8604                 codec_err(codec, "ca0132 DSP load image failed\n");
8605                 goto exit_download;
8606         }
8607
8608         dsp_loaded = dspload_wait_loaded(codec);
8609
8610 exit_download:
8611         release_firmware(fw_entry);
8612
8613         return dsp_loaded;
8614 }
8615
8616 static void ca0132_download_dsp(struct hda_codec *codec)
8617 {
8618         struct ca0132_spec *spec = codec->spec;
8619
8620 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8621         return; /* NOP */
8622 #endif
8623
8624         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8625                 return; /* don't retry failures */
8626
8627         chipio_enable_clocks(codec);
8628         if (spec->dsp_state != DSP_DOWNLOADED) {
8629                 spec->dsp_state = DSP_DOWNLOADING;
8630
8631                 if (!ca0132_download_dsp_images(codec))
8632                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
8633                 else
8634                         spec->dsp_state = DSP_DOWNLOADED;
8635         }
8636
8637         /* For codecs using alt functions, this is already done earlier */
8638         if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8639                 ca0132_set_dsp_msr(codec, true);
8640 }
8641
8642 static void ca0132_process_dsp_response(struct hda_codec *codec,
8643                                         struct hda_jack_callback *callback)
8644 {
8645         struct ca0132_spec *spec = codec->spec;
8646
8647         codec_dbg(codec, "ca0132_process_dsp_response\n");
8648         snd_hda_power_up_pm(codec);
8649         if (spec->wait_scp) {
8650                 if (dspio_get_response_data(codec) >= 0)
8651                         spec->wait_scp = 0;
8652         }
8653
8654         dspio_clear_response_queue(codec);
8655         snd_hda_power_down_pm(codec);
8656 }
8657
8658 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8659 {
8660         struct ca0132_spec *spec = codec->spec;
8661         struct hda_jack_tbl *tbl;
8662
8663         /* Delay enabling the HP amp, to let the mic-detection
8664          * state machine run.
8665          */
8666         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8667         if (tbl)
8668                 tbl->block_report = 1;
8669         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8670 }
8671
8672 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8673 {
8674         struct ca0132_spec *spec = codec->spec;
8675
8676         if (ca0132_use_alt_functions(spec))
8677                 ca0132_alt_select_in(codec);
8678         else
8679                 ca0132_select_mic(codec);
8680 }
8681
8682 static void ca0132_setup_unsol(struct hda_codec *codec)
8683 {
8684         struct ca0132_spec *spec = codec->spec;
8685         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8686         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8687                                             amic_callback);
8688         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8689                                             ca0132_process_dsp_response);
8690         /* Front headphone jack detection */
8691         if (ca0132_use_alt_functions(spec))
8692                 snd_hda_jack_detect_enable_callback(codec,
8693                         spec->unsol_tag_front_hp, hp_callback);
8694 }
8695
8696 /*
8697  * Verbs tables.
8698  */
8699
8700 /* Sends before DSP download. */
8701 static const struct hda_verb ca0132_base_init_verbs[] = {
8702         /*enable ct extension*/
8703         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8704         {}
8705 };
8706
8707 /* Send at exit. */
8708 static const struct hda_verb ca0132_base_exit_verbs[] = {
8709         /*set afg to D3*/
8710         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8711         /*disable ct extension*/
8712         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8713         {}
8714 };
8715
8716 /* Other verbs tables. Sends after DSP download. */
8717
8718 static const struct hda_verb ca0132_init_verbs0[] = {
8719         /* chip init verbs */
8720         {0x15, 0x70D, 0xF0},
8721         {0x15, 0x70E, 0xFE},
8722         {0x15, 0x707, 0x75},
8723         {0x15, 0x707, 0xD3},
8724         {0x15, 0x707, 0x09},
8725         {0x15, 0x707, 0x53},
8726         {0x15, 0x707, 0xD4},
8727         {0x15, 0x707, 0xEF},
8728         {0x15, 0x707, 0x75},
8729         {0x15, 0x707, 0xD3},
8730         {0x15, 0x707, 0x09},
8731         {0x15, 0x707, 0x02},
8732         {0x15, 0x707, 0x37},
8733         {0x15, 0x707, 0x78},
8734         {0x15, 0x53C, 0xCE},
8735         {0x15, 0x575, 0xC9},
8736         {0x15, 0x53D, 0xCE},
8737         {0x15, 0x5B7, 0xC9},
8738         {0x15, 0x70D, 0xE8},
8739         {0x15, 0x70E, 0xFE},
8740         {0x15, 0x707, 0x02},
8741         {0x15, 0x707, 0x68},
8742         {0x15, 0x707, 0x62},
8743         {0x15, 0x53A, 0xCE},
8744         {0x15, 0x546, 0xC9},
8745         {0x15, 0x53B, 0xCE},
8746         {0x15, 0x5E8, 0xC9},
8747         {}
8748 };
8749
8750 /* Extra init verbs for desktop cards. */
8751 static const struct hda_verb ca0132_init_verbs1[] = {
8752         {0x15, 0x70D, 0x20},
8753         {0x15, 0x70E, 0x19},
8754         {0x15, 0x707, 0x00},
8755         {0x15, 0x539, 0xCE},
8756         {0x15, 0x546, 0xC9},
8757         {0x15, 0x70D, 0xB7},
8758         {0x15, 0x70E, 0x09},
8759         {0x15, 0x707, 0x10},
8760         {0x15, 0x70D, 0xAF},
8761         {0x15, 0x70E, 0x09},
8762         {0x15, 0x707, 0x01},
8763         {0x15, 0x707, 0x05},
8764         {0x15, 0x70D, 0x73},
8765         {0x15, 0x70E, 0x09},
8766         {0x15, 0x707, 0x14},
8767         {0x15, 0x6FF, 0xC4},
8768         {}
8769 };
8770
8771 static void ca0132_init_chip(struct hda_codec *codec)
8772 {
8773         struct ca0132_spec *spec = codec->spec;
8774         int num_fx;
8775         int i;
8776         unsigned int on;
8777
8778         mutex_init(&spec->chipio_mutex);
8779
8780         /*
8781          * The Windows driver always does this upon startup, which seems to
8782          * clear out any previous configuration. This should help issues where
8783          * a boot into Windows prior to a boot into Linux breaks things. Also,
8784          * Windows always sends the reset twice.
8785          */
8786         if (ca0132_use_alt_functions(spec)) {
8787                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8788                 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8789
8790                 snd_hda_codec_write(codec, codec->core.afg, 0,
8791                             AC_VERB_SET_CODEC_RESET, 0);
8792                 snd_hda_codec_write(codec, codec->core.afg, 0,
8793                             AC_VERB_SET_CODEC_RESET, 0);
8794         }
8795
8796         spec->cur_out_type = SPEAKER_OUT;
8797         if (!ca0132_use_alt_functions(spec))
8798                 spec->cur_mic_type = DIGITAL_MIC;
8799         else
8800                 spec->cur_mic_type = REAR_MIC;
8801
8802         spec->cur_mic_boost = 0;
8803
8804         for (i = 0; i < VNODES_COUNT; i++) {
8805                 spec->vnode_lvol[i] = 0x5a;
8806                 spec->vnode_rvol[i] = 0x5a;
8807                 spec->vnode_lswitch[i] = 0;
8808                 spec->vnode_rswitch[i] = 0;
8809         }
8810
8811         /*
8812          * Default states for effects are in ca0132_effects[].
8813          */
8814         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8815         for (i = 0; i < num_fx; i++) {
8816                 on = (unsigned int)ca0132_effects[i].reqs[0];
8817                 spec->effects_switch[i] = on ? 1 : 0;
8818         }
8819         /*
8820          * Sets defaults for the effect slider controls, only for alternative
8821          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8822          */
8823         if (ca0132_use_alt_controls(spec)) {
8824                 /* Set speakers to default to full range. */
8825                 spec->speaker_range_val[0] = 1;
8826                 spec->speaker_range_val[1] = 1;
8827
8828                 spec->xbass_xover_freq = 8;
8829                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8830                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
8831
8832                 spec->bass_redirect_xover_freq = 8;
8833         }
8834
8835         spec->voicefx_val = 0;
8836         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8837         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8838
8839         /*
8840          * The ZxR doesn't have a front panel header, and it's line-in is on
8841          * the daughter board. So, there is no input enum control, and we need
8842          * to make sure that spec->in_enum_val is set properly.
8843          */
8844         if (ca0132_quirk(spec) == QUIRK_ZXR)
8845                 spec->in_enum_val = REAR_MIC;
8846
8847 #ifdef ENABLE_TUNING_CONTROLS
8848         ca0132_init_tuning_defaults(codec);
8849 #endif
8850 }
8851
8852 /*
8853  * Recon3Di exit specific commands.
8854  */
8855 /* prevents popping noise on shutdown */
8856 static void r3di_gpio_shutdown(struct hda_codec *codec)
8857 {
8858         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8859 }
8860
8861 /*
8862  * Sound Blaster Z exit specific commands.
8863  */
8864 static void sbz_region2_exit(struct hda_codec *codec)
8865 {
8866         struct ca0132_spec *spec = codec->spec;
8867         unsigned int i;
8868
8869         for (i = 0; i < 4; i++)
8870                 writeb(0x0, spec->mem_base + 0x100);
8871         for (i = 0; i < 8; i++)
8872                 writeb(0xb3, spec->mem_base + 0x304);
8873
8874         ca0113_mmio_gpio_set(codec, 0, false);
8875         ca0113_mmio_gpio_set(codec, 1, false);
8876         ca0113_mmio_gpio_set(codec, 4, true);
8877         ca0113_mmio_gpio_set(codec, 5, false);
8878         ca0113_mmio_gpio_set(codec, 7, false);
8879 }
8880
8881 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8882 {
8883         static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8884         unsigned int i;
8885
8886         snd_hda_codec_write(codec, 0x11, 0,
8887                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8888
8889         for (i = 0; i < ARRAY_SIZE(pins); i++)
8890                 snd_hda_codec_write(codec, pins[i], 0,
8891                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8892 }
8893
8894 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8895 {
8896         static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8897         unsigned int i;
8898
8899         for (i = 0; i < ARRAY_SIZE(pins); i++) {
8900                 snd_hda_codec_write(codec, pins[i], 0,
8901                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8902         }
8903 }
8904
8905 /* On shutdown, sends commands in sets of three */
8906 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8907                                                         int mask, int data)
8908 {
8909         if (dir >= 0)
8910                 snd_hda_codec_write(codec, 0x01, 0,
8911                                 AC_VERB_SET_GPIO_DIRECTION, dir);
8912         if (mask >= 0)
8913                 snd_hda_codec_write(codec, 0x01, 0,
8914                                 AC_VERB_SET_GPIO_MASK, mask);
8915
8916         if (data >= 0)
8917                 snd_hda_codec_write(codec, 0x01, 0,
8918                                 AC_VERB_SET_GPIO_DATA, data);
8919 }
8920
8921 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8922 {
8923         static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8924         unsigned int i;
8925
8926         for (i = 0; i < ARRAY_SIZE(pins); i++)
8927                 snd_hda_codec_write(codec, pins[i], 0,
8928                                 AC_VERB_SET_POWER_STATE, 0x03);
8929 }
8930
8931 static void sbz_exit_chip(struct hda_codec *codec)
8932 {
8933         chipio_set_stream_control(codec, 0x03, 0);
8934         chipio_set_stream_control(codec, 0x04, 0);
8935
8936         /* Mess with GPIO */
8937         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8938         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8939         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8940
8941         chipio_set_stream_control(codec, 0x14, 0);
8942         chipio_set_stream_control(codec, 0x0C, 0);
8943
8944         chipio_set_conn_rate(codec, 0x41, SR_192_000);
8945         chipio_set_conn_rate(codec, 0x91, SR_192_000);
8946
8947         chipio_write(codec, 0x18a020, 0x00000083);
8948
8949         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8950         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8951         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8952
8953         chipio_set_stream_control(codec, 0x0C, 0);
8954
8955         chipio_set_control_param(codec, 0x0D, 0x24);
8956
8957         ca0132_clear_unsolicited(codec);
8958         sbz_set_pin_ctl_default(codec);
8959
8960         snd_hda_codec_write(codec, 0x0B, 0,
8961                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8962
8963         sbz_region2_exit(codec);
8964 }
8965
8966 static void r3d_exit_chip(struct hda_codec *codec)
8967 {
8968         ca0132_clear_unsolicited(codec);
8969         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8970         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8971 }
8972
8973 static void ae5_exit_chip(struct hda_codec *codec)
8974 {
8975         chipio_set_stream_control(codec, 0x03, 0);
8976         chipio_set_stream_control(codec, 0x04, 0);
8977
8978         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8979         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8980         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8981         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8982         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8983         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8984         ca0113_mmio_gpio_set(codec, 0, false);
8985         ca0113_mmio_gpio_set(codec, 1, false);
8986
8987         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8988         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8989
8990         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8991
8992         chipio_set_stream_control(codec, 0x18, 0);
8993         chipio_set_stream_control(codec, 0x0c, 0);
8994
8995         snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8996 }
8997
8998 static void ae7_exit_chip(struct hda_codec *codec)
8999 {
9000         chipio_set_stream_control(codec, 0x18, 0);
9001         chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9002         chipio_set_stream_channels(codec, 0x21, 0);
9003         chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9004         chipio_set_control_param(codec, 0x20, 0x01);
9005
9006         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9007
9008         chipio_set_stream_control(codec, 0x18, 0);
9009         chipio_set_stream_control(codec, 0x0c, 0);
9010
9011         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9012         snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9013         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9014         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9015         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9016         ca0113_mmio_gpio_set(codec, 0, false);
9017         ca0113_mmio_gpio_set(codec, 1, false);
9018         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9019
9020         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9021         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9022 }
9023
9024 static void zxr_exit_chip(struct hda_codec *codec)
9025 {
9026         chipio_set_stream_control(codec, 0x03, 0);
9027         chipio_set_stream_control(codec, 0x04, 0);
9028         chipio_set_stream_control(codec, 0x14, 0);
9029         chipio_set_stream_control(codec, 0x0C, 0);
9030
9031         chipio_set_conn_rate(codec, 0x41, SR_192_000);
9032         chipio_set_conn_rate(codec, 0x91, SR_192_000);
9033
9034         chipio_write(codec, 0x18a020, 0x00000083);
9035
9036         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9037         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9038
9039         ca0132_clear_unsolicited(codec);
9040         sbz_set_pin_ctl_default(codec);
9041         snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9042
9043         ca0113_mmio_gpio_set(codec, 5, false);
9044         ca0113_mmio_gpio_set(codec, 2, false);
9045         ca0113_mmio_gpio_set(codec, 3, false);
9046         ca0113_mmio_gpio_set(codec, 0, false);
9047         ca0113_mmio_gpio_set(codec, 4, true);
9048         ca0113_mmio_gpio_set(codec, 0, true);
9049         ca0113_mmio_gpio_set(codec, 5, true);
9050         ca0113_mmio_gpio_set(codec, 2, false);
9051         ca0113_mmio_gpio_set(codec, 3, false);
9052 }
9053
9054 static void ca0132_exit_chip(struct hda_codec *codec)
9055 {
9056         /* put any chip cleanup stuffs here. */
9057
9058         if (dspload_is_loaded(codec))
9059                 dsp_reset(codec);
9060 }
9061
9062 /*
9063  * This fixes a problem that was hard to reproduce. Very rarely, I would
9064  * boot up, and there would be no sound, but the DSP indicated it had loaded
9065  * properly. I did a few memory dumps to see if anything was different, and
9066  * there were a few areas of memory uninitialized with a1a2a3a4. This function
9067  * checks if those areas are uninitialized, and if they are, it'll attempt to
9068  * reload the card 3 times. Usually it fixes by the second.
9069  */
9070 static void sbz_dsp_startup_check(struct hda_codec *codec)
9071 {
9072         struct ca0132_spec *spec = codec->spec;
9073         unsigned int dsp_data_check[4];
9074         unsigned int cur_address = 0x390;
9075         unsigned int i;
9076         unsigned int failure = 0;
9077         unsigned int reload = 3;
9078
9079         if (spec->startup_check_entered)
9080                 return;
9081
9082         spec->startup_check_entered = true;
9083
9084         for (i = 0; i < 4; i++) {
9085                 chipio_read(codec, cur_address, &dsp_data_check[i]);
9086                 cur_address += 0x4;
9087         }
9088         for (i = 0; i < 4; i++) {
9089                 if (dsp_data_check[i] == 0xa1a2a3a4)
9090                         failure = 1;
9091         }
9092
9093         codec_dbg(codec, "Startup Check: %d ", failure);
9094         if (failure)
9095                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9096         /*
9097          * While the failure condition is true, and we haven't reached our
9098          * three reload limit, continue trying to reload the driver and
9099          * fix the issue.
9100          */
9101         while (failure && (reload != 0)) {
9102                 codec_info(codec, "Reloading... Tries left: %d", reload);
9103                 sbz_exit_chip(codec);
9104                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9105                 codec->patch_ops.init(codec);
9106                 failure = 0;
9107                 for (i = 0; i < 4; i++) {
9108                         chipio_read(codec, cur_address, &dsp_data_check[i]);
9109                         cur_address += 0x4;
9110                 }
9111                 for (i = 0; i < 4; i++) {
9112                         if (dsp_data_check[i] == 0xa1a2a3a4)
9113                                 failure = 1;
9114                 }
9115                 reload--;
9116         }
9117
9118         if (!failure && reload < 3)
9119                 codec_info(codec, "DSP fixed.");
9120
9121         if (!failure)
9122                 return;
9123
9124         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9125 }
9126
9127 /*
9128  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9129  * extra precision for decibel values. If you had the dB value in floating point
9130  * you would take the value after the decimal point, multiply by 64, and divide
9131  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9132  * implement fixed point or floating point dB volumes. For now, I'll set them
9133  * to 0 just incase a value has lingered from a boot into Windows.
9134  */
9135 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9136 {
9137         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9138         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9139         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9140         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9141         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9142         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9143         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9144         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9145 }
9146
9147 /*
9148  * Extra commands that don't really fit anywhere else.
9149  */
9150 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9151 {
9152         struct ca0132_spec *spec = codec->spec;
9153
9154         writel(0x00820680, spec->mem_base + 0x01C);
9155         writel(0x00820680, spec->mem_base + 0x01C);
9156
9157         chipio_write(codec, 0x18b0a4, 0x000000c2);
9158
9159         snd_hda_codec_write(codec, 0x11, 0,
9160                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9161 }
9162
9163 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9164 {
9165         chipio_write(codec, 0x18b0a4, 0x000000c2);
9166
9167         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9168
9169         snd_hda_codec_write(codec, 0x11, 0,
9170                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9171 }
9172
9173 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9174 {
9175         chipio_write(codec, 0x18b0a4, 0x000000c2);
9176
9177         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9178         chipio_8051_write_exram(codec, 0x1920, 0x00);
9179         chipio_8051_write_exram(codec, 0x1921, 0x40);
9180
9181         snd_hda_codec_write(codec, 0x11, 0,
9182                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9183 }
9184
9185 /*
9186  * The ZxR seems to use alternative DAC's for the surround channels, which
9187  * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9188  * this up, we get no audio out of the surround jacks.
9189  */
9190 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9191 {
9192         static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9193         static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9194         unsigned int i;
9195
9196         chipio_write(codec, 0x189000, 0x0001f100);
9197         msleep(50);
9198         chipio_write(codec, 0x18900c, 0x0001f100);
9199         msleep(50);
9200
9201         /*
9202          * This writes a RET instruction at the entry point of the function at
9203          * 0xfa92 in exram. This function seems to have something to do with
9204          * ASI. Might be some way to prevent the card from reconfiguring the
9205          * ASI stuff itself.
9206          */
9207         chipio_8051_write_exram(codec, 0xfa92, 0x22);
9208
9209         chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9210
9211         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9212         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9213
9214         chipio_write(codec, 0x18902c, 0x00000000);
9215         msleep(50);
9216         chipio_write(codec, 0x18902c, 0x00000003);
9217         msleep(50);
9218
9219         for (i = 0; i < ARRAY_SIZE(addr); i++)
9220                 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9221 }
9222
9223 /*
9224  * These are sent before the DSP is downloaded. Not sure
9225  * what they do, or if they're necessary. Could possibly
9226  * be removed. Figure they're better to leave in.
9227  */
9228 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9229         0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9230         0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9231 };
9232
9233 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9234         0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9235         0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9236         0x000000c1, 0x00000080
9237 };
9238
9239 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9240         0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9241         0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9242         0x000000c1, 0x00000080
9243 };
9244
9245 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9246         0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9247         0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9248         0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9249         0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9250 };
9251
9252 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9253         0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9254         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9255         0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9256         0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9257         0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9258         0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9259         0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9260         0x00000080, 0x00880680
9261 };
9262
9263 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9264 {
9265         struct ca0132_spec *spec = codec->spec;
9266         unsigned int tmp[2], i, count, cur_addr;
9267         const unsigned int *addr, *data;
9268
9269         addr = ca0113_mmio_init_address_sbz;
9270         for (i = 0; i < 3; i++)
9271                 writel(0x00000000, spec->mem_base + addr[i]);
9272
9273         cur_addr = i;
9274         switch (ca0132_quirk(spec)) {
9275         case QUIRK_ZXR:
9276                 tmp[0] = 0x00880480;
9277                 tmp[1] = 0x00000080;
9278                 break;
9279         case QUIRK_SBZ:
9280                 tmp[0] = 0x00820680;
9281                 tmp[1] = 0x00000083;
9282                 break;
9283         case QUIRK_R3D:
9284                 tmp[0] = 0x00880680;
9285                 tmp[1] = 0x00000083;
9286                 break;
9287         default:
9288                 tmp[0] = 0x00000000;
9289                 tmp[1] = 0x00000000;
9290                 break;
9291         }
9292
9293         for (i = 0; i < 2; i++)
9294                 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9295
9296         cur_addr += i;
9297
9298         switch (ca0132_quirk(spec)) {
9299         case QUIRK_ZXR:
9300                 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9301                 data = ca0113_mmio_init_data_zxr;
9302                 break;
9303         default:
9304                 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9305                 data = ca0113_mmio_init_data_sbz;
9306                 break;
9307         }
9308
9309         for (i = 0; i < count; i++)
9310                 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9311 }
9312
9313 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9314 {
9315         struct ca0132_spec *spec = codec->spec;
9316         const unsigned int *addr, *data;
9317         unsigned int i, count;
9318
9319         addr = ca0113_mmio_init_address_ae5;
9320         data = ca0113_mmio_init_data_ae5;
9321         count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9322
9323         if (ca0132_quirk(spec) == QUIRK_AE7) {
9324                 writel(0x00000680, spec->mem_base + 0x1c);
9325                 writel(0x00880680, spec->mem_base + 0x1c);
9326         }
9327
9328         for (i = 0; i < count; i++) {
9329                 /*
9330                  * AE-7 shares all writes with the AE-5, except that it writes
9331                  * a different value to 0x20c.
9332                  */
9333                 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9334                         writel(0x00800001, spec->mem_base + addr[i]);
9335                         continue;
9336                 }
9337
9338                 writel(data[i], spec->mem_base + addr[i]);
9339         }
9340
9341         if (ca0132_quirk(spec) == QUIRK_AE5)
9342                 writel(0x00880680, spec->mem_base + 0x1c);
9343 }
9344
9345 static void ca0132_mmio_init(struct hda_codec *codec)
9346 {
9347         struct ca0132_spec *spec = codec->spec;
9348
9349         switch (ca0132_quirk(spec)) {
9350         case QUIRK_R3D:
9351         case QUIRK_SBZ:
9352         case QUIRK_ZXR:
9353                 ca0132_mmio_init_sbz(codec);
9354                 break;
9355         case QUIRK_AE5:
9356                 ca0132_mmio_init_ae5(codec);
9357                 break;
9358         default:
9359                 break;
9360         }
9361 }
9362
9363 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9364         0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9365         0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9366 };
9367
9368 static const unsigned char ca0132_ae5_register_set_data[] = {
9369         0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9370         0x01, 0x6b, 0x57
9371 };
9372
9373 /*
9374  * This function writes to some SFR's, does some region2 writes, and then
9375  * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9376  * what it does.
9377  */
9378 static void ae5_register_set(struct hda_codec *codec)
9379 {
9380         struct ca0132_spec *spec = codec->spec;
9381         unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9382         const unsigned int *addr = ca0132_ae5_register_set_addresses;
9383         const unsigned char *data = ca0132_ae5_register_set_data;
9384         unsigned int i, cur_addr;
9385         unsigned char tmp[3];
9386
9387         if (ca0132_quirk(spec) == QUIRK_AE7)
9388                 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9389
9390         chipio_8051_write_direct(codec, 0x93, 0x10);
9391         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9392
9393         if (ca0132_quirk(spec) == QUIRK_AE7) {
9394                 tmp[0] = 0x03;
9395                 tmp[1] = 0x03;
9396                 tmp[2] = 0x07;
9397         } else {
9398                 tmp[0] = 0x0f;
9399                 tmp[1] = 0x0f;
9400                 tmp[2] = 0x0f;
9401         }
9402
9403         for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9404                 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9405
9406         /*
9407          * First writes are in single bytes, final are in 4 bytes. So, we use
9408          * writeb, then writel.
9409          */
9410         for (i = 0; cur_addr < 12; i++, cur_addr++)
9411                 writeb(data[i], spec->mem_base + addr[cur_addr]);
9412
9413         for (; cur_addr < count; i++, cur_addr++)
9414                 writel(data[i], spec->mem_base + addr[cur_addr]);
9415
9416         writel(0x00800001, spec->mem_base + 0x20c);
9417
9418         if (ca0132_quirk(spec) == QUIRK_AE7) {
9419                 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9420                 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9421         } else {
9422                 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9423         }
9424
9425         chipio_8051_write_direct(codec, 0x90, 0x00);
9426         chipio_8051_write_direct(codec, 0x90, 0x10);
9427
9428         if (ca0132_quirk(spec) == QUIRK_AE5)
9429                 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9430 }
9431
9432 /*
9433  * Extra init functions for alternative ca0132 codecs. Done
9434  * here so they don't clutter up the main ca0132_init function
9435  * anymore than they have to.
9436  */
9437 static void ca0132_alt_init(struct hda_codec *codec)
9438 {
9439         struct ca0132_spec *spec = codec->spec;
9440
9441         ca0132_alt_vol_setup(codec);
9442
9443         switch (ca0132_quirk(spec)) {
9444         case QUIRK_SBZ:
9445                 codec_dbg(codec, "SBZ alt_init");
9446                 ca0132_gpio_init(codec);
9447                 sbz_pre_dsp_setup(codec);
9448                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9449                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9450                 break;
9451         case QUIRK_R3DI:
9452                 codec_dbg(codec, "R3DI alt_init");
9453                 ca0132_gpio_init(codec);
9454                 ca0132_gpio_setup(codec);
9455                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9456                 r3di_pre_dsp_setup(codec);
9457                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9458                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9459                 break;
9460         case QUIRK_R3D:
9461                 r3d_pre_dsp_setup(codec);
9462                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9463                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9464                 break;
9465         case QUIRK_AE5:
9466                 ca0132_gpio_init(codec);
9467                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9468                 chipio_write(codec, 0x18b030, 0x00000020);
9469                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9470                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9471                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9472                 break;
9473         case QUIRK_AE7:
9474                 ca0132_gpio_init(codec);
9475                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9476                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9477                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9478                 chipio_write(codec, 0x18b008, 0x000000f8);
9479                 chipio_write(codec, 0x18b008, 0x000000f0);
9480                 chipio_write(codec, 0x18b030, 0x00000020);
9481                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9482                 break;
9483         case QUIRK_ZXR:
9484                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9485                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9486                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9487                 zxr_pre_dsp_setup(codec);
9488                 break;
9489         default:
9490                 break;
9491         }
9492 }
9493
9494 static int ca0132_init(struct hda_codec *codec)
9495 {
9496         struct ca0132_spec *spec = codec->spec;
9497         struct auto_pin_cfg *cfg = &spec->autocfg;
9498         int i;
9499         bool dsp_loaded;
9500
9501         /*
9502          * If the DSP is already downloaded, and init has been entered again,
9503          * there's only two reasons for it. One, the codec has awaken from a
9504          * suspended state, and in that case dspload_is_loaded will return
9505          * false, and the init will be ran again. The other reason it gets
9506          * re entered is on startup for some reason it triggers a suspend and
9507          * resume state. In this case, it will check if the DSP is downloaded,
9508          * and not run the init function again. For codecs using alt_functions,
9509          * it will check if the DSP is loaded properly.
9510          */
9511         if (spec->dsp_state == DSP_DOWNLOADED) {
9512                 dsp_loaded = dspload_is_loaded(codec);
9513                 if (!dsp_loaded) {
9514                         spec->dsp_reload = true;
9515                         spec->dsp_state = DSP_DOWNLOAD_INIT;
9516                 } else {
9517                         if (ca0132_quirk(spec) == QUIRK_SBZ)
9518                                 sbz_dsp_startup_check(codec);
9519                         return 0;
9520                 }
9521         }
9522
9523         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9524                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9525         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9526
9527         if (ca0132_use_pci_mmio(spec))
9528                 ca0132_mmio_init(codec);
9529
9530         snd_hda_power_up_pm(codec);
9531
9532         if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9533                 ae5_register_set(codec);
9534
9535         ca0132_init_params(codec);
9536         ca0132_init_flags(codec);
9537
9538         snd_hda_sequence_write(codec, spec->base_init_verbs);
9539
9540         if (ca0132_use_alt_functions(spec))
9541                 ca0132_alt_init(codec);
9542
9543         ca0132_download_dsp(codec);
9544
9545         ca0132_refresh_widget_caps(codec);
9546
9547         switch (ca0132_quirk(spec)) {
9548         case QUIRK_R3DI:
9549         case QUIRK_R3D:
9550                 r3d_setup_defaults(codec);
9551                 break;
9552         case QUIRK_SBZ:
9553         case QUIRK_ZXR:
9554                 sbz_setup_defaults(codec);
9555                 break;
9556         case QUIRK_AE5:
9557                 ae5_setup_defaults(codec);
9558                 break;
9559         case QUIRK_AE7:
9560                 ae7_setup_defaults(codec);
9561                 break;
9562         default:
9563                 ca0132_setup_defaults(codec);
9564                 ca0132_init_analog_mic2(codec);
9565                 ca0132_init_dmic(codec);
9566                 break;
9567         }
9568
9569         for (i = 0; i < spec->num_outputs; i++)
9570                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9571
9572         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9573
9574         for (i = 0; i < spec->num_inputs; i++)
9575                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9576
9577         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9578
9579         if (!ca0132_use_alt_functions(spec)) {
9580                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9581                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9582                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9583                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9584                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9585         }
9586
9587         if (ca0132_quirk(spec) == QUIRK_SBZ)
9588                 ca0132_gpio_setup(codec);
9589
9590         snd_hda_sequence_write(codec, spec->spec_init_verbs);
9591         if (ca0132_use_alt_functions(spec)) {
9592                 ca0132_alt_select_out(codec);
9593                 ca0132_alt_select_in(codec);
9594         } else {
9595                 ca0132_select_out(codec);
9596                 ca0132_select_mic(codec);
9597         }
9598
9599         snd_hda_jack_report_sync(codec);
9600
9601         /*
9602          * Re set the PlayEnhancement switch on a resume event, because the
9603          * controls will not be reloaded.
9604          */
9605         if (spec->dsp_reload) {
9606                 spec->dsp_reload = false;
9607                 ca0132_pe_switch_set(codec);
9608         }
9609
9610         snd_hda_power_down_pm(codec);
9611
9612         return 0;
9613 }
9614
9615 static int dbpro_init(struct hda_codec *codec)
9616 {
9617         struct ca0132_spec *spec = codec->spec;
9618         struct auto_pin_cfg *cfg = &spec->autocfg;
9619         unsigned int i;
9620
9621         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9622         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9623
9624         for (i = 0; i < spec->num_inputs; i++)
9625                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9626
9627         return 0;
9628 }
9629
9630 static void ca0132_free(struct hda_codec *codec)
9631 {
9632         struct ca0132_spec *spec = codec->spec;
9633
9634         cancel_delayed_work_sync(&spec->unsol_hp_work);
9635         snd_hda_power_up(codec);
9636         switch (ca0132_quirk(spec)) {
9637         case QUIRK_SBZ:
9638                 sbz_exit_chip(codec);
9639                 break;
9640         case QUIRK_ZXR:
9641                 zxr_exit_chip(codec);
9642                 break;
9643         case QUIRK_R3D:
9644                 r3d_exit_chip(codec);
9645                 break;
9646         case QUIRK_AE5:
9647                 ae5_exit_chip(codec);
9648                 break;
9649         case QUIRK_AE7:
9650                 ae7_exit_chip(codec);
9651                 break;
9652         case QUIRK_R3DI:
9653                 r3di_gpio_shutdown(codec);
9654                 break;
9655         default:
9656                 break;
9657         }
9658
9659         snd_hda_sequence_write(codec, spec->base_exit_verbs);
9660         ca0132_exit_chip(codec);
9661
9662         snd_hda_power_down(codec);
9663 #ifdef CONFIG_PCI
9664         if (spec->mem_base)
9665                 pci_iounmap(codec->bus->pci, spec->mem_base);
9666 #endif
9667         kfree(spec->spec_init_verbs);
9668         kfree(codec->spec);
9669 }
9670
9671 static void dbpro_free(struct hda_codec *codec)
9672 {
9673         struct ca0132_spec *spec = codec->spec;
9674
9675         zxr_dbpro_power_state_shutdown(codec);
9676
9677         kfree(spec->spec_init_verbs);
9678         kfree(codec->spec);
9679 }
9680
9681 #ifdef CONFIG_PM
9682 static int ca0132_suspend(struct hda_codec *codec)
9683 {
9684         struct ca0132_spec *spec = codec->spec;
9685
9686         cancel_delayed_work_sync(&spec->unsol_hp_work);
9687         return 0;
9688 }
9689 #endif
9690
9691 static const struct hda_codec_ops ca0132_patch_ops = {
9692         .build_controls = ca0132_build_controls,
9693         .build_pcms = ca0132_build_pcms,
9694         .init = ca0132_init,
9695         .free = ca0132_free,
9696         .unsol_event = snd_hda_jack_unsol_event,
9697 #ifdef CONFIG_PM
9698         .suspend = ca0132_suspend,
9699 #endif
9700 };
9701
9702 static const struct hda_codec_ops dbpro_patch_ops = {
9703         .build_controls = dbpro_build_controls,
9704         .build_pcms = dbpro_build_pcms,
9705         .init = dbpro_init,
9706         .free = dbpro_free,
9707 };
9708
9709 static void ca0132_config(struct hda_codec *codec)
9710 {
9711         struct ca0132_spec *spec = codec->spec;
9712
9713         spec->dacs[0] = 0x2;
9714         spec->dacs[1] = 0x3;
9715         spec->dacs[2] = 0x4;
9716
9717         spec->multiout.dac_nids = spec->dacs;
9718         spec->multiout.num_dacs = 3;
9719
9720         if (!ca0132_use_alt_functions(spec))
9721                 spec->multiout.max_channels = 2;
9722         else
9723                 spec->multiout.max_channels = 6;
9724
9725         switch (ca0132_quirk(spec)) {
9726         case QUIRK_ALIENWARE:
9727                 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9728                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9729                 break;
9730         case QUIRK_SBZ:
9731                 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9732                 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9733                 break;
9734         case QUIRK_ZXR:
9735                 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9736                 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9737                 break;
9738         case QUIRK_R3D:
9739                 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9740                 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9741                 break;
9742         case QUIRK_R3DI:
9743                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9744                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9745                 break;
9746         case QUIRK_AE5:
9747                 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9748                 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9749                 break;
9750         case QUIRK_AE7:
9751                 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9752                 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9753                 break;
9754         default:
9755                 break;
9756         }
9757
9758         switch (ca0132_quirk(spec)) {
9759         case QUIRK_ALIENWARE:
9760                 spec->num_outputs = 2;
9761                 spec->out_pins[0] = 0x0b; /* speaker out */
9762                 spec->out_pins[1] = 0x0f;
9763                 spec->shared_out_nid = 0x2;
9764                 spec->unsol_tag_hp = 0x0f;
9765
9766                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9767                 spec->adcs[1] = 0x8; /* analog mic2 */
9768                 spec->adcs[2] = 0xa; /* what u hear */
9769
9770                 spec->num_inputs = 3;
9771                 spec->input_pins[0] = 0x12;
9772                 spec->input_pins[1] = 0x11;
9773                 spec->input_pins[2] = 0x13;
9774                 spec->shared_mic_nid = 0x7;
9775                 spec->unsol_tag_amic1 = 0x11;
9776                 break;
9777         case QUIRK_SBZ:
9778         case QUIRK_R3D:
9779                 spec->num_outputs = 2;
9780                 spec->out_pins[0] = 0x0B; /* Line out */
9781                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9782                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9783                 spec->out_pins[3] = 0x11; /* Rear surround */
9784                 spec->shared_out_nid = 0x2;
9785                 spec->unsol_tag_hp = spec->out_pins[1];
9786                 spec->unsol_tag_front_hp = spec->out_pins[2];
9787
9788                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9789                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9790                 spec->adcs[2] = 0xa; /* what u hear */
9791
9792                 spec->num_inputs = 2;
9793                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9794                 spec->input_pins[1] = 0x13; /* What U Hear */
9795                 spec->shared_mic_nid = 0x7;
9796                 spec->unsol_tag_amic1 = spec->input_pins[0];
9797
9798                 /* SPDIF I/O */
9799                 spec->dig_out = 0x05;
9800                 spec->multiout.dig_out_nid = spec->dig_out;
9801                 spec->dig_in = 0x09;
9802                 break;
9803         case QUIRK_ZXR:
9804                 spec->num_outputs = 2;
9805                 spec->out_pins[0] = 0x0B; /* Line out */
9806                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9807                 spec->out_pins[2] = 0x10; /* Center/LFE */
9808                 spec->out_pins[3] = 0x11; /* Rear surround */
9809                 spec->shared_out_nid = 0x2;
9810                 spec->unsol_tag_hp = spec->out_pins[1];
9811                 spec->unsol_tag_front_hp = spec->out_pins[2];
9812
9813                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9814                 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9815                 spec->adcs[2] = 0xa; /* what u hear */
9816
9817                 spec->num_inputs = 2;
9818                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9819                 spec->input_pins[1] = 0x13; /* What U Hear */
9820                 spec->shared_mic_nid = 0x7;
9821                 spec->unsol_tag_amic1 = spec->input_pins[0];
9822                 break;
9823         case QUIRK_ZXR_DBPRO:
9824                 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9825
9826                 spec->num_inputs = 1;
9827                 spec->input_pins[0] = 0x11; /* RCA Line-in */
9828
9829                 spec->dig_out = 0x05;
9830                 spec->multiout.dig_out_nid = spec->dig_out;
9831
9832                 spec->dig_in = 0x09;
9833                 break;
9834         case QUIRK_AE5:
9835         case QUIRK_AE7:
9836                 spec->num_outputs = 2;
9837                 spec->out_pins[0] = 0x0B; /* Line out */
9838                 spec->out_pins[1] = 0x11; /* Rear headphone out */
9839                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9840                 spec->out_pins[3] = 0x0F; /* Rear surround */
9841                 spec->shared_out_nid = 0x2;
9842                 spec->unsol_tag_hp = spec->out_pins[1];
9843                 spec->unsol_tag_front_hp = spec->out_pins[2];
9844
9845                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9846                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9847                 spec->adcs[2] = 0xa; /* what u hear */
9848
9849                 spec->num_inputs = 2;
9850                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9851                 spec->input_pins[1] = 0x13; /* What U Hear */
9852                 spec->shared_mic_nid = 0x7;
9853                 spec->unsol_tag_amic1 = spec->input_pins[0];
9854
9855                 /* SPDIF I/O */
9856                 spec->dig_out = 0x05;
9857                 spec->multiout.dig_out_nid = spec->dig_out;
9858                 break;
9859         case QUIRK_R3DI:
9860                 spec->num_outputs = 2;
9861                 spec->out_pins[0] = 0x0B; /* Line out */
9862                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9863                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9864                 spec->out_pins[3] = 0x11; /* Rear surround */
9865                 spec->shared_out_nid = 0x2;
9866                 spec->unsol_tag_hp = spec->out_pins[1];
9867                 spec->unsol_tag_front_hp = spec->out_pins[2];
9868
9869                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9870                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9871                 spec->adcs[2] = 0x0a; /* what u hear */
9872
9873                 spec->num_inputs = 2;
9874                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9875                 spec->input_pins[1] = 0x13; /* What U Hear */
9876                 spec->shared_mic_nid = 0x7;
9877                 spec->unsol_tag_amic1 = spec->input_pins[0];
9878
9879                 /* SPDIF I/O */
9880                 spec->dig_out = 0x05;
9881                 spec->multiout.dig_out_nid = spec->dig_out;
9882                 break;
9883         default:
9884                 spec->num_outputs = 2;
9885                 spec->out_pins[0] = 0x0b; /* speaker out */
9886                 spec->out_pins[1] = 0x10; /* headphone out */
9887                 spec->shared_out_nid = 0x2;
9888                 spec->unsol_tag_hp = spec->out_pins[1];
9889
9890                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9891                 spec->adcs[1] = 0x8; /* analog mic2 */
9892                 spec->adcs[2] = 0xa; /* what u hear */
9893
9894                 spec->num_inputs = 3;
9895                 spec->input_pins[0] = 0x12;
9896                 spec->input_pins[1] = 0x11;
9897                 spec->input_pins[2] = 0x13;
9898                 spec->shared_mic_nid = 0x7;
9899                 spec->unsol_tag_amic1 = spec->input_pins[0];
9900
9901                 /* SPDIF I/O */
9902                 spec->dig_out = 0x05;
9903                 spec->multiout.dig_out_nid = spec->dig_out;
9904                 spec->dig_in = 0x09;
9905                 break;
9906         }
9907 }
9908
9909 static int ca0132_prepare_verbs(struct hda_codec *codec)
9910 {
9911 /* Verbs + terminator (an empty element) */
9912 #define NUM_SPEC_VERBS 2
9913         struct ca0132_spec *spec = codec->spec;
9914
9915         spec->chip_init_verbs = ca0132_init_verbs0;
9916         /*
9917          * Since desktop cards use pci_mmio, this can be used to determine
9918          * whether or not to use these verbs instead of a separate bool.
9919          */
9920         if (ca0132_use_pci_mmio(spec))
9921                 spec->desktop_init_verbs = ca0132_init_verbs1;
9922         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9923                                         sizeof(struct hda_verb),
9924                                         GFP_KERNEL);
9925         if (!spec->spec_init_verbs)
9926                 return -ENOMEM;
9927
9928         /* config EAPD */
9929         spec->spec_init_verbs[0].nid = 0x0b;
9930         spec->spec_init_verbs[0].param = 0x78D;
9931         spec->spec_init_verbs[0].verb = 0x00;
9932
9933         /* Previously commented configuration */
9934         /*
9935         spec->spec_init_verbs[2].nid = 0x0b;
9936         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9937         spec->spec_init_verbs[2].verb = 0x02;
9938
9939         spec->spec_init_verbs[3].nid = 0x10;
9940         spec->spec_init_verbs[3].param = 0x78D;
9941         spec->spec_init_verbs[3].verb = 0x02;
9942
9943         spec->spec_init_verbs[4].nid = 0x10;
9944         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9945         spec->spec_init_verbs[4].verb = 0x02;
9946         */
9947
9948         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9949         return 0;
9950 }
9951
9952 /*
9953  * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9954  * Sound Blaster Z cards. However, they have different HDA codec subsystem
9955  * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9956  * daughter boards ID.
9957  */
9958 static void sbz_detect_quirk(struct hda_codec *codec)
9959 {
9960         struct ca0132_spec *spec = codec->spec;
9961
9962         switch (codec->core.subsystem_id) {
9963         case 0x11020033:
9964                 spec->quirk = QUIRK_ZXR;
9965                 break;
9966         case 0x1102003f:
9967                 spec->quirk = QUIRK_ZXR_DBPRO;
9968                 break;
9969         default:
9970                 spec->quirk = QUIRK_SBZ;
9971                 break;
9972         }
9973 }
9974
9975 static int patch_ca0132(struct hda_codec *codec)
9976 {
9977         struct ca0132_spec *spec;
9978         int err;
9979         const struct snd_pci_quirk *quirk;
9980
9981         codec_dbg(codec, "patch_ca0132\n");
9982
9983         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9984         if (!spec)
9985                 return -ENOMEM;
9986         codec->spec = spec;
9987         spec->codec = codec;
9988
9989         /* Detect codec quirk */
9990         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9991         if (quirk)
9992                 spec->quirk = quirk->value;
9993         else
9994                 spec->quirk = QUIRK_NONE;
9995         if (ca0132_quirk(spec) == QUIRK_SBZ)
9996                 sbz_detect_quirk(codec);
9997
9998         if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9999                 codec->patch_ops = dbpro_patch_ops;
10000         else
10001                 codec->patch_ops = ca0132_patch_ops;
10002
10003         codec->pcm_format_first = 1;
10004         codec->no_sticky_stream = 1;
10005
10006
10007         spec->dsp_state = DSP_DOWNLOAD_INIT;
10008         spec->num_mixers = 1;
10009
10010         /* Set which mixers each quirk uses. */
10011         switch (ca0132_quirk(spec)) {
10012         case QUIRK_SBZ:
10013                 spec->mixers[0] = desktop_mixer;
10014                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10015                 break;
10016         case QUIRK_ZXR:
10017                 spec->mixers[0] = desktop_mixer;
10018                 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10019                 break;
10020         case QUIRK_ZXR_DBPRO:
10021                 break;
10022         case QUIRK_R3D:
10023                 spec->mixers[0] = desktop_mixer;
10024                 snd_hda_codec_set_name(codec, "Recon3D");
10025                 break;
10026         case QUIRK_R3DI:
10027                 spec->mixers[0] = r3di_mixer;
10028                 snd_hda_codec_set_name(codec, "Recon3Di");
10029                 break;
10030         case QUIRK_AE5:
10031                 spec->mixers[0] = desktop_mixer;
10032                 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10033                 break;
10034         case QUIRK_AE7:
10035                 spec->mixers[0] = desktop_mixer;
10036                 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10037                 break;
10038         default:
10039                 spec->mixers[0] = ca0132_mixer;
10040                 break;
10041         }
10042
10043         /* Setup whether or not to use alt functions/controls/pci_mmio */
10044         switch (ca0132_quirk(spec)) {
10045         case QUIRK_SBZ:
10046         case QUIRK_R3D:
10047         case QUIRK_AE5:
10048         case QUIRK_AE7:
10049         case QUIRK_ZXR:
10050                 spec->use_alt_controls = true;
10051                 spec->use_alt_functions = true;
10052                 spec->use_pci_mmio = true;
10053                 break;
10054         case QUIRK_R3DI:
10055                 spec->use_alt_controls = true;
10056                 spec->use_alt_functions = true;
10057                 spec->use_pci_mmio = false;
10058                 break;
10059         default:
10060                 spec->use_alt_controls = false;
10061                 spec->use_alt_functions = false;
10062                 spec->use_pci_mmio = false;
10063                 break;
10064         }
10065
10066 #ifdef CONFIG_PCI
10067         if (spec->use_pci_mmio) {
10068                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10069                 if (spec->mem_base == NULL) {
10070                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10071                         spec->quirk = QUIRK_NONE;
10072                 }
10073         }
10074 #endif
10075
10076         spec->base_init_verbs = ca0132_base_init_verbs;
10077         spec->base_exit_verbs = ca0132_base_exit_verbs;
10078
10079         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10080
10081         ca0132_init_chip(codec);
10082
10083         ca0132_config(codec);
10084
10085         err = ca0132_prepare_verbs(codec);
10086         if (err < 0)
10087                 goto error;
10088
10089         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10090         if (err < 0)
10091                 goto error;
10092
10093         ca0132_setup_unsol(codec);
10094
10095         return 0;
10096
10097  error:
10098         ca0132_free(codec);
10099         return err;
10100 }
10101
10102 /*
10103  * patch entries
10104  */
10105 static const struct hda_device_id snd_hda_id_ca0132[] = {
10106         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
10107         {} /* terminator */
10108 };
10109 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10110
10111 MODULE_LICENSE("GPL");
10112 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10113
10114 static struct hda_codec_driver ca0132_driver = {
10115         .id = snd_hda_id_ca0132,
10116 };
10117
10118 module_hda_codec_driver(ca0132_driver);