sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative CA0132 chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/mutex.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/io.h>
  33 #include <linux/pci.h>
  34 #include <asm/io.h>
  35 #include <sound/core.h>
  36 #include "hda_codec.h"
  37 #include "hda_local.h"
  38 #include "hda_auto_parser.h"
  39 #include "hda_jack.h"
  40
  41 #include "ca0132_regs.h"
  42
  43 /* Enable this to see controls for tuning purpose. */
  44 /*#define ENABLE_TUNING_CONTROLS*/
  45
  46 #ifdef ENABLE_TUNING_CONTROLS
  47 #include <sound/tlv.h>
  48 #endif
  49
  50 #define FLOAT_ZERO      0x00000000
  51 #define FLOAT_ONE       0x3f800000
  52 #define FLOAT_TWO       0x40000000
  53 #define FLOAT_THREE     0x40400000
  54 #define FLOAT_EIGHT     0x41000000
  55 #define FLOAT_MINUS_5   0xc0a00000
  56
  57 #define UNSOL_TAG_DSP   0x16
  58
  59 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  60 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  61
  62 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  63 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  64 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  65
  66 #define MASTERCONTROL                           0x80
  67 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  68 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  69
  70 #define WIDGET_CHIP_CTRL      0x15
  71 #define WIDGET_DSP_CTRL       0x16
  72
  73 #define MEM_CONNID_MICIN1     3
  74 #define MEM_CONNID_MICIN2     5
  75 #define MEM_CONNID_MICOUT1    12
  76 #define MEM_CONNID_MICOUT2    14
  77 #define MEM_CONNID_WUH        10
  78 #define MEM_CONNID_DSP        16
  79 #define MEM_CONNID_DMIC       100
  80
  81 #define SCP_SET    0
  82 #define SCP_GET    1
  83
  84 #define EFX_FILE   "/*(DEBLOBBED)*/"
  85 #define SBZ_EFX_FILE   "/*(DEBLOBBED)*/"
  86 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  87
  88 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  89 /*(DEBLOBBED)*/
  90 #endif
  91
  92 static const char *const dirstr[2] = { "Playback", "Capture" };
  93
  94 #define NUM_OF_OUTPUTS 3
  95 enum {
  96         SPEAKER_OUT,
  97         HEADPHONE_OUT,
  98         SURROUND_OUT
  99 };
 100
 101 enum {
 102         DIGITAL_MIC,
 103         LINE_MIC_IN
 104 };
 105
 106 /* Strings for Input Source Enum Control */
 107 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
 108 #define IN_SRC_NUM_OF_INPUTS 3
 109 enum {
 110         REAR_MIC,
 111         REAR_LINE_IN,
 112         FRONT_MIC,
 113 };
 114
 115 enum {
 116 #define VNODE_START_NID    0x80
 117         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 118         VNID_MIC,
 119         VNID_HP_SEL,
 120         VNID_AMIC1_SEL,
 121         VNID_HP_ASEL,
 122         VNID_AMIC1_ASEL,
 123         VNODE_END_NID,
 124 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 125
 126 #define EFFECT_START_NID    0x90
 127 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 128         SURROUND = OUT_EFFECT_START_NID,
 129         CRYSTALIZER,
 130         DIALOG_PLUS,
 131         SMART_VOLUME,
 132         X_BASS,
 133         EQUALIZER,
 134         OUT_EFFECT_END_NID,
 135 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 136
 137 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 138         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 139         VOICE_FOCUS,
 140         MIC_SVM,
 141         NOISE_REDUCTION,
 142         IN_EFFECT_END_NID,
 143 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 144
 145         VOICEFX = IN_EFFECT_END_NID,
 146         PLAY_ENHANCEMENT,
 147         CRYSTAL_VOICE,
 148         EFFECT_END_NID,
 149         OUTPUT_SOURCE_ENUM,
 150         INPUT_SOURCE_ENUM,
 151         XBASS_XOVER,
 152         EQ_PRESET_ENUM,
 153         SMART_VOLUME_ENUM,
 154         MIC_BOOST_ENUM
 155 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 156 };
 157
 158 /* Effects values size*/
 159 #define EFFECT_VALS_MAX_COUNT 12
 160
 161 /*
 162  * Default values for the effect slider controls, they are in order of their
 163  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 164  * X-bass.
 165  */
 166 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 167 /* Amount of effect level sliders for ca0132_alt controls. */
 168 #define EFFECT_LEVEL_SLIDERS 5
 169
 170 /* Latency introduced by DSP blocks in milliseconds. */
 171 #define DSP_CAPTURE_INIT_LATENCY        0
 172 #define DSP_CRYSTAL_VOICE_LATENCY       124
 173 #define DSP_PLAYBACK_INIT_LATENCY       13
 174 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 175 #define DSP_SPEAKER_OUT_LATENCY         7
 176
 177 struct ct_effect {
 178         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 179         hda_nid_t nid;
 180         int mid; /*effect module ID*/
 181         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 182         int direct; /* 0:output; 1:input*/
 183         int params; /* number of default non-on/off params */
 184         /*effect default values, 1st is on/off. */
 185         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 186 };
 187
 188 #define EFX_DIR_OUT 0
 189 #define EFX_DIR_IN  1
 190
 191 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 192         { .name = "Surround",
 193           .nid = SURROUND,
 194           .mid = 0x96,
 195           .reqs = {0, 1},
 196           .direct = EFX_DIR_OUT,
 197           .params = 1,
 198           .def_vals = {0x3F800000, 0x3F2B851F}
 199         },
 200         { .name = "Crystalizer",
 201           .nid = CRYSTALIZER,
 202           .mid = 0x96,
 203           .reqs = {7, 8},
 204           .direct = EFX_DIR_OUT,
 205           .params = 1,
 206           .def_vals = {0x3F800000, 0x3F266666}
 207         },
 208         { .name = "Dialog Plus",
 209           .nid = DIALOG_PLUS,
 210           .mid = 0x96,
 211           .reqs = {2, 3},
 212           .direct = EFX_DIR_OUT,
 213           .params = 1,
 214           .def_vals = {0x00000000, 0x3F000000}
 215         },
 216         { .name = "Smart Volume",
 217           .nid = SMART_VOLUME,
 218           .mid = 0x96,
 219           .reqs = {4, 5, 6},
 220           .direct = EFX_DIR_OUT,
 221           .params = 2,
 222           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 223         },
 224         { .name = "X-Bass",
 225           .nid = X_BASS,
 226           .mid = 0x96,
 227           .reqs = {24, 23, 25},
 228           .direct = EFX_DIR_OUT,
 229           .params = 2,
 230           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 231         },
 232         { .name = "Equalizer",
 233           .nid = EQUALIZER,
 234           .mid = 0x96,
 235           .reqs = {9, 10, 11, 12, 13, 14,
 236                         15, 16, 17, 18, 19, 20},
 237           .direct = EFX_DIR_OUT,
 238           .params = 11,
 239           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 240                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 241                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 242         },
 243         { .name = "Echo Cancellation",
 244           .nid = ECHO_CANCELLATION,
 245           .mid = 0x95,
 246           .reqs = {0, 1, 2, 3},
 247           .direct = EFX_DIR_IN,
 248           .params = 3,
 249           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 250         },
 251         { .name = "Voice Focus",
 252           .nid = VOICE_FOCUS,
 253           .mid = 0x95,
 254           .reqs = {6, 7, 8, 9},
 255           .direct = EFX_DIR_IN,
 256           .params = 3,
 257           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 258         },
 259         { .name = "Mic SVM",
 260           .nid = MIC_SVM,
 261           .mid = 0x95,
 262           .reqs = {44, 45},
 263           .direct = EFX_DIR_IN,
 264           .params = 1,
 265           .def_vals = {0x00000000, 0x3F3D70A4}
 266         },
 267         { .name = "Noise Reduction",
 268           .nid = NOISE_REDUCTION,
 269           .mid = 0x95,
 270           .reqs = {4, 5},
 271           .direct = EFX_DIR_IN,
 272           .params = 1,
 273           .def_vals = {0x3F800000, 0x3F000000}
 274         },
 275         { .name = "VoiceFX",
 276           .nid = VOICEFX,
 277           .mid = 0x95,
 278           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 279           .direct = EFX_DIR_IN,
 280           .params = 8,
 281           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 282                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 283                        0x00000000}
 284         }
 285 };
 286
 287 /* Tuning controls */
 288 #ifdef ENABLE_TUNING_CONTROLS
 289
 290 enum {
 291 #define TUNING_CTL_START_NID  0xC0
 292         WEDGE_ANGLE = TUNING_CTL_START_NID,
 293         SVM_LEVEL,
 294         EQUALIZER_BAND_0,
 295         EQUALIZER_BAND_1,
 296         EQUALIZER_BAND_2,
 297         EQUALIZER_BAND_3,
 298         EQUALIZER_BAND_4,
 299         EQUALIZER_BAND_5,
 300         EQUALIZER_BAND_6,
 301         EQUALIZER_BAND_7,
 302         EQUALIZER_BAND_8,
 303         EQUALIZER_BAND_9,
 304         TUNING_CTL_END_NID
 305 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 306 };
 307
 308 struct ct_tuning_ctl {
 309         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 310         hda_nid_t parent_nid;
 311         hda_nid_t nid;
 312         int mid; /*effect module ID*/
 313         int req; /*effect module request*/
 314         int direct; /* 0:output; 1:input*/
 315         unsigned int def_val;/*effect default values*/
 316 };
 317
 318 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 319         { .name = "Wedge Angle",
 320           .parent_nid = VOICE_FOCUS,
 321           .nid = WEDGE_ANGLE,
 322           .mid = 0x95,
 323           .req = 8,
 324           .direct = EFX_DIR_IN,
 325           .def_val = 0x41F00000
 326         },
 327         { .name = "SVM Level",
 328           .parent_nid = MIC_SVM,
 329           .nid = SVM_LEVEL,
 330           .mid = 0x95,
 331           .req = 45,
 332           .direct = EFX_DIR_IN,
 333           .def_val = 0x3F3D70A4
 334         },
 335         { .name = "EQ Band0",
 336           .parent_nid = EQUALIZER,
 337           .nid = EQUALIZER_BAND_0,
 338           .mid = 0x96,
 339           .req = 11,
 340           .direct = EFX_DIR_OUT,
 341           .def_val = 0x00000000
 342         },
 343         { .name = "EQ Band1",
 344           .parent_nid = EQUALIZER,
 345           .nid = EQUALIZER_BAND_1,
 346           .mid = 0x96,
 347           .req = 12,
 348           .direct = EFX_DIR_OUT,
 349           .def_val = 0x00000000
 350         },
 351         { .name = "EQ Band2",
 352           .parent_nid = EQUALIZER,
 353           .nid = EQUALIZER_BAND_2,
 354           .mid = 0x96,
 355           .req = 13,
 356           .direct = EFX_DIR_OUT,
 357           .def_val = 0x00000000
 358         },
 359         { .name = "EQ Band3",
 360           .parent_nid = EQUALIZER,
 361           .nid = EQUALIZER_BAND_3,
 362           .mid = 0x96,
 363           .req = 14,
 364           .direct = EFX_DIR_OUT,
 365           .def_val = 0x00000000
 366         },
 367         { .name = "EQ Band4",
 368           .parent_nid = EQUALIZER,
 369           .nid = EQUALIZER_BAND_4,
 370           .mid = 0x96,
 371           .req = 15,
 372           .direct = EFX_DIR_OUT,
 373           .def_val = 0x00000000
 374         },
 375         { .name = "EQ Band5",
 376           .parent_nid = EQUALIZER,
 377           .nid = EQUALIZER_BAND_5,
 378           .mid = 0x96,
 379           .req = 16,
 380           .direct = EFX_DIR_OUT,
 381           .def_val = 0x00000000
 382         },
 383         { .name = "EQ Band6",
 384           .parent_nid = EQUALIZER,
 385           .nid = EQUALIZER_BAND_6,
 386           .mid = 0x96,
 387           .req = 17,
 388           .direct = EFX_DIR_OUT,
 389           .def_val = 0x00000000
 390         },
 391         { .name = "EQ Band7",
 392           .parent_nid = EQUALIZER,
 393           .nid = EQUALIZER_BAND_7,
 394           .mid = 0x96,
 395           .req = 18,
 396           .direct = EFX_DIR_OUT,
 397           .def_val = 0x00000000
 398         },
 399         { .name = "EQ Band8",
 400           .parent_nid = EQUALIZER,
 401           .nid = EQUALIZER_BAND_8,
 402           .mid = 0x96,
 403           .req = 19,
 404           .direct = EFX_DIR_OUT,
 405           .def_val = 0x00000000
 406         },
 407         { .name = "EQ Band9",
 408           .parent_nid = EQUALIZER,
 409           .nid = EQUALIZER_BAND_9,
 410           .mid = 0x96,
 411           .req = 20,
 412           .direct = EFX_DIR_OUT,
 413           .def_val = 0x00000000
 414         }
 415 };
 416 #endif
 417
 418 /* Voice FX Presets */
 419 #define VOICEFX_MAX_PARAM_COUNT 9
 420
 421 struct ct_voicefx {
 422         char *name;
 423         hda_nid_t nid;
 424         int mid;
 425         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 426 };
 427
 428 struct ct_voicefx_preset {
 429         char *name; /*preset name*/
 430         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 431 };
 432
 433 static const struct ct_voicefx ca0132_voicefx = {
 434         .name = "VoiceFX Capture Switch",
 435         .nid = VOICEFX,
 436         .mid = 0x95,
 437         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 438 };
 439
 440 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 441         { .name = "Neutral",
 442           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 443                     0x44FA0000, 0x3F800000, 0x3F800000,
 444                     0x3F800000, 0x00000000, 0x00000000 }
 445         },
 446         { .name = "Female2Male",
 447           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 448                     0x44FA0000, 0x3F19999A, 0x3F866666,
 449                     0x3F800000, 0x00000000, 0x00000000 }
 450         },
 451         { .name = "Male2Female",
 452           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 453                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 454                     0x3F800000, 0x00000000, 0x00000000 }
 455         },
 456         { .name = "ScrappyKid",
 457           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 458                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 459                     0x3F800000, 0x00000000, 0x00000000 }
 460         },
 461         { .name = "Elderly",
 462           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 463                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 464                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 465         },
 466         { .name = "Orc",
 467           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 468                     0x45098000, 0x3F266666, 0x3FC00000,
 469                     0x3F800000, 0x00000000, 0x00000000 }
 470         },
 471         { .name = "Elf",
 472           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 473                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 474                     0x3F800000, 0x00000000, 0x00000000 }
 475         },
 476         { .name = "Dwarf",
 477           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 478                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 479                     0x3F800000, 0x00000000, 0x00000000 }
 480         },
 481         { .name = "AlienBrute",
 482           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 483                     0x451F6000, 0x3F266666, 0x3FA7D945,
 484                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 485         },
 486         { .name = "Robot",
 487           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 488                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 489                     0xBC07010E, 0x00000000, 0x00000000 }
 490         },
 491         { .name = "Marine",
 492           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 493                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 494                     0x3F0A3D71, 0x00000000, 0x00000000 }
 495         },
 496         { .name = "Emo",
 497           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 498                     0x44FA0000, 0x3F800000, 0x3F800000,
 499                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 500         },
 501         { .name = "DeepVoice",
 502           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 503                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 504                     0x3F800000, 0x00000000, 0x00000000 }
 505         },
 506         { .name = "Munchkin",
 507           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 508                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 509                     0x3F800000, 0x00000000, 0x00000000 }
 510         }
 511 };
 512
 513 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 514
 515 #define EQ_PRESET_MAX_PARAM_COUNT 11
 516
 517 struct ct_eq {
 518         char *name;
 519         hda_nid_t nid;
 520         int mid;
 521         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 522 };
 523
 524 struct ct_eq_preset {
 525         char *name; /*preset name*/
 526         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 527 };
 528
 529 static const struct ct_eq ca0132_alt_eq_enum = {
 530         .name = "FX: Equalizer Preset Switch",
 531         .nid = EQ_PRESET_ENUM,
 532         .mid = 0x96,
 533         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 534 };
 535
 536
 537 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 538         { .name = "Flat",
 539          .vals = { 0x00000000, 0x00000000, 0x00000000,
 540                    0x00000000, 0x00000000, 0x00000000,
 541                    0x00000000, 0x00000000, 0x00000000,
 542                    0x00000000, 0x00000000            }
 543         },
 544         { .name = "Acoustic",
 545          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 546                    0x40000000, 0x00000000, 0x00000000,
 547                    0x00000000, 0x00000000, 0x40000000,
 548                    0x40000000, 0x40000000            }
 549         },
 550         { .name = "Classical",
 551          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 552                    0x40C00000, 0x40466666, 0x00000000,
 553                    0x00000000, 0x00000000, 0x00000000,
 554                    0x40466666, 0x40466666            }
 555         },
 556         { .name = "Country",
 557          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 558                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 559                    0x00000000, 0x00000000, 0x40000000,
 560                    0x40466666, 0x40800000            }
 561         },
 562         { .name = "Dance",
 563          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 564                    0x40466666, 0x40866666, 0xBF99999A,
 565                    0xBF99999A, 0x00000000, 0x00000000,
 566                    0x40800000, 0x40800000            }
 567         },
 568         { .name = "Jazz",
 569          .vals = { 0x00000000, 0x00000000, 0x00000000,
 570                    0x3F8CCCCD, 0x40800000, 0x40800000,
 571                    0x40800000, 0x00000000, 0x3F8CCCCD,
 572                    0x40466666, 0x40466666            }
 573         },
 574         { .name = "New Age",
 575          .vals = { 0x00000000, 0x00000000, 0x40000000,
 576                    0x40000000, 0x00000000, 0x00000000,
 577                    0x00000000, 0x3F8CCCCD, 0x40000000,
 578                    0x40000000, 0x40000000            }
 579         },
 580         { .name = "Pop",
 581          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 582                    0x40000000, 0x40000000, 0x00000000,
 583                    0xBF99999A, 0xBF99999A, 0x00000000,
 584                    0x40466666, 0x40C00000            }
 585         },
 586         { .name = "Rock",
 587          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 588                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 589                    0xBF99999A, 0x00000000, 0x00000000,
 590                    0x40800000, 0x40800000            }
 591         },
 592         { .name = "Vocal",
 593          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 594                    0xBF99999A, 0x00000000, 0x40466666,
 595                    0x40800000, 0x40466666, 0x00000000,
 596                    0x00000000, 0x3F8CCCCD            }
 597         }
 598 };
 599
 600 /* DSP command sequences for ca0132_alt_select_out */
 601 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
 602 struct ca0132_alt_out_set {
 603         char *name; /*preset name*/
 604         unsigned char commands;
 605         unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
 606         unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
 607         unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
 608 };
 609
 610 static const struct ca0132_alt_out_set alt_out_presets[] = {
 611         { .name = "Line Out",
 612           .commands = 7,
 613           .mids = { 0x96, 0x96, 0x96, 0x8F,
 614                     0x96, 0x96, 0x96 },
 615           .reqs = { 0x19, 0x17, 0x18, 0x01,
 616                     0x1F, 0x15, 0x3A },
 617           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 618                     0x00000000, 0x00000000, 0x00000000,
 619                     0x00000000 }
 620         },
 621         { .name = "Headphone",
 622           .commands = 7,
 623           .mids = { 0x96, 0x96, 0x96, 0x8F,
 624                     0x96, 0x96, 0x96 },
 625           .reqs = { 0x19, 0x17, 0x18, 0x01,
 626                     0x1F, 0x15, 0x3A },
 627           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 628                     0x00000000, 0x00000000, 0x00000000,
 629                     0x00000000 }
 630         },
 631         { .name = "Surround",
 632           .commands = 8,
 633           .mids = { 0x96, 0x8F, 0x96, 0x96,
 634                     0x96, 0x96, 0x96, 0x96 },
 635           .reqs = { 0x18, 0x01, 0x1F, 0x15,
 636                     0x3A, 0x1A, 0x1B, 0x1C },
 637           .vals = { 0x00000000, 0x00000000, 0x00000000,
 638                     0x00000000, 0x00000000, 0x00000000,
 639                     0x00000000, 0x00000000 }
 640         }
 641 };
 642
 643 /*
 644  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 645  * and I don't know what the third req is, but it's always zero. I assume it's
 646  * some sort of update or set command to tell the DSP there's new volume info.
 647  */
 648 #define DSP_VOL_OUT 0
 649 #define DSP_VOL_IN  1
 650
 651 struct ct_dsp_volume_ctl {
 652         hda_nid_t vnid;
 653         int mid; /* module ID*/
 654         unsigned int reqs[3]; /* scp req ID */
 655 };
 656
 657 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 658         { .vnid = VNID_SPK,
 659           .mid = 0x32,
 660           .reqs = {3, 4, 2}
 661         },
 662         { .vnid = VNID_MIC,
 663           .mid = 0x37,
 664           .reqs = {2, 3, 1}
 665         }
 666 };
 667
 668 enum hda_cmd_vendor_io {
 669         /* for DspIO node */
 670         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 671         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 672
 673         VENDOR_DSPIO_STATUS                  = 0xF01,
 674         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 675         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 676         VENDOR_DSPIO_DSP_INIT                = 0x703,
 677         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 678         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 679
 680         /* for ChipIO node */
 681         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 682         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 683         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 684         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 685         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 686
 687         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 688         VENDOR_CHIPIO_STATUS                 = 0xF01,
 689         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 690         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 691
 692         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 693         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 694
 695         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 696         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 697
 698         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 699         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 700         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 701         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 702         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 703         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 704         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 705         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 706
 707         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 708         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 709         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 710         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 711
 712         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 713         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 714         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 715         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 716
 717         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 718         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 719         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 720         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 721         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 722         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 723
 724         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 725 };
 726
 727 /*
 728  *  Control flag IDs
 729  */
 730 enum control_flag_id {
 731         /* Connection manager stream setup is bypassed/enabled */
 732         CONTROL_FLAG_C_MGR                  = 0,
 733         /* DSP DMA is bypassed/enabled */
 734         CONTROL_FLAG_DMA                    = 1,
 735         /* 8051 'idle' mode is disabled/enabled */
 736         CONTROL_FLAG_IDLE_ENABLE            = 2,
 737         /* Tracker for the SPDIF-in path is bypassed/enabled */
 738         CONTROL_FLAG_TRACKER                = 3,
 739         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 740         CONTROL_FLAG_SPDIF2OUT              = 4,
 741         /* Digital Microphone is disabled/enabled */
 742         CONTROL_FLAG_DMIC                   = 5,
 743         /* ADC_B rate is 48 kHz/96 kHz */
 744         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 745         /* ADC_C rate is 48 kHz/96 kHz */
 746         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 747         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 748         CONTROL_FLAG_DAC_96KHZ              = 8,
 749         /* DSP rate is 48 kHz/96 kHz */
 750         CONTROL_FLAG_DSP_96KHZ              = 9,
 751         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 752         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 753         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 754         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 755         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 756         CONTROL_FLAG_DECODE_LOOP            = 12,
 757         /* De-emphasis filter on DAC-1 disabled/enabled */
 758         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 759         /* De-emphasis filter on DAC-2 disabled/enabled */
 760         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 761         /* De-emphasis filter on DAC-3 disabled/enabled */
 762         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 763         /* High-pass filter on ADC_B disabled/enabled */
 764         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 765         /* High-pass filter on ADC_C disabled/enabled */
 766         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 767         /* Common mode on Port_A disabled/enabled */
 768         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 769         /* Common mode on Port_D disabled/enabled */
 770         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 771         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 772         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 773         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 774         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 775         /* ASI rate is 48kHz/96kHz */
 776         CONTROL_FLAG_ASI_96KHZ              = 22,
 777         /* DAC power settings able to control attached ports no/yes */
 778         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 779         /* Clock Stop OK reporting is disabled/enabled */
 780         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 781         /* Number of control flags */
 782         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 783 };
 784
 785 /*
 786  * Control parameter IDs
 787  */
 788 enum control_param_id {
 789         /* 0: None, 1: Mic1In*/
 790         CONTROL_PARAM_VIP_SOURCE               = 1,
 791         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 792         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 793         /* Port A output stage gain setting to use when 16 Ohm output
 794          * impedance is selected*/
 795         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 796         /* Port D output stage gain setting to use when 16 Ohm output
 797          * impedance is selected*/
 798         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 799
 800         /* Stream Control */
 801
 802         /* Select stream with the given ID */
 803         CONTROL_PARAM_STREAM_ID                = 24,
 804         /* Source connection point for the selected stream */
 805         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 806         /* Destination connection point for the selected stream */
 807         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 808         /* Number of audio channels in the selected stream */
 809         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 810         /*Enable control for the selected stream */
 811         CONTROL_PARAM_STREAM_CONTROL           = 28,
 812
 813         /* Connection Point Control */
 814
 815         /* Select connection point with the given ID */
 816         CONTROL_PARAM_CONN_POINT_ID            = 29,
 817         /* Connection point sample rate */
 818         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 819
 820         /* Node Control */
 821
 822         /* Select HDA node with the given ID */
 823         CONTROL_PARAM_NODE_ID                  = 31
 824 };
 825
 826 /*
 827  *  Dsp Io Status codes
 828  */
 829 enum hda_vendor_status_dspio {
 830         /* Success */
 831         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 832         /* Busy, unable to accept new command, the host must retry */
 833         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 834         /* SCP command queue is full */
 835         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 836         /* SCP response queue is empty */
 837         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 838 };
 839
 840 /*
 841  *  Chip Io Status codes
 842  */
 843 enum hda_vendor_status_chipio {
 844         /* Success */
 845         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 846         /* Busy, unable to accept new command, the host must retry */
 847         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 848 };
 849
 850 /*
 851  *  CA0132 sample rate
 852  */
 853 enum ca0132_sample_rate {
 854         SR_6_000        = 0x00,
 855         SR_8_000        = 0x01,
 856         SR_9_600        = 0x02,
 857         SR_11_025       = 0x03,
 858         SR_16_000       = 0x04,
 859         SR_22_050       = 0x05,
 860         SR_24_000       = 0x06,
 861         SR_32_000       = 0x07,
 862         SR_44_100       = 0x08,
 863         SR_48_000       = 0x09,
 864         SR_88_200       = 0x0A,
 865         SR_96_000       = 0x0B,
 866         SR_144_000      = 0x0C,
 867         SR_176_400      = 0x0D,
 868         SR_192_000      = 0x0E,
 869         SR_384_000      = 0x0F,
 870
 871         SR_COUNT        = 0x10,
 872
 873         SR_RATE_UNKNOWN = 0x1F
 874 };
 875
 876 enum dsp_download_state {
 877         DSP_DOWNLOAD_FAILED = -1,
 878         DSP_DOWNLOAD_INIT   = 0,
 879         DSP_DOWNLOADING     = 1,
 880         DSP_DOWNLOADED      = 2
 881 };
 882
 883 /* retrieve parameters from hda format */
 884 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 885 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 886 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 887 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 888
 889 /*
 890  * CA0132 specific
 891  */
 892
 893 struct ca0132_spec {
 894         const struct snd_kcontrol_new *mixers[5];
 895         unsigned int num_mixers;
 896         const struct hda_verb *base_init_verbs;
 897         const struct hda_verb *base_exit_verbs;
 898         const struct hda_verb *chip_init_verbs;
 899         const struct hda_verb *desktop_init_verbs;
 900         struct hda_verb *spec_init_verbs;
 901         struct auto_pin_cfg autocfg;
 902
 903         /* Nodes configurations */
 904         struct hda_multi_out multiout;
 905         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 906         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 907         unsigned int num_outputs;
 908         hda_nid_t input_pins[AUTO_PIN_LAST];
 909         hda_nid_t adcs[AUTO_PIN_LAST];
 910         hda_nid_t dig_out;
 911         hda_nid_t dig_in;
 912         unsigned int num_inputs;
 913         hda_nid_t shared_mic_nid;
 914         hda_nid_t shared_out_nid;
 915         hda_nid_t unsol_tag_hp;
 916         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
 917         hda_nid_t unsol_tag_amic1;
 918
 919         /* chip access */
 920         struct mutex chipio_mutex; /* chip access mutex */
 921         u32 curr_chip_addx;
 922
 923         /* DSP download related */
 924         enum dsp_download_state dsp_state;
 925         unsigned int dsp_stream_id;
 926         unsigned int wait_scp;
 927         unsigned int wait_scp_header;
 928         unsigned int wait_num_data;
 929         unsigned int scp_resp_header;
 930         unsigned int scp_resp_data[4];
 931         unsigned int scp_resp_count;
 932         bool alt_firmware_present;
 933         bool startup_check_entered;
 934         bool dsp_reload;
 935
 936         /* mixer and effects related */
 937         unsigned char dmic_ctl;
 938         int cur_out_type;
 939         int cur_mic_type;
 940         long vnode_lvol[VNODES_COUNT];
 941         long vnode_rvol[VNODES_COUNT];
 942         long vnode_lswitch[VNODES_COUNT];
 943         long vnode_rswitch[VNODES_COUNT];
 944         long effects_switch[EFFECTS_COUNT];
 945         long voicefx_val;
 946         long cur_mic_boost;
 947         /* ca0132_alt control related values */
 948         unsigned char in_enum_val;
 949         unsigned char out_enum_val;
 950         unsigned char mic_boost_enum_val;
 951         unsigned char smart_volume_setting;
 952         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
 953         long xbass_xover_freq;
 954         long eq_preset_val;
 955         unsigned int tlv[4];
 956         struct hda_vmaster_mute_hook vmaster_mute;
 957
 958
 959         struct hda_codec *codec;
 960         struct delayed_work unsol_hp_work;
 961         int quirk;
 962
 963 #ifdef ENABLE_TUNING_CONTROLS
 964         long cur_ctl_vals[TUNING_CTLS_COUNT];
 965 #endif
 966         /*
 967          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
 968          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
 969          * things.
 970          */
 971         bool use_pci_mmio;
 972         void __iomem *mem_base;
 973
 974         /*
 975          * Whether or not to use the alt functions like alt_select_out,
 976          * alt_select_in, etc. Only used on desktop codecs for now, because of
 977          * surround sound support.
 978          */
 979         bool use_alt_functions;
 980
 981         /*
 982          * Whether or not to use alt controls:  volume effect sliders, EQ
 983          * presets, smart volume presets, and new control names with FX prefix.
 984          * Renames PlayEnhancement and CrystalVoice too.
 985          */
 986         bool use_alt_controls;
 987 };
 988
 989 /*
 990  * CA0132 quirks table
 991  */
 992 enum {
 993         QUIRK_NONE,
 994         QUIRK_ALIENWARE,
 995         QUIRK_ALIENWARE_M17XR4,
 996         QUIRK_SBZ,
 997         QUIRK_R3DI,
 998         QUIRK_R3D,
 999 };
1000
1001 static const struct hda_pintbl alienware_pincfgs[] = {
1002         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1003         { 0x0c, 0x411111f0 }, /* N/A */
1004         { 0x0d, 0x411111f0 }, /* N/A */
1005         { 0x0e, 0x411111f0 }, /* N/A */
1006         { 0x0f, 0x0321101f }, /* HP */
1007         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1008         { 0x11, 0x03a11021 }, /* Mic */
1009         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1010         { 0x13, 0x411111f0 }, /* N/A */
1011         { 0x18, 0x411111f0 }, /* N/A */
1012         {}
1013 };
1014
1015 /* Sound Blaster Z pin configs taken from Windows Driver */
1016 static const struct hda_pintbl sbz_pincfgs[] = {
1017         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1018         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1019         { 0x0d, 0x014510f0 }, /* Digital Out */
1020         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1021         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1022         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1023         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1024         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1025         { 0x13, 0x908700f0 }, /* What U Hear In*/
1026         { 0x18, 0x50d000f0 }, /* N/A */
1027         {}
1028 };
1029
1030 /* Recon3D pin configs taken from Windows Driver */
1031 static const struct hda_pintbl r3d_pincfgs[] = {
1032         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1033         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1034         { 0x0d, 0x014510f0 }, /* Digital Out */
1035         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1036         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1037         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1038         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1039         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1040         { 0x13, 0x908700f0 }, /* What U Hear In*/
1041         { 0x18, 0x50d000f0 }, /* N/A */
1042         {}
1043 };
1044
1045 /* Recon3D integrated pin configs taken from Windows Driver */
1046 static const struct hda_pintbl r3di_pincfgs[] = {
1047         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1048         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1049         { 0x0d, 0x014510f0 }, /* Digital Out */
1050         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1051         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1052         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1053         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1054         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1055         { 0x13, 0x908700f0 }, /* What U Hear In*/
1056         { 0x18, 0x500000f0 }, /* N/A */
1057         {}
1058 };
1059
1060 static const struct snd_pci_quirk ca0132_quirks[] = {
1061         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1062         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1063         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1064         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1065         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1066         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1067         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1068         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1069         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1070         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1071         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1072         {}
1073 };
1074
1075 /*
1076  * CA0132 codec access
1077  */
1078 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1079                 unsigned int verb, unsigned int parm, unsigned int *res)
1080 {
1081         unsigned int response;
1082         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1083         *res = response;
1084
1085         return ((response == -1) ? -1 : 0);
1086 }
1087
1088 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1089                 unsigned short converter_format, unsigned int *res)
1090 {
1091         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1092                                 converter_format & 0xffff, res);
1093 }
1094
1095 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1096                                 hda_nid_t nid, unsigned char stream,
1097                                 unsigned char channel, unsigned int *res)
1098 {
1099         unsigned char converter_stream_channel = 0;
1100
1101         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1102         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1103                                 converter_stream_channel, res);
1104 }
1105
1106 /* Chip access helper function */
1107 static int chipio_send(struct hda_codec *codec,
1108                        unsigned int reg,
1109                        unsigned int data)
1110 {
1111         unsigned int res;
1112         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1113
1114         /* send bits of data specified by reg */
1115         do {
1116                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1117                                          reg, data);
1118                 if (res == VENDOR_STATUS_CHIPIO_OK)
1119                         return 0;
1120                 msleep(20);
1121         } while (time_before(jiffies, timeout));
1122
1123         return -EIO;
1124 }
1125
1126 /*
1127  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1128  */
1129 static int chipio_write_address(struct hda_codec *codec,
1130                                 unsigned int chip_addx)
1131 {
1132         struct ca0132_spec *spec = codec->spec;
1133         int res;
1134
1135         if (spec->curr_chip_addx == chip_addx)
1136                         return 0;
1137
1138         /* send low 16 bits of the address */
1139         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1140                           chip_addx & 0xffff);
1141
1142         if (res != -EIO) {
1143                 /* send high 16 bits of the address */
1144                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1145                                   chip_addx >> 16);
1146         }
1147
1148         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1149
1150         return res;
1151 }
1152
1153 /*
1154  * Write data through the vendor widget -- NOT protected by the Mutex!
1155  */
1156 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1157 {
1158         struct ca0132_spec *spec = codec->spec;
1159         int res;
1160
1161         /* send low 16 bits of the data */
1162         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1163
1164         if (res != -EIO) {
1165                 /* send high 16 bits of the data */
1166                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1167                                   data >> 16);
1168         }
1169
1170         /*If no error encountered, automatically increment the address
1171         as per chip behaviour*/
1172         spec->curr_chip_addx = (res != -EIO) ?
1173                                         (spec->curr_chip_addx + 4) : ~0U;
1174         return res;
1175 }
1176
1177 /*
1178  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1179  */
1180 static int chipio_write_data_multiple(struct hda_codec *codec,
1181                                       const u32 *data,
1182                                       unsigned int count)
1183 {
1184         int status = 0;
1185
1186         if (data == NULL) {
1187                 codec_dbg(codec, "chipio_write_data null ptr\n");
1188                 return -EINVAL;
1189         }
1190
1191         while ((count-- != 0) && (status == 0))
1192                 status = chipio_write_data(codec, *data++);
1193
1194         return status;
1195 }
1196
1197
1198 /*
1199  * Read data through the vendor widget -- NOT protected by the Mutex!
1200  */
1201 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1202 {
1203         struct ca0132_spec *spec = codec->spec;
1204         int res;
1205
1206         /* post read */
1207         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1208
1209         if (res != -EIO) {
1210                 /* read status */
1211                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1212         }
1213
1214         if (res != -EIO) {
1215                 /* read data */
1216                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1217                                            VENDOR_CHIPIO_HIC_READ_DATA,
1218                                            0);
1219         }
1220
1221         /*If no error encountered, automatically increment the address
1222         as per chip behaviour*/
1223         spec->curr_chip_addx = (res != -EIO) ?
1224                                         (spec->curr_chip_addx + 4) : ~0U;
1225         return res;
1226 }
1227
1228 /*
1229  * Write given value to the given address through the chip I/O widget.
1230  * protected by the Mutex
1231  */
1232 static int chipio_write(struct hda_codec *codec,
1233                 unsigned int chip_addx, const unsigned int data)
1234 {
1235         struct ca0132_spec *spec = codec->spec;
1236         int err;
1237
1238         mutex_lock(&spec->chipio_mutex);
1239
1240         /* write the address, and if successful proceed to write data */
1241         err = chipio_write_address(codec, chip_addx);
1242         if (err < 0)
1243                 goto exit;
1244
1245         err = chipio_write_data(codec, data);
1246         if (err < 0)
1247                 goto exit;
1248
1249 exit:
1250         mutex_unlock(&spec->chipio_mutex);
1251         return err;
1252 }
1253
1254 /*
1255  * Write given value to the given address through the chip I/O widget.
1256  * not protected by the Mutex
1257  */
1258 static int chipio_write_no_mutex(struct hda_codec *codec,
1259                 unsigned int chip_addx, const unsigned int data)
1260 {
1261         int err;
1262
1263
1264         /* write the address, and if successful proceed to write data */
1265         err = chipio_write_address(codec, chip_addx);
1266         if (err < 0)
1267                 goto exit;
1268
1269         err = chipio_write_data(codec, data);
1270         if (err < 0)
1271                 goto exit;
1272
1273 exit:
1274         return err;
1275 }
1276
1277 /*
1278  * Write multiple values to the given address through the chip I/O widget.
1279  * protected by the Mutex
1280  */
1281 static int chipio_write_multiple(struct hda_codec *codec,
1282                                  u32 chip_addx,
1283                                  const u32 *data,
1284                                  unsigned int count)
1285 {
1286         struct ca0132_spec *spec = codec->spec;
1287         int status;
1288
1289         mutex_lock(&spec->chipio_mutex);
1290         status = chipio_write_address(codec, chip_addx);
1291         if (status < 0)
1292                 goto error;
1293
1294         status = chipio_write_data_multiple(codec, data, count);
1295 error:
1296         mutex_unlock(&spec->chipio_mutex);
1297
1298         return status;
1299 }
1300
1301 /*
1302  * Read the given address through the chip I/O widget
1303  * protected by the Mutex
1304  */
1305 static int chipio_read(struct hda_codec *codec,
1306                 unsigned int chip_addx, unsigned int *data)
1307 {
1308         struct ca0132_spec *spec = codec->spec;
1309         int err;
1310
1311         mutex_lock(&spec->chipio_mutex);
1312
1313         /* write the address, and if successful proceed to write data */
1314         err = chipio_write_address(codec, chip_addx);
1315         if (err < 0)
1316                 goto exit;
1317
1318         err = chipio_read_data(codec, data);
1319         if (err < 0)
1320                 goto exit;
1321
1322 exit:
1323         mutex_unlock(&spec->chipio_mutex);
1324         return err;
1325 }
1326
1327 /*
1328  * Set chip control flags through the chip I/O widget.
1329  */
1330 static void chipio_set_control_flag(struct hda_codec *codec,
1331                                     enum control_flag_id flag_id,
1332                                     bool flag_state)
1333 {
1334         unsigned int val;
1335         unsigned int flag_bit;
1336
1337         flag_bit = (flag_state ? 1 : 0);
1338         val = (flag_bit << 7) | (flag_id);
1339         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1340                             VENDOR_CHIPIO_FLAG_SET, val);
1341 }
1342
1343 /*
1344  * Set chip parameters through the chip I/O widget.
1345  */
1346 static void chipio_set_control_param(struct hda_codec *codec,
1347                 enum control_param_id param_id, int param_val)
1348 {
1349         struct ca0132_spec *spec = codec->spec;
1350         int val;
1351
1352         if ((param_id < 32) && (param_val < 8)) {
1353                 val = (param_val << 5) | (param_id);
1354                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1355                                     VENDOR_CHIPIO_PARAM_SET, val);
1356         } else {
1357                 mutex_lock(&spec->chipio_mutex);
1358                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1359                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1360                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1361                                             param_id);
1362                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1363                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1364                                             param_val);
1365                 }
1366                 mutex_unlock(&spec->chipio_mutex);
1367         }
1368 }
1369
1370 /*
1371  * Set chip parameters through the chip I/O widget. NO MUTEX.
1372  */
1373 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1374                 enum control_param_id param_id, int param_val)
1375 {
1376         int val;
1377
1378         if ((param_id < 32) && (param_val < 8)) {
1379                 val = (param_val << 5) | (param_id);
1380                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1381                                     VENDOR_CHIPIO_PARAM_SET, val);
1382         } else {
1383                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1384                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1385                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1386                                             param_id);
1387                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1388                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1389                                             param_val);
1390                 }
1391         }
1392 }
1393 /*
1394  * Connect stream to a source point, and then connect
1395  * that source point to a destination point.
1396  */
1397 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1398                                 int streamid, int source_point, int dest_point)
1399 {
1400         chipio_set_control_param_no_mutex(codec,
1401                         CONTROL_PARAM_STREAM_ID, streamid);
1402         chipio_set_control_param_no_mutex(codec,
1403                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1404         chipio_set_control_param_no_mutex(codec,
1405                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1406 }
1407
1408 /*
1409  * Set number of channels in the selected stream.
1410  */
1411 static void chipio_set_stream_channels(struct hda_codec *codec,
1412                                 int streamid, unsigned int channels)
1413 {
1414         chipio_set_control_param_no_mutex(codec,
1415                         CONTROL_PARAM_STREAM_ID, streamid);
1416         chipio_set_control_param_no_mutex(codec,
1417                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1418 }
1419
1420 /*
1421  * Enable/Disable audio stream.
1422  */
1423 static void chipio_set_stream_control(struct hda_codec *codec,
1424                                 int streamid, int enable)
1425 {
1426         chipio_set_control_param_no_mutex(codec,
1427                         CONTROL_PARAM_STREAM_ID, streamid);
1428         chipio_set_control_param_no_mutex(codec,
1429                         CONTROL_PARAM_STREAM_CONTROL, enable);
1430 }
1431
1432
1433 /*
1434  * Set sampling rate of the connection point. NO MUTEX.
1435  */
1436 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1437                                 int connid, enum ca0132_sample_rate rate)
1438 {
1439         chipio_set_control_param_no_mutex(codec,
1440                         CONTROL_PARAM_CONN_POINT_ID, connid);
1441         chipio_set_control_param_no_mutex(codec,
1442                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1443 }
1444
1445 /*
1446  * Set sampling rate of the connection point.
1447  */
1448 static void chipio_set_conn_rate(struct hda_codec *codec,
1449                                 int connid, enum ca0132_sample_rate rate)
1450 {
1451         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1452         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1453                                  rate);
1454 }
1455
1456 /*
1457  * Enable clocks.
1458  */
1459 static void chipio_enable_clocks(struct hda_codec *codec)
1460 {
1461         struct ca0132_spec *spec = codec->spec;
1462
1463         mutex_lock(&spec->chipio_mutex);
1464         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1465                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1466         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1468         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1470         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1471                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1472         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1474         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1476         mutex_unlock(&spec->chipio_mutex);
1477 }
1478
1479 /*
1480  * CA0132 DSP IO stuffs
1481  */
1482 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1483                       unsigned int data)
1484 {
1485         int res;
1486         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1487
1488         /* send bits of data specified by reg to dsp */
1489         do {
1490                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1491                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1492                         return res;
1493                 msleep(20);
1494         } while (time_before(jiffies, timeout));
1495
1496         return -EIO;
1497 }
1498
1499 /*
1500  * Wait for DSP to be ready for commands
1501  */
1502 static void dspio_write_wait(struct hda_codec *codec)
1503 {
1504         int status;
1505         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1506
1507         do {
1508                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1509                                                 VENDOR_DSPIO_STATUS, 0);
1510                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1511                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1512                         break;
1513                 msleep(1);
1514         } while (time_before(jiffies, timeout));
1515 }
1516
1517 /*
1518  * Write SCP data to DSP
1519  */
1520 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1521 {
1522         struct ca0132_spec *spec = codec->spec;
1523         int status;
1524
1525         dspio_write_wait(codec);
1526
1527         mutex_lock(&spec->chipio_mutex);
1528         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1529                             scp_data & 0xffff);
1530         if (status < 0)
1531                 goto error;
1532
1533         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1534                                     scp_data >> 16);
1535         if (status < 0)
1536                 goto error;
1537
1538         /* OK, now check if the write itself has executed*/
1539         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1540                                     VENDOR_DSPIO_STATUS, 0);
1541 error:
1542         mutex_unlock(&spec->chipio_mutex);
1543
1544         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1545                         -EIO : 0;
1546 }
1547
1548 /*
1549  * Write multiple SCP data to DSP
1550  */
1551 static int dspio_write_multiple(struct hda_codec *codec,
1552                                 unsigned int *buffer, unsigned int size)
1553 {
1554         int status = 0;
1555         unsigned int count;
1556
1557         if (buffer == NULL)
1558                 return -EINVAL;
1559
1560         count = 0;
1561         while (count < size) {
1562                 status = dspio_write(codec, *buffer++);
1563                 if (status != 0)
1564                         break;
1565                 count++;
1566         }
1567
1568         return status;
1569 }
1570
1571 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1572 {
1573         int status;
1574
1575         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1576         if (status == -EIO)
1577                 return status;
1578
1579         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1580         if (status == -EIO ||
1581             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1582                 return -EIO;
1583
1584         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1585                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1586
1587         return 0;
1588 }
1589
1590 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1591                                unsigned int *buf_size, unsigned int size_count)
1592 {
1593         int status = 0;
1594         unsigned int size = *buf_size;
1595         unsigned int count;
1596         unsigned int skip_count;
1597         unsigned int dummy;
1598
1599         if (buffer == NULL)
1600                 return -1;
1601
1602         count = 0;
1603         while (count < size && count < size_count) {
1604                 status = dspio_read(codec, buffer++);
1605                 if (status != 0)
1606                         break;
1607                 count++;
1608         }
1609
1610         skip_count = count;
1611         if (status == 0) {
1612                 while (skip_count < size) {
1613                         status = dspio_read(codec, &dummy);
1614                         if (status != 0)
1615                                 break;
1616                         skip_count++;
1617                 }
1618         }
1619         *buf_size = count;
1620
1621         return status;
1622 }
1623
1624 /*
1625  * Construct the SCP header using corresponding fields
1626  */
1627 static inline unsigned int
1628 make_scp_header(unsigned int target_id, unsigned int source_id,
1629                 unsigned int get_flag, unsigned int req,
1630                 unsigned int device_flag, unsigned int resp_flag,
1631                 unsigned int error_flag, unsigned int data_size)
1632 {
1633         unsigned int header = 0;
1634
1635         header = (data_size & 0x1f) << 27;
1636         header |= (error_flag & 0x01) << 26;
1637         header |= (resp_flag & 0x01) << 25;
1638         header |= (device_flag & 0x01) << 24;
1639         header |= (req & 0x7f) << 17;
1640         header |= (get_flag & 0x01) << 16;
1641         header |= (source_id & 0xff) << 8;
1642         header |= target_id & 0xff;
1643
1644         return header;
1645 }
1646
1647 /*
1648  * Extract corresponding fields from SCP header
1649  */
1650 static inline void
1651 extract_scp_header(unsigned int header,
1652                    unsigned int *target_id, unsigned int *source_id,
1653                    unsigned int *get_flag, unsigned int *req,
1654                    unsigned int *device_flag, unsigned int *resp_flag,
1655                    unsigned int *error_flag, unsigned int *data_size)
1656 {
1657         if (data_size)
1658                 *data_size = (header >> 27) & 0x1f;
1659         if (error_flag)
1660                 *error_flag = (header >> 26) & 0x01;
1661         if (resp_flag)
1662                 *resp_flag = (header >> 25) & 0x01;
1663         if (device_flag)
1664                 *device_flag = (header >> 24) & 0x01;
1665         if (req)
1666                 *req = (header >> 17) & 0x7f;
1667         if (get_flag)
1668                 *get_flag = (header >> 16) & 0x01;
1669         if (source_id)
1670                 *source_id = (header >> 8) & 0xff;
1671         if (target_id)
1672                 *target_id = header & 0xff;
1673 }
1674
1675 #define SCP_MAX_DATA_WORDS  (16)
1676
1677 /* Structure to contain any SCP message */
1678 struct scp_msg {
1679         unsigned int hdr;
1680         unsigned int data[SCP_MAX_DATA_WORDS];
1681 };
1682
1683 static void dspio_clear_response_queue(struct hda_codec *codec)
1684 {
1685         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1686         unsigned int dummy = 0;
1687         int status;
1688
1689         /* clear all from the response queue */
1690         do {
1691                 status = dspio_read(codec, &dummy);
1692         } while (status == 0 && time_before(jiffies, timeout));
1693 }
1694
1695 static int dspio_get_response_data(struct hda_codec *codec)
1696 {
1697         struct ca0132_spec *spec = codec->spec;
1698         unsigned int data = 0;
1699         unsigned int count;
1700
1701         if (dspio_read(codec, &data) < 0)
1702                 return -EIO;
1703
1704         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1705                 spec->scp_resp_header = data;
1706                 spec->scp_resp_count = data >> 27;
1707                 count = spec->wait_num_data;
1708                 dspio_read_multiple(codec, spec->scp_resp_data,
1709                                     &spec->scp_resp_count, count);
1710                 return 0;
1711         }
1712
1713         return -EIO;
1714 }
1715
1716 /*
1717  * Send SCP message to DSP
1718  */
1719 static int dspio_send_scp_message(struct hda_codec *codec,
1720                                   unsigned char *send_buf,
1721                                   unsigned int send_buf_size,
1722                                   unsigned char *return_buf,
1723                                   unsigned int return_buf_size,
1724                                   unsigned int *bytes_returned)
1725 {
1726         struct ca0132_spec *spec = codec->spec;
1727         int status = -1;
1728         unsigned int scp_send_size = 0;
1729         unsigned int total_size;
1730         bool waiting_for_resp = false;
1731         unsigned int header;
1732         struct scp_msg *ret_msg;
1733         unsigned int resp_src_id, resp_target_id;
1734         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1735
1736         if (bytes_returned)
1737                 *bytes_returned = 0;
1738
1739         /* get scp header from buffer */
1740         header = *((unsigned int *)send_buf);
1741         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1742                            &device_flag, NULL, NULL, &data_size);
1743         scp_send_size = data_size + 1;
1744         total_size = (scp_send_size * 4);
1745
1746         if (send_buf_size < total_size)
1747                 return -EINVAL;
1748
1749         if (get_flag || device_flag) {
1750                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1751                         return -EINVAL;
1752
1753                 spec->wait_scp_header = *((unsigned int *)send_buf);
1754
1755                 /* swap source id with target id */
1756                 resp_target_id = src_id;
1757                 resp_src_id = target_id;
1758                 spec->wait_scp_header &= 0xffff0000;
1759                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1760                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1761                 spec->wait_scp = 1;
1762                 waiting_for_resp = true;
1763         }
1764
1765         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1766                                       scp_send_size);
1767         if (status < 0) {
1768                 spec->wait_scp = 0;
1769                 return status;
1770         }
1771
1772         if (waiting_for_resp) {
1773                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1774                 memset(return_buf, 0, return_buf_size);
1775                 do {
1776                         msleep(20);
1777                 } while (spec->wait_scp && time_before(jiffies, timeout));
1778                 waiting_for_resp = false;
1779                 if (!spec->wait_scp) {
1780                         ret_msg = (struct scp_msg *)return_buf;
1781                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1782                         memcpy(&ret_msg->data, spec->scp_resp_data,
1783                                spec->wait_num_data);
1784                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1785                         status = 0;
1786                 } else {
1787                         status = -EIO;
1788                 }
1789                 spec->wait_scp = 0;
1790         }
1791
1792         return status;
1793 }
1794
1795 /**
1796  * Prepare and send the SCP message to DSP
1797  * @codec: the HDA codec
1798  * @mod_id: ID of the DSP module to send the command
1799  * @req: ID of request to send to the DSP module
1800  * @dir: SET or GET
1801  * @data: pointer to the data to send with the request, request specific
1802  * @len: length of the data, in bytes
1803  * @reply: point to the buffer to hold data returned for a reply
1804  * @reply_len: length of the reply buffer returned from GET
1805  *
1806  * Returns zero or a negative error code.
1807  */
1808 static int dspio_scp(struct hda_codec *codec,
1809                 int mod_id, int src_id, int req, int dir, const void *data,
1810                 unsigned int len, void *reply, unsigned int *reply_len)
1811 {
1812         int status = 0;
1813         struct scp_msg scp_send, scp_reply;
1814         unsigned int ret_bytes, send_size, ret_size;
1815         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1816         unsigned int reply_data_size;
1817
1818         memset(&scp_send, 0, sizeof(scp_send));
1819         memset(&scp_reply, 0, sizeof(scp_reply));
1820
1821         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1822                 return -EINVAL;
1823
1824         if (dir == SCP_GET && reply == NULL) {
1825                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1826                 return -EINVAL;
1827         }
1828
1829         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1830                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1831                 return -EINVAL;
1832         }
1833
1834         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1835                                        0, 0, 0, len/sizeof(unsigned int));
1836         if (data != NULL && len > 0) {
1837                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1838                 memcpy(scp_send.data, data, len);
1839         }
1840
1841         ret_bytes = 0;
1842         send_size = sizeof(unsigned int) + len;
1843         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1844                                         send_size, (unsigned char *)&scp_reply,
1845                                         sizeof(scp_reply), &ret_bytes);
1846
1847         if (status < 0) {
1848                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1849                 return status;
1850         }
1851
1852         /* extract send and reply headers members */
1853         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1854                            NULL, NULL, NULL, NULL, NULL);
1855         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1856                            &reply_resp_flag, &reply_error_flag,
1857                            &reply_data_size);
1858
1859         if (!send_get_flag)
1860                 return 0;
1861
1862         if (reply_resp_flag && !reply_error_flag) {
1863                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1864                                         / sizeof(unsigned int);
1865
1866                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1867                         codec_dbg(codec, "reply too long for buf\n");
1868                         return -EINVAL;
1869                 } else if (ret_size != reply_data_size) {
1870                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1871                         return -EINVAL;
1872                 } else if (!reply) {
1873                         codec_dbg(codec, "NULL reply\n");
1874                         return -EINVAL;
1875                 } else {
1876                         *reply_len = ret_size*sizeof(unsigned int);
1877                         memcpy(reply, scp_reply.data, *reply_len);
1878                 }
1879         } else {
1880                 codec_dbg(codec, "reply ill-formed or errflag set\n");
1881                 return -EIO;
1882         }
1883
1884         return status;
1885 }
1886
1887 /*
1888  * Set DSP parameters
1889  */
1890 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1891                         int src_id, int req, const void *data, unsigned int len)
1892 {
1893         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1894                         NULL);
1895 }
1896
1897 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1898                         int req, const unsigned int data)
1899 {
1900         return dspio_set_param(codec, mod_id, 0x20, req, &data,
1901                         sizeof(unsigned int));
1902 }
1903
1904 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1905                         int req, const unsigned int data)
1906 {
1907         return dspio_set_param(codec, mod_id, 0x00, req, &data,
1908                         sizeof(unsigned int));
1909 }
1910
1911 /*
1912  * Allocate a DSP DMA channel via an SCP message
1913  */
1914 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1915 {
1916         int status = 0;
1917         unsigned int size = sizeof(dma_chan);
1918
1919         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1920         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1921                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1922                         dma_chan, &size);
1923
1924         if (status < 0) {
1925                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1926                 return status;
1927         }
1928
1929         if ((*dma_chan + 1) == 0) {
1930                 codec_dbg(codec, "no free dma channels to allocate\n");
1931                 return -EBUSY;
1932         }
1933
1934         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1935         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1936
1937         return status;
1938 }
1939
1940 /*
1941  * Free a DSP DMA via an SCP message
1942  */
1943 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1944 {
1945         int status = 0;
1946         unsigned int dummy = 0;
1947
1948         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1949         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1950
1951         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1952                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1953                         sizeof(dma_chan), NULL, &dummy);
1954
1955         if (status < 0) {
1956                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1957                 return status;
1958         }
1959
1960         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1961
1962         return status;
1963 }
1964
1965 /*
1966  * (Re)start the DSP
1967  */
1968 static int dsp_set_run_state(struct hda_codec *codec)
1969 {
1970         unsigned int dbg_ctrl_reg;
1971         unsigned int halt_state;
1972         int err;
1973
1974         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1975         if (err < 0)
1976                 return err;
1977
1978         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1979                       DSP_DBGCNTL_STATE_LOBIT;
1980
1981         if (halt_state != 0) {
1982                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1983                                   DSP_DBGCNTL_SS_MASK);
1984                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1985                                    dbg_ctrl_reg);
1986                 if (err < 0)
1987                         return err;
1988
1989                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1990                                 DSP_DBGCNTL_EXEC_MASK;
1991                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1992                                    dbg_ctrl_reg);
1993                 if (err < 0)
1994                         return err;
1995         }
1996
1997         return 0;
1998 }
1999
2000 /*
2001  * Reset the DSP
2002  */
2003 static int dsp_reset(struct hda_codec *codec)
2004 {
2005         unsigned int res;
2006         int retry = 20;
2007
2008         codec_dbg(codec, "dsp_reset\n");
2009         do {
2010                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2011                 retry--;
2012         } while (res == -EIO && retry);
2013
2014         if (!retry) {
2015                 codec_dbg(codec, "dsp_reset timeout\n");
2016                 return -EIO;
2017         }
2018
2019         return 0;
2020 }
2021
2022 /*
2023  * Convert chip address to DSP address
2024  */
2025 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2026                                         bool *code, bool *yram)
2027 {
2028         *code = *yram = false;
2029
2030         if (UC_RANGE(chip_addx, 1)) {
2031                 *code = true;
2032                 return UC_OFF(chip_addx);
2033         } else if (X_RANGE_ALL(chip_addx, 1)) {
2034                 return X_OFF(chip_addx);
2035         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2036                 *yram = true;
2037                 return Y_OFF(chip_addx);
2038         }
2039
2040         return INVALID_CHIP_ADDRESS;
2041 }
2042
2043 /*
2044  * Check if the DSP DMA is active
2045  */
2046 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2047 {
2048         unsigned int dma_chnlstart_reg;
2049
2050         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2051
2052         return ((dma_chnlstart_reg & (1 <<
2053                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2054 }
2055
2056 static int dsp_dma_setup_common(struct hda_codec *codec,
2057                                 unsigned int chip_addx,
2058                                 unsigned int dma_chan,
2059                                 unsigned int port_map_mask,
2060                                 bool ovly)
2061 {
2062         int status = 0;
2063         unsigned int chnl_prop;
2064         unsigned int dsp_addx;
2065         unsigned int active;
2066         bool code, yram;
2067
2068         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2069
2070         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2071                 codec_dbg(codec, "dma chan num invalid\n");
2072                 return -EINVAL;
2073         }
2074
2075         if (dsp_is_dma_active(codec, dma_chan)) {
2076                 codec_dbg(codec, "dma already active\n");
2077                 return -EBUSY;
2078         }
2079
2080         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2081
2082         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2083                 codec_dbg(codec, "invalid chip addr\n");
2084                 return -ENXIO;
2085         }
2086
2087         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2088         active = 0;
2089
2090         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2091
2092         if (ovly) {
2093                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2094                                      &chnl_prop);
2095
2096                 if (status < 0) {
2097                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2098                         return status;
2099                 }
2100                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2101         }
2102
2103         if (!code)
2104                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2105         else
2106                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2107
2108         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2109
2110         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2111         if (status < 0) {
2112                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2113                 return status;
2114         }
2115         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2116
2117         if (ovly) {
2118                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2119                                      &active);
2120
2121                 if (status < 0) {
2122                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2123                         return status;
2124                 }
2125                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2126         }
2127
2128         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2129                 DSPDMAC_ACTIVE_AAR_MASK;
2130
2131         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2132         if (status < 0) {
2133                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2134                 return status;
2135         }
2136
2137         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2138
2139         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2140                               port_map_mask);
2141         if (status < 0) {
2142                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2143                 return status;
2144         }
2145         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2146
2147         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2148                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2149         if (status < 0) {
2150                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2151                 return status;
2152         }
2153         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2154
2155         codec_dbg(codec,
2156                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2157                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2158                    chip_addx, dsp_addx, dma_chan,
2159                    port_map_mask, chnl_prop, active);
2160
2161         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2162
2163         return 0;
2164 }
2165
2166 /*
2167  * Setup the DSP DMA per-transfer-specific registers
2168  */
2169 static int dsp_dma_setup(struct hda_codec *codec,
2170                         unsigned int chip_addx,
2171                         unsigned int count,
2172                         unsigned int dma_chan)
2173 {
2174         int status = 0;
2175         bool code, yram;
2176         unsigned int dsp_addx;
2177         unsigned int addr_field;
2178         unsigned int incr_field;
2179         unsigned int base_cnt;
2180         unsigned int cur_cnt;
2181         unsigned int dma_cfg = 0;
2182         unsigned int adr_ofs = 0;
2183         unsigned int xfr_cnt = 0;
2184         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2185                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2186
2187         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2188
2189         if (count > max_dma_count) {
2190                 codec_dbg(codec, "count too big\n");
2191                 return -EINVAL;
2192         }
2193
2194         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2195         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2196                 codec_dbg(codec, "invalid chip addr\n");
2197                 return -ENXIO;
2198         }
2199
2200         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2201
2202         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2203         incr_field   = 0;
2204
2205         if (!code) {
2206                 addr_field <<= 1;
2207                 if (yram)
2208                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2209
2210                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2211         }
2212
2213         dma_cfg = addr_field + incr_field;
2214         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2215                                 dma_cfg);
2216         if (status < 0) {
2217                 codec_dbg(codec, "write DMACFG Reg fail\n");
2218                 return status;
2219         }
2220         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2221
2222         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2223                                                         (code ? 0 : 1));
2224
2225         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2226                                 adr_ofs);
2227         if (status < 0) {
2228                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2229                 return status;
2230         }
2231         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2232
2233         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2234
2235         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2236
2237         xfr_cnt = base_cnt | cur_cnt;
2238
2239         status = chipio_write(codec,
2240                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2241         if (status < 0) {
2242                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2243                 return status;
2244         }
2245         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2246
2247         codec_dbg(codec,
2248                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2249                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2250                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2251
2252         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2253
2254         return 0;
2255 }
2256
2257 /*
2258  * Start the DSP DMA
2259  */
2260 static int dsp_dma_start(struct hda_codec *codec,
2261                          unsigned int dma_chan, bool ovly)
2262 {
2263         unsigned int reg = 0;
2264         int status = 0;
2265
2266         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2267
2268         if (ovly) {
2269                 status = chipio_read(codec,
2270                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2271
2272                 if (status < 0) {
2273                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2274                         return status;
2275                 }
2276                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2277
2278                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2279                                 DSPDMAC_CHNLSTART_DIS_MASK);
2280         }
2281
2282         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2283                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2284         if (status < 0) {
2285                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2286                 return status;
2287         }
2288         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2289
2290         return status;
2291 }
2292
2293 /*
2294  * Stop the DSP DMA
2295  */
2296 static int dsp_dma_stop(struct hda_codec *codec,
2297                         unsigned int dma_chan, bool ovly)
2298 {
2299         unsigned int reg = 0;
2300         int status = 0;
2301
2302         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2303
2304         if (ovly) {
2305                 status = chipio_read(codec,
2306                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2307
2308                 if (status < 0) {
2309                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2310                         return status;
2311                 }
2312                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2313                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2314                                 DSPDMAC_CHNLSTART_DIS_MASK);
2315         }
2316
2317         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2318                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2319         if (status < 0) {
2320                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2321                 return status;
2322         }
2323         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2324
2325         return status;
2326 }
2327
2328 /**
2329  * Allocate router ports
2330  *
2331  * @codec: the HDA codec
2332  * @num_chans: number of channels in the stream
2333  * @ports_per_channel: number of ports per channel
2334  * @start_device: start device
2335  * @port_map: pointer to the port list to hold the allocated ports
2336  *
2337  * Returns zero or a negative error code.
2338  */
2339 static int dsp_allocate_router_ports(struct hda_codec *codec,
2340                                      unsigned int num_chans,
2341                                      unsigned int ports_per_channel,
2342                                      unsigned int start_device,
2343                                      unsigned int *port_map)
2344 {
2345         int status = 0;
2346         int res;
2347         u8 val;
2348
2349         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2350         if (status < 0)
2351                 return status;
2352
2353         val = start_device << 6;
2354         val |= (ports_per_channel - 1) << 4;
2355         val |= num_chans - 1;
2356
2357         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2358                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2359                             val);
2360
2361         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2362                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2363                             MEM_CONNID_DSP);
2364
2365         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2366         if (status < 0)
2367                 return status;
2368
2369         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2370                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2371
2372         *port_map = res;
2373
2374         return (res < 0) ? res : 0;
2375 }
2376
2377 /*
2378  * Free router ports
2379  */
2380 static int dsp_free_router_ports(struct hda_codec *codec)
2381 {
2382         int status = 0;
2383
2384         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2385         if (status < 0)
2386                 return status;
2387
2388         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2389                             VENDOR_CHIPIO_PORT_FREE_SET,
2390                             MEM_CONNID_DSP);
2391
2392         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2393
2394         return status;
2395 }
2396
2397 /*
2398  * Allocate DSP ports for the download stream
2399  */
2400 static int dsp_allocate_ports(struct hda_codec *codec,
2401                         unsigned int num_chans,
2402                         unsigned int rate_multi, unsigned int *port_map)
2403 {
2404         int status;
2405
2406         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2407
2408         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2409                 codec_dbg(codec, "bad rate multiple\n");
2410                 return -EINVAL;
2411         }
2412
2413         status = dsp_allocate_router_ports(codec, num_chans,
2414                                            rate_multi, 0, port_map);
2415
2416         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2417
2418         return status;
2419 }
2420
2421 static int dsp_allocate_ports_format(struct hda_codec *codec,
2422                         const unsigned short fmt,
2423                         unsigned int *port_map)
2424 {
2425         int status;
2426         unsigned int num_chans;
2427
2428         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2429         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2430         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2431
2432         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2433                 codec_dbg(codec, "bad rate multiple\n");
2434                 return -EINVAL;
2435         }
2436
2437         num_chans = get_hdafmt_chs(fmt) + 1;
2438
2439         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2440
2441         return status;
2442 }
2443
2444 /*
2445  * free DSP ports
2446  */
2447 static int dsp_free_ports(struct hda_codec *codec)
2448 {
2449         int status;
2450
2451         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2452
2453         status = dsp_free_router_ports(codec);
2454         if (status < 0) {
2455                 codec_dbg(codec, "free router ports fail\n");
2456                 return status;
2457         }
2458         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2459
2460         return status;
2461 }
2462
2463 /*
2464  *  HDA DMA engine stuffs for DSP code download
2465  */
2466 struct dma_engine {
2467         struct hda_codec *codec;
2468         unsigned short m_converter_format;
2469         struct snd_dma_buffer *dmab;
2470         unsigned int buf_size;
2471 };
2472
2473
2474 enum dma_state {
2475         DMA_STATE_STOP  = 0,
2476         DMA_STATE_RUN   = 1
2477 };
2478
2479 static int dma_convert_to_hda_format(struct hda_codec *codec,
2480                 unsigned int sample_rate,
2481                 unsigned short channels,
2482                 unsigned short *hda_format)
2483 {
2484         unsigned int format_val;
2485
2486         format_val = snd_hdac_calc_stream_format(sample_rate,
2487                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2488
2489         if (hda_format)
2490                 *hda_format = (unsigned short)format_val;
2491
2492         return 0;
2493 }
2494
2495 /*
2496  *  Reset DMA for DSP download
2497  */
2498 static int dma_reset(struct dma_engine *dma)
2499 {
2500         struct hda_codec *codec = dma->codec;
2501         struct ca0132_spec *spec = codec->spec;
2502         int status;
2503
2504         if (dma->dmab->area)
2505                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2506
2507         status = snd_hda_codec_load_dsp_prepare(codec,
2508                         dma->m_converter_format,
2509                         dma->buf_size,
2510                         dma->dmab);
2511         if (status < 0)
2512                 return status;
2513         spec->dsp_stream_id = status;
2514         return 0;
2515 }
2516
2517 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2518 {
2519         bool cmd;
2520
2521         switch (state) {
2522         case DMA_STATE_STOP:
2523                 cmd = false;
2524                 break;
2525         case DMA_STATE_RUN:
2526                 cmd = true;
2527                 break;
2528         default:
2529                 return 0;
2530         }
2531
2532         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2533         return 0;
2534 }
2535
2536 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2537 {
2538         return dma->dmab->bytes;
2539 }
2540
2541 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2542 {
2543         return dma->dmab->area;
2544 }
2545
2546 static int dma_xfer(struct dma_engine *dma,
2547                 const unsigned int *data,
2548                 unsigned int count)
2549 {
2550         memcpy(dma->dmab->area, data, count);
2551         return 0;
2552 }
2553
2554 static void dma_get_converter_format(
2555                 struct dma_engine *dma,
2556                 unsigned short *format)
2557 {
2558         if (format)
2559                 *format = dma->m_converter_format;
2560 }
2561
2562 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2563 {
2564         struct ca0132_spec *spec = dma->codec->spec;
2565
2566         return spec->dsp_stream_id;
2567 }
2568
2569 struct dsp_image_seg {
2570         u32 magic;
2571         u32 chip_addr;
2572         u32 count;
2573         u32 data[0];
2574 };
2575
2576 static const u32 g_magic_value = 0x4c46584d;
2577 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2578
2579 static bool is_valid(const struct dsp_image_seg *p)
2580 {
2581         return p->magic == g_magic_value;
2582 }
2583
2584 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2585 {
2586         return g_chip_addr_magic_value == p->chip_addr;
2587 }
2588
2589 static bool is_last(const struct dsp_image_seg *p)
2590 {
2591         return p->count == 0;
2592 }
2593
2594 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2595 {
2596         return sizeof(*p) + p->count*sizeof(u32);
2597 }
2598
2599 static const struct dsp_image_seg *get_next_seg_ptr(
2600                                 const struct dsp_image_seg *p)
2601 {
2602         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2603 }
2604
2605 /*
2606  * CA0132 chip DSP transfer stuffs.  For DSP download.
2607  */
2608 #define INVALID_DMA_CHANNEL (~0U)
2609
2610 /*
2611  * Program a list of address/data pairs via the ChipIO widget.
2612  * The segment data is in the format of successive pairs of words.
2613  * These are repeated as indicated by the segment's count field.
2614  */
2615 static int dspxfr_hci_write(struct hda_codec *codec,
2616                         const struct dsp_image_seg *fls)
2617 {
2618         int status;
2619         const u32 *data;
2620         unsigned int count;
2621
2622         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2623                 codec_dbg(codec, "hci_write invalid params\n");
2624                 return -EINVAL;
2625         }
2626
2627         count = fls->count;
2628         data = (u32 *)(fls->data);
2629         while (count >= 2) {
2630                 status = chipio_write(codec, data[0], data[1]);
2631                 if (status < 0) {
2632                         codec_dbg(codec, "hci_write chipio failed\n");
2633                         return status;
2634                 }
2635                 count -= 2;
2636                 data  += 2;
2637         }
2638         return 0;
2639 }
2640
2641 /**
2642  * Write a block of data into DSP code or data RAM using pre-allocated
2643  * DMA engine.
2644  *
2645  * @codec: the HDA codec
2646  * @fls: pointer to a fast load image
2647  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2648  *         no relocation
2649  * @dma_engine: pointer to DMA engine to be used for DSP download
2650  * @dma_chan: The number of DMA channels used for DSP download
2651  * @port_map_mask: port mapping
2652  * @ovly: TRUE if overlay format is required
2653  *
2654  * Returns zero or a negative error code.
2655  */
2656 static int dspxfr_one_seg(struct hda_codec *codec,
2657                         const struct dsp_image_seg *fls,
2658                         unsigned int reloc,
2659                         struct dma_engine *dma_engine,
2660                         unsigned int dma_chan,
2661                         unsigned int port_map_mask,
2662                         bool ovly)
2663 {
2664         int status = 0;
2665         bool comm_dma_setup_done = false;
2666         const unsigned int *data;
2667         unsigned int chip_addx;
2668         unsigned int words_to_write;
2669         unsigned int buffer_size_words;
2670         unsigned char *buffer_addx;
2671         unsigned short hda_format;
2672         unsigned int sample_rate_div;
2673         unsigned int sample_rate_mul;
2674         unsigned int num_chans;
2675         unsigned int hda_frame_size_words;
2676         unsigned int remainder_words;
2677         const u32 *data_remainder;
2678         u32 chip_addx_remainder;
2679         unsigned int run_size_words;
2680         const struct dsp_image_seg *hci_write = NULL;
2681         unsigned long timeout;
2682         bool dma_active;
2683
2684         if (fls == NULL)
2685                 return -EINVAL;
2686         if (is_hci_prog_list_seg(fls)) {
2687                 hci_write = fls;
2688                 fls = get_next_seg_ptr(fls);
2689         }
2690
2691         if (hci_write && (!fls || is_last(fls))) {
2692                 codec_dbg(codec, "hci_write\n");
2693                 return dspxfr_hci_write(codec, hci_write);
2694         }
2695
2696         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2697                 codec_dbg(codec, "Invalid Params\n");
2698                 return -EINVAL;
2699         }
2700
2701         data = fls->data;
2702         chip_addx = fls->chip_addr,
2703         words_to_write = fls->count;
2704
2705         if (!words_to_write)
2706                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2707         if (reloc)
2708                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2709
2710         if (!UC_RANGE(chip_addx, words_to_write) &&
2711             !X_RANGE_ALL(chip_addx, words_to_write) &&
2712             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2713                 codec_dbg(codec, "Invalid chip_addx Params\n");
2714                 return -EINVAL;
2715         }
2716
2717         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2718                                         sizeof(u32);
2719
2720         buffer_addx = dma_get_buffer_addr(dma_engine);
2721
2722         if (buffer_addx == NULL) {
2723                 codec_dbg(codec, "dma_engine buffer NULL\n");
2724                 return -EINVAL;
2725         }
2726
2727         dma_get_converter_format(dma_engine, &hda_format);
2728         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2729         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2730         num_chans = get_hdafmt_chs(hda_format) + 1;
2731
2732         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2733                         (num_chans * sample_rate_mul / sample_rate_div));
2734
2735         if (hda_frame_size_words == 0) {
2736                 codec_dbg(codec, "frmsz zero\n");
2737                 return -EINVAL;
2738         }
2739
2740         buffer_size_words = min(buffer_size_words,
2741                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2742                                 65536 : 32768));
2743         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2744         codec_dbg(codec,
2745                    "chpadr=0x%08x frmsz=%u nchan=%u "
2746                    "rate_mul=%u div=%u bufsz=%u\n",
2747                    chip_addx, hda_frame_size_words, num_chans,
2748                    sample_rate_mul, sample_rate_div, buffer_size_words);
2749
2750         if (buffer_size_words < hda_frame_size_words) {
2751                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2752                 return -EINVAL;
2753         }
2754
2755         remainder_words = words_to_write % hda_frame_size_words;
2756         data_remainder = data;
2757         chip_addx_remainder = chip_addx;
2758
2759         data += remainder_words;
2760         chip_addx += remainder_words*sizeof(u32);
2761         words_to_write -= remainder_words;
2762
2763         while (words_to_write != 0) {
2764                 run_size_words = min(buffer_size_words, words_to_write);
2765                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2766                             words_to_write, run_size_words, remainder_words);
2767                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2768                 if (!comm_dma_setup_done) {
2769                         status = dsp_dma_stop(codec, dma_chan, ovly);
2770                         if (status < 0)
2771                                 return status;
2772                         status = dsp_dma_setup_common(codec, chip_addx,
2773                                                 dma_chan, port_map_mask, ovly);
2774                         if (status < 0)
2775                                 return status;
2776                         comm_dma_setup_done = true;
2777                 }
2778
2779                 status = dsp_dma_setup(codec, chip_addx,
2780                                                 run_size_words, dma_chan);
2781                 if (status < 0)
2782                         return status;
2783                 status = dsp_dma_start(codec, dma_chan, ovly);
2784                 if (status < 0)
2785                         return status;
2786                 if (!dsp_is_dma_active(codec, dma_chan)) {
2787                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2788                         return -EIO;
2789                 }
2790                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2791                 if (status < 0)
2792                         return status;
2793                 if (remainder_words != 0) {
2794                         status = chipio_write_multiple(codec,
2795                                                 chip_addx_remainder,
2796                                                 data_remainder,
2797                                                 remainder_words);
2798                         if (status < 0)
2799                                 return status;
2800                         remainder_words = 0;
2801                 }
2802                 if (hci_write) {
2803                         status = dspxfr_hci_write(codec, hci_write);
2804                         if (status < 0)
2805                                 return status;
2806                         hci_write = NULL;
2807                 }
2808
2809                 timeout = jiffies + msecs_to_jiffies(2000);
2810                 do {
2811                         dma_active = dsp_is_dma_active(codec, dma_chan);
2812                         if (!dma_active)
2813                                 break;
2814                         msleep(20);
2815                 } while (time_before(jiffies, timeout));
2816                 if (dma_active)
2817                         break;
2818
2819                 codec_dbg(codec, "+++++ DMA complete\n");
2820                 dma_set_state(dma_engine, DMA_STATE_STOP);
2821                 status = dma_reset(dma_engine);
2822
2823                 if (status < 0)
2824                         return status;
2825
2826                 data += run_size_words;
2827                 chip_addx += run_size_words*sizeof(u32);
2828                 words_to_write -= run_size_words;
2829         }
2830
2831         if (remainder_words != 0) {
2832                 status = chipio_write_multiple(codec, chip_addx_remainder,
2833                                         data_remainder, remainder_words);
2834         }
2835
2836         return status;
2837 }
2838
2839 /**
2840  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2841  *
2842  * @codec: the HDA codec
2843  * @fls_data: pointer to a fast load image
2844  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2845  *         no relocation
2846  * @sample_rate: sampling rate of the stream used for DSP download
2847  * @channels: channels of the stream used for DSP download
2848  * @ovly: TRUE if overlay format is required
2849  *
2850  * Returns zero or a negative error code.
2851  */
2852 static int dspxfr_image(struct hda_codec *codec,
2853                         const struct dsp_image_seg *fls_data,
2854                         unsigned int reloc,
2855                         unsigned int sample_rate,
2856                         unsigned short channels,
2857                         bool ovly)
2858 {
2859         struct ca0132_spec *spec = codec->spec;
2860         int status;
2861         unsigned short hda_format = 0;
2862         unsigned int response;
2863         unsigned char stream_id = 0;
2864         struct dma_engine *dma_engine;
2865         unsigned int dma_chan;
2866         unsigned int port_map_mask;
2867
2868         if (fls_data == NULL)
2869                 return -EINVAL;
2870
2871         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2872         if (!dma_engine)
2873                 return -ENOMEM;
2874
2875         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2876         if (!dma_engine->dmab) {
2877                 kfree(dma_engine);
2878                 return -ENOMEM;
2879         }
2880
2881         dma_engine->codec = codec;
2882         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2883         dma_engine->m_converter_format = hda_format;
2884         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2885                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2886
2887         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2888
2889         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2890                                         hda_format, &response);
2891
2892         if (status < 0) {
2893                 codec_dbg(codec, "set converter format fail\n");
2894                 goto exit;
2895         }
2896
2897         status = snd_hda_codec_load_dsp_prepare(codec,
2898                                 dma_engine->m_converter_format,
2899                                 dma_engine->buf_size,
2900                                 dma_engine->dmab);
2901         if (status < 0)
2902                 goto exit;
2903         spec->dsp_stream_id = status;
2904
2905         if (ovly) {
2906                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2907                 if (status < 0) {
2908                         codec_dbg(codec, "alloc dmachan fail\n");
2909                         dma_chan = INVALID_DMA_CHANNEL;
2910                         goto exit;
2911                 }
2912         }
2913
2914         port_map_mask = 0;
2915         status = dsp_allocate_ports_format(codec, hda_format,
2916                                         &port_map_mask);
2917         if (status < 0) {
2918                 codec_dbg(codec, "alloc ports fail\n");
2919                 goto exit;
2920         }
2921
2922         stream_id = dma_get_stream_id(dma_engine);
2923         status = codec_set_converter_stream_channel(codec,
2924                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2925         if (status < 0) {
2926                 codec_dbg(codec, "set stream chan fail\n");
2927                 goto exit;
2928         }
2929
2930         while ((fls_data != NULL) && !is_last(fls_data)) {
2931                 if (!is_valid(fls_data)) {
2932                         codec_dbg(codec, "FLS check fail\n");
2933                         status = -EINVAL;
2934                         goto exit;
2935                 }
2936                 status = dspxfr_one_seg(codec, fls_data, reloc,
2937                                         dma_engine, dma_chan,
2938                                         port_map_mask, ovly);
2939                 if (status < 0)
2940                         break;
2941
2942                 if (is_hci_prog_list_seg(fls_data))
2943                         fls_data = get_next_seg_ptr(fls_data);
2944
2945                 if ((fls_data != NULL) && !is_last(fls_data))
2946                         fls_data = get_next_seg_ptr(fls_data);
2947         }
2948
2949         if (port_map_mask != 0)
2950                 status = dsp_free_ports(codec);
2951
2952         if (status < 0)
2953                 goto exit;
2954
2955         status = codec_set_converter_stream_channel(codec,
2956                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2957
2958 exit:
2959         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2960                 dspio_free_dma_chan(codec, dma_chan);
2961
2962         if (dma_engine->dmab->area)
2963                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2964         kfree(dma_engine->dmab);
2965         kfree(dma_engine);
2966
2967         return status;
2968 }
2969
2970 /*
2971  * CA0132 DSP download stuffs.
2972  */
2973 static void dspload_post_setup(struct hda_codec *codec)
2974 {
2975         struct ca0132_spec *spec = codec->spec;
2976         codec_dbg(codec, "---- dspload_post_setup ------\n");
2977         if (!spec->use_alt_functions) {
2978                 /*set DSP speaker to 2.0 configuration*/
2979                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2980                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2981
2982                 /*update write pointer*/
2983                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2984         }
2985 }
2986
2987 /**
2988  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2989  *
2990  * @codec: the HDA codec
2991  * @fls: pointer to a fast load image
2992  * @ovly: TRUE if overlay format is required
2993  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2994  *         no relocation
2995  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2996  * @router_chans: number of audio router channels to be allocated (0 means use
2997  *                internal defaults; max is 32)
2998  *
2999  * Download DSP from a DSP Image Fast Load structure. This structure is a
3000  * linear, non-constant sized element array of structures, each of which
3001  * contain the count of the data to be loaded, the data itself, and the
3002  * corresponding starting chip address of the starting data location.
3003  * Returns zero or a negative error code.
3004  */
3005 static int dspload_image(struct hda_codec *codec,
3006                         const struct dsp_image_seg *fls,
3007                         bool ovly,
3008                         unsigned int reloc,
3009                         bool autostart,
3010                         int router_chans)
3011 {
3012         int status = 0;
3013         unsigned int sample_rate;
3014         unsigned short channels;
3015
3016         codec_dbg(codec, "---- dspload_image begin ------\n");
3017         if (router_chans == 0) {
3018                 if (!ovly)
3019                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3020                 else
3021                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3022         }
3023
3024         sample_rate = 48000;
3025         channels = (unsigned short)router_chans;
3026
3027         while (channels > 16) {
3028                 sample_rate *= 2;
3029                 channels /= 2;
3030         }
3031
3032         do {
3033                 codec_dbg(codec, "Ready to program DMA\n");
3034                 if (!ovly)
3035                         status = dsp_reset(codec);
3036
3037                 if (status < 0)
3038                         break;
3039
3040                 codec_dbg(codec, "dsp_reset() complete\n");
3041                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3042                                       ovly);
3043
3044                 if (status < 0)
3045                         break;
3046
3047                 codec_dbg(codec, "dspxfr_image() complete\n");
3048                 if (autostart && !ovly) {
3049                         dspload_post_setup(codec);
3050                         status = dsp_set_run_state(codec);
3051                 }
3052
3053                 codec_dbg(codec, "LOAD FINISHED\n");
3054         } while (0);
3055
3056         return status;
3057 }
3058
3059 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3060 static bool dspload_is_loaded(struct hda_codec *codec)
3061 {
3062         unsigned int data = 0;
3063         int status = 0;
3064
3065         status = chipio_read(codec, 0x40004, &data);
3066         if ((status < 0) || (data != 1))
3067                 return false;
3068
3069         return true;
3070 }
3071 #else
3072 #define dspload_is_loaded(codec)        false
3073 #endif
3074
3075 static bool dspload_wait_loaded(struct hda_codec *codec)
3076 {
3077         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3078
3079         do {
3080                 if (dspload_is_loaded(codec)) {
3081                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3082                         return true;
3083                 }
3084                 msleep(20);
3085         } while (time_before(jiffies, timeout));
3086
3087         codec_err(codec, "ca0132 failed to download DSP\n");
3088         return false;
3089 }
3090
3091 /*
3092  * Setup GPIO for the other variants of Core3D.
3093  */
3094
3095 /*
3096  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3097  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3098  * The first eight bits are just the number of the pin. So far, I've only seen
3099  * this number go to 7.
3100  */
3101 static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3102                 bool enable)
3103 {
3104         struct ca0132_spec *spec = codec->spec;
3105         unsigned short gpio_data;
3106
3107         gpio_data = gpio_pin & 0xF;
3108         gpio_data |= ((enable << 8) & 0x100);
3109
3110         writew(gpio_data, spec->mem_base + 0x320);
3111 }
3112
3113 /*
3114  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3115  * the card shows as having no GPIO pins.
3116  */
3117 static void ca0132_gpio_init(struct hda_codec *codec)
3118 {
3119         struct ca0132_spec *spec = codec->spec;
3120
3121         switch (spec->quirk) {
3122         case QUIRK_SBZ:
3123                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3124                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3125                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3126                 break;
3127         case QUIRK_R3DI:
3128                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3129                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3130                 break;
3131         }
3132
3133 }
3134
3135 /* Sets the GPIO for audio output. */
3136 static void ca0132_gpio_setup(struct hda_codec *codec)
3137 {
3138         struct ca0132_spec *spec = codec->spec;
3139
3140         switch (spec->quirk) {
3141         case QUIRK_SBZ:
3142                 snd_hda_codec_write(codec, 0x01, 0,
3143                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3144                 snd_hda_codec_write(codec, 0x01, 0,
3145                                 AC_VERB_SET_GPIO_MASK, 0x07);
3146                 snd_hda_codec_write(codec, 0x01, 0,
3147                                 AC_VERB_SET_GPIO_DATA, 0x04);
3148                 snd_hda_codec_write(codec, 0x01, 0,
3149                                 AC_VERB_SET_GPIO_DATA, 0x06);
3150                 break;
3151         case QUIRK_R3DI:
3152                 snd_hda_codec_write(codec, 0x01, 0,
3153                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3154                 snd_hda_codec_write(codec, 0x01, 0,
3155                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3156                 snd_hda_codec_write(codec, 0x01, 0,
3157                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3158                 break;
3159         }
3160 }
3161
3162 /*
3163  * GPIO control functions for the Recon3D integrated.
3164  */
3165
3166 enum r3di_gpio_bit {
3167         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3168         R3DI_MIC_SELECT_BIT = 1,
3169         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3170         R3DI_OUT_SELECT_BIT = 2,
3171         /*
3172          * I dunno what this actually does, but it stays on until the dsp
3173          * is downloaded.
3174          */
3175         R3DI_GPIO_DSP_DOWNLOADING = 3,
3176         /*
3177          * Same as above, no clue what it does, but it comes on after the dsp
3178          * is downloaded.
3179          */
3180         R3DI_GPIO_DSP_DOWNLOADED = 4
3181 };
3182
3183 enum r3di_mic_select {
3184         /* Set GPIO bit 1 to 0 for rear mic */
3185         R3DI_REAR_MIC = 0,
3186         /* Set GPIO bit 1 to 1 for front microphone*/
3187         R3DI_FRONT_MIC = 1
3188 };
3189
3190 enum r3di_out_select {
3191         /* Set GPIO bit 2 to 0 for headphone */
3192         R3DI_HEADPHONE_OUT = 0,
3193         /* Set GPIO bit 2 to 1 for speaker */
3194         R3DI_LINE_OUT = 1
3195 };
3196 enum r3di_dsp_status {
3197         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3198         R3DI_DSP_DOWNLOADING = 0,
3199         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3200         R3DI_DSP_DOWNLOADED = 1
3201 };
3202
3203
3204 static void r3di_gpio_mic_set(struct hda_codec *codec,
3205                 enum r3di_mic_select cur_mic)
3206 {
3207         unsigned int cur_gpio;
3208
3209         /* Get the current GPIO Data setup */
3210         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3211
3212         switch (cur_mic) {
3213         case R3DI_REAR_MIC:
3214                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3215                 break;
3216         case R3DI_FRONT_MIC:
3217                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3218                 break;
3219         }
3220         snd_hda_codec_write(codec, codec->core.afg, 0,
3221                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3222 }
3223
3224 static void r3di_gpio_out_set(struct hda_codec *codec,
3225                 enum r3di_out_select cur_out)
3226 {
3227         unsigned int cur_gpio;
3228
3229         /* Get the current GPIO Data setup */
3230         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3231
3232         switch (cur_out) {
3233         case R3DI_HEADPHONE_OUT:
3234                 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3235                 break;
3236         case R3DI_LINE_OUT:
3237                 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3238                 break;
3239         }
3240         snd_hda_codec_write(codec, codec->core.afg, 0,
3241                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3242 }
3243
3244 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3245                 enum r3di_dsp_status dsp_status)
3246 {
3247         unsigned int cur_gpio;
3248
3249         /* Get the current GPIO Data setup */
3250         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3251
3252         switch (dsp_status) {
3253         case R3DI_DSP_DOWNLOADING:
3254                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3255                 snd_hda_codec_write(codec, codec->core.afg, 0,
3256                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3257                 break;
3258         case R3DI_DSP_DOWNLOADED:
3259                 /* Set DOWNLOADING bit to 0. */
3260                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3261
3262                 snd_hda_codec_write(codec, codec->core.afg, 0,
3263                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3264
3265                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3266                 break;
3267         }
3268
3269         snd_hda_codec_write(codec, codec->core.afg, 0,
3270                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3271 }
3272
3273 /*
3274  * PCM callbacks
3275  */
3276 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3277                         struct hda_codec *codec,
3278                         unsigned int stream_tag,
3279                         unsigned int format,
3280                         struct snd_pcm_substream *substream)
3281 {
3282         struct ca0132_spec *spec = codec->spec;
3283
3284         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3285
3286         return 0;
3287 }
3288
3289 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3290                         struct hda_codec *codec,
3291                         struct snd_pcm_substream *substream)
3292 {
3293         struct ca0132_spec *spec = codec->spec;
3294
3295         if (spec->dsp_state == DSP_DOWNLOADING)
3296                 return 0;
3297
3298         /*If Playback effects are on, allow stream some time to flush
3299          *effects tail*/
3300         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3301                 msleep(50);
3302
3303         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3304
3305         return 0;
3306 }
3307
3308 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3309                         struct hda_codec *codec,
3310                         struct snd_pcm_substream *substream)
3311 {
3312         struct ca0132_spec *spec = codec->spec;
3313         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3314         struct snd_pcm_runtime *runtime = substream->runtime;
3315
3316         if (spec->dsp_state != DSP_DOWNLOADED)
3317                 return 0;
3318
3319         /* Add latency if playback enhancement and either effect is enabled. */
3320         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3321                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3322                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3323                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3324         }
3325
3326         /* Applying Speaker EQ adds latency as well. */
3327         if (spec->cur_out_type == SPEAKER_OUT)
3328                 latency += DSP_SPEAKER_OUT_LATENCY;
3329
3330         return (latency * runtime->rate) / 1000;
3331 }
3332
3333 /*
3334  * Digital out
3335  */
3336 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3337                                         struct hda_codec *codec,
3338                                         struct snd_pcm_substream *substream)
3339 {
3340         struct ca0132_spec *spec = codec->spec;
3341         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3342 }
3343
3344 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3345                         struct hda_codec *codec,
3346                         unsigned int stream_tag,
3347                         unsigned int format,
3348                         struct snd_pcm_substream *substream)
3349 {
3350         struct ca0132_spec *spec = codec->spec;
3351         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3352                                              stream_tag, format, substream);
3353 }
3354
3355 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3356                         struct hda_codec *codec,
3357                         struct snd_pcm_substream *substream)
3358 {
3359         struct ca0132_spec *spec = codec->spec;
3360         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3361 }
3362
3363 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3364                                          struct hda_codec *codec,
3365                                          struct snd_pcm_substream *substream)
3366 {
3367         struct ca0132_spec *spec = codec->spec;
3368         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3369 }
3370
3371 /*
3372  * Analog capture
3373  */
3374 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3375                                         struct hda_codec *codec,
3376                                         unsigned int stream_tag,
3377                                         unsigned int format,
3378                                         struct snd_pcm_substream *substream)
3379 {
3380         snd_hda_codec_setup_stream(codec, hinfo->nid,
3381                                    stream_tag, 0, format);
3382
3383         return 0;
3384 }
3385
3386 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3387                         struct hda_codec *codec,
3388                         struct snd_pcm_substream *substream)
3389 {
3390         struct ca0132_spec *spec = codec->spec;
3391
3392         if (spec->dsp_state == DSP_DOWNLOADING)
3393                 return 0;
3394
3395         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3396         return 0;
3397 }
3398
3399 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3400                         struct hda_codec *codec,
3401                         struct snd_pcm_substream *substream)
3402 {
3403         struct ca0132_spec *spec = codec->spec;
3404         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3405         struct snd_pcm_runtime *runtime = substream->runtime;
3406
3407         if (spec->dsp_state != DSP_DOWNLOADED)
3408                 return 0;
3409
3410         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3411                 latency += DSP_CRYSTAL_VOICE_LATENCY;
3412
3413         return (latency * runtime->rate) / 1000;
3414 }
3415
3416 /*
3417  * Controls stuffs.
3418  */
3419
3420 /*
3421  * Mixer controls helpers.
3422  */
3423 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3424         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3425           .name = xname, \
3426           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3427           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3428                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3429                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3430           .info = ca0132_volume_info, \
3431           .get = ca0132_volume_get, \
3432           .put = ca0132_volume_put, \
3433           .tlv = { .c = ca0132_volume_tlv }, \
3434           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3435
3436 /*
3437  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3438  * volume put, which is used for setting the DSP volume. This was done because
3439  * the ca0132 functions were taking too much time and causing lag.
3440  */
3441 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3442         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3443           .name = xname, \
3444           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3445           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3446                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3447                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3448           .info = snd_hda_mixer_amp_volume_info, \
3449           .get = snd_hda_mixer_amp_volume_get, \
3450           .put = ca0132_alt_volume_put, \
3451           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3452           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3453
3454 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3455         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3456           .name = xname, \
3457           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3458           .info = snd_hda_mixer_amp_switch_info, \
3459           .get = ca0132_switch_get, \
3460           .put = ca0132_switch_put, \
3461           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3462
3463 /* stereo */
3464 #define CA0132_CODEC_VOL(xname, nid, dir) \
3465         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3466 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3467         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3468 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3469         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3470
3471 /* lookup tables */
3472 /*
3473  * Lookup table with decibel values for the DSP. When volume is changed in
3474  * Windows, the DSP is also sent the dB value in floating point. In Windows,
3475  * these values have decimal points, probably because the Windows driver
3476  * actually uses floating point. We can't here, so I made a lookup table of
3477  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3478  * DAC's, and 9 is the maximum.
3479  */
3480 static const unsigned int float_vol_db_lookup[] = {
3481 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3482 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3483 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3484 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3485 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3486 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3487 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3488 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3489 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3490 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3491 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3492 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3493 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3494 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3495 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3496 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3497 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3498 };
3499
3500 /*
3501  * This table counts from float 0 to 1 in increments of .01, which is
3502  * useful for a few different sliders.
3503  */
3504 static const unsigned int float_zero_to_one_lookup[] = {
3505 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3506 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3507 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3508 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3509 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3510 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3511 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3512 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3513 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3514 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3515 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3516 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3517 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3518 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3519 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3520 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3521 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3522 };
3523
3524 /*
3525  * This table counts from float 10 to 1000, which is the range of the x-bass
3526  * crossover slider in Windows.
3527  */
3528 static const unsigned int float_xbass_xover_lookup[] = {
3529 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3530 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3531 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3532 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3533 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3534 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3535 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3536 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3537 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3538 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3539 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3540 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3541 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3542 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3543 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3544 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3545 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3546 };
3547
3548 /* The following are for tuning of products */
3549 #ifdef ENABLE_TUNING_CONTROLS
3550
3551 static unsigned int voice_focus_vals_lookup[] = {
3552 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3553 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3554 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3555 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3556 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3557 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3558 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3559 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3560 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3561 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3562 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3563 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3564 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3565 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3566 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3567 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3568 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3569 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3570 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3571 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3572 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3573 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3574 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3575 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3576 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3577 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3578 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3579 };
3580
3581 static unsigned int mic_svm_vals_lookup[] = {
3582 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3583 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3584 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3585 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3586 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3587 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3588 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3589 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3590 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3591 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3592 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3593 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3594 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3595 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3596 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3597 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3598 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3599 };
3600
3601 static unsigned int equalizer_vals_lookup[] = {
3602 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3603 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3604 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3605 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3606 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3607 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3608 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3609 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3610 0x41C00000
3611 };
3612
3613 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3614                           unsigned int *lookup, int idx)
3615 {
3616         int i = 0;
3617
3618         for (i = 0; i < TUNING_CTLS_COUNT; i++)
3619                 if (nid == ca0132_tuning_ctls[i].nid)
3620                         break;
3621
3622         snd_hda_power_up(codec);
3623         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3624                         ca0132_tuning_ctls[i].req,
3625                         &(lookup[idx]), sizeof(unsigned int));
3626         snd_hda_power_down(codec);
3627
3628         return 1;
3629 }
3630
3631 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3632                           struct snd_ctl_elem_value *ucontrol)
3633 {
3634         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3635         struct ca0132_spec *spec = codec->spec;
3636         hda_nid_t nid = get_amp_nid(kcontrol);
3637         long *valp = ucontrol->value.integer.value;
3638         int idx = nid - TUNING_CTL_START_NID;
3639
3640         *valp = spec->cur_ctl_vals[idx];
3641         return 0;
3642 }
3643
3644 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3645                               struct snd_ctl_elem_info *uinfo)
3646 {
3647         int chs = get_amp_channels(kcontrol);
3648         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3649         uinfo->count = chs == 3 ? 2 : 1;
3650         uinfo->value.integer.min = 20;
3651         uinfo->value.integer.max = 180;
3652         uinfo->value.integer.step = 1;
3653
3654         return 0;
3655 }
3656
3657 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3658                                 struct snd_ctl_elem_value *ucontrol)
3659 {
3660         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3661         struct ca0132_spec *spec = codec->spec;
3662         hda_nid_t nid = get_amp_nid(kcontrol);
3663         long *valp = ucontrol->value.integer.value;
3664         int idx;
3665
3666         idx = nid - TUNING_CTL_START_NID;
3667         /* any change? */
3668         if (spec->cur_ctl_vals[idx] == *valp)
3669                 return 0;
3670
3671         spec->cur_ctl_vals[idx] = *valp;
3672
3673         idx = *valp - 20;
3674         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3675
3676         return 1;
3677 }
3678
3679 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3680                               struct snd_ctl_elem_info *uinfo)
3681 {
3682         int chs = get_amp_channels(kcontrol);
3683         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3684         uinfo->count = chs == 3 ? 2 : 1;
3685         uinfo->value.integer.min = 0;
3686         uinfo->value.integer.max = 100;
3687         uinfo->value.integer.step = 1;
3688
3689         return 0;
3690 }
3691
3692 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3693                                 struct snd_ctl_elem_value *ucontrol)
3694 {
3695         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3696         struct ca0132_spec *spec = codec->spec;
3697         hda_nid_t nid = get_amp_nid(kcontrol);
3698         long *valp = ucontrol->value.integer.value;
3699         int idx;
3700
3701         idx = nid - TUNING_CTL_START_NID;
3702         /* any change? */
3703         if (spec->cur_ctl_vals[idx] == *valp)
3704                 return 0;
3705
3706         spec->cur_ctl_vals[idx] = *valp;
3707
3708         idx = *valp;
3709         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3710
3711         return 0;
3712 }
3713
3714 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3715                               struct snd_ctl_elem_info *uinfo)
3716 {
3717         int chs = get_amp_channels(kcontrol);
3718         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3719         uinfo->count = chs == 3 ? 2 : 1;
3720         uinfo->value.integer.min = 0;
3721         uinfo->value.integer.max = 48;
3722         uinfo->value.integer.step = 1;
3723
3724         return 0;
3725 }
3726
3727 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3728                                 struct snd_ctl_elem_value *ucontrol)
3729 {
3730         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3731         struct ca0132_spec *spec = codec->spec;
3732         hda_nid_t nid = get_amp_nid(kcontrol);
3733         long *valp = ucontrol->value.integer.value;
3734         int idx;
3735
3736         idx = nid - TUNING_CTL_START_NID;
3737         /* any change? */
3738         if (spec->cur_ctl_vals[idx] == *valp)
3739                 return 0;
3740
3741         spec->cur_ctl_vals[idx] = *valp;
3742
3743         idx = *valp;
3744         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3745
3746         return 1;
3747 }
3748
3749 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3750 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3751
3752 static int add_tuning_control(struct hda_codec *codec,
3753                                 hda_nid_t pnid, hda_nid_t nid,
3754                                 const char *name, int dir)
3755 {
3756         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3757         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3758         struct snd_kcontrol_new knew =
3759                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3760
3761         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3762                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3763         knew.tlv.c = 0;
3764         knew.tlv.p = 0;
3765         switch (pnid) {
3766         case VOICE_FOCUS:
3767                 knew.info = voice_focus_ctl_info;
3768                 knew.get = tuning_ctl_get;
3769                 knew.put = voice_focus_ctl_put;
3770                 knew.tlv.p = voice_focus_db_scale;
3771                 break;
3772         case MIC_SVM:
3773                 knew.info = mic_svm_ctl_info;
3774                 knew.get = tuning_ctl_get;
3775                 knew.put = mic_svm_ctl_put;
3776                 break;
3777         case EQUALIZER:
3778                 knew.info = equalizer_ctl_info;
3779                 knew.get = tuning_ctl_get;
3780                 knew.put = equalizer_ctl_put;
3781                 knew.tlv.p = eq_db_scale;
3782                 break;
3783         default:
3784                 return 0;
3785         }
3786         knew.private_value =
3787                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3788         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3789         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3790 }
3791
3792 static int add_tuning_ctls(struct hda_codec *codec)
3793 {
3794         int i;
3795         int err;
3796
3797         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3798                 err = add_tuning_control(codec,
3799                                         ca0132_tuning_ctls[i].parent_nid,
3800                                         ca0132_tuning_ctls[i].nid,
3801                                         ca0132_tuning_ctls[i].name,
3802                                         ca0132_tuning_ctls[i].direct);
3803                 if (err < 0)
3804                         return err;
3805         }
3806
3807         return 0;
3808 }
3809
3810 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3811 {
3812         struct ca0132_spec *spec = codec->spec;
3813         int i;
3814
3815         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3816         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3817         /* SVM level defaults to 0.74. */
3818         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3819
3820         /* EQ defaults to 0dB. */
3821         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3822                 spec->cur_ctl_vals[i] = 24;
3823 }
3824 #endif /*ENABLE_TUNING_CONTROLS*/
3825
3826 /*
3827  * Select the active output.
3828  * If autodetect is enabled, output will be selected based on jack detection.
3829  * If jack inserted, headphone will be selected, else built-in speakers
3830  * If autodetect is disabled, output will be selected based on selection.
3831  */
3832 static int ca0132_select_out(struct hda_codec *codec)
3833 {
3834         struct ca0132_spec *spec = codec->spec;
3835         unsigned int pin_ctl;
3836         int jack_present;
3837         int auto_jack;
3838         unsigned int tmp;
3839         int err;
3840
3841         codec_dbg(codec, "ca0132_select_out\n");
3842
3843         snd_hda_power_up_pm(codec);
3844
3845         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3846
3847         if (auto_jack)
3848                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3849         else
3850                 jack_present =
3851                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3852
3853         if (jack_present)
3854                 spec->cur_out_type = HEADPHONE_OUT;
3855         else
3856                 spec->cur_out_type = SPEAKER_OUT;
3857
3858         if (spec->cur_out_type == SPEAKER_OUT) {
3859                 codec_dbg(codec, "ca0132_select_out speaker\n");
3860                 /*speaker out config*/
3861                 tmp = FLOAT_ONE;
3862                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3863                 if (err < 0)
3864                         goto exit;
3865                 /*enable speaker EQ*/
3866                 tmp = FLOAT_ONE;
3867                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3868                 if (err < 0)
3869                         goto exit;
3870
3871                 /* Setup EAPD */
3872                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3873                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3874                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3875                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3876                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3877                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3878                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3879                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3880
3881                 /* disable headphone node */
3882                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3883                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3884                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3885                                     pin_ctl & ~PIN_HP);
3886                 /* enable speaker node */
3887                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3888                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3889                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3890                                     pin_ctl | PIN_OUT);
3891         } else {
3892                 codec_dbg(codec, "ca0132_select_out hp\n");
3893                 /*headphone out config*/
3894                 tmp = FLOAT_ZERO;
3895                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3896                 if (err < 0)
3897                         goto exit;
3898                 /*disable speaker EQ*/
3899                 tmp = FLOAT_ZERO;
3900                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3901                 if (err < 0)
3902                         goto exit;
3903
3904                 /* Setup EAPD */
3905                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3906                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3907                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3908                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3909                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3910                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3911                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3912                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3913
3914                 /* disable speaker*/
3915                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3916                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3917                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3918                                     pin_ctl & ~PIN_HP);
3919                 /* enable headphone*/
3920                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3921                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3922                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3923                                     pin_ctl | PIN_HP);
3924         }
3925
3926 exit:
3927         snd_hda_power_down_pm(codec);
3928
3929         return err < 0 ? err : 0;
3930 }
3931
3932 /*
3933  * This function behaves similarly to the ca0132_select_out funciton above,
3934  * except with a few differences. It adds the ability to select the current
3935  * output with an enumerated control "output source" if the auto detect
3936  * mute switch is set to off. If the auto detect mute switch is enabled, it
3937  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3938  * It also adds the ability to auto-detect the front headphone port. The only
3939  * way to select surround is to disable auto detect, and set Surround with the
3940  * enumerated control.
3941  */
3942 static int ca0132_alt_select_out(struct hda_codec *codec)
3943 {
3944         struct ca0132_spec *spec = codec->spec;
3945         unsigned int pin_ctl;
3946         int jack_present;
3947         int auto_jack;
3948         unsigned int i;
3949         unsigned int tmp;
3950         int err;
3951         /* Default Headphone is rear headphone */
3952         hda_nid_t headphone_nid = spec->out_pins[1];
3953
3954         codec_dbg(codec, "%s\n", __func__);
3955
3956         snd_hda_power_up_pm(codec);
3957
3958         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3959
3960         /*
3961          * If headphone rear or front is plugged in, set to headphone.
3962          * If neither is plugged in, set to rear line out. Only if
3963          * hp/speaker auto detect is enabled.
3964          */
3965         if (auto_jack) {
3966                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3967                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3968
3969                 if (jack_present)
3970                         spec->cur_out_type = HEADPHONE_OUT;
3971                 else
3972                         spec->cur_out_type = SPEAKER_OUT;
3973         } else
3974                 spec->cur_out_type = spec->out_enum_val;
3975
3976         /* Begin DSP output switch */
3977         tmp = FLOAT_ONE;
3978         err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3979         if (err < 0)
3980                 goto exit;
3981
3982         switch (spec->cur_out_type) {
3983         case SPEAKER_OUT:
3984                 codec_dbg(codec, "%s speaker\n", __func__);
3985                 /*speaker out config*/
3986                 switch (spec->quirk) {
3987                 case QUIRK_SBZ:
3988                         ca0132_mmio_gpio_set(codec, 7, false);
3989                         ca0132_mmio_gpio_set(codec, 4, true);
3990                         ca0132_mmio_gpio_set(codec, 1, true);
3991                         chipio_set_control_param(codec, 0x0D, 0x18);
3992                         break;
3993                 case QUIRK_R3DI:
3994                         chipio_set_control_param(codec, 0x0D, 0x24);
3995                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3996                         break;
3997                 case QUIRK_R3D:
3998                         chipio_set_control_param(codec, 0x0D, 0x24);
3999                         ca0132_mmio_gpio_set(codec, 1, true);
4000                         break;
4001                 }
4002
4003                 /* disable headphone node */
4004                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4005                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4006                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4007                                     pin_ctl & ~PIN_HP);
4008                 /* enable line-out node */
4009                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4010                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4011                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4012                                     pin_ctl | PIN_OUT);
4013                 /* Enable EAPD */
4014                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4015                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4016
4017                 /* If PlayEnhancement is enabled, set different source */
4018                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4019                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4020                 else
4021                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4022                 break;
4023         case HEADPHONE_OUT:
4024                 codec_dbg(codec, "%s hp\n", __func__);
4025                 /* Headphone out config*/
4026                 switch (spec->quirk) {
4027                 case QUIRK_SBZ:
4028                         ca0132_mmio_gpio_set(codec, 7, true);
4029                         ca0132_mmio_gpio_set(codec, 4, true);
4030                         ca0132_mmio_gpio_set(codec, 1, false);
4031                         chipio_set_control_param(codec, 0x0D, 0x12);
4032                         break;
4033                 case QUIRK_R3DI:
4034                         chipio_set_control_param(codec, 0x0D, 0x21);
4035                         r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4036                         break;
4037                 case QUIRK_R3D:
4038                         chipio_set_control_param(codec, 0x0D, 0x21);
4039                         ca0132_mmio_gpio_set(codec, 0x1, false);
4040                         break;
4041                 }
4042
4043                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4044                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4045
4046                 /* disable speaker*/
4047                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4048                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4049                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4050                                 pin_ctl & ~PIN_HP);
4051
4052                 /* enable headphone, either front or rear */
4053
4054                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4055                         headphone_nid = spec->out_pins[2];
4056                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4057                         headphone_nid = spec->out_pins[1];
4058
4059                 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4060                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4061                 snd_hda_set_pin_ctl(codec, headphone_nid,
4062                                     pin_ctl | PIN_HP);
4063
4064                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4065                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4066                 else
4067                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4068                 break;
4069         case SURROUND_OUT:
4070                 codec_dbg(codec, "%s surround\n", __func__);
4071                 /* Surround out config*/
4072                 switch (spec->quirk) {
4073                 case QUIRK_SBZ:
4074                         ca0132_mmio_gpio_set(codec, 7, false);
4075                         ca0132_mmio_gpio_set(codec, 4, true);
4076                         ca0132_mmio_gpio_set(codec, 1, true);
4077                         chipio_set_control_param(codec, 0x0D, 0x18);
4078                         break;
4079                 case QUIRK_R3DI:
4080                         chipio_set_control_param(codec, 0x0D, 0x24);
4081                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4082                         break;
4083                 case QUIRK_R3D:
4084                         ca0132_mmio_gpio_set(codec, 1, true);
4085                         chipio_set_control_param(codec, 0x0D, 0x24);
4086                         break;
4087                 }
4088                 /* enable line out node */
4089                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4090                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4091                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4092                                                 pin_ctl | PIN_OUT);
4093                 /* Disable headphone out */
4094                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4095                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4096                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4097                                     pin_ctl & ~PIN_HP);
4098                 /* Enable EAPD on line out */
4099                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4100                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4101                 /* enable center/lfe out node */
4102                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4103                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4104                 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4105                                     pin_ctl | PIN_OUT);
4106                 /* Now set rear surround node as out. */
4107                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4108                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4109                 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4110                                     pin_ctl | PIN_OUT);
4111
4112                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4113                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4114                 else
4115                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4116                 break;
4117         }
4118
4119         /* run through the output dsp commands for line-out */
4120         for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4121                 err = dspio_set_uint_param(codec,
4122                 alt_out_presets[spec->cur_out_type].mids[i],
4123                 alt_out_presets[spec->cur_out_type].reqs[i],
4124                 alt_out_presets[spec->cur_out_type].vals[i]);
4125
4126                 if (err < 0)
4127                         goto exit;
4128         }
4129
4130 exit:
4131         snd_hda_power_down_pm(codec);
4132
4133         return err < 0 ? err : 0;
4134 }
4135
4136 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4137 {
4138         struct ca0132_spec *spec = container_of(
4139                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4140         struct hda_jack_tbl *jack;
4141
4142         if (spec->use_alt_functions)
4143                 ca0132_alt_select_out(spec->codec);
4144         else
4145                 ca0132_select_out(spec->codec);
4146
4147         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4148         if (jack) {
4149                 jack->block_report = 0;
4150                 snd_hda_jack_report_sync(spec->codec);
4151         }
4152 }
4153
4154 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4155 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4156 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4157 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4158 static int stop_mic1(struct hda_codec *codec);
4159 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4160 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4161
4162 /*
4163  * Select the active VIP source
4164  */
4165 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4166 {
4167         struct ca0132_spec *spec = codec->spec;
4168         unsigned int tmp;
4169
4170         if (spec->dsp_state != DSP_DOWNLOADED)
4171                 return 0;
4172
4173         /* if CrystalVoice if off, vipsource should be 0 */
4174         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4175             (val == 0)) {
4176                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4177                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4178                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4179                 if (spec->cur_mic_type == DIGITAL_MIC)
4180                         tmp = FLOAT_TWO;
4181                 else
4182                         tmp = FLOAT_ONE;
4183                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4184                 tmp = FLOAT_ZERO;
4185                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4186         } else {
4187                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4188                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4189                 if (spec->cur_mic_type == DIGITAL_MIC)
4190                         tmp = FLOAT_TWO;
4191                 else
4192                         tmp = FLOAT_ONE;
4193                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4194                 tmp = FLOAT_ONE;
4195                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4196                 msleep(20);
4197                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4198         }
4199
4200         return 1;
4201 }
4202
4203 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4204 {
4205         struct ca0132_spec *spec = codec->spec;
4206         unsigned int tmp;
4207
4208         if (spec->dsp_state != DSP_DOWNLOADED)
4209                 return 0;
4210
4211         codec_dbg(codec, "%s\n", __func__);
4212
4213         chipio_set_stream_control(codec, 0x03, 0);
4214         chipio_set_stream_control(codec, 0x04, 0);
4215
4216         /* if CrystalVoice is off, vipsource should be 0 */
4217         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4218             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4219                 codec_dbg(codec, "%s: off.", __func__);
4220                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4221
4222                 tmp = FLOAT_ZERO;
4223                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4224
4225                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4226                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4227                 if (spec->quirk == QUIRK_R3DI)
4228                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4229
4230
4231                 if (spec->in_enum_val == REAR_LINE_IN)
4232                         tmp = FLOAT_ZERO;
4233                 else {
4234                         if (spec->quirk == QUIRK_SBZ)
4235                                 tmp = FLOAT_THREE;
4236                         else
4237                                 tmp = FLOAT_ONE;
4238                 }
4239
4240                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4241
4242         } else {
4243                 codec_dbg(codec, "%s: on.", __func__);
4244                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4245                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4246                 if (spec->quirk == QUIRK_R3DI)
4247                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4248
4249                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4250                         tmp = FLOAT_TWO;
4251                 else
4252                         tmp = FLOAT_ONE;
4253                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4254
4255                 tmp = FLOAT_ONE;
4256                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4257
4258                 msleep(20);
4259                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4260         }
4261
4262         chipio_set_stream_control(codec, 0x03, 1);
4263         chipio_set_stream_control(codec, 0x04, 1);
4264
4265         return 1;
4266 }
4267
4268 /*
4269  * Select the active microphone.
4270  * If autodetect is enabled, mic will be selected based on jack detection.
4271  * If jack inserted, ext.mic will be selected, else built-in mic
4272  * If autodetect is disabled, mic will be selected based on selection.
4273  */
4274 static int ca0132_select_mic(struct hda_codec *codec)
4275 {
4276         struct ca0132_spec *spec = codec->spec;
4277         int jack_present;
4278         int auto_jack;
4279
4280         codec_dbg(codec, "ca0132_select_mic\n");
4281
4282         snd_hda_power_up_pm(codec);
4283
4284         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4285
4286         if (auto_jack)
4287                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4288         else
4289                 jack_present =
4290                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4291
4292         if (jack_present)
4293                 spec->cur_mic_type = LINE_MIC_IN;
4294         else
4295                 spec->cur_mic_type = DIGITAL_MIC;
4296
4297         if (spec->cur_mic_type == DIGITAL_MIC) {
4298                 /* enable digital Mic */
4299                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4300                 ca0132_set_dmic(codec, 1);
4301                 ca0132_mic_boost_set(codec, 0);
4302                 /* set voice focus */
4303                 ca0132_effects_set(codec, VOICE_FOCUS,
4304                                    spec->effects_switch
4305                                    [VOICE_FOCUS - EFFECT_START_NID]);
4306         } else {
4307                 /* disable digital Mic */
4308                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4309                 ca0132_set_dmic(codec, 0);
4310                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4311                 /* disable voice focus */
4312                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4313         }
4314
4315         snd_hda_power_down_pm(codec);
4316
4317         return 0;
4318 }
4319
4320 /*
4321  * Select the active input.
4322  * Mic detection isn't used, because it's kind of pointless on the SBZ.
4323  * The front mic has no jack-detection, so the only way to switch to it
4324  * is to do it manually in alsamixer.
4325  */
4326 static int ca0132_alt_select_in(struct hda_codec *codec)
4327 {
4328         struct ca0132_spec *spec = codec->spec;
4329         unsigned int tmp;
4330
4331         codec_dbg(codec, "%s\n", __func__);
4332
4333         snd_hda_power_up_pm(codec);
4334
4335         chipio_set_stream_control(codec, 0x03, 0);
4336         chipio_set_stream_control(codec, 0x04, 0);
4337
4338         spec->cur_mic_type = spec->in_enum_val;
4339
4340         switch (spec->cur_mic_type) {
4341         case REAR_MIC:
4342                 switch (spec->quirk) {
4343                 case QUIRK_SBZ:
4344                 case QUIRK_R3D:
4345                         ca0132_mmio_gpio_set(codec, 0, false);
4346                         tmp = FLOAT_THREE;
4347                         break;
4348                 case QUIRK_R3DI:
4349                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4350                         tmp = FLOAT_ONE;
4351                         break;
4352                 default:
4353                         tmp = FLOAT_ONE;
4354                         break;
4355                 }
4356
4357                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4358                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4359                 if (spec->quirk == QUIRK_R3DI)
4360                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4361
4362                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4363
4364                 chipio_set_stream_control(codec, 0x03, 1);
4365                 chipio_set_stream_control(codec, 0x04, 1);
4366
4367                 if (spec->quirk == QUIRK_SBZ) {
4368                         chipio_write(codec, 0x18B098, 0x0000000C);
4369                         chipio_write(codec, 0x18B09C, 0x0000000C);
4370                 }
4371                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4372                 break;
4373         case REAR_LINE_IN:
4374                 ca0132_mic_boost_set(codec, 0);
4375                 switch (spec->quirk) {
4376                 case QUIRK_SBZ:
4377                 case QUIRK_R3D:
4378                         ca0132_mmio_gpio_set(codec, 0, false);
4379                         break;
4380                 case QUIRK_R3DI:
4381                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4382                         break;
4383                 }
4384
4385                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4386                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4387                 if (spec->quirk == QUIRK_R3DI)
4388                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4389
4390                 tmp = FLOAT_ZERO;
4391                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4392
4393                 if (spec->quirk == QUIRK_SBZ) {
4394                         chipio_write(codec, 0x18B098, 0x00000000);
4395                         chipio_write(codec, 0x18B09C, 0x00000000);
4396                 }
4397
4398                 chipio_set_stream_control(codec, 0x03, 1);
4399                 chipio_set_stream_control(codec, 0x04, 1);
4400                 break;
4401         case FRONT_MIC:
4402                 switch (spec->quirk) {
4403                 case QUIRK_SBZ:
4404                 case QUIRK_R3D:
4405                         ca0132_mmio_gpio_set(codec, 0, true);
4406                         ca0132_mmio_gpio_set(codec, 5, false);
4407                         tmp = FLOAT_THREE;
4408                         break;
4409                 case QUIRK_R3DI:
4410                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4411                         tmp = FLOAT_ONE;
4412                         break;
4413                 default:
4414                         tmp = FLOAT_ONE;
4415                         break;
4416                 }
4417
4418                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4419                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4420                 if (spec->quirk == QUIRK_R3DI)
4421                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4422
4423                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4424
4425                 chipio_set_stream_control(codec, 0x03, 1);
4426                 chipio_set_stream_control(codec, 0x04, 1);
4427
4428                 if (spec->quirk == QUIRK_SBZ) {
4429                         chipio_write(codec, 0x18B098, 0x0000000C);
4430                         chipio_write(codec, 0x18B09C, 0x000000CC);
4431                 }
4432                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4433                 break;
4434         }
4435         ca0132_cvoice_switch_set(codec);
4436
4437         snd_hda_power_down_pm(codec);
4438         return 0;
4439
4440 }
4441
4442 /*
4443  * Check if VNODE settings take effect immediately.
4444  */
4445 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4446                                      hda_nid_t vnid,
4447                                      hda_nid_t *shared_nid)
4448 {
4449         struct ca0132_spec *spec = codec->spec;
4450         hda_nid_t nid;
4451
4452         switch (vnid) {
4453         case VNID_SPK:
4454                 nid = spec->shared_out_nid;
4455                 break;
4456         case VNID_MIC:
4457                 nid = spec->shared_mic_nid;
4458                 break;
4459         default:
4460                 return false;
4461         }
4462
4463         if (shared_nid)
4464                 *shared_nid = nid;
4465
4466         return true;
4467 }
4468
4469 /*
4470 * The following functions are control change helpers.
4471 * They return 0 if no changed.  Return 1 if changed.
4472 */
4473 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4474 {
4475         struct ca0132_spec *spec = codec->spec;
4476         unsigned int tmp;
4477
4478         /* based on CrystalVoice state to enable VoiceFX. */
4479         if (enable) {
4480                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4481                         FLOAT_ONE : FLOAT_ZERO;
4482         } else {
4483                 tmp = FLOAT_ZERO;
4484         }
4485
4486         dspio_set_uint_param(codec, ca0132_voicefx.mid,
4487                              ca0132_voicefx.reqs[0], tmp);
4488
4489         return 1;
4490 }
4491
4492 /*
4493  * Set the effects parameters
4494  */
4495 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4496 {
4497         struct ca0132_spec *spec = codec->spec;
4498         unsigned int on, tmp;
4499         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4500         int err = 0;
4501         int idx = nid - EFFECT_START_NID;
4502
4503         if ((idx < 0) || (idx >= num_fx))
4504                 return 0; /* no changed */
4505
4506         /* for out effect, qualify with PE */
4507         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4508                 /* if PE if off, turn off out effects. */
4509                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4510                         val = 0;
4511         }
4512
4513         /* for in effect, qualify with CrystalVoice */
4514         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4515                 /* if CrystalVoice if off, turn off in effects. */
4516                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4517                         val = 0;
4518
4519                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4520                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4521                         val = 0;
4522
4523                 /* If Voice Focus on SBZ, set to two channel. */
4524                 if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio)
4525                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4526                         if (spec->effects_switch[CRYSTAL_VOICE -
4527                                                  EFFECT_START_NID]) {
4528
4529                                 if (spec->effects_switch[VOICE_FOCUS -
4530                                                          EFFECT_START_NID]) {
4531                                         tmp = FLOAT_TWO;
4532                                         val = 1;
4533                                 } else
4534                                         tmp = FLOAT_ONE;
4535
4536                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4537                         }
4538                 }
4539                 /*
4540                  * For SBZ noise reduction, there's an extra command
4541                  * to module ID 0x47. No clue why.
4542                  */
4543                 if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio)
4544                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4545                         if (spec->effects_switch[CRYSTAL_VOICE -
4546                                                  EFFECT_START_NID]) {
4547                                 if (spec->effects_switch[NOISE_REDUCTION -
4548                                                          EFFECT_START_NID])
4549                                         tmp = FLOAT_ONE;
4550                                 else
4551                                         tmp = FLOAT_ZERO;
4552                         } else
4553                                 tmp = FLOAT_ZERO;
4554
4555                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4556                 }
4557
4558                 /* If rear line in disable effects. */
4559                 if (spec->use_alt_functions &&
4560                                 spec->in_enum_val == REAR_LINE_IN)
4561                         val = 0;
4562         }
4563
4564         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4565                     nid, val);
4566
4567         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4568         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4569                                    ca0132_effects[idx].reqs[0], on);
4570
4571         if (err < 0)
4572                 return 0; /* no changed */
4573
4574         return 1;
4575 }
4576
4577 /*
4578  * Turn on/off Playback Enhancements
4579  */
4580 static int ca0132_pe_switch_set(struct hda_codec *codec)
4581 {
4582         struct ca0132_spec *spec = codec->spec;
4583         hda_nid_t nid;
4584         int i, ret = 0;
4585
4586         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4587                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4588
4589         if (spec->use_alt_functions)
4590                 ca0132_alt_select_out(codec);
4591
4592         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4593         nid = OUT_EFFECT_START_NID;
4594         /* PE affects all out effects */
4595         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4596                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4597
4598         return ret;
4599 }
4600
4601 /* Check if Mic1 is streaming, if so, stop streaming */
4602 static int stop_mic1(struct hda_codec *codec)
4603 {
4604         struct ca0132_spec *spec = codec->spec;
4605         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4606                                                  AC_VERB_GET_CONV, 0);
4607         if (oldval != 0)
4608                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4609                                     AC_VERB_SET_CHANNEL_STREAMID,
4610                                     0);
4611         return oldval;
4612 }
4613
4614 /* Resume Mic1 streaming if it was stopped. */
4615 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4616 {
4617         struct ca0132_spec *spec = codec->spec;
4618         /* Restore the previous stream and channel */
4619         if (oldval != 0)
4620                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4621                                     AC_VERB_SET_CHANNEL_STREAMID,
4622                                     oldval);
4623 }
4624
4625 /*
4626  * Turn on/off CrystalVoice
4627  */
4628 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4629 {
4630         struct ca0132_spec *spec = codec->spec;
4631         hda_nid_t nid;
4632         int i, ret = 0;
4633         unsigned int oldval;
4634
4635         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4636                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4637
4638         i = IN_EFFECT_START_NID - EFFECT_START_NID;
4639         nid = IN_EFFECT_START_NID;
4640         /* CrystalVoice affects all in effects */
4641         for (; nid < IN_EFFECT_END_NID; nid++, i++)
4642                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4643
4644         /* including VoiceFX */
4645         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4646
4647         /* set correct vipsource */
4648         oldval = stop_mic1(codec);
4649         if (spec->use_alt_functions)
4650                 ret |= ca0132_alt_set_vipsource(codec, 1);
4651         else
4652                 ret |= ca0132_set_vipsource(codec, 1);
4653         resume_mic1(codec, oldval);
4654         return ret;
4655 }
4656
4657 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4658 {
4659         struct ca0132_spec *spec = codec->spec;
4660         int ret = 0;
4661
4662         if (val) /* on */
4663                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4664                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4665         else /* off */
4666                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4667                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4668
4669         return ret;
4670 }
4671
4672 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4673 {
4674         struct ca0132_spec *spec = codec->spec;
4675         int ret = 0;
4676
4677         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4678                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4679         return ret;
4680 }
4681
4682 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4683                                 struct snd_ctl_elem_value *ucontrol)
4684 {
4685         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4686         hda_nid_t nid = get_amp_nid(kcontrol);
4687         hda_nid_t shared_nid = 0;
4688         bool effective;
4689         int ret = 0;
4690         struct ca0132_spec *spec = codec->spec;
4691         int auto_jack;
4692
4693         if (nid == VNID_HP_SEL) {
4694                 auto_jack =
4695                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4696                 if (!auto_jack) {
4697                         if (spec->use_alt_functions)
4698                                 ca0132_alt_select_out(codec);
4699                         else
4700                                 ca0132_select_out(codec);
4701                 }
4702                 return 1;
4703         }
4704
4705         if (nid == VNID_AMIC1_SEL) {
4706                 auto_jack =
4707                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4708                 if (!auto_jack)
4709                         ca0132_select_mic(codec);
4710                 return 1;
4711         }
4712
4713         if (nid == VNID_HP_ASEL) {
4714                 if (spec->use_alt_functions)
4715                         ca0132_alt_select_out(codec);
4716                 else
4717                         ca0132_select_out(codec);
4718                 return 1;
4719         }
4720
4721         if (nid == VNID_AMIC1_ASEL) {
4722                 ca0132_select_mic(codec);
4723                 return 1;
4724         }
4725
4726         /* if effective conditions, then update hw immediately. */
4727         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4728         if (effective) {
4729                 int dir = get_amp_direction(kcontrol);
4730                 int ch = get_amp_channels(kcontrol);
4731                 unsigned long pval;
4732
4733                 mutex_lock(&codec->control_mutex);
4734                 pval = kcontrol->private_value;
4735                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4736                                                                 0, dir);
4737                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4738                 kcontrol->private_value = pval;
4739                 mutex_unlock(&codec->control_mutex);
4740         }
4741
4742         return ret;
4743 }
4744 /* End of control change helpers. */
4745 /*
4746  * Below I've added controls to mess with the effect levels, I've only enabled
4747  * them on the Sound Blaster Z, but they would probably also work on the
4748  * Chromebook. I figured they were probably tuned specifically for it, and left
4749  * out for a reason.
4750  */
4751
4752 /* Sets DSP effect level from the sliders above the controls */
4753 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4754                           const unsigned int *lookup, int idx)
4755 {
4756         int i = 0;
4757         unsigned int y;
4758         /*
4759          * For X_BASS, req 2 is actually crossover freq instead of
4760          * effect level
4761          */
4762         if (nid == X_BASS)
4763                 y = 2;
4764         else
4765                 y = 1;
4766
4767         snd_hda_power_up(codec);
4768         if (nid == XBASS_XOVER) {
4769                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4770                         if (ca0132_effects[i].nid == X_BASS)
4771                                 break;
4772
4773                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4774                                 ca0132_effects[i].reqs[1],
4775                                 &(lookup[idx - 1]), sizeof(unsigned int));
4776         } else {
4777                 /* Find the actual effect structure */
4778                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4779                         if (nid == ca0132_effects[i].nid)
4780                                 break;
4781
4782                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4783                                 ca0132_effects[i].reqs[y],
4784                                 &(lookup[idx]), sizeof(unsigned int));
4785         }
4786
4787         snd_hda_power_down(codec);
4788
4789         return 0;
4790 }
4791
4792 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4793                           struct snd_ctl_elem_value *ucontrol)
4794 {
4795         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4796         struct ca0132_spec *spec = codec->spec;
4797         long *valp = ucontrol->value.integer.value;
4798
4799         *valp = spec->xbass_xover_freq;
4800         return 0;
4801 }
4802
4803 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4804                           struct snd_ctl_elem_value *ucontrol)
4805 {
4806         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4807         struct ca0132_spec *spec = codec->spec;
4808         hda_nid_t nid = get_amp_nid(kcontrol);
4809         long *valp = ucontrol->value.integer.value;
4810         int idx = nid - OUT_EFFECT_START_NID;
4811
4812         *valp = spec->fx_ctl_val[idx];
4813         return 0;
4814 }
4815
4816 /*
4817  * The X-bass crossover starts at 10hz, so the min is 1. The
4818  * frequency is set in multiples of 10.
4819  */
4820 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4821                 struct snd_ctl_elem_info *uinfo)
4822 {
4823         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4824         uinfo->count = 1;
4825         uinfo->value.integer.min = 1;
4826         uinfo->value.integer.max = 100;
4827         uinfo->value.integer.step = 1;
4828
4829         return 0;
4830 }
4831
4832 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4833                 struct snd_ctl_elem_info *uinfo)
4834 {
4835         int chs = get_amp_channels(kcontrol);
4836
4837         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4838         uinfo->count = chs == 3 ? 2 : 1;
4839         uinfo->value.integer.min = 0;
4840         uinfo->value.integer.max = 100;
4841         uinfo->value.integer.step = 1;
4842
4843         return 0;
4844 }
4845
4846 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4847                                 struct snd_ctl_elem_value *ucontrol)
4848 {
4849         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4850         struct ca0132_spec *spec = codec->spec;
4851         hda_nid_t nid = get_amp_nid(kcontrol);
4852         long *valp = ucontrol->value.integer.value;
4853         int idx;
4854
4855         /* any change? */
4856         if (spec->xbass_xover_freq == *valp)
4857                 return 0;
4858
4859         spec->xbass_xover_freq = *valp;
4860
4861         idx = *valp;
4862         ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4863
4864         return 0;
4865 }
4866
4867 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4868                                 struct snd_ctl_elem_value *ucontrol)
4869 {
4870         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4871         struct ca0132_spec *spec = codec->spec;
4872         hda_nid_t nid = get_amp_nid(kcontrol);
4873         long *valp = ucontrol->value.integer.value;
4874         int idx;
4875
4876         idx = nid - EFFECT_START_NID;
4877         /* any change? */
4878         if (spec->fx_ctl_val[idx] == *valp)
4879                 return 0;
4880
4881         spec->fx_ctl_val[idx] = *valp;
4882
4883         idx = *valp;
4884         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4885
4886         return 0;
4887 }
4888
4889
4890 /*
4891  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4892  * only has off or full 30 dB, and didn't like making a volume slider that has
4893  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4894  */
4895 #define MIC_BOOST_NUM_OF_STEPS 4
4896 #define MIC_BOOST_ENUM_MAX_STRLEN 10
4897
4898 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4899                                  struct snd_ctl_elem_info *uinfo)
4900 {
4901         char *sfx = "dB";
4902         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4903
4904         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4905         uinfo->count = 1;
4906         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4907         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4908                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4909         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4910         strcpy(uinfo->value.enumerated.name, namestr);
4911         return 0;
4912 }
4913
4914 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4915                                 struct snd_ctl_elem_value *ucontrol)
4916 {
4917         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4918         struct ca0132_spec *spec = codec->spec;
4919
4920         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4921         return 0;
4922 }
4923
4924 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4925                                 struct snd_ctl_elem_value *ucontrol)
4926 {
4927         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4928         struct ca0132_spec *spec = codec->spec;
4929         int sel = ucontrol->value.enumerated.item[0];
4930         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4931
4932         if (sel >= items)
4933                 return 0;
4934
4935         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4936                     sel);
4937
4938         spec->mic_boost_enum_val = sel;
4939
4940         if (spec->in_enum_val != REAR_LINE_IN)
4941                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4942
4943         return 1;
4944 }
4945
4946
4947 /*
4948  * Input Select Control for alternative ca0132 codecs. This exists because
4949  * front microphone has no auto-detect, and we need a way to set the rear
4950  * as line-in
4951  */
4952 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4953                                  struct snd_ctl_elem_info *uinfo)
4954 {
4955         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4956         uinfo->count = 1;
4957         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4958         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4959                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4960         strcpy(uinfo->value.enumerated.name,
4961                         in_src_str[uinfo->value.enumerated.item]);
4962         return 0;
4963 }
4964
4965 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4966                                 struct snd_ctl_elem_value *ucontrol)
4967 {
4968         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4969         struct ca0132_spec *spec = codec->spec;
4970
4971         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4972         return 0;
4973 }
4974
4975 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4976                                 struct snd_ctl_elem_value *ucontrol)
4977 {
4978         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4979         struct ca0132_spec *spec = codec->spec;
4980         int sel = ucontrol->value.enumerated.item[0];
4981         unsigned int items = IN_SRC_NUM_OF_INPUTS;
4982
4983         if (sel >= items)
4984                 return 0;
4985
4986         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4987                     sel, in_src_str[sel]);
4988
4989         spec->in_enum_val = sel;
4990
4991         ca0132_alt_select_in(codec);
4992
4993         return 1;
4994 }
4995
4996 /* Sound Blaster Z Output Select Control */
4997 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4998                                  struct snd_ctl_elem_info *uinfo)
4999 {
5000         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5001         uinfo->count = 1;
5002         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5003         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5004                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5005         strcpy(uinfo->value.enumerated.name,
5006                         alt_out_presets[uinfo->value.enumerated.item].name);
5007         return 0;
5008 }
5009
5010 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5011                                 struct snd_ctl_elem_value *ucontrol)
5012 {
5013         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5014         struct ca0132_spec *spec = codec->spec;
5015
5016         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5017         return 0;
5018 }
5019
5020 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5021                                 struct snd_ctl_elem_value *ucontrol)
5022 {
5023         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5024         struct ca0132_spec *spec = codec->spec;
5025         int sel = ucontrol->value.enumerated.item[0];
5026         unsigned int items = NUM_OF_OUTPUTS;
5027         unsigned int auto_jack;
5028
5029         if (sel >= items)
5030                 return 0;
5031
5032         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5033                     sel, alt_out_presets[sel].name);
5034
5035         spec->out_enum_val = sel;
5036
5037         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5038
5039         if (!auto_jack)
5040                 ca0132_alt_select_out(codec);
5041
5042         return 1;
5043 }
5044
5045 /*
5046  * Smart Volume output setting control. Three different settings, Normal,
5047  * which takes the value from the smart volume slider. The two others, loud
5048  * and night, disregard the slider value and have uneditable values.
5049  */
5050 #define NUM_OF_SVM_SETTINGS 3
5051 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5052
5053 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5054                                  struct snd_ctl_elem_info *uinfo)
5055 {
5056         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5057         uinfo->count = 1;
5058         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5059         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5060                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5061         strcpy(uinfo->value.enumerated.name,
5062                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
5063         return 0;
5064 }
5065
5066 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5067                                 struct snd_ctl_elem_value *ucontrol)
5068 {
5069         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5070         struct ca0132_spec *spec = codec->spec;
5071
5072         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5073         return 0;
5074 }
5075
5076 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5077                                 struct snd_ctl_elem_value *ucontrol)
5078 {
5079         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5080         struct ca0132_spec *spec = codec->spec;
5081         int sel = ucontrol->value.enumerated.item[0];
5082         unsigned int items = NUM_OF_SVM_SETTINGS;
5083         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5084         unsigned int tmp;
5085
5086         if (sel >= items)
5087                 return 0;
5088
5089         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5090                     sel, out_svm_set_enum_str[sel]);
5091
5092         spec->smart_volume_setting = sel;
5093
5094         switch (sel) {
5095         case 0:
5096                 tmp = FLOAT_ZERO;
5097                 break;
5098         case 1:
5099                 tmp = FLOAT_ONE;
5100                 break;
5101         case 2:
5102                 tmp = FLOAT_TWO;
5103                 break;
5104         default:
5105                 tmp = FLOAT_ZERO;
5106                 break;
5107         }
5108         /* Req 2 is the Smart Volume Setting req. */
5109         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5110                         ca0132_effects[idx].reqs[2], tmp);
5111         return 1;
5112 }
5113
5114 /* Sound Blaster Z EQ preset controls */
5115 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5116                                  struct snd_ctl_elem_info *uinfo)
5117 {
5118         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5119
5120         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5121         uinfo->count = 1;
5122         uinfo->value.enumerated.items = items;
5123         if (uinfo->value.enumerated.item >= items)
5124                 uinfo->value.enumerated.item = items - 1;
5125         strcpy(uinfo->value.enumerated.name,
5126                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5127         return 0;
5128 }
5129
5130 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5131                                 struct snd_ctl_elem_value *ucontrol)
5132 {
5133         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5134         struct ca0132_spec *spec = codec->spec;
5135
5136         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5137         return 0;
5138 }
5139
5140 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5141                                 struct snd_ctl_elem_value *ucontrol)
5142 {
5143         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5144         struct ca0132_spec *spec = codec->spec;
5145         int i, err = 0;
5146         int sel = ucontrol->value.enumerated.item[0];
5147         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5148
5149         if (sel >= items)
5150                 return 0;
5151
5152         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5153                         ca0132_alt_eq_presets[sel].name);
5154         /*
5155          * Idx 0 is default.
5156          * Default needs to qualify with CrystalVoice state.
5157          */
5158         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5159                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5160                                 ca0132_alt_eq_enum.reqs[i],
5161                                 ca0132_alt_eq_presets[sel].vals[i]);
5162                 if (err < 0)
5163                         break;
5164         }
5165
5166         if (err >= 0)
5167                 spec->eq_preset_val = sel;
5168
5169         return 1;
5170 }
5171
5172 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5173                                  struct snd_ctl_elem_info *uinfo)
5174 {
5175         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5176
5177         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5178         uinfo->count = 1;
5179         uinfo->value.enumerated.items = items;
5180         if (uinfo->value.enumerated.item >= items)
5181                 uinfo->value.enumerated.item = items - 1;
5182         strcpy(uinfo->value.enumerated.name,
5183                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5184         return 0;
5185 }
5186
5187 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5188                                 struct snd_ctl_elem_value *ucontrol)
5189 {
5190         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5191         struct ca0132_spec *spec = codec->spec;
5192
5193         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5194         return 0;
5195 }
5196
5197 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5198                                 struct snd_ctl_elem_value *ucontrol)
5199 {
5200         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5201         struct ca0132_spec *spec = codec->spec;
5202         int i, err = 0;
5203         int sel = ucontrol->value.enumerated.item[0];
5204
5205         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5206                 return 0;
5207
5208         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5209                     sel, ca0132_voicefx_presets[sel].name);
5210
5211         /*
5212          * Idx 0 is default.
5213          * Default needs to qualify with CrystalVoice state.
5214          */
5215         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5216                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5217                                 ca0132_voicefx.reqs[i],
5218                                 ca0132_voicefx_presets[sel].vals[i]);
5219                 if (err < 0)
5220                         break;
5221         }
5222
5223         if (err >= 0) {
5224                 spec->voicefx_val = sel;
5225                 /* enable voice fx */
5226                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5227         }
5228
5229         return 1;
5230 }
5231
5232 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5233                                 struct snd_ctl_elem_value *ucontrol)
5234 {
5235         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5236         struct ca0132_spec *spec = codec->spec;
5237         hda_nid_t nid = get_amp_nid(kcontrol);
5238         int ch = get_amp_channels(kcontrol);
5239         long *valp = ucontrol->value.integer.value;
5240
5241         /* vnode */
5242         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5243                 if (ch & 1) {
5244                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5245                         valp++;
5246                 }
5247                 if (ch & 2) {
5248                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5249                         valp++;
5250                 }
5251                 return 0;
5252         }
5253
5254         /* effects, include PE and CrystalVoice */
5255         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5256                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5257                 return 0;
5258         }
5259
5260         /* mic boost */
5261         if (nid == spec->input_pins[0]) {
5262                 *valp = spec->cur_mic_boost;
5263                 return 0;
5264         }
5265
5266         return 0;
5267 }
5268
5269 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5270                              struct snd_ctl_elem_value *ucontrol)
5271 {
5272         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5273         struct ca0132_spec *spec = codec->spec;
5274         hda_nid_t nid = get_amp_nid(kcontrol);
5275         int ch = get_amp_channels(kcontrol);
5276         long *valp = ucontrol->value.integer.value;
5277         int changed = 1;
5278
5279         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5280                     nid, *valp);
5281
5282         snd_hda_power_up(codec);
5283         /* vnode */
5284         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5285                 if (ch & 1) {
5286                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5287                         valp++;
5288                 }
5289                 if (ch & 2) {
5290                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5291                         valp++;
5292                 }
5293                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5294                 goto exit;
5295         }
5296
5297         /* PE */
5298         if (nid == PLAY_ENHANCEMENT) {
5299                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5300                 changed = ca0132_pe_switch_set(codec);
5301                 goto exit;
5302         }
5303
5304         /* CrystalVoice */
5305         if (nid == CRYSTAL_VOICE) {
5306                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5307                 changed = ca0132_cvoice_switch_set(codec);
5308                 goto exit;
5309         }
5310
5311         /* out and in effects */
5312         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5313             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5314                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5315                 changed = ca0132_effects_set(codec, nid, *valp);
5316                 goto exit;
5317         }
5318
5319         /* mic boost */
5320         if (nid == spec->input_pins[0]) {
5321                 spec->cur_mic_boost = *valp;
5322                 if (spec->use_alt_functions) {
5323                         if (spec->in_enum_val != REAR_LINE_IN)
5324                                 changed = ca0132_mic_boost_set(codec, *valp);
5325                 } else {
5326                         /* Mic boost does not apply to Digital Mic */
5327                         if (spec->cur_mic_type != DIGITAL_MIC)
5328                                 changed = ca0132_mic_boost_set(codec, *valp);
5329                 }
5330
5331                 goto exit;
5332         }
5333
5334 exit:
5335         snd_hda_power_down(codec);
5336         return changed;
5337 }
5338
5339 /*
5340  * Volume related
5341  */
5342 /*
5343  * Sets the internal DSP decibel level to match the DAC for output, and the
5344  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5345  * all alternative codecs set DSP playback volume.
5346  */
5347 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5348 {
5349         struct ca0132_spec *spec = codec->spec;
5350         unsigned int dsp_dir;
5351         unsigned int lookup_val;
5352
5353         if (nid == VNID_SPK)
5354                 dsp_dir = DSP_VOL_OUT;
5355         else
5356                 dsp_dir = DSP_VOL_IN;
5357
5358         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5359
5360         dspio_set_uint_param(codec,
5361                 ca0132_alt_vol_ctls[dsp_dir].mid,
5362                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5363                 float_vol_db_lookup[lookup_val]);
5364
5365         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5366
5367         dspio_set_uint_param(codec,
5368                 ca0132_alt_vol_ctls[dsp_dir].mid,
5369                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5370                 float_vol_db_lookup[lookup_val]);
5371
5372         dspio_set_uint_param(codec,
5373                 ca0132_alt_vol_ctls[dsp_dir].mid,
5374                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5375 }
5376
5377 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5378                               struct snd_ctl_elem_info *uinfo)
5379 {
5380         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5381         struct ca0132_spec *spec = codec->spec;
5382         hda_nid_t nid = get_amp_nid(kcontrol);
5383         int ch = get_amp_channels(kcontrol);
5384         int dir = get_amp_direction(kcontrol);
5385         unsigned long pval;
5386         int err;
5387
5388         switch (nid) {
5389         case VNID_SPK:
5390                 /* follow shared_out info */
5391                 nid = spec->shared_out_nid;
5392                 mutex_lock(&codec->control_mutex);
5393                 pval = kcontrol->private_value;
5394                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5395                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5396                 kcontrol->private_value = pval;
5397                 mutex_unlock(&codec->control_mutex);
5398                 break;
5399         case VNID_MIC:
5400                 /* follow shared_mic info */
5401                 nid = spec->shared_mic_nid;
5402                 mutex_lock(&codec->control_mutex);
5403                 pval = kcontrol->private_value;
5404                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5405                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5406                 kcontrol->private_value = pval;
5407                 mutex_unlock(&codec->control_mutex);
5408                 break;
5409         default:
5410                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5411         }
5412         return err;
5413 }
5414
5415 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5416                                 struct snd_ctl_elem_value *ucontrol)
5417 {
5418         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5419         struct ca0132_spec *spec = codec->spec;
5420         hda_nid_t nid = get_amp_nid(kcontrol);
5421         int ch = get_amp_channels(kcontrol);
5422         long *valp = ucontrol->value.integer.value;
5423
5424         /* store the left and right volume */
5425         if (ch & 1) {
5426                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5427                 valp++;
5428         }
5429         if (ch & 2) {
5430                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5431                 valp++;
5432         }
5433         return 0;
5434 }
5435
5436 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5437                                 struct snd_ctl_elem_value *ucontrol)
5438 {
5439         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5440         struct ca0132_spec *spec = codec->spec;
5441         hda_nid_t nid = get_amp_nid(kcontrol);
5442         int ch = get_amp_channels(kcontrol);
5443         long *valp = ucontrol->value.integer.value;
5444         hda_nid_t shared_nid = 0;
5445         bool effective;
5446         int changed = 1;
5447
5448         /* store the left and right volume */
5449         if (ch & 1) {
5450                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5451                 valp++;
5452         }
5453         if (ch & 2) {
5454                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5455                 valp++;
5456         }
5457
5458         /* if effective conditions, then update hw immediately. */
5459         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5460         if (effective) {
5461                 int dir = get_amp_direction(kcontrol);
5462                 unsigned long pval;
5463
5464                 snd_hda_power_up(codec);
5465                 mutex_lock(&codec->control_mutex);
5466                 pval = kcontrol->private_value;
5467                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5468                                                                 0, dir);
5469                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5470                 kcontrol->private_value = pval;
5471                 mutex_unlock(&codec->control_mutex);
5472                 snd_hda_power_down(codec);
5473         }
5474
5475         return changed;
5476 }
5477
5478 /*
5479  * This function is the same as the one above, because using an if statement
5480  * inside of the above volume control for the DSP volume would cause too much
5481  * lag. This is a lot more smooth.
5482  */
5483 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5484                                 struct snd_ctl_elem_value *ucontrol)
5485 {
5486         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5487         struct ca0132_spec *spec = codec->spec;
5488         hda_nid_t nid = get_amp_nid(kcontrol);
5489         int ch = get_amp_channels(kcontrol);
5490         long *valp = ucontrol->value.integer.value;
5491         hda_nid_t vnid = 0;
5492         int changed = 1;
5493
5494         switch (nid) {
5495         case 0x02:
5496                 vnid = VNID_SPK;
5497                 break;
5498         case 0x07:
5499                 vnid = VNID_MIC;
5500                 break;
5501         }
5502
5503         /* store the left and right volume */
5504         if (ch & 1) {
5505                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5506                 valp++;
5507         }
5508         if (ch & 2) {
5509                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5510                 valp++;
5511         }
5512
5513         snd_hda_power_up(codec);
5514         ca0132_alt_dsp_volume_put(codec, vnid);
5515         mutex_lock(&codec->control_mutex);
5516         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5517         mutex_unlock(&codec->control_mutex);
5518         snd_hda_power_down(codec);
5519
5520         return changed;
5521 }
5522
5523 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5524                              unsigned int size, unsigned int __user *tlv)
5525 {
5526         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5527         struct ca0132_spec *spec = codec->spec;
5528         hda_nid_t nid = get_amp_nid(kcontrol);
5529         int ch = get_amp_channels(kcontrol);
5530         int dir = get_amp_direction(kcontrol);
5531         unsigned long pval;
5532         int err;
5533
5534         switch (nid) {
5535         case VNID_SPK:
5536                 /* follow shared_out tlv */
5537                 nid = spec->shared_out_nid;
5538                 mutex_lock(&codec->control_mutex);
5539                 pval = kcontrol->private_value;
5540                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5541                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5542                 kcontrol->private_value = pval;
5543                 mutex_unlock(&codec->control_mutex);
5544                 break;
5545         case VNID_MIC:
5546                 /* follow shared_mic tlv */
5547                 nid = spec->shared_mic_nid;
5548                 mutex_lock(&codec->control_mutex);
5549                 pval = kcontrol->private_value;
5550                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5551                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5552                 kcontrol->private_value = pval;
5553                 mutex_unlock(&codec->control_mutex);
5554                 break;
5555         default:
5556                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5557         }
5558         return err;
5559 }
5560
5561 /* Add volume slider control for effect level */
5562 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5563                                         const char *pfx, int dir)
5564 {
5565         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5566         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5567         struct snd_kcontrol_new knew =
5568                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5569
5570         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5571
5572         knew.tlv.c = NULL;
5573
5574         switch (nid) {
5575         case XBASS_XOVER:
5576                 knew.info = ca0132_alt_xbass_xover_slider_info;
5577                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5578                 knew.put = ca0132_alt_xbass_xover_slider_put;
5579                 break;
5580         default:
5581                 knew.info = ca0132_alt_effect_slider_info;
5582                 knew.get = ca0132_alt_slider_ctl_get;
5583                 knew.put = ca0132_alt_effect_slider_put;
5584                 knew.private_value =
5585                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5586                 break;
5587         }
5588
5589         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5590 }
5591
5592 /*
5593  * Added FX: prefix for the alternative codecs, because otherwise the surround
5594  * effect would conflict with the Surround sound volume control. Also seems more
5595  * clear as to what the switches do. Left alone for others.
5596  */
5597 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5598                          const char *pfx, int dir)
5599 {
5600         struct ca0132_spec *spec = codec->spec;
5601         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5602         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5603         struct snd_kcontrol_new knew =
5604                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5605         /* If using alt_controls, add FX: prefix. But, don't add FX:
5606          * prefix to OutFX or InFX enable controls.
5607          */
5608         if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5609                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5610         else
5611                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5612
5613         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5614 }
5615
5616 static int add_voicefx(struct hda_codec *codec)
5617 {
5618         struct snd_kcontrol_new knew =
5619                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5620                                     VOICEFX, 1, 0, HDA_INPUT);
5621         knew.info = ca0132_voicefx_info;
5622         knew.get = ca0132_voicefx_get;
5623         knew.put = ca0132_voicefx_put;
5624         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5625 }
5626
5627 /* Create the EQ Preset control */
5628 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5629 {
5630         struct snd_kcontrol_new knew =
5631                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5632                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5633         knew.info = ca0132_alt_eq_preset_info;
5634         knew.get = ca0132_alt_eq_preset_get;
5635         knew.put = ca0132_alt_eq_preset_put;
5636         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5637                                 snd_ctl_new1(&knew, codec));
5638 }
5639
5640 /*
5641  * Add enumerated control for the three different settings of the smart volume
5642  * output effect. Normal just uses the slider value, and loud and night are
5643  * their own things that ignore that value.
5644  */
5645 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5646 {
5647         struct snd_kcontrol_new knew =
5648                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5649                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5650         knew.info = ca0132_alt_svm_setting_info;
5651         knew.get = ca0132_alt_svm_setting_get;
5652         knew.put = ca0132_alt_svm_setting_put;
5653         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5654                                 snd_ctl_new1(&knew, codec));
5655
5656 }
5657
5658 /*
5659  * Create an Output Select enumerated control for codecs with surround
5660  * out capabilities.
5661  */
5662 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5663 {
5664         struct snd_kcontrol_new knew =
5665                 HDA_CODEC_MUTE_MONO("Output Select",
5666                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5667         knew.info = ca0132_alt_output_select_get_info;
5668         knew.get = ca0132_alt_output_select_get;
5669         knew.put = ca0132_alt_output_select_put;
5670         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5671                                 snd_ctl_new1(&knew, codec));
5672 }
5673
5674 /*
5675  * Create an Input Source enumerated control for the alternate ca0132 codecs
5676  * because the front microphone has no auto-detect, and Line-in has to be set
5677  * somehow.
5678  */
5679 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5680 {
5681         struct snd_kcontrol_new knew =
5682                 HDA_CODEC_MUTE_MONO("Input Source",
5683                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5684         knew.info = ca0132_alt_input_source_info;
5685         knew.get = ca0132_alt_input_source_get;
5686         knew.put = ca0132_alt_input_source_put;
5687         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5688                                 snd_ctl_new1(&knew, codec));
5689 }
5690
5691 /*
5692  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5693  * more control than the original mic boost, which is either full 30dB or off.
5694  */
5695 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5696 {
5697         struct snd_kcontrol_new knew =
5698                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5699                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5700         knew.info = ca0132_alt_mic_boost_info;
5701         knew.get = ca0132_alt_mic_boost_get;
5702         knew.put = ca0132_alt_mic_boost_put;
5703         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5704                                 snd_ctl_new1(&knew, codec));
5705
5706 }
5707
5708 /*
5709  * Need to create slave controls for the alternate codecs that have surround
5710  * capabilities.
5711  */
5712 static const char * const ca0132_alt_slave_pfxs[] = {
5713         "Front", "Surround", "Center", "LFE", NULL,
5714 };
5715
5716 /*
5717  * Also need special channel map, because the default one is incorrect.
5718  * I think this has to do with the pin for rear surround being 0x11,
5719  * and the center/lfe being 0x10. Usually the pin order is the opposite.
5720  */
5721 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5722         { .channels = 2,
5723           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5724         { .channels = 4,
5725           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5726                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5727         { .channels = 6,
5728           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5729                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5730                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5731         { }
5732 };
5733
5734 /* Add the correct chmap for streams with 6 channels. */
5735 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5736 {
5737         int err = 0;
5738         struct hda_pcm *pcm;
5739
5740         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5741                 struct hda_pcm_stream *hinfo =
5742                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5743                 struct snd_pcm_chmap *chmap;
5744                 const struct snd_pcm_chmap_elem *elem;
5745
5746                 elem = ca0132_alt_chmaps;
5747                 if (hinfo->channels_max == 6) {
5748                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
5749                                         SNDRV_PCM_STREAM_PLAYBACK,
5750                                         elem, hinfo->channels_max, 0, &chmap);
5751                         if (err < 0)
5752                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5753                 }
5754         }
5755 }
5756
5757 /*
5758  * When changing Node IDs for Mixer Controls below, make sure to update
5759  * Node IDs in ca0132_config() as well.
5760  */
5761 static const struct snd_kcontrol_new ca0132_mixer[] = {
5762         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5763         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5764         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5765         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5766         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5767         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5768         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5769         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5770         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5771                                0x12, 1, HDA_INPUT),
5772         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5773                                VNID_HP_SEL, 1, HDA_OUTPUT),
5774         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5775                                VNID_AMIC1_SEL, 1, HDA_INPUT),
5776         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5777                                VNID_HP_ASEL, 1, HDA_OUTPUT),
5778         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5779                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
5780         { } /* end */
5781 };
5782
5783 /*
5784  * Desktop specific control mixer. Removes auto-detect for mic, and adds
5785  * surround controls. Also sets both the Front Playback and Capture Volume
5786  * controls to alt so they set the DSP's decibel level.
5787  */
5788 static const struct snd_kcontrol_new desktop_mixer[] = {
5789         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5790         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5791         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5792         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5793         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5794         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5795         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5796         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5797         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5798         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5799         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5800         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5801         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5802                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5803         { } /* end */
5804 };
5805
5806 /*
5807  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5808  * because it doesn't set decibel levels for the DSP for capture.
5809  */
5810 static const struct snd_kcontrol_new r3di_mixer[] = {
5811         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5812         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5813         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5814         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5815         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5816         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5817         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5818         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5819         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5820         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5821         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5822         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5823         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5824                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5825         { } /* end */
5826 };
5827
5828 static int ca0132_build_controls(struct hda_codec *codec)
5829 {
5830         struct ca0132_spec *spec = codec->spec;
5831         int i, num_fx, num_sliders;
5832         int err = 0;
5833
5834         /* Add Mixer controls */
5835         for (i = 0; i < spec->num_mixers; i++) {
5836                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5837                 if (err < 0)
5838                         return err;
5839         }
5840         /* Setup vmaster with surround slaves for desktop ca0132 devices */
5841         if (spec->use_alt_functions) {
5842                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5843                                         spec->tlv);
5844                 snd_hda_add_vmaster(codec, "Master Playback Volume",
5845                                         spec->tlv, ca0132_alt_slave_pfxs,
5846                                         "Playback Volume");
5847                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5848                                             NULL, ca0132_alt_slave_pfxs,
5849                                             "Playback Switch",
5850                                             true, &spec->vmaster_mute.sw_kctl);
5851
5852         }
5853
5854         /* Add in and out effects controls.
5855          * VoiceFX, PE and CrystalVoice are added separately.
5856          */
5857         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5858         for (i = 0; i < num_fx; i++) {
5859                 /* Desktop cards break if Echo Cancellation is used. */
5860                 if (spec->use_pci_mmio) {
5861                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5862                                                 OUT_EFFECTS_COUNT))
5863                                 continue;
5864                 }
5865
5866                 err = add_fx_switch(codec, ca0132_effects[i].nid,
5867                                     ca0132_effects[i].name,
5868                                     ca0132_effects[i].direct);
5869                 if (err < 0)
5870                         return err;
5871         }
5872         /*
5873          * If codec has use_alt_controls set to true, add effect level sliders,
5874          * EQ presets, and Smart Volume presets. Also, change names to add FX
5875          * prefix, and change PlayEnhancement and CrystalVoice to match.
5876          */
5877         if (spec->use_alt_controls) {
5878                 ca0132_alt_add_svm_enum(codec);
5879                 add_ca0132_alt_eq_presets(codec);
5880                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5881                                         "Enable OutFX", 0);
5882                 if (err < 0)
5883                         return err;
5884
5885                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5886                                         "Enable InFX", 1);
5887                 if (err < 0)
5888                         return err;
5889
5890                 num_sliders = OUT_EFFECTS_COUNT - 1;
5891                 for (i = 0; i < num_sliders; i++) {
5892                         err = ca0132_alt_add_effect_slider(codec,
5893                                             ca0132_effects[i].nid,
5894                                             ca0132_effects[i].name,
5895                                             ca0132_effects[i].direct);
5896                         if (err < 0)
5897                                 return err;
5898                 }
5899
5900                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5901                                         "X-Bass Crossover", EFX_DIR_OUT);
5902
5903                 if (err < 0)
5904                         return err;
5905         } else {
5906                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5907                                         "PlayEnhancement", 0);
5908                 if (err < 0)
5909                         return err;
5910
5911                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5912                                         "CrystalVoice", 1);
5913                 if (err < 0)
5914                         return err;
5915         }
5916         add_voicefx(codec);
5917
5918         /*
5919          * If the codec uses alt_functions, you need the enumerated controls
5920          * to select the new outputs and inputs, plus add the new mic boost
5921          * setting control.
5922          */
5923         if (spec->use_alt_functions) {
5924                 ca0132_alt_add_output_enum(codec);
5925                 ca0132_alt_add_input_enum(codec);
5926                 ca0132_alt_add_mic_boost_enum(codec);
5927         }
5928 #ifdef ENABLE_TUNING_CONTROLS
5929         add_tuning_ctls(codec);
5930 #endif
5931
5932         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5933         if (err < 0)
5934                 return err;
5935
5936         if (spec->dig_out) {
5937                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5938                                                     spec->dig_out);
5939                 if (err < 0)
5940                         return err;
5941                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5942                 if (err < 0)
5943                         return err;
5944                 /* spec->multiout.share_spdif = 1; */
5945         }
5946
5947         if (spec->dig_in) {
5948                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5949                 if (err < 0)
5950                         return err;
5951         }
5952
5953         if (spec->use_alt_functions)
5954                 ca0132_alt_add_chmap_ctls(codec);
5955
5956         return 0;
5957 }
5958
5959 /*
5960  * PCM
5961  */
5962 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5963         .substreams = 1,
5964         .channels_min = 2,
5965         .channels_max = 6,
5966         .ops = {
5967                 .prepare = ca0132_playback_pcm_prepare,
5968                 .cleanup = ca0132_playback_pcm_cleanup,
5969                 .get_delay = ca0132_playback_pcm_delay,
5970         },
5971 };
5972
5973 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5974         .substreams = 1,
5975         .channels_min = 2,
5976         .channels_max = 2,
5977         .ops = {
5978                 .prepare = ca0132_capture_pcm_prepare,
5979                 .cleanup = ca0132_capture_pcm_cleanup,
5980                 .get_delay = ca0132_capture_pcm_delay,
5981         },
5982 };
5983
5984 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5985         .substreams = 1,
5986         .channels_min = 2,
5987         .channels_max = 2,
5988         .ops = {
5989                 .open = ca0132_dig_playback_pcm_open,
5990                 .close = ca0132_dig_playback_pcm_close,
5991                 .prepare = ca0132_dig_playback_pcm_prepare,
5992                 .cleanup = ca0132_dig_playback_pcm_cleanup
5993         },
5994 };
5995
5996 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
5997         .substreams = 1,
5998         .channels_min = 2,
5999         .channels_max = 2,
6000 };
6001
6002 static int ca0132_build_pcms(struct hda_codec *codec)
6003 {
6004         struct ca0132_spec *spec = codec->spec;
6005         struct hda_pcm *info;
6006
6007         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6008         if (!info)
6009                 return -ENOMEM;
6010         if (spec->use_alt_functions) {
6011                 info->own_chmap = true;
6012                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6013                         = ca0132_alt_chmaps;
6014         }
6015         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6016         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6017         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6018                 spec->multiout.max_channels;
6019         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6020         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6021         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6022
6023         /* With the DSP enabled, desktops don't use this ADC. */
6024         if (!spec->use_alt_functions) {
6025                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6026                 if (!info)
6027                         return -ENOMEM;
6028                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6029                         ca0132_pcm_analog_capture;
6030                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6031                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6032         }
6033
6034         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6035         if (!info)
6036                 return -ENOMEM;
6037         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6038         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6039         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6040
6041         if (!spec->dig_out && !spec->dig_in)
6042                 return 0;
6043
6044         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6045         if (!info)
6046                 return -ENOMEM;
6047         info->pcm_type = HDA_PCM_TYPE_SPDIF;
6048         if (spec->dig_out) {
6049                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6050                         ca0132_pcm_digital_playback;
6051                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6052         }
6053         if (spec->dig_in) {
6054                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6055                         ca0132_pcm_digital_capture;
6056                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6057         }
6058
6059         return 0;
6060 }
6061
6062 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6063 {
6064         if (pin) {
6065                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6066                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6067                         snd_hda_codec_write(codec, pin, 0,
6068                                             AC_VERB_SET_AMP_GAIN_MUTE,
6069                                             AMP_OUT_UNMUTE);
6070         }
6071         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6072                 snd_hda_codec_write(codec, dac, 0,
6073                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6074 }
6075
6076 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6077 {
6078         if (pin) {
6079                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6080                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6081                         snd_hda_codec_write(codec, pin, 0,
6082                                             AC_VERB_SET_AMP_GAIN_MUTE,
6083                                             AMP_IN_UNMUTE(0));
6084         }
6085         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6086                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6087                                     AMP_IN_UNMUTE(0));
6088
6089                 /* init to 0 dB and unmute. */
6090                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6091                                          HDA_AMP_VOLMASK, 0x5a);
6092                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6093                                          HDA_AMP_MUTE, 0);
6094         }
6095 }
6096
6097 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6098 {
6099         unsigned int caps;
6100
6101         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6102                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6103         snd_hda_override_amp_caps(codec, nid, dir, caps);
6104 }
6105
6106 /*
6107  * Switch between Digital built-in mic and analog mic.
6108  */
6109 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6110 {
6111         struct ca0132_spec *spec = codec->spec;
6112         unsigned int tmp;
6113         u8 val;
6114         unsigned int oldval;
6115
6116         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6117
6118         oldval = stop_mic1(codec);
6119         ca0132_set_vipsource(codec, 0);
6120         if (enable) {
6121                 /* set DMic input as 2-ch */
6122                 tmp = FLOAT_TWO;
6123                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6124
6125                 val = spec->dmic_ctl;
6126                 val |= 0x80;
6127                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6128                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6129
6130                 if (!(spec->dmic_ctl & 0x20))
6131                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6132         } else {
6133                 /* set AMic input as mono */
6134                 tmp = FLOAT_ONE;
6135                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6136
6137                 val = spec->dmic_ctl;
6138                 /* clear bit7 and bit5 to disable dmic */
6139                 val &= 0x5f;
6140                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6141                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6142
6143                 if (!(spec->dmic_ctl & 0x20))
6144                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6145         }
6146         ca0132_set_vipsource(codec, 1);
6147         resume_mic1(codec, oldval);
6148 }
6149
6150 /*
6151  * Initialization for Digital Mic.
6152  */
6153 static void ca0132_init_dmic(struct hda_codec *codec)
6154 {
6155         struct ca0132_spec *spec = codec->spec;
6156         u8 val;
6157
6158         /* Setup Digital Mic here, but don't enable.
6159          * Enable based on jack detect.
6160          */
6161
6162         /* MCLK uses MPIO1, set to enable.
6163          * Bit 2-0: MPIO select
6164          * Bit   3: set to disable
6165          * Bit 7-4: reserved
6166          */
6167         val = 0x01;
6168         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6169                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6170
6171         /* Data1 uses MPIO3. Data2 not use
6172          * Bit 2-0: Data1 MPIO select
6173          * Bit   3: set disable Data1
6174          * Bit 6-4: Data2 MPIO select
6175          * Bit   7: set disable Data2
6176          */
6177         val = 0x83;
6178         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6179                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
6180
6181         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6182          * Bit 3-0: Channel mask
6183          * Bit   4: set for 48KHz, clear for 32KHz
6184          * Bit   5: mode
6185          * Bit   6: set to select Data2, clear for Data1
6186          * Bit   7: set to enable DMic, clear for AMic
6187          */
6188         if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6189                 val = 0x33;
6190         else
6191                 val = 0x23;
6192         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6193         spec->dmic_ctl = val;
6194         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6195                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
6196 }
6197
6198 /*
6199  * Initialization for Analog Mic 2
6200  */
6201 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6202 {
6203         struct ca0132_spec *spec = codec->spec;
6204
6205         mutex_lock(&spec->chipio_mutex);
6206         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6207                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6208         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6209                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6210         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6211                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6212         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6213                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6214         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6215                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6216         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6217                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6218         mutex_unlock(&spec->chipio_mutex);
6219 }
6220
6221 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6222 {
6223         struct ca0132_spec *spec = codec->spec;
6224         int i;
6225
6226         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6227         snd_hda_codec_update_widgets(codec);
6228
6229         for (i = 0; i < spec->multiout.num_dacs; i++)
6230                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6231
6232         for (i = 0; i < spec->num_outputs; i++)
6233                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6234
6235         for (i = 0; i < spec->num_inputs; i++) {
6236                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6237                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6238         }
6239 }
6240
6241 /*
6242  * Recon3D r3d_setup_defaults sub functions.
6243  */
6244
6245 static void r3d_dsp_scp_startup(struct hda_codec *codec)
6246 {
6247         unsigned int tmp;
6248
6249         tmp = 0x00000000;
6250         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6251
6252         tmp = 0x00000001;
6253         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6254
6255         tmp = 0x00000004;
6256         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6257
6258         tmp = 0x00000005;
6259         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6260
6261         tmp = 0x00000000;
6262         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6263
6264 }
6265
6266 static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6267 {
6268         unsigned int tmp;
6269
6270         /* Mic 1 Setup */
6271         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6272         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6273         /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6274         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6275         tmp = FLOAT_ONE;
6276         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6277
6278         /* Mic 2 Setup, even though it isn't connected on SBZ */
6279         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6280         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6281         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6282         tmp = FLOAT_ZERO;
6283         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6284 }
6285
6286 /*
6287  * Initialize Sound Blaster Z analog microphones.
6288  */
6289 static void sbz_init_analog_mics(struct hda_codec *codec)
6290 {
6291         unsigned int tmp;
6292
6293         /* Mic 1 Setup */
6294         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6295         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6296         tmp = FLOAT_THREE;
6297         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6298
6299         /* Mic 2 Setup, even though it isn't connected on SBZ */
6300         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6301         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6302         tmp = FLOAT_ZERO;
6303         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6304
6305 }
6306
6307 /*
6308  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6309  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6310  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6311  * having an updated DAC, which changes the destination to that DAC.
6312  */
6313 static void sbz_connect_streams(struct hda_codec *codec)
6314 {
6315         struct ca0132_spec *spec = codec->spec;
6316
6317         mutex_lock(&spec->chipio_mutex);
6318
6319         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6320
6321         chipio_set_stream_channels(codec, 0x0C, 6);
6322         chipio_set_stream_control(codec, 0x0C, 1);
6323
6324         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6325         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6326
6327         /* Setup stream 0x14 with it's source and destination points */
6328         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6329         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6330         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6331         chipio_set_stream_channels(codec, 0x14, 2);
6332         chipio_set_stream_control(codec, 0x14, 1);
6333
6334         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6335
6336         mutex_unlock(&spec->chipio_mutex);
6337
6338 }
6339
6340 /*
6341  * Write data through ChipIO to setup proper stream destinations.
6342  * Not sure how it exactly works, but it seems to direct data
6343  * to different destinations. Example is f8 to c0, e0 to c0.
6344  * All I know is, if you don't set these, you get no sound.
6345  */
6346 static void sbz_chipio_startup_data(struct hda_codec *codec)
6347 {
6348         struct ca0132_spec *spec = codec->spec;
6349
6350         mutex_lock(&spec->chipio_mutex);
6351         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6352
6353         /* These control audio output */
6354         chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6355         chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6356         chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6357         chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6358         /* Signal to update I think */
6359         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6360
6361         chipio_set_stream_channels(codec, 0x0C, 6);
6362         chipio_set_stream_control(codec, 0x0C, 1);
6363         /* No clue what these control */
6364         chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6365         chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6366         chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6367         chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6368         chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6369         chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6370         chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6371         chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6372         chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6373         chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6374         chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6375         chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6376
6377         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6378
6379         codec_dbg(codec, "Startup Data exited, mutex released.\n");
6380         mutex_unlock(&spec->chipio_mutex);
6381 }
6382
6383 /*
6384  * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6385  * without a 0x20 source like normal.
6386  */
6387 static void sbz_dsp_scp_startup(struct hda_codec *codec)
6388 {
6389         unsigned int tmp;
6390
6391         tmp = 0x00000003;
6392         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6393
6394         tmp = 0x00000000;
6395         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6396
6397         tmp = 0x00000001;
6398         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6399
6400         tmp = 0x00000004;
6401         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6402
6403         tmp = 0x00000005;
6404         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6405
6406         tmp = 0x00000000;
6407         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6408
6409 }
6410
6411 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6412 {
6413         unsigned int tmp;
6414
6415         chipio_set_stream_control(codec, 0x03, 0);
6416         chipio_set_stream_control(codec, 0x04, 0);
6417
6418         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6419         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6420
6421         tmp = FLOAT_THREE;
6422         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6423
6424         chipio_set_stream_control(codec, 0x03, 1);
6425         chipio_set_stream_control(codec, 0x04, 1);
6426
6427         chipio_write(codec, 0x18b098, 0x0000000c);
6428         chipio_write(codec, 0x18b09C, 0x0000000c);
6429 }
6430
6431 /*
6432  * Setup default parameters for DSP
6433  */
6434 static void ca0132_setup_defaults(struct hda_codec *codec)
6435 {
6436         struct ca0132_spec *spec = codec->spec;
6437         unsigned int tmp;
6438         int num_fx;
6439         int idx, i;
6440
6441         if (spec->dsp_state != DSP_DOWNLOADED)
6442                 return;
6443
6444         /* out, in effects + voicefx */
6445         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6446         for (idx = 0; idx < num_fx; idx++) {
6447                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6448                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6449                                              ca0132_effects[idx].reqs[i],
6450                                              ca0132_effects[idx].def_vals[i]);
6451                 }
6452         }
6453
6454         /*remove DSP headroom*/
6455         tmp = FLOAT_ZERO;
6456         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6457
6458         /*set speaker EQ bypass attenuation*/
6459         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6460
6461         /* set AMic1 and AMic2 as mono mic */
6462         tmp = FLOAT_ONE;
6463         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6464         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6465
6466         /* set AMic1 as CrystalVoice input */
6467         tmp = FLOAT_ONE;
6468         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6469
6470         /* set WUH source */
6471         tmp = FLOAT_TWO;
6472         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6473 }
6474
6475 /*
6476  * Setup default parameters for Recon3D/Recon3Di DSP.
6477  */
6478
6479 static void r3d_setup_defaults(struct hda_codec *codec)
6480 {
6481         struct ca0132_spec *spec = codec->spec;
6482         unsigned int tmp;
6483         int num_fx;
6484         int idx, i;
6485
6486         if (spec->dsp_state != DSP_DOWNLOADED)
6487                 return;
6488
6489         r3d_dsp_scp_startup(codec);
6490
6491         r3d_dsp_initial_mic_setup(codec);
6492
6493         /*remove DSP headroom*/
6494         tmp = FLOAT_ZERO;
6495         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6496
6497         /* set WUH source */
6498         tmp = FLOAT_TWO;
6499         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6500         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6501
6502         /* Set speaker source? */
6503         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6504
6505         if (spec->quirk == QUIRK_R3DI)
6506                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6507
6508         /* Setup effect defaults */
6509         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6510         for (idx = 0; idx < num_fx; idx++) {
6511                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6512                         dspio_set_uint_param(codec,
6513                                         ca0132_effects[idx].mid,
6514                                         ca0132_effects[idx].reqs[i],
6515                                         ca0132_effects[idx].def_vals[i]);
6516                 }
6517         }
6518 }
6519
6520 /*
6521  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6522  * than the Chromebook setup.
6523  */
6524 static void sbz_setup_defaults(struct hda_codec *codec)
6525 {
6526         struct ca0132_spec *spec = codec->spec;
6527         unsigned int tmp, stream_format;
6528         int num_fx;
6529         int idx, i;
6530
6531         if (spec->dsp_state != DSP_DOWNLOADED)
6532                 return;
6533
6534         sbz_dsp_scp_startup(codec);
6535
6536         sbz_init_analog_mics(codec);
6537
6538         sbz_connect_streams(codec);
6539
6540         sbz_chipio_startup_data(codec);
6541
6542         chipio_set_stream_control(codec, 0x03, 1);
6543         chipio_set_stream_control(codec, 0x04, 1);
6544
6545         /*
6546          * Sets internal input loopback to off, used to have a switch to
6547          * enable input loopback, but turned out to be way too buggy.
6548          */
6549         tmp = FLOAT_ONE;
6550         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6551         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6552
6553         /*remove DSP headroom*/
6554         tmp = FLOAT_ZERO;
6555         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6556
6557         /* set WUH source */
6558         tmp = FLOAT_TWO;
6559         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6560         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6561
6562         /* Set speaker source? */
6563         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6564
6565         sbz_dsp_initial_mic_setup(codec);
6566
6567
6568         /* out, in effects + voicefx */
6569         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6570         for (idx = 0; idx < num_fx; idx++) {
6571                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6572                         dspio_set_uint_param(codec,
6573                                         ca0132_effects[idx].mid,
6574                                         ca0132_effects[idx].reqs[i],
6575                                         ca0132_effects[idx].def_vals[i]);
6576                 }
6577         }
6578
6579         /*
6580          * Have to make a stream to bind the sound output to, otherwise
6581          * you'll get dead audio. Before I did this, it would bind to an
6582          * audio input, and would never work
6583          */
6584         stream_format = snd_hdac_calc_stream_format(48000, 2,
6585                         SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6586
6587         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6588                                         0, stream_format);
6589
6590         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6591
6592         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6593                                         0, stream_format);
6594
6595         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6596 }
6597
6598 /*
6599  * Initialization of flags in chip
6600  */
6601 static void ca0132_init_flags(struct hda_codec *codec)
6602 {
6603         struct ca0132_spec *spec = codec->spec;
6604
6605         if (spec->use_alt_functions) {
6606                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6607                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6608                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6609                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6610                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6611                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6612                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6613                 chipio_set_control_flag(codec,
6614                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6615                 chipio_set_control_flag(codec,
6616                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6617         } else {
6618                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6619                 chipio_set_control_flag(codec,
6620                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6621                 chipio_set_control_flag(codec,
6622                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6623                 chipio_set_control_flag(codec,
6624                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6625                 chipio_set_control_flag(codec,
6626                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6627                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6628         }
6629 }
6630
6631 /*
6632  * Initialization of parameters in chip
6633  */
6634 static void ca0132_init_params(struct hda_codec *codec)
6635 {
6636         struct ca0132_spec *spec = codec->spec;
6637
6638         if (spec->use_alt_functions) {
6639                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6640                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6641                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6642                 chipio_set_control_param(codec, 0, 0);
6643                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6644         }
6645
6646         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6647         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6648 }
6649
6650 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6651 {
6652         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6653         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6654         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6655         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6656         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6657         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6658
6659         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6660         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6661         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6662 }
6663
6664 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6665 {
6666         bool dsp_loaded = false;
6667         struct ca0132_spec *spec = codec->spec;
6668         const struct dsp_image_seg *dsp_os_image;
6669         const struct firmware *fw_entry;
6670         /*
6671          * Alternate firmwares for different variants. The Recon3Di apparently
6672          * can use the default firmware, but I'll leave the option in case
6673          * it needs it again.
6674          */
6675         switch (spec->quirk) {
6676         case QUIRK_SBZ:
6677                 if (reject_firmware(&fw_entry, SBZ_EFX_FILE,
6678                                         codec->card->dev) != 0) {
6679                         codec_dbg(codec, "SBZ alt firmware not detected. ");
6680                         spec->alt_firmware_present = false;
6681                 } else {
6682                         codec_dbg(codec, "Sound Blaster Z firmware selected.");
6683                         spec->alt_firmware_present = true;
6684                 }
6685                 break;
6686         case QUIRK_R3DI:
6687                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
6688                                         codec->card->dev) != 0) {
6689                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
6690                         spec->alt_firmware_present = false;
6691                 } else {
6692                         codec_dbg(codec, "Recon3Di firmware selected.");
6693                         spec->alt_firmware_present = true;
6694                 }
6695                 break;
6696         default:
6697                 spec->alt_firmware_present = false;
6698                 break;
6699         }
6700 /*(DEBLOBBED)*/
6701         if (!spec->alt_firmware_present) {
6702                 codec_dbg(codec, "Default firmware selected.");
6703                 if (reject_firmware(&fw_entry, EFX_FILE,
6704                                         codec->card->dev) != 0)
6705                         return false;
6706         }
6707
6708         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6709         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6710                 codec_err(codec, "ca0132 DSP load image failed\n");
6711                 goto exit_download;
6712         }
6713
6714         dsp_loaded = dspload_wait_loaded(codec);
6715
6716 exit_download:
6717         release_firmware(fw_entry);
6718
6719         return dsp_loaded;
6720 }
6721
6722 static void ca0132_download_dsp(struct hda_codec *codec)
6723 {
6724         struct ca0132_spec *spec = codec->spec;
6725
6726 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6727         return; /* NOP */
6728 #endif
6729
6730         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6731                 return; /* don't retry failures */
6732
6733         chipio_enable_clocks(codec);
6734         if (spec->dsp_state != DSP_DOWNLOADED) {
6735                 spec->dsp_state = DSP_DOWNLOADING;
6736
6737                 if (!ca0132_download_dsp_images(codec))
6738                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
6739                 else
6740                         spec->dsp_state = DSP_DOWNLOADED;
6741         }
6742
6743         /* For codecs using alt functions, this is already done earlier */
6744         if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6745                 ca0132_set_dsp_msr(codec, true);
6746 }
6747
6748 static void ca0132_process_dsp_response(struct hda_codec *codec,
6749                                         struct hda_jack_callback *callback)
6750 {
6751         struct ca0132_spec *spec = codec->spec;
6752
6753         codec_dbg(codec, "ca0132_process_dsp_response\n");
6754         snd_hda_power_up_pm(codec);
6755         if (spec->wait_scp) {
6756                 if (dspio_get_response_data(codec) >= 0)
6757                         spec->wait_scp = 0;
6758         }
6759
6760         dspio_clear_response_queue(codec);
6761         snd_hda_power_down_pm(codec);
6762 }
6763
6764 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6765 {
6766         struct ca0132_spec *spec = codec->spec;
6767         struct hda_jack_tbl *tbl;
6768
6769         /* Delay enabling the HP amp, to let the mic-detection
6770          * state machine run.
6771          */
6772         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6773         if (tbl)
6774                 tbl->block_report = 1;
6775         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6776 }
6777
6778 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6779 {
6780         struct ca0132_spec *spec = codec->spec;
6781
6782         if (spec->use_alt_functions)
6783                 ca0132_alt_select_in(codec);
6784         else
6785                 ca0132_select_mic(codec);
6786 }
6787
6788 static void ca0132_init_unsol(struct hda_codec *codec)
6789 {
6790         struct ca0132_spec *spec = codec->spec;
6791         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6792         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6793                                             amic_callback);
6794         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6795                                             ca0132_process_dsp_response);
6796         /* Front headphone jack detection */
6797         if (spec->use_alt_functions)
6798                 snd_hda_jack_detect_enable_callback(codec,
6799                         spec->unsol_tag_front_hp, hp_callback);
6800 }
6801
6802 /*
6803  * Verbs tables.
6804  */
6805
6806 /* Sends before DSP download. */
6807 static struct hda_verb ca0132_base_init_verbs[] = {
6808         /*enable ct extension*/
6809         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6810         {}
6811 };
6812
6813 /* Send at exit. */
6814 static struct hda_verb ca0132_base_exit_verbs[] = {
6815         /*set afg to D3*/
6816         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6817         /*disable ct extension*/
6818         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6819         {}
6820 };
6821
6822 /* Other verbs tables. Sends after DSP download. */
6823
6824 static struct hda_verb ca0132_init_verbs0[] = {
6825         /* chip init verbs */
6826         {0x15, 0x70D, 0xF0},
6827         {0x15, 0x70E, 0xFE},
6828         {0x15, 0x707, 0x75},
6829         {0x15, 0x707, 0xD3},
6830         {0x15, 0x707, 0x09},
6831         {0x15, 0x707, 0x53},
6832         {0x15, 0x707, 0xD4},
6833         {0x15, 0x707, 0xEF},
6834         {0x15, 0x707, 0x75},
6835         {0x15, 0x707, 0xD3},
6836         {0x15, 0x707, 0x09},
6837         {0x15, 0x707, 0x02},
6838         {0x15, 0x707, 0x37},
6839         {0x15, 0x707, 0x78},
6840         {0x15, 0x53C, 0xCE},
6841         {0x15, 0x575, 0xC9},
6842         {0x15, 0x53D, 0xCE},
6843         {0x15, 0x5B7, 0xC9},
6844         {0x15, 0x70D, 0xE8},
6845         {0x15, 0x70E, 0xFE},
6846         {0x15, 0x707, 0x02},
6847         {0x15, 0x707, 0x68},
6848         {0x15, 0x707, 0x62},
6849         {0x15, 0x53A, 0xCE},
6850         {0x15, 0x546, 0xC9},
6851         {0x15, 0x53B, 0xCE},
6852         {0x15, 0x5E8, 0xC9},
6853         {}
6854 };
6855
6856 /* Extra init verbs for desktop cards. */
6857 static struct hda_verb ca0132_init_verbs1[] = {
6858         {0x15, 0x70D, 0x20},
6859         {0x15, 0x70E, 0x19},
6860         {0x15, 0x707, 0x00},
6861         {0x15, 0x539, 0xCE},
6862         {0x15, 0x546, 0xC9},
6863         {0x15, 0x70D, 0xB7},
6864         {0x15, 0x70E, 0x09},
6865         {0x15, 0x707, 0x10},
6866         {0x15, 0x70D, 0xAF},
6867         {0x15, 0x70E, 0x09},
6868         {0x15, 0x707, 0x01},
6869         {0x15, 0x707, 0x05},
6870         {0x15, 0x70D, 0x73},
6871         {0x15, 0x70E, 0x09},
6872         {0x15, 0x707, 0x14},
6873         {0x15, 0x6FF, 0xC4},
6874         {}
6875 };
6876
6877 static void ca0132_init_chip(struct hda_codec *codec)
6878 {
6879         struct ca0132_spec *spec = codec->spec;
6880         int num_fx;
6881         int i;
6882         unsigned int on;
6883
6884         mutex_init(&spec->chipio_mutex);
6885
6886         spec->cur_out_type = SPEAKER_OUT;
6887         if (!spec->use_alt_functions)
6888                 spec->cur_mic_type = DIGITAL_MIC;
6889         else
6890                 spec->cur_mic_type = REAR_MIC;
6891
6892         spec->cur_mic_boost = 0;
6893
6894         for (i = 0; i < VNODES_COUNT; i++) {
6895                 spec->vnode_lvol[i] = 0x5a;
6896                 spec->vnode_rvol[i] = 0x5a;
6897                 spec->vnode_lswitch[i] = 0;
6898                 spec->vnode_rswitch[i] = 0;
6899         }
6900
6901         /*
6902          * Default states for effects are in ca0132_effects[].
6903          */
6904         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6905         for (i = 0; i < num_fx; i++) {
6906                 on = (unsigned int)ca0132_effects[i].reqs[0];
6907                 spec->effects_switch[i] = on ? 1 : 0;
6908         }
6909         /*
6910          * Sets defaults for the effect slider controls, only for alternative
6911          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6912          */
6913         if (spec->use_alt_controls) {
6914                 spec->xbass_xover_freq = 8;
6915                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6916                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
6917         }
6918
6919         spec->voicefx_val = 0;
6920         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6921         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6922
6923 #ifdef ENABLE_TUNING_CONTROLS
6924         ca0132_init_tuning_defaults(codec);
6925 #endif
6926 }
6927
6928 /*
6929  * Recon3Di exit specific commands.
6930  */
6931 /* prevents popping noise on shutdown */
6932 static void r3di_gpio_shutdown(struct hda_codec *codec)
6933 {
6934         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6935 }
6936
6937 /*
6938  * Sound Blaster Z exit specific commands.
6939  */
6940 static void sbz_region2_exit(struct hda_codec *codec)
6941 {
6942         struct ca0132_spec *spec = codec->spec;
6943         unsigned int i;
6944
6945         for (i = 0; i < 4; i++)
6946                 writeb(0x0, spec->mem_base + 0x100);
6947         for (i = 0; i < 8; i++)
6948                 writeb(0xb3, spec->mem_base + 0x304);
6949
6950         ca0132_mmio_gpio_set(codec, 0, false);
6951         ca0132_mmio_gpio_set(codec, 1, false);
6952         ca0132_mmio_gpio_set(codec, 4, true);
6953         ca0132_mmio_gpio_set(codec, 5, false);
6954         ca0132_mmio_gpio_set(codec, 7, false);
6955 }
6956
6957 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6958 {
6959         hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6960         unsigned int i;
6961
6962         snd_hda_codec_write(codec, 0x11, 0,
6963                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6964
6965         for (i = 0; i < 5; i++)
6966                 snd_hda_codec_write(codec, pins[i], 0,
6967                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6968 }
6969
6970 static void ca0132_clear_unsolicited(struct hda_codec *codec)
6971 {
6972         hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6973         unsigned int i;
6974
6975         for (i = 0; i < 7; i++) {
6976                 snd_hda_codec_write(codec, pins[i], 0,
6977                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6978         }
6979 }
6980
6981 /* On shutdown, sends commands in sets of three */
6982 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6983                                                         int mask, int data)
6984 {
6985         if (dir >= 0)
6986                 snd_hda_codec_write(codec, 0x01, 0,
6987                                 AC_VERB_SET_GPIO_DIRECTION, dir);
6988         if (mask >= 0)
6989                 snd_hda_codec_write(codec, 0x01, 0,
6990                                 AC_VERB_SET_GPIO_MASK, mask);
6991
6992         if (data >= 0)
6993                 snd_hda_codec_write(codec, 0x01, 0,
6994                                 AC_VERB_SET_GPIO_DATA, data);
6995 }
6996
6997 static void sbz_exit_chip(struct hda_codec *codec)
6998 {
6999         chipio_set_stream_control(codec, 0x03, 0);
7000         chipio_set_stream_control(codec, 0x04, 0);
7001
7002         /* Mess with GPIO */
7003         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7004         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7005         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7006
7007         chipio_set_stream_control(codec, 0x14, 0);
7008         chipio_set_stream_control(codec, 0x0C, 0);
7009
7010         chipio_set_conn_rate(codec, 0x41, SR_192_000);
7011         chipio_set_conn_rate(codec, 0x91, SR_192_000);
7012
7013         chipio_write(codec, 0x18a020, 0x00000083);
7014
7015         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7016         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7017         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7018
7019         chipio_set_stream_control(codec, 0x0C, 0);
7020
7021         chipio_set_control_param(codec, 0x0D, 0x24);
7022
7023         ca0132_clear_unsolicited(codec);
7024         sbz_set_pin_ctl_default(codec);
7025
7026         snd_hda_codec_write(codec, 0x0B, 0,
7027                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7028
7029         sbz_region2_exit(codec);
7030 }
7031
7032 static void r3d_exit_chip(struct hda_codec *codec)
7033 {
7034         ca0132_clear_unsolicited(codec);
7035         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7036         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7037 }
7038
7039 static void ca0132_exit_chip(struct hda_codec *codec)
7040 {
7041         /* put any chip cleanup stuffs here. */
7042
7043         if (dspload_is_loaded(codec))
7044                 dsp_reset(codec);
7045 }
7046
7047 /*
7048  * This fixes a problem that was hard to reproduce. Very rarely, I would
7049  * boot up, and there would be no sound, but the DSP indicated it had loaded
7050  * properly. I did a few memory dumps to see if anything was different, and
7051  * there were a few areas of memory uninitialized with a1a2a3a4. This function
7052  * checks if those areas are uninitialized, and if they are, it'll attempt to
7053  * reload the card 3 times. Usually it fixes by the second.
7054  */
7055 static void sbz_dsp_startup_check(struct hda_codec *codec)
7056 {
7057         struct ca0132_spec *spec = codec->spec;
7058         unsigned int dsp_data_check[4];
7059         unsigned int cur_address = 0x390;
7060         unsigned int i;
7061         unsigned int failure = 0;
7062         unsigned int reload = 3;
7063
7064         if (spec->startup_check_entered)
7065                 return;
7066
7067         spec->startup_check_entered = true;
7068
7069         for (i = 0; i < 4; i++) {
7070                 chipio_read(codec, cur_address, &dsp_data_check[i]);
7071                 cur_address += 0x4;
7072         }
7073         for (i = 0; i < 4; i++) {
7074                 if (dsp_data_check[i] == 0xa1a2a3a4)
7075                         failure = 1;
7076         }
7077
7078         codec_dbg(codec, "Startup Check: %d ", failure);
7079         if (failure)
7080                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7081         /*
7082          * While the failure condition is true, and we haven't reached our
7083          * three reload limit, continue trying to reload the driver and
7084          * fix the issue.
7085          */
7086         while (failure && (reload != 0)) {
7087                 codec_info(codec, "Reloading... Tries left: %d", reload);
7088                 sbz_exit_chip(codec);
7089                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7090                 codec->patch_ops.init(codec);
7091                 failure = 0;
7092                 for (i = 0; i < 4; i++) {
7093                         chipio_read(codec, cur_address, &dsp_data_check[i]);
7094                         cur_address += 0x4;
7095                 }
7096                 for (i = 0; i < 4; i++) {
7097                         if (dsp_data_check[i] == 0xa1a2a3a4)
7098                                 failure = 1;
7099                 }
7100                 reload--;
7101         }
7102
7103         if (!failure && reload < 3)
7104                 codec_info(codec, "DSP fixed.");
7105
7106         if (!failure)
7107                 return;
7108
7109         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7110 }
7111
7112 /*
7113  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7114  * extra precision for decibel values. If you had the dB value in floating point
7115  * you would take the value after the decimal point, multiply by 64, and divide
7116  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7117  * implement fixed point or floating point dB volumes. For now, I'll set them
7118  * to 0 just incase a value has lingered from a boot into Windows.
7119  */
7120 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7121 {
7122         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7123         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7124         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7125         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7126         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7127         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7128         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7129         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7130 }
7131
7132 /*
7133  * Extra commands that don't really fit anywhere else.
7134  */
7135 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7136 {
7137         struct ca0132_spec *spec = codec->spec;
7138
7139         writel(0x00820680, spec->mem_base + 0x01C);
7140         writel(0x00820680, spec->mem_base + 0x01C);
7141
7142         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7143         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7144         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7145         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7146
7147         chipio_write(codec, 0x18b0a4, 0x000000c2);
7148
7149         snd_hda_codec_write(codec, 0x11, 0,
7150                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7151 }
7152
7153 static void r3d_pre_dsp_setup(struct hda_codec *codec)
7154 {
7155
7156         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7157         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7158         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7159         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7160
7161         chipio_write(codec, 0x18b0a4, 0x000000c2);
7162
7163         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7164                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7165         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7166                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7167         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7168                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7169
7170         snd_hda_codec_write(codec, 0x11, 0,
7171                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7172 }
7173
7174 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7175 {
7176         chipio_write(codec, 0x18b0a4, 0x000000c2);
7177
7178         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7179                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7180         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7181                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7182         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7183                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7184
7185         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7186                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7187         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7188                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7189         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7190                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7191         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7192                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7193
7194         snd_hda_codec_write(codec, 0x11, 0,
7195                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7196 }
7197
7198 /*
7199  * These are sent before the DSP is downloaded. Not sure
7200  * what they do, or if they're necessary. Could possibly
7201  * be removed. Figure they're better to leave in.
7202  */
7203 static void ca0132_mmio_init(struct hda_codec *codec)
7204 {
7205         struct ca0132_spec *spec = codec->spec;
7206
7207         writel(0x00000000, spec->mem_base + 0x400);
7208         writel(0x00000000, spec->mem_base + 0x408);
7209         writel(0x00000000, spec->mem_base + 0x40C);
7210         writel(0x00880680, spec->mem_base + 0x01C);
7211         writel(0x00000083, spec->mem_base + 0xC0C);
7212         writel(0x00000030, spec->mem_base + 0xC00);
7213         writel(0x00000000, spec->mem_base + 0xC04);
7214         writel(0x00000003, spec->mem_base + 0xC0C);
7215         writel(0x00000003, spec->mem_base + 0xC0C);
7216         writel(0x00000003, spec->mem_base + 0xC0C);
7217         writel(0x00000003, spec->mem_base + 0xC0C);
7218         writel(0x000000C1, spec->mem_base + 0xC08);
7219         writel(0x000000F1, spec->mem_base + 0xC08);
7220         writel(0x00000001, spec->mem_base + 0xC08);
7221         writel(0x000000C7, spec->mem_base + 0xC08);
7222         writel(0x000000C1, spec->mem_base + 0xC08);
7223         writel(0x00000080, spec->mem_base + 0xC04);
7224 }
7225
7226 /*
7227  * Extra init functions for alternative ca0132 codecs. Done
7228  * here so they don't clutter up the main ca0132_init function
7229  * anymore than they have to.
7230  */
7231 static void ca0132_alt_init(struct hda_codec *codec)
7232 {
7233         struct ca0132_spec *spec = codec->spec;
7234
7235         ca0132_alt_vol_setup(codec);
7236
7237         switch (spec->quirk) {
7238         case QUIRK_SBZ:
7239                 codec_dbg(codec, "SBZ alt_init");
7240                 ca0132_gpio_init(codec);
7241                 sbz_pre_dsp_setup(codec);
7242                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7243                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7244                 break;
7245         case QUIRK_R3DI:
7246                 codec_dbg(codec, "R3DI alt_init");
7247                 ca0132_gpio_init(codec);
7248                 ca0132_gpio_setup(codec);
7249                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7250                 r3di_pre_dsp_setup(codec);
7251                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7252                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7253                 break;
7254         case QUIRK_R3D:
7255                 r3d_pre_dsp_setup(codec);
7256                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7257                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7258                 break;
7259         }
7260 }
7261
7262 static int ca0132_init(struct hda_codec *codec)
7263 {
7264         struct ca0132_spec *spec = codec->spec;
7265         struct auto_pin_cfg *cfg = &spec->autocfg;
7266         int i;
7267         bool dsp_loaded;
7268
7269         /*
7270          * If the DSP is already downloaded, and init has been entered again,
7271          * there's only two reasons for it. One, the codec has awaken from a
7272          * suspended state, and in that case dspload_is_loaded will return
7273          * false, and the init will be ran again. The other reason it gets
7274          * re entered is on startup for some reason it triggers a suspend and
7275          * resume state. In this case, it will check if the DSP is downloaded,
7276          * and not run the init function again. For codecs using alt_functions,
7277          * it will check if the DSP is loaded properly.
7278          */
7279         if (spec->dsp_state == DSP_DOWNLOADED) {
7280                 dsp_loaded = dspload_is_loaded(codec);
7281                 if (!dsp_loaded) {
7282                         spec->dsp_reload = true;
7283                         spec->dsp_state = DSP_DOWNLOAD_INIT;
7284                 } else {
7285                         if (spec->quirk == QUIRK_SBZ)
7286                                 sbz_dsp_startup_check(codec);
7287                         return 0;
7288                 }
7289         }
7290
7291         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7292                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7293         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7294
7295         if (spec->use_pci_mmio)
7296                 ca0132_mmio_init(codec);
7297
7298         snd_hda_power_up_pm(codec);
7299
7300         ca0132_init_unsol(codec);
7301         ca0132_init_params(codec);
7302         ca0132_init_flags(codec);
7303
7304         snd_hda_sequence_write(codec, spec->base_init_verbs);
7305
7306         if (spec->use_alt_functions)
7307                 ca0132_alt_init(codec);
7308
7309         ca0132_download_dsp(codec);
7310
7311         ca0132_refresh_widget_caps(codec);
7312
7313         switch (spec->quirk) {
7314         case QUIRK_R3DI:
7315         case QUIRK_R3D:
7316                 r3d_setup_defaults(codec);
7317                 break;
7318         case QUIRK_SBZ:
7319                 sbz_setup_defaults(codec);
7320                 break;
7321         default:
7322                 ca0132_setup_defaults(codec);
7323                 ca0132_init_analog_mic2(codec);
7324                 ca0132_init_dmic(codec);
7325                 break;
7326         }
7327
7328         for (i = 0; i < spec->num_outputs; i++)
7329                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7330
7331         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7332
7333         for (i = 0; i < spec->num_inputs; i++)
7334                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7335
7336         init_input(codec, cfg->dig_in_pin, spec->dig_in);
7337
7338         if (!spec->use_alt_functions) {
7339                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7340                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7341                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7342                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7343                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7344         }
7345
7346         if (spec->quirk == QUIRK_SBZ)
7347                 ca0132_gpio_setup(codec);
7348
7349         snd_hda_sequence_write(codec, spec->spec_init_verbs);
7350         if (spec->use_alt_functions) {
7351                 ca0132_alt_select_out(codec);
7352                 ca0132_alt_select_in(codec);
7353         } else {
7354                 ca0132_select_out(codec);
7355                 ca0132_select_mic(codec);
7356         }
7357
7358         snd_hda_jack_report_sync(codec);
7359
7360         /*
7361          * Re set the PlayEnhancement switch on a resume event, because the
7362          * controls will not be reloaded.
7363          */
7364         if (spec->dsp_reload) {
7365                 spec->dsp_reload = false;
7366                 ca0132_pe_switch_set(codec);
7367         }
7368
7369         snd_hda_power_down_pm(codec);
7370
7371         return 0;
7372 }
7373
7374 static void ca0132_free(struct hda_codec *codec)
7375 {
7376         struct ca0132_spec *spec = codec->spec;
7377
7378         cancel_delayed_work_sync(&spec->unsol_hp_work);
7379         snd_hda_power_up(codec);
7380         switch (spec->quirk) {
7381         case QUIRK_SBZ:
7382                 sbz_exit_chip(codec);
7383                 break;
7384         case QUIRK_R3D:
7385                 r3d_exit_chip(codec);
7386                 break;
7387         case QUIRK_R3DI:
7388                 r3di_gpio_shutdown(codec);
7389                 break;
7390         }
7391
7392         snd_hda_sequence_write(codec, spec->base_exit_verbs);
7393         ca0132_exit_chip(codec);
7394
7395         snd_hda_power_down(codec);
7396 #ifdef CONFIG_PCI
7397         if (spec->mem_base)
7398                 pci_iounmap(codec->bus->pci, spec->mem_base);
7399 #endif
7400         kfree(spec->spec_init_verbs);
7401         kfree(codec->spec);
7402 }
7403
7404 static void ca0132_reboot_notify(struct hda_codec *codec)
7405 {
7406         codec->patch_ops.free(codec);
7407 }
7408
7409 #ifdef CONFIG_PM
7410 static int ca0132_suspend(struct hda_codec *codec)
7411 {
7412         struct ca0132_spec *spec = codec->spec;
7413
7414         cancel_delayed_work_sync(&spec->unsol_hp_work);
7415         return 0;
7416 }
7417 #endif
7418
7419 static const struct hda_codec_ops ca0132_patch_ops = {
7420         .build_controls = ca0132_build_controls,
7421         .build_pcms = ca0132_build_pcms,
7422         .init = ca0132_init,
7423         .free = ca0132_free,
7424         .unsol_event = snd_hda_jack_unsol_event,
7425 #ifdef CONFIG_PM
7426         .suspend = ca0132_suspend,
7427 #endif
7428         .reboot_notify = ca0132_reboot_notify,
7429 };
7430
7431 static void ca0132_config(struct hda_codec *codec)
7432 {
7433         struct ca0132_spec *spec = codec->spec;
7434
7435         spec->dacs[0] = 0x2;
7436         spec->dacs[1] = 0x3;
7437         spec->dacs[2] = 0x4;
7438
7439         spec->multiout.dac_nids = spec->dacs;
7440         spec->multiout.num_dacs = 3;
7441
7442         if (!spec->use_alt_functions)
7443                 spec->multiout.max_channels = 2;
7444         else
7445                 spec->multiout.max_channels = 6;
7446
7447         switch (spec->quirk) {
7448         case QUIRK_ALIENWARE:
7449                 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7450                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7451
7452                 spec->num_outputs = 2;
7453                 spec->out_pins[0] = 0x0b; /* speaker out */
7454                 spec->out_pins[1] = 0x0f;
7455                 spec->shared_out_nid = 0x2;
7456                 spec->unsol_tag_hp = 0x0f;
7457
7458                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7459                 spec->adcs[1] = 0x8; /* analog mic2 */
7460                 spec->adcs[2] = 0xa; /* what u hear */
7461
7462                 spec->num_inputs = 3;
7463                 spec->input_pins[0] = 0x12;
7464                 spec->input_pins[1] = 0x11;
7465                 spec->input_pins[2] = 0x13;
7466                 spec->shared_mic_nid = 0x7;
7467                 spec->unsol_tag_amic1 = 0x11;
7468                 break;
7469         case QUIRK_SBZ:
7470         case QUIRK_R3D:
7471                 if (spec->quirk == QUIRK_SBZ) {
7472                         codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7473                         snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7474                 }
7475                 if (spec->quirk == QUIRK_R3D) {
7476                         codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7477                         snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7478                 }
7479
7480                 spec->num_outputs = 2;
7481                 spec->out_pins[0] = 0x0B; /* Line out */
7482                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7483                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7484                 spec->out_pins[3] = 0x11; /* Rear surround */
7485                 spec->shared_out_nid = 0x2;
7486                 spec->unsol_tag_hp = spec->out_pins[1];
7487                 spec->unsol_tag_front_hp = spec->out_pins[2];
7488
7489                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7490                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7491                 spec->adcs[2] = 0xa; /* what u hear */
7492
7493                 spec->num_inputs = 2;
7494                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7495                 spec->input_pins[1] = 0x13; /* What U Hear */
7496                 spec->shared_mic_nid = 0x7;
7497                 spec->unsol_tag_amic1 = spec->input_pins[0];
7498
7499                 /* SPDIF I/O */
7500                 spec->dig_out = 0x05;
7501                 spec->multiout.dig_out_nid = spec->dig_out;
7502                 spec->dig_in = 0x09;
7503                 break;
7504         case QUIRK_R3DI:
7505                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7506                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7507
7508                 spec->num_outputs = 2;
7509                 spec->out_pins[0] = 0x0B; /* Line out */
7510                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7511                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7512                 spec->out_pins[3] = 0x11; /* Rear surround */
7513                 spec->shared_out_nid = 0x2;
7514                 spec->unsol_tag_hp = spec->out_pins[1];
7515                 spec->unsol_tag_front_hp = spec->out_pins[2];
7516
7517                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7518                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7519                 spec->adcs[2] = 0x0a; /* what u hear */
7520
7521                 spec->num_inputs = 2;
7522                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7523                 spec->input_pins[1] = 0x13; /* What U Hear */
7524                 spec->shared_mic_nid = 0x7;
7525                 spec->unsol_tag_amic1 = spec->input_pins[0];
7526
7527                 /* SPDIF I/O */
7528                 spec->dig_out = 0x05;
7529                 spec->multiout.dig_out_nid = spec->dig_out;
7530                 break;
7531         default:
7532                 spec->num_outputs = 2;
7533                 spec->out_pins[0] = 0x0b; /* speaker out */
7534                 spec->out_pins[1] = 0x10; /* headphone out */
7535                 spec->shared_out_nid = 0x2;
7536                 spec->unsol_tag_hp = spec->out_pins[1];
7537
7538                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7539                 spec->adcs[1] = 0x8; /* analog mic2 */
7540                 spec->adcs[2] = 0xa; /* what u hear */
7541
7542                 spec->num_inputs = 3;
7543                 spec->input_pins[0] = 0x12;
7544                 spec->input_pins[1] = 0x11;
7545                 spec->input_pins[2] = 0x13;
7546                 spec->shared_mic_nid = 0x7;
7547                 spec->unsol_tag_amic1 = spec->input_pins[0];
7548
7549                 /* SPDIF I/O */
7550                 spec->dig_out = 0x05;
7551                 spec->multiout.dig_out_nid = spec->dig_out;
7552                 spec->dig_in = 0x09;
7553                 break;
7554         }
7555 }
7556
7557 static int ca0132_prepare_verbs(struct hda_codec *codec)
7558 {
7559 /* Verbs + terminator (an empty element) */
7560 #define NUM_SPEC_VERBS 2
7561         struct ca0132_spec *spec = codec->spec;
7562
7563         spec->chip_init_verbs = ca0132_init_verbs0;
7564         if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
7565                 spec->desktop_init_verbs = ca0132_init_verbs1;
7566         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7567                                         sizeof(struct hda_verb),
7568                                         GFP_KERNEL);
7569         if (!spec->spec_init_verbs)
7570                 return -ENOMEM;
7571
7572         /* config EAPD */
7573         spec->spec_init_verbs[0].nid = 0x0b;
7574         spec->spec_init_verbs[0].param = 0x78D;
7575         spec->spec_init_verbs[0].verb = 0x00;
7576
7577         /* Previously commented configuration */
7578         /*
7579         spec->spec_init_verbs[2].nid = 0x0b;
7580         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7581         spec->spec_init_verbs[2].verb = 0x02;
7582
7583         spec->spec_init_verbs[3].nid = 0x10;
7584         spec->spec_init_verbs[3].param = 0x78D;
7585         spec->spec_init_verbs[3].verb = 0x02;
7586
7587         spec->spec_init_verbs[4].nid = 0x10;
7588         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7589         spec->spec_init_verbs[4].verb = 0x02;
7590         */
7591
7592         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7593         return 0;
7594 }
7595
7596 static int patch_ca0132(struct hda_codec *codec)
7597 {
7598         struct ca0132_spec *spec;
7599         int err;
7600         const struct snd_pci_quirk *quirk;
7601
7602         codec_dbg(codec, "patch_ca0132\n");
7603
7604         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7605         if (!spec)
7606                 return -ENOMEM;
7607         codec->spec = spec;
7608         spec->codec = codec;
7609
7610         codec->patch_ops = ca0132_patch_ops;
7611         codec->pcm_format_first = 1;
7612         codec->no_sticky_stream = 1;
7613
7614         /* Detect codec quirk */
7615         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7616         if (quirk)
7617                 spec->quirk = quirk->value;
7618         else
7619                 spec->quirk = QUIRK_NONE;
7620
7621         spec->dsp_state = DSP_DOWNLOAD_INIT;
7622         spec->num_mixers = 1;
7623
7624         /* Set which mixers each quirk uses. */
7625         switch (spec->quirk) {
7626         case QUIRK_SBZ:
7627                 spec->mixers[0] = desktop_mixer;
7628                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7629                 break;
7630         case QUIRK_R3D:
7631                 spec->mixers[0] = desktop_mixer;
7632                 snd_hda_codec_set_name(codec, "Recon3D");
7633                 break;
7634         case QUIRK_R3DI:
7635                 spec->mixers[0] = r3di_mixer;
7636                 snd_hda_codec_set_name(codec, "Recon3Di");
7637                 break;
7638         default:
7639                 spec->mixers[0] = ca0132_mixer;
7640                 break;
7641         }
7642
7643         /* Setup whether or not to use alt functions/controls/pci_mmio */
7644         switch (spec->quirk) {
7645         case QUIRK_SBZ:
7646         case QUIRK_R3D:
7647                 spec->use_alt_controls = true;
7648                 spec->use_alt_functions = true;
7649                 spec->use_pci_mmio = true;
7650                 break;
7651         case QUIRK_R3DI:
7652                 spec->use_alt_controls = true;
7653                 spec->use_alt_functions = true;
7654                 spec->use_pci_mmio = false;
7655                 break;
7656         default:
7657                 spec->use_alt_controls = false;
7658                 spec->use_alt_functions = false;
7659                 spec->use_pci_mmio = false;
7660                 break;
7661         }
7662
7663         if (spec->use_pci_mmio) {
7664                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7665                 if (spec->mem_base == NULL) {
7666                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7667                         spec->quirk = QUIRK_NONE;
7668                 }
7669         }
7670
7671         spec->base_init_verbs = ca0132_base_init_verbs;
7672         spec->base_exit_verbs = ca0132_base_exit_verbs;
7673
7674         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7675
7676         ca0132_init_chip(codec);
7677
7678         ca0132_config(codec);
7679
7680         err = ca0132_prepare_verbs(codec);
7681         if (err < 0)
7682                 goto error;
7683
7684         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7685         if (err < 0)
7686                 goto error;
7687
7688         return 0;
7689
7690  error:
7691         ca0132_free(codec);
7692         return err;
7693 }
7694
7695 /*
7696  * patch entries
7697  */
7698 static struct hda_device_id snd_hda_id_ca0132[] = {
7699         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7700         {} /* terminator */
7701 };
7702 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7703
7704 MODULE_LICENSE("GPL");
7705 MODULE_DESCRIPTION("Creative Sound Core3D codec");
7706
7707 static struct hda_codec_driver ca0132_driver = {
7708         .id = snd_hda_id_ca0132,
7709 };
7710
7711 module_hda_codec_driver(ca0132_driver);