sound/pci/hda/patch_ca0132.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Creative CA0132 chip
   4  *
   5  * Copyright (c) 2011, Creative Technology Ltd.
   6  *
   7  * Based on patch_ca0110.c
   8  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/module.h>
  16 #include <linux/firmware.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <asm/io.h>
  22 #include <sound/core.h>
  23 #include <sound/hda_codec.h>
  24 #include "hda_local.h"
  25 #include "hda_auto_parser.h"
  26 #include "hda_jack.h"
  27
  28 #include "ca0132_regs.h"
  29
  30 /* Enable this to see controls for tuning purpose. */
  31 /*#define ENABLE_TUNING_CONTROLS*/
  32
  33 #ifdef ENABLE_TUNING_CONTROLS
  34 #include <sound/tlv.h>
  35 #endif
  36
  37 #define FLOAT_ZERO      0x00000000
  38 #define FLOAT_ONE       0x3f800000
  39 #define FLOAT_TWO       0x40000000
  40 #define FLOAT_THREE     0x40400000
  41 #define FLOAT_FIVE      0x40a00000
  42 #define FLOAT_SIX       0x40c00000
  43 #define FLOAT_EIGHT     0x41000000
  44 #define FLOAT_MINUS_5   0xc0a00000
  45
  46 #define UNSOL_TAG_DSP   0x16
  47
  48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  50
  51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  54
  55 #define MASTERCONTROL                           0x80
  56 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  58
  59 #define WIDGET_CHIP_CTRL      0x15
  60 #define WIDGET_DSP_CTRL       0x16
  61
  62 #define MEM_CONNID_MICIN1     3
  63 #define MEM_CONNID_MICIN2     5
  64 #define MEM_CONNID_MICOUT1    12
  65 #define MEM_CONNID_MICOUT2    14
  66 #define MEM_CONNID_WUH        10
  67 #define MEM_CONNID_DSP        16
  68 #define MEM_CONNID_DMIC       100
  69
  70 #define SCP_SET    0
  71 #define SCP_GET    1
  72
  73 #define EFX_FILE   "/*(DEBLOBBED)*/"
  74 #define DESKTOP_EFX_FILE   "/*(DEBLOBBED)*/"
  75 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  76
  77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  78 /*(DEBLOBBED)*/
  79 #endif
  80
  81 static const char *const dirstr[2] = { "Playback", "Capture" };
  82
  83 #define NUM_OF_OUTPUTS 2
  84 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
  85 enum {
  86         SPEAKER_OUT,
  87         HEADPHONE_OUT,
  88 };
  89
  90 enum {
  91         DIGITAL_MIC,
  92         LINE_MIC_IN
  93 };
  94
  95 /* Strings for Input Source Enum Control */
  96 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
  97 #define IN_SRC_NUM_OF_INPUTS 3
  98 enum {
  99         REAR_MIC,
 100         REAR_LINE_IN,
 101         FRONT_MIC,
 102 };
 103
 104 enum {
 105 #define VNODE_START_NID    0x80
 106         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 107         VNID_MIC,
 108         VNID_HP_SEL,
 109         VNID_AMIC1_SEL,
 110         VNID_HP_ASEL,
 111         VNID_AMIC1_ASEL,
 112         VNODE_END_NID,
 113 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 114
 115 #define EFFECT_START_NID    0x90
 116 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 117         SURROUND = OUT_EFFECT_START_NID,
 118         CRYSTALIZER,
 119         DIALOG_PLUS,
 120         SMART_VOLUME,
 121         X_BASS,
 122         EQUALIZER,
 123         OUT_EFFECT_END_NID,
 124 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 125
 126 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 127         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 128         VOICE_FOCUS,
 129         MIC_SVM,
 130         NOISE_REDUCTION,
 131         IN_EFFECT_END_NID,
 132 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 133
 134         VOICEFX = IN_EFFECT_END_NID,
 135         PLAY_ENHANCEMENT,
 136         CRYSTAL_VOICE,
 137         EFFECT_END_NID,
 138         OUTPUT_SOURCE_ENUM,
 139         INPUT_SOURCE_ENUM,
 140         XBASS_XOVER,
 141         EQ_PRESET_ENUM,
 142         SMART_VOLUME_ENUM,
 143         MIC_BOOST_ENUM,
 144         AE5_HEADPHONE_GAIN_ENUM,
 145         AE5_SOUND_FILTER_ENUM,
 146         ZXR_HEADPHONE_GAIN,
 147         SPEAKER_CHANNEL_CFG_ENUM,
 148         SPEAKER_FULL_RANGE_FRONT,
 149         SPEAKER_FULL_RANGE_REAR,
 150         BASS_REDIRECTION,
 151         BASS_REDIRECTION_XOVER,
 152 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 153 };
 154
 155 /* Effects values size*/
 156 #define EFFECT_VALS_MAX_COUNT 12
 157
 158 /*
 159  * Default values for the effect slider controls, they are in order of their
 160  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 161  * X-bass.
 162  */
 163 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 164 /* Amount of effect level sliders for ca0132_alt controls. */
 165 #define EFFECT_LEVEL_SLIDERS 5
 166
 167 /* Latency introduced by DSP blocks in milliseconds. */
 168 #define DSP_CAPTURE_INIT_LATENCY        0
 169 #define DSP_CRYSTAL_VOICE_LATENCY       124
 170 #define DSP_PLAYBACK_INIT_LATENCY       13
 171 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 172 #define DSP_SPEAKER_OUT_LATENCY         7
 173
 174 struct ct_effect {
 175         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 176         hda_nid_t nid;
 177         int mid; /*effect module ID*/
 178         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 179         int direct; /* 0:output; 1:input*/
 180         int params; /* number of default non-on/off params */
 181         /*effect default values, 1st is on/off. */
 182         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 183 };
 184
 185 #define EFX_DIR_OUT 0
 186 #define EFX_DIR_IN  1
 187
 188 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 189         { .name = "Surround",
 190           .nid = SURROUND,
 191           .mid = 0x96,
 192           .reqs = {0, 1},
 193           .direct = EFX_DIR_OUT,
 194           .params = 1,
 195           .def_vals = {0x3F800000, 0x3F2B851F}
 196         },
 197         { .name = "Crystalizer",
 198           .nid = CRYSTALIZER,
 199           .mid = 0x96,
 200           .reqs = {7, 8},
 201           .direct = EFX_DIR_OUT,
 202           .params = 1,
 203           .def_vals = {0x3F800000, 0x3F266666}
 204         },
 205         { .name = "Dialog Plus",
 206           .nid = DIALOG_PLUS,
 207           .mid = 0x96,
 208           .reqs = {2, 3},
 209           .direct = EFX_DIR_OUT,
 210           .params = 1,
 211           .def_vals = {0x00000000, 0x3F000000}
 212         },
 213         { .name = "Smart Volume",
 214           .nid = SMART_VOLUME,
 215           .mid = 0x96,
 216           .reqs = {4, 5, 6},
 217           .direct = EFX_DIR_OUT,
 218           .params = 2,
 219           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 220         },
 221         { .name = "X-Bass",
 222           .nid = X_BASS,
 223           .mid = 0x96,
 224           .reqs = {24, 23, 25},
 225           .direct = EFX_DIR_OUT,
 226           .params = 2,
 227           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 228         },
 229         { .name = "Equalizer",
 230           .nid = EQUALIZER,
 231           .mid = 0x96,
 232           .reqs = {9, 10, 11, 12, 13, 14,
 233                         15, 16, 17, 18, 19, 20},
 234           .direct = EFX_DIR_OUT,
 235           .params = 11,
 236           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 237                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 238                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 239         },
 240         { .name = "Echo Cancellation",
 241           .nid = ECHO_CANCELLATION,
 242           .mid = 0x95,
 243           .reqs = {0, 1, 2, 3},
 244           .direct = EFX_DIR_IN,
 245           .params = 3,
 246           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 247         },
 248         { .name = "Voice Focus",
 249           .nid = VOICE_FOCUS,
 250           .mid = 0x95,
 251           .reqs = {6, 7, 8, 9},
 252           .direct = EFX_DIR_IN,
 253           .params = 3,
 254           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 255         },
 256         { .name = "Mic SVM",
 257           .nid = MIC_SVM,
 258           .mid = 0x95,
 259           .reqs = {44, 45},
 260           .direct = EFX_DIR_IN,
 261           .params = 1,
 262           .def_vals = {0x00000000, 0x3F3D70A4}
 263         },
 264         { .name = "Noise Reduction",
 265           .nid = NOISE_REDUCTION,
 266           .mid = 0x95,
 267           .reqs = {4, 5},
 268           .direct = EFX_DIR_IN,
 269           .params = 1,
 270           .def_vals = {0x3F800000, 0x3F000000}
 271         },
 272         { .name = "VoiceFX",
 273           .nid = VOICEFX,
 274           .mid = 0x95,
 275           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 276           .direct = EFX_DIR_IN,
 277           .params = 8,
 278           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 279                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 280                        0x00000000}
 281         }
 282 };
 283
 284 /* Tuning controls */
 285 #ifdef ENABLE_TUNING_CONTROLS
 286
 287 enum {
 288 #define TUNING_CTL_START_NID  0xC0
 289         WEDGE_ANGLE = TUNING_CTL_START_NID,
 290         SVM_LEVEL,
 291         EQUALIZER_BAND_0,
 292         EQUALIZER_BAND_1,
 293         EQUALIZER_BAND_2,
 294         EQUALIZER_BAND_3,
 295         EQUALIZER_BAND_4,
 296         EQUALIZER_BAND_5,
 297         EQUALIZER_BAND_6,
 298         EQUALIZER_BAND_7,
 299         EQUALIZER_BAND_8,
 300         EQUALIZER_BAND_9,
 301         TUNING_CTL_END_NID
 302 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 303 };
 304
 305 struct ct_tuning_ctl {
 306         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 307         hda_nid_t parent_nid;
 308         hda_nid_t nid;
 309         int mid; /*effect module ID*/
 310         int req; /*effect module request*/
 311         int direct; /* 0:output; 1:input*/
 312         unsigned int def_val;/*effect default values*/
 313 };
 314
 315 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 316         { .name = "Wedge Angle",
 317           .parent_nid = VOICE_FOCUS,
 318           .nid = WEDGE_ANGLE,
 319           .mid = 0x95,
 320           .req = 8,
 321           .direct = EFX_DIR_IN,
 322           .def_val = 0x41F00000
 323         },
 324         { .name = "SVM Level",
 325           .parent_nid = MIC_SVM,
 326           .nid = SVM_LEVEL,
 327           .mid = 0x95,
 328           .req = 45,
 329           .direct = EFX_DIR_IN,
 330           .def_val = 0x3F3D70A4
 331         },
 332         { .name = "EQ Band0",
 333           .parent_nid = EQUALIZER,
 334           .nid = EQUALIZER_BAND_0,
 335           .mid = 0x96,
 336           .req = 11,
 337           .direct = EFX_DIR_OUT,
 338           .def_val = 0x00000000
 339         },
 340         { .name = "EQ Band1",
 341           .parent_nid = EQUALIZER,
 342           .nid = EQUALIZER_BAND_1,
 343           .mid = 0x96,
 344           .req = 12,
 345           .direct = EFX_DIR_OUT,
 346           .def_val = 0x00000000
 347         },
 348         { .name = "EQ Band2",
 349           .parent_nid = EQUALIZER,
 350           .nid = EQUALIZER_BAND_2,
 351           .mid = 0x96,
 352           .req = 13,
 353           .direct = EFX_DIR_OUT,
 354           .def_val = 0x00000000
 355         },
 356         { .name = "EQ Band3",
 357           .parent_nid = EQUALIZER,
 358           .nid = EQUALIZER_BAND_3,
 359           .mid = 0x96,
 360           .req = 14,
 361           .direct = EFX_DIR_OUT,
 362           .def_val = 0x00000000
 363         },
 364         { .name = "EQ Band4",
 365           .parent_nid = EQUALIZER,
 366           .nid = EQUALIZER_BAND_4,
 367           .mid = 0x96,
 368           .req = 15,
 369           .direct = EFX_DIR_OUT,
 370           .def_val = 0x00000000
 371         },
 372         { .name = "EQ Band5",
 373           .parent_nid = EQUALIZER,
 374           .nid = EQUALIZER_BAND_5,
 375           .mid = 0x96,
 376           .req = 16,
 377           .direct = EFX_DIR_OUT,
 378           .def_val = 0x00000000
 379         },
 380         { .name = "EQ Band6",
 381           .parent_nid = EQUALIZER,
 382           .nid = EQUALIZER_BAND_6,
 383           .mid = 0x96,
 384           .req = 17,
 385           .direct = EFX_DIR_OUT,
 386           .def_val = 0x00000000
 387         },
 388         { .name = "EQ Band7",
 389           .parent_nid = EQUALIZER,
 390           .nid = EQUALIZER_BAND_7,
 391           .mid = 0x96,
 392           .req = 18,
 393           .direct = EFX_DIR_OUT,
 394           .def_val = 0x00000000
 395         },
 396         { .name = "EQ Band8",
 397           .parent_nid = EQUALIZER,
 398           .nid = EQUALIZER_BAND_8,
 399           .mid = 0x96,
 400           .req = 19,
 401           .direct = EFX_DIR_OUT,
 402           .def_val = 0x00000000
 403         },
 404         { .name = "EQ Band9",
 405           .parent_nid = EQUALIZER,
 406           .nid = EQUALIZER_BAND_9,
 407           .mid = 0x96,
 408           .req = 20,
 409           .direct = EFX_DIR_OUT,
 410           .def_val = 0x00000000
 411         }
 412 };
 413 #endif
 414
 415 /* Voice FX Presets */
 416 #define VOICEFX_MAX_PARAM_COUNT 9
 417
 418 struct ct_voicefx {
 419         char *name;
 420         hda_nid_t nid;
 421         int mid;
 422         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 423 };
 424
 425 struct ct_voicefx_preset {
 426         char *name; /*preset name*/
 427         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 428 };
 429
 430 static const struct ct_voicefx ca0132_voicefx = {
 431         .name = "VoiceFX Capture Switch",
 432         .nid = VOICEFX,
 433         .mid = 0x95,
 434         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 435 };
 436
 437 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 438         { .name = "Neutral",
 439           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 440                     0x44FA0000, 0x3F800000, 0x3F800000,
 441                     0x3F800000, 0x00000000, 0x00000000 }
 442         },
 443         { .name = "Female2Male",
 444           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 445                     0x44FA0000, 0x3F19999A, 0x3F866666,
 446                     0x3F800000, 0x00000000, 0x00000000 }
 447         },
 448         { .name = "Male2Female",
 449           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 450                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 451                     0x3F800000, 0x00000000, 0x00000000 }
 452         },
 453         { .name = "ScrappyKid",
 454           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 455                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 456                     0x3F800000, 0x00000000, 0x00000000 }
 457         },
 458         { .name = "Elderly",
 459           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 460                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 461                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 462         },
 463         { .name = "Orc",
 464           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 465                     0x45098000, 0x3F266666, 0x3FC00000,
 466                     0x3F800000, 0x00000000, 0x00000000 }
 467         },
 468         { .name = "Elf",
 469           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 470                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 471                     0x3F800000, 0x00000000, 0x00000000 }
 472         },
 473         { .name = "Dwarf",
 474           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 475                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 476                     0x3F800000, 0x00000000, 0x00000000 }
 477         },
 478         { .name = "AlienBrute",
 479           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 480                     0x451F6000, 0x3F266666, 0x3FA7D945,
 481                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 482         },
 483         { .name = "Robot",
 484           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 485                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 486                     0xBC07010E, 0x00000000, 0x00000000 }
 487         },
 488         { .name = "Marine",
 489           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 490                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 491                     0x3F0A3D71, 0x00000000, 0x00000000 }
 492         },
 493         { .name = "Emo",
 494           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 495                     0x44FA0000, 0x3F800000, 0x3F800000,
 496                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 497         },
 498         { .name = "DeepVoice",
 499           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 500                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 501                     0x3F800000, 0x00000000, 0x00000000 }
 502         },
 503         { .name = "Munchkin",
 504           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 505                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 506                     0x3F800000, 0x00000000, 0x00000000 }
 507         }
 508 };
 509
 510 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 511
 512 #define EQ_PRESET_MAX_PARAM_COUNT 11
 513
 514 struct ct_eq {
 515         char *name;
 516         hda_nid_t nid;
 517         int mid;
 518         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 519 };
 520
 521 struct ct_eq_preset {
 522         char *name; /*preset name*/
 523         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 524 };
 525
 526 static const struct ct_eq ca0132_alt_eq_enum = {
 527         .name = "FX: Equalizer Preset Switch",
 528         .nid = EQ_PRESET_ENUM,
 529         .mid = 0x96,
 530         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 531 };
 532
 533
 534 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 535         { .name = "Flat",
 536          .vals = { 0x00000000, 0x00000000, 0x00000000,
 537                    0x00000000, 0x00000000, 0x00000000,
 538                    0x00000000, 0x00000000, 0x00000000,
 539                    0x00000000, 0x00000000            }
 540         },
 541         { .name = "Acoustic",
 542          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 543                    0x40000000, 0x00000000, 0x00000000,
 544                    0x00000000, 0x00000000, 0x40000000,
 545                    0x40000000, 0x40000000            }
 546         },
 547         { .name = "Classical",
 548          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 549                    0x40C00000, 0x40466666, 0x00000000,
 550                    0x00000000, 0x00000000, 0x00000000,
 551                    0x40466666, 0x40466666            }
 552         },
 553         { .name = "Country",
 554          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 555                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 556                    0x00000000, 0x00000000, 0x40000000,
 557                    0x40466666, 0x40800000            }
 558         },
 559         { .name = "Dance",
 560          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 561                    0x40466666, 0x40866666, 0xBF99999A,
 562                    0xBF99999A, 0x00000000, 0x00000000,
 563                    0x40800000, 0x40800000            }
 564         },
 565         { .name = "Jazz",
 566          .vals = { 0x00000000, 0x00000000, 0x00000000,
 567                    0x3F8CCCCD, 0x40800000, 0x40800000,
 568                    0x40800000, 0x00000000, 0x3F8CCCCD,
 569                    0x40466666, 0x40466666            }
 570         },
 571         { .name = "New Age",
 572          .vals = { 0x00000000, 0x00000000, 0x40000000,
 573                    0x40000000, 0x00000000, 0x00000000,
 574                    0x00000000, 0x3F8CCCCD, 0x40000000,
 575                    0x40000000, 0x40000000            }
 576         },
 577         { .name = "Pop",
 578          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 579                    0x40000000, 0x40000000, 0x00000000,
 580                    0xBF99999A, 0xBF99999A, 0x00000000,
 581                    0x40466666, 0x40C00000            }
 582         },
 583         { .name = "Rock",
 584          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 585                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 586                    0xBF99999A, 0x00000000, 0x00000000,
 587                    0x40800000, 0x40800000            }
 588         },
 589         { .name = "Vocal",
 590          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 591                    0xBF99999A, 0x00000000, 0x40466666,
 592                    0x40800000, 0x40466666, 0x00000000,
 593                    0x00000000, 0x3F8CCCCD            }
 594         }
 595 };
 596
 597 /*
 598  * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
 599  * set as not being full range, and bass redirection is enabled, all
 600  * frequencies below the crossover frequency are redirected to the LFE
 601  * channel. If the surround configuration has no LFE channel, this can't be
 602  * enabled. X-Bass must be disabled when using these.
 603  */
 604 enum speaker_range_reqs {
 605         SPEAKER_BASS_REDIRECT            = 0x15,
 606         SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
 607         /* Between 0x16-0x1a are the X-Bass reqs. */
 608         SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
 609         SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
 610         SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
 611         SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
 612         SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
 613 };
 614
 615 /*
 616  * Definitions for the DSP req's to handle speaker tuning. These all belong to
 617  * module ID 0x96, the output effects module.
 618  */
 619 enum speaker_tuning_reqs {
 620         /*
 621          * Currently, this value is always set to 0.0f. However, on Windows,
 622          * when selecting certain headphone profiles on the new Sound Blaster
 623          * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
 624          * sent. This gets the speaker EQ address area, which is then used to
 625          * send over (presumably) an equalizer profile for the specific
 626          * headphone setup. It is sent using the same method the DSP
 627          * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
 628          * file exists in linux firmware tree but goes unused. It would also
 629          * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
 630          * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
 631          * set to 1.0f.
 632          */
 633         SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
 634         SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
 635         SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
 636         SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
 637         SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
 638         SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
 639         SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
 640         SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
 641         SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
 642         SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
 643         /*
 644          * Inversion is used when setting headphone virtualization to line
 645          * out. Not sure why this is, but it's the only place it's ever used.
 646          */
 647         SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
 648         SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
 649         SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
 650         SPEAKER_TUNING_LFE_INVERT               = 0x2c,
 651         SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
 652         SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
 653         SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
 654         SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
 655         /* Delay is used when setting surround speaker distance in Windows. */
 656         SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
 657         SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
 658         SPEAKER_TUNING_CENTER_DELAY             = 0x33,
 659         SPEAKER_TUNING_LFE_DELAY                = 0x34,
 660         SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
 661         SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
 662         SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
 663         SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
 664         /* Of these two, only mute seems to ever be used. */
 665         SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
 666         SPEAKER_TUNING_MUTE                     = 0x3a,
 667 };
 668
 669 /* Surround output channel count configuration structures. */
 670 #define SPEAKER_CHANNEL_CFG_COUNT 5
 671 enum {
 672         SPEAKER_CHANNELS_2_0,
 673         SPEAKER_CHANNELS_2_1,
 674         SPEAKER_CHANNELS_4_0,
 675         SPEAKER_CHANNELS_4_1,
 676         SPEAKER_CHANNELS_5_1,
 677 };
 678
 679 struct ca0132_alt_speaker_channel_cfg {
 680         char *name;
 681         unsigned int val;
 682 };
 683
 684 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
 685         { .name = "2.0",
 686           .val = FLOAT_ONE
 687         },
 688         { .name = "2.1",
 689           .val = FLOAT_TWO
 690         },
 691         { .name = "4.0",
 692           .val = FLOAT_FIVE
 693         },
 694         { .name = "4.1",
 695           .val = FLOAT_SIX
 696         },
 697         { .name = "5.1",
 698           .val = FLOAT_EIGHT
 699         }
 700 };
 701
 702 /*
 703  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 704  * and I don't know what the third req is, but it's always zero. I assume it's
 705  * some sort of update or set command to tell the DSP there's new volume info.
 706  */
 707 #define DSP_VOL_OUT 0
 708 #define DSP_VOL_IN  1
 709
 710 struct ct_dsp_volume_ctl {
 711         hda_nid_t vnid;
 712         int mid; /* module ID*/
 713         unsigned int reqs[3]; /* scp req ID */
 714 };
 715
 716 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 717         { .vnid = VNID_SPK,
 718           .mid = 0x32,
 719           .reqs = {3, 4, 2}
 720         },
 721         { .vnid = VNID_MIC,
 722           .mid = 0x37,
 723           .reqs = {2, 3, 1}
 724         }
 725 };
 726
 727 /* Values for ca0113_mmio_command_set for selecting output. */
 728 #define AE_CA0113_OUT_SET_COMMANDS 6
 729 struct ae_ca0113_output_set {
 730         unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
 731         unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
 732         unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
 733 };
 734
 735 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
 736         .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 737         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 738                     /* Speakers. */
 739         .vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 740                     /* Headphones. */
 741                     { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
 742 };
 743
 744 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
 745         .group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 746         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 747                     /* Speakers. */
 748         .vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 749                     /* Headphones. */
 750                     { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
 751 };
 752
 753 /* ae5 ca0113 command sequences to set headphone gain levels. */
 754 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
 755 struct ae5_headphone_gain_set {
 756         char *name;
 757         unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
 758 };
 759
 760 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
 761         { .name = "Low (16-31",
 762           .vals = { 0xff, 0x2c, 0xf5, 0x32 }
 763         },
 764         { .name = "Medium (32-149",
 765           .vals = { 0x38, 0xa8, 0x3e, 0x4c }
 766         },
 767         { .name = "High (150-600",
 768           .vals = { 0xff, 0xff, 0xff, 0x7f }
 769         }
 770 };
 771
 772 struct ae5_filter_set {
 773         char *name;
 774         unsigned int val;
 775 };
 776
 777 static const struct ae5_filter_set ae5_filter_presets[] = {
 778         { .name = "Slow Roll Off",
 779           .val = 0xa0
 780         },
 781         { .name = "Minimum Phase",
 782           .val = 0xc0
 783         },
 784         { .name = "Fast Roll Off",
 785           .val = 0x80
 786         }
 787 };
 788
 789 /*
 790  * Data structures for storing audio router remapping data. These are used to
 791  * remap a currently active streams ports.
 792  */
 793 struct chipio_stream_remap_data {
 794         unsigned int stream_id;
 795         unsigned int count;
 796
 797         unsigned int offset[16];
 798         unsigned int value[16];
 799 };
 800
 801 static const struct chipio_stream_remap_data stream_remap_data[] = {
 802         { .stream_id = 0x14,
 803           .count     = 0x04,
 804           .offset    = { 0x00, 0x04, 0x08, 0x0c },
 805           .value     = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
 806         },
 807         { .stream_id = 0x0c,
 808           .count     = 0x0c,
 809           .offset    = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
 810                          0x20, 0x24, 0x28, 0x2c },
 811           .value     = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
 812                          0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
 813                          0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
 814         },
 815         { .stream_id = 0x0c,
 816           .count     = 0x08,
 817           .offset    = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
 818           .value     = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
 819                          0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
 820         }
 821 };
 822
 823 enum hda_cmd_vendor_io {
 824         /* for DspIO node */
 825         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 826         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 827
 828         VENDOR_DSPIO_STATUS                  = 0xF01,
 829         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 830         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 831         VENDOR_DSPIO_DSP_INIT                = 0x703,
 832         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 833         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 834
 835         /* for ChipIO node */
 836         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 837         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 838         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 839         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 840         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 841
 842         VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
 843         VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
 844
 845         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 846         VENDOR_CHIPIO_STATUS                 = 0xF01,
 847         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 848         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 849
 850         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 851         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 852         VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
 853         VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
 854         VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
 855
 856         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 857         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 858
 859         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 860         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 861         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 862         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 863         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 864         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 865         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 866         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 867
 868         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 869         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 870         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 871         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 872
 873         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 874         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 875         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 876         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 877
 878         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 879         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 880         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 881         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 882         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 883         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 884
 885         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 886 };
 887
 888 /*
 889  *  Control flag IDs
 890  */
 891 enum control_flag_id {
 892         /* Connection manager stream setup is bypassed/enabled */
 893         CONTROL_FLAG_C_MGR                  = 0,
 894         /* DSP DMA is bypassed/enabled */
 895         CONTROL_FLAG_DMA                    = 1,
 896         /* 8051 'idle' mode is disabled/enabled */
 897         CONTROL_FLAG_IDLE_ENABLE            = 2,
 898         /* Tracker for the SPDIF-in path is bypassed/enabled */
 899         CONTROL_FLAG_TRACKER                = 3,
 900         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 901         CONTROL_FLAG_SPDIF2OUT              = 4,
 902         /* Digital Microphone is disabled/enabled */
 903         CONTROL_FLAG_DMIC                   = 5,
 904         /* ADC_B rate is 48 kHz/96 kHz */
 905         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 906         /* ADC_C rate is 48 kHz/96 kHz */
 907         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 908         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 909         CONTROL_FLAG_DAC_96KHZ              = 8,
 910         /* DSP rate is 48 kHz/96 kHz */
 911         CONTROL_FLAG_DSP_96KHZ              = 9,
 912         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 913         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 914         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 915         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 916         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 917         CONTROL_FLAG_DECODE_LOOP            = 12,
 918         /* De-emphasis filter on DAC-1 disabled/enabled */
 919         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 920         /* De-emphasis filter on DAC-2 disabled/enabled */
 921         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 922         /* De-emphasis filter on DAC-3 disabled/enabled */
 923         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 924         /* High-pass filter on ADC_B disabled/enabled */
 925         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 926         /* High-pass filter on ADC_C disabled/enabled */
 927         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 928         /* Common mode on Port_A disabled/enabled */
 929         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 930         /* Common mode on Port_D disabled/enabled */
 931         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 932         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 933         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 934         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 935         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 936         /* ASI rate is 48kHz/96kHz */
 937         CONTROL_FLAG_ASI_96KHZ              = 22,
 938         /* DAC power settings able to control attached ports no/yes */
 939         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 940         /* Clock Stop OK reporting is disabled/enabled */
 941         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 942         /* Number of control flags */
 943         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 944 };
 945
 946 /*
 947  * Control parameter IDs
 948  */
 949 enum control_param_id {
 950         /* 0: None, 1: Mic1In*/
 951         CONTROL_PARAM_VIP_SOURCE               = 1,
 952         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 953         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 954         /* Port A output stage gain setting to use when 16 Ohm output
 955          * impedance is selected*/
 956         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 957         /* Port D output stage gain setting to use when 16 Ohm output
 958          * impedance is selected*/
 959         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 960
 961         /*
 962          * This control param name was found in the 8051 memory, and makes
 963          * sense given the fact the AE-5 uses it and has the ASI flag set.
 964          */
 965         CONTROL_PARAM_ASI                      = 23,
 966
 967         /* Stream Control */
 968
 969         /* Select stream with the given ID */
 970         CONTROL_PARAM_STREAM_ID                = 24,
 971         /* Source connection point for the selected stream */
 972         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 973         /* Destination connection point for the selected stream */
 974         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 975         /* Number of audio channels in the selected stream */
 976         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 977         /*Enable control for the selected stream */
 978         CONTROL_PARAM_STREAM_CONTROL           = 28,
 979
 980         /* Connection Point Control */
 981
 982         /* Select connection point with the given ID */
 983         CONTROL_PARAM_CONN_POINT_ID            = 29,
 984         /* Connection point sample rate */
 985         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 986
 987         /* Node Control */
 988
 989         /* Select HDA node with the given ID */
 990         CONTROL_PARAM_NODE_ID                  = 31
 991 };
 992
 993 /*
 994  *  Dsp Io Status codes
 995  */
 996 enum hda_vendor_status_dspio {
 997         /* Success */
 998         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 999         /* Busy, unable to accept new command, the host must retry */
1000         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
1001         /* SCP command queue is full */
1002         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
1003         /* SCP response queue is empty */
1004         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1005 };
1006
1007 /*
1008  *  Chip Io Status codes
1009  */
1010 enum hda_vendor_status_chipio {
1011         /* Success */
1012         VENDOR_STATUS_CHIPIO_OK   = 0x00,
1013         /* Busy, unable to accept new command, the host must retry */
1014         VENDOR_STATUS_CHIPIO_BUSY = 0x01
1015 };
1016
1017 /*
1018  *  CA0132 sample rate
1019  */
1020 enum ca0132_sample_rate {
1021         SR_6_000        = 0x00,
1022         SR_8_000        = 0x01,
1023         SR_9_600        = 0x02,
1024         SR_11_025       = 0x03,
1025         SR_16_000       = 0x04,
1026         SR_22_050       = 0x05,
1027         SR_24_000       = 0x06,
1028         SR_32_000       = 0x07,
1029         SR_44_100       = 0x08,
1030         SR_48_000       = 0x09,
1031         SR_88_200       = 0x0A,
1032         SR_96_000       = 0x0B,
1033         SR_144_000      = 0x0C,
1034         SR_176_400      = 0x0D,
1035         SR_192_000      = 0x0E,
1036         SR_384_000      = 0x0F,
1037
1038         SR_COUNT        = 0x10,
1039
1040         SR_RATE_UNKNOWN = 0x1F
1041 };
1042
1043 enum dsp_download_state {
1044         DSP_DOWNLOAD_FAILED = -1,
1045         DSP_DOWNLOAD_INIT   = 0,
1046         DSP_DOWNLOADING     = 1,
1047         DSP_DOWNLOADED      = 2
1048 };
1049
1050 /* retrieve parameters from hda format */
1051 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
1052 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
1053 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
1054 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
1055
1056 /*
1057  * CA0132 specific
1058  */
1059
1060 struct ca0132_spec {
1061         const struct snd_kcontrol_new *mixers[5];
1062         unsigned int num_mixers;
1063         const struct hda_verb *base_init_verbs;
1064         const struct hda_verb *base_exit_verbs;
1065         const struct hda_verb *chip_init_verbs;
1066         const struct hda_verb *desktop_init_verbs;
1067         struct hda_verb *spec_init_verbs;
1068         struct auto_pin_cfg autocfg;
1069
1070         /* Nodes configurations */
1071         struct hda_multi_out multiout;
1072         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1073         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1074         unsigned int num_outputs;
1075         hda_nid_t input_pins[AUTO_PIN_LAST];
1076         hda_nid_t adcs[AUTO_PIN_LAST];
1077         hda_nid_t dig_out;
1078         hda_nid_t dig_in;
1079         unsigned int num_inputs;
1080         hda_nid_t shared_mic_nid;
1081         hda_nid_t shared_out_nid;
1082         hda_nid_t unsol_tag_hp;
1083         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1084         hda_nid_t unsol_tag_amic1;
1085
1086         /* chip access */
1087         struct mutex chipio_mutex; /* chip access mutex */
1088         u32 curr_chip_addx;
1089
1090         /* DSP download related */
1091         enum dsp_download_state dsp_state;
1092         unsigned int dsp_stream_id;
1093         unsigned int wait_scp;
1094         unsigned int wait_scp_header;
1095         unsigned int wait_num_data;
1096         unsigned int scp_resp_header;
1097         unsigned int scp_resp_data[4];
1098         unsigned int scp_resp_count;
1099         bool startup_check_entered;
1100         bool dsp_reload;
1101
1102         /* mixer and effects related */
1103         unsigned char dmic_ctl;
1104         int cur_out_type;
1105         int cur_mic_type;
1106         long vnode_lvol[VNODES_COUNT];
1107         long vnode_rvol[VNODES_COUNT];
1108         long vnode_lswitch[VNODES_COUNT];
1109         long vnode_rswitch[VNODES_COUNT];
1110         long effects_switch[EFFECTS_COUNT];
1111         long voicefx_val;
1112         long cur_mic_boost;
1113         /* ca0132_alt control related values */
1114         unsigned char in_enum_val;
1115         unsigned char out_enum_val;
1116         unsigned char channel_cfg_val;
1117         unsigned char speaker_range_val[2];
1118         unsigned char mic_boost_enum_val;
1119         unsigned char smart_volume_setting;
1120         unsigned char bass_redirection_val;
1121         long bass_redirect_xover_freq;
1122         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1123         long xbass_xover_freq;
1124         long eq_preset_val;
1125         unsigned int tlv[4];
1126         struct hda_vmaster_mute_hook vmaster_mute;
1127         /* AE-5 Control values */
1128         unsigned char ae5_headphone_gain_val;
1129         unsigned char ae5_filter_val;
1130         /* ZxR Control Values */
1131         unsigned char zxr_gain_set;
1132
1133         struct hda_codec *codec;
1134         struct delayed_work unsol_hp_work;
1135         int quirk;
1136
1137 #ifdef ENABLE_TUNING_CONTROLS
1138         long cur_ctl_vals[TUNING_CTLS_COUNT];
1139 #endif
1140         /*
1141          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1142          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1143          * things.
1144          */
1145         bool use_pci_mmio;
1146         void __iomem *mem_base;
1147
1148         /*
1149          * Whether or not to use the alt functions like alt_select_out,
1150          * alt_select_in, etc. Only used on desktop codecs for now, because of
1151          * surround sound support.
1152          */
1153         bool use_alt_functions;
1154
1155         /*
1156          * Whether or not to use alt controls:  volume effect sliders, EQ
1157          * presets, smart volume presets, and new control names with FX prefix.
1158          * Renames PlayEnhancement and CrystalVoice too.
1159          */
1160         bool use_alt_controls;
1161 };
1162
1163 /*
1164  * CA0132 quirks table
1165  */
1166 enum {
1167         QUIRK_NONE,
1168         QUIRK_ALIENWARE,
1169         QUIRK_ALIENWARE_M17XR4,
1170         QUIRK_SBZ,
1171         QUIRK_ZXR,
1172         QUIRK_ZXR_DBPRO,
1173         QUIRK_R3DI,
1174         QUIRK_R3D,
1175         QUIRK_AE5,
1176         QUIRK_AE7,
1177 };
1178
1179 #ifdef CONFIG_PCI
1180 #define ca0132_quirk(spec)              ((spec)->quirk)
1181 #define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
1182 #define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
1183 #define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
1184 #else
1185 #define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
1186 #define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
1187 #define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
1188 #define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
1189 #endif
1190
1191 static const struct hda_pintbl alienware_pincfgs[] = {
1192         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1193         { 0x0c, 0x411111f0 }, /* N/A */
1194         { 0x0d, 0x411111f0 }, /* N/A */
1195         { 0x0e, 0x411111f0 }, /* N/A */
1196         { 0x0f, 0x0321101f }, /* HP */
1197         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1198         { 0x11, 0x03a11021 }, /* Mic */
1199         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1200         { 0x13, 0x411111f0 }, /* N/A */
1201         { 0x18, 0x411111f0 }, /* N/A */
1202         {}
1203 };
1204
1205 /* Sound Blaster Z pin configs taken from Windows Driver */
1206 static const struct hda_pintbl sbz_pincfgs[] = {
1207         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1208         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1209         { 0x0d, 0x014510f0 }, /* Digital Out */
1210         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1211         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1212         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1213         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1214         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1215         { 0x13, 0x908700f0 }, /* What U Hear In*/
1216         { 0x18, 0x50d000f0 }, /* N/A */
1217         {}
1218 };
1219
1220 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1221 static const struct hda_pintbl zxr_pincfgs[] = {
1222         { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1223         { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1224         { 0x0d, 0x014510f0 }, /* Digital Out */
1225         { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1226         { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1227         { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1228         { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1229         { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1230         { 0x13, 0x908700f0 }, /* What U Hear In*/
1231         { 0x18, 0x50d000f0 }, /* N/A */
1232         {}
1233 };
1234
1235 /* Recon3D pin configs taken from Windows Driver */
1236 static const struct hda_pintbl r3d_pincfgs[] = {
1237         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1238         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1239         { 0x0d, 0x014510f0 }, /* Digital Out */
1240         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1241         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1242         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1243         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1244         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1245         { 0x13, 0x908700f0 }, /* What U Hear In*/
1246         { 0x18, 0x50d000f0 }, /* N/A */
1247         {}
1248 };
1249
1250 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1251 static const struct hda_pintbl ae5_pincfgs[] = {
1252         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1253         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1254         { 0x0d, 0x014510f0 }, /* Digital Out */
1255         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1256         { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1257         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1258         { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1259         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1260         { 0x13, 0x908700f0 }, /* What U Hear In*/
1261         { 0x18, 0x50d000f0 }, /* N/A */
1262         {}
1263 };
1264
1265 /* Recon3D integrated pin configs taken from Windows Driver */
1266 static const struct hda_pintbl r3di_pincfgs[] = {
1267         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1268         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1269         { 0x0d, 0x014510f0 }, /* Digital Out */
1270         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1271         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1272         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1273         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1274         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1275         { 0x13, 0x908700f0 }, /* What U Hear In*/
1276         { 0x18, 0x500000f0 }, /* N/A */
1277         {}
1278 };
1279
1280 static const struct hda_pintbl ae7_pincfgs[] = {
1281         { 0x0b, 0x01017010 },
1282         { 0x0c, 0x014510f0 },
1283         { 0x0d, 0x414510f0 },
1284         { 0x0e, 0x01c520f0 },
1285         { 0x0f, 0x01017114 },
1286         { 0x10, 0x01017011 },
1287         { 0x11, 0x018170ff },
1288         { 0x12, 0x01a170f0 },
1289         { 0x13, 0x908700f0 },
1290         { 0x18, 0x500000f0 },
1291         {}
1292 };
1293
1294 static const struct snd_pci_quirk ca0132_quirks[] = {
1295         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1296         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1297         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1298         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1299         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1300         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1301         SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1302         SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1303         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1304         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1305         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1306         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1307         SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1308         SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1309         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1310         SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1311         SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1312         SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1313         SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1314         {}
1315 };
1316
1317 /* Output selection quirk info structures. */
1318 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1319 #define MAX_QUIRK_SCP_SET_VALS 2
1320 struct ca0132_alt_out_set_info {
1321         unsigned int dac2port; /* ParamID 0x0d value. */
1322
1323         bool has_hda_gpio;
1324         char hda_gpio_pin;
1325         char hda_gpio_set;
1326
1327         unsigned int mmio_gpio_count;
1328         char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1329         char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1330
1331         unsigned int scp_cmds_count;
1332         unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1333         unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1334         unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1335
1336         bool has_chipio_write;
1337         unsigned int chipio_write_addr;
1338         unsigned int chipio_write_data;
1339 };
1340
1341 struct ca0132_alt_out_set_quirk_data {
1342         int quirk_id;
1343
1344         bool has_headphone_gain;
1345         bool is_ae_series;
1346
1347         struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1348 };
1349
1350 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1351         { .quirk_id = QUIRK_R3DI,
1352           .has_headphone_gain = false,
1353           .is_ae_series       = false,
1354           .out_set_info = {
1355                 /* Speakers. */
1356                 { .dac2port         = 0x24,
1357                   .has_hda_gpio     = true,
1358                   .hda_gpio_pin     = 2,
1359                   .hda_gpio_set     = 1,
1360                   .mmio_gpio_count  = 0,
1361                   .scp_cmds_count   = 0,
1362                   .has_chipio_write = false,
1363                 },
1364                 /* Headphones. */
1365                 { .dac2port         = 0x21,
1366                   .has_hda_gpio     = true,
1367                   .hda_gpio_pin     = 2,
1368                   .hda_gpio_set     = 0,
1369                   .mmio_gpio_count  = 0,
1370                   .scp_cmds_count   = 0,
1371                   .has_chipio_write = false,
1372                 } },
1373         },
1374         { .quirk_id = QUIRK_R3D,
1375           .has_headphone_gain = false,
1376           .is_ae_series       = false,
1377           .out_set_info = {
1378                 /* Speakers. */
1379                 { .dac2port         = 0x24,
1380                   .has_hda_gpio     = false,
1381                   .mmio_gpio_count  = 1,
1382                   .mmio_gpio_pin    = { 1 },
1383                   .mmio_gpio_set    = { 1 },
1384                   .scp_cmds_count   = 0,
1385                   .has_chipio_write = false,
1386                 },
1387                 /* Headphones. */
1388                 { .dac2port         = 0x21,
1389                   .has_hda_gpio     = false,
1390                   .mmio_gpio_count  = 1,
1391                   .mmio_gpio_pin    = { 1 },
1392                   .mmio_gpio_set    = { 0 },
1393                   .scp_cmds_count   = 0,
1394                   .has_chipio_write = false,
1395                 } },
1396         },
1397         { .quirk_id = QUIRK_SBZ,
1398           .has_headphone_gain = false,
1399           .is_ae_series       = false,
1400           .out_set_info = {
1401                 /* Speakers. */
1402                 { .dac2port         = 0x18,
1403                   .has_hda_gpio     = false,
1404                   .mmio_gpio_count  = 3,
1405                   .mmio_gpio_pin    = { 7, 4, 1 },
1406                   .mmio_gpio_set    = { 0, 1, 1 },
1407                   .scp_cmds_count   = 0,
1408                   .has_chipio_write = false, },
1409                 /* Headphones. */
1410                 { .dac2port         = 0x12,
1411                   .has_hda_gpio     = false,
1412                   .mmio_gpio_count  = 3,
1413                   .mmio_gpio_pin    = { 7, 4, 1 },
1414                   .mmio_gpio_set    = { 1, 1, 0 },
1415                   .scp_cmds_count   = 0,
1416                   .has_chipio_write = false,
1417                 } },
1418         },
1419         { .quirk_id = QUIRK_ZXR,
1420           .has_headphone_gain = true,
1421           .is_ae_series       = false,
1422           .out_set_info = {
1423                 /* Speakers. */
1424                 { .dac2port         = 0x24,
1425                   .has_hda_gpio     = false,
1426                   .mmio_gpio_count  = 3,
1427                   .mmio_gpio_pin    = { 2, 3, 5 },
1428                   .mmio_gpio_set    = { 1, 1, 0 },
1429                   .scp_cmds_count   = 0,
1430                   .has_chipio_write = false,
1431                 },
1432                 /* Headphones. */
1433                 { .dac2port         = 0x21,
1434                   .has_hda_gpio     = false,
1435                   .mmio_gpio_count  = 3,
1436                   .mmio_gpio_pin    = { 2, 3, 5 },
1437                   .mmio_gpio_set    = { 0, 1, 1 },
1438                   .scp_cmds_count   = 0,
1439                   .has_chipio_write = false,
1440                 } },
1441         },
1442         { .quirk_id = QUIRK_AE5,
1443           .has_headphone_gain = true,
1444           .is_ae_series       = true,
1445           .out_set_info = {
1446                 /* Speakers. */
1447                 { .dac2port          = 0xa4,
1448                   .has_hda_gpio      = false,
1449                   .mmio_gpio_count   = 0,
1450                   .scp_cmds_count    = 2,
1451                   .scp_cmd_mid       = { 0x96, 0x96 },
1452                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1453                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1454                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1455                   .has_chipio_write  = true,
1456                   .chipio_write_addr = 0x0018b03c,
1457                   .chipio_write_data = 0x00000012
1458                 },
1459                 /* Headphones. */
1460                 { .dac2port          = 0xa1,
1461                   .has_hda_gpio      = false,
1462                   .mmio_gpio_count   = 0,
1463                   .scp_cmds_count    = 2,
1464                   .scp_cmd_mid       = { 0x96, 0x96 },
1465                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1466                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1467                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1468                   .has_chipio_write  = true,
1469                   .chipio_write_addr = 0x0018b03c,
1470                   .chipio_write_data = 0x00000012
1471                 } },
1472         },
1473         { .quirk_id = QUIRK_AE7,
1474           .has_headphone_gain = true,
1475           .is_ae_series       = true,
1476           .out_set_info = {
1477                 /* Speakers. */
1478                 { .dac2port          = 0x58,
1479                   .has_hda_gpio      = false,
1480                   .mmio_gpio_count   = 1,
1481                   .mmio_gpio_pin     = { 0 },
1482                   .mmio_gpio_set     = { 1 },
1483                   .scp_cmds_count    = 2,
1484                   .scp_cmd_mid       = { 0x96, 0x96 },
1485                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1486                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1487                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1488                   .has_chipio_write  = true,
1489                   .chipio_write_addr = 0x0018b03c,
1490                   .chipio_write_data = 0x00000000
1491                 },
1492                 /* Headphones. */
1493                 { .dac2port          = 0x58,
1494                   .has_hda_gpio      = false,
1495                   .mmio_gpio_count   = 1,
1496                   .mmio_gpio_pin     = { 0 },
1497                   .mmio_gpio_set     = { 1 },
1498                   .scp_cmds_count    = 2,
1499                   .scp_cmd_mid       = { 0x96, 0x96 },
1500                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1501                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1502                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1503                   .has_chipio_write  = true,
1504                   .chipio_write_addr = 0x0018b03c,
1505                   .chipio_write_data = 0x00000010
1506                 } },
1507         }
1508 };
1509
1510 /*
1511  * CA0132 codec access
1512  */
1513 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1514                 unsigned int verb, unsigned int parm, unsigned int *res)
1515 {
1516         unsigned int response;
1517         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1518         *res = response;
1519
1520         return ((response == -1) ? -1 : 0);
1521 }
1522
1523 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1524                 unsigned short converter_format, unsigned int *res)
1525 {
1526         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1527                                 converter_format & 0xffff, res);
1528 }
1529
1530 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1531                                 hda_nid_t nid, unsigned char stream,
1532                                 unsigned char channel, unsigned int *res)
1533 {
1534         unsigned char converter_stream_channel = 0;
1535
1536         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1537         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1538                                 converter_stream_channel, res);
1539 }
1540
1541 /* Chip access helper function */
1542 static int chipio_send(struct hda_codec *codec,
1543                        unsigned int reg,
1544                        unsigned int data)
1545 {
1546         unsigned int res;
1547         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1548
1549         /* send bits of data specified by reg */
1550         do {
1551                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1552                                          reg, data);
1553                 if (res == VENDOR_STATUS_CHIPIO_OK)
1554                         return 0;
1555                 msleep(20);
1556         } while (time_before(jiffies, timeout));
1557
1558         return -EIO;
1559 }
1560
1561 /*
1562  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1563  */
1564 static int chipio_write_address(struct hda_codec *codec,
1565                                 unsigned int chip_addx)
1566 {
1567         struct ca0132_spec *spec = codec->spec;
1568         int res;
1569
1570         if (spec->curr_chip_addx == chip_addx)
1571                         return 0;
1572
1573         /* send low 16 bits of the address */
1574         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1575                           chip_addx & 0xffff);
1576
1577         if (res != -EIO) {
1578                 /* send high 16 bits of the address */
1579                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1580                                   chip_addx >> 16);
1581         }
1582
1583         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1584
1585         return res;
1586 }
1587
1588 /*
1589  * Write data through the vendor widget -- NOT protected by the Mutex!
1590  */
1591 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1592 {
1593         struct ca0132_spec *spec = codec->spec;
1594         int res;
1595
1596         /* send low 16 bits of the data */
1597         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1598
1599         if (res != -EIO) {
1600                 /* send high 16 bits of the data */
1601                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1602                                   data >> 16);
1603         }
1604
1605         /*If no error encountered, automatically increment the address
1606         as per chip behaviour*/
1607         spec->curr_chip_addx = (res != -EIO) ?
1608                                         (spec->curr_chip_addx + 4) : ~0U;
1609         return res;
1610 }
1611
1612 /*
1613  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1614  */
1615 static int chipio_write_data_multiple(struct hda_codec *codec,
1616                                       const u32 *data,
1617                                       unsigned int count)
1618 {
1619         int status = 0;
1620
1621         if (data == NULL) {
1622                 codec_dbg(codec, "chipio_write_data null ptr\n");
1623                 return -EINVAL;
1624         }
1625
1626         while ((count-- != 0) && (status == 0))
1627                 status = chipio_write_data(codec, *data++);
1628
1629         return status;
1630 }
1631
1632
1633 /*
1634  * Read data through the vendor widget -- NOT protected by the Mutex!
1635  */
1636 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1637 {
1638         struct ca0132_spec *spec = codec->spec;
1639         int res;
1640
1641         /* post read */
1642         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1643
1644         if (res != -EIO) {
1645                 /* read status */
1646                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1647         }
1648
1649         if (res != -EIO) {
1650                 /* read data */
1651                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1652                                            VENDOR_CHIPIO_HIC_READ_DATA,
1653                                            0);
1654         }
1655
1656         /*If no error encountered, automatically increment the address
1657         as per chip behaviour*/
1658         spec->curr_chip_addx = (res != -EIO) ?
1659                                         (spec->curr_chip_addx + 4) : ~0U;
1660         return res;
1661 }
1662
1663 /*
1664  * Write given value to the given address through the chip I/O widget.
1665  * protected by the Mutex
1666  */
1667 static int chipio_write(struct hda_codec *codec,
1668                 unsigned int chip_addx, const unsigned int data)
1669 {
1670         struct ca0132_spec *spec = codec->spec;
1671         int err;
1672
1673         mutex_lock(&spec->chipio_mutex);
1674
1675         /* write the address, and if successful proceed to write data */
1676         err = chipio_write_address(codec, chip_addx);
1677         if (err < 0)
1678                 goto exit;
1679
1680         err = chipio_write_data(codec, data);
1681         if (err < 0)
1682                 goto exit;
1683
1684 exit:
1685         mutex_unlock(&spec->chipio_mutex);
1686         return err;
1687 }
1688
1689 /*
1690  * Write given value to the given address through the chip I/O widget.
1691  * not protected by the Mutex
1692  */
1693 static int chipio_write_no_mutex(struct hda_codec *codec,
1694                 unsigned int chip_addx, const unsigned int data)
1695 {
1696         int err;
1697
1698
1699         /* write the address, and if successful proceed to write data */
1700         err = chipio_write_address(codec, chip_addx);
1701         if (err < 0)
1702                 goto exit;
1703
1704         err = chipio_write_data(codec, data);
1705         if (err < 0)
1706                 goto exit;
1707
1708 exit:
1709         return err;
1710 }
1711
1712 /*
1713  * Write multiple values to the given address through the chip I/O widget.
1714  * protected by the Mutex
1715  */
1716 static int chipio_write_multiple(struct hda_codec *codec,
1717                                  u32 chip_addx,
1718                                  const u32 *data,
1719                                  unsigned int count)
1720 {
1721         struct ca0132_spec *spec = codec->spec;
1722         int status;
1723
1724         mutex_lock(&spec->chipio_mutex);
1725         status = chipio_write_address(codec, chip_addx);
1726         if (status < 0)
1727                 goto error;
1728
1729         status = chipio_write_data_multiple(codec, data, count);
1730 error:
1731         mutex_unlock(&spec->chipio_mutex);
1732
1733         return status;
1734 }
1735
1736 /*
1737  * Read the given address through the chip I/O widget
1738  * protected by the Mutex
1739  */
1740 static int chipio_read(struct hda_codec *codec,
1741                 unsigned int chip_addx, unsigned int *data)
1742 {
1743         struct ca0132_spec *spec = codec->spec;
1744         int err;
1745
1746         mutex_lock(&spec->chipio_mutex);
1747
1748         /* write the address, and if successful proceed to write data */
1749         err = chipio_write_address(codec, chip_addx);
1750         if (err < 0)
1751                 goto exit;
1752
1753         err = chipio_read_data(codec, data);
1754         if (err < 0)
1755                 goto exit;
1756
1757 exit:
1758         mutex_unlock(&spec->chipio_mutex);
1759         return err;
1760 }
1761
1762 /*
1763  * Set chip control flags through the chip I/O widget.
1764  */
1765 static void chipio_set_control_flag(struct hda_codec *codec,
1766                                     enum control_flag_id flag_id,
1767                                     bool flag_state)
1768 {
1769         unsigned int val;
1770         unsigned int flag_bit;
1771
1772         flag_bit = (flag_state ? 1 : 0);
1773         val = (flag_bit << 7) | (flag_id);
1774         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1775                             VENDOR_CHIPIO_FLAG_SET, val);
1776 }
1777
1778 /*
1779  * Set chip parameters through the chip I/O widget.
1780  */
1781 static void chipio_set_control_param(struct hda_codec *codec,
1782                 enum control_param_id param_id, int param_val)
1783 {
1784         struct ca0132_spec *spec = codec->spec;
1785         int val;
1786
1787         if ((param_id < 32) && (param_val < 8)) {
1788                 val = (param_val << 5) | (param_id);
1789                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790                                     VENDOR_CHIPIO_PARAM_SET, val);
1791         } else {
1792                 mutex_lock(&spec->chipio_mutex);
1793                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1794                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1796                                             param_id);
1797                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1798                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1799                                             param_val);
1800                 }
1801                 mutex_unlock(&spec->chipio_mutex);
1802         }
1803 }
1804
1805 /*
1806  * Set chip parameters through the chip I/O widget. NO MUTEX.
1807  */
1808 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1809                 enum control_param_id param_id, int param_val)
1810 {
1811         int val;
1812
1813         if ((param_id < 32) && (param_val < 8)) {
1814                 val = (param_val << 5) | (param_id);
1815                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1816                                     VENDOR_CHIPIO_PARAM_SET, val);
1817         } else {
1818                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1819                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1820                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1821                                             param_id);
1822                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1823                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1824                                             param_val);
1825                 }
1826         }
1827 }
1828 /*
1829  * Connect stream to a source point, and then connect
1830  * that source point to a destination point.
1831  */
1832 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1833                                 int streamid, int source_point, int dest_point)
1834 {
1835         chipio_set_control_param_no_mutex(codec,
1836                         CONTROL_PARAM_STREAM_ID, streamid);
1837         chipio_set_control_param_no_mutex(codec,
1838                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1839         chipio_set_control_param_no_mutex(codec,
1840                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1841 }
1842
1843 /*
1844  * Set number of channels in the selected stream.
1845  */
1846 static void chipio_set_stream_channels(struct hda_codec *codec,
1847                                 int streamid, unsigned int channels)
1848 {
1849         chipio_set_control_param_no_mutex(codec,
1850                         CONTROL_PARAM_STREAM_ID, streamid);
1851         chipio_set_control_param_no_mutex(codec,
1852                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1853 }
1854
1855 /*
1856  * Enable/Disable audio stream.
1857  */
1858 static void chipio_set_stream_control(struct hda_codec *codec,
1859                                 int streamid, int enable)
1860 {
1861         chipio_set_control_param_no_mutex(codec,
1862                         CONTROL_PARAM_STREAM_ID, streamid);
1863         chipio_set_control_param_no_mutex(codec,
1864                         CONTROL_PARAM_STREAM_CONTROL, enable);
1865 }
1866
1867 /*
1868  * Get ChipIO audio stream's status.
1869  */
1870 static void chipio_get_stream_control(struct hda_codec *codec,
1871                                 int streamid, unsigned int *enable)
1872 {
1873         chipio_set_control_param_no_mutex(codec,
1874                         CONTROL_PARAM_STREAM_ID, streamid);
1875         *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1876                            VENDOR_CHIPIO_PARAM_GET,
1877                            CONTROL_PARAM_STREAM_CONTROL);
1878 }
1879
1880 /*
1881  * Set sampling rate of the connection point. NO MUTEX.
1882  */
1883 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1884                                 int connid, enum ca0132_sample_rate rate)
1885 {
1886         chipio_set_control_param_no_mutex(codec,
1887                         CONTROL_PARAM_CONN_POINT_ID, connid);
1888         chipio_set_control_param_no_mutex(codec,
1889                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1890 }
1891
1892 /*
1893  * Set sampling rate of the connection point.
1894  */
1895 static void chipio_set_conn_rate(struct hda_codec *codec,
1896                                 int connid, enum ca0132_sample_rate rate)
1897 {
1898         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1899         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1900                                  rate);
1901 }
1902
1903 /*
1904  * Writes to the 8051's internal address space directly instead of indirectly,
1905  * giving access to the special function registers located at addresses
1906  * 0x80-0xFF.
1907  */
1908 static void chipio_8051_write_direct(struct hda_codec *codec,
1909                 unsigned int addr, unsigned int data)
1910 {
1911         unsigned int verb;
1912
1913         verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1914         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1915 }
1916
1917 /*
1918  * Writes to the 8051's exram, which has 16-bits of address space.
1919  * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1920  * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1921  * setting the pmem bank selection SFR.
1922  * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1923  * being writable.
1924  */
1925 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1926 {
1927         unsigned int tmp;
1928
1929         /* Lower 8-bits. */
1930         tmp = addr & 0xff;
1931         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1932                             VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1933
1934         /* Upper 8-bits. */
1935         tmp = (addr >> 8) & 0xff;
1936         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1937                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1938 }
1939
1940 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1941 {
1942         /* 8-bits of data. */
1943         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1944                             VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1945 }
1946
1947 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1948 {
1949         return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1950                                    VENDOR_CHIPIO_8051_DATA_READ, 0);
1951 }
1952
1953 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
1954 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1955 {
1956         /* 8-bits of data. */
1957         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958                             VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1959 }
1960
1961 static void chipio_8051_write_exram(struct hda_codec *codec,
1962                 unsigned int addr, unsigned int data)
1963 {
1964         struct ca0132_spec *spec = codec->spec;
1965
1966         mutex_lock(&spec->chipio_mutex);
1967
1968         chipio_8051_set_address(codec, addr);
1969         chipio_8051_set_data(codec, data);
1970
1971         mutex_unlock(&spec->chipio_mutex);
1972 }
1973
1974 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1975                 unsigned int addr, unsigned int data)
1976 {
1977         chipio_8051_set_address(codec, addr);
1978         chipio_8051_set_data(codec, data);
1979 }
1980
1981 /* Readback data from the 8051's exram. No mutex. */
1982 static void chipio_8051_read_exram(struct hda_codec *codec,
1983                 unsigned int addr, unsigned int *data)
1984 {
1985         chipio_8051_set_address(codec, addr);
1986         *data = chipio_8051_get_data(codec);
1987 }
1988
1989 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1990                 unsigned int addr, unsigned int data)
1991 {
1992         struct ca0132_spec *spec = codec->spec;
1993
1994         mutex_lock(&spec->chipio_mutex);
1995
1996         chipio_8051_set_address(codec, addr & 0xff);
1997         chipio_8051_set_data_pll(codec, data);
1998
1999         mutex_unlock(&spec->chipio_mutex);
2000 }
2001
2002 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2003                 unsigned int addr, unsigned int data)
2004 {
2005         chipio_8051_set_address(codec, addr & 0xff);
2006         chipio_8051_set_data_pll(codec, data);
2007 }
2008
2009 /*
2010  * Enable clocks.
2011  */
2012 static void chipio_enable_clocks(struct hda_codec *codec)
2013 {
2014         struct ca0132_spec *spec = codec->spec;
2015
2016         mutex_lock(&spec->chipio_mutex);
2017
2018         chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2019         chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2020         chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2021
2022         mutex_unlock(&spec->chipio_mutex);
2023 }
2024
2025 /*
2026  * CA0132 DSP IO stuffs
2027  */
2028 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2029                       unsigned int data)
2030 {
2031         int res;
2032         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2033
2034         /* send bits of data specified by reg to dsp */
2035         do {
2036                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2037                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2038                         return res;
2039                 msleep(20);
2040         } while (time_before(jiffies, timeout));
2041
2042         return -EIO;
2043 }
2044
2045 /*
2046  * Wait for DSP to be ready for commands
2047  */
2048 static void dspio_write_wait(struct hda_codec *codec)
2049 {
2050         int status;
2051         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2052
2053         do {
2054                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2055                                                 VENDOR_DSPIO_STATUS, 0);
2056                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2057                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2058                         break;
2059                 msleep(1);
2060         } while (time_before(jiffies, timeout));
2061 }
2062
2063 /*
2064  * Write SCP data to DSP
2065  */
2066 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2067 {
2068         struct ca0132_spec *spec = codec->spec;
2069         int status;
2070
2071         dspio_write_wait(codec);
2072
2073         mutex_lock(&spec->chipio_mutex);
2074         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2075                             scp_data & 0xffff);
2076         if (status < 0)
2077                 goto error;
2078
2079         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2080                                     scp_data >> 16);
2081         if (status < 0)
2082                 goto error;
2083
2084         /* OK, now check if the write itself has executed*/
2085         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2086                                     VENDOR_DSPIO_STATUS, 0);
2087 error:
2088         mutex_unlock(&spec->chipio_mutex);
2089
2090         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2091                         -EIO : 0;
2092 }
2093
2094 /*
2095  * Write multiple SCP data to DSP
2096  */
2097 static int dspio_write_multiple(struct hda_codec *codec,
2098                                 unsigned int *buffer, unsigned int size)
2099 {
2100         int status = 0;
2101         unsigned int count;
2102
2103         if (buffer == NULL)
2104                 return -EINVAL;
2105
2106         count = 0;
2107         while (count < size) {
2108                 status = dspio_write(codec, *buffer++);
2109                 if (status != 0)
2110                         break;
2111                 count++;
2112         }
2113
2114         return status;
2115 }
2116
2117 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2118 {
2119         int status;
2120
2121         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2122         if (status == -EIO)
2123                 return status;
2124
2125         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2126         if (status == -EIO ||
2127             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2128                 return -EIO;
2129
2130         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2131                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
2132
2133         return 0;
2134 }
2135
2136 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2137                                unsigned int *buf_size, unsigned int size_count)
2138 {
2139         int status = 0;
2140         unsigned int size = *buf_size;
2141         unsigned int count;
2142         unsigned int skip_count;
2143         unsigned int dummy;
2144
2145         if (buffer == NULL)
2146                 return -1;
2147
2148         count = 0;
2149         while (count < size && count < size_count) {
2150                 status = dspio_read(codec, buffer++);
2151                 if (status != 0)
2152                         break;
2153                 count++;
2154         }
2155
2156         skip_count = count;
2157         if (status == 0) {
2158                 while (skip_count < size) {
2159                         status = dspio_read(codec, &dummy);
2160                         if (status != 0)
2161                                 break;
2162                         skip_count++;
2163                 }
2164         }
2165         *buf_size = count;
2166
2167         return status;
2168 }
2169
2170 /*
2171  * Construct the SCP header using corresponding fields
2172  */
2173 static inline unsigned int
2174 make_scp_header(unsigned int target_id, unsigned int source_id,
2175                 unsigned int get_flag, unsigned int req,
2176                 unsigned int device_flag, unsigned int resp_flag,
2177                 unsigned int error_flag, unsigned int data_size)
2178 {
2179         unsigned int header = 0;
2180
2181         header = (data_size & 0x1f) << 27;
2182         header |= (error_flag & 0x01) << 26;
2183         header |= (resp_flag & 0x01) << 25;
2184         header |= (device_flag & 0x01) << 24;
2185         header |= (req & 0x7f) << 17;
2186         header |= (get_flag & 0x01) << 16;
2187         header |= (source_id & 0xff) << 8;
2188         header |= target_id & 0xff;
2189
2190         return header;
2191 }
2192
2193 /*
2194  * Extract corresponding fields from SCP header
2195  */
2196 static inline void
2197 extract_scp_header(unsigned int header,
2198                    unsigned int *target_id, unsigned int *source_id,
2199                    unsigned int *get_flag, unsigned int *req,
2200                    unsigned int *device_flag, unsigned int *resp_flag,
2201                    unsigned int *error_flag, unsigned int *data_size)
2202 {
2203         if (data_size)
2204                 *data_size = (header >> 27) & 0x1f;
2205         if (error_flag)
2206                 *error_flag = (header >> 26) & 0x01;
2207         if (resp_flag)
2208                 *resp_flag = (header >> 25) & 0x01;
2209         if (device_flag)
2210                 *device_flag = (header >> 24) & 0x01;
2211         if (req)
2212                 *req = (header >> 17) & 0x7f;
2213         if (get_flag)
2214                 *get_flag = (header >> 16) & 0x01;
2215         if (source_id)
2216                 *source_id = (header >> 8) & 0xff;
2217         if (target_id)
2218                 *target_id = header & 0xff;
2219 }
2220
2221 #define SCP_MAX_DATA_WORDS  (16)
2222
2223 /* Structure to contain any SCP message */
2224 struct scp_msg {
2225         unsigned int hdr;
2226         unsigned int data[SCP_MAX_DATA_WORDS];
2227 };
2228
2229 static void dspio_clear_response_queue(struct hda_codec *codec)
2230 {
2231         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2232         unsigned int dummy = 0;
2233         int status;
2234
2235         /* clear all from the response queue */
2236         do {
2237                 status = dspio_read(codec, &dummy);
2238         } while (status == 0 && time_before(jiffies, timeout));
2239 }
2240
2241 static int dspio_get_response_data(struct hda_codec *codec)
2242 {
2243         struct ca0132_spec *spec = codec->spec;
2244         unsigned int data = 0;
2245         unsigned int count;
2246
2247         if (dspio_read(codec, &data) < 0)
2248                 return -EIO;
2249
2250         if ((data & 0x00ffffff) == spec->wait_scp_header) {
2251                 spec->scp_resp_header = data;
2252                 spec->scp_resp_count = data >> 27;
2253                 count = spec->wait_num_data;
2254                 dspio_read_multiple(codec, spec->scp_resp_data,
2255                                     &spec->scp_resp_count, count);
2256                 return 0;
2257         }
2258
2259         return -EIO;
2260 }
2261
2262 /*
2263  * Send SCP message to DSP
2264  */
2265 static int dspio_send_scp_message(struct hda_codec *codec,
2266                                   unsigned char *send_buf,
2267                                   unsigned int send_buf_size,
2268                                   unsigned char *return_buf,
2269                                   unsigned int return_buf_size,
2270                                   unsigned int *bytes_returned)
2271 {
2272         struct ca0132_spec *spec = codec->spec;
2273         int status;
2274         unsigned int scp_send_size = 0;
2275         unsigned int total_size;
2276         bool waiting_for_resp = false;
2277         unsigned int header;
2278         struct scp_msg *ret_msg;
2279         unsigned int resp_src_id, resp_target_id;
2280         unsigned int data_size, src_id, target_id, get_flag, device_flag;
2281
2282         if (bytes_returned)
2283                 *bytes_returned = 0;
2284
2285         /* get scp header from buffer */
2286         header = *((unsigned int *)send_buf);
2287         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2288                            &device_flag, NULL, NULL, &data_size);
2289         scp_send_size = data_size + 1;
2290         total_size = (scp_send_size * 4);
2291
2292         if (send_buf_size < total_size)
2293                 return -EINVAL;
2294
2295         if (get_flag || device_flag) {
2296                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2297                         return -EINVAL;
2298
2299                 spec->wait_scp_header = *((unsigned int *)send_buf);
2300
2301                 /* swap source id with target id */
2302                 resp_target_id = src_id;
2303                 resp_src_id = target_id;
2304                 spec->wait_scp_header &= 0xffff0000;
2305                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2306                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2307                 spec->wait_scp = 1;
2308                 waiting_for_resp = true;
2309         }
2310
2311         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2312                                       scp_send_size);
2313         if (status < 0) {
2314                 spec->wait_scp = 0;
2315                 return status;
2316         }
2317
2318         if (waiting_for_resp) {
2319                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2320                 memset(return_buf, 0, return_buf_size);
2321                 do {
2322                         msleep(20);
2323                 } while (spec->wait_scp && time_before(jiffies, timeout));
2324                 waiting_for_resp = false;
2325                 if (!spec->wait_scp) {
2326                         ret_msg = (struct scp_msg *)return_buf;
2327                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2328                         memcpy(&ret_msg->data, spec->scp_resp_data,
2329                                spec->wait_num_data);
2330                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
2331                         status = 0;
2332                 } else {
2333                         status = -EIO;
2334                 }
2335                 spec->wait_scp = 0;
2336         }
2337
2338         return status;
2339 }
2340
2341 /**
2342  * dspio_scp - Prepare and send the SCP message to DSP
2343  * @codec: the HDA codec
2344  * @mod_id: ID of the DSP module to send the command
2345  * @src_id: ID of the source
2346  * @req: ID of request to send to the DSP module
2347  * @dir: SET or GET
2348  * @data: pointer to the data to send with the request, request specific
2349  * @len: length of the data, in bytes
2350  * @reply: point to the buffer to hold data returned for a reply
2351  * @reply_len: length of the reply buffer returned from GET
2352  *
2353  * Returns zero or a negative error code.
2354  */
2355 static int dspio_scp(struct hda_codec *codec,
2356                 int mod_id, int src_id, int req, int dir, const void *data,
2357                 unsigned int len, void *reply, unsigned int *reply_len)
2358 {
2359         int status = 0;
2360         struct scp_msg scp_send, scp_reply;
2361         unsigned int ret_bytes, send_size, ret_size;
2362         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2363         unsigned int reply_data_size;
2364
2365         memset(&scp_send, 0, sizeof(scp_send));
2366         memset(&scp_reply, 0, sizeof(scp_reply));
2367
2368         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2369                 return -EINVAL;
2370
2371         if (dir == SCP_GET && reply == NULL) {
2372                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2373                 return -EINVAL;
2374         }
2375
2376         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2377                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2378                 return -EINVAL;
2379         }
2380
2381         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2382                                        0, 0, 0, len/sizeof(unsigned int));
2383         if (data != NULL && len > 0) {
2384                 len = min((unsigned int)(sizeof(scp_send.data)), len);
2385                 memcpy(scp_send.data, data, len);
2386         }
2387
2388         ret_bytes = 0;
2389         send_size = sizeof(unsigned int) + len;
2390         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2391                                         send_size, (unsigned char *)&scp_reply,
2392                                         sizeof(scp_reply), &ret_bytes);
2393
2394         if (status < 0) {
2395                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2396                 return status;
2397         }
2398
2399         /* extract send and reply headers members */
2400         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2401                            NULL, NULL, NULL, NULL, NULL);
2402         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2403                            &reply_resp_flag, &reply_error_flag,
2404                            &reply_data_size);
2405
2406         if (!send_get_flag)
2407                 return 0;
2408
2409         if (reply_resp_flag && !reply_error_flag) {
2410                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2411                                         / sizeof(unsigned int);
2412
2413                 if (*reply_len < ret_size*sizeof(unsigned int)) {
2414                         codec_dbg(codec, "reply too long for buf\n");
2415                         return -EINVAL;
2416                 } else if (ret_size != reply_data_size) {
2417                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2418                         return -EINVAL;
2419                 } else if (!reply) {
2420                         codec_dbg(codec, "NULL reply\n");
2421                         return -EINVAL;
2422                 } else {
2423                         *reply_len = ret_size*sizeof(unsigned int);
2424                         memcpy(reply, scp_reply.data, *reply_len);
2425                 }
2426         } else {
2427                 codec_dbg(codec, "reply ill-formed or errflag set\n");
2428                 return -EIO;
2429         }
2430
2431         return status;
2432 }
2433
2434 /*
2435  * Set DSP parameters
2436  */
2437 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2438                         int src_id, int req, const void *data, unsigned int len)
2439 {
2440         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2441                         NULL);
2442 }
2443
2444 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2445                         int req, const unsigned int data)
2446 {
2447         return dspio_set_param(codec, mod_id, 0x20, req, &data,
2448                         sizeof(unsigned int));
2449 }
2450
2451 /*
2452  * Allocate a DSP DMA channel via an SCP message
2453  */
2454 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2455 {
2456         int status = 0;
2457         unsigned int size = sizeof(*dma_chan);
2458
2459         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2460         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2461                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2462                         dma_chan, &size);
2463
2464         if (status < 0) {
2465                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2466                 return status;
2467         }
2468
2469         if ((*dma_chan + 1) == 0) {
2470                 codec_dbg(codec, "no free dma channels to allocate\n");
2471                 return -EBUSY;
2472         }
2473
2474         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2475         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2476
2477         return status;
2478 }
2479
2480 /*
2481  * Free a DSP DMA via an SCP message
2482  */
2483 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2484 {
2485         int status = 0;
2486         unsigned int dummy = 0;
2487
2488         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2489         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2490
2491         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2492                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2493                         sizeof(dma_chan), NULL, &dummy);
2494
2495         if (status < 0) {
2496                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2497                 return status;
2498         }
2499
2500         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2501
2502         return status;
2503 }
2504
2505 /*
2506  * (Re)start the DSP
2507  */
2508 static int dsp_set_run_state(struct hda_codec *codec)
2509 {
2510         unsigned int dbg_ctrl_reg;
2511         unsigned int halt_state;
2512         int err;
2513
2514         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2515         if (err < 0)
2516                 return err;
2517
2518         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2519                       DSP_DBGCNTL_STATE_LOBIT;
2520
2521         if (halt_state != 0) {
2522                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2523                                   DSP_DBGCNTL_SS_MASK);
2524                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2525                                    dbg_ctrl_reg);
2526                 if (err < 0)
2527                         return err;
2528
2529                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2530                                 DSP_DBGCNTL_EXEC_MASK;
2531                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2532                                    dbg_ctrl_reg);
2533                 if (err < 0)
2534                         return err;
2535         }
2536
2537         return 0;
2538 }
2539
2540 /*
2541  * Reset the DSP
2542  */
2543 static int dsp_reset(struct hda_codec *codec)
2544 {
2545         unsigned int res;
2546         int retry = 20;
2547
2548         codec_dbg(codec, "dsp_reset\n");
2549         do {
2550                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2551                 retry--;
2552         } while (res == -EIO && retry);
2553
2554         if (!retry) {
2555                 codec_dbg(codec, "dsp_reset timeout\n");
2556                 return -EIO;
2557         }
2558
2559         return 0;
2560 }
2561
2562 /*
2563  * Convert chip address to DSP address
2564  */
2565 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2566                                         bool *code, bool *yram)
2567 {
2568         *code = *yram = false;
2569
2570         if (UC_RANGE(chip_addx, 1)) {
2571                 *code = true;
2572                 return UC_OFF(chip_addx);
2573         } else if (X_RANGE_ALL(chip_addx, 1)) {
2574                 return X_OFF(chip_addx);
2575         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2576                 *yram = true;
2577                 return Y_OFF(chip_addx);
2578         }
2579
2580         return INVALID_CHIP_ADDRESS;
2581 }
2582
2583 /*
2584  * Check if the DSP DMA is active
2585  */
2586 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2587 {
2588         unsigned int dma_chnlstart_reg;
2589
2590         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2591
2592         return ((dma_chnlstart_reg & (1 <<
2593                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2594 }
2595
2596 static int dsp_dma_setup_common(struct hda_codec *codec,
2597                                 unsigned int chip_addx,
2598                                 unsigned int dma_chan,
2599                                 unsigned int port_map_mask,
2600                                 bool ovly)
2601 {
2602         int status = 0;
2603         unsigned int chnl_prop;
2604         unsigned int dsp_addx;
2605         unsigned int active;
2606         bool code, yram;
2607
2608         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2609
2610         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2611                 codec_dbg(codec, "dma chan num invalid\n");
2612                 return -EINVAL;
2613         }
2614
2615         if (dsp_is_dma_active(codec, dma_chan)) {
2616                 codec_dbg(codec, "dma already active\n");
2617                 return -EBUSY;
2618         }
2619
2620         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2621
2622         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2623                 codec_dbg(codec, "invalid chip addr\n");
2624                 return -ENXIO;
2625         }
2626
2627         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2628         active = 0;
2629
2630         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2631
2632         if (ovly) {
2633                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2634                                      &chnl_prop);
2635
2636                 if (status < 0) {
2637                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2638                         return status;
2639                 }
2640                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2641         }
2642
2643         if (!code)
2644                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2645         else
2646                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2647
2648         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2649
2650         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2651         if (status < 0) {
2652                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2653                 return status;
2654         }
2655         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2656
2657         if (ovly) {
2658                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2659                                      &active);
2660
2661                 if (status < 0) {
2662                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2663                         return status;
2664                 }
2665                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2666         }
2667
2668         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2669                 DSPDMAC_ACTIVE_AAR_MASK;
2670
2671         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2672         if (status < 0) {
2673                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2674                 return status;
2675         }
2676
2677         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2678
2679         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2680                               port_map_mask);
2681         if (status < 0) {
2682                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2683                 return status;
2684         }
2685         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2686
2687         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2688                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2689         if (status < 0) {
2690                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2691                 return status;
2692         }
2693         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2694
2695         codec_dbg(codec,
2696                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2697                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2698                    chip_addx, dsp_addx, dma_chan,
2699                    port_map_mask, chnl_prop, active);
2700
2701         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2702
2703         return 0;
2704 }
2705
2706 /*
2707  * Setup the DSP DMA per-transfer-specific registers
2708  */
2709 static int dsp_dma_setup(struct hda_codec *codec,
2710                         unsigned int chip_addx,
2711                         unsigned int count,
2712                         unsigned int dma_chan)
2713 {
2714         int status = 0;
2715         bool code, yram;
2716         unsigned int dsp_addx;
2717         unsigned int addr_field;
2718         unsigned int incr_field;
2719         unsigned int base_cnt;
2720         unsigned int cur_cnt;
2721         unsigned int dma_cfg = 0;
2722         unsigned int adr_ofs = 0;
2723         unsigned int xfr_cnt = 0;
2724         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2725                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2726
2727         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2728
2729         if (count > max_dma_count) {
2730                 codec_dbg(codec, "count too big\n");
2731                 return -EINVAL;
2732         }
2733
2734         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2735         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2736                 codec_dbg(codec, "invalid chip addr\n");
2737                 return -ENXIO;
2738         }
2739
2740         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2741
2742         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2743         incr_field   = 0;
2744
2745         if (!code) {
2746                 addr_field <<= 1;
2747                 if (yram)
2748                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2749
2750                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2751         }
2752
2753         dma_cfg = addr_field + incr_field;
2754         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2755                                 dma_cfg);
2756         if (status < 0) {
2757                 codec_dbg(codec, "write DMACFG Reg fail\n");
2758                 return status;
2759         }
2760         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2761
2762         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2763                                                         (code ? 0 : 1));
2764
2765         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2766                                 adr_ofs);
2767         if (status < 0) {
2768                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2769                 return status;
2770         }
2771         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2772
2773         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2774
2775         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2776
2777         xfr_cnt = base_cnt | cur_cnt;
2778
2779         status = chipio_write(codec,
2780                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2781         if (status < 0) {
2782                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2783                 return status;
2784         }
2785         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2786
2787         codec_dbg(codec,
2788                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2789                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2790                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2791
2792         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2793
2794         return 0;
2795 }
2796
2797 /*
2798  * Start the DSP DMA
2799  */
2800 static int dsp_dma_start(struct hda_codec *codec,
2801                          unsigned int dma_chan, bool ovly)
2802 {
2803         unsigned int reg = 0;
2804         int status = 0;
2805
2806         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2807
2808         if (ovly) {
2809                 status = chipio_read(codec,
2810                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2811
2812                 if (status < 0) {
2813                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2814                         return status;
2815                 }
2816                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2817
2818                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2819                                 DSPDMAC_CHNLSTART_DIS_MASK);
2820         }
2821
2822         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2823                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2824         if (status < 0) {
2825                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2826                 return status;
2827         }
2828         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2829
2830         return status;
2831 }
2832
2833 /*
2834  * Stop the DSP DMA
2835  */
2836 static int dsp_dma_stop(struct hda_codec *codec,
2837                         unsigned int dma_chan, bool ovly)
2838 {
2839         unsigned int reg = 0;
2840         int status = 0;
2841
2842         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2843
2844         if (ovly) {
2845                 status = chipio_read(codec,
2846                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2847
2848                 if (status < 0) {
2849                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2850                         return status;
2851                 }
2852                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2853                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2854                                 DSPDMAC_CHNLSTART_DIS_MASK);
2855         }
2856
2857         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2858                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2859         if (status < 0) {
2860                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2861                 return status;
2862         }
2863         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2864
2865         return status;
2866 }
2867
2868 /**
2869  * dsp_allocate_router_ports - Allocate router ports
2870  *
2871  * @codec: the HDA codec
2872  * @num_chans: number of channels in the stream
2873  * @ports_per_channel: number of ports per channel
2874  * @start_device: start device
2875  * @port_map: pointer to the port list to hold the allocated ports
2876  *
2877  * Returns zero or a negative error code.
2878  */
2879 static int dsp_allocate_router_ports(struct hda_codec *codec,
2880                                      unsigned int num_chans,
2881                                      unsigned int ports_per_channel,
2882                                      unsigned int start_device,
2883                                      unsigned int *port_map)
2884 {
2885         int status = 0;
2886         int res;
2887         u8 val;
2888
2889         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2890         if (status < 0)
2891                 return status;
2892
2893         val = start_device << 6;
2894         val |= (ports_per_channel - 1) << 4;
2895         val |= num_chans - 1;
2896
2897         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2898                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2899                             val);
2900
2901         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2902                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2903                             MEM_CONNID_DSP);
2904
2905         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2906         if (status < 0)
2907                 return status;
2908
2909         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2910                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2911
2912         *port_map = res;
2913
2914         return (res < 0) ? res : 0;
2915 }
2916
2917 /*
2918  * Free router ports
2919  */
2920 static int dsp_free_router_ports(struct hda_codec *codec)
2921 {
2922         int status = 0;
2923
2924         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2925         if (status < 0)
2926                 return status;
2927
2928         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2929                             VENDOR_CHIPIO_PORT_FREE_SET,
2930                             MEM_CONNID_DSP);
2931
2932         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2933
2934         return status;
2935 }
2936
2937 /*
2938  * Allocate DSP ports for the download stream
2939  */
2940 static int dsp_allocate_ports(struct hda_codec *codec,
2941                         unsigned int num_chans,
2942                         unsigned int rate_multi, unsigned int *port_map)
2943 {
2944         int status;
2945
2946         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2947
2948         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2949                 codec_dbg(codec, "bad rate multiple\n");
2950                 return -EINVAL;
2951         }
2952
2953         status = dsp_allocate_router_ports(codec, num_chans,
2954                                            rate_multi, 0, port_map);
2955
2956         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2957
2958         return status;
2959 }
2960
2961 static int dsp_allocate_ports_format(struct hda_codec *codec,
2962                         const unsigned short fmt,
2963                         unsigned int *port_map)
2964 {
2965         int status;
2966         unsigned int num_chans;
2967
2968         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2969         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2970         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2971
2972         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2973                 codec_dbg(codec, "bad rate multiple\n");
2974                 return -EINVAL;
2975         }
2976
2977         num_chans = get_hdafmt_chs(fmt) + 1;
2978
2979         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2980
2981         return status;
2982 }
2983
2984 /*
2985  * free DSP ports
2986  */
2987 static int dsp_free_ports(struct hda_codec *codec)
2988 {
2989         int status;
2990
2991         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2992
2993         status = dsp_free_router_ports(codec);
2994         if (status < 0) {
2995                 codec_dbg(codec, "free router ports fail\n");
2996                 return status;
2997         }
2998         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2999
3000         return status;
3001 }
3002
3003 /*
3004  *  HDA DMA engine stuffs for DSP code download
3005  */
3006 struct dma_engine {
3007         struct hda_codec *codec;
3008         unsigned short m_converter_format;
3009         struct snd_dma_buffer *dmab;
3010         unsigned int buf_size;
3011 };
3012
3013
3014 enum dma_state {
3015         DMA_STATE_STOP  = 0,
3016         DMA_STATE_RUN   = 1
3017 };
3018
3019 static int dma_convert_to_hda_format(struct hda_codec *codec,
3020                 unsigned int sample_rate,
3021                 unsigned short channels,
3022                 unsigned short *hda_format)
3023 {
3024         unsigned int format_val;
3025
3026         format_val = snd_hdac_calc_stream_format(sample_rate,
3027                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3028
3029         if (hda_format)
3030                 *hda_format = (unsigned short)format_val;
3031
3032         return 0;
3033 }
3034
3035 /*
3036  *  Reset DMA for DSP download
3037  */
3038 static int dma_reset(struct dma_engine *dma)
3039 {
3040         struct hda_codec *codec = dma->codec;
3041         struct ca0132_spec *spec = codec->spec;
3042         int status;
3043
3044         if (dma->dmab->area)
3045                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3046
3047         status = snd_hda_codec_load_dsp_prepare(codec,
3048                         dma->m_converter_format,
3049                         dma->buf_size,
3050                         dma->dmab);
3051         if (status < 0)
3052                 return status;
3053         spec->dsp_stream_id = status;
3054         return 0;
3055 }
3056
3057 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3058 {
3059         bool cmd;
3060
3061         switch (state) {
3062         case DMA_STATE_STOP:
3063                 cmd = false;
3064                 break;
3065         case DMA_STATE_RUN:
3066                 cmd = true;
3067                 break;
3068         default:
3069                 return 0;
3070         }
3071
3072         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3073         return 0;
3074 }
3075
3076 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3077 {
3078         return dma->dmab->bytes;
3079 }
3080
3081 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3082 {
3083         return dma->dmab->area;
3084 }
3085
3086 static int dma_xfer(struct dma_engine *dma,
3087                 const unsigned int *data,
3088                 unsigned int count)
3089 {
3090         memcpy(dma->dmab->area, data, count);
3091         return 0;
3092 }
3093
3094 static void dma_get_converter_format(
3095                 struct dma_engine *dma,
3096                 unsigned short *format)
3097 {
3098         if (format)
3099                 *format = dma->m_converter_format;
3100 }
3101
3102 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3103 {
3104         struct ca0132_spec *spec = dma->codec->spec;
3105
3106         return spec->dsp_stream_id;
3107 }
3108
3109 struct dsp_image_seg {
3110         u32 magic;
3111         u32 chip_addr;
3112         u32 count;
3113         u32 data[];
3114 };
3115
3116 static const u32 g_magic_value = 0x4c46584d;
3117 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3118
3119 static bool is_valid(const struct dsp_image_seg *p)
3120 {
3121         return p->magic == g_magic_value;
3122 }
3123
3124 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3125 {
3126         return g_chip_addr_magic_value == p->chip_addr;
3127 }
3128
3129 static bool is_last(const struct dsp_image_seg *p)
3130 {
3131         return p->count == 0;
3132 }
3133
3134 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3135 {
3136         return struct_size(p, data, p->count);
3137 }
3138
3139 static const struct dsp_image_seg *get_next_seg_ptr(
3140                                 const struct dsp_image_seg *p)
3141 {
3142         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3143 }
3144
3145 /*
3146  * CA0132 chip DSP transfer stuffs.  For DSP download.
3147  */
3148 #define INVALID_DMA_CHANNEL (~0U)
3149
3150 /*
3151  * Program a list of address/data pairs via the ChipIO widget.
3152  * The segment data is in the format of successive pairs of words.
3153  * These are repeated as indicated by the segment's count field.
3154  */
3155 static int dspxfr_hci_write(struct hda_codec *codec,
3156                         const struct dsp_image_seg *fls)
3157 {
3158         int status;
3159         const u32 *data;
3160         unsigned int count;
3161
3162         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3163                 codec_dbg(codec, "hci_write invalid params\n");
3164                 return -EINVAL;
3165         }
3166
3167         count = fls->count;
3168         data = (u32 *)(fls->data);
3169         while (count >= 2) {
3170                 status = chipio_write(codec, data[0], data[1]);
3171                 if (status < 0) {
3172                         codec_dbg(codec, "hci_write chipio failed\n");
3173                         return status;
3174                 }
3175                 count -= 2;
3176                 data  += 2;
3177         }
3178         return 0;
3179 }
3180
3181 /**
3182  * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3183  *
3184  * @codec: the HDA codec
3185  * @fls: pointer to a fast load image
3186  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3187  *         no relocation
3188  * @dma_engine: pointer to DMA engine to be used for DSP download
3189  * @dma_chan: The number of DMA channels used for DSP download
3190  * @port_map_mask: port mapping
3191  * @ovly: TRUE if overlay format is required
3192  *
3193  * Returns zero or a negative error code.
3194  */
3195 static int dspxfr_one_seg(struct hda_codec *codec,
3196                         const struct dsp_image_seg *fls,
3197                         unsigned int reloc,
3198                         struct dma_engine *dma_engine,
3199                         unsigned int dma_chan,
3200                         unsigned int port_map_mask,
3201                         bool ovly)
3202 {
3203         int status = 0;
3204         bool comm_dma_setup_done = false;
3205         const unsigned int *data;
3206         unsigned int chip_addx;
3207         unsigned int words_to_write;
3208         unsigned int buffer_size_words;
3209         unsigned char *buffer_addx;
3210         unsigned short hda_format;
3211         unsigned int sample_rate_div;
3212         unsigned int sample_rate_mul;
3213         unsigned int num_chans;
3214         unsigned int hda_frame_size_words;
3215         unsigned int remainder_words;
3216         const u32 *data_remainder;
3217         u32 chip_addx_remainder;
3218         unsigned int run_size_words;
3219         const struct dsp_image_seg *hci_write = NULL;
3220         unsigned long timeout;
3221         bool dma_active;
3222
3223         if (fls == NULL)
3224                 return -EINVAL;
3225         if (is_hci_prog_list_seg(fls)) {
3226                 hci_write = fls;
3227                 fls = get_next_seg_ptr(fls);
3228         }
3229
3230         if (hci_write && (!fls || is_last(fls))) {
3231                 codec_dbg(codec, "hci_write\n");
3232                 return dspxfr_hci_write(codec, hci_write);
3233         }
3234
3235         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3236                 codec_dbg(codec, "Invalid Params\n");
3237                 return -EINVAL;
3238         }
3239
3240         data = fls->data;
3241         chip_addx = fls->chip_addr;
3242         words_to_write = fls->count;
3243
3244         if (!words_to_write)
3245                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3246         if (reloc)
3247                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3248
3249         if (!UC_RANGE(chip_addx, words_to_write) &&
3250             !X_RANGE_ALL(chip_addx, words_to_write) &&
3251             !Y_RANGE_ALL(chip_addx, words_to_write)) {
3252                 codec_dbg(codec, "Invalid chip_addx Params\n");
3253                 return -EINVAL;
3254         }
3255
3256         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3257                                         sizeof(u32);
3258
3259         buffer_addx = dma_get_buffer_addr(dma_engine);
3260
3261         if (buffer_addx == NULL) {
3262                 codec_dbg(codec, "dma_engine buffer NULL\n");
3263                 return -EINVAL;
3264         }
3265
3266         dma_get_converter_format(dma_engine, &hda_format);
3267         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3268         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3269         num_chans = get_hdafmt_chs(hda_format) + 1;
3270
3271         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3272                         (num_chans * sample_rate_mul / sample_rate_div));
3273
3274         if (hda_frame_size_words == 0) {
3275                 codec_dbg(codec, "frmsz zero\n");
3276                 return -EINVAL;
3277         }
3278
3279         buffer_size_words = min(buffer_size_words,
3280                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3281                                 65536 : 32768));
3282         buffer_size_words -= buffer_size_words % hda_frame_size_words;
3283         codec_dbg(codec,
3284                    "chpadr=0x%08x frmsz=%u nchan=%u "
3285                    "rate_mul=%u div=%u bufsz=%u\n",
3286                    chip_addx, hda_frame_size_words, num_chans,
3287                    sample_rate_mul, sample_rate_div, buffer_size_words);
3288
3289         if (buffer_size_words < hda_frame_size_words) {
3290                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3291                 return -EINVAL;
3292         }
3293
3294         remainder_words = words_to_write % hda_frame_size_words;
3295         data_remainder = data;
3296         chip_addx_remainder = chip_addx;
3297
3298         data += remainder_words;
3299         chip_addx += remainder_words*sizeof(u32);
3300         words_to_write -= remainder_words;
3301
3302         while (words_to_write != 0) {
3303                 run_size_words = min(buffer_size_words, words_to_write);
3304                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3305                             words_to_write, run_size_words, remainder_words);
3306                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3307                 if (!comm_dma_setup_done) {
3308                         status = dsp_dma_stop(codec, dma_chan, ovly);
3309                         if (status < 0)
3310                                 return status;
3311                         status = dsp_dma_setup_common(codec, chip_addx,
3312                                                 dma_chan, port_map_mask, ovly);
3313                         if (status < 0)
3314                                 return status;
3315                         comm_dma_setup_done = true;
3316                 }
3317
3318                 status = dsp_dma_setup(codec, chip_addx,
3319                                                 run_size_words, dma_chan);
3320                 if (status < 0)
3321                         return status;
3322                 status = dsp_dma_start(codec, dma_chan, ovly);
3323                 if (status < 0)
3324                         return status;
3325                 if (!dsp_is_dma_active(codec, dma_chan)) {
3326                         codec_dbg(codec, "dspxfr:DMA did not start\n");
3327                         return -EIO;
3328                 }
3329                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3330                 if (status < 0)
3331                         return status;
3332                 if (remainder_words != 0) {
3333                         status = chipio_write_multiple(codec,
3334                                                 chip_addx_remainder,
3335                                                 data_remainder,
3336                                                 remainder_words);
3337                         if (status < 0)
3338                                 return status;
3339                         remainder_words = 0;
3340                 }
3341                 if (hci_write) {
3342                         status = dspxfr_hci_write(codec, hci_write);
3343                         if (status < 0)
3344                                 return status;
3345                         hci_write = NULL;
3346                 }
3347
3348                 timeout = jiffies + msecs_to_jiffies(2000);
3349                 do {
3350                         dma_active = dsp_is_dma_active(codec, dma_chan);
3351                         if (!dma_active)
3352                                 break;
3353                         msleep(20);
3354                 } while (time_before(jiffies, timeout));
3355                 if (dma_active)
3356                         break;
3357
3358                 codec_dbg(codec, "+++++ DMA complete\n");
3359                 dma_set_state(dma_engine, DMA_STATE_STOP);
3360                 status = dma_reset(dma_engine);
3361
3362                 if (status < 0)
3363                         return status;
3364
3365                 data += run_size_words;
3366                 chip_addx += run_size_words*sizeof(u32);
3367                 words_to_write -= run_size_words;
3368         }
3369
3370         if (remainder_words != 0) {
3371                 status = chipio_write_multiple(codec, chip_addx_remainder,
3372                                         data_remainder, remainder_words);
3373         }
3374
3375         return status;
3376 }
3377
3378 /**
3379  * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3380  *
3381  * @codec: the HDA codec
3382  * @fls_data: pointer to a fast load image
3383  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3384  *         no relocation
3385  * @sample_rate: sampling rate of the stream used for DSP download
3386  * @channels: channels of the stream used for DSP download
3387  * @ovly: TRUE if overlay format is required
3388  *
3389  * Returns zero or a negative error code.
3390  */
3391 static int dspxfr_image(struct hda_codec *codec,
3392                         const struct dsp_image_seg *fls_data,
3393                         unsigned int reloc,
3394                         unsigned int sample_rate,
3395                         unsigned short channels,
3396                         bool ovly)
3397 {
3398         struct ca0132_spec *spec = codec->spec;
3399         int status;
3400         unsigned short hda_format = 0;
3401         unsigned int response;
3402         unsigned char stream_id = 0;
3403         struct dma_engine *dma_engine;
3404         unsigned int dma_chan;
3405         unsigned int port_map_mask;
3406
3407         if (fls_data == NULL)
3408                 return -EINVAL;
3409
3410         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3411         if (!dma_engine)
3412                 return -ENOMEM;
3413
3414         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3415         if (!dma_engine->dmab) {
3416                 kfree(dma_engine);
3417                 return -ENOMEM;
3418         }
3419
3420         dma_engine->codec = codec;
3421         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3422         dma_engine->m_converter_format = hda_format;
3423         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3424                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3425
3426         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3427
3428         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3429                                         hda_format, &response);
3430
3431         if (status < 0) {
3432                 codec_dbg(codec, "set converter format fail\n");
3433                 goto exit;
3434         }
3435
3436         status = snd_hda_codec_load_dsp_prepare(codec,
3437                                 dma_engine->m_converter_format,
3438                                 dma_engine->buf_size,
3439                                 dma_engine->dmab);
3440         if (status < 0)
3441                 goto exit;
3442         spec->dsp_stream_id = status;
3443
3444         if (ovly) {
3445                 status = dspio_alloc_dma_chan(codec, &dma_chan);
3446                 if (status < 0) {
3447                         codec_dbg(codec, "alloc dmachan fail\n");
3448                         dma_chan = INVALID_DMA_CHANNEL;
3449                         goto exit;
3450                 }
3451         }
3452
3453         port_map_mask = 0;
3454         status = dsp_allocate_ports_format(codec, hda_format,
3455                                         &port_map_mask);
3456         if (status < 0) {
3457                 codec_dbg(codec, "alloc ports fail\n");
3458                 goto exit;
3459         }
3460
3461         stream_id = dma_get_stream_id(dma_engine);
3462         status = codec_set_converter_stream_channel(codec,
3463                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
3464         if (status < 0) {
3465                 codec_dbg(codec, "set stream chan fail\n");
3466                 goto exit;
3467         }
3468
3469         while ((fls_data != NULL) && !is_last(fls_data)) {
3470                 if (!is_valid(fls_data)) {
3471                         codec_dbg(codec, "FLS check fail\n");
3472                         status = -EINVAL;
3473                         goto exit;
3474                 }
3475                 status = dspxfr_one_seg(codec, fls_data, reloc,
3476                                         dma_engine, dma_chan,
3477                                         port_map_mask, ovly);
3478                 if (status < 0)
3479                         break;
3480
3481                 if (is_hci_prog_list_seg(fls_data))
3482                         fls_data = get_next_seg_ptr(fls_data);
3483
3484                 if ((fls_data != NULL) && !is_last(fls_data))
3485                         fls_data = get_next_seg_ptr(fls_data);
3486         }
3487
3488         if (port_map_mask != 0)
3489                 status = dsp_free_ports(codec);
3490
3491         if (status < 0)
3492                 goto exit;
3493
3494         status = codec_set_converter_stream_channel(codec,
3495                                 WIDGET_CHIP_CTRL, 0, 0, &response);
3496
3497 exit:
3498         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3499                 dspio_free_dma_chan(codec, dma_chan);
3500
3501         if (dma_engine->dmab->area)
3502                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3503         kfree(dma_engine->dmab);
3504         kfree(dma_engine);
3505
3506         return status;
3507 }
3508
3509 /*
3510  * CA0132 DSP download stuffs.
3511  */
3512 static void dspload_post_setup(struct hda_codec *codec)
3513 {
3514         struct ca0132_spec *spec = codec->spec;
3515         codec_dbg(codec, "---- dspload_post_setup ------\n");
3516         if (!ca0132_use_alt_functions(spec)) {
3517                 /*set DSP speaker to 2.0 configuration*/
3518                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3519                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3520
3521                 /*update write pointer*/
3522                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3523         }
3524 }
3525
3526 /**
3527  * dspload_image - Download DSP from a DSP Image Fast Load structure.
3528  *
3529  * @codec: the HDA codec
3530  * @fls: pointer to a fast load image
3531  * @ovly: TRUE if overlay format is required
3532  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3533  *         no relocation
3534  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3535  * @router_chans: number of audio router channels to be allocated (0 means use
3536  *                internal defaults; max is 32)
3537  *
3538  * Download DSP from a DSP Image Fast Load structure. This structure is a
3539  * linear, non-constant sized element array of structures, each of which
3540  * contain the count of the data to be loaded, the data itself, and the
3541  * corresponding starting chip address of the starting data location.
3542  * Returns zero or a negative error code.
3543  */
3544 static int dspload_image(struct hda_codec *codec,
3545                         const struct dsp_image_seg *fls,
3546                         bool ovly,
3547                         unsigned int reloc,
3548                         bool autostart,
3549                         int router_chans)
3550 {
3551         int status = 0;
3552         unsigned int sample_rate;
3553         unsigned short channels;
3554
3555         codec_dbg(codec, "---- dspload_image begin ------\n");
3556         if (router_chans == 0) {
3557                 if (!ovly)
3558                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3559                 else
3560                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3561         }
3562
3563         sample_rate = 48000;
3564         channels = (unsigned short)router_chans;
3565
3566         while (channels > 16) {
3567                 sample_rate *= 2;
3568                 channels /= 2;
3569         }
3570
3571         do {
3572                 codec_dbg(codec, "Ready to program DMA\n");
3573                 if (!ovly)
3574                         status = dsp_reset(codec);
3575
3576                 if (status < 0)
3577                         break;
3578
3579                 codec_dbg(codec, "dsp_reset() complete\n");
3580                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3581                                       ovly);
3582
3583                 if (status < 0)
3584                         break;
3585
3586                 codec_dbg(codec, "dspxfr_image() complete\n");
3587                 if (autostart && !ovly) {
3588                         dspload_post_setup(codec);
3589                         status = dsp_set_run_state(codec);
3590                 }
3591
3592                 codec_dbg(codec, "LOAD FINISHED\n");
3593         } while (0);
3594
3595         return status;
3596 }
3597
3598 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3599 static bool dspload_is_loaded(struct hda_codec *codec)
3600 {
3601         unsigned int data = 0;
3602         int status = 0;
3603
3604         status = chipio_read(codec, 0x40004, &data);
3605         if ((status < 0) || (data != 1))
3606                 return false;
3607
3608         return true;
3609 }
3610 #else
3611 #define dspload_is_loaded(codec)        false
3612 #endif
3613
3614 static bool dspload_wait_loaded(struct hda_codec *codec)
3615 {
3616         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3617
3618         do {
3619                 if (dspload_is_loaded(codec)) {
3620                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3621                         return true;
3622                 }
3623                 msleep(20);
3624         } while (time_before(jiffies, timeout));
3625
3626         codec_err(codec, "ca0132 failed to download DSP\n");
3627         return false;
3628 }
3629
3630 /*
3631  * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3632  * based cards, and has a second mmio region, region2, that's used for special
3633  * commands.
3634  */
3635
3636 /*
3637  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3638  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3639  * The first eight bits are just the number of the pin. So far, I've only seen
3640  * this number go to 7.
3641  * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3642  * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3643  * then off to send that bit.
3644  */
3645 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3646                 bool enable)
3647 {
3648         struct ca0132_spec *spec = codec->spec;
3649         unsigned short gpio_data;
3650
3651         gpio_data = gpio_pin & 0xF;
3652         gpio_data |= ((enable << 8) & 0x100);
3653
3654         writew(gpio_data, spec->mem_base + 0x320);
3655 }
3656
3657 /*
3658  * Special pci region2 commands that are only used by the AE-5. They follow
3659  * a set format, and require reads at certain points to seemingly 'clear'
3660  * the response data. My first tests didn't do these reads, and would cause
3661  * the card to get locked up until the memory was read. These commands
3662  * seem to work with three distinct values that I've taken to calling group,
3663  * target-id, and value.
3664  */
3665 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3666                 unsigned int target, unsigned int value)
3667 {
3668         struct ca0132_spec *spec = codec->spec;
3669         unsigned int write_val;
3670
3671         writel(0x0000007e, spec->mem_base + 0x210);
3672         readl(spec->mem_base + 0x210);
3673         writel(0x0000005a, spec->mem_base + 0x210);
3674         readl(spec->mem_base + 0x210);
3675         readl(spec->mem_base + 0x210);
3676
3677         writel(0x00800005, spec->mem_base + 0x20c);
3678         writel(group, spec->mem_base + 0x804);
3679
3680         writel(0x00800005, spec->mem_base + 0x20c);
3681         write_val = (target & 0xff);
3682         write_val |= (value << 8);
3683
3684
3685         writel(write_val, spec->mem_base + 0x204);
3686         /*
3687          * Need delay here or else it goes too fast and works inconsistently.
3688          */
3689         msleep(20);
3690
3691         readl(spec->mem_base + 0x860);
3692         readl(spec->mem_base + 0x854);
3693         readl(spec->mem_base + 0x840);
3694
3695         writel(0x00800004, spec->mem_base + 0x20c);
3696         writel(0x00000000, spec->mem_base + 0x210);
3697         readl(spec->mem_base + 0x210);
3698         readl(spec->mem_base + 0x210);
3699 }
3700
3701 /*
3702  * This second type of command is used for setting the sound filter type.
3703  */
3704 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3705                 unsigned int group, unsigned int target, unsigned int value)
3706 {
3707         struct ca0132_spec *spec = codec->spec;
3708         unsigned int write_val;
3709
3710         writel(0x0000007e, spec->mem_base + 0x210);
3711         readl(spec->mem_base + 0x210);
3712         writel(0x0000005a, spec->mem_base + 0x210);
3713         readl(spec->mem_base + 0x210);
3714         readl(spec->mem_base + 0x210);
3715
3716         writel(0x00800003, spec->mem_base + 0x20c);
3717         writel(group, spec->mem_base + 0x804);
3718
3719         writel(0x00800005, spec->mem_base + 0x20c);
3720         write_val = (target & 0xff);
3721         write_val |= (value << 8);
3722
3723
3724         writel(write_val, spec->mem_base + 0x204);
3725         msleep(20);
3726         readl(spec->mem_base + 0x860);
3727         readl(spec->mem_base + 0x854);
3728         readl(spec->mem_base + 0x840);
3729
3730         writel(0x00800004, spec->mem_base + 0x20c);
3731         writel(0x00000000, spec->mem_base + 0x210);
3732         readl(spec->mem_base + 0x210);
3733         readl(spec->mem_base + 0x210);
3734 }
3735
3736 /*
3737  * Setup GPIO for the other variants of Core3D.
3738  */
3739
3740 /*
3741  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3742  * the card shows as having no GPIO pins.
3743  */
3744 static void ca0132_gpio_init(struct hda_codec *codec)
3745 {
3746         struct ca0132_spec *spec = codec->spec;
3747
3748         switch (ca0132_quirk(spec)) {
3749         case QUIRK_SBZ:
3750         case QUIRK_AE5:
3751         case QUIRK_AE7:
3752                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3753                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3754                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3755                 break;
3756         case QUIRK_R3DI:
3757                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3758                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3759                 break;
3760         default:
3761                 break;
3762         }
3763
3764 }
3765
3766 /* Sets the GPIO for audio output. */
3767 static void ca0132_gpio_setup(struct hda_codec *codec)
3768 {
3769         struct ca0132_spec *spec = codec->spec;
3770
3771         switch (ca0132_quirk(spec)) {
3772         case QUIRK_SBZ:
3773                 snd_hda_codec_write(codec, 0x01, 0,
3774                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3775                 snd_hda_codec_write(codec, 0x01, 0,
3776                                 AC_VERB_SET_GPIO_MASK, 0x07);
3777                 snd_hda_codec_write(codec, 0x01, 0,
3778                                 AC_VERB_SET_GPIO_DATA, 0x04);
3779                 snd_hda_codec_write(codec, 0x01, 0,
3780                                 AC_VERB_SET_GPIO_DATA, 0x06);
3781                 break;
3782         case QUIRK_R3DI:
3783                 snd_hda_codec_write(codec, 0x01, 0,
3784                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3785                 snd_hda_codec_write(codec, 0x01, 0,
3786                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3787                 snd_hda_codec_write(codec, 0x01, 0,
3788                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3789                 break;
3790         default:
3791                 break;
3792         }
3793 }
3794
3795 /*
3796  * GPIO control functions for the Recon3D integrated.
3797  */
3798
3799 enum r3di_gpio_bit {
3800         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3801         R3DI_MIC_SELECT_BIT = 1,
3802         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3803         R3DI_OUT_SELECT_BIT = 2,
3804         /*
3805          * I dunno what this actually does, but it stays on until the dsp
3806          * is downloaded.
3807          */
3808         R3DI_GPIO_DSP_DOWNLOADING = 3,
3809         /*
3810          * Same as above, no clue what it does, but it comes on after the dsp
3811          * is downloaded.
3812          */
3813         R3DI_GPIO_DSP_DOWNLOADED = 4
3814 };
3815
3816 enum r3di_mic_select {
3817         /* Set GPIO bit 1 to 0 for rear mic */
3818         R3DI_REAR_MIC = 0,
3819         /* Set GPIO bit 1 to 1 for front microphone*/
3820         R3DI_FRONT_MIC = 1
3821 };
3822
3823 enum r3di_out_select {
3824         /* Set GPIO bit 2 to 0 for headphone */
3825         R3DI_HEADPHONE_OUT = 0,
3826         /* Set GPIO bit 2 to 1 for speaker */
3827         R3DI_LINE_OUT = 1
3828 };
3829 enum r3di_dsp_status {
3830         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3831         R3DI_DSP_DOWNLOADING = 0,
3832         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3833         R3DI_DSP_DOWNLOADED = 1
3834 };
3835
3836
3837 static void r3di_gpio_mic_set(struct hda_codec *codec,
3838                 enum r3di_mic_select cur_mic)
3839 {
3840         unsigned int cur_gpio;
3841
3842         /* Get the current GPIO Data setup */
3843         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3844
3845         switch (cur_mic) {
3846         case R3DI_REAR_MIC:
3847                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3848                 break;
3849         case R3DI_FRONT_MIC:
3850                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3851                 break;
3852         }
3853         snd_hda_codec_write(codec, codec->core.afg, 0,
3854                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3855 }
3856
3857 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3858                 enum r3di_dsp_status dsp_status)
3859 {
3860         unsigned int cur_gpio;
3861
3862         /* Get the current GPIO Data setup */
3863         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3864
3865         switch (dsp_status) {
3866         case R3DI_DSP_DOWNLOADING:
3867                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3868                 snd_hda_codec_write(codec, codec->core.afg, 0,
3869                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3870                 break;
3871         case R3DI_DSP_DOWNLOADED:
3872                 /* Set DOWNLOADING bit to 0. */
3873                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3874
3875                 snd_hda_codec_write(codec, codec->core.afg, 0,
3876                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3877
3878                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3879                 break;
3880         }
3881
3882         snd_hda_codec_write(codec, codec->core.afg, 0,
3883                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3884 }
3885
3886 /*
3887  * PCM callbacks
3888  */
3889 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3890                         struct hda_codec *codec,
3891                         unsigned int stream_tag,
3892                         unsigned int format,
3893                         struct snd_pcm_substream *substream)
3894 {
3895         struct ca0132_spec *spec = codec->spec;
3896
3897         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3898
3899         return 0;
3900 }
3901
3902 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3903                         struct hda_codec *codec,
3904                         struct snd_pcm_substream *substream)
3905 {
3906         struct ca0132_spec *spec = codec->spec;
3907
3908         if (spec->dsp_state == DSP_DOWNLOADING)
3909                 return 0;
3910
3911         /*If Playback effects are on, allow stream some time to flush
3912          *effects tail*/
3913         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3914                 msleep(50);
3915
3916         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3917
3918         return 0;
3919 }
3920
3921 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3922                         struct hda_codec *codec,
3923                         struct snd_pcm_substream *substream)
3924 {
3925         struct ca0132_spec *spec = codec->spec;
3926         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3927         struct snd_pcm_runtime *runtime = substream->runtime;
3928
3929         if (spec->dsp_state != DSP_DOWNLOADED)
3930                 return 0;
3931
3932         /* Add latency if playback enhancement and either effect is enabled. */
3933         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3934                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3935                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3936                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3937         }
3938
3939         /* Applying Speaker EQ adds latency as well. */
3940         if (spec->cur_out_type == SPEAKER_OUT)
3941                 latency += DSP_SPEAKER_OUT_LATENCY;
3942
3943         return (latency * runtime->rate) / 1000;
3944 }
3945
3946 /*
3947  * Digital out
3948  */
3949 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3950                                         struct hda_codec *codec,
3951                                         struct snd_pcm_substream *substream)
3952 {
3953         struct ca0132_spec *spec = codec->spec;
3954         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3955 }
3956
3957 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3958                         struct hda_codec *codec,
3959                         unsigned int stream_tag,
3960                         unsigned int format,
3961                         struct snd_pcm_substream *substream)
3962 {
3963         struct ca0132_spec *spec = codec->spec;
3964         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3965                                              stream_tag, format, substream);
3966 }
3967
3968 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3969                         struct hda_codec *codec,
3970                         struct snd_pcm_substream *substream)
3971 {
3972         struct ca0132_spec *spec = codec->spec;
3973         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3974 }
3975
3976 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3977                                          struct hda_codec *codec,
3978                                          struct snd_pcm_substream *substream)
3979 {
3980         struct ca0132_spec *spec = codec->spec;
3981         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3982 }
3983
3984 /*
3985  * Analog capture
3986  */
3987 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3988                                         struct hda_codec *codec,
3989                                         unsigned int stream_tag,
3990                                         unsigned int format,
3991                                         struct snd_pcm_substream *substream)
3992 {
3993         snd_hda_codec_setup_stream(codec, hinfo->nid,
3994                                    stream_tag, 0, format);
3995
3996         return 0;
3997 }
3998
3999 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
4000                         struct hda_codec *codec,
4001                         struct snd_pcm_substream *substream)
4002 {
4003         struct ca0132_spec *spec = codec->spec;
4004
4005         if (spec->dsp_state == DSP_DOWNLOADING)
4006                 return 0;
4007
4008         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4009         return 0;
4010 }
4011
4012 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4013                         struct hda_codec *codec,
4014                         struct snd_pcm_substream *substream)
4015 {
4016         struct ca0132_spec *spec = codec->spec;
4017         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4018         struct snd_pcm_runtime *runtime = substream->runtime;
4019
4020         if (spec->dsp_state != DSP_DOWNLOADED)
4021                 return 0;
4022
4023         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4024                 latency += DSP_CRYSTAL_VOICE_LATENCY;
4025
4026         return (latency * runtime->rate) / 1000;
4027 }
4028
4029 /*
4030  * Controls stuffs.
4031  */
4032
4033 /*
4034  * Mixer controls helpers.
4035  */
4036 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4037         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4038           .name = xname, \
4039           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4040           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4041                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4042                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4043           .info = ca0132_volume_info, \
4044           .get = ca0132_volume_get, \
4045           .put = ca0132_volume_put, \
4046           .tlv = { .c = ca0132_volume_tlv }, \
4047           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4048
4049 /*
4050  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4051  * volume put, which is used for setting the DSP volume. This was done because
4052  * the ca0132 functions were taking too much time and causing lag.
4053  */
4054 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4055         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4056           .name = xname, \
4057           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4058           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4059                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4060                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4061           .info = snd_hda_mixer_amp_volume_info, \
4062           .get = snd_hda_mixer_amp_volume_get, \
4063           .put = ca0132_alt_volume_put, \
4064           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4065           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4066
4067 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4068         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4069           .name = xname, \
4070           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4071           .info = snd_hda_mixer_amp_switch_info, \
4072           .get = ca0132_switch_get, \
4073           .put = ca0132_switch_put, \
4074           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4075
4076 /* stereo */
4077 #define CA0132_CODEC_VOL(xname, nid, dir) \
4078         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4079 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4080         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4081 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4082         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4083
4084 /* lookup tables */
4085 /*
4086  * Lookup table with decibel values for the DSP. When volume is changed in
4087  * Windows, the DSP is also sent the dB value in floating point. In Windows,
4088  * these values have decimal points, probably because the Windows driver
4089  * actually uses floating point. We can't here, so I made a lookup table of
4090  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4091  * DAC's, and 9 is the maximum.
4092  */
4093 static const unsigned int float_vol_db_lookup[] = {
4094 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4095 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4096 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4097 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4098 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4099 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4100 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4101 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4102 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4103 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4104 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4105 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4106 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4107 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4108 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4109 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4110 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4111 };
4112
4113 /*
4114  * This table counts from float 0 to 1 in increments of .01, which is
4115  * useful for a few different sliders.
4116  */
4117 static const unsigned int float_zero_to_one_lookup[] = {
4118 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4119 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4120 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4121 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4122 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4123 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4124 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4125 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4126 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4127 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4128 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4129 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4130 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4131 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4132 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4133 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4134 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4135 };
4136
4137 /*
4138  * This table counts from float 10 to 1000, which is the range of the x-bass
4139  * crossover slider in Windows.
4140  */
4141 static const unsigned int float_xbass_xover_lookup[] = {
4142 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4143 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4144 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4145 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4146 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4147 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4148 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4149 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4150 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4151 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4152 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4153 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4154 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4155 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4156 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4157 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4158 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4159 };
4160
4161 /* The following are for tuning of products */
4162 #ifdef ENABLE_TUNING_CONTROLS
4163
4164 static const unsigned int voice_focus_vals_lookup[] = {
4165 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4166 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4167 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4168 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4169 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4170 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4171 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4172 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4173 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4174 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4175 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4176 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4177 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4178 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4179 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4180 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4181 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4182 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4183 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4184 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4185 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4186 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4187 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4188 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4189 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4190 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4191 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4192 };
4193
4194 static const unsigned int mic_svm_vals_lookup[] = {
4195 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4196 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4197 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4198 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4199 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4200 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4201 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4202 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4203 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4204 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4205 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4206 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4207 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4208 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4209 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4210 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4211 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4212 };
4213
4214 static const unsigned int equalizer_vals_lookup[] = {
4215 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4216 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4217 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4218 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4219 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4220 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4221 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4222 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4223 0x41C00000
4224 };
4225
4226 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4227                           const unsigned int *lookup, int idx)
4228 {
4229         int i = 0;
4230
4231         for (i = 0; i < TUNING_CTLS_COUNT; i++)
4232                 if (nid == ca0132_tuning_ctls[i].nid)
4233                         goto found;
4234
4235         return -EINVAL;
4236 found:
4237         snd_hda_power_up(codec);
4238         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4239                         ca0132_tuning_ctls[i].req,
4240                         &(lookup[idx]), sizeof(unsigned int));
4241         snd_hda_power_down(codec);
4242
4243         return 1;
4244 }
4245
4246 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4247                           struct snd_ctl_elem_value *ucontrol)
4248 {
4249         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4250         struct ca0132_spec *spec = codec->spec;
4251         hda_nid_t nid = get_amp_nid(kcontrol);
4252         long *valp = ucontrol->value.integer.value;
4253         int idx = nid - TUNING_CTL_START_NID;
4254
4255         *valp = spec->cur_ctl_vals[idx];
4256         return 0;
4257 }
4258
4259 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4260                               struct snd_ctl_elem_info *uinfo)
4261 {
4262         int chs = get_amp_channels(kcontrol);
4263         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4264         uinfo->count = chs == 3 ? 2 : 1;
4265         uinfo->value.integer.min = 20;
4266         uinfo->value.integer.max = 180;
4267         uinfo->value.integer.step = 1;
4268
4269         return 0;
4270 }
4271
4272 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4273                                 struct snd_ctl_elem_value *ucontrol)
4274 {
4275         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4276         struct ca0132_spec *spec = codec->spec;
4277         hda_nid_t nid = get_amp_nid(kcontrol);
4278         long *valp = ucontrol->value.integer.value;
4279         int idx;
4280
4281         idx = nid - TUNING_CTL_START_NID;
4282         /* any change? */
4283         if (spec->cur_ctl_vals[idx] == *valp)
4284                 return 0;
4285
4286         spec->cur_ctl_vals[idx] = *valp;
4287
4288         idx = *valp - 20;
4289         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4290
4291         return 1;
4292 }
4293
4294 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4295                               struct snd_ctl_elem_info *uinfo)
4296 {
4297         int chs = get_amp_channels(kcontrol);
4298         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4299         uinfo->count = chs == 3 ? 2 : 1;
4300         uinfo->value.integer.min = 0;
4301         uinfo->value.integer.max = 100;
4302         uinfo->value.integer.step = 1;
4303
4304         return 0;
4305 }
4306
4307 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4308                                 struct snd_ctl_elem_value *ucontrol)
4309 {
4310         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4311         struct ca0132_spec *spec = codec->spec;
4312         hda_nid_t nid = get_amp_nid(kcontrol);
4313         long *valp = ucontrol->value.integer.value;
4314         int idx;
4315
4316         idx = nid - TUNING_CTL_START_NID;
4317         /* any change? */
4318         if (spec->cur_ctl_vals[idx] == *valp)
4319                 return 0;
4320
4321         spec->cur_ctl_vals[idx] = *valp;
4322
4323         idx = *valp;
4324         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4325
4326         return 0;
4327 }
4328
4329 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4330                               struct snd_ctl_elem_info *uinfo)
4331 {
4332         int chs = get_amp_channels(kcontrol);
4333         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4334         uinfo->count = chs == 3 ? 2 : 1;
4335         uinfo->value.integer.min = 0;
4336         uinfo->value.integer.max = 48;
4337         uinfo->value.integer.step = 1;
4338
4339         return 0;
4340 }
4341
4342 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4343                                 struct snd_ctl_elem_value *ucontrol)
4344 {
4345         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4346         struct ca0132_spec *spec = codec->spec;
4347         hda_nid_t nid = get_amp_nid(kcontrol);
4348         long *valp = ucontrol->value.integer.value;
4349         int idx;
4350
4351         idx = nid - TUNING_CTL_START_NID;
4352         /* any change? */
4353         if (spec->cur_ctl_vals[idx] == *valp)
4354                 return 0;
4355
4356         spec->cur_ctl_vals[idx] = *valp;
4357
4358         idx = *valp;
4359         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4360
4361         return 1;
4362 }
4363
4364 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4365 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4366
4367 static int add_tuning_control(struct hda_codec *codec,
4368                                 hda_nid_t pnid, hda_nid_t nid,
4369                                 const char *name, int dir)
4370 {
4371         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4372         int type = dir ? HDA_INPUT : HDA_OUTPUT;
4373         struct snd_kcontrol_new knew =
4374                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4375
4376         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4377                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4378         knew.tlv.c = 0;
4379         knew.tlv.p = 0;
4380         switch (pnid) {
4381         case VOICE_FOCUS:
4382                 knew.info = voice_focus_ctl_info;
4383                 knew.get = tuning_ctl_get;
4384                 knew.put = voice_focus_ctl_put;
4385                 knew.tlv.p = voice_focus_db_scale;
4386                 break;
4387         case MIC_SVM:
4388                 knew.info = mic_svm_ctl_info;
4389                 knew.get = tuning_ctl_get;
4390                 knew.put = mic_svm_ctl_put;
4391                 break;
4392         case EQUALIZER:
4393                 knew.info = equalizer_ctl_info;
4394                 knew.get = tuning_ctl_get;
4395                 knew.put = equalizer_ctl_put;
4396                 knew.tlv.p = eq_db_scale;
4397                 break;
4398         default:
4399                 return 0;
4400         }
4401         knew.private_value =
4402                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4403         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4404         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4405 }
4406
4407 static int add_tuning_ctls(struct hda_codec *codec)
4408 {
4409         int i;
4410         int err;
4411
4412         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4413                 err = add_tuning_control(codec,
4414                                         ca0132_tuning_ctls[i].parent_nid,
4415                                         ca0132_tuning_ctls[i].nid,
4416                                         ca0132_tuning_ctls[i].name,
4417                                         ca0132_tuning_ctls[i].direct);
4418                 if (err < 0)
4419                         return err;
4420         }
4421
4422         return 0;
4423 }
4424
4425 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4426 {
4427         struct ca0132_spec *spec = codec->spec;
4428         int i;
4429
4430         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4431         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4432         /* SVM level defaults to 0.74. */
4433         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4434
4435         /* EQ defaults to 0dB. */
4436         for (i = 2; i < TUNING_CTLS_COUNT; i++)
4437                 spec->cur_ctl_vals[i] = 24;
4438 }
4439 #endif /*ENABLE_TUNING_CONTROLS*/
4440
4441 /*
4442  * Select the active output.
4443  * If autodetect is enabled, output will be selected based on jack detection.
4444  * If jack inserted, headphone will be selected, else built-in speakers
4445  * If autodetect is disabled, output will be selected based on selection.
4446  */
4447 static int ca0132_select_out(struct hda_codec *codec)
4448 {
4449         struct ca0132_spec *spec = codec->spec;
4450         unsigned int pin_ctl;
4451         int jack_present;
4452         int auto_jack;
4453         unsigned int tmp;
4454         int err;
4455
4456         codec_dbg(codec, "ca0132_select_out\n");
4457
4458         snd_hda_power_up_pm(codec);
4459
4460         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4461
4462         if (auto_jack)
4463                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4464         else
4465                 jack_present =
4466                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4467
4468         if (jack_present)
4469                 spec->cur_out_type = HEADPHONE_OUT;
4470         else
4471                 spec->cur_out_type = SPEAKER_OUT;
4472
4473         if (spec->cur_out_type == SPEAKER_OUT) {
4474                 codec_dbg(codec, "ca0132_select_out speaker\n");
4475                 /*speaker out config*/
4476                 tmp = FLOAT_ONE;
4477                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4478                 if (err < 0)
4479                         goto exit;
4480                 /*enable speaker EQ*/
4481                 tmp = FLOAT_ONE;
4482                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4483                 if (err < 0)
4484                         goto exit;
4485
4486                 /* Setup EAPD */
4487                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4488                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4489                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4490                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4491                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4492                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4493                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4494                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4495
4496                 /* disable headphone node */
4497                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4498                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4499                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4500                                     pin_ctl & ~PIN_HP);
4501                 /* enable speaker node */
4502                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4503                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4504                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4505                                     pin_ctl | PIN_OUT);
4506         } else {
4507                 codec_dbg(codec, "ca0132_select_out hp\n");
4508                 /*headphone out config*/
4509                 tmp = FLOAT_ZERO;
4510                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4511                 if (err < 0)
4512                         goto exit;
4513                 /*disable speaker EQ*/
4514                 tmp = FLOAT_ZERO;
4515                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4516                 if (err < 0)
4517                         goto exit;
4518
4519                 /* Setup EAPD */
4520                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4521                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4522                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4523                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4524                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4525                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4526                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4527                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4528
4529                 /* disable speaker*/
4530                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4531                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4532                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4533                                     pin_ctl & ~PIN_HP);
4534                 /* enable headphone*/
4535                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4536                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4537                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4538                                     pin_ctl | PIN_HP);
4539         }
4540
4541 exit:
4542         snd_hda_power_down_pm(codec);
4543
4544         return err < 0 ? err : 0;
4545 }
4546
4547 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4548 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4549 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4550
4551 static void ae5_mmio_select_out(struct hda_codec *codec)
4552 {
4553         struct ca0132_spec *spec = codec->spec;
4554         const struct ae_ca0113_output_set *out_cmds;
4555         unsigned int i;
4556
4557         if (ca0132_quirk(spec) == QUIRK_AE5)
4558                 out_cmds = &ae5_ca0113_output_presets;
4559         else
4560                 out_cmds = &ae7_ca0113_output_presets;
4561
4562         for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4563                 ca0113_mmio_command_set(codec, out_cmds->group[i],
4564                                 out_cmds->target[i],
4565                                 out_cmds->vals[spec->cur_out_type][i]);
4566 }
4567
4568 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4569 {
4570         struct ca0132_spec *spec = codec->spec;
4571         int quirk = ca0132_quirk(spec);
4572         unsigned int tmp;
4573         int err;
4574
4575         /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4576         if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4577                         || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4578                 return 0;
4579
4580         /* Set front L/R full range. Zero for full-range, one for redirection. */
4581         tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4582         err = dspio_set_uint_param(codec, 0x96,
4583                         SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4584         if (err < 0)
4585                 return err;
4586
4587         /* When setting full-range rear, both rear and center/lfe are set. */
4588         tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4589         err = dspio_set_uint_param(codec, 0x96,
4590                         SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4591         if (err < 0)
4592                 return err;
4593
4594         err = dspio_set_uint_param(codec, 0x96,
4595                         SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4596         if (err < 0)
4597                 return err;
4598
4599         /*
4600          * Only the AE series cards set this value when setting full-range,
4601          * and it's always 1.0f.
4602          */
4603         if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4604                 err = dspio_set_uint_param(codec, 0x96,
4605                                 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4606                 if (err < 0)
4607                         return err;
4608         }
4609
4610         return 0;
4611 }
4612
4613 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4614                 bool val)
4615 {
4616         struct ca0132_spec *spec = codec->spec;
4617         unsigned int tmp;
4618         int err;
4619
4620         if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4621                         spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4622                 tmp = FLOAT_ONE;
4623         else
4624                 tmp = FLOAT_ZERO;
4625
4626         err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4627         if (err < 0)
4628                 return err;
4629
4630         /* If it is enabled, make sure to set the crossover frequency. */
4631         if (tmp) {
4632                 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4633                 err = dspio_set_uint_param(codec, 0x96,
4634                                 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4635                 if (err < 0)
4636                         return err;
4637         }
4638
4639         return 0;
4640 }
4641
4642 /*
4643  * These are the commands needed to setup output on each of the different card
4644  * types.
4645  */
4646 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4647                 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4648 {
4649         struct ca0132_spec *spec = codec->spec;
4650         int quirk = ca0132_quirk(spec);
4651         unsigned int i;
4652
4653         *quirk_data = NULL;
4654         for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4655                 if (quirk_out_set_data[i].quirk_id == quirk) {
4656                         *quirk_data = &quirk_out_set_data[i];
4657                         return;
4658                 }
4659         }
4660 }
4661
4662 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4663 {
4664         const struct ca0132_alt_out_set_quirk_data *quirk_data;
4665         const struct ca0132_alt_out_set_info *out_info;
4666         struct ca0132_spec *spec = codec->spec;
4667         unsigned int i, gpio_data;
4668         int err;
4669
4670         ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4671         if (!quirk_data)
4672                 return 0;
4673
4674         out_info = &quirk_data->out_set_info[spec->cur_out_type];
4675         if (quirk_data->is_ae_series)
4676                 ae5_mmio_select_out(codec);
4677
4678         if (out_info->has_hda_gpio) {
4679                 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4680                                 AC_VERB_GET_GPIO_DATA, 0);
4681
4682                 if (out_info->hda_gpio_set)
4683                         gpio_data |= (1 << out_info->hda_gpio_pin);
4684                 else
4685                         gpio_data &= ~(1 << out_info->hda_gpio_pin);
4686
4687                 snd_hda_codec_write(codec, codec->core.afg, 0,
4688                                     AC_VERB_SET_GPIO_DATA, gpio_data);
4689         }
4690
4691         if (out_info->mmio_gpio_count) {
4692                 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4693                         ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4694                                         out_info->mmio_gpio_set[i]);
4695                 }
4696         }
4697
4698         if (out_info->scp_cmds_count) {
4699                 for (i = 0; i < out_info->scp_cmds_count; i++) {
4700                         err = dspio_set_uint_param(codec,
4701                                         out_info->scp_cmd_mid[i],
4702                                         out_info->scp_cmd_req[i],
4703                                         out_info->scp_cmd_val[i]);
4704                         if (err < 0)
4705                                 return err;
4706                 }
4707         }
4708
4709         chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4710
4711         if (out_info->has_chipio_write) {
4712                 chipio_write(codec, out_info->chipio_write_addr,
4713                                 out_info->chipio_write_data);
4714         }
4715
4716         if (quirk_data->has_headphone_gain) {
4717                 if (spec->cur_out_type != HEADPHONE_OUT) {
4718                         if (quirk_data->is_ae_series)
4719                                 ae5_headphone_gain_set(codec, 2);
4720                         else
4721                                 zxr_headphone_gain_set(codec, 0);
4722                 } else {
4723                         if (quirk_data->is_ae_series)
4724                                 ae5_headphone_gain_set(codec,
4725                                                 spec->ae5_headphone_gain_val);
4726                         else
4727                                 zxr_headphone_gain_set(codec,
4728                                                 spec->zxr_gain_set);
4729                 }
4730         }
4731
4732         return 0;
4733 }
4734
4735 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4736                 bool out_enable, bool hp_enable)
4737 {
4738         unsigned int pin_ctl;
4739
4740         pin_ctl = snd_hda_codec_read(codec, nid, 0,
4741                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4742
4743         pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4744         pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4745         snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4746 }
4747
4748 /*
4749  * This function behaves similarly to the ca0132_select_out funciton above,
4750  * except with a few differences. It adds the ability to select the current
4751  * output with an enumerated control "output source" if the auto detect
4752  * mute switch is set to off. If the auto detect mute switch is enabled, it
4753  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4754  * It also adds the ability to auto-detect the front headphone port.
4755  */
4756 static int ca0132_alt_select_out(struct hda_codec *codec)
4757 {
4758         struct ca0132_spec *spec = codec->spec;
4759         unsigned int tmp, outfx_set;
4760         int jack_present;
4761         int auto_jack;
4762         int err;
4763         /* Default Headphone is rear headphone */
4764         hda_nid_t headphone_nid = spec->out_pins[1];
4765
4766         codec_dbg(codec, "%s\n", __func__);
4767
4768         snd_hda_power_up_pm(codec);
4769
4770         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4771
4772         /*
4773          * If headphone rear or front is plugged in, set to headphone.
4774          * If neither is plugged in, set to rear line out. Only if
4775          * hp/speaker auto detect is enabled.
4776          */
4777         if (auto_jack) {
4778                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4779                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4780
4781                 if (jack_present)
4782                         spec->cur_out_type = HEADPHONE_OUT;
4783                 else
4784                         spec->cur_out_type = SPEAKER_OUT;
4785         } else
4786                 spec->cur_out_type = spec->out_enum_val;
4787
4788         outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4789
4790         /* Begin DSP output switch, mute DSP volume. */
4791         err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4792         if (err < 0)
4793                 goto exit;
4794
4795         if (ca0132_alt_select_out_quirk_set(codec) < 0)
4796                 goto exit;
4797
4798         switch (spec->cur_out_type) {
4799         case SPEAKER_OUT:
4800                 codec_dbg(codec, "%s speaker\n", __func__);
4801
4802                 /* Enable EAPD */
4803                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4804                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4805
4806                 /* Disable headphone node. */
4807                 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4808                 /* Set front L-R to output. */
4809                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4810                 /* Set Center/LFE to output. */
4811                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4812                 /* Set rear surround to output. */
4813                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4814
4815                 /*
4816                  * Without PlayEnhancement being enabled, if we've got a 2.0
4817                  * setup, set it to floating point eight to disable any DSP
4818                  * processing effects.
4819                  */
4820                 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4821                         tmp = FLOAT_EIGHT;
4822                 else
4823                         tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4824
4825                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4826                 if (err < 0)
4827                         goto exit;
4828
4829                 break;
4830         case HEADPHONE_OUT:
4831                 codec_dbg(codec, "%s hp\n", __func__);
4832                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4833                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4834
4835                 /* Disable all speaker nodes. */
4836                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4837                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4838                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4839
4840                 /* enable headphone, either front or rear */
4841                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4842                         headphone_nid = spec->out_pins[2];
4843                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4844                         headphone_nid = spec->out_pins[1];
4845
4846                 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4847
4848                 if (outfx_set)
4849                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4850                 else
4851                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4852
4853                 if (err < 0)
4854                         goto exit;
4855                 break;
4856         }
4857         /*
4858          * If output effects are enabled, set the X-Bass effect value again to
4859          * make sure that it's properly enabled/disabled for speaker
4860          * configurations with an LFE channel.
4861          */
4862         if (outfx_set)
4863                 ca0132_effects_set(codec, X_BASS,
4864                         spec->effects_switch[X_BASS - EFFECT_START_NID]);
4865
4866         /* Set speaker EQ bypass attenuation to 0. */
4867         err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4868         if (err < 0)
4869                 goto exit;
4870
4871         /*
4872          * Although unused on all cards but the AE series, this is always set
4873          * to zero when setting the output.
4874          */
4875         err = dspio_set_uint_param(codec, 0x96,
4876                         SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4877         if (err < 0)
4878                 goto exit;
4879
4880         if (spec->cur_out_type == SPEAKER_OUT)
4881                 err = ca0132_alt_surround_set_bass_redirection(codec,
4882                                 spec->bass_redirection_val);
4883         else
4884                 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4885
4886         /* Unmute DSP now that we're done with output selection. */
4887         err = dspio_set_uint_param(codec, 0x96,
4888                         SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4889         if (err < 0)
4890                 goto exit;
4891
4892         if (spec->cur_out_type == SPEAKER_OUT) {
4893                 err = ca0132_alt_set_full_range_speaker(codec);
4894                 if (err < 0)
4895                         goto exit;
4896         }
4897
4898 exit:
4899         snd_hda_power_down_pm(codec);
4900
4901         return err < 0 ? err : 0;
4902 }
4903
4904 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4905 {
4906         struct ca0132_spec *spec = container_of(
4907                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4908         struct hda_jack_tbl *jack;
4909
4910         if (ca0132_use_alt_functions(spec))
4911                 ca0132_alt_select_out(spec->codec);
4912         else
4913                 ca0132_select_out(spec->codec);
4914
4915         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4916         if (jack) {
4917                 jack->block_report = 0;
4918                 snd_hda_jack_report_sync(spec->codec);
4919         }
4920 }
4921
4922 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4923 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4924 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4925 static int stop_mic1(struct hda_codec *codec);
4926 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4927 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4928
4929 /*
4930  * Select the active VIP source
4931  */
4932 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4933 {
4934         struct ca0132_spec *spec = codec->spec;
4935         unsigned int tmp;
4936
4937         if (spec->dsp_state != DSP_DOWNLOADED)
4938                 return 0;
4939
4940         /* if CrystalVoice if off, vipsource should be 0 */
4941         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4942             (val == 0)) {
4943                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4944                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4945                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4946                 if (spec->cur_mic_type == DIGITAL_MIC)
4947                         tmp = FLOAT_TWO;
4948                 else
4949                         tmp = FLOAT_ONE;
4950                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4951                 tmp = FLOAT_ZERO;
4952                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4953         } else {
4954                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4955                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4956                 if (spec->cur_mic_type == DIGITAL_MIC)
4957                         tmp = FLOAT_TWO;
4958                 else
4959                         tmp = FLOAT_ONE;
4960                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4961                 tmp = FLOAT_ONE;
4962                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4963                 msleep(20);
4964                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4965         }
4966
4967         return 1;
4968 }
4969
4970 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4971 {
4972         struct ca0132_spec *spec = codec->spec;
4973         unsigned int tmp;
4974
4975         if (spec->dsp_state != DSP_DOWNLOADED)
4976                 return 0;
4977
4978         codec_dbg(codec, "%s\n", __func__);
4979
4980         chipio_set_stream_control(codec, 0x03, 0);
4981         chipio_set_stream_control(codec, 0x04, 0);
4982
4983         /* if CrystalVoice is off, vipsource should be 0 */
4984         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4985             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4986                 codec_dbg(codec, "%s: off.", __func__);
4987                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4988
4989                 tmp = FLOAT_ZERO;
4990                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4991
4992                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4993                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4994                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4995                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4996
4997
4998                 if (spec->in_enum_val == REAR_LINE_IN)
4999                         tmp = FLOAT_ZERO;
5000                 else {
5001                         if (ca0132_quirk(spec) == QUIRK_SBZ)
5002                                 tmp = FLOAT_THREE;
5003                         else
5004                                 tmp = FLOAT_ONE;
5005                 }
5006
5007                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5008
5009         } else {
5010                 codec_dbg(codec, "%s: on.", __func__);
5011                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5012                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5013                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5014                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5015
5016                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5017                         tmp = FLOAT_TWO;
5018                 else
5019                         tmp = FLOAT_ONE;
5020                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5021
5022                 tmp = FLOAT_ONE;
5023                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5024
5025                 msleep(20);
5026                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5027         }
5028
5029         chipio_set_stream_control(codec, 0x03, 1);
5030         chipio_set_stream_control(codec, 0x04, 1);
5031
5032         return 1;
5033 }
5034
5035 /*
5036  * Select the active microphone.
5037  * If autodetect is enabled, mic will be selected based on jack detection.
5038  * If jack inserted, ext.mic will be selected, else built-in mic
5039  * If autodetect is disabled, mic will be selected based on selection.
5040  */
5041 static int ca0132_select_mic(struct hda_codec *codec)
5042 {
5043         struct ca0132_spec *spec = codec->spec;
5044         int jack_present;
5045         int auto_jack;
5046
5047         codec_dbg(codec, "ca0132_select_mic\n");
5048
5049         snd_hda_power_up_pm(codec);
5050
5051         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5052
5053         if (auto_jack)
5054                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5055         else
5056                 jack_present =
5057                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5058
5059         if (jack_present)
5060                 spec->cur_mic_type = LINE_MIC_IN;
5061         else
5062                 spec->cur_mic_type = DIGITAL_MIC;
5063
5064         if (spec->cur_mic_type == DIGITAL_MIC) {
5065                 /* enable digital Mic */
5066                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5067                 ca0132_set_dmic(codec, 1);
5068                 ca0132_mic_boost_set(codec, 0);
5069                 /* set voice focus */
5070                 ca0132_effects_set(codec, VOICE_FOCUS,
5071                                    spec->effects_switch
5072                                    [VOICE_FOCUS - EFFECT_START_NID]);
5073         } else {
5074                 /* disable digital Mic */
5075                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5076                 ca0132_set_dmic(codec, 0);
5077                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5078                 /* disable voice focus */
5079                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5080         }
5081
5082         snd_hda_power_down_pm(codec);
5083
5084         return 0;
5085 }
5086
5087 /*
5088  * Select the active input.
5089  * Mic detection isn't used, because it's kind of pointless on the SBZ.
5090  * The front mic has no jack-detection, so the only way to switch to it
5091  * is to do it manually in alsamixer.
5092  */
5093 static int ca0132_alt_select_in(struct hda_codec *codec)
5094 {
5095         struct ca0132_spec *spec = codec->spec;
5096         unsigned int tmp;
5097
5098         codec_dbg(codec, "%s\n", __func__);
5099
5100         snd_hda_power_up_pm(codec);
5101
5102         chipio_set_stream_control(codec, 0x03, 0);
5103         chipio_set_stream_control(codec, 0x04, 0);
5104
5105         spec->cur_mic_type = spec->in_enum_val;
5106
5107         switch (spec->cur_mic_type) {
5108         case REAR_MIC:
5109                 switch (ca0132_quirk(spec)) {
5110                 case QUIRK_SBZ:
5111                 case QUIRK_R3D:
5112                         ca0113_mmio_gpio_set(codec, 0, false);
5113                         tmp = FLOAT_THREE;
5114                         break;
5115                 case QUIRK_ZXR:
5116                         tmp = FLOAT_THREE;
5117                         break;
5118                 case QUIRK_R3DI:
5119                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5120                         tmp = FLOAT_ONE;
5121                         break;
5122                 case QUIRK_AE5:
5123                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5124                         tmp = FLOAT_THREE;
5125                         break;
5126                 case QUIRK_AE7:
5127                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5128                         tmp = FLOAT_THREE;
5129                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5130                                         SR_96_000);
5131                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5132                                         SR_96_000);
5133                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5134                         break;
5135                 default:
5136                         tmp = FLOAT_ONE;
5137                         break;
5138                 }
5139
5140                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5141                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5142                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5143                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5144
5145                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5146
5147                 chipio_set_stream_control(codec, 0x03, 1);
5148                 chipio_set_stream_control(codec, 0x04, 1);
5149                 switch (ca0132_quirk(spec)) {
5150                 case QUIRK_SBZ:
5151                         chipio_write(codec, 0x18B098, 0x0000000C);
5152                         chipio_write(codec, 0x18B09C, 0x0000000C);
5153                         break;
5154                 case QUIRK_ZXR:
5155                         chipio_write(codec, 0x18B098, 0x0000000C);
5156                         chipio_write(codec, 0x18B09C, 0x000000CC);
5157                         break;
5158                 case QUIRK_AE5:
5159                         chipio_write(codec, 0x18B098, 0x0000000C);
5160                         chipio_write(codec, 0x18B09C, 0x0000004C);
5161                         break;
5162                 default:
5163                         break;
5164                 }
5165                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5166                 break;
5167         case REAR_LINE_IN:
5168                 ca0132_mic_boost_set(codec, 0);
5169                 switch (ca0132_quirk(spec)) {
5170                 case QUIRK_SBZ:
5171                 case QUIRK_R3D:
5172                         ca0113_mmio_gpio_set(codec, 0, false);
5173                         break;
5174                 case QUIRK_R3DI:
5175                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5176                         break;
5177                 case QUIRK_AE5:
5178                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5179                         break;
5180                 case QUIRK_AE7:
5181                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5182                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5183                                         SR_96_000);
5184                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5185                                         SR_96_000);
5186                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5187                         break;
5188                 default:
5189                         break;
5190                 }
5191
5192                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5193                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5194                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5195                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5196
5197                 if (ca0132_quirk(spec) == QUIRK_AE7)
5198                         tmp = FLOAT_THREE;
5199                 else
5200                         tmp = FLOAT_ZERO;
5201                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5202
5203                 switch (ca0132_quirk(spec)) {
5204                 case QUIRK_SBZ:
5205                 case QUIRK_AE5:
5206                         chipio_write(codec, 0x18B098, 0x00000000);
5207                         chipio_write(codec, 0x18B09C, 0x00000000);
5208                         break;
5209                 default:
5210                         break;
5211                 }
5212                 chipio_set_stream_control(codec, 0x03, 1);
5213                 chipio_set_stream_control(codec, 0x04, 1);
5214                 break;
5215         case FRONT_MIC:
5216                 switch (ca0132_quirk(spec)) {
5217                 case QUIRK_SBZ:
5218                 case QUIRK_R3D:
5219                         ca0113_mmio_gpio_set(codec, 0, true);
5220                         ca0113_mmio_gpio_set(codec, 5, false);
5221                         tmp = FLOAT_THREE;
5222                         break;
5223                 case QUIRK_R3DI:
5224                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5225                         tmp = FLOAT_ONE;
5226                         break;
5227                 case QUIRK_AE5:
5228                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5229                         tmp = FLOAT_THREE;
5230                         break;
5231                 default:
5232                         tmp = FLOAT_ONE;
5233                         break;
5234                 }
5235
5236                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5237                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5238                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5239                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5240
5241                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5242
5243                 chipio_set_stream_control(codec, 0x03, 1);
5244                 chipio_set_stream_control(codec, 0x04, 1);
5245
5246                 switch (ca0132_quirk(spec)) {
5247                 case QUIRK_SBZ:
5248                         chipio_write(codec, 0x18B098, 0x0000000C);
5249                         chipio_write(codec, 0x18B09C, 0x000000CC);
5250                         break;
5251                 case QUIRK_AE5:
5252                         chipio_write(codec, 0x18B098, 0x0000000C);
5253                         chipio_write(codec, 0x18B09C, 0x0000004C);
5254                         break;
5255                 default:
5256                         break;
5257                 }
5258                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5259                 break;
5260         }
5261         ca0132_cvoice_switch_set(codec);
5262
5263         snd_hda_power_down_pm(codec);
5264         return 0;
5265 }
5266
5267 /*
5268  * Check if VNODE settings take effect immediately.
5269  */
5270 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5271                                      hda_nid_t vnid,
5272                                      hda_nid_t *shared_nid)
5273 {
5274         struct ca0132_spec *spec = codec->spec;
5275         hda_nid_t nid;
5276
5277         switch (vnid) {
5278         case VNID_SPK:
5279                 nid = spec->shared_out_nid;
5280                 break;
5281         case VNID_MIC:
5282                 nid = spec->shared_mic_nid;
5283                 break;
5284         default:
5285                 return false;
5286         }
5287
5288         if (shared_nid)
5289                 *shared_nid = nid;
5290
5291         return true;
5292 }
5293
5294 /*
5295 * The following functions are control change helpers.
5296 * They return 0 if no changed.  Return 1 if changed.
5297 */
5298 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5299 {
5300         struct ca0132_spec *spec = codec->spec;
5301         unsigned int tmp;
5302
5303         /* based on CrystalVoice state to enable VoiceFX. */
5304         if (enable) {
5305                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5306                         FLOAT_ONE : FLOAT_ZERO;
5307         } else {
5308                 tmp = FLOAT_ZERO;
5309         }
5310
5311         dspio_set_uint_param(codec, ca0132_voicefx.mid,
5312                              ca0132_voicefx.reqs[0], tmp);
5313
5314         return 1;
5315 }
5316
5317 /*
5318  * Set the effects parameters
5319  */
5320 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5321 {
5322         struct ca0132_spec *spec = codec->spec;
5323         unsigned int on, tmp, channel_cfg;
5324         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5325         int err = 0;
5326         int idx = nid - EFFECT_START_NID;
5327
5328         if ((idx < 0) || (idx >= num_fx))
5329                 return 0; /* no changed */
5330
5331         /* for out effect, qualify with PE */
5332         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5333                 /* if PE if off, turn off out effects. */
5334                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5335                         val = 0;
5336                 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5337                         channel_cfg = spec->channel_cfg_val;
5338                         if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5339                                         channel_cfg != SPEAKER_CHANNELS_4_0)
5340                                 val = 0;
5341                 }
5342         }
5343
5344         /* for in effect, qualify with CrystalVoice */
5345         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5346                 /* if CrystalVoice if off, turn off in effects. */
5347                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5348                         val = 0;
5349
5350                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5351                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5352                         val = 0;
5353
5354                 /* If Voice Focus on SBZ, set to two channel. */
5355                 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5356                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5357                         if (spec->effects_switch[CRYSTAL_VOICE -
5358                                                  EFFECT_START_NID]) {
5359
5360                                 if (spec->effects_switch[VOICE_FOCUS -
5361                                                          EFFECT_START_NID]) {
5362                                         tmp = FLOAT_TWO;
5363                                         val = 1;
5364                                 } else
5365                                         tmp = FLOAT_ONE;
5366
5367                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5368                         }
5369                 }
5370                 /*
5371                  * For SBZ noise reduction, there's an extra command
5372                  * to module ID 0x47. No clue why.
5373                  */
5374                 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5375                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5376                         if (spec->effects_switch[CRYSTAL_VOICE -
5377                                                  EFFECT_START_NID]) {
5378                                 if (spec->effects_switch[NOISE_REDUCTION -
5379                                                          EFFECT_START_NID])
5380                                         tmp = FLOAT_ONE;
5381                                 else
5382                                         tmp = FLOAT_ZERO;
5383                         } else
5384                                 tmp = FLOAT_ZERO;
5385
5386                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5387                 }
5388
5389                 /* If rear line in disable effects. */
5390                 if (ca0132_use_alt_functions(spec) &&
5391                                 spec->in_enum_val == REAR_LINE_IN)
5392                         val = 0;
5393         }
5394
5395         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5396                     nid, val);
5397
5398         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5399         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5400                                    ca0132_effects[idx].reqs[0], on);
5401
5402         if (err < 0)
5403                 return 0; /* no changed */
5404
5405         return 1;
5406 }
5407
5408 /*
5409  * Turn on/off Playback Enhancements
5410  */
5411 static int ca0132_pe_switch_set(struct hda_codec *codec)
5412 {
5413         struct ca0132_spec *spec = codec->spec;
5414         hda_nid_t nid;
5415         int i, ret = 0;
5416
5417         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5418                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5419
5420         if (ca0132_use_alt_functions(spec))
5421                 ca0132_alt_select_out(codec);
5422
5423         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5424         nid = OUT_EFFECT_START_NID;
5425         /* PE affects all out effects */
5426         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5427                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5428
5429         return ret;
5430 }
5431
5432 /* Check if Mic1 is streaming, if so, stop streaming */
5433 static int stop_mic1(struct hda_codec *codec)
5434 {
5435         struct ca0132_spec *spec = codec->spec;
5436         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5437                                                  AC_VERB_GET_CONV, 0);
5438         if (oldval != 0)
5439                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5440                                     AC_VERB_SET_CHANNEL_STREAMID,
5441                                     0);
5442         return oldval;
5443 }
5444
5445 /* Resume Mic1 streaming if it was stopped. */
5446 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5447 {
5448         struct ca0132_spec *spec = codec->spec;
5449         /* Restore the previous stream and channel */
5450         if (oldval != 0)
5451                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5452                                     AC_VERB_SET_CHANNEL_STREAMID,
5453                                     oldval);
5454 }
5455
5456 /*
5457  * Turn on/off CrystalVoice
5458  */
5459 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5460 {
5461         struct ca0132_spec *spec = codec->spec;
5462         hda_nid_t nid;
5463         int i, ret = 0;
5464         unsigned int oldval;
5465
5466         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5467                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5468
5469         i = IN_EFFECT_START_NID - EFFECT_START_NID;
5470         nid = IN_EFFECT_START_NID;
5471         /* CrystalVoice affects all in effects */
5472         for (; nid < IN_EFFECT_END_NID; nid++, i++)
5473                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5474
5475         /* including VoiceFX */
5476         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5477
5478         /* set correct vipsource */
5479         oldval = stop_mic1(codec);
5480         if (ca0132_use_alt_functions(spec))
5481                 ret |= ca0132_alt_set_vipsource(codec, 1);
5482         else
5483                 ret |= ca0132_set_vipsource(codec, 1);
5484         resume_mic1(codec, oldval);
5485         return ret;
5486 }
5487
5488 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5489 {
5490         struct ca0132_spec *spec = codec->spec;
5491         int ret = 0;
5492
5493         if (val) /* on */
5494                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5495                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5496         else /* off */
5497                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5498                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5499
5500         return ret;
5501 }
5502
5503 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5504 {
5505         struct ca0132_spec *spec = codec->spec;
5506         int ret = 0;
5507
5508         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5509                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5510         return ret;
5511 }
5512
5513 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5514 {
5515         unsigned int i;
5516
5517         for (i = 0; i < 4; i++)
5518                 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5519                                 ae5_headphone_gain_presets[val].vals[i]);
5520         return 0;
5521 }
5522
5523 /*
5524  * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5525  * amplifier to handle a 600 ohm load.
5526  */
5527 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5528 {
5529         ca0113_mmio_gpio_set(codec, 1, val);
5530
5531         return 0;
5532 }
5533
5534 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5535                                 struct snd_ctl_elem_value *ucontrol)
5536 {
5537         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5538         hda_nid_t nid = get_amp_nid(kcontrol);
5539         hda_nid_t shared_nid = 0;
5540         bool effective;
5541         int ret = 0;
5542         struct ca0132_spec *spec = codec->spec;
5543         int auto_jack;
5544
5545         if (nid == VNID_HP_SEL) {
5546                 auto_jack =
5547                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5548                 if (!auto_jack) {
5549                         if (ca0132_use_alt_functions(spec))
5550                                 ca0132_alt_select_out(codec);
5551                         else
5552                                 ca0132_select_out(codec);
5553                 }
5554                 return 1;
5555         }
5556
5557         if (nid == VNID_AMIC1_SEL) {
5558                 auto_jack =
5559                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5560                 if (!auto_jack)
5561                         ca0132_select_mic(codec);
5562                 return 1;
5563         }
5564
5565         if (nid == VNID_HP_ASEL) {
5566                 if (ca0132_use_alt_functions(spec))
5567                         ca0132_alt_select_out(codec);
5568                 else
5569                         ca0132_select_out(codec);
5570                 return 1;
5571         }
5572
5573         if (nid == VNID_AMIC1_ASEL) {
5574                 ca0132_select_mic(codec);
5575                 return 1;
5576         }
5577
5578         /* if effective conditions, then update hw immediately. */
5579         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5580         if (effective) {
5581                 int dir = get_amp_direction(kcontrol);
5582                 int ch = get_amp_channels(kcontrol);
5583                 unsigned long pval;
5584
5585                 mutex_lock(&codec->control_mutex);
5586                 pval = kcontrol->private_value;
5587                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5588                                                                 0, dir);
5589                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5590                 kcontrol->private_value = pval;
5591                 mutex_unlock(&codec->control_mutex);
5592         }
5593
5594         return ret;
5595 }
5596 /* End of control change helpers. */
5597
5598 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5599                 long idx)
5600 {
5601         snd_hda_power_up(codec);
5602
5603         dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5604                         &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5605
5606         snd_hda_power_down(codec);
5607 }
5608
5609 /*
5610  * Below I've added controls to mess with the effect levels, I've only enabled
5611  * them on the Sound Blaster Z, but they would probably also work on the
5612  * Chromebook. I figured they were probably tuned specifically for it, and left
5613  * out for a reason.
5614  */
5615
5616 /* Sets DSP effect level from the sliders above the controls */
5617
5618 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5619                           const unsigned int *lookup, int idx)
5620 {
5621         int i = 0;
5622         unsigned int y;
5623         /*
5624          * For X_BASS, req 2 is actually crossover freq instead of
5625          * effect level
5626          */
5627         if (nid == X_BASS)
5628                 y = 2;
5629         else
5630                 y = 1;
5631
5632         snd_hda_power_up(codec);
5633         if (nid == XBASS_XOVER) {
5634                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5635                         if (ca0132_effects[i].nid == X_BASS)
5636                                 break;
5637
5638                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5639                                 ca0132_effects[i].reqs[1],
5640                                 &(lookup[idx - 1]), sizeof(unsigned int));
5641         } else {
5642                 /* Find the actual effect structure */
5643                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5644                         if (nid == ca0132_effects[i].nid)
5645                                 break;
5646
5647                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5648                                 ca0132_effects[i].reqs[y],
5649                                 &(lookup[idx]), sizeof(unsigned int));
5650         }
5651
5652         snd_hda_power_down(codec);
5653
5654         return 0;
5655 }
5656
5657 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5658                           struct snd_ctl_elem_value *ucontrol)
5659 {
5660         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5661         struct ca0132_spec *spec = codec->spec;
5662         long *valp = ucontrol->value.integer.value;
5663         hda_nid_t nid = get_amp_nid(kcontrol);
5664
5665         if (nid == BASS_REDIRECTION_XOVER)
5666                 *valp = spec->bass_redirect_xover_freq;
5667         else
5668                 *valp = spec->xbass_xover_freq;
5669
5670         return 0;
5671 }
5672
5673 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5674                           struct snd_ctl_elem_value *ucontrol)
5675 {
5676         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5677         struct ca0132_spec *spec = codec->spec;
5678         hda_nid_t nid = get_amp_nid(kcontrol);
5679         long *valp = ucontrol->value.integer.value;
5680         int idx = nid - OUT_EFFECT_START_NID;
5681
5682         *valp = spec->fx_ctl_val[idx];
5683         return 0;
5684 }
5685
5686 /*
5687  * The X-bass crossover starts at 10hz, so the min is 1. The
5688  * frequency is set in multiples of 10.
5689  */
5690 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5691                 struct snd_ctl_elem_info *uinfo)
5692 {
5693         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5694         uinfo->count = 1;
5695         uinfo->value.integer.min = 1;
5696         uinfo->value.integer.max = 100;
5697         uinfo->value.integer.step = 1;
5698
5699         return 0;
5700 }
5701
5702 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5703                 struct snd_ctl_elem_info *uinfo)
5704 {
5705         int chs = get_amp_channels(kcontrol);
5706
5707         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5708         uinfo->count = chs == 3 ? 2 : 1;
5709         uinfo->value.integer.min = 0;
5710         uinfo->value.integer.max = 100;
5711         uinfo->value.integer.step = 1;
5712
5713         return 0;
5714 }
5715
5716 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5717                                 struct snd_ctl_elem_value *ucontrol)
5718 {
5719         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5720         struct ca0132_spec *spec = codec->spec;
5721         hda_nid_t nid = get_amp_nid(kcontrol);
5722         long *valp = ucontrol->value.integer.value;
5723         long *cur_val;
5724         int idx;
5725
5726         if (nid == BASS_REDIRECTION_XOVER)
5727                 cur_val = &spec->bass_redirect_xover_freq;
5728         else
5729                 cur_val = &spec->xbass_xover_freq;
5730
5731         /* any change? */
5732         if (*cur_val == *valp)
5733                 return 0;
5734
5735         *cur_val = *valp;
5736
5737         idx = *valp;
5738         if (nid == BASS_REDIRECTION_XOVER)
5739                 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5740         else
5741                 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5742
5743         return 0;
5744 }
5745
5746 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5747                                 struct snd_ctl_elem_value *ucontrol)
5748 {
5749         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5750         struct ca0132_spec *spec = codec->spec;
5751         hda_nid_t nid = get_amp_nid(kcontrol);
5752         long *valp = ucontrol->value.integer.value;
5753         int idx;
5754
5755         idx = nid - EFFECT_START_NID;
5756         /* any change? */
5757         if (spec->fx_ctl_val[idx] == *valp)
5758                 return 0;
5759
5760         spec->fx_ctl_val[idx] = *valp;
5761
5762         idx = *valp;
5763         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5764
5765         return 0;
5766 }
5767
5768
5769 /*
5770  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5771  * only has off or full 30 dB, and didn't like making a volume slider that has
5772  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5773  */
5774 #define MIC_BOOST_NUM_OF_STEPS 4
5775 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5776
5777 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5778                                  struct snd_ctl_elem_info *uinfo)
5779 {
5780         char *sfx = "dB";
5781         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5782
5783         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5784         uinfo->count = 1;
5785         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5786         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5787                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5788         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5789         strcpy(uinfo->value.enumerated.name, namestr);
5790         return 0;
5791 }
5792
5793 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5794                                 struct snd_ctl_elem_value *ucontrol)
5795 {
5796         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5797         struct ca0132_spec *spec = codec->spec;
5798
5799         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5800         return 0;
5801 }
5802
5803 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5804                                 struct snd_ctl_elem_value *ucontrol)
5805 {
5806         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5807         struct ca0132_spec *spec = codec->spec;
5808         int sel = ucontrol->value.enumerated.item[0];
5809         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5810
5811         if (sel >= items)
5812                 return 0;
5813
5814         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5815                     sel);
5816
5817         spec->mic_boost_enum_val = sel;
5818
5819         if (spec->in_enum_val != REAR_LINE_IN)
5820                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5821
5822         return 1;
5823 }
5824
5825 /*
5826  * Sound BlasterX AE-5 Headphone Gain Controls.
5827  */
5828 #define AE5_HEADPHONE_GAIN_MAX 3
5829 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5830                                  struct snd_ctl_elem_info *uinfo)
5831 {
5832         char *sfx = " Ohms)";
5833         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5834
5835         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5836         uinfo->count = 1;
5837         uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5838         if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5839                 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5840         sprintf(namestr, "%s %s",
5841                 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5842                 sfx);
5843         strcpy(uinfo->value.enumerated.name, namestr);
5844         return 0;
5845 }
5846
5847 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5848                                 struct snd_ctl_elem_value *ucontrol)
5849 {
5850         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5851         struct ca0132_spec *spec = codec->spec;
5852
5853         ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5854         return 0;
5855 }
5856
5857 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5858                                 struct snd_ctl_elem_value *ucontrol)
5859 {
5860         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5861         struct ca0132_spec *spec = codec->spec;
5862         int sel = ucontrol->value.enumerated.item[0];
5863         unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5864
5865         if (sel >= items)
5866                 return 0;
5867
5868         codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5869                     sel);
5870
5871         spec->ae5_headphone_gain_val = sel;
5872
5873         if (spec->out_enum_val == HEADPHONE_OUT)
5874                 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5875
5876         return 1;
5877 }
5878
5879 /*
5880  * Sound BlasterX AE-5 sound filter enumerated control.
5881  */
5882 #define AE5_SOUND_FILTER_MAX 3
5883
5884 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5885                                  struct snd_ctl_elem_info *uinfo)
5886 {
5887         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5888
5889         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5890         uinfo->count = 1;
5891         uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5892         if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5893                 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5894         sprintf(namestr, "%s",
5895                         ae5_filter_presets[uinfo->value.enumerated.item].name);
5896         strcpy(uinfo->value.enumerated.name, namestr);
5897         return 0;
5898 }
5899
5900 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5901                                 struct snd_ctl_elem_value *ucontrol)
5902 {
5903         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5904         struct ca0132_spec *spec = codec->spec;
5905
5906         ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5907         return 0;
5908 }
5909
5910 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5911                                 struct snd_ctl_elem_value *ucontrol)
5912 {
5913         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5914         struct ca0132_spec *spec = codec->spec;
5915         int sel = ucontrol->value.enumerated.item[0];
5916         unsigned int items = AE5_SOUND_FILTER_MAX;
5917
5918         if (sel >= items)
5919                 return 0;
5920
5921         codec_dbg(codec, "ae5_sound_filter: %s\n",
5922                         ae5_filter_presets[sel].name);
5923
5924         spec->ae5_filter_val = sel;
5925
5926         ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5927                         ae5_filter_presets[sel].val);
5928
5929         return 1;
5930 }
5931
5932 /*
5933  * Input Select Control for alternative ca0132 codecs. This exists because
5934  * front microphone has no auto-detect, and we need a way to set the rear
5935  * as line-in
5936  */
5937 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5938                                  struct snd_ctl_elem_info *uinfo)
5939 {
5940         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5941         uinfo->count = 1;
5942         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5943         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5944                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5945         strcpy(uinfo->value.enumerated.name,
5946                         in_src_str[uinfo->value.enumerated.item]);
5947         return 0;
5948 }
5949
5950 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5951                                 struct snd_ctl_elem_value *ucontrol)
5952 {
5953         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5954         struct ca0132_spec *spec = codec->spec;
5955
5956         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5957         return 0;
5958 }
5959
5960 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5961                                 struct snd_ctl_elem_value *ucontrol)
5962 {
5963         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5964         struct ca0132_spec *spec = codec->spec;
5965         int sel = ucontrol->value.enumerated.item[0];
5966         unsigned int items = IN_SRC_NUM_OF_INPUTS;
5967
5968         /*
5969          * The AE-7 has no front microphone, so limit items to 2: rear mic and
5970          * line-in.
5971          */
5972         if (ca0132_quirk(spec) == QUIRK_AE7)
5973                 items = 2;
5974
5975         if (sel >= items)
5976                 return 0;
5977
5978         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5979                     sel, in_src_str[sel]);
5980
5981         spec->in_enum_val = sel;
5982
5983         ca0132_alt_select_in(codec);
5984
5985         return 1;
5986 }
5987
5988 /* Sound Blaster Z Output Select Control */
5989 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5990                                  struct snd_ctl_elem_info *uinfo)
5991 {
5992         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5993         uinfo->count = 1;
5994         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5995         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5996                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5997         strcpy(uinfo->value.enumerated.name,
5998                         out_type_str[uinfo->value.enumerated.item]);
5999         return 0;
6000 }
6001
6002 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
6003                                 struct snd_ctl_elem_value *ucontrol)
6004 {
6005         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6006         struct ca0132_spec *spec = codec->spec;
6007
6008         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6009         return 0;
6010 }
6011
6012 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6013                                 struct snd_ctl_elem_value *ucontrol)
6014 {
6015         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6016         struct ca0132_spec *spec = codec->spec;
6017         int sel = ucontrol->value.enumerated.item[0];
6018         unsigned int items = NUM_OF_OUTPUTS;
6019         unsigned int auto_jack;
6020
6021         if (sel >= items)
6022                 return 0;
6023
6024         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6025                     sel, out_type_str[sel]);
6026
6027         spec->out_enum_val = sel;
6028
6029         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6030
6031         if (!auto_jack)
6032                 ca0132_alt_select_out(codec);
6033
6034         return 1;
6035 }
6036
6037 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
6038 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6039                                  struct snd_ctl_elem_info *uinfo)
6040 {
6041         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6042
6043         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6044         uinfo->count = 1;
6045         uinfo->value.enumerated.items = items;
6046         if (uinfo->value.enumerated.item >= items)
6047                 uinfo->value.enumerated.item = items - 1;
6048         strcpy(uinfo->value.enumerated.name,
6049                         speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6050         return 0;
6051 }
6052
6053 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6054                                 struct snd_ctl_elem_value *ucontrol)
6055 {
6056         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6057         struct ca0132_spec *spec = codec->spec;
6058
6059         ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6060         return 0;
6061 }
6062
6063 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6064                                 struct snd_ctl_elem_value *ucontrol)
6065 {
6066         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6067         struct ca0132_spec *spec = codec->spec;
6068         int sel = ucontrol->value.enumerated.item[0];
6069         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6070
6071         if (sel >= items)
6072                 return 0;
6073
6074         codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6075                     sel, speaker_channel_cfgs[sel].name);
6076
6077         spec->channel_cfg_val = sel;
6078
6079         if (spec->out_enum_val == SPEAKER_OUT)
6080                 ca0132_alt_select_out(codec);
6081
6082         return 1;
6083 }
6084
6085 /*
6086  * Smart Volume output setting control. Three different settings, Normal,
6087  * which takes the value from the smart volume slider. The two others, loud
6088  * and night, disregard the slider value and have uneditable values.
6089  */
6090 #define NUM_OF_SVM_SETTINGS 3
6091 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6092
6093 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6094                                  struct snd_ctl_elem_info *uinfo)
6095 {
6096         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6097         uinfo->count = 1;
6098         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6099         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6100                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6101         strcpy(uinfo->value.enumerated.name,
6102                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
6103         return 0;
6104 }
6105
6106 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6107                                 struct snd_ctl_elem_value *ucontrol)
6108 {
6109         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6110         struct ca0132_spec *spec = codec->spec;
6111
6112         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6113         return 0;
6114 }
6115
6116 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6117                                 struct snd_ctl_elem_value *ucontrol)
6118 {
6119         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6120         struct ca0132_spec *spec = codec->spec;
6121         int sel = ucontrol->value.enumerated.item[0];
6122         unsigned int items = NUM_OF_SVM_SETTINGS;
6123         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6124         unsigned int tmp;
6125
6126         if (sel >= items)
6127                 return 0;
6128
6129         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6130                     sel, out_svm_set_enum_str[sel]);
6131
6132         spec->smart_volume_setting = sel;
6133
6134         switch (sel) {
6135         case 0:
6136                 tmp = FLOAT_ZERO;
6137                 break;
6138         case 1:
6139                 tmp = FLOAT_ONE;
6140                 break;
6141         case 2:
6142                 tmp = FLOAT_TWO;
6143                 break;
6144         default:
6145                 tmp = FLOAT_ZERO;
6146                 break;
6147         }
6148         /* Req 2 is the Smart Volume Setting req. */
6149         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6150                         ca0132_effects[idx].reqs[2], tmp);
6151         return 1;
6152 }
6153
6154 /* Sound Blaster Z EQ preset controls */
6155 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6156                                  struct snd_ctl_elem_info *uinfo)
6157 {
6158         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6159
6160         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6161         uinfo->count = 1;
6162         uinfo->value.enumerated.items = items;
6163         if (uinfo->value.enumerated.item >= items)
6164                 uinfo->value.enumerated.item = items - 1;
6165         strcpy(uinfo->value.enumerated.name,
6166                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6167         return 0;
6168 }
6169
6170 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6171                                 struct snd_ctl_elem_value *ucontrol)
6172 {
6173         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6174         struct ca0132_spec *spec = codec->spec;
6175
6176         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6177         return 0;
6178 }
6179
6180 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6181                                 struct snd_ctl_elem_value *ucontrol)
6182 {
6183         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6184         struct ca0132_spec *spec = codec->spec;
6185         int i, err = 0;
6186         int sel = ucontrol->value.enumerated.item[0];
6187         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6188
6189         if (sel >= items)
6190                 return 0;
6191
6192         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6193                         ca0132_alt_eq_presets[sel].name);
6194         /*
6195          * Idx 0 is default.
6196          * Default needs to qualify with CrystalVoice state.
6197          */
6198         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6199                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6200                                 ca0132_alt_eq_enum.reqs[i],
6201                                 ca0132_alt_eq_presets[sel].vals[i]);
6202                 if (err < 0)
6203                         break;
6204         }
6205
6206         if (err >= 0)
6207                 spec->eq_preset_val = sel;
6208
6209         return 1;
6210 }
6211
6212 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6213                                  struct snd_ctl_elem_info *uinfo)
6214 {
6215         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6216
6217         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6218         uinfo->count = 1;
6219         uinfo->value.enumerated.items = items;
6220         if (uinfo->value.enumerated.item >= items)
6221                 uinfo->value.enumerated.item = items - 1;
6222         strcpy(uinfo->value.enumerated.name,
6223                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6224         return 0;
6225 }
6226
6227 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6228                                 struct snd_ctl_elem_value *ucontrol)
6229 {
6230         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6231         struct ca0132_spec *spec = codec->spec;
6232
6233         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6234         return 0;
6235 }
6236
6237 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6238                                 struct snd_ctl_elem_value *ucontrol)
6239 {
6240         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6241         struct ca0132_spec *spec = codec->spec;
6242         int i, err = 0;
6243         int sel = ucontrol->value.enumerated.item[0];
6244
6245         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6246                 return 0;
6247
6248         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6249                     sel, ca0132_voicefx_presets[sel].name);
6250
6251         /*
6252          * Idx 0 is default.
6253          * Default needs to qualify with CrystalVoice state.
6254          */
6255         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6256                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6257                                 ca0132_voicefx.reqs[i],
6258                                 ca0132_voicefx_presets[sel].vals[i]);
6259                 if (err < 0)
6260                         break;
6261         }
6262
6263         if (err >= 0) {
6264                 spec->voicefx_val = sel;
6265                 /* enable voice fx */
6266                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6267         }
6268
6269         return 1;
6270 }
6271
6272 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6273                                 struct snd_ctl_elem_value *ucontrol)
6274 {
6275         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6276         struct ca0132_spec *spec = codec->spec;
6277         hda_nid_t nid = get_amp_nid(kcontrol);
6278         int ch = get_amp_channels(kcontrol);
6279         long *valp = ucontrol->value.integer.value;
6280
6281         /* vnode */
6282         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6283                 if (ch & 1) {
6284                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6285                         valp++;
6286                 }
6287                 if (ch & 2) {
6288                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6289                         valp++;
6290                 }
6291                 return 0;
6292         }
6293
6294         /* effects, include PE and CrystalVoice */
6295         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6296                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6297                 return 0;
6298         }
6299
6300         /* mic boost */
6301         if (nid == spec->input_pins[0]) {
6302                 *valp = spec->cur_mic_boost;
6303                 return 0;
6304         }
6305
6306         if (nid == ZXR_HEADPHONE_GAIN) {
6307                 *valp = spec->zxr_gain_set;
6308                 return 0;
6309         }
6310
6311         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6312                 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6313                 return 0;
6314         }
6315
6316         if (nid == BASS_REDIRECTION) {
6317                 *valp = spec->bass_redirection_val;
6318                 return 0;
6319         }
6320
6321         return 0;
6322 }
6323
6324 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6325                              struct snd_ctl_elem_value *ucontrol)
6326 {
6327         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6328         struct ca0132_spec *spec = codec->spec;
6329         hda_nid_t nid = get_amp_nid(kcontrol);
6330         int ch = get_amp_channels(kcontrol);
6331         long *valp = ucontrol->value.integer.value;
6332         int changed = 1;
6333
6334         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6335                     nid, *valp);
6336
6337         snd_hda_power_up(codec);
6338         /* vnode */
6339         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6340                 if (ch & 1) {
6341                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6342                         valp++;
6343                 }
6344                 if (ch & 2) {
6345                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6346                         valp++;
6347                 }
6348                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6349                 goto exit;
6350         }
6351
6352         /* PE */
6353         if (nid == PLAY_ENHANCEMENT) {
6354                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6355                 changed = ca0132_pe_switch_set(codec);
6356                 goto exit;
6357         }
6358
6359         /* CrystalVoice */
6360         if (nid == CRYSTAL_VOICE) {
6361                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6362                 changed = ca0132_cvoice_switch_set(codec);
6363                 goto exit;
6364         }
6365
6366         /* out and in effects */
6367         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6368             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6369                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6370                 changed = ca0132_effects_set(codec, nid, *valp);
6371                 goto exit;
6372         }
6373
6374         /* mic boost */
6375         if (nid == spec->input_pins[0]) {
6376                 spec->cur_mic_boost = *valp;
6377                 if (ca0132_use_alt_functions(spec)) {
6378                         if (spec->in_enum_val != REAR_LINE_IN)
6379                                 changed = ca0132_mic_boost_set(codec, *valp);
6380                 } else {
6381                         /* Mic boost does not apply to Digital Mic */
6382                         if (spec->cur_mic_type != DIGITAL_MIC)
6383                                 changed = ca0132_mic_boost_set(codec, *valp);
6384                 }
6385
6386                 goto exit;
6387         }
6388
6389         if (nid == ZXR_HEADPHONE_GAIN) {
6390                 spec->zxr_gain_set = *valp;
6391                 if (spec->cur_out_type == HEADPHONE_OUT)
6392                         changed = zxr_headphone_gain_set(codec, *valp);
6393                 else
6394                         changed = 0;
6395
6396                 goto exit;
6397         }
6398
6399         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6400                 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6401                 if (spec->cur_out_type == SPEAKER_OUT)
6402                         ca0132_alt_set_full_range_speaker(codec);
6403
6404                 changed = 0;
6405         }
6406
6407         if (nid == BASS_REDIRECTION) {
6408                 spec->bass_redirection_val = *valp;
6409                 if (spec->cur_out_type == SPEAKER_OUT)
6410                         ca0132_alt_surround_set_bass_redirection(codec, *valp);
6411
6412                 changed = 0;
6413         }
6414
6415 exit:
6416         snd_hda_power_down(codec);
6417         return changed;
6418 }
6419
6420 /*
6421  * Volume related
6422  */
6423 /*
6424  * Sets the internal DSP decibel level to match the DAC for output, and the
6425  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6426  * all alternative codecs set DSP playback volume.
6427  */
6428 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6429 {
6430         struct ca0132_spec *spec = codec->spec;
6431         unsigned int dsp_dir;
6432         unsigned int lookup_val;
6433
6434         if (nid == VNID_SPK)
6435                 dsp_dir = DSP_VOL_OUT;
6436         else
6437                 dsp_dir = DSP_VOL_IN;
6438
6439         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6440
6441         dspio_set_uint_param(codec,
6442                 ca0132_alt_vol_ctls[dsp_dir].mid,
6443                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6444                 float_vol_db_lookup[lookup_val]);
6445
6446         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6447
6448         dspio_set_uint_param(codec,
6449                 ca0132_alt_vol_ctls[dsp_dir].mid,
6450                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6451                 float_vol_db_lookup[lookup_val]);
6452
6453         dspio_set_uint_param(codec,
6454                 ca0132_alt_vol_ctls[dsp_dir].mid,
6455                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6456 }
6457
6458 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6459                               struct snd_ctl_elem_info *uinfo)
6460 {
6461         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6462         struct ca0132_spec *spec = codec->spec;
6463         hda_nid_t nid = get_amp_nid(kcontrol);
6464         int ch = get_amp_channels(kcontrol);
6465         int dir = get_amp_direction(kcontrol);
6466         unsigned long pval;
6467         int err;
6468
6469         switch (nid) {
6470         case VNID_SPK:
6471                 /* follow shared_out info */
6472                 nid = spec->shared_out_nid;
6473                 mutex_lock(&codec->control_mutex);
6474                 pval = kcontrol->private_value;
6475                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6476                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6477                 kcontrol->private_value = pval;
6478                 mutex_unlock(&codec->control_mutex);
6479                 break;
6480         case VNID_MIC:
6481                 /* follow shared_mic info */
6482                 nid = spec->shared_mic_nid;
6483                 mutex_lock(&codec->control_mutex);
6484                 pval = kcontrol->private_value;
6485                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6486                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6487                 kcontrol->private_value = pval;
6488                 mutex_unlock(&codec->control_mutex);
6489                 break;
6490         default:
6491                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6492         }
6493         return err;
6494 }
6495
6496 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6497                                 struct snd_ctl_elem_value *ucontrol)
6498 {
6499         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6500         struct ca0132_spec *spec = codec->spec;
6501         hda_nid_t nid = get_amp_nid(kcontrol);
6502         int ch = get_amp_channels(kcontrol);
6503         long *valp = ucontrol->value.integer.value;
6504
6505         /* store the left and right volume */
6506         if (ch & 1) {
6507                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6508                 valp++;
6509         }
6510         if (ch & 2) {
6511                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6512                 valp++;
6513         }
6514         return 0;
6515 }
6516
6517 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6518                                 struct snd_ctl_elem_value *ucontrol)
6519 {
6520         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6521         struct ca0132_spec *spec = codec->spec;
6522         hda_nid_t nid = get_amp_nid(kcontrol);
6523         int ch = get_amp_channels(kcontrol);
6524         long *valp = ucontrol->value.integer.value;
6525         hda_nid_t shared_nid = 0;
6526         bool effective;
6527         int changed = 1;
6528
6529         /* store the left and right volume */
6530         if (ch & 1) {
6531                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6532                 valp++;
6533         }
6534         if (ch & 2) {
6535                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6536                 valp++;
6537         }
6538
6539         /* if effective conditions, then update hw immediately. */
6540         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6541         if (effective) {
6542                 int dir = get_amp_direction(kcontrol);
6543                 unsigned long pval;
6544
6545                 snd_hda_power_up(codec);
6546                 mutex_lock(&codec->control_mutex);
6547                 pval = kcontrol->private_value;
6548                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6549                                                                 0, dir);
6550                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6551                 kcontrol->private_value = pval;
6552                 mutex_unlock(&codec->control_mutex);
6553                 snd_hda_power_down(codec);
6554         }
6555
6556         return changed;
6557 }
6558
6559 /*
6560  * This function is the same as the one above, because using an if statement
6561  * inside of the above volume control for the DSP volume would cause too much
6562  * lag. This is a lot more smooth.
6563  */
6564 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6565                                 struct snd_ctl_elem_value *ucontrol)
6566 {
6567         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6568         struct ca0132_spec *spec = codec->spec;
6569         hda_nid_t nid = get_amp_nid(kcontrol);
6570         int ch = get_amp_channels(kcontrol);
6571         long *valp = ucontrol->value.integer.value;
6572         hda_nid_t vnid = 0;
6573         int changed;
6574
6575         switch (nid) {
6576         case 0x02:
6577                 vnid = VNID_SPK;
6578                 break;
6579         case 0x07:
6580                 vnid = VNID_MIC;
6581                 break;
6582         }
6583
6584         /* store the left and right volume */
6585         if (ch & 1) {
6586                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6587                 valp++;
6588         }
6589         if (ch & 2) {
6590                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6591                 valp++;
6592         }
6593
6594         snd_hda_power_up(codec);
6595         ca0132_alt_dsp_volume_put(codec, vnid);
6596         mutex_lock(&codec->control_mutex);
6597         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6598         mutex_unlock(&codec->control_mutex);
6599         snd_hda_power_down(codec);
6600
6601         return changed;
6602 }
6603
6604 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6605                              unsigned int size, unsigned int __user *tlv)
6606 {
6607         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6608         struct ca0132_spec *spec = codec->spec;
6609         hda_nid_t nid = get_amp_nid(kcontrol);
6610         int ch = get_amp_channels(kcontrol);
6611         int dir = get_amp_direction(kcontrol);
6612         unsigned long pval;
6613         int err;
6614
6615         switch (nid) {
6616         case VNID_SPK:
6617                 /* follow shared_out tlv */
6618                 nid = spec->shared_out_nid;
6619                 mutex_lock(&codec->control_mutex);
6620                 pval = kcontrol->private_value;
6621                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6622                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6623                 kcontrol->private_value = pval;
6624                 mutex_unlock(&codec->control_mutex);
6625                 break;
6626         case VNID_MIC:
6627                 /* follow shared_mic tlv */
6628                 nid = spec->shared_mic_nid;
6629                 mutex_lock(&codec->control_mutex);
6630                 pval = kcontrol->private_value;
6631                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6632                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6633                 kcontrol->private_value = pval;
6634                 mutex_unlock(&codec->control_mutex);
6635                 break;
6636         default:
6637                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6638         }
6639         return err;
6640 }
6641
6642 /* Add volume slider control for effect level */
6643 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6644                                         const char *pfx, int dir)
6645 {
6646         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6647         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6648         struct snd_kcontrol_new knew =
6649                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6650
6651         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6652
6653         knew.tlv.c = NULL;
6654
6655         switch (nid) {
6656         case XBASS_XOVER:
6657                 knew.info = ca0132_alt_xbass_xover_slider_info;
6658                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6659                 knew.put = ca0132_alt_xbass_xover_slider_put;
6660                 break;
6661         default:
6662                 knew.info = ca0132_alt_effect_slider_info;
6663                 knew.get = ca0132_alt_slider_ctl_get;
6664                 knew.put = ca0132_alt_effect_slider_put;
6665                 knew.private_value =
6666                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6667                 break;
6668         }
6669
6670         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6671 }
6672
6673 /*
6674  * Added FX: prefix for the alternative codecs, because otherwise the surround
6675  * effect would conflict with the Surround sound volume control. Also seems more
6676  * clear as to what the switches do. Left alone for others.
6677  */
6678 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6679                          const char *pfx, int dir)
6680 {
6681         struct ca0132_spec *spec = codec->spec;
6682         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6683         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6684         struct snd_kcontrol_new knew =
6685                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6686         /* If using alt_controls, add FX: prefix. But, don't add FX:
6687          * prefix to OutFX or InFX enable controls.
6688          */
6689         if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6690                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6691         else
6692                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6693
6694         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6695 }
6696
6697 static int add_voicefx(struct hda_codec *codec)
6698 {
6699         struct snd_kcontrol_new knew =
6700                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6701                                     VOICEFX, 1, 0, HDA_INPUT);
6702         knew.info = ca0132_voicefx_info;
6703         knew.get = ca0132_voicefx_get;
6704         knew.put = ca0132_voicefx_put;
6705         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6706 }
6707
6708 /* Create the EQ Preset control */
6709 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6710 {
6711         struct snd_kcontrol_new knew =
6712                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6713                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6714         knew.info = ca0132_alt_eq_preset_info;
6715         knew.get = ca0132_alt_eq_preset_get;
6716         knew.put = ca0132_alt_eq_preset_put;
6717         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6718                                 snd_ctl_new1(&knew, codec));
6719 }
6720
6721 /*
6722  * Add enumerated control for the three different settings of the smart volume
6723  * output effect. Normal just uses the slider value, and loud and night are
6724  * their own things that ignore that value.
6725  */
6726 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6727 {
6728         struct snd_kcontrol_new knew =
6729                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6730                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6731         knew.info = ca0132_alt_svm_setting_info;
6732         knew.get = ca0132_alt_svm_setting_get;
6733         knew.put = ca0132_alt_svm_setting_put;
6734         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6735                                 snd_ctl_new1(&knew, codec));
6736
6737 }
6738
6739 /*
6740  * Create an Output Select enumerated control for codecs with surround
6741  * out capabilities.
6742  */
6743 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6744 {
6745         struct snd_kcontrol_new knew =
6746                 HDA_CODEC_MUTE_MONO("Output Select",
6747                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6748         knew.info = ca0132_alt_output_select_get_info;
6749         knew.get = ca0132_alt_output_select_get;
6750         knew.put = ca0132_alt_output_select_put;
6751         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6752                                 snd_ctl_new1(&knew, codec));
6753 }
6754
6755 /*
6756  * Add a control for selecting channel count on speaker output. Setting this
6757  * allows the DSP to do bass redirection and channel upmixing on surround
6758  * configurations.
6759  */
6760 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6761 {
6762         struct snd_kcontrol_new knew =
6763                 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6764                                     SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6765         knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6766         knew.get = ca0132_alt_speaker_channel_cfg_get;
6767         knew.put = ca0132_alt_speaker_channel_cfg_put;
6768         return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6769                                 snd_ctl_new1(&knew, codec));
6770 }
6771
6772 /*
6773  * Full range front stereo and rear surround switches. When these are set to
6774  * full range, the lower frequencies from these channels are no longer
6775  * redirected to the LFE channel.
6776  */
6777 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6778 {
6779         struct snd_kcontrol_new knew =
6780                 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6781                                     SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6782
6783         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6784                                 snd_ctl_new1(&knew, codec));
6785 }
6786
6787 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6788 {
6789         struct snd_kcontrol_new knew =
6790                 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6791                                     SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6792
6793         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6794                                 snd_ctl_new1(&knew, codec));
6795 }
6796
6797 /*
6798  * Bass redirection redirects audio below the crossover frequency to the LFE
6799  * channel on speakers that are set as not being full-range. On configurations
6800  * without an LFE channel, it does nothing. Bass redirection seems to be the
6801  * replacement for X-Bass on configurations with an LFE channel.
6802  */
6803 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6804 {
6805         const char *namestr = "Bass Redirection Crossover";
6806         struct snd_kcontrol_new knew =
6807                 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6808                                 HDA_OUTPUT);
6809
6810         knew.tlv.c = NULL;
6811         knew.info = ca0132_alt_xbass_xover_slider_info;
6812         knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6813         knew.put = ca0132_alt_xbass_xover_slider_put;
6814
6815         return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6816                         snd_ctl_new1(&knew, codec));
6817 }
6818
6819 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6820 {
6821         const char *namestr = "Bass Redirection";
6822         struct snd_kcontrol_new knew =
6823                 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6824                                 HDA_OUTPUT);
6825
6826         return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6827                         snd_ctl_new1(&knew, codec));
6828 }
6829
6830 /*
6831  * Create an Input Source enumerated control for the alternate ca0132 codecs
6832  * because the front microphone has no auto-detect, and Line-in has to be set
6833  * somehow.
6834  */
6835 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6836 {
6837         struct snd_kcontrol_new knew =
6838                 HDA_CODEC_MUTE_MONO("Input Source",
6839                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6840         knew.info = ca0132_alt_input_source_info;
6841         knew.get = ca0132_alt_input_source_get;
6842         knew.put = ca0132_alt_input_source_put;
6843         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6844                                 snd_ctl_new1(&knew, codec));
6845 }
6846
6847 /*
6848  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6849  * more control than the original mic boost, which is either full 30dB or off.
6850  */
6851 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6852 {
6853         struct snd_kcontrol_new knew =
6854                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6855                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6856         knew.info = ca0132_alt_mic_boost_info;
6857         knew.get = ca0132_alt_mic_boost_get;
6858         knew.put = ca0132_alt_mic_boost_put;
6859         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6860                                 snd_ctl_new1(&knew, codec));
6861
6862 }
6863
6864 /*
6865  * Add headphone gain enumerated control for the AE-5. This switches between
6866  * three modes, low, medium, and high. When non-headphone outputs are selected,
6867  * it is automatically set to high. This is the same behavior as Windows.
6868  */
6869 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6870 {
6871         struct snd_kcontrol_new knew =
6872                 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6873                                     AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6874         knew.info = ae5_headphone_gain_info;
6875         knew.get = ae5_headphone_gain_get;
6876         knew.put = ae5_headphone_gain_put;
6877         return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6878                                 snd_ctl_new1(&knew, codec));
6879 }
6880
6881 /*
6882  * Add sound filter enumerated control for the AE-5. This adds three different
6883  * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6884  * read into it, it changes the DAC's interpolation filter.
6885  */
6886 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6887 {
6888         struct snd_kcontrol_new knew =
6889                 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6890                                     AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6891         knew.info = ae5_sound_filter_info;
6892         knew.get = ae5_sound_filter_get;
6893         knew.put = ae5_sound_filter_put;
6894         return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6895                                 snd_ctl_new1(&knew, codec));
6896 }
6897
6898 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6899 {
6900         struct snd_kcontrol_new knew =
6901                 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6902                                     ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6903
6904         return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6905                                 snd_ctl_new1(&knew, codec));
6906 }
6907
6908 /*
6909  * Need to create follower controls for the alternate codecs that have surround
6910  * capabilities.
6911  */
6912 static const char * const ca0132_alt_follower_pfxs[] = {
6913         "Front", "Surround", "Center", "LFE", NULL,
6914 };
6915
6916 /*
6917  * Also need special channel map, because the default one is incorrect.
6918  * I think this has to do with the pin for rear surround being 0x11,
6919  * and the center/lfe being 0x10. Usually the pin order is the opposite.
6920  */
6921 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6922         { .channels = 2,
6923           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6924         { .channels = 4,
6925           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6926                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6927         { .channels = 6,
6928           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6929                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6930                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6931         { }
6932 };
6933
6934 /* Add the correct chmap for streams with 6 channels. */
6935 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6936 {
6937         int err = 0;
6938         struct hda_pcm *pcm;
6939
6940         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6941                 struct hda_pcm_stream *hinfo =
6942                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6943                 struct snd_pcm_chmap *chmap;
6944                 const struct snd_pcm_chmap_elem *elem;
6945
6946                 elem = ca0132_alt_chmaps;
6947                 if (hinfo->channels_max == 6) {
6948                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
6949                                         SNDRV_PCM_STREAM_PLAYBACK,
6950                                         elem, hinfo->channels_max, 0, &chmap);
6951                         if (err < 0)
6952                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6953                 }
6954         }
6955 }
6956
6957 /*
6958  * When changing Node IDs for Mixer Controls below, make sure to update
6959  * Node IDs in ca0132_config() as well.
6960  */
6961 static const struct snd_kcontrol_new ca0132_mixer[] = {
6962         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6963         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6964         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6965         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6966         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6967         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6968         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6969         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6970         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6971                                0x12, 1, HDA_INPUT),
6972         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6973                                VNID_HP_SEL, 1, HDA_OUTPUT),
6974         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6975                                VNID_AMIC1_SEL, 1, HDA_INPUT),
6976         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6977                                VNID_HP_ASEL, 1, HDA_OUTPUT),
6978         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6979                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
6980         { } /* end */
6981 };
6982
6983 /*
6984  * Desktop specific control mixer. Removes auto-detect for mic, and adds
6985  * surround controls. Also sets both the Front Playback and Capture Volume
6986  * controls to alt so they set the DSP's decibel level.
6987  */
6988 static const struct snd_kcontrol_new desktop_mixer[] = {
6989         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6990         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6991         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6992         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6993         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6994         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6995         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6996         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6997         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6998         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6999         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7000         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7001         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7002                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
7003         { } /* end */
7004 };
7005
7006 /*
7007  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7008  * because it doesn't set decibel levels for the DSP for capture.
7009  */
7010 static const struct snd_kcontrol_new r3di_mixer[] = {
7011         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7012         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7013         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7014         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7015         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7016         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7017         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7018         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7019         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7020         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7021         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7022         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7023         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7024                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
7025         { } /* end */
7026 };
7027
7028 static int ca0132_build_controls(struct hda_codec *codec)
7029 {
7030         struct ca0132_spec *spec = codec->spec;
7031         int i, num_fx, num_sliders;
7032         int err = 0;
7033
7034         /* Add Mixer controls */
7035         for (i = 0; i < spec->num_mixers; i++) {
7036                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7037                 if (err < 0)
7038                         return err;
7039         }
7040         /* Setup vmaster with surround followers for desktop ca0132 devices */
7041         if (ca0132_use_alt_functions(spec)) {
7042                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7043                                         spec->tlv);
7044                 snd_hda_add_vmaster(codec, "Master Playback Volume",
7045                                         spec->tlv, ca0132_alt_follower_pfxs,
7046                                         "Playback Volume", 0);
7047                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7048                                             NULL, ca0132_alt_follower_pfxs,
7049                                             "Playback Switch",
7050                                             true, 0, &spec->vmaster_mute.sw_kctl);
7051                 if (err < 0)
7052                         return err;
7053         }
7054
7055         /* Add in and out effects controls.
7056          * VoiceFX, PE and CrystalVoice are added separately.
7057          */
7058         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7059         for (i = 0; i < num_fx; i++) {
7060                 /* Desktop cards break if Echo Cancellation is used. */
7061                 if (ca0132_use_pci_mmio(spec)) {
7062                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7063                                                 OUT_EFFECTS_COUNT))
7064                                 continue;
7065                 }
7066
7067                 err = add_fx_switch(codec, ca0132_effects[i].nid,
7068                                     ca0132_effects[i].name,
7069                                     ca0132_effects[i].direct);
7070                 if (err < 0)
7071                         return err;
7072         }
7073         /*
7074          * If codec has use_alt_controls set to true, add effect level sliders,
7075          * EQ presets, and Smart Volume presets. Also, change names to add FX
7076          * prefix, and change PlayEnhancement and CrystalVoice to match.
7077          */
7078         if (ca0132_use_alt_controls(spec)) {
7079                 err = ca0132_alt_add_svm_enum(codec);
7080                 if (err < 0)
7081                         return err;
7082
7083                 err = add_ca0132_alt_eq_presets(codec);
7084                 if (err < 0)
7085                         return err;
7086
7087                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7088                                         "Enable OutFX", 0);
7089                 if (err < 0)
7090                         return err;
7091
7092                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7093                                         "Enable InFX", 1);
7094                 if (err < 0)
7095                         return err;
7096
7097                 num_sliders = OUT_EFFECTS_COUNT - 1;
7098                 for (i = 0; i < num_sliders; i++) {
7099                         err = ca0132_alt_add_effect_slider(codec,
7100                                             ca0132_effects[i].nid,
7101                                             ca0132_effects[i].name,
7102                                             ca0132_effects[i].direct);
7103                         if (err < 0)
7104                                 return err;
7105                 }
7106
7107                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7108                                         "X-Bass Crossover", EFX_DIR_OUT);
7109
7110                 if (err < 0)
7111                         return err;
7112         } else {
7113                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7114                                         "PlayEnhancement", 0);
7115                 if (err < 0)
7116                         return err;
7117
7118                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7119                                         "CrystalVoice", 1);
7120                 if (err < 0)
7121                         return err;
7122         }
7123         err = add_voicefx(codec);
7124         if (err < 0)
7125                 return err;
7126
7127         /*
7128          * If the codec uses alt_functions, you need the enumerated controls
7129          * to select the new outputs and inputs, plus add the new mic boost
7130          * setting control.
7131          */
7132         if (ca0132_use_alt_functions(spec)) {
7133                 err = ca0132_alt_add_output_enum(codec);
7134                 if (err < 0)
7135                         return err;
7136                 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7137                 if (err < 0)
7138                         return err;
7139                 err = ca0132_alt_add_front_full_range_switch(codec);
7140                 if (err < 0)
7141                         return err;
7142                 err = ca0132_alt_add_rear_full_range_switch(codec);
7143                 if (err < 0)
7144                         return err;
7145                 err = ca0132_alt_add_bass_redirection_crossover(codec);
7146                 if (err < 0)
7147                         return err;
7148                 err = ca0132_alt_add_bass_redirection_switch(codec);
7149                 if (err < 0)
7150                         return err;
7151                 err = ca0132_alt_add_mic_boost_enum(codec);
7152                 if (err < 0)
7153                         return err;
7154                 /*
7155                  * ZxR only has microphone input, there is no front panel
7156                  * header on the card, and aux-in is handled by the DBPro board.
7157                  */
7158                 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7159                         err = ca0132_alt_add_input_enum(codec);
7160                         if (err < 0)
7161                                 return err;
7162                 }
7163         }
7164
7165         switch (ca0132_quirk(spec)) {
7166         case QUIRK_AE5:
7167         case QUIRK_AE7:
7168                 err = ae5_add_headphone_gain_enum(codec);
7169                 if (err < 0)
7170                         return err;
7171                 err = ae5_add_sound_filter_enum(codec);
7172                 if (err < 0)
7173                         return err;
7174                 break;
7175         case QUIRK_ZXR:
7176                 err = zxr_add_headphone_gain_switch(codec);
7177                 if (err < 0)
7178                         return err;
7179                 break;
7180         default:
7181                 break;
7182         }
7183
7184 #ifdef ENABLE_TUNING_CONTROLS
7185         add_tuning_ctls(codec);
7186 #endif
7187
7188         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7189         if (err < 0)
7190                 return err;
7191
7192         if (spec->dig_out) {
7193                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7194                                                     spec->dig_out);
7195                 if (err < 0)
7196                         return err;
7197                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7198                 if (err < 0)
7199                         return err;
7200                 /* spec->multiout.share_spdif = 1; */
7201         }
7202
7203         if (spec->dig_in) {
7204                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7205                 if (err < 0)
7206                         return err;
7207         }
7208
7209         if (ca0132_use_alt_functions(spec))
7210                 ca0132_alt_add_chmap_ctls(codec);
7211
7212         return 0;
7213 }
7214
7215 static int dbpro_build_controls(struct hda_codec *codec)
7216 {
7217         struct ca0132_spec *spec = codec->spec;
7218         int err = 0;
7219
7220         if (spec->dig_out) {
7221                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7222                                 spec->dig_out);
7223                 if (err < 0)
7224                         return err;
7225         }
7226
7227         if (spec->dig_in) {
7228                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7229                 if (err < 0)
7230                         return err;
7231         }
7232
7233         return 0;
7234 }
7235
7236 /*
7237  * PCM
7238  */
7239 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7240         .substreams = 1,
7241         .channels_min = 2,
7242         .channels_max = 6,
7243         .ops = {
7244                 .prepare = ca0132_playback_pcm_prepare,
7245                 .cleanup = ca0132_playback_pcm_cleanup,
7246                 .get_delay = ca0132_playback_pcm_delay,
7247         },
7248 };
7249
7250 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7251         .substreams = 1,
7252         .channels_min = 2,
7253         .channels_max = 2,
7254         .ops = {
7255                 .prepare = ca0132_capture_pcm_prepare,
7256                 .cleanup = ca0132_capture_pcm_cleanup,
7257                 .get_delay = ca0132_capture_pcm_delay,
7258         },
7259 };
7260
7261 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7262         .substreams = 1,
7263         .channels_min = 2,
7264         .channels_max = 2,
7265         .ops = {
7266                 .open = ca0132_dig_playback_pcm_open,
7267                 .close = ca0132_dig_playback_pcm_close,
7268                 .prepare = ca0132_dig_playback_pcm_prepare,
7269                 .cleanup = ca0132_dig_playback_pcm_cleanup
7270         },
7271 };
7272
7273 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7274         .substreams = 1,
7275         .channels_min = 2,
7276         .channels_max = 2,
7277 };
7278
7279 static int ca0132_build_pcms(struct hda_codec *codec)
7280 {
7281         struct ca0132_spec *spec = codec->spec;
7282         struct hda_pcm *info;
7283
7284         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7285         if (!info)
7286                 return -ENOMEM;
7287         if (ca0132_use_alt_functions(spec)) {
7288                 info->own_chmap = true;
7289                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7290                         = ca0132_alt_chmaps;
7291         }
7292         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7293         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7294         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7295                 spec->multiout.max_channels;
7296         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7297         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7298         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7299
7300         /* With the DSP enabled, desktops don't use this ADC. */
7301         if (!ca0132_use_alt_functions(spec)) {
7302                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7303                 if (!info)
7304                         return -ENOMEM;
7305                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7306                         ca0132_pcm_analog_capture;
7307                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7308                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7309         }
7310
7311         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7312         if (!info)
7313                 return -ENOMEM;
7314         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7315         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7316         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7317
7318         if (!spec->dig_out && !spec->dig_in)
7319                 return 0;
7320
7321         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7322         if (!info)
7323                 return -ENOMEM;
7324         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7325         if (spec->dig_out) {
7326                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7327                         ca0132_pcm_digital_playback;
7328                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7329         }
7330         if (spec->dig_in) {
7331                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7332                         ca0132_pcm_digital_capture;
7333                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7334         }
7335
7336         return 0;
7337 }
7338
7339 static int dbpro_build_pcms(struct hda_codec *codec)
7340 {
7341         struct ca0132_spec *spec = codec->spec;
7342         struct hda_pcm *info;
7343
7344         info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7345         if (!info)
7346                 return -ENOMEM;
7347         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7348         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7349         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7350
7351
7352         if (!spec->dig_out && !spec->dig_in)
7353                 return 0;
7354
7355         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7356         if (!info)
7357                 return -ENOMEM;
7358         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7359         if (spec->dig_out) {
7360                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7361                         ca0132_pcm_digital_playback;
7362                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7363         }
7364         if (spec->dig_in) {
7365                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7366                         ca0132_pcm_digital_capture;
7367                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7368         }
7369
7370         return 0;
7371 }
7372
7373 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7374 {
7375         if (pin) {
7376                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7377                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7378                         snd_hda_codec_write(codec, pin, 0,
7379                                             AC_VERB_SET_AMP_GAIN_MUTE,
7380                                             AMP_OUT_UNMUTE);
7381         }
7382         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7383                 snd_hda_codec_write(codec, dac, 0,
7384                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7385 }
7386
7387 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7388 {
7389         if (pin) {
7390                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7391                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7392                         snd_hda_codec_write(codec, pin, 0,
7393                                             AC_VERB_SET_AMP_GAIN_MUTE,
7394                                             AMP_IN_UNMUTE(0));
7395         }
7396         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7397                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7398                                     AMP_IN_UNMUTE(0));
7399
7400                 /* init to 0 dB and unmute. */
7401                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7402                                          HDA_AMP_VOLMASK, 0x5a);
7403                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7404                                          HDA_AMP_MUTE, 0);
7405         }
7406 }
7407
7408 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7409 {
7410         unsigned int caps;
7411
7412         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7413                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7414         snd_hda_override_amp_caps(codec, nid, dir, caps);
7415 }
7416
7417 /*
7418  * Switch between Digital built-in mic and analog mic.
7419  */
7420 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7421 {
7422         struct ca0132_spec *spec = codec->spec;
7423         unsigned int tmp;
7424         u8 val;
7425         unsigned int oldval;
7426
7427         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7428
7429         oldval = stop_mic1(codec);
7430         ca0132_set_vipsource(codec, 0);
7431         if (enable) {
7432                 /* set DMic input as 2-ch */
7433                 tmp = FLOAT_TWO;
7434                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7435
7436                 val = spec->dmic_ctl;
7437                 val |= 0x80;
7438                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7439                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7440
7441                 if (!(spec->dmic_ctl & 0x20))
7442                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7443         } else {
7444                 /* set AMic input as mono */
7445                 tmp = FLOAT_ONE;
7446                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7447
7448                 val = spec->dmic_ctl;
7449                 /* clear bit7 and bit5 to disable dmic */
7450                 val &= 0x5f;
7451                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7452                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7453
7454                 if (!(spec->dmic_ctl & 0x20))
7455                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7456         }
7457         ca0132_set_vipsource(codec, 1);
7458         resume_mic1(codec, oldval);
7459 }
7460
7461 /*
7462  * Initialization for Digital Mic.
7463  */
7464 static void ca0132_init_dmic(struct hda_codec *codec)
7465 {
7466         struct ca0132_spec *spec = codec->spec;
7467         u8 val;
7468
7469         /* Setup Digital Mic here, but don't enable.
7470          * Enable based on jack detect.
7471          */
7472
7473         /* MCLK uses MPIO1, set to enable.
7474          * Bit 2-0: MPIO select
7475          * Bit   3: set to disable
7476          * Bit 7-4: reserved
7477          */
7478         val = 0x01;
7479         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7480                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7481
7482         /* Data1 uses MPIO3. Data2 not use
7483          * Bit 2-0: Data1 MPIO select
7484          * Bit   3: set disable Data1
7485          * Bit 6-4: Data2 MPIO select
7486          * Bit   7: set disable Data2
7487          */
7488         val = 0x83;
7489         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7490                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
7491
7492         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7493          * Bit 3-0: Channel mask
7494          * Bit   4: set for 48KHz, clear for 32KHz
7495          * Bit   5: mode
7496          * Bit   6: set to select Data2, clear for Data1
7497          * Bit   7: set to enable DMic, clear for AMic
7498          */
7499         if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7500                 val = 0x33;
7501         else
7502                 val = 0x23;
7503         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7504         spec->dmic_ctl = val;
7505         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7506                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
7507 }
7508
7509 /*
7510  * Initialization for Analog Mic 2
7511  */
7512 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7513 {
7514         struct ca0132_spec *spec = codec->spec;
7515
7516         mutex_lock(&spec->chipio_mutex);
7517
7518         chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7519         chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7520
7521         mutex_unlock(&spec->chipio_mutex);
7522 }
7523
7524 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7525 {
7526         struct ca0132_spec *spec = codec->spec;
7527         int i;
7528
7529         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7530         snd_hda_codec_update_widgets(codec);
7531
7532         for (i = 0; i < spec->multiout.num_dacs; i++)
7533                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7534
7535         for (i = 0; i < spec->num_outputs; i++)
7536                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7537
7538         for (i = 0; i < spec->num_inputs; i++) {
7539                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7540                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7541         }
7542 }
7543
7544
7545 /* If there is an active channel for some reason, find it and free it. */
7546 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7547 {
7548         unsigned int i, tmp;
7549         int status;
7550
7551         /* Read active DSPDMAC channel register. */
7552         status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7553         if (status >= 0) {
7554                 /* AND against 0xfff to get the active channel bits. */
7555                 tmp = tmp & 0xfff;
7556
7557                 /* If there are no active channels, nothing to free. */
7558                 if (!tmp)
7559                         return;
7560         } else {
7561                 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7562                                 __func__);
7563                 return;
7564         }
7565
7566         /*
7567          * Check each DSP DMA channel for activity, and if the channel is
7568          * active, free it.
7569          */
7570         for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7571                 if (dsp_is_dma_active(codec, i)) {
7572                         status = dspio_free_dma_chan(codec, i);
7573                         if (status < 0)
7574                                 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7575                                                 __func__, i);
7576                 }
7577         }
7578 }
7579
7580 /*
7581  * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7582  * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7583  * Instead, audio is now routed through the DSP's DMA controllers, which
7584  * the DSP is tasked with setting up itself. Through debugging, it seems the
7585  * cause of most of the no-audio on startup issues were due to improperly
7586  * configured DSP DMA channels.
7587  *
7588  * Normally, the DSP configures these the first time an HDA audio stream is
7589  * started post DSP firmware download. That is why creating a 'dummy' stream
7590  * worked in fixing the audio in some cases. This works most of the time, but
7591  * sometimes if a stream is started/stopped before the DSP can setup the DMA
7592  * configuration registers, it ends up in a broken state. Issues can also
7593  * arise if streams are started in an unusual order, i.e the audio output dma
7594  * channel being sandwiched between the mic1 and mic2 dma channels.
7595  *
7596  * The solution to this is to make sure that the DSP has no DMA channels
7597  * in use post DSP firmware download, and then to manually start each default
7598  * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7599  * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7600  */
7601 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7602 {
7603         static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7604         struct ca0132_spec *spec = codec->spec;
7605         unsigned int i, tmp;
7606
7607         /*
7608          * Check if any of the default streams are active, and if they are,
7609          * stop them.
7610          */
7611         mutex_lock(&spec->chipio_mutex);
7612
7613         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7614                 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7615
7616                 if (tmp) {
7617                         chipio_set_stream_control(codec,
7618                                         dsp_dma_stream_ids[i], 0);
7619                 }
7620         }
7621
7622         mutex_unlock(&spec->chipio_mutex);
7623
7624         /*
7625          * If all DSP streams are inactive, there should be no active DSP DMA
7626          * channels. Check and make sure this is the case, and if it isn't,
7627          * free any active channels.
7628          */
7629         ca0132_alt_free_active_dma_channels(codec);
7630
7631         mutex_lock(&spec->chipio_mutex);
7632
7633         /* Make sure stream 0x0c is six channels. */
7634         chipio_set_stream_channels(codec, 0x0c, 6);
7635
7636         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7637                 chipio_set_stream_control(codec,
7638                                 dsp_dma_stream_ids[i], 1);
7639
7640                 /* Give the DSP some time to setup the DMA channel. */
7641                 msleep(75);
7642         }
7643
7644         mutex_unlock(&spec->chipio_mutex);
7645 }
7646
7647 /*
7648  * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7649  * router', where each entry represents a 48khz audio channel, with a format
7650  * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7651  * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7652  * and 3 if it's using Sample Rate Converter ports.
7653  * An example is:
7654  * 0x0001f8c0
7655  * In this case, f8 is the destination, and c0 is the source. The number value
7656  * is 1.
7657  * This region of memory is normally managed internally by the 8051, where
7658  * the region of exram memory from 0x1477-0x1575 has each byte represent an
7659  * entry within the 0x190000 range, and when a range of entries is in use, the
7660  * ending value is overwritten with 0xff.
7661  * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7662  * streamID's, where each entry is a starting 0x190000 port offset.
7663  * 0x159d in exram is the same as 0x1578, except it contains the ending port
7664  * offset for the corresponding streamID.
7665  *
7666  * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7667  * the 8051, then manually overwritten to remap the ports to work with the
7668  * new DACs.
7669  *
7670  * Currently known portID's:
7671  * 0x00-0x1f: HDA audio stream input/output ports.
7672  * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7673  *            have the lower-nibble set to 0x1, 0x2, and 0x9.
7674  * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7675  * 0xe0-0xff: DAC/ADC audio input/output ports.
7676  *
7677  * Currently known streamID's:
7678  * 0x03: Mic1 ADC to DSP.
7679  * 0x04: Mic2 ADC to DSP.
7680  * 0x05: HDA node 0x02 audio stream to DSP.
7681  * 0x0f: DSP Mic exit to HDA node 0x07.
7682  * 0x0c: DSP processed audio to DACs.
7683  * 0x14: DAC0, front L/R.
7684  *
7685  * It is possible to route the HDA audio streams directly to the DAC and
7686  * bypass the DSP entirely, with the only downside being that since the DSP
7687  * does volume control, the only volume control you'll get is through PCM on
7688  * the PC side, in the same way volume is handled for optical out. This may be
7689  * useful for debugging.
7690  */
7691 static void chipio_remap_stream(struct hda_codec *codec,
7692                 const struct chipio_stream_remap_data *remap_data)
7693 {
7694         unsigned int i, stream_offset;
7695
7696         /* Get the starting port for the stream to be remapped. */
7697         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7698                         &stream_offset);
7699
7700         /*
7701          * Check if the stream's port value is 0xff, because the 8051 may not
7702          * have gotten around to setting up the stream yet. Wait until it's
7703          * setup to remap it's ports.
7704          */
7705         if (stream_offset == 0xff) {
7706                 for (i = 0; i < 5; i++) {
7707                         msleep(25);
7708
7709                         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7710                                         &stream_offset);
7711
7712                         if (stream_offset != 0xff)
7713                                 break;
7714                 }
7715         }
7716
7717         if (stream_offset == 0xff) {
7718                 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7719                                 __func__, remap_data->stream_id);
7720                 return;
7721         }
7722
7723         /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7724         stream_offset *= 0x04;
7725         stream_offset += 0x190000;
7726
7727         for (i = 0; i < remap_data->count; i++) {
7728                 chipio_write_no_mutex(codec,
7729                                 stream_offset + remap_data->offset[i],
7730                                 remap_data->value[i]);
7731         }
7732
7733         /* Update stream map configuration. */
7734         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7735 }
7736
7737 /*
7738  * Default speaker tuning values setup for alternative codecs.
7739  */
7740 static const unsigned int sbz_default_delay_values[] = {
7741         /* Non-zero values are floating point 0.000198. */
7742         0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7743 };
7744
7745 static const unsigned int zxr_default_delay_values[] = {
7746         /* Non-zero values are floating point 0.000220. */
7747         0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7748 };
7749
7750 static const unsigned int ae5_default_delay_values[] = {
7751         /* Non-zero values are floating point 0.000100. */
7752         0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7753 };
7754
7755 /*
7756  * If we never change these, probably only need them on initialization.
7757  */
7758 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7759 {
7760         struct ca0132_spec *spec = codec->spec;
7761         unsigned int i, tmp, start_req, end_req;
7762         const unsigned int *values;
7763
7764         switch (ca0132_quirk(spec)) {
7765         case QUIRK_SBZ:
7766                 values = sbz_default_delay_values;
7767                 break;
7768         case QUIRK_ZXR:
7769                 values = zxr_default_delay_values;
7770                 break;
7771         case QUIRK_AE5:
7772         case QUIRK_AE7:
7773                 values = ae5_default_delay_values;
7774                 break;
7775         default:
7776                 values = sbz_default_delay_values;
7777                 break;
7778         }
7779
7780         tmp = FLOAT_ZERO;
7781         dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7782
7783         start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7784         end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7785         for (i = start_req; i < end_req + 1; i++)
7786                 dspio_set_uint_param(codec, 0x96, i, tmp);
7787
7788         start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7789         end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7790         for (i = start_req; i < end_req + 1; i++)
7791                 dspio_set_uint_param(codec, 0x96, i, tmp);
7792
7793
7794         for (i = 0; i < 6; i++)
7795                 dspio_set_uint_param(codec, 0x96,
7796                                 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7797 }
7798
7799 /*
7800  * Initialize mic for non-chromebook ca0132 implementations.
7801  */
7802 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7803 {
7804         struct ca0132_spec *spec = codec->spec;
7805         unsigned int tmp;
7806
7807         /* Mic 1 Setup */
7808         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7809         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7810         if (ca0132_quirk(spec) == QUIRK_R3DI) {
7811                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7812                 tmp = FLOAT_ONE;
7813         } else
7814                 tmp = FLOAT_THREE;
7815         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7816
7817         /* Mic 2 setup (not present on desktop cards) */
7818         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7819         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7820         if (ca0132_quirk(spec) == QUIRK_R3DI)
7821                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7822         tmp = FLOAT_ZERO;
7823         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7824 }
7825
7826 /*
7827  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7828  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7829  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7830  * having an updated DAC, which changes the destination to that DAC.
7831  */
7832 static void sbz_connect_streams(struct hda_codec *codec)
7833 {
7834         struct ca0132_spec *spec = codec->spec;
7835
7836         mutex_lock(&spec->chipio_mutex);
7837
7838         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7839
7840         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7841         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7842
7843         /* Setup stream 0x14 with it's source and destination points */
7844         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7845         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7846         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7847         chipio_set_stream_channels(codec, 0x14, 2);
7848         chipio_set_stream_control(codec, 0x14, 1);
7849
7850         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7851
7852         mutex_unlock(&spec->chipio_mutex);
7853 }
7854
7855 /*
7856  * Write data through ChipIO to setup proper stream destinations.
7857  * Not sure how it exactly works, but it seems to direct data
7858  * to different destinations. Example is f8 to c0, e0 to c0.
7859  * All I know is, if you don't set these, you get no sound.
7860  */
7861 static void sbz_chipio_startup_data(struct hda_codec *codec)
7862 {
7863         const struct chipio_stream_remap_data *dsp_out_remap_data;
7864         struct ca0132_spec *spec = codec->spec;
7865
7866         mutex_lock(&spec->chipio_mutex);
7867         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7868
7869         /* Remap DAC0's output ports. */
7870         chipio_remap_stream(codec, &stream_remap_data[0]);
7871
7872         /* Remap DSP audio output stream ports. */
7873         switch (ca0132_quirk(spec)) {
7874         case QUIRK_SBZ:
7875                 dsp_out_remap_data = &stream_remap_data[1];
7876                 break;
7877
7878         case QUIRK_ZXR:
7879                 dsp_out_remap_data = &stream_remap_data[2];
7880                 break;
7881
7882         default:
7883                 dsp_out_remap_data = NULL;
7884                 break;
7885         }
7886
7887         if (dsp_out_remap_data)
7888                 chipio_remap_stream(codec, dsp_out_remap_data);
7889
7890         codec_dbg(codec, "Startup Data exited, mutex released.\n");
7891         mutex_unlock(&spec->chipio_mutex);
7892 }
7893
7894 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7895 {
7896         struct ca0132_spec *spec = codec->spec;
7897         unsigned int tmp;
7898
7899         chipio_set_stream_control(codec, 0x03, 0);
7900         chipio_set_stream_control(codec, 0x04, 0);
7901
7902         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7903         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7904
7905         tmp = FLOAT_THREE;
7906         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7907
7908         chipio_set_stream_control(codec, 0x03, 1);
7909         chipio_set_stream_control(codec, 0x04, 1);
7910
7911         switch (ca0132_quirk(spec)) {
7912         case QUIRK_SBZ:
7913                 chipio_write(codec, 0x18b098, 0x0000000c);
7914                 chipio_write(codec, 0x18b09C, 0x0000000c);
7915                 break;
7916         case QUIRK_AE5:
7917                 chipio_write(codec, 0x18b098, 0x0000000c);
7918                 chipio_write(codec, 0x18b09c, 0x0000004c);
7919                 break;
7920         default:
7921                 break;
7922         }
7923 }
7924
7925 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7926 {
7927         struct ca0132_spec *spec = codec->spec;
7928
7929         chipio_8051_write_direct(codec, 0x93, 0x10);
7930         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7931
7932         writeb(0xff, spec->mem_base + 0x304);
7933         writeb(0xff, spec->mem_base + 0x304);
7934         writeb(0xff, spec->mem_base + 0x304);
7935         writeb(0xff, spec->mem_base + 0x304);
7936         writeb(0x00, spec->mem_base + 0x100);
7937         writeb(0xff, spec->mem_base + 0x304);
7938         writeb(0x00, spec->mem_base + 0x100);
7939         writeb(0xff, spec->mem_base + 0x304);
7940         writeb(0x00, spec->mem_base + 0x100);
7941         writeb(0xff, spec->mem_base + 0x304);
7942         writeb(0x00, spec->mem_base + 0x100);
7943         writeb(0xff, spec->mem_base + 0x304);
7944
7945         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7946         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7947         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7948 }
7949
7950 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7951 {
7952         /*
7953          * Param3 in the 8051's memory is represented by the ascii string 'mch'
7954          * which seems to be 'multichannel'. This is also mentioned in the
7955          * AE-5's registry values in Windows.
7956          */
7957         chipio_set_control_param(codec, 3, 0);
7958         /*
7959          * I believe ASI is 'audio serial interface' and that it's used to
7960          * change colors on the external LED strip connected to the AE-5.
7961          */
7962         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7963
7964         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7965         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7966
7967         chipio_8051_write_exram(codec, 0xfa92, 0x22);
7968 }
7969
7970 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7971 {
7972         chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7973         chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7974         chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7975         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7976         chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7977 }
7978
7979 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7980 {
7981         struct ca0132_spec *spec = codec->spec;
7982
7983         mutex_lock(&spec->chipio_mutex);
7984
7985         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7986
7987         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7988
7989         chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7990
7991         chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7992         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7993         chipio_set_stream_channels(codec, 0x18, 6);
7994         chipio_set_stream_control(codec, 0x18, 1);
7995
7996         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7997
7998         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7999
8000         ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
8001
8002         mutex_unlock(&spec->chipio_mutex);
8003 }
8004
8005 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8006 {
8007         struct ca0132_spec *spec = codec->spec;
8008
8009         mutex_lock(&spec->chipio_mutex);
8010
8011         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8012         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8013         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8014         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8015
8016         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8017         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8018         ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8019         ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8020         ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8021         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8022         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8023         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8024         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8025         ca0113_mmio_gpio_set(codec, 0, true);
8026         ca0113_mmio_gpio_set(codec, 1, true);
8027         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8028
8029         chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8030
8031         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8032         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8033
8034         mutex_unlock(&spec->chipio_mutex);
8035 }
8036
8037 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8038 {
8039         struct ca0132_spec *spec = codec->spec;
8040
8041         mutex_lock(&spec->chipio_mutex);
8042
8043         /* Seems to share the same port remapping as the SBZ. */
8044         chipio_remap_stream(codec, &stream_remap_data[1]);
8045
8046         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8047         ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8048         ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8049         ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8050         ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8051         ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8052         ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8053         ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8054
8055         mutex_unlock(&spec->chipio_mutex);
8056 }
8057
8058 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8059 {
8060         struct ca0132_spec *spec = codec->spec;
8061
8062         mutex_lock(&spec->chipio_mutex);
8063
8064         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8065         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8066
8067         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8068
8069         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8070         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8071
8072         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8073         chipio_set_stream_channels(codec, 0x18, 6);
8074         chipio_set_stream_control(codec, 0x18, 1);
8075
8076         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8077
8078         mutex_unlock(&spec->chipio_mutex);
8079 }
8080
8081 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8082 {
8083         static const unsigned int addr[] = {
8084                 0x41, 0x45, 0x40, 0x43, 0x51
8085         };
8086         static const unsigned int data[] = {
8087                 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8088         };
8089         unsigned int i;
8090
8091         for (i = 0; i < ARRAY_SIZE(addr); i++)
8092                 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8093 }
8094
8095 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8096 {
8097         struct ca0132_spec *spec = codec->spec;
8098         static const unsigned int target[] = {
8099                 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8100         };
8101         static const unsigned int data[] = {
8102                 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8103         };
8104         unsigned int i;
8105
8106         mutex_lock(&spec->chipio_mutex);
8107
8108         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8109
8110         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8111         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8112         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8113         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8114
8115         ae7_post_dsp_pll_setup(codec);
8116         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8117
8118         for (i = 0; i < ARRAY_SIZE(target); i++)
8119                 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8120
8121         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8122         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8123         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8124
8125         chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8126         chipio_set_stream_channels(codec, 0x21, 2);
8127         chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8128
8129         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8130         /*
8131          * In the 8051's memory, this param is referred to as 'n2sid', which I
8132          * believe is 'node to streamID'. It seems to be a way to assign a
8133          * stream to a given HDA node.
8134          */
8135         chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8136
8137         chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8138
8139         /*
8140          * Now, at this point on Windows, an actual stream is setup and
8141          * seemingly sends data to the HDA node 0x09, which is the digital
8142          * audio input node. This is left out here, because obviously I don't
8143          * know what data is being sent. Interestingly, the AE-5 seems to go
8144          * through the motions of getting here and never actually takes this
8145          * step, but the AE-7 does.
8146          */
8147
8148         ca0113_mmio_gpio_set(codec, 0, 1);
8149         ca0113_mmio_gpio_set(codec, 1, 1);
8150
8151         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8152         chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8153         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8154         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8155
8156         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8157         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8158
8159         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8160         chipio_set_stream_channels(codec, 0x18, 6);
8161
8162         /*
8163          * Runs again, this has been repeated a few times, but I'm just
8164          * following what the Windows driver does.
8165          */
8166         ae7_post_dsp_pll_setup(codec);
8167         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8168
8169         mutex_unlock(&spec->chipio_mutex);
8170 }
8171
8172 /*
8173  * The Windows driver has commands that seem to setup ASI, which I believe to
8174  * be some sort of audio serial interface. My current speculation is that it's
8175  * related to communicating with the new DAC.
8176  */
8177 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8178 {
8179         chipio_8051_write_direct(codec, 0x93, 0x10);
8180
8181         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8182
8183         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8184         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8185
8186         chipio_set_control_param(codec, 3, 3);
8187         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8188
8189         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8190         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8191         snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8192
8193         chipio_8051_write_exram(codec, 0xfa92, 0x22);
8194
8195         ae7_post_dsp_pll_setup(codec);
8196         ae7_post_dsp_asi_stream_setup(codec);
8197
8198         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8199
8200         ae7_post_dsp_asi_setup_ports(codec);
8201 }
8202
8203 /*
8204  * Setup default parameters for DSP
8205  */
8206 static void ca0132_setup_defaults(struct hda_codec *codec)
8207 {
8208         struct ca0132_spec *spec = codec->spec;
8209         unsigned int tmp;
8210         int num_fx;
8211         int idx, i;
8212
8213         if (spec->dsp_state != DSP_DOWNLOADED)
8214                 return;
8215
8216         /* out, in effects + voicefx */
8217         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8218         for (idx = 0; idx < num_fx; idx++) {
8219                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8220                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8221                                              ca0132_effects[idx].reqs[i],
8222                                              ca0132_effects[idx].def_vals[i]);
8223                 }
8224         }
8225
8226         /*remove DSP headroom*/
8227         tmp = FLOAT_ZERO;
8228         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8229
8230         /*set speaker EQ bypass attenuation*/
8231         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8232
8233         /* set AMic1 and AMic2 as mono mic */
8234         tmp = FLOAT_ONE;
8235         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8236         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8237
8238         /* set AMic1 as CrystalVoice input */
8239         tmp = FLOAT_ONE;
8240         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8241
8242         /* set WUH source */
8243         tmp = FLOAT_TWO;
8244         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8245 }
8246
8247 /*
8248  * Setup default parameters for Recon3D/Recon3Di DSP.
8249  */
8250
8251 static void r3d_setup_defaults(struct hda_codec *codec)
8252 {
8253         struct ca0132_spec *spec = codec->spec;
8254         unsigned int tmp;
8255         int num_fx;
8256         int idx, i;
8257
8258         if (spec->dsp_state != DSP_DOWNLOADED)
8259                 return;
8260
8261         ca0132_alt_init_analog_mics(codec);
8262         ca0132_alt_start_dsp_audio_streams(codec);
8263
8264         /*remove DSP headroom*/
8265         tmp = FLOAT_ZERO;
8266         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8267
8268         /* set WUH source */
8269         tmp = FLOAT_TWO;
8270         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8271         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8272
8273         /* Set speaker source? */
8274         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8275
8276         if (ca0132_quirk(spec) == QUIRK_R3DI)
8277                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8278
8279         /* Disable mute on Center/LFE. */
8280         if (ca0132_quirk(spec) == QUIRK_R3D) {
8281                 ca0113_mmio_gpio_set(codec, 2, false);
8282                 ca0113_mmio_gpio_set(codec, 4, true);
8283         }
8284
8285         /* Setup effect defaults */
8286         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8287         for (idx = 0; idx < num_fx; idx++) {
8288                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8289                         dspio_set_uint_param(codec,
8290                                         ca0132_effects[idx].mid,
8291                                         ca0132_effects[idx].reqs[i],
8292                                         ca0132_effects[idx].def_vals[i]);
8293                 }
8294         }
8295 }
8296
8297 /*
8298  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8299  * than the Chromebook setup.
8300  */
8301 static void sbz_setup_defaults(struct hda_codec *codec)
8302 {
8303         struct ca0132_spec *spec = codec->spec;
8304         unsigned int tmp;
8305         int num_fx;
8306         int idx, i;
8307
8308         if (spec->dsp_state != DSP_DOWNLOADED)
8309                 return;
8310
8311         ca0132_alt_init_analog_mics(codec);
8312         ca0132_alt_start_dsp_audio_streams(codec);
8313         sbz_connect_streams(codec);
8314         sbz_chipio_startup_data(codec);
8315
8316         /*
8317          * Sets internal input loopback to off, used to have a switch to
8318          * enable input loopback, but turned out to be way too buggy.
8319          */
8320         tmp = FLOAT_ONE;
8321         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8322         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8323
8324         /*remove DSP headroom*/
8325         tmp = FLOAT_ZERO;
8326         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8327
8328         /* set WUH source */
8329         tmp = FLOAT_TWO;
8330         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8331         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8332
8333         /* Set speaker source? */
8334         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8335
8336         ca0132_alt_dsp_initial_mic_setup(codec);
8337
8338         /* out, in effects + voicefx */
8339         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8340         for (idx = 0; idx < num_fx; idx++) {
8341                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8342                         dspio_set_uint_param(codec,
8343                                         ca0132_effects[idx].mid,
8344                                         ca0132_effects[idx].reqs[i],
8345                                         ca0132_effects[idx].def_vals[i]);
8346                 }
8347         }
8348
8349         ca0132_alt_init_speaker_tuning(codec);
8350 }
8351
8352 /*
8353  * Setup default parameters for the Sound BlasterX AE-5 DSP.
8354  */
8355 static void ae5_setup_defaults(struct hda_codec *codec)
8356 {
8357         struct ca0132_spec *spec = codec->spec;
8358         unsigned int tmp;
8359         int num_fx;
8360         int idx, i;
8361
8362         if (spec->dsp_state != DSP_DOWNLOADED)
8363                 return;
8364
8365         ca0132_alt_init_analog_mics(codec);
8366         ca0132_alt_start_dsp_audio_streams(codec);
8367
8368         /* New, unknown SCP req's */
8369         tmp = FLOAT_ZERO;
8370         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8371         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8372         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8373         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8374
8375         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8376         ca0113_mmio_gpio_set(codec, 0, false);
8377         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8378
8379         /* Internal loopback off */
8380         tmp = FLOAT_ONE;
8381         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8382         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8383
8384         /*remove DSP headroom*/
8385         tmp = FLOAT_ZERO;
8386         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8387
8388         /* set WUH source */
8389         tmp = FLOAT_TWO;
8390         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8391         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8392
8393         /* Set speaker source? */
8394         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8395
8396         ca0132_alt_dsp_initial_mic_setup(codec);
8397         ae5_post_dsp_register_set(codec);
8398         ae5_post_dsp_param_setup(codec);
8399         ae5_post_dsp_pll_setup(codec);
8400         ae5_post_dsp_stream_setup(codec);
8401         ae5_post_dsp_startup_data(codec);
8402
8403         /* out, in effects + voicefx */
8404         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8405         for (idx = 0; idx < num_fx; idx++) {
8406                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8407                         dspio_set_uint_param(codec,
8408                                         ca0132_effects[idx].mid,
8409                                         ca0132_effects[idx].reqs[i],
8410                                         ca0132_effects[idx].def_vals[i]);
8411                 }
8412         }
8413
8414         ca0132_alt_init_speaker_tuning(codec);
8415 }
8416
8417 /*
8418  * Setup default parameters for the Sound Blaster AE-7 DSP.
8419  */
8420 static void ae7_setup_defaults(struct hda_codec *codec)
8421 {
8422         struct ca0132_spec *spec = codec->spec;
8423         unsigned int tmp;
8424         int num_fx;
8425         int idx, i;
8426
8427         if (spec->dsp_state != DSP_DOWNLOADED)
8428                 return;
8429
8430         ca0132_alt_init_analog_mics(codec);
8431         ca0132_alt_start_dsp_audio_streams(codec);
8432         ae7_post_dsp_setup_ports(codec);
8433
8434         tmp = FLOAT_ZERO;
8435         dspio_set_uint_param(codec, 0x96,
8436                         SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8437         dspio_set_uint_param(codec, 0x96,
8438                         SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8439
8440         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8441
8442         /* New, unknown SCP req's */
8443         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8444         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8445
8446         ca0113_mmio_gpio_set(codec, 0, false);
8447
8448         /* Internal loopback off */
8449         tmp = FLOAT_ONE;
8450         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8451         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8452
8453         /*remove DSP headroom*/
8454         tmp = FLOAT_ZERO;
8455         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8456
8457         /* set WUH source */
8458         tmp = FLOAT_TWO;
8459         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8460         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8461
8462         /* Set speaker source? */
8463         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8464         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8465
8466         /*
8467          * This is the second time we've called this, but this is seemingly
8468          * what Windows does.
8469          */
8470         ca0132_alt_init_analog_mics(codec);
8471
8472         ae7_post_dsp_asi_setup(codec);
8473
8474         /*
8475          * Not sure why, but these are both set to 1. They're only set to 0
8476          * upon shutdown.
8477          */
8478         ca0113_mmio_gpio_set(codec, 0, true);
8479         ca0113_mmio_gpio_set(codec, 1, true);
8480
8481         /* Volume control related. */
8482         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8483         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8484         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8485
8486         /* out, in effects + voicefx */
8487         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8488         for (idx = 0; idx < num_fx; idx++) {
8489                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8490                         dspio_set_uint_param(codec,
8491                                         ca0132_effects[idx].mid,
8492                                         ca0132_effects[idx].reqs[i],
8493                                         ca0132_effects[idx].def_vals[i]);
8494                 }
8495         }
8496
8497         ca0132_alt_init_speaker_tuning(codec);
8498 }
8499
8500 /*
8501  * Initialization of flags in chip
8502  */
8503 static void ca0132_init_flags(struct hda_codec *codec)
8504 {
8505         struct ca0132_spec *spec = codec->spec;
8506
8507         if (ca0132_use_alt_functions(spec)) {
8508                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8509                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8510                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8511                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8512                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8513                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8514                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8515                 chipio_set_control_flag(codec,
8516                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8517                 chipio_set_control_flag(codec,
8518                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8519         } else {
8520                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8521                 chipio_set_control_flag(codec,
8522                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8523                 chipio_set_control_flag(codec,
8524                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8525                 chipio_set_control_flag(codec,
8526                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8527                 chipio_set_control_flag(codec,
8528                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8529                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8530         }
8531 }
8532
8533 /*
8534  * Initialization of parameters in chip
8535  */
8536 static void ca0132_init_params(struct hda_codec *codec)
8537 {
8538         struct ca0132_spec *spec = codec->spec;
8539
8540         if (ca0132_use_alt_functions(spec)) {
8541                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8542                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8543                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8544                 chipio_set_control_param(codec, 0, 0);
8545                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8546         }
8547
8548         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8549         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8550 }
8551
8552 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8553 {
8554         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8555         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8556         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8557         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8558         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8559         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8560
8561         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8562         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8563         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8564 }
8565
8566 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8567 {
8568         bool dsp_loaded = false;
8569         struct ca0132_spec *spec = codec->spec;
8570         const struct dsp_image_seg *dsp_os_image;
8571         const struct firmware *fw_entry = NULL;
8572         /*
8573          * Alternate firmwares for different variants. The Recon3Di apparently
8574          * can use the default firmware, but I'll leave the option in case
8575          * it needs it again.
8576          */
8577         switch (ca0132_quirk(spec)) {
8578         case QUIRK_SBZ:
8579         case QUIRK_R3D:
8580         case QUIRK_AE5:
8581                 if (reject_firmware(&fw_entry, DESKTOP_EFX_FILE,
8582                                         codec->card->dev) != 0)
8583                         codec_dbg(codec, "Desktop firmware not found.");
8584                 else
8585                         codec_dbg(codec, "Desktop firmware selected.");
8586                 break;
8587         case QUIRK_R3DI:
8588                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
8589                                         codec->card->dev) != 0)
8590                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
8591                 else
8592                         codec_dbg(codec, "Recon3Di firmware selected.");
8593                 break;
8594         default:
8595                 break;
8596         }
8597 /*(DEBLOBBED)*/
8598         if (!fw_entry) {
8599                 codec_dbg(codec, "Default firmware selected.");
8600                 if (reject_firmware(&fw_entry, EFX_FILE,
8601                                         codec->card->dev) != 0)
8602                         return false;
8603         }
8604
8605         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8606         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8607                 codec_err(codec, "ca0132 DSP load image failed\n");
8608                 goto exit_download;
8609         }
8610
8611         dsp_loaded = dspload_wait_loaded(codec);
8612
8613 exit_download:
8614         release_firmware(fw_entry);
8615
8616         return dsp_loaded;
8617 }
8618
8619 static void ca0132_download_dsp(struct hda_codec *codec)
8620 {
8621         struct ca0132_spec *spec = codec->spec;
8622
8623 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8624         return; /* NOP */
8625 #endif
8626
8627         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8628                 return; /* don't retry failures */
8629
8630         chipio_enable_clocks(codec);
8631         if (spec->dsp_state != DSP_DOWNLOADED) {
8632                 spec->dsp_state = DSP_DOWNLOADING;
8633
8634                 if (!ca0132_download_dsp_images(codec))
8635                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
8636                 else
8637                         spec->dsp_state = DSP_DOWNLOADED;
8638         }
8639
8640         /* For codecs using alt functions, this is already done earlier */
8641         if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8642                 ca0132_set_dsp_msr(codec, true);
8643 }
8644
8645 static void ca0132_process_dsp_response(struct hda_codec *codec,
8646                                         struct hda_jack_callback *callback)
8647 {
8648         struct ca0132_spec *spec = codec->spec;
8649
8650         codec_dbg(codec, "ca0132_process_dsp_response\n");
8651         snd_hda_power_up_pm(codec);
8652         if (spec->wait_scp) {
8653                 if (dspio_get_response_data(codec) >= 0)
8654                         spec->wait_scp = 0;
8655         }
8656
8657         dspio_clear_response_queue(codec);
8658         snd_hda_power_down_pm(codec);
8659 }
8660
8661 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8662 {
8663         struct ca0132_spec *spec = codec->spec;
8664         struct hda_jack_tbl *tbl;
8665
8666         /* Delay enabling the HP amp, to let the mic-detection
8667          * state machine run.
8668          */
8669         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8670         if (tbl)
8671                 tbl->block_report = 1;
8672         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8673 }
8674
8675 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8676 {
8677         struct ca0132_spec *spec = codec->spec;
8678
8679         if (ca0132_use_alt_functions(spec))
8680                 ca0132_alt_select_in(codec);
8681         else
8682                 ca0132_select_mic(codec);
8683 }
8684
8685 static void ca0132_setup_unsol(struct hda_codec *codec)
8686 {
8687         struct ca0132_spec *spec = codec->spec;
8688         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8689         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8690                                             amic_callback);
8691         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8692                                             ca0132_process_dsp_response);
8693         /* Front headphone jack detection */
8694         if (ca0132_use_alt_functions(spec))
8695                 snd_hda_jack_detect_enable_callback(codec,
8696                         spec->unsol_tag_front_hp, hp_callback);
8697 }
8698
8699 /*
8700  * Verbs tables.
8701  */
8702
8703 /* Sends before DSP download. */
8704 static const struct hda_verb ca0132_base_init_verbs[] = {
8705         /*enable ct extension*/
8706         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8707         {}
8708 };
8709
8710 /* Send at exit. */
8711 static const struct hda_verb ca0132_base_exit_verbs[] = {
8712         /*set afg to D3*/
8713         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8714         /*disable ct extension*/
8715         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8716         {}
8717 };
8718
8719 /* Other verbs tables. Sends after DSP download. */
8720
8721 static const struct hda_verb ca0132_init_verbs0[] = {
8722         /* chip init verbs */
8723         {0x15, 0x70D, 0xF0},
8724         {0x15, 0x70E, 0xFE},
8725         {0x15, 0x707, 0x75},
8726         {0x15, 0x707, 0xD3},
8727         {0x15, 0x707, 0x09},
8728         {0x15, 0x707, 0x53},
8729         {0x15, 0x707, 0xD4},
8730         {0x15, 0x707, 0xEF},
8731         {0x15, 0x707, 0x75},
8732         {0x15, 0x707, 0xD3},
8733         {0x15, 0x707, 0x09},
8734         {0x15, 0x707, 0x02},
8735         {0x15, 0x707, 0x37},
8736         {0x15, 0x707, 0x78},
8737         {0x15, 0x53C, 0xCE},
8738         {0x15, 0x575, 0xC9},
8739         {0x15, 0x53D, 0xCE},
8740         {0x15, 0x5B7, 0xC9},
8741         {0x15, 0x70D, 0xE8},
8742         {0x15, 0x70E, 0xFE},
8743         {0x15, 0x707, 0x02},
8744         {0x15, 0x707, 0x68},
8745         {0x15, 0x707, 0x62},
8746         {0x15, 0x53A, 0xCE},
8747         {0x15, 0x546, 0xC9},
8748         {0x15, 0x53B, 0xCE},
8749         {0x15, 0x5E8, 0xC9},
8750         {}
8751 };
8752
8753 /* Extra init verbs for desktop cards. */
8754 static const struct hda_verb ca0132_init_verbs1[] = {
8755         {0x15, 0x70D, 0x20},
8756         {0x15, 0x70E, 0x19},
8757         {0x15, 0x707, 0x00},
8758         {0x15, 0x539, 0xCE},
8759         {0x15, 0x546, 0xC9},
8760         {0x15, 0x70D, 0xB7},
8761         {0x15, 0x70E, 0x09},
8762         {0x15, 0x707, 0x10},
8763         {0x15, 0x70D, 0xAF},
8764         {0x15, 0x70E, 0x09},
8765         {0x15, 0x707, 0x01},
8766         {0x15, 0x707, 0x05},
8767         {0x15, 0x70D, 0x73},
8768         {0x15, 0x70E, 0x09},
8769         {0x15, 0x707, 0x14},
8770         {0x15, 0x6FF, 0xC4},
8771         {}
8772 };
8773
8774 static void ca0132_init_chip(struct hda_codec *codec)
8775 {
8776         struct ca0132_spec *spec = codec->spec;
8777         int num_fx;
8778         int i;
8779         unsigned int on;
8780
8781         mutex_init(&spec->chipio_mutex);
8782
8783         /*
8784          * The Windows driver always does this upon startup, which seems to
8785          * clear out any previous configuration. This should help issues where
8786          * a boot into Windows prior to a boot into Linux breaks things. Also,
8787          * Windows always sends the reset twice.
8788          */
8789         if (ca0132_use_alt_functions(spec)) {
8790                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8791                 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8792
8793                 snd_hda_codec_write(codec, codec->core.afg, 0,
8794                             AC_VERB_SET_CODEC_RESET, 0);
8795                 snd_hda_codec_write(codec, codec->core.afg, 0,
8796                             AC_VERB_SET_CODEC_RESET, 0);
8797         }
8798
8799         spec->cur_out_type = SPEAKER_OUT;
8800         if (!ca0132_use_alt_functions(spec))
8801                 spec->cur_mic_type = DIGITAL_MIC;
8802         else
8803                 spec->cur_mic_type = REAR_MIC;
8804
8805         spec->cur_mic_boost = 0;
8806
8807         for (i = 0; i < VNODES_COUNT; i++) {
8808                 spec->vnode_lvol[i] = 0x5a;
8809                 spec->vnode_rvol[i] = 0x5a;
8810                 spec->vnode_lswitch[i] = 0;
8811                 spec->vnode_rswitch[i] = 0;
8812         }
8813
8814         /*
8815          * Default states for effects are in ca0132_effects[].
8816          */
8817         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8818         for (i = 0; i < num_fx; i++) {
8819                 on = (unsigned int)ca0132_effects[i].reqs[0];
8820                 spec->effects_switch[i] = on ? 1 : 0;
8821         }
8822         /*
8823          * Sets defaults for the effect slider controls, only for alternative
8824          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8825          */
8826         if (ca0132_use_alt_controls(spec)) {
8827                 /* Set speakers to default to full range. */
8828                 spec->speaker_range_val[0] = 1;
8829                 spec->speaker_range_val[1] = 1;
8830
8831                 spec->xbass_xover_freq = 8;
8832                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8833                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
8834
8835                 spec->bass_redirect_xover_freq = 8;
8836         }
8837
8838         spec->voicefx_val = 0;
8839         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8840         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8841
8842         /*
8843          * The ZxR doesn't have a front panel header, and it's line-in is on
8844          * the daughter board. So, there is no input enum control, and we need
8845          * to make sure that spec->in_enum_val is set properly.
8846          */
8847         if (ca0132_quirk(spec) == QUIRK_ZXR)
8848                 spec->in_enum_val = REAR_MIC;
8849
8850 #ifdef ENABLE_TUNING_CONTROLS
8851         ca0132_init_tuning_defaults(codec);
8852 #endif
8853 }
8854
8855 /*
8856  * Recon3Di exit specific commands.
8857  */
8858 /* prevents popping noise on shutdown */
8859 static void r3di_gpio_shutdown(struct hda_codec *codec)
8860 {
8861         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8862 }
8863
8864 /*
8865  * Sound Blaster Z exit specific commands.
8866  */
8867 static void sbz_region2_exit(struct hda_codec *codec)
8868 {
8869         struct ca0132_spec *spec = codec->spec;
8870         unsigned int i;
8871
8872         for (i = 0; i < 4; i++)
8873                 writeb(0x0, spec->mem_base + 0x100);
8874         for (i = 0; i < 8; i++)
8875                 writeb(0xb3, spec->mem_base + 0x304);
8876
8877         ca0113_mmio_gpio_set(codec, 0, false);
8878         ca0113_mmio_gpio_set(codec, 1, false);
8879         ca0113_mmio_gpio_set(codec, 4, true);
8880         ca0113_mmio_gpio_set(codec, 5, false);
8881         ca0113_mmio_gpio_set(codec, 7, false);
8882 }
8883
8884 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8885 {
8886         static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8887         unsigned int i;
8888
8889         snd_hda_codec_write(codec, 0x11, 0,
8890                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8891
8892         for (i = 0; i < ARRAY_SIZE(pins); i++)
8893                 snd_hda_codec_write(codec, pins[i], 0,
8894                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8895 }
8896
8897 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8898 {
8899         static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8900         unsigned int i;
8901
8902         for (i = 0; i < ARRAY_SIZE(pins); i++) {
8903                 snd_hda_codec_write(codec, pins[i], 0,
8904                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8905         }
8906 }
8907
8908 /* On shutdown, sends commands in sets of three */
8909 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8910                                                         int mask, int data)
8911 {
8912         if (dir >= 0)
8913                 snd_hda_codec_write(codec, 0x01, 0,
8914                                 AC_VERB_SET_GPIO_DIRECTION, dir);
8915         if (mask >= 0)
8916                 snd_hda_codec_write(codec, 0x01, 0,
8917                                 AC_VERB_SET_GPIO_MASK, mask);
8918
8919         if (data >= 0)
8920                 snd_hda_codec_write(codec, 0x01, 0,
8921                                 AC_VERB_SET_GPIO_DATA, data);
8922 }
8923
8924 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8925 {
8926         static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8927         unsigned int i;
8928
8929         for (i = 0; i < ARRAY_SIZE(pins); i++)
8930                 snd_hda_codec_write(codec, pins[i], 0,
8931                                 AC_VERB_SET_POWER_STATE, 0x03);
8932 }
8933
8934 static void sbz_exit_chip(struct hda_codec *codec)
8935 {
8936         chipio_set_stream_control(codec, 0x03, 0);
8937         chipio_set_stream_control(codec, 0x04, 0);
8938
8939         /* Mess with GPIO */
8940         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8941         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8942         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8943
8944         chipio_set_stream_control(codec, 0x14, 0);
8945         chipio_set_stream_control(codec, 0x0C, 0);
8946
8947         chipio_set_conn_rate(codec, 0x41, SR_192_000);
8948         chipio_set_conn_rate(codec, 0x91, SR_192_000);
8949
8950         chipio_write(codec, 0x18a020, 0x00000083);
8951
8952         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8953         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8954         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8955
8956         chipio_set_stream_control(codec, 0x0C, 0);
8957
8958         chipio_set_control_param(codec, 0x0D, 0x24);
8959
8960         ca0132_clear_unsolicited(codec);
8961         sbz_set_pin_ctl_default(codec);
8962
8963         snd_hda_codec_write(codec, 0x0B, 0,
8964                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8965
8966         sbz_region2_exit(codec);
8967 }
8968
8969 static void r3d_exit_chip(struct hda_codec *codec)
8970 {
8971         ca0132_clear_unsolicited(codec);
8972         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8973         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8974 }
8975
8976 static void ae5_exit_chip(struct hda_codec *codec)
8977 {
8978         chipio_set_stream_control(codec, 0x03, 0);
8979         chipio_set_stream_control(codec, 0x04, 0);
8980
8981         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8982         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8983         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8984         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8985         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8986         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8987         ca0113_mmio_gpio_set(codec, 0, false);
8988         ca0113_mmio_gpio_set(codec, 1, false);
8989
8990         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8991         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8992
8993         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8994
8995         chipio_set_stream_control(codec, 0x18, 0);
8996         chipio_set_stream_control(codec, 0x0c, 0);
8997
8998         snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8999 }
9000
9001 static void ae7_exit_chip(struct hda_codec *codec)
9002 {
9003         chipio_set_stream_control(codec, 0x18, 0);
9004         chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9005         chipio_set_stream_channels(codec, 0x21, 0);
9006         chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9007         chipio_set_control_param(codec, 0x20, 0x01);
9008
9009         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9010
9011         chipio_set_stream_control(codec, 0x18, 0);
9012         chipio_set_stream_control(codec, 0x0c, 0);
9013
9014         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9015         snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9016         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9017         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9018         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9019         ca0113_mmio_gpio_set(codec, 0, false);
9020         ca0113_mmio_gpio_set(codec, 1, false);
9021         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9022
9023         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9024         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9025 }
9026
9027 static void zxr_exit_chip(struct hda_codec *codec)
9028 {
9029         chipio_set_stream_control(codec, 0x03, 0);
9030         chipio_set_stream_control(codec, 0x04, 0);
9031         chipio_set_stream_control(codec, 0x14, 0);
9032         chipio_set_stream_control(codec, 0x0C, 0);
9033
9034         chipio_set_conn_rate(codec, 0x41, SR_192_000);
9035         chipio_set_conn_rate(codec, 0x91, SR_192_000);
9036
9037         chipio_write(codec, 0x18a020, 0x00000083);
9038
9039         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9040         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9041
9042         ca0132_clear_unsolicited(codec);
9043         sbz_set_pin_ctl_default(codec);
9044         snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9045
9046         ca0113_mmio_gpio_set(codec, 5, false);
9047         ca0113_mmio_gpio_set(codec, 2, false);
9048         ca0113_mmio_gpio_set(codec, 3, false);
9049         ca0113_mmio_gpio_set(codec, 0, false);
9050         ca0113_mmio_gpio_set(codec, 4, true);
9051         ca0113_mmio_gpio_set(codec, 0, true);
9052         ca0113_mmio_gpio_set(codec, 5, true);
9053         ca0113_mmio_gpio_set(codec, 2, false);
9054         ca0113_mmio_gpio_set(codec, 3, false);
9055 }
9056
9057 static void ca0132_exit_chip(struct hda_codec *codec)
9058 {
9059         /* put any chip cleanup stuffs here. */
9060
9061         if (dspload_is_loaded(codec))
9062                 dsp_reset(codec);
9063 }
9064
9065 /*
9066  * This fixes a problem that was hard to reproduce. Very rarely, I would
9067  * boot up, and there would be no sound, but the DSP indicated it had loaded
9068  * properly. I did a few memory dumps to see if anything was different, and
9069  * there were a few areas of memory uninitialized with a1a2a3a4. This function
9070  * checks if those areas are uninitialized, and if they are, it'll attempt to
9071  * reload the card 3 times. Usually it fixes by the second.
9072  */
9073 static void sbz_dsp_startup_check(struct hda_codec *codec)
9074 {
9075         struct ca0132_spec *spec = codec->spec;
9076         unsigned int dsp_data_check[4];
9077         unsigned int cur_address = 0x390;
9078         unsigned int i;
9079         unsigned int failure = 0;
9080         unsigned int reload = 3;
9081
9082         if (spec->startup_check_entered)
9083                 return;
9084
9085         spec->startup_check_entered = true;
9086
9087         for (i = 0; i < 4; i++) {
9088                 chipio_read(codec, cur_address, &dsp_data_check[i]);
9089                 cur_address += 0x4;
9090         }
9091         for (i = 0; i < 4; i++) {
9092                 if (dsp_data_check[i] == 0xa1a2a3a4)
9093                         failure = 1;
9094         }
9095
9096         codec_dbg(codec, "Startup Check: %d ", failure);
9097         if (failure)
9098                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9099         /*
9100          * While the failure condition is true, and we haven't reached our
9101          * three reload limit, continue trying to reload the driver and
9102          * fix the issue.
9103          */
9104         while (failure && (reload != 0)) {
9105                 codec_info(codec, "Reloading... Tries left: %d", reload);
9106                 sbz_exit_chip(codec);
9107                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9108                 codec->patch_ops.init(codec);
9109                 failure = 0;
9110                 for (i = 0; i < 4; i++) {
9111                         chipio_read(codec, cur_address, &dsp_data_check[i]);
9112                         cur_address += 0x4;
9113                 }
9114                 for (i = 0; i < 4; i++) {
9115                         if (dsp_data_check[i] == 0xa1a2a3a4)
9116                                 failure = 1;
9117                 }
9118                 reload--;
9119         }
9120
9121         if (!failure && reload < 3)
9122                 codec_info(codec, "DSP fixed.");
9123
9124         if (!failure)
9125                 return;
9126
9127         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9128 }
9129
9130 /*
9131  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9132  * extra precision for decibel values. If you had the dB value in floating point
9133  * you would take the value after the decimal point, multiply by 64, and divide
9134  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9135  * implement fixed point or floating point dB volumes. For now, I'll set them
9136  * to 0 just incase a value has lingered from a boot into Windows.
9137  */
9138 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9139 {
9140         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9141         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9142         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9143         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9144         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9145         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9146         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9147         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9148 }
9149
9150 /*
9151  * Extra commands that don't really fit anywhere else.
9152  */
9153 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9154 {
9155         struct ca0132_spec *spec = codec->spec;
9156
9157         writel(0x00820680, spec->mem_base + 0x01C);
9158         writel(0x00820680, spec->mem_base + 0x01C);
9159
9160         chipio_write(codec, 0x18b0a4, 0x000000c2);
9161
9162         snd_hda_codec_write(codec, 0x11, 0,
9163                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9164 }
9165
9166 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9167 {
9168         chipio_write(codec, 0x18b0a4, 0x000000c2);
9169
9170         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9171
9172         snd_hda_codec_write(codec, 0x11, 0,
9173                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9174 }
9175
9176 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9177 {
9178         chipio_write(codec, 0x18b0a4, 0x000000c2);
9179
9180         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9181         chipio_8051_write_exram(codec, 0x1920, 0x00);
9182         chipio_8051_write_exram(codec, 0x1921, 0x40);
9183
9184         snd_hda_codec_write(codec, 0x11, 0,
9185                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9186 }
9187
9188 /*
9189  * The ZxR seems to use alternative DAC's for the surround channels, which
9190  * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9191  * this up, we get no audio out of the surround jacks.
9192  */
9193 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9194 {
9195         static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9196         static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9197         unsigned int i;
9198
9199         chipio_write(codec, 0x189000, 0x0001f100);
9200         msleep(50);
9201         chipio_write(codec, 0x18900c, 0x0001f100);
9202         msleep(50);
9203
9204         /*
9205          * This writes a RET instruction at the entry point of the function at
9206          * 0xfa92 in exram. This function seems to have something to do with
9207          * ASI. Might be some way to prevent the card from reconfiguring the
9208          * ASI stuff itself.
9209          */
9210         chipio_8051_write_exram(codec, 0xfa92, 0x22);
9211
9212         chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9213
9214         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9215         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9216
9217         chipio_write(codec, 0x18902c, 0x00000000);
9218         msleep(50);
9219         chipio_write(codec, 0x18902c, 0x00000003);
9220         msleep(50);
9221
9222         for (i = 0; i < ARRAY_SIZE(addr); i++)
9223                 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9224 }
9225
9226 /*
9227  * These are sent before the DSP is downloaded. Not sure
9228  * what they do, or if they're necessary. Could possibly
9229  * be removed. Figure they're better to leave in.
9230  */
9231 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9232         0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9233         0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9234 };
9235
9236 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9237         0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9238         0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9239         0x000000c1, 0x00000080
9240 };
9241
9242 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9243         0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9244         0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9245         0x000000c1, 0x00000080
9246 };
9247
9248 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9249         0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9250         0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9251         0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9252         0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9253 };
9254
9255 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9256         0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9257         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9258         0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9259         0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9260         0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9261         0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9262         0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9263         0x00000080, 0x00880680
9264 };
9265
9266 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9267 {
9268         struct ca0132_spec *spec = codec->spec;
9269         unsigned int tmp[2], i, count, cur_addr;
9270         const unsigned int *addr, *data;
9271
9272         addr = ca0113_mmio_init_address_sbz;
9273         for (i = 0; i < 3; i++)
9274                 writel(0x00000000, spec->mem_base + addr[i]);
9275
9276         cur_addr = i;
9277         switch (ca0132_quirk(spec)) {
9278         case QUIRK_ZXR:
9279                 tmp[0] = 0x00880480;
9280                 tmp[1] = 0x00000080;
9281                 break;
9282         case QUIRK_SBZ:
9283                 tmp[0] = 0x00820680;
9284                 tmp[1] = 0x00000083;
9285                 break;
9286         case QUIRK_R3D:
9287                 tmp[0] = 0x00880680;
9288                 tmp[1] = 0x00000083;
9289                 break;
9290         default:
9291                 tmp[0] = 0x00000000;
9292                 tmp[1] = 0x00000000;
9293                 break;
9294         }
9295
9296         for (i = 0; i < 2; i++)
9297                 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9298
9299         cur_addr += i;
9300
9301         switch (ca0132_quirk(spec)) {
9302         case QUIRK_ZXR:
9303                 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9304                 data = ca0113_mmio_init_data_zxr;
9305                 break;
9306         default:
9307                 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9308                 data = ca0113_mmio_init_data_sbz;
9309                 break;
9310         }
9311
9312         for (i = 0; i < count; i++)
9313                 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9314 }
9315
9316 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9317 {
9318         struct ca0132_spec *spec = codec->spec;
9319         const unsigned int *addr, *data;
9320         unsigned int i, count;
9321
9322         addr = ca0113_mmio_init_address_ae5;
9323         data = ca0113_mmio_init_data_ae5;
9324         count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9325
9326         if (ca0132_quirk(spec) == QUIRK_AE7) {
9327                 writel(0x00000680, spec->mem_base + 0x1c);
9328                 writel(0x00880680, spec->mem_base + 0x1c);
9329         }
9330
9331         for (i = 0; i < count; i++) {
9332                 /*
9333                  * AE-7 shares all writes with the AE-5, except that it writes
9334                  * a different value to 0x20c.
9335                  */
9336                 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9337                         writel(0x00800001, spec->mem_base + addr[i]);
9338                         continue;
9339                 }
9340
9341                 writel(data[i], spec->mem_base + addr[i]);
9342         }
9343
9344         if (ca0132_quirk(spec) == QUIRK_AE5)
9345                 writel(0x00880680, spec->mem_base + 0x1c);
9346 }
9347
9348 static void ca0132_mmio_init(struct hda_codec *codec)
9349 {
9350         struct ca0132_spec *spec = codec->spec;
9351
9352         switch (ca0132_quirk(spec)) {
9353         case QUIRK_R3D:
9354         case QUIRK_SBZ:
9355         case QUIRK_ZXR:
9356                 ca0132_mmio_init_sbz(codec);
9357                 break;
9358         case QUIRK_AE5:
9359                 ca0132_mmio_init_ae5(codec);
9360                 break;
9361         default:
9362                 break;
9363         }
9364 }
9365
9366 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9367         0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9368         0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9369 };
9370
9371 static const unsigned char ca0132_ae5_register_set_data[] = {
9372         0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9373         0x01, 0x6b, 0x57
9374 };
9375
9376 /*
9377  * This function writes to some SFR's, does some region2 writes, and then
9378  * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9379  * what it does.
9380  */
9381 static void ae5_register_set(struct hda_codec *codec)
9382 {
9383         struct ca0132_spec *spec = codec->spec;
9384         unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9385         const unsigned int *addr = ca0132_ae5_register_set_addresses;
9386         const unsigned char *data = ca0132_ae5_register_set_data;
9387         unsigned int i, cur_addr;
9388         unsigned char tmp[3];
9389
9390         if (ca0132_quirk(spec) == QUIRK_AE7)
9391                 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9392
9393         chipio_8051_write_direct(codec, 0x93, 0x10);
9394         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9395
9396         if (ca0132_quirk(spec) == QUIRK_AE7) {
9397                 tmp[0] = 0x03;
9398                 tmp[1] = 0x03;
9399                 tmp[2] = 0x07;
9400         } else {
9401                 tmp[0] = 0x0f;
9402                 tmp[1] = 0x0f;
9403                 tmp[2] = 0x0f;
9404         }
9405
9406         for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9407                 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9408
9409         /*
9410          * First writes are in single bytes, final are in 4 bytes. So, we use
9411          * writeb, then writel.
9412          */
9413         for (i = 0; cur_addr < 12; i++, cur_addr++)
9414                 writeb(data[i], spec->mem_base + addr[cur_addr]);
9415
9416         for (; cur_addr < count; i++, cur_addr++)
9417                 writel(data[i], spec->mem_base + addr[cur_addr]);
9418
9419         writel(0x00800001, spec->mem_base + 0x20c);
9420
9421         if (ca0132_quirk(spec) == QUIRK_AE7) {
9422                 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9423                 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9424         } else {
9425                 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9426         }
9427
9428         chipio_8051_write_direct(codec, 0x90, 0x00);
9429         chipio_8051_write_direct(codec, 0x90, 0x10);
9430
9431         if (ca0132_quirk(spec) == QUIRK_AE5)
9432                 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9433 }
9434
9435 /*
9436  * Extra init functions for alternative ca0132 codecs. Done
9437  * here so they don't clutter up the main ca0132_init function
9438  * anymore than they have to.
9439  */
9440 static void ca0132_alt_init(struct hda_codec *codec)
9441 {
9442         struct ca0132_spec *spec = codec->spec;
9443
9444         ca0132_alt_vol_setup(codec);
9445
9446         switch (ca0132_quirk(spec)) {
9447         case QUIRK_SBZ:
9448                 codec_dbg(codec, "SBZ alt_init");
9449                 ca0132_gpio_init(codec);
9450                 sbz_pre_dsp_setup(codec);
9451                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9452                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9453                 break;
9454         case QUIRK_R3DI:
9455                 codec_dbg(codec, "R3DI alt_init");
9456                 ca0132_gpio_init(codec);
9457                 ca0132_gpio_setup(codec);
9458                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9459                 r3di_pre_dsp_setup(codec);
9460                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9461                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9462                 break;
9463         case QUIRK_R3D:
9464                 r3d_pre_dsp_setup(codec);
9465                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9466                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9467                 break;
9468         case QUIRK_AE5:
9469                 ca0132_gpio_init(codec);
9470                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9471                 chipio_write(codec, 0x18b030, 0x00000020);
9472                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9473                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9474                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9475                 break;
9476         case QUIRK_AE7:
9477                 ca0132_gpio_init(codec);
9478                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9479                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9480                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9481                 chipio_write(codec, 0x18b008, 0x000000f8);
9482                 chipio_write(codec, 0x18b008, 0x000000f0);
9483                 chipio_write(codec, 0x18b030, 0x00000020);
9484                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9485                 break;
9486         case QUIRK_ZXR:
9487                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9488                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9489                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9490                 zxr_pre_dsp_setup(codec);
9491                 break;
9492         default:
9493                 break;
9494         }
9495 }
9496
9497 static int ca0132_init(struct hda_codec *codec)
9498 {
9499         struct ca0132_spec *spec = codec->spec;
9500         struct auto_pin_cfg *cfg = &spec->autocfg;
9501         int i;
9502         bool dsp_loaded;
9503
9504         /*
9505          * If the DSP is already downloaded, and init has been entered again,
9506          * there's only two reasons for it. One, the codec has awaken from a
9507          * suspended state, and in that case dspload_is_loaded will return
9508          * false, and the init will be ran again. The other reason it gets
9509          * re entered is on startup for some reason it triggers a suspend and
9510          * resume state. In this case, it will check if the DSP is downloaded,
9511          * and not run the init function again. For codecs using alt_functions,
9512          * it will check if the DSP is loaded properly.
9513          */
9514         if (spec->dsp_state == DSP_DOWNLOADED) {
9515                 dsp_loaded = dspload_is_loaded(codec);
9516                 if (!dsp_loaded) {
9517                         spec->dsp_reload = true;
9518                         spec->dsp_state = DSP_DOWNLOAD_INIT;
9519                 } else {
9520                         if (ca0132_quirk(spec) == QUIRK_SBZ)
9521                                 sbz_dsp_startup_check(codec);
9522                         return 0;
9523                 }
9524         }
9525
9526         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9527                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9528         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9529
9530         if (ca0132_use_pci_mmio(spec))
9531                 ca0132_mmio_init(codec);
9532
9533         snd_hda_power_up_pm(codec);
9534
9535         if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9536                 ae5_register_set(codec);
9537
9538         ca0132_init_params(codec);
9539         ca0132_init_flags(codec);
9540
9541         snd_hda_sequence_write(codec, spec->base_init_verbs);
9542
9543         if (ca0132_use_alt_functions(spec))
9544                 ca0132_alt_init(codec);
9545
9546         ca0132_download_dsp(codec);
9547
9548         ca0132_refresh_widget_caps(codec);
9549
9550         switch (ca0132_quirk(spec)) {
9551         case QUIRK_R3DI:
9552         case QUIRK_R3D:
9553                 r3d_setup_defaults(codec);
9554                 break;
9555         case QUIRK_SBZ:
9556         case QUIRK_ZXR:
9557                 sbz_setup_defaults(codec);
9558                 break;
9559         case QUIRK_AE5:
9560                 ae5_setup_defaults(codec);
9561                 break;
9562         case QUIRK_AE7:
9563                 ae7_setup_defaults(codec);
9564                 break;
9565         default:
9566                 ca0132_setup_defaults(codec);
9567                 ca0132_init_analog_mic2(codec);
9568                 ca0132_init_dmic(codec);
9569                 break;
9570         }
9571
9572         for (i = 0; i < spec->num_outputs; i++)
9573                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9574
9575         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9576
9577         for (i = 0; i < spec->num_inputs; i++)
9578                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9579
9580         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9581
9582         if (!ca0132_use_alt_functions(spec)) {
9583                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9584                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9585                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9586                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9587                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9588         }
9589
9590         if (ca0132_quirk(spec) == QUIRK_SBZ)
9591                 ca0132_gpio_setup(codec);
9592
9593         snd_hda_sequence_write(codec, spec->spec_init_verbs);
9594         if (ca0132_use_alt_functions(spec)) {
9595                 ca0132_alt_select_out(codec);
9596                 ca0132_alt_select_in(codec);
9597         } else {
9598                 ca0132_select_out(codec);
9599                 ca0132_select_mic(codec);
9600         }
9601
9602         snd_hda_jack_report_sync(codec);
9603
9604         /*
9605          * Re set the PlayEnhancement switch on a resume event, because the
9606          * controls will not be reloaded.
9607          */
9608         if (spec->dsp_reload) {
9609                 spec->dsp_reload = false;
9610                 ca0132_pe_switch_set(codec);
9611         }
9612
9613         snd_hda_power_down_pm(codec);
9614
9615         return 0;
9616 }
9617
9618 static int dbpro_init(struct hda_codec *codec)
9619 {
9620         struct ca0132_spec *spec = codec->spec;
9621         struct auto_pin_cfg *cfg = &spec->autocfg;
9622         unsigned int i;
9623
9624         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9625         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9626
9627         for (i = 0; i < spec->num_inputs; i++)
9628                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9629
9630         return 0;
9631 }
9632
9633 static void ca0132_free(struct hda_codec *codec)
9634 {
9635         struct ca0132_spec *spec = codec->spec;
9636
9637         cancel_delayed_work_sync(&spec->unsol_hp_work);
9638         snd_hda_power_up(codec);
9639         switch (ca0132_quirk(spec)) {
9640         case QUIRK_SBZ:
9641                 sbz_exit_chip(codec);
9642                 break;
9643         case QUIRK_ZXR:
9644                 zxr_exit_chip(codec);
9645                 break;
9646         case QUIRK_R3D:
9647                 r3d_exit_chip(codec);
9648                 break;
9649         case QUIRK_AE5:
9650                 ae5_exit_chip(codec);
9651                 break;
9652         case QUIRK_AE7:
9653                 ae7_exit_chip(codec);
9654                 break;
9655         case QUIRK_R3DI:
9656                 r3di_gpio_shutdown(codec);
9657                 break;
9658         default:
9659                 break;
9660         }
9661
9662         snd_hda_sequence_write(codec, spec->base_exit_verbs);
9663         ca0132_exit_chip(codec);
9664
9665         snd_hda_power_down(codec);
9666 #ifdef CONFIG_PCI
9667         if (spec->mem_base)
9668                 pci_iounmap(codec->bus->pci, spec->mem_base);
9669 #endif
9670         kfree(spec->spec_init_verbs);
9671         kfree(codec->spec);
9672 }
9673
9674 static void dbpro_free(struct hda_codec *codec)
9675 {
9676         struct ca0132_spec *spec = codec->spec;
9677
9678         zxr_dbpro_power_state_shutdown(codec);
9679
9680         kfree(spec->spec_init_verbs);
9681         kfree(codec->spec);
9682 }
9683
9684 #ifdef CONFIG_PM
9685 static int ca0132_suspend(struct hda_codec *codec)
9686 {
9687         struct ca0132_spec *spec = codec->spec;
9688
9689         cancel_delayed_work_sync(&spec->unsol_hp_work);
9690         return 0;
9691 }
9692 #endif
9693
9694 static const struct hda_codec_ops ca0132_patch_ops = {
9695         .build_controls = ca0132_build_controls,
9696         .build_pcms = ca0132_build_pcms,
9697         .init = ca0132_init,
9698         .free = ca0132_free,
9699         .unsol_event = snd_hda_jack_unsol_event,
9700 #ifdef CONFIG_PM
9701         .suspend = ca0132_suspend,
9702 #endif
9703 };
9704
9705 static const struct hda_codec_ops dbpro_patch_ops = {
9706         .build_controls = dbpro_build_controls,
9707         .build_pcms = dbpro_build_pcms,
9708         .init = dbpro_init,
9709         .free = dbpro_free,
9710 };
9711
9712 static void ca0132_config(struct hda_codec *codec)
9713 {
9714         struct ca0132_spec *spec = codec->spec;
9715
9716         spec->dacs[0] = 0x2;
9717         spec->dacs[1] = 0x3;
9718         spec->dacs[2] = 0x4;
9719
9720         spec->multiout.dac_nids = spec->dacs;
9721         spec->multiout.num_dacs = 3;
9722
9723         if (!ca0132_use_alt_functions(spec))
9724                 spec->multiout.max_channels = 2;
9725         else
9726                 spec->multiout.max_channels = 6;
9727
9728         switch (ca0132_quirk(spec)) {
9729         case QUIRK_ALIENWARE:
9730                 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9731                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9732                 break;
9733         case QUIRK_SBZ:
9734                 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9735                 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9736                 break;
9737         case QUIRK_ZXR:
9738                 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9739                 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9740                 break;
9741         case QUIRK_R3D:
9742                 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9743                 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9744                 break;
9745         case QUIRK_R3DI:
9746                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9747                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9748                 break;
9749         case QUIRK_AE5:
9750                 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9751                 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9752                 break;
9753         case QUIRK_AE7:
9754                 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9755                 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9756                 break;
9757         default:
9758                 break;
9759         }
9760
9761         switch (ca0132_quirk(spec)) {
9762         case QUIRK_ALIENWARE:
9763                 spec->num_outputs = 2;
9764                 spec->out_pins[0] = 0x0b; /* speaker out */
9765                 spec->out_pins[1] = 0x0f;
9766                 spec->shared_out_nid = 0x2;
9767                 spec->unsol_tag_hp = 0x0f;
9768
9769                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9770                 spec->adcs[1] = 0x8; /* analog mic2 */
9771                 spec->adcs[2] = 0xa; /* what u hear */
9772
9773                 spec->num_inputs = 3;
9774                 spec->input_pins[0] = 0x12;
9775                 spec->input_pins[1] = 0x11;
9776                 spec->input_pins[2] = 0x13;
9777                 spec->shared_mic_nid = 0x7;
9778                 spec->unsol_tag_amic1 = 0x11;
9779                 break;
9780         case QUIRK_SBZ:
9781         case QUIRK_R3D:
9782                 spec->num_outputs = 2;
9783                 spec->out_pins[0] = 0x0B; /* Line out */
9784                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9785                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9786                 spec->out_pins[3] = 0x11; /* Rear surround */
9787                 spec->shared_out_nid = 0x2;
9788                 spec->unsol_tag_hp = spec->out_pins[1];
9789                 spec->unsol_tag_front_hp = spec->out_pins[2];
9790
9791                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9792                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9793                 spec->adcs[2] = 0xa; /* what u hear */
9794
9795                 spec->num_inputs = 2;
9796                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9797                 spec->input_pins[1] = 0x13; /* What U Hear */
9798                 spec->shared_mic_nid = 0x7;
9799                 spec->unsol_tag_amic1 = spec->input_pins[0];
9800
9801                 /* SPDIF I/O */
9802                 spec->dig_out = 0x05;
9803                 spec->multiout.dig_out_nid = spec->dig_out;
9804                 spec->dig_in = 0x09;
9805                 break;
9806         case QUIRK_ZXR:
9807                 spec->num_outputs = 2;
9808                 spec->out_pins[0] = 0x0B; /* Line out */
9809                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9810                 spec->out_pins[2] = 0x10; /* Center/LFE */
9811                 spec->out_pins[3] = 0x11; /* Rear surround */
9812                 spec->shared_out_nid = 0x2;
9813                 spec->unsol_tag_hp = spec->out_pins[1];
9814                 spec->unsol_tag_front_hp = spec->out_pins[2];
9815
9816                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9817                 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9818                 spec->adcs[2] = 0xa; /* what u hear */
9819
9820                 spec->num_inputs = 2;
9821                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9822                 spec->input_pins[1] = 0x13; /* What U Hear */
9823                 spec->shared_mic_nid = 0x7;
9824                 spec->unsol_tag_amic1 = spec->input_pins[0];
9825                 break;
9826         case QUIRK_ZXR_DBPRO:
9827                 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9828
9829                 spec->num_inputs = 1;
9830                 spec->input_pins[0] = 0x11; /* RCA Line-in */
9831
9832                 spec->dig_out = 0x05;
9833                 spec->multiout.dig_out_nid = spec->dig_out;
9834
9835                 spec->dig_in = 0x09;
9836                 break;
9837         case QUIRK_AE5:
9838         case QUIRK_AE7:
9839                 spec->num_outputs = 2;
9840                 spec->out_pins[0] = 0x0B; /* Line out */
9841                 spec->out_pins[1] = 0x11; /* Rear headphone out */
9842                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9843                 spec->out_pins[3] = 0x0F; /* Rear surround */
9844                 spec->shared_out_nid = 0x2;
9845                 spec->unsol_tag_hp = spec->out_pins[1];
9846                 spec->unsol_tag_front_hp = spec->out_pins[2];
9847
9848                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9849                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9850                 spec->adcs[2] = 0xa; /* what u hear */
9851
9852                 spec->num_inputs = 2;
9853                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9854                 spec->input_pins[1] = 0x13; /* What U Hear */
9855                 spec->shared_mic_nid = 0x7;
9856                 spec->unsol_tag_amic1 = spec->input_pins[0];
9857
9858                 /* SPDIF I/O */
9859                 spec->dig_out = 0x05;
9860                 spec->multiout.dig_out_nid = spec->dig_out;
9861                 break;
9862         case QUIRK_R3DI:
9863                 spec->num_outputs = 2;
9864                 spec->out_pins[0] = 0x0B; /* Line out */
9865                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9866                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9867                 spec->out_pins[3] = 0x11; /* Rear surround */
9868                 spec->shared_out_nid = 0x2;
9869                 spec->unsol_tag_hp = spec->out_pins[1];
9870                 spec->unsol_tag_front_hp = spec->out_pins[2];
9871
9872                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9873                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9874                 spec->adcs[2] = 0x0a; /* what u hear */
9875
9876                 spec->num_inputs = 2;
9877                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9878                 spec->input_pins[1] = 0x13; /* What U Hear */
9879                 spec->shared_mic_nid = 0x7;
9880                 spec->unsol_tag_amic1 = spec->input_pins[0];
9881
9882                 /* SPDIF I/O */
9883                 spec->dig_out = 0x05;
9884                 spec->multiout.dig_out_nid = spec->dig_out;
9885                 break;
9886         default:
9887                 spec->num_outputs = 2;
9888                 spec->out_pins[0] = 0x0b; /* speaker out */
9889                 spec->out_pins[1] = 0x10; /* headphone out */
9890                 spec->shared_out_nid = 0x2;
9891                 spec->unsol_tag_hp = spec->out_pins[1];
9892
9893                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9894                 spec->adcs[1] = 0x8; /* analog mic2 */
9895                 spec->adcs[2] = 0xa; /* what u hear */
9896
9897                 spec->num_inputs = 3;
9898                 spec->input_pins[0] = 0x12;
9899                 spec->input_pins[1] = 0x11;
9900                 spec->input_pins[2] = 0x13;
9901                 spec->shared_mic_nid = 0x7;
9902                 spec->unsol_tag_amic1 = spec->input_pins[0];
9903
9904                 /* SPDIF I/O */
9905                 spec->dig_out = 0x05;
9906                 spec->multiout.dig_out_nid = spec->dig_out;
9907                 spec->dig_in = 0x09;
9908                 break;
9909         }
9910 }
9911
9912 static int ca0132_prepare_verbs(struct hda_codec *codec)
9913 {
9914 /* Verbs + terminator (an empty element) */
9915 #define NUM_SPEC_VERBS 2
9916         struct ca0132_spec *spec = codec->spec;
9917
9918         spec->chip_init_verbs = ca0132_init_verbs0;
9919         /*
9920          * Since desktop cards use pci_mmio, this can be used to determine
9921          * whether or not to use these verbs instead of a separate bool.
9922          */
9923         if (ca0132_use_pci_mmio(spec))
9924                 spec->desktop_init_verbs = ca0132_init_verbs1;
9925         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9926                                         sizeof(struct hda_verb),
9927                                         GFP_KERNEL);
9928         if (!spec->spec_init_verbs)
9929                 return -ENOMEM;
9930
9931         /* config EAPD */
9932         spec->spec_init_verbs[0].nid = 0x0b;
9933         spec->spec_init_verbs[0].param = 0x78D;
9934         spec->spec_init_verbs[0].verb = 0x00;
9935
9936         /* Previously commented configuration */
9937         /*
9938         spec->spec_init_verbs[2].nid = 0x0b;
9939         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9940         spec->spec_init_verbs[2].verb = 0x02;
9941
9942         spec->spec_init_verbs[3].nid = 0x10;
9943         spec->spec_init_verbs[3].param = 0x78D;
9944         spec->spec_init_verbs[3].verb = 0x02;
9945
9946         spec->spec_init_verbs[4].nid = 0x10;
9947         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9948         spec->spec_init_verbs[4].verb = 0x02;
9949         */
9950
9951         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9952         return 0;
9953 }
9954
9955 /*
9956  * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9957  * Sound Blaster Z cards. However, they have different HDA codec subsystem
9958  * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9959  * daughter boards ID.
9960  */
9961 static void sbz_detect_quirk(struct hda_codec *codec)
9962 {
9963         struct ca0132_spec *spec = codec->spec;
9964
9965         switch (codec->core.subsystem_id) {
9966         case 0x11020033:
9967                 spec->quirk = QUIRK_ZXR;
9968                 break;
9969         case 0x1102003f:
9970                 spec->quirk = QUIRK_ZXR_DBPRO;
9971                 break;
9972         default:
9973                 spec->quirk = QUIRK_SBZ;
9974                 break;
9975         }
9976 }
9977
9978 static int patch_ca0132(struct hda_codec *codec)
9979 {
9980         struct ca0132_spec *spec;
9981         int err;
9982         const struct snd_pci_quirk *quirk;
9983
9984         codec_dbg(codec, "patch_ca0132\n");
9985
9986         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9987         if (!spec)
9988                 return -ENOMEM;
9989         codec->spec = spec;
9990         spec->codec = codec;
9991
9992         /* Detect codec quirk */
9993         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9994         if (quirk)
9995                 spec->quirk = quirk->value;
9996         else
9997                 spec->quirk = QUIRK_NONE;
9998         if (ca0132_quirk(spec) == QUIRK_SBZ)
9999                 sbz_detect_quirk(codec);
10000
10001         if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10002                 codec->patch_ops = dbpro_patch_ops;
10003         else
10004                 codec->patch_ops = ca0132_patch_ops;
10005
10006         codec->pcm_format_first = 1;
10007         codec->no_sticky_stream = 1;
10008
10009
10010         spec->dsp_state = DSP_DOWNLOAD_INIT;
10011         spec->num_mixers = 1;
10012
10013         /* Set which mixers each quirk uses. */
10014         switch (ca0132_quirk(spec)) {
10015         case QUIRK_SBZ:
10016                 spec->mixers[0] = desktop_mixer;
10017                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10018                 break;
10019         case QUIRK_ZXR:
10020                 spec->mixers[0] = desktop_mixer;
10021                 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10022                 break;
10023         case QUIRK_ZXR_DBPRO:
10024                 break;
10025         case QUIRK_R3D:
10026                 spec->mixers[0] = desktop_mixer;
10027                 snd_hda_codec_set_name(codec, "Recon3D");
10028                 break;
10029         case QUIRK_R3DI:
10030                 spec->mixers[0] = r3di_mixer;
10031                 snd_hda_codec_set_name(codec, "Recon3Di");
10032                 break;
10033         case QUIRK_AE5:
10034                 spec->mixers[0] = desktop_mixer;
10035                 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10036                 break;
10037         case QUIRK_AE7:
10038                 spec->mixers[0] = desktop_mixer;
10039                 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10040                 break;
10041         default:
10042                 spec->mixers[0] = ca0132_mixer;
10043                 break;
10044         }
10045
10046         /* Setup whether or not to use alt functions/controls/pci_mmio */
10047         switch (ca0132_quirk(spec)) {
10048         case QUIRK_SBZ:
10049         case QUIRK_R3D:
10050         case QUIRK_AE5:
10051         case QUIRK_AE7:
10052         case QUIRK_ZXR:
10053                 spec->use_alt_controls = true;
10054                 spec->use_alt_functions = true;
10055                 spec->use_pci_mmio = true;
10056                 break;
10057         case QUIRK_R3DI:
10058                 spec->use_alt_controls = true;
10059                 spec->use_alt_functions = true;
10060                 spec->use_pci_mmio = false;
10061                 break;
10062         default:
10063                 spec->use_alt_controls = false;
10064                 spec->use_alt_functions = false;
10065                 spec->use_pci_mmio = false;
10066                 break;
10067         }
10068
10069 #ifdef CONFIG_PCI
10070         if (spec->use_pci_mmio) {
10071                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10072                 if (spec->mem_base == NULL) {
10073                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10074                         spec->quirk = QUIRK_NONE;
10075                 }
10076         }
10077 #endif
10078
10079         spec->base_init_verbs = ca0132_base_init_verbs;
10080         spec->base_exit_verbs = ca0132_base_exit_verbs;
10081
10082         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10083
10084         ca0132_init_chip(codec);
10085
10086         ca0132_config(codec);
10087
10088         err = ca0132_prepare_verbs(codec);
10089         if (err < 0)
10090                 goto error;
10091
10092         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10093         if (err < 0)
10094                 goto error;
10095
10096         ca0132_setup_unsol(codec);
10097
10098         return 0;
10099
10100  error:
10101         ca0132_free(codec);
10102         return err;
10103 }
10104
10105 /*
10106  * patch entries
10107  */
10108 static const struct hda_device_id snd_hda_id_ca0132[] = {
10109         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
10110         {} /* terminator */
10111 };
10112 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10113
10114 MODULE_LICENSE("GPL");
10115 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10116
10117 static struct hda_codec_driver ca0132_driver = {
10118         .id = snd_hda_id_ca0132,
10119 };
10120
10121 module_hda_codec_driver(ca0132_driver);