sound/pci/hda/patch_ca0132.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Creative CA0132 chip
   4  *
   5  * Copyright (c) 2011, Creative Technology Ltd.
   6  *
   7  * Based on patch_ca0110.c
   8  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/module.h>
  16 #include <linux/firmware.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <asm/io.h>
  22 #include <sound/core.h>
  23 #include <sound/hda_codec.h>
  24 #include "hda_local.h"
  25 #include "hda_auto_parser.h"
  26 #include "hda_jack.h"
  27
  28 #include "ca0132_regs.h"
  29
  30 /* Enable this to see controls for tuning purpose. */
  31 /*#define ENABLE_TUNING_CONTROLS*/
  32
  33 #ifdef ENABLE_TUNING_CONTROLS
  34 #include <sound/tlv.h>
  35 #endif
  36
  37 #define FLOAT_ZERO      0x00000000
  38 #define FLOAT_ONE       0x3f800000
  39 #define FLOAT_TWO       0x40000000
  40 #define FLOAT_THREE     0x40400000
  41 #define FLOAT_EIGHT     0x41000000
  42 #define FLOAT_MINUS_5   0xc0a00000
  43
  44 #define UNSOL_TAG_DSP   0x16
  45
  46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  48
  49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  52
  53 #define MASTERCONTROL                           0x80
  54 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  56
  57 #define WIDGET_CHIP_CTRL      0x15
  58 #define WIDGET_DSP_CTRL       0x16
  59
  60 #define MEM_CONNID_MICIN1     3
  61 #define MEM_CONNID_MICIN2     5
  62 #define MEM_CONNID_MICOUT1    12
  63 #define MEM_CONNID_MICOUT2    14
  64 #define MEM_CONNID_WUH        10
  65 #define MEM_CONNID_DSP        16
  66 #define MEM_CONNID_DMIC       100
  67
  68 #define SCP_SET    0
  69 #define SCP_GET    1
  70
  71 #define EFX_FILE   "/*(DEBLOBBED)*/"
  72 #define DESKTOP_EFX_FILE   "/*(DEBLOBBED)*/"
  73 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  74
  75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  76 /*(DEBLOBBED)*/
  77 #endif
  78
  79 static const char *const dirstr[2] = { "Playback", "Capture" };
  80
  81 #define NUM_OF_OUTPUTS 3
  82 enum {
  83         SPEAKER_OUT,
  84         HEADPHONE_OUT,
  85         SURROUND_OUT
  86 };
  87
  88 enum {
  89         DIGITAL_MIC,
  90         LINE_MIC_IN
  91 };
  92
  93 /* Strings for Input Source Enum Control */
  94 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
  95 #define IN_SRC_NUM_OF_INPUTS 3
  96 enum {
  97         REAR_MIC,
  98         REAR_LINE_IN,
  99         FRONT_MIC,
 100 };
 101
 102 enum {
 103 #define VNODE_START_NID    0x80
 104         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 105         VNID_MIC,
 106         VNID_HP_SEL,
 107         VNID_AMIC1_SEL,
 108         VNID_HP_ASEL,
 109         VNID_AMIC1_ASEL,
 110         VNODE_END_NID,
 111 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 112
 113 #define EFFECT_START_NID    0x90
 114 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 115         SURROUND = OUT_EFFECT_START_NID,
 116         CRYSTALIZER,
 117         DIALOG_PLUS,
 118         SMART_VOLUME,
 119         X_BASS,
 120         EQUALIZER,
 121         OUT_EFFECT_END_NID,
 122 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 123
 124 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 125         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 126         VOICE_FOCUS,
 127         MIC_SVM,
 128         NOISE_REDUCTION,
 129         IN_EFFECT_END_NID,
 130 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 131
 132         VOICEFX = IN_EFFECT_END_NID,
 133         PLAY_ENHANCEMENT,
 134         CRYSTAL_VOICE,
 135         EFFECT_END_NID,
 136         OUTPUT_SOURCE_ENUM,
 137         INPUT_SOURCE_ENUM,
 138         XBASS_XOVER,
 139         EQ_PRESET_ENUM,
 140         SMART_VOLUME_ENUM,
 141         MIC_BOOST_ENUM,
 142         AE5_HEADPHONE_GAIN_ENUM,
 143         AE5_SOUND_FILTER_ENUM,
 144         ZXR_HEADPHONE_GAIN
 145 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 146 };
 147
 148 /* Effects values size*/
 149 #define EFFECT_VALS_MAX_COUNT 12
 150
 151 /*
 152  * Default values for the effect slider controls, they are in order of their
 153  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 154  * X-bass.
 155  */
 156 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 157 /* Amount of effect level sliders for ca0132_alt controls. */
 158 #define EFFECT_LEVEL_SLIDERS 5
 159
 160 /* Latency introduced by DSP blocks in milliseconds. */
 161 #define DSP_CAPTURE_INIT_LATENCY        0
 162 #define DSP_CRYSTAL_VOICE_LATENCY       124
 163 #define DSP_PLAYBACK_INIT_LATENCY       13
 164 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 165 #define DSP_SPEAKER_OUT_LATENCY         7
 166
 167 struct ct_effect {
 168         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 169         hda_nid_t nid;
 170         int mid; /*effect module ID*/
 171         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 172         int direct; /* 0:output; 1:input*/
 173         int params; /* number of default non-on/off params */
 174         /*effect default values, 1st is on/off. */
 175         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 176 };
 177
 178 #define EFX_DIR_OUT 0
 179 #define EFX_DIR_IN  1
 180
 181 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 182         { .name = "Surround",
 183           .nid = SURROUND,
 184           .mid = 0x96,
 185           .reqs = {0, 1},
 186           .direct = EFX_DIR_OUT,
 187           .params = 1,
 188           .def_vals = {0x3F800000, 0x3F2B851F}
 189         },
 190         { .name = "Crystalizer",
 191           .nid = CRYSTALIZER,
 192           .mid = 0x96,
 193           .reqs = {7, 8},
 194           .direct = EFX_DIR_OUT,
 195           .params = 1,
 196           .def_vals = {0x3F800000, 0x3F266666}
 197         },
 198         { .name = "Dialog Plus",
 199           .nid = DIALOG_PLUS,
 200           .mid = 0x96,
 201           .reqs = {2, 3},
 202           .direct = EFX_DIR_OUT,
 203           .params = 1,
 204           .def_vals = {0x00000000, 0x3F000000}
 205         },
 206         { .name = "Smart Volume",
 207           .nid = SMART_VOLUME,
 208           .mid = 0x96,
 209           .reqs = {4, 5, 6},
 210           .direct = EFX_DIR_OUT,
 211           .params = 2,
 212           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 213         },
 214         { .name = "X-Bass",
 215           .nid = X_BASS,
 216           .mid = 0x96,
 217           .reqs = {24, 23, 25},
 218           .direct = EFX_DIR_OUT,
 219           .params = 2,
 220           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 221         },
 222         { .name = "Equalizer",
 223           .nid = EQUALIZER,
 224           .mid = 0x96,
 225           .reqs = {9, 10, 11, 12, 13, 14,
 226                         15, 16, 17, 18, 19, 20},
 227           .direct = EFX_DIR_OUT,
 228           .params = 11,
 229           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 230                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 231                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 232         },
 233         { .name = "Echo Cancellation",
 234           .nid = ECHO_CANCELLATION,
 235           .mid = 0x95,
 236           .reqs = {0, 1, 2, 3},
 237           .direct = EFX_DIR_IN,
 238           .params = 3,
 239           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 240         },
 241         { .name = "Voice Focus",
 242           .nid = VOICE_FOCUS,
 243           .mid = 0x95,
 244           .reqs = {6, 7, 8, 9},
 245           .direct = EFX_DIR_IN,
 246           .params = 3,
 247           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 248         },
 249         { .name = "Mic SVM",
 250           .nid = MIC_SVM,
 251           .mid = 0x95,
 252           .reqs = {44, 45},
 253           .direct = EFX_DIR_IN,
 254           .params = 1,
 255           .def_vals = {0x00000000, 0x3F3D70A4}
 256         },
 257         { .name = "Noise Reduction",
 258           .nid = NOISE_REDUCTION,
 259           .mid = 0x95,
 260           .reqs = {4, 5},
 261           .direct = EFX_DIR_IN,
 262           .params = 1,
 263           .def_vals = {0x3F800000, 0x3F000000}
 264         },
 265         { .name = "VoiceFX",
 266           .nid = VOICEFX,
 267           .mid = 0x95,
 268           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 269           .direct = EFX_DIR_IN,
 270           .params = 8,
 271           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 272                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 273                        0x00000000}
 274         }
 275 };
 276
 277 /* Tuning controls */
 278 #ifdef ENABLE_TUNING_CONTROLS
 279
 280 enum {
 281 #define TUNING_CTL_START_NID  0xC0
 282         WEDGE_ANGLE = TUNING_CTL_START_NID,
 283         SVM_LEVEL,
 284         EQUALIZER_BAND_0,
 285         EQUALIZER_BAND_1,
 286         EQUALIZER_BAND_2,
 287         EQUALIZER_BAND_3,
 288         EQUALIZER_BAND_4,
 289         EQUALIZER_BAND_5,
 290         EQUALIZER_BAND_6,
 291         EQUALIZER_BAND_7,
 292         EQUALIZER_BAND_8,
 293         EQUALIZER_BAND_9,
 294         TUNING_CTL_END_NID
 295 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 296 };
 297
 298 struct ct_tuning_ctl {
 299         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 300         hda_nid_t parent_nid;
 301         hda_nid_t nid;
 302         int mid; /*effect module ID*/
 303         int req; /*effect module request*/
 304         int direct; /* 0:output; 1:input*/
 305         unsigned int def_val;/*effect default values*/
 306 };
 307
 308 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 309         { .name = "Wedge Angle",
 310           .parent_nid = VOICE_FOCUS,
 311           .nid = WEDGE_ANGLE,
 312           .mid = 0x95,
 313           .req = 8,
 314           .direct = EFX_DIR_IN,
 315           .def_val = 0x41F00000
 316         },
 317         { .name = "SVM Level",
 318           .parent_nid = MIC_SVM,
 319           .nid = SVM_LEVEL,
 320           .mid = 0x95,
 321           .req = 45,
 322           .direct = EFX_DIR_IN,
 323           .def_val = 0x3F3D70A4
 324         },
 325         { .name = "EQ Band0",
 326           .parent_nid = EQUALIZER,
 327           .nid = EQUALIZER_BAND_0,
 328           .mid = 0x96,
 329           .req = 11,
 330           .direct = EFX_DIR_OUT,
 331           .def_val = 0x00000000
 332         },
 333         { .name = "EQ Band1",
 334           .parent_nid = EQUALIZER,
 335           .nid = EQUALIZER_BAND_1,
 336           .mid = 0x96,
 337           .req = 12,
 338           .direct = EFX_DIR_OUT,
 339           .def_val = 0x00000000
 340         },
 341         { .name = "EQ Band2",
 342           .parent_nid = EQUALIZER,
 343           .nid = EQUALIZER_BAND_2,
 344           .mid = 0x96,
 345           .req = 13,
 346           .direct = EFX_DIR_OUT,
 347           .def_val = 0x00000000
 348         },
 349         { .name = "EQ Band3",
 350           .parent_nid = EQUALIZER,
 351           .nid = EQUALIZER_BAND_3,
 352           .mid = 0x96,
 353           .req = 14,
 354           .direct = EFX_DIR_OUT,
 355           .def_val = 0x00000000
 356         },
 357         { .name = "EQ Band4",
 358           .parent_nid = EQUALIZER,
 359           .nid = EQUALIZER_BAND_4,
 360           .mid = 0x96,
 361           .req = 15,
 362           .direct = EFX_DIR_OUT,
 363           .def_val = 0x00000000
 364         },
 365         { .name = "EQ Band5",
 366           .parent_nid = EQUALIZER,
 367           .nid = EQUALIZER_BAND_5,
 368           .mid = 0x96,
 369           .req = 16,
 370           .direct = EFX_DIR_OUT,
 371           .def_val = 0x00000000
 372         },
 373         { .name = "EQ Band6",
 374           .parent_nid = EQUALIZER,
 375           .nid = EQUALIZER_BAND_6,
 376           .mid = 0x96,
 377           .req = 17,
 378           .direct = EFX_DIR_OUT,
 379           .def_val = 0x00000000
 380         },
 381         { .name = "EQ Band7",
 382           .parent_nid = EQUALIZER,
 383           .nid = EQUALIZER_BAND_7,
 384           .mid = 0x96,
 385           .req = 18,
 386           .direct = EFX_DIR_OUT,
 387           .def_val = 0x00000000
 388         },
 389         { .name = "EQ Band8",
 390           .parent_nid = EQUALIZER,
 391           .nid = EQUALIZER_BAND_8,
 392           .mid = 0x96,
 393           .req = 19,
 394           .direct = EFX_DIR_OUT,
 395           .def_val = 0x00000000
 396         },
 397         { .name = "EQ Band9",
 398           .parent_nid = EQUALIZER,
 399           .nid = EQUALIZER_BAND_9,
 400           .mid = 0x96,
 401           .req = 20,
 402           .direct = EFX_DIR_OUT,
 403           .def_val = 0x00000000
 404         }
 405 };
 406 #endif
 407
 408 /* Voice FX Presets */
 409 #define VOICEFX_MAX_PARAM_COUNT 9
 410
 411 struct ct_voicefx {
 412         char *name;
 413         hda_nid_t nid;
 414         int mid;
 415         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 416 };
 417
 418 struct ct_voicefx_preset {
 419         char *name; /*preset name*/
 420         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 421 };
 422
 423 static const struct ct_voicefx ca0132_voicefx = {
 424         .name = "VoiceFX Capture Switch",
 425         .nid = VOICEFX,
 426         .mid = 0x95,
 427         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 428 };
 429
 430 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 431         { .name = "Neutral",
 432           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 433                     0x44FA0000, 0x3F800000, 0x3F800000,
 434                     0x3F800000, 0x00000000, 0x00000000 }
 435         },
 436         { .name = "Female2Male",
 437           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 438                     0x44FA0000, 0x3F19999A, 0x3F866666,
 439                     0x3F800000, 0x00000000, 0x00000000 }
 440         },
 441         { .name = "Male2Female",
 442           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 443                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 444                     0x3F800000, 0x00000000, 0x00000000 }
 445         },
 446         { .name = "ScrappyKid",
 447           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 448                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 449                     0x3F800000, 0x00000000, 0x00000000 }
 450         },
 451         { .name = "Elderly",
 452           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 453                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 454                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 455         },
 456         { .name = "Orc",
 457           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 458                     0x45098000, 0x3F266666, 0x3FC00000,
 459                     0x3F800000, 0x00000000, 0x00000000 }
 460         },
 461         { .name = "Elf",
 462           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 463                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 464                     0x3F800000, 0x00000000, 0x00000000 }
 465         },
 466         { .name = "Dwarf",
 467           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 468                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 469                     0x3F800000, 0x00000000, 0x00000000 }
 470         },
 471         { .name = "AlienBrute",
 472           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 473                     0x451F6000, 0x3F266666, 0x3FA7D945,
 474                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 475         },
 476         { .name = "Robot",
 477           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 478                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 479                     0xBC07010E, 0x00000000, 0x00000000 }
 480         },
 481         { .name = "Marine",
 482           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 483                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 484                     0x3F0A3D71, 0x00000000, 0x00000000 }
 485         },
 486         { .name = "Emo",
 487           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 488                     0x44FA0000, 0x3F800000, 0x3F800000,
 489                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 490         },
 491         { .name = "DeepVoice",
 492           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 493                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 494                     0x3F800000, 0x00000000, 0x00000000 }
 495         },
 496         { .name = "Munchkin",
 497           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 498                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 499                     0x3F800000, 0x00000000, 0x00000000 }
 500         }
 501 };
 502
 503 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 504
 505 #define EQ_PRESET_MAX_PARAM_COUNT 11
 506
 507 struct ct_eq {
 508         char *name;
 509         hda_nid_t nid;
 510         int mid;
 511         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 512 };
 513
 514 struct ct_eq_preset {
 515         char *name; /*preset name*/
 516         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 517 };
 518
 519 static const struct ct_eq ca0132_alt_eq_enum = {
 520         .name = "FX: Equalizer Preset Switch",
 521         .nid = EQ_PRESET_ENUM,
 522         .mid = 0x96,
 523         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 524 };
 525
 526
 527 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 528         { .name = "Flat",
 529          .vals = { 0x00000000, 0x00000000, 0x00000000,
 530                    0x00000000, 0x00000000, 0x00000000,
 531                    0x00000000, 0x00000000, 0x00000000,
 532                    0x00000000, 0x00000000            }
 533         },
 534         { .name = "Acoustic",
 535          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 536                    0x40000000, 0x00000000, 0x00000000,
 537                    0x00000000, 0x00000000, 0x40000000,
 538                    0x40000000, 0x40000000            }
 539         },
 540         { .name = "Classical",
 541          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 542                    0x40C00000, 0x40466666, 0x00000000,
 543                    0x00000000, 0x00000000, 0x00000000,
 544                    0x40466666, 0x40466666            }
 545         },
 546         { .name = "Country",
 547          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 548                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 549                    0x00000000, 0x00000000, 0x40000000,
 550                    0x40466666, 0x40800000            }
 551         },
 552         { .name = "Dance",
 553          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 554                    0x40466666, 0x40866666, 0xBF99999A,
 555                    0xBF99999A, 0x00000000, 0x00000000,
 556                    0x40800000, 0x40800000            }
 557         },
 558         { .name = "Jazz",
 559          .vals = { 0x00000000, 0x00000000, 0x00000000,
 560                    0x3F8CCCCD, 0x40800000, 0x40800000,
 561                    0x40800000, 0x00000000, 0x3F8CCCCD,
 562                    0x40466666, 0x40466666            }
 563         },
 564         { .name = "New Age",
 565          .vals = { 0x00000000, 0x00000000, 0x40000000,
 566                    0x40000000, 0x00000000, 0x00000000,
 567                    0x00000000, 0x3F8CCCCD, 0x40000000,
 568                    0x40000000, 0x40000000            }
 569         },
 570         { .name = "Pop",
 571          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 572                    0x40000000, 0x40000000, 0x00000000,
 573                    0xBF99999A, 0xBF99999A, 0x00000000,
 574                    0x40466666, 0x40C00000            }
 575         },
 576         { .name = "Rock",
 577          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 578                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 579                    0xBF99999A, 0x00000000, 0x00000000,
 580                    0x40800000, 0x40800000            }
 581         },
 582         { .name = "Vocal",
 583          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 584                    0xBF99999A, 0x00000000, 0x40466666,
 585                    0x40800000, 0x40466666, 0x00000000,
 586                    0x00000000, 0x3F8CCCCD            }
 587         }
 588 };
 589
 590 /* DSP command sequences for ca0132_alt_select_out */
 591 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
 592 struct ca0132_alt_out_set {
 593         char *name; /*preset name*/
 594         unsigned char commands;
 595         unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
 596         unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
 597         unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
 598 };
 599
 600 static const struct ca0132_alt_out_set alt_out_presets[] = {
 601         { .name = "Line Out",
 602           .commands = 7,
 603           .mids = { 0x96, 0x96, 0x96, 0x8F,
 604                     0x96, 0x96, 0x96 },
 605           .reqs = { 0x19, 0x17, 0x18, 0x01,
 606                     0x1F, 0x15, 0x3A },
 607           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 608                     0x00000000, 0x00000000, 0x00000000,
 609                     0x00000000 }
 610         },
 611         { .name = "Headphone",
 612           .commands = 7,
 613           .mids = { 0x96, 0x96, 0x96, 0x8F,
 614                     0x96, 0x96, 0x96 },
 615           .reqs = { 0x19, 0x17, 0x18, 0x01,
 616                     0x1F, 0x15, 0x3A },
 617           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 618                     0x00000000, 0x00000000, 0x00000000,
 619                     0x00000000 }
 620         },
 621         { .name = "Surround",
 622           .commands = 8,
 623           .mids = { 0x96, 0x8F, 0x96, 0x96,
 624                     0x96, 0x96, 0x96, 0x96 },
 625           .reqs = { 0x18, 0x01, 0x1F, 0x15,
 626                     0x3A, 0x1A, 0x1B, 0x1C },
 627           .vals = { 0x00000000, 0x00000000, 0x00000000,
 628                     0x00000000, 0x00000000, 0x00000000,
 629                     0x00000000, 0x00000000 }
 630         }
 631 };
 632
 633 /*
 634  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 635  * and I don't know what the third req is, but it's always zero. I assume it's
 636  * some sort of update or set command to tell the DSP there's new volume info.
 637  */
 638 #define DSP_VOL_OUT 0
 639 #define DSP_VOL_IN  1
 640
 641 struct ct_dsp_volume_ctl {
 642         hda_nid_t vnid;
 643         int mid; /* module ID*/
 644         unsigned int reqs[3]; /* scp req ID */
 645 };
 646
 647 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 648         { .vnid = VNID_SPK,
 649           .mid = 0x32,
 650           .reqs = {3, 4, 2}
 651         },
 652         { .vnid = VNID_MIC,
 653           .mid = 0x37,
 654           .reqs = {2, 3, 1}
 655         }
 656 };
 657
 658 /* Values for ca0113_mmio_command_set for selecting output. */
 659 #define AE5_CA0113_OUT_SET_COMMANDS 6
 660 struct ae5_ca0113_output_set {
 661         unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
 662         unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
 663         unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
 664 };
 665
 666 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
 667         { .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 668           .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 669           .vals =   { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
 670         },
 671         { .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 672           .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 673           .vals =   { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
 674         },
 675         { .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 676           .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 677           .vals =   { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
 678         }
 679 };
 680
 681 /* ae5 ca0113 command sequences to set headphone gain levels. */
 682 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
 683 struct ae5_headphone_gain_set {
 684         char *name;
 685         unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
 686 };
 687
 688 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
 689         { .name = "Low (16-31",
 690           .vals = { 0xff, 0x2c, 0xf5, 0x32 }
 691         },
 692         { .name = "Medium (32-149",
 693           .vals = { 0x38, 0xa8, 0x3e, 0x4c }
 694         },
 695         { .name = "High (150-600",
 696           .vals = { 0xff, 0xff, 0xff, 0x7f }
 697         }
 698 };
 699
 700 struct ae5_filter_set {
 701         char *name;
 702         unsigned int val;
 703 };
 704
 705 static const struct ae5_filter_set ae5_filter_presets[] = {
 706         { .name = "Slow Roll Off",
 707           .val = 0xa0
 708         },
 709         { .name = "Minimum Phase",
 710           .val = 0xc0
 711         },
 712         { .name = "Fast Roll Off",
 713           .val = 0x80
 714         }
 715 };
 716
 717 enum hda_cmd_vendor_io {
 718         /* for DspIO node */
 719         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 720         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 721
 722         VENDOR_DSPIO_STATUS                  = 0xF01,
 723         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 724         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 725         VENDOR_DSPIO_DSP_INIT                = 0x703,
 726         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 727         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 728
 729         /* for ChipIO node */
 730         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 731         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 732         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 733         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 734         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 735
 736         VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
 737         VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
 738
 739         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 740         VENDOR_CHIPIO_STATUS                 = 0xF01,
 741         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 742         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 743
 744         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 745         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 746         VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
 747         VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
 748         VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
 749
 750         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 751         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 752
 753         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 754         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 755         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 756         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 757         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 758         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 759         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 760         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 761
 762         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 763         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 764         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 765         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 766
 767         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 768         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 769         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 770         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 771
 772         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 773         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 774         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 775         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 776         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 777         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 778
 779         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 780 };
 781
 782 /*
 783  *  Control flag IDs
 784  */
 785 enum control_flag_id {
 786         /* Connection manager stream setup is bypassed/enabled */
 787         CONTROL_FLAG_C_MGR                  = 0,
 788         /* DSP DMA is bypassed/enabled */
 789         CONTROL_FLAG_DMA                    = 1,
 790         /* 8051 'idle' mode is disabled/enabled */
 791         CONTROL_FLAG_IDLE_ENABLE            = 2,
 792         /* Tracker for the SPDIF-in path is bypassed/enabled */
 793         CONTROL_FLAG_TRACKER                = 3,
 794         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 795         CONTROL_FLAG_SPDIF2OUT              = 4,
 796         /* Digital Microphone is disabled/enabled */
 797         CONTROL_FLAG_DMIC                   = 5,
 798         /* ADC_B rate is 48 kHz/96 kHz */
 799         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 800         /* ADC_C rate is 48 kHz/96 kHz */
 801         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 802         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 803         CONTROL_FLAG_DAC_96KHZ              = 8,
 804         /* DSP rate is 48 kHz/96 kHz */
 805         CONTROL_FLAG_DSP_96KHZ              = 9,
 806         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 807         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 808         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 809         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 810         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 811         CONTROL_FLAG_DECODE_LOOP            = 12,
 812         /* De-emphasis filter on DAC-1 disabled/enabled */
 813         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 814         /* De-emphasis filter on DAC-2 disabled/enabled */
 815         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 816         /* De-emphasis filter on DAC-3 disabled/enabled */
 817         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 818         /* High-pass filter on ADC_B disabled/enabled */
 819         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 820         /* High-pass filter on ADC_C disabled/enabled */
 821         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 822         /* Common mode on Port_A disabled/enabled */
 823         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 824         /* Common mode on Port_D disabled/enabled */
 825         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 826         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 827         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 828         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 829         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 830         /* ASI rate is 48kHz/96kHz */
 831         CONTROL_FLAG_ASI_96KHZ              = 22,
 832         /* DAC power settings able to control attached ports no/yes */
 833         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 834         /* Clock Stop OK reporting is disabled/enabled */
 835         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 836         /* Number of control flags */
 837         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 838 };
 839
 840 /*
 841  * Control parameter IDs
 842  */
 843 enum control_param_id {
 844         /* 0: None, 1: Mic1In*/
 845         CONTROL_PARAM_VIP_SOURCE               = 1,
 846         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 847         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 848         /* Port A output stage gain setting to use when 16 Ohm output
 849          * impedance is selected*/
 850         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 851         /* Port D output stage gain setting to use when 16 Ohm output
 852          * impedance is selected*/
 853         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 854
 855         /*
 856          * This control param name was found in the 8051 memory, and makes
 857          * sense given the fact the AE-5 uses it and has the ASI flag set.
 858          */
 859         CONTROL_PARAM_ASI                      = 23,
 860
 861         /* Stream Control */
 862
 863         /* Select stream with the given ID */
 864         CONTROL_PARAM_STREAM_ID                = 24,
 865         /* Source connection point for the selected stream */
 866         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 867         /* Destination connection point for the selected stream */
 868         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 869         /* Number of audio channels in the selected stream */
 870         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 871         /*Enable control for the selected stream */
 872         CONTROL_PARAM_STREAM_CONTROL           = 28,
 873
 874         /* Connection Point Control */
 875
 876         /* Select connection point with the given ID */
 877         CONTROL_PARAM_CONN_POINT_ID            = 29,
 878         /* Connection point sample rate */
 879         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 880
 881         /* Node Control */
 882
 883         /* Select HDA node with the given ID */
 884         CONTROL_PARAM_NODE_ID                  = 31
 885 };
 886
 887 /*
 888  *  Dsp Io Status codes
 889  */
 890 enum hda_vendor_status_dspio {
 891         /* Success */
 892         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 893         /* Busy, unable to accept new command, the host must retry */
 894         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 895         /* SCP command queue is full */
 896         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 897         /* SCP response queue is empty */
 898         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 899 };
 900
 901 /*
 902  *  Chip Io Status codes
 903  */
 904 enum hda_vendor_status_chipio {
 905         /* Success */
 906         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 907         /* Busy, unable to accept new command, the host must retry */
 908         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 909 };
 910
 911 /*
 912  *  CA0132 sample rate
 913  */
 914 enum ca0132_sample_rate {
 915         SR_6_000        = 0x00,
 916         SR_8_000        = 0x01,
 917         SR_9_600        = 0x02,
 918         SR_11_025       = 0x03,
 919         SR_16_000       = 0x04,
 920         SR_22_050       = 0x05,
 921         SR_24_000       = 0x06,
 922         SR_32_000       = 0x07,
 923         SR_44_100       = 0x08,
 924         SR_48_000       = 0x09,
 925         SR_88_200       = 0x0A,
 926         SR_96_000       = 0x0B,
 927         SR_144_000      = 0x0C,
 928         SR_176_400      = 0x0D,
 929         SR_192_000      = 0x0E,
 930         SR_384_000      = 0x0F,
 931
 932         SR_COUNT        = 0x10,
 933
 934         SR_RATE_UNKNOWN = 0x1F
 935 };
 936
 937 enum dsp_download_state {
 938         DSP_DOWNLOAD_FAILED = -1,
 939         DSP_DOWNLOAD_INIT   = 0,
 940         DSP_DOWNLOADING     = 1,
 941         DSP_DOWNLOADED      = 2
 942 };
 943
 944 /* retrieve parameters from hda format */
 945 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 946 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 947 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 948 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 949
 950 /*
 951  * CA0132 specific
 952  */
 953
 954 struct ca0132_spec {
 955         const struct snd_kcontrol_new *mixers[5];
 956         unsigned int num_mixers;
 957         const struct hda_verb *base_init_verbs;
 958         const struct hda_verb *base_exit_verbs;
 959         const struct hda_verb *chip_init_verbs;
 960         const struct hda_verb *desktop_init_verbs;
 961         struct hda_verb *spec_init_verbs;
 962         struct auto_pin_cfg autocfg;
 963
 964         /* Nodes configurations */
 965         struct hda_multi_out multiout;
 966         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 967         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 968         unsigned int num_outputs;
 969         hda_nid_t input_pins[AUTO_PIN_LAST];
 970         hda_nid_t adcs[AUTO_PIN_LAST];
 971         hda_nid_t dig_out;
 972         hda_nid_t dig_in;
 973         unsigned int num_inputs;
 974         hda_nid_t shared_mic_nid;
 975         hda_nid_t shared_out_nid;
 976         hda_nid_t unsol_tag_hp;
 977         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
 978         hda_nid_t unsol_tag_amic1;
 979
 980         /* chip access */
 981         struct mutex chipio_mutex; /* chip access mutex */
 982         u32 curr_chip_addx;
 983
 984         /* DSP download related */
 985         enum dsp_download_state dsp_state;
 986         unsigned int dsp_stream_id;
 987         unsigned int wait_scp;
 988         unsigned int wait_scp_header;
 989         unsigned int wait_num_data;
 990         unsigned int scp_resp_header;
 991         unsigned int scp_resp_data[4];
 992         unsigned int scp_resp_count;
 993         bool startup_check_entered;
 994         bool dsp_reload;
 995
 996         /* mixer and effects related */
 997         unsigned char dmic_ctl;
 998         int cur_out_type;
 999         int cur_mic_type;
1000         long vnode_lvol[VNODES_COUNT];
1001         long vnode_rvol[VNODES_COUNT];
1002         long vnode_lswitch[VNODES_COUNT];
1003         long vnode_rswitch[VNODES_COUNT];
1004         long effects_switch[EFFECTS_COUNT];
1005         long voicefx_val;
1006         long cur_mic_boost;
1007         /* ca0132_alt control related values */
1008         unsigned char in_enum_val;
1009         unsigned char out_enum_val;
1010         unsigned char mic_boost_enum_val;
1011         unsigned char smart_volume_setting;
1012         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1013         long xbass_xover_freq;
1014         long eq_preset_val;
1015         unsigned int tlv[4];
1016         struct hda_vmaster_mute_hook vmaster_mute;
1017         /* AE-5 Control values */
1018         unsigned char ae5_headphone_gain_val;
1019         unsigned char ae5_filter_val;
1020         /* ZxR Control Values */
1021         unsigned char zxr_gain_set;
1022
1023         struct hda_codec *codec;
1024         struct delayed_work unsol_hp_work;
1025         int quirk;
1026
1027 #ifdef ENABLE_TUNING_CONTROLS
1028         long cur_ctl_vals[TUNING_CTLS_COUNT];
1029 #endif
1030         /*
1031          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1032          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1033          * things.
1034          */
1035         bool use_pci_mmio;
1036         void __iomem *mem_base;
1037
1038         /*
1039          * Whether or not to use the alt functions like alt_select_out,
1040          * alt_select_in, etc. Only used on desktop codecs for now, because of
1041          * surround sound support.
1042          */
1043         bool use_alt_functions;
1044
1045         /*
1046          * Whether or not to use alt controls:  volume effect sliders, EQ
1047          * presets, smart volume presets, and new control names with FX prefix.
1048          * Renames PlayEnhancement and CrystalVoice too.
1049          */
1050         bool use_alt_controls;
1051 };
1052
1053 /*
1054  * CA0132 quirks table
1055  */
1056 enum {
1057         QUIRK_NONE,
1058         QUIRK_ALIENWARE,
1059         QUIRK_ALIENWARE_M17XR4,
1060         QUIRK_SBZ,
1061         QUIRK_ZXR,
1062         QUIRK_ZXR_DBPRO,
1063         QUIRK_R3DI,
1064         QUIRK_R3D,
1065         QUIRK_AE5,
1066         QUIRK_AE7,
1067 };
1068
1069 #ifdef CONFIG_PCI
1070 #define ca0132_quirk(spec)              ((spec)->quirk)
1071 #define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
1072 #define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
1073 #define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
1074 #else
1075 #define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
1076 #define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
1077 #define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
1078 #define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
1079 #endif
1080
1081 static const struct hda_pintbl alienware_pincfgs[] = {
1082         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1083         { 0x0c, 0x411111f0 }, /* N/A */
1084         { 0x0d, 0x411111f0 }, /* N/A */
1085         { 0x0e, 0x411111f0 }, /* N/A */
1086         { 0x0f, 0x0321101f }, /* HP */
1087         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1088         { 0x11, 0x03a11021 }, /* Mic */
1089         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1090         { 0x13, 0x411111f0 }, /* N/A */
1091         { 0x18, 0x411111f0 }, /* N/A */
1092         {}
1093 };
1094
1095 /* Sound Blaster Z pin configs taken from Windows Driver */
1096 static const struct hda_pintbl sbz_pincfgs[] = {
1097         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1098         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1099         { 0x0d, 0x014510f0 }, /* Digital Out */
1100         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1101         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1102         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1103         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1104         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1105         { 0x13, 0x908700f0 }, /* What U Hear In*/
1106         { 0x18, 0x50d000f0 }, /* N/A */
1107         {}
1108 };
1109
1110 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1111 static const struct hda_pintbl zxr_pincfgs[] = {
1112         { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1113         { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1114         { 0x0d, 0x014510f0 }, /* Digital Out */
1115         { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1116         { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1117         { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1118         { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1119         { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1120         { 0x13, 0x908700f0 }, /* What U Hear In*/
1121         { 0x18, 0x50d000f0 }, /* N/A */
1122         {}
1123 };
1124
1125 /* Recon3D pin configs taken from Windows Driver */
1126 static const struct hda_pintbl r3d_pincfgs[] = {
1127         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1128         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1129         { 0x0d, 0x014510f0 }, /* Digital Out */
1130         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1131         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1132         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1133         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1134         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1135         { 0x13, 0x908700f0 }, /* What U Hear In*/
1136         { 0x18, 0x50d000f0 }, /* N/A */
1137         {}
1138 };
1139
1140 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1141 static const struct hda_pintbl ae5_pincfgs[] = {
1142         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1143         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1144         { 0x0d, 0x014510f0 }, /* Digital Out */
1145         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1146         { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1147         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1148         { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1149         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1150         { 0x13, 0x908700f0 }, /* What U Hear In*/
1151         { 0x18, 0x50d000f0 }, /* N/A */
1152         {}
1153 };
1154
1155 /* Recon3D integrated pin configs taken from Windows Driver */
1156 static const struct hda_pintbl r3di_pincfgs[] = {
1157         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1158         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1159         { 0x0d, 0x014510f0 }, /* Digital Out */
1160         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1161         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1162         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1163         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1164         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1165         { 0x13, 0x908700f0 }, /* What U Hear In*/
1166         { 0x18, 0x500000f0 }, /* N/A */
1167         {}
1168 };
1169
1170 static const struct snd_pci_quirk ca0132_quirks[] = {
1171         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1172         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1173         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1174         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1175         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1176         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1177         SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1178         SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1179         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1180         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1181         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1182         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1183         SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1184         SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1185         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1186         SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1187         SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1188         SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1189         SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1190         {}
1191 };
1192
1193 /*
1194  * CA0132 codec access
1195  */
1196 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1197                 unsigned int verb, unsigned int parm, unsigned int *res)
1198 {
1199         unsigned int response;
1200         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1201         *res = response;
1202
1203         return ((response == -1) ? -1 : 0);
1204 }
1205
1206 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1207                 unsigned short converter_format, unsigned int *res)
1208 {
1209         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1210                                 converter_format & 0xffff, res);
1211 }
1212
1213 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1214                                 hda_nid_t nid, unsigned char stream,
1215                                 unsigned char channel, unsigned int *res)
1216 {
1217         unsigned char converter_stream_channel = 0;
1218
1219         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1220         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1221                                 converter_stream_channel, res);
1222 }
1223
1224 /* Chip access helper function */
1225 static int chipio_send(struct hda_codec *codec,
1226                        unsigned int reg,
1227                        unsigned int data)
1228 {
1229         unsigned int res;
1230         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1231
1232         /* send bits of data specified by reg */
1233         do {
1234                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1235                                          reg, data);
1236                 if (res == VENDOR_STATUS_CHIPIO_OK)
1237                         return 0;
1238                 msleep(20);
1239         } while (time_before(jiffies, timeout));
1240
1241         return -EIO;
1242 }
1243
1244 /*
1245  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1246  */
1247 static int chipio_write_address(struct hda_codec *codec,
1248                                 unsigned int chip_addx)
1249 {
1250         struct ca0132_spec *spec = codec->spec;
1251         int res;
1252
1253         if (spec->curr_chip_addx == chip_addx)
1254                         return 0;
1255
1256         /* send low 16 bits of the address */
1257         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1258                           chip_addx & 0xffff);
1259
1260         if (res != -EIO) {
1261                 /* send high 16 bits of the address */
1262                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1263                                   chip_addx >> 16);
1264         }
1265
1266         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1267
1268         return res;
1269 }
1270
1271 /*
1272  * Write data through the vendor widget -- NOT protected by the Mutex!
1273  */
1274 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1275 {
1276         struct ca0132_spec *spec = codec->spec;
1277         int res;
1278
1279         /* send low 16 bits of the data */
1280         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1281
1282         if (res != -EIO) {
1283                 /* send high 16 bits of the data */
1284                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1285                                   data >> 16);
1286         }
1287
1288         /*If no error encountered, automatically increment the address
1289         as per chip behaviour*/
1290         spec->curr_chip_addx = (res != -EIO) ?
1291                                         (spec->curr_chip_addx + 4) : ~0U;
1292         return res;
1293 }
1294
1295 /*
1296  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1297  */
1298 static int chipio_write_data_multiple(struct hda_codec *codec,
1299                                       const u32 *data,
1300                                       unsigned int count)
1301 {
1302         int status = 0;
1303
1304         if (data == NULL) {
1305                 codec_dbg(codec, "chipio_write_data null ptr\n");
1306                 return -EINVAL;
1307         }
1308
1309         while ((count-- != 0) && (status == 0))
1310                 status = chipio_write_data(codec, *data++);
1311
1312         return status;
1313 }
1314
1315
1316 /*
1317  * Read data through the vendor widget -- NOT protected by the Mutex!
1318  */
1319 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1320 {
1321         struct ca0132_spec *spec = codec->spec;
1322         int res;
1323
1324         /* post read */
1325         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1326
1327         if (res != -EIO) {
1328                 /* read status */
1329                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1330         }
1331
1332         if (res != -EIO) {
1333                 /* read data */
1334                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1335                                            VENDOR_CHIPIO_HIC_READ_DATA,
1336                                            0);
1337         }
1338
1339         /*If no error encountered, automatically increment the address
1340         as per chip behaviour*/
1341         spec->curr_chip_addx = (res != -EIO) ?
1342                                         (spec->curr_chip_addx + 4) : ~0U;
1343         return res;
1344 }
1345
1346 /*
1347  * Write given value to the given address through the chip I/O widget.
1348  * protected by the Mutex
1349  */
1350 static int chipio_write(struct hda_codec *codec,
1351                 unsigned int chip_addx, const unsigned int data)
1352 {
1353         struct ca0132_spec *spec = codec->spec;
1354         int err;
1355
1356         mutex_lock(&spec->chipio_mutex);
1357
1358         /* write the address, and if successful proceed to write data */
1359         err = chipio_write_address(codec, chip_addx);
1360         if (err < 0)
1361                 goto exit;
1362
1363         err = chipio_write_data(codec, data);
1364         if (err < 0)
1365                 goto exit;
1366
1367 exit:
1368         mutex_unlock(&spec->chipio_mutex);
1369         return err;
1370 }
1371
1372 /*
1373  * Write given value to the given address through the chip I/O widget.
1374  * not protected by the Mutex
1375  */
1376 static int chipio_write_no_mutex(struct hda_codec *codec,
1377                 unsigned int chip_addx, const unsigned int data)
1378 {
1379         int err;
1380
1381
1382         /* write the address, and if successful proceed to write data */
1383         err = chipio_write_address(codec, chip_addx);
1384         if (err < 0)
1385                 goto exit;
1386
1387         err = chipio_write_data(codec, data);
1388         if (err < 0)
1389                 goto exit;
1390
1391 exit:
1392         return err;
1393 }
1394
1395 /*
1396  * Write multiple values to the given address through the chip I/O widget.
1397  * protected by the Mutex
1398  */
1399 static int chipio_write_multiple(struct hda_codec *codec,
1400                                  u32 chip_addx,
1401                                  const u32 *data,
1402                                  unsigned int count)
1403 {
1404         struct ca0132_spec *spec = codec->spec;
1405         int status;
1406
1407         mutex_lock(&spec->chipio_mutex);
1408         status = chipio_write_address(codec, chip_addx);
1409         if (status < 0)
1410                 goto error;
1411
1412         status = chipio_write_data_multiple(codec, data, count);
1413 error:
1414         mutex_unlock(&spec->chipio_mutex);
1415
1416         return status;
1417 }
1418
1419 /*
1420  * Read the given address through the chip I/O widget
1421  * protected by the Mutex
1422  */
1423 static int chipio_read(struct hda_codec *codec,
1424                 unsigned int chip_addx, unsigned int *data)
1425 {
1426         struct ca0132_spec *spec = codec->spec;
1427         int err;
1428
1429         mutex_lock(&spec->chipio_mutex);
1430
1431         /* write the address, and if successful proceed to write data */
1432         err = chipio_write_address(codec, chip_addx);
1433         if (err < 0)
1434                 goto exit;
1435
1436         err = chipio_read_data(codec, data);
1437         if (err < 0)
1438                 goto exit;
1439
1440 exit:
1441         mutex_unlock(&spec->chipio_mutex);
1442         return err;
1443 }
1444
1445 /*
1446  * Set chip control flags through the chip I/O widget.
1447  */
1448 static void chipio_set_control_flag(struct hda_codec *codec,
1449                                     enum control_flag_id flag_id,
1450                                     bool flag_state)
1451 {
1452         unsigned int val;
1453         unsigned int flag_bit;
1454
1455         flag_bit = (flag_state ? 1 : 0);
1456         val = (flag_bit << 7) | (flag_id);
1457         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1458                             VENDOR_CHIPIO_FLAG_SET, val);
1459 }
1460
1461 /*
1462  * Set chip parameters through the chip I/O widget.
1463  */
1464 static void chipio_set_control_param(struct hda_codec *codec,
1465                 enum control_param_id param_id, int param_val)
1466 {
1467         struct ca0132_spec *spec = codec->spec;
1468         int val;
1469
1470         if ((param_id < 32) && (param_val < 8)) {
1471                 val = (param_val << 5) | (param_id);
1472                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473                                     VENDOR_CHIPIO_PARAM_SET, val);
1474         } else {
1475                 mutex_lock(&spec->chipio_mutex);
1476                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1477                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1478                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1479                                             param_id);
1480                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1481                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1482                                             param_val);
1483                 }
1484                 mutex_unlock(&spec->chipio_mutex);
1485         }
1486 }
1487
1488 /*
1489  * Set chip parameters through the chip I/O widget. NO MUTEX.
1490  */
1491 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1492                 enum control_param_id param_id, int param_val)
1493 {
1494         int val;
1495
1496         if ((param_id < 32) && (param_val < 8)) {
1497                 val = (param_val << 5) | (param_id);
1498                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1499                                     VENDOR_CHIPIO_PARAM_SET, val);
1500         } else {
1501                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1502                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1503                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1504                                             param_id);
1505                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1506                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1507                                             param_val);
1508                 }
1509         }
1510 }
1511 /*
1512  * Connect stream to a source point, and then connect
1513  * that source point to a destination point.
1514  */
1515 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1516                                 int streamid, int source_point, int dest_point)
1517 {
1518         chipio_set_control_param_no_mutex(codec,
1519                         CONTROL_PARAM_STREAM_ID, streamid);
1520         chipio_set_control_param_no_mutex(codec,
1521                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1522         chipio_set_control_param_no_mutex(codec,
1523                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1524 }
1525
1526 /*
1527  * Set number of channels in the selected stream.
1528  */
1529 static void chipio_set_stream_channels(struct hda_codec *codec,
1530                                 int streamid, unsigned int channels)
1531 {
1532         chipio_set_control_param_no_mutex(codec,
1533                         CONTROL_PARAM_STREAM_ID, streamid);
1534         chipio_set_control_param_no_mutex(codec,
1535                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1536 }
1537
1538 /*
1539  * Enable/Disable audio stream.
1540  */
1541 static void chipio_set_stream_control(struct hda_codec *codec,
1542                                 int streamid, int enable)
1543 {
1544         chipio_set_control_param_no_mutex(codec,
1545                         CONTROL_PARAM_STREAM_ID, streamid);
1546         chipio_set_control_param_no_mutex(codec,
1547                         CONTROL_PARAM_STREAM_CONTROL, enable);
1548 }
1549
1550
1551 /*
1552  * Set sampling rate of the connection point. NO MUTEX.
1553  */
1554 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1555                                 int connid, enum ca0132_sample_rate rate)
1556 {
1557         chipio_set_control_param_no_mutex(codec,
1558                         CONTROL_PARAM_CONN_POINT_ID, connid);
1559         chipio_set_control_param_no_mutex(codec,
1560                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1561 }
1562
1563 /*
1564  * Set sampling rate of the connection point.
1565  */
1566 static void chipio_set_conn_rate(struct hda_codec *codec,
1567                                 int connid, enum ca0132_sample_rate rate)
1568 {
1569         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1570         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1571                                  rate);
1572 }
1573
1574 /*
1575  * Writes to the 8051's internal address space directly instead of indirectly,
1576  * giving access to the special function registers located at addresses
1577  * 0x80-0xFF.
1578  */
1579 static void chipio_8051_write_direct(struct hda_codec *codec,
1580                 unsigned int addr, unsigned int data)
1581 {
1582         unsigned int verb;
1583
1584         verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1585         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1586 }
1587
1588 /*
1589  * Enable clocks.
1590  */
1591 static void chipio_enable_clocks(struct hda_codec *codec)
1592 {
1593         struct ca0132_spec *spec = codec->spec;
1594
1595         mutex_lock(&spec->chipio_mutex);
1596         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1597                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1598         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1599                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1600         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1601                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1602         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1603                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1604         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1605                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1606         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1607                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1608         mutex_unlock(&spec->chipio_mutex);
1609 }
1610
1611 /*
1612  * CA0132 DSP IO stuffs
1613  */
1614 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1615                       unsigned int data)
1616 {
1617         int res;
1618         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1619
1620         /* send bits of data specified by reg to dsp */
1621         do {
1622                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1623                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1624                         return res;
1625                 msleep(20);
1626         } while (time_before(jiffies, timeout));
1627
1628         return -EIO;
1629 }
1630
1631 /*
1632  * Wait for DSP to be ready for commands
1633  */
1634 static void dspio_write_wait(struct hda_codec *codec)
1635 {
1636         int status;
1637         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1638
1639         do {
1640                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1641                                                 VENDOR_DSPIO_STATUS, 0);
1642                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1643                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1644                         break;
1645                 msleep(1);
1646         } while (time_before(jiffies, timeout));
1647 }
1648
1649 /*
1650  * Write SCP data to DSP
1651  */
1652 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1653 {
1654         struct ca0132_spec *spec = codec->spec;
1655         int status;
1656
1657         dspio_write_wait(codec);
1658
1659         mutex_lock(&spec->chipio_mutex);
1660         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1661                             scp_data & 0xffff);
1662         if (status < 0)
1663                 goto error;
1664
1665         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1666                                     scp_data >> 16);
1667         if (status < 0)
1668                 goto error;
1669
1670         /* OK, now check if the write itself has executed*/
1671         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1672                                     VENDOR_DSPIO_STATUS, 0);
1673 error:
1674         mutex_unlock(&spec->chipio_mutex);
1675
1676         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1677                         -EIO : 0;
1678 }
1679
1680 /*
1681  * Write multiple SCP data to DSP
1682  */
1683 static int dspio_write_multiple(struct hda_codec *codec,
1684                                 unsigned int *buffer, unsigned int size)
1685 {
1686         int status = 0;
1687         unsigned int count;
1688
1689         if (buffer == NULL)
1690                 return -EINVAL;
1691
1692         count = 0;
1693         while (count < size) {
1694                 status = dspio_write(codec, *buffer++);
1695                 if (status != 0)
1696                         break;
1697                 count++;
1698         }
1699
1700         return status;
1701 }
1702
1703 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1704 {
1705         int status;
1706
1707         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1708         if (status == -EIO)
1709                 return status;
1710
1711         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1712         if (status == -EIO ||
1713             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1714                 return -EIO;
1715
1716         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1717                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1718
1719         return 0;
1720 }
1721
1722 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1723                                unsigned int *buf_size, unsigned int size_count)
1724 {
1725         int status = 0;
1726         unsigned int size = *buf_size;
1727         unsigned int count;
1728         unsigned int skip_count;
1729         unsigned int dummy;
1730
1731         if (buffer == NULL)
1732                 return -1;
1733
1734         count = 0;
1735         while (count < size && count < size_count) {
1736                 status = dspio_read(codec, buffer++);
1737                 if (status != 0)
1738                         break;
1739                 count++;
1740         }
1741
1742         skip_count = count;
1743         if (status == 0) {
1744                 while (skip_count < size) {
1745                         status = dspio_read(codec, &dummy);
1746                         if (status != 0)
1747                                 break;
1748                         skip_count++;
1749                 }
1750         }
1751         *buf_size = count;
1752
1753         return status;
1754 }
1755
1756 /*
1757  * Construct the SCP header using corresponding fields
1758  */
1759 static inline unsigned int
1760 make_scp_header(unsigned int target_id, unsigned int source_id,
1761                 unsigned int get_flag, unsigned int req,
1762                 unsigned int device_flag, unsigned int resp_flag,
1763                 unsigned int error_flag, unsigned int data_size)
1764 {
1765         unsigned int header = 0;
1766
1767         header = (data_size & 0x1f) << 27;
1768         header |= (error_flag & 0x01) << 26;
1769         header |= (resp_flag & 0x01) << 25;
1770         header |= (device_flag & 0x01) << 24;
1771         header |= (req & 0x7f) << 17;
1772         header |= (get_flag & 0x01) << 16;
1773         header |= (source_id & 0xff) << 8;
1774         header |= target_id & 0xff;
1775
1776         return header;
1777 }
1778
1779 /*
1780  * Extract corresponding fields from SCP header
1781  */
1782 static inline void
1783 extract_scp_header(unsigned int header,
1784                    unsigned int *target_id, unsigned int *source_id,
1785                    unsigned int *get_flag, unsigned int *req,
1786                    unsigned int *device_flag, unsigned int *resp_flag,
1787                    unsigned int *error_flag, unsigned int *data_size)
1788 {
1789         if (data_size)
1790                 *data_size = (header >> 27) & 0x1f;
1791         if (error_flag)
1792                 *error_flag = (header >> 26) & 0x01;
1793         if (resp_flag)
1794                 *resp_flag = (header >> 25) & 0x01;
1795         if (device_flag)
1796                 *device_flag = (header >> 24) & 0x01;
1797         if (req)
1798                 *req = (header >> 17) & 0x7f;
1799         if (get_flag)
1800                 *get_flag = (header >> 16) & 0x01;
1801         if (source_id)
1802                 *source_id = (header >> 8) & 0xff;
1803         if (target_id)
1804                 *target_id = header & 0xff;
1805 }
1806
1807 #define SCP_MAX_DATA_WORDS  (16)
1808
1809 /* Structure to contain any SCP message */
1810 struct scp_msg {
1811         unsigned int hdr;
1812         unsigned int data[SCP_MAX_DATA_WORDS];
1813 };
1814
1815 static void dspio_clear_response_queue(struct hda_codec *codec)
1816 {
1817         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1818         unsigned int dummy = 0;
1819         int status;
1820
1821         /* clear all from the response queue */
1822         do {
1823                 status = dspio_read(codec, &dummy);
1824         } while (status == 0 && time_before(jiffies, timeout));
1825 }
1826
1827 static int dspio_get_response_data(struct hda_codec *codec)
1828 {
1829         struct ca0132_spec *spec = codec->spec;
1830         unsigned int data = 0;
1831         unsigned int count;
1832
1833         if (dspio_read(codec, &data) < 0)
1834                 return -EIO;
1835
1836         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1837                 spec->scp_resp_header = data;
1838                 spec->scp_resp_count = data >> 27;
1839                 count = spec->wait_num_data;
1840                 dspio_read_multiple(codec, spec->scp_resp_data,
1841                                     &spec->scp_resp_count, count);
1842                 return 0;
1843         }
1844
1845         return -EIO;
1846 }
1847
1848 /*
1849  * Send SCP message to DSP
1850  */
1851 static int dspio_send_scp_message(struct hda_codec *codec,
1852                                   unsigned char *send_buf,
1853                                   unsigned int send_buf_size,
1854                                   unsigned char *return_buf,
1855                                   unsigned int return_buf_size,
1856                                   unsigned int *bytes_returned)
1857 {
1858         struct ca0132_spec *spec = codec->spec;
1859         int status = -1;
1860         unsigned int scp_send_size = 0;
1861         unsigned int total_size;
1862         bool waiting_for_resp = false;
1863         unsigned int header;
1864         struct scp_msg *ret_msg;
1865         unsigned int resp_src_id, resp_target_id;
1866         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1867
1868         if (bytes_returned)
1869                 *bytes_returned = 0;
1870
1871         /* get scp header from buffer */
1872         header = *((unsigned int *)send_buf);
1873         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1874                            &device_flag, NULL, NULL, &data_size);
1875         scp_send_size = data_size + 1;
1876         total_size = (scp_send_size * 4);
1877
1878         if (send_buf_size < total_size)
1879                 return -EINVAL;
1880
1881         if (get_flag || device_flag) {
1882                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1883                         return -EINVAL;
1884
1885                 spec->wait_scp_header = *((unsigned int *)send_buf);
1886
1887                 /* swap source id with target id */
1888                 resp_target_id = src_id;
1889                 resp_src_id = target_id;
1890                 spec->wait_scp_header &= 0xffff0000;
1891                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1892                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1893                 spec->wait_scp = 1;
1894                 waiting_for_resp = true;
1895         }
1896
1897         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1898                                       scp_send_size);
1899         if (status < 0) {
1900                 spec->wait_scp = 0;
1901                 return status;
1902         }
1903
1904         if (waiting_for_resp) {
1905                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1906                 memset(return_buf, 0, return_buf_size);
1907                 do {
1908                         msleep(20);
1909                 } while (spec->wait_scp && time_before(jiffies, timeout));
1910                 waiting_for_resp = false;
1911                 if (!spec->wait_scp) {
1912                         ret_msg = (struct scp_msg *)return_buf;
1913                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1914                         memcpy(&ret_msg->data, spec->scp_resp_data,
1915                                spec->wait_num_data);
1916                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1917                         status = 0;
1918                 } else {
1919                         status = -EIO;
1920                 }
1921                 spec->wait_scp = 0;
1922         }
1923
1924         return status;
1925 }
1926
1927 /**
1928  * Prepare and send the SCP message to DSP
1929  * @codec: the HDA codec
1930  * @mod_id: ID of the DSP module to send the command
1931  * @req: ID of request to send to the DSP module
1932  * @dir: SET or GET
1933  * @data: pointer to the data to send with the request, request specific
1934  * @len: length of the data, in bytes
1935  * @reply: point to the buffer to hold data returned for a reply
1936  * @reply_len: length of the reply buffer returned from GET
1937  *
1938  * Returns zero or a negative error code.
1939  */
1940 static int dspio_scp(struct hda_codec *codec,
1941                 int mod_id, int src_id, int req, int dir, const void *data,
1942                 unsigned int len, void *reply, unsigned int *reply_len)
1943 {
1944         int status = 0;
1945         struct scp_msg scp_send, scp_reply;
1946         unsigned int ret_bytes, send_size, ret_size;
1947         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1948         unsigned int reply_data_size;
1949
1950         memset(&scp_send, 0, sizeof(scp_send));
1951         memset(&scp_reply, 0, sizeof(scp_reply));
1952
1953         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1954                 return -EINVAL;
1955
1956         if (dir == SCP_GET && reply == NULL) {
1957                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1958                 return -EINVAL;
1959         }
1960
1961         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1962                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1963                 return -EINVAL;
1964         }
1965
1966         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1967                                        0, 0, 0, len/sizeof(unsigned int));
1968         if (data != NULL && len > 0) {
1969                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1970                 memcpy(scp_send.data, data, len);
1971         }
1972
1973         ret_bytes = 0;
1974         send_size = sizeof(unsigned int) + len;
1975         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1976                                         send_size, (unsigned char *)&scp_reply,
1977                                         sizeof(scp_reply), &ret_bytes);
1978
1979         if (status < 0) {
1980                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1981                 return status;
1982         }
1983
1984         /* extract send and reply headers members */
1985         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1986                            NULL, NULL, NULL, NULL, NULL);
1987         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1988                            &reply_resp_flag, &reply_error_flag,
1989                            &reply_data_size);
1990
1991         if (!send_get_flag)
1992                 return 0;
1993
1994         if (reply_resp_flag && !reply_error_flag) {
1995                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1996                                         / sizeof(unsigned int);
1997
1998                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1999                         codec_dbg(codec, "reply too long for buf\n");
2000                         return -EINVAL;
2001                 } else if (ret_size != reply_data_size) {
2002                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2003                         return -EINVAL;
2004                 } else if (!reply) {
2005                         codec_dbg(codec, "NULL reply\n");
2006                         return -EINVAL;
2007                 } else {
2008                         *reply_len = ret_size*sizeof(unsigned int);
2009                         memcpy(reply, scp_reply.data, *reply_len);
2010                 }
2011         } else {
2012                 codec_dbg(codec, "reply ill-formed or errflag set\n");
2013                 return -EIO;
2014         }
2015
2016         return status;
2017 }
2018
2019 /*
2020  * Set DSP parameters
2021  */
2022 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2023                         int src_id, int req, const void *data, unsigned int len)
2024 {
2025         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2026                         NULL);
2027 }
2028
2029 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2030                         int req, const unsigned int data)
2031 {
2032         return dspio_set_param(codec, mod_id, 0x20, req, &data,
2033                         sizeof(unsigned int));
2034 }
2035
2036 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2037                         int req, const unsigned int data)
2038 {
2039         return dspio_set_param(codec, mod_id, 0x00, req, &data,
2040                         sizeof(unsigned int));
2041 }
2042
2043 /*
2044  * Allocate a DSP DMA channel via an SCP message
2045  */
2046 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2047 {
2048         int status = 0;
2049         unsigned int size = sizeof(*dma_chan);
2050
2051         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2052         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2053                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2054                         dma_chan, &size);
2055
2056         if (status < 0) {
2057                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2058                 return status;
2059         }
2060
2061         if ((*dma_chan + 1) == 0) {
2062                 codec_dbg(codec, "no free dma channels to allocate\n");
2063                 return -EBUSY;
2064         }
2065
2066         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2067         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2068
2069         return status;
2070 }
2071
2072 /*
2073  * Free a DSP DMA via an SCP message
2074  */
2075 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2076 {
2077         int status = 0;
2078         unsigned int dummy = 0;
2079
2080         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2081         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2082
2083         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2084                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2085                         sizeof(dma_chan), NULL, &dummy);
2086
2087         if (status < 0) {
2088                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2089                 return status;
2090         }
2091
2092         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2093
2094         return status;
2095 }
2096
2097 /*
2098  * (Re)start the DSP
2099  */
2100 static int dsp_set_run_state(struct hda_codec *codec)
2101 {
2102         unsigned int dbg_ctrl_reg;
2103         unsigned int halt_state;
2104         int err;
2105
2106         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2107         if (err < 0)
2108                 return err;
2109
2110         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2111                       DSP_DBGCNTL_STATE_LOBIT;
2112
2113         if (halt_state != 0) {
2114                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2115                                   DSP_DBGCNTL_SS_MASK);
2116                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2117                                    dbg_ctrl_reg);
2118                 if (err < 0)
2119                         return err;
2120
2121                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2122                                 DSP_DBGCNTL_EXEC_MASK;
2123                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2124                                    dbg_ctrl_reg);
2125                 if (err < 0)
2126                         return err;
2127         }
2128
2129         return 0;
2130 }
2131
2132 /*
2133  * Reset the DSP
2134  */
2135 static int dsp_reset(struct hda_codec *codec)
2136 {
2137         unsigned int res;
2138         int retry = 20;
2139
2140         codec_dbg(codec, "dsp_reset\n");
2141         do {
2142                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2143                 retry--;
2144         } while (res == -EIO && retry);
2145
2146         if (!retry) {
2147                 codec_dbg(codec, "dsp_reset timeout\n");
2148                 return -EIO;
2149         }
2150
2151         return 0;
2152 }
2153
2154 /*
2155  * Convert chip address to DSP address
2156  */
2157 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2158                                         bool *code, bool *yram)
2159 {
2160         *code = *yram = false;
2161
2162         if (UC_RANGE(chip_addx, 1)) {
2163                 *code = true;
2164                 return UC_OFF(chip_addx);
2165         } else if (X_RANGE_ALL(chip_addx, 1)) {
2166                 return X_OFF(chip_addx);
2167         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2168                 *yram = true;
2169                 return Y_OFF(chip_addx);
2170         }
2171
2172         return INVALID_CHIP_ADDRESS;
2173 }
2174
2175 /*
2176  * Check if the DSP DMA is active
2177  */
2178 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2179 {
2180         unsigned int dma_chnlstart_reg;
2181
2182         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2183
2184         return ((dma_chnlstart_reg & (1 <<
2185                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2186 }
2187
2188 static int dsp_dma_setup_common(struct hda_codec *codec,
2189                                 unsigned int chip_addx,
2190                                 unsigned int dma_chan,
2191                                 unsigned int port_map_mask,
2192                                 bool ovly)
2193 {
2194         int status = 0;
2195         unsigned int chnl_prop;
2196         unsigned int dsp_addx;
2197         unsigned int active;
2198         bool code, yram;
2199
2200         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2201
2202         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2203                 codec_dbg(codec, "dma chan num invalid\n");
2204                 return -EINVAL;
2205         }
2206
2207         if (dsp_is_dma_active(codec, dma_chan)) {
2208                 codec_dbg(codec, "dma already active\n");
2209                 return -EBUSY;
2210         }
2211
2212         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2213
2214         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2215                 codec_dbg(codec, "invalid chip addr\n");
2216                 return -ENXIO;
2217         }
2218
2219         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2220         active = 0;
2221
2222         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2223
2224         if (ovly) {
2225                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2226                                      &chnl_prop);
2227
2228                 if (status < 0) {
2229                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2230                         return status;
2231                 }
2232                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2233         }
2234
2235         if (!code)
2236                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2237         else
2238                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2239
2240         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2241
2242         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2243         if (status < 0) {
2244                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2245                 return status;
2246         }
2247         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2248
2249         if (ovly) {
2250                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2251                                      &active);
2252
2253                 if (status < 0) {
2254                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2255                         return status;
2256                 }
2257                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2258         }
2259
2260         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2261                 DSPDMAC_ACTIVE_AAR_MASK;
2262
2263         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2264         if (status < 0) {
2265                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2266                 return status;
2267         }
2268
2269         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2270
2271         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2272                               port_map_mask);
2273         if (status < 0) {
2274                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2275                 return status;
2276         }
2277         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2278
2279         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2280                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2281         if (status < 0) {
2282                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2283                 return status;
2284         }
2285         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2286
2287         codec_dbg(codec,
2288                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2289                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2290                    chip_addx, dsp_addx, dma_chan,
2291                    port_map_mask, chnl_prop, active);
2292
2293         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2294
2295         return 0;
2296 }
2297
2298 /*
2299  * Setup the DSP DMA per-transfer-specific registers
2300  */
2301 static int dsp_dma_setup(struct hda_codec *codec,
2302                         unsigned int chip_addx,
2303                         unsigned int count,
2304                         unsigned int dma_chan)
2305 {
2306         int status = 0;
2307         bool code, yram;
2308         unsigned int dsp_addx;
2309         unsigned int addr_field;
2310         unsigned int incr_field;
2311         unsigned int base_cnt;
2312         unsigned int cur_cnt;
2313         unsigned int dma_cfg = 0;
2314         unsigned int adr_ofs = 0;
2315         unsigned int xfr_cnt = 0;
2316         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2317                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2318
2319         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2320
2321         if (count > max_dma_count) {
2322                 codec_dbg(codec, "count too big\n");
2323                 return -EINVAL;
2324         }
2325
2326         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2327         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2328                 codec_dbg(codec, "invalid chip addr\n");
2329                 return -ENXIO;
2330         }
2331
2332         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2333
2334         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2335         incr_field   = 0;
2336
2337         if (!code) {
2338                 addr_field <<= 1;
2339                 if (yram)
2340                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2341
2342                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2343         }
2344
2345         dma_cfg = addr_field + incr_field;
2346         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2347                                 dma_cfg);
2348         if (status < 0) {
2349                 codec_dbg(codec, "write DMACFG Reg fail\n");
2350                 return status;
2351         }
2352         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2353
2354         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2355                                                         (code ? 0 : 1));
2356
2357         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2358                                 adr_ofs);
2359         if (status < 0) {
2360                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2361                 return status;
2362         }
2363         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2364
2365         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2366
2367         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2368
2369         xfr_cnt = base_cnt | cur_cnt;
2370
2371         status = chipio_write(codec,
2372                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2373         if (status < 0) {
2374                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2375                 return status;
2376         }
2377         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2378
2379         codec_dbg(codec,
2380                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2381                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2382                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2383
2384         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2385
2386         return 0;
2387 }
2388
2389 /*
2390  * Start the DSP DMA
2391  */
2392 static int dsp_dma_start(struct hda_codec *codec,
2393                          unsigned int dma_chan, bool ovly)
2394 {
2395         unsigned int reg = 0;
2396         int status = 0;
2397
2398         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2399
2400         if (ovly) {
2401                 status = chipio_read(codec,
2402                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2403
2404                 if (status < 0) {
2405                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2406                         return status;
2407                 }
2408                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2409
2410                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2411                                 DSPDMAC_CHNLSTART_DIS_MASK);
2412         }
2413
2414         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2415                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2416         if (status < 0) {
2417                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2418                 return status;
2419         }
2420         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2421
2422         return status;
2423 }
2424
2425 /*
2426  * Stop the DSP DMA
2427  */
2428 static int dsp_dma_stop(struct hda_codec *codec,
2429                         unsigned int dma_chan, bool ovly)
2430 {
2431         unsigned int reg = 0;
2432         int status = 0;
2433
2434         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2435
2436         if (ovly) {
2437                 status = chipio_read(codec,
2438                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2439
2440                 if (status < 0) {
2441                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2442                         return status;
2443                 }
2444                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2445                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2446                                 DSPDMAC_CHNLSTART_DIS_MASK);
2447         }
2448
2449         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2450                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2451         if (status < 0) {
2452                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2453                 return status;
2454         }
2455         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2456
2457         return status;
2458 }
2459
2460 /**
2461  * Allocate router ports
2462  *
2463  * @codec: the HDA codec
2464  * @num_chans: number of channels in the stream
2465  * @ports_per_channel: number of ports per channel
2466  * @start_device: start device
2467  * @port_map: pointer to the port list to hold the allocated ports
2468  *
2469  * Returns zero or a negative error code.
2470  */
2471 static int dsp_allocate_router_ports(struct hda_codec *codec,
2472                                      unsigned int num_chans,
2473                                      unsigned int ports_per_channel,
2474                                      unsigned int start_device,
2475                                      unsigned int *port_map)
2476 {
2477         int status = 0;
2478         int res;
2479         u8 val;
2480
2481         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2482         if (status < 0)
2483                 return status;
2484
2485         val = start_device << 6;
2486         val |= (ports_per_channel - 1) << 4;
2487         val |= num_chans - 1;
2488
2489         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2490                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2491                             val);
2492
2493         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2494                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2495                             MEM_CONNID_DSP);
2496
2497         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2498         if (status < 0)
2499                 return status;
2500
2501         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2502                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2503
2504         *port_map = res;
2505
2506         return (res < 0) ? res : 0;
2507 }
2508
2509 /*
2510  * Free router ports
2511  */
2512 static int dsp_free_router_ports(struct hda_codec *codec)
2513 {
2514         int status = 0;
2515
2516         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2517         if (status < 0)
2518                 return status;
2519
2520         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2521                             VENDOR_CHIPIO_PORT_FREE_SET,
2522                             MEM_CONNID_DSP);
2523
2524         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2525
2526         return status;
2527 }
2528
2529 /*
2530  * Allocate DSP ports for the download stream
2531  */
2532 static int dsp_allocate_ports(struct hda_codec *codec,
2533                         unsigned int num_chans,
2534                         unsigned int rate_multi, unsigned int *port_map)
2535 {
2536         int status;
2537
2538         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2539
2540         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2541                 codec_dbg(codec, "bad rate multiple\n");
2542                 return -EINVAL;
2543         }
2544
2545         status = dsp_allocate_router_ports(codec, num_chans,
2546                                            rate_multi, 0, port_map);
2547
2548         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2549
2550         return status;
2551 }
2552
2553 static int dsp_allocate_ports_format(struct hda_codec *codec,
2554                         const unsigned short fmt,
2555                         unsigned int *port_map)
2556 {
2557         int status;
2558         unsigned int num_chans;
2559
2560         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2561         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2562         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2563
2564         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2565                 codec_dbg(codec, "bad rate multiple\n");
2566                 return -EINVAL;
2567         }
2568
2569         num_chans = get_hdafmt_chs(fmt) + 1;
2570
2571         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2572
2573         return status;
2574 }
2575
2576 /*
2577  * free DSP ports
2578  */
2579 static int dsp_free_ports(struct hda_codec *codec)
2580 {
2581         int status;
2582
2583         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2584
2585         status = dsp_free_router_ports(codec);
2586         if (status < 0) {
2587                 codec_dbg(codec, "free router ports fail\n");
2588                 return status;
2589         }
2590         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2591
2592         return status;
2593 }
2594
2595 /*
2596  *  HDA DMA engine stuffs for DSP code download
2597  */
2598 struct dma_engine {
2599         struct hda_codec *codec;
2600         unsigned short m_converter_format;
2601         struct snd_dma_buffer *dmab;
2602         unsigned int buf_size;
2603 };
2604
2605
2606 enum dma_state {
2607         DMA_STATE_STOP  = 0,
2608         DMA_STATE_RUN   = 1
2609 };
2610
2611 static int dma_convert_to_hda_format(struct hda_codec *codec,
2612                 unsigned int sample_rate,
2613                 unsigned short channels,
2614                 unsigned short *hda_format)
2615 {
2616         unsigned int format_val;
2617
2618         format_val = snd_hdac_calc_stream_format(sample_rate,
2619                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2620
2621         if (hda_format)
2622                 *hda_format = (unsigned short)format_val;
2623
2624         return 0;
2625 }
2626
2627 /*
2628  *  Reset DMA for DSP download
2629  */
2630 static int dma_reset(struct dma_engine *dma)
2631 {
2632         struct hda_codec *codec = dma->codec;
2633         struct ca0132_spec *spec = codec->spec;
2634         int status;
2635
2636         if (dma->dmab->area)
2637                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2638
2639         status = snd_hda_codec_load_dsp_prepare(codec,
2640                         dma->m_converter_format,
2641                         dma->buf_size,
2642                         dma->dmab);
2643         if (status < 0)
2644                 return status;
2645         spec->dsp_stream_id = status;
2646         return 0;
2647 }
2648
2649 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2650 {
2651         bool cmd;
2652
2653         switch (state) {
2654         case DMA_STATE_STOP:
2655                 cmd = false;
2656                 break;
2657         case DMA_STATE_RUN:
2658                 cmd = true;
2659                 break;
2660         default:
2661                 return 0;
2662         }
2663
2664         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2665         return 0;
2666 }
2667
2668 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2669 {
2670         return dma->dmab->bytes;
2671 }
2672
2673 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2674 {
2675         return dma->dmab->area;
2676 }
2677
2678 static int dma_xfer(struct dma_engine *dma,
2679                 const unsigned int *data,
2680                 unsigned int count)
2681 {
2682         memcpy(dma->dmab->area, data, count);
2683         return 0;
2684 }
2685
2686 static void dma_get_converter_format(
2687                 struct dma_engine *dma,
2688                 unsigned short *format)
2689 {
2690         if (format)
2691                 *format = dma->m_converter_format;
2692 }
2693
2694 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2695 {
2696         struct ca0132_spec *spec = dma->codec->spec;
2697
2698         return spec->dsp_stream_id;
2699 }
2700
2701 struct dsp_image_seg {
2702         u32 magic;
2703         u32 chip_addr;
2704         u32 count;
2705         u32 data[0];
2706 };
2707
2708 static const u32 g_magic_value = 0x4c46584d;
2709 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2710
2711 static bool is_valid(const struct dsp_image_seg *p)
2712 {
2713         return p->magic == g_magic_value;
2714 }
2715
2716 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2717 {
2718         return g_chip_addr_magic_value == p->chip_addr;
2719 }
2720
2721 static bool is_last(const struct dsp_image_seg *p)
2722 {
2723         return p->count == 0;
2724 }
2725
2726 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2727 {
2728         return struct_size(p, data, p->count);
2729 }
2730
2731 static const struct dsp_image_seg *get_next_seg_ptr(
2732                                 const struct dsp_image_seg *p)
2733 {
2734         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2735 }
2736
2737 /*
2738  * CA0132 chip DSP transfer stuffs.  For DSP download.
2739  */
2740 #define INVALID_DMA_CHANNEL (~0U)
2741
2742 /*
2743  * Program a list of address/data pairs via the ChipIO widget.
2744  * The segment data is in the format of successive pairs of words.
2745  * These are repeated as indicated by the segment's count field.
2746  */
2747 static int dspxfr_hci_write(struct hda_codec *codec,
2748                         const struct dsp_image_seg *fls)
2749 {
2750         int status;
2751         const u32 *data;
2752         unsigned int count;
2753
2754         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2755                 codec_dbg(codec, "hci_write invalid params\n");
2756                 return -EINVAL;
2757         }
2758
2759         count = fls->count;
2760         data = (u32 *)(fls->data);
2761         while (count >= 2) {
2762                 status = chipio_write(codec, data[0], data[1]);
2763                 if (status < 0) {
2764                         codec_dbg(codec, "hci_write chipio failed\n");
2765                         return status;
2766                 }
2767                 count -= 2;
2768                 data  += 2;
2769         }
2770         return 0;
2771 }
2772
2773 /**
2774  * Write a block of data into DSP code or data RAM using pre-allocated
2775  * DMA engine.
2776  *
2777  * @codec: the HDA codec
2778  * @fls: pointer to a fast load image
2779  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2780  *         no relocation
2781  * @dma_engine: pointer to DMA engine to be used for DSP download
2782  * @dma_chan: The number of DMA channels used for DSP download
2783  * @port_map_mask: port mapping
2784  * @ovly: TRUE if overlay format is required
2785  *
2786  * Returns zero or a negative error code.
2787  */
2788 static int dspxfr_one_seg(struct hda_codec *codec,
2789                         const struct dsp_image_seg *fls,
2790                         unsigned int reloc,
2791                         struct dma_engine *dma_engine,
2792                         unsigned int dma_chan,
2793                         unsigned int port_map_mask,
2794                         bool ovly)
2795 {
2796         int status = 0;
2797         bool comm_dma_setup_done = false;
2798         const unsigned int *data;
2799         unsigned int chip_addx;
2800         unsigned int words_to_write;
2801         unsigned int buffer_size_words;
2802         unsigned char *buffer_addx;
2803         unsigned short hda_format;
2804         unsigned int sample_rate_div;
2805         unsigned int sample_rate_mul;
2806         unsigned int num_chans;
2807         unsigned int hda_frame_size_words;
2808         unsigned int remainder_words;
2809         const u32 *data_remainder;
2810         u32 chip_addx_remainder;
2811         unsigned int run_size_words;
2812         const struct dsp_image_seg *hci_write = NULL;
2813         unsigned long timeout;
2814         bool dma_active;
2815
2816         if (fls == NULL)
2817                 return -EINVAL;
2818         if (is_hci_prog_list_seg(fls)) {
2819                 hci_write = fls;
2820                 fls = get_next_seg_ptr(fls);
2821         }
2822
2823         if (hci_write && (!fls || is_last(fls))) {
2824                 codec_dbg(codec, "hci_write\n");
2825                 return dspxfr_hci_write(codec, hci_write);
2826         }
2827
2828         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2829                 codec_dbg(codec, "Invalid Params\n");
2830                 return -EINVAL;
2831         }
2832
2833         data = fls->data;
2834         chip_addx = fls->chip_addr,
2835         words_to_write = fls->count;
2836
2837         if (!words_to_write)
2838                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2839         if (reloc)
2840                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2841
2842         if (!UC_RANGE(chip_addx, words_to_write) &&
2843             !X_RANGE_ALL(chip_addx, words_to_write) &&
2844             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2845                 codec_dbg(codec, "Invalid chip_addx Params\n");
2846                 return -EINVAL;
2847         }
2848
2849         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2850                                         sizeof(u32);
2851
2852         buffer_addx = dma_get_buffer_addr(dma_engine);
2853
2854         if (buffer_addx == NULL) {
2855                 codec_dbg(codec, "dma_engine buffer NULL\n");
2856                 return -EINVAL;
2857         }
2858
2859         dma_get_converter_format(dma_engine, &hda_format);
2860         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2861         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2862         num_chans = get_hdafmt_chs(hda_format) + 1;
2863
2864         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2865                         (num_chans * sample_rate_mul / sample_rate_div));
2866
2867         if (hda_frame_size_words == 0) {
2868                 codec_dbg(codec, "frmsz zero\n");
2869                 return -EINVAL;
2870         }
2871
2872         buffer_size_words = min(buffer_size_words,
2873                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2874                                 65536 : 32768));
2875         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2876         codec_dbg(codec,
2877                    "chpadr=0x%08x frmsz=%u nchan=%u "
2878                    "rate_mul=%u div=%u bufsz=%u\n",
2879                    chip_addx, hda_frame_size_words, num_chans,
2880                    sample_rate_mul, sample_rate_div, buffer_size_words);
2881
2882         if (buffer_size_words < hda_frame_size_words) {
2883                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2884                 return -EINVAL;
2885         }
2886
2887         remainder_words = words_to_write % hda_frame_size_words;
2888         data_remainder = data;
2889         chip_addx_remainder = chip_addx;
2890
2891         data += remainder_words;
2892         chip_addx += remainder_words*sizeof(u32);
2893         words_to_write -= remainder_words;
2894
2895         while (words_to_write != 0) {
2896                 run_size_words = min(buffer_size_words, words_to_write);
2897                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2898                             words_to_write, run_size_words, remainder_words);
2899                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2900                 if (!comm_dma_setup_done) {
2901                         status = dsp_dma_stop(codec, dma_chan, ovly);
2902                         if (status < 0)
2903                                 return status;
2904                         status = dsp_dma_setup_common(codec, chip_addx,
2905                                                 dma_chan, port_map_mask, ovly);
2906                         if (status < 0)
2907                                 return status;
2908                         comm_dma_setup_done = true;
2909                 }
2910
2911                 status = dsp_dma_setup(codec, chip_addx,
2912                                                 run_size_words, dma_chan);
2913                 if (status < 0)
2914                         return status;
2915                 status = dsp_dma_start(codec, dma_chan, ovly);
2916                 if (status < 0)
2917                         return status;
2918                 if (!dsp_is_dma_active(codec, dma_chan)) {
2919                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2920                         return -EIO;
2921                 }
2922                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2923                 if (status < 0)
2924                         return status;
2925                 if (remainder_words != 0) {
2926                         status = chipio_write_multiple(codec,
2927                                                 chip_addx_remainder,
2928                                                 data_remainder,
2929                                                 remainder_words);
2930                         if (status < 0)
2931                                 return status;
2932                         remainder_words = 0;
2933                 }
2934                 if (hci_write) {
2935                         status = dspxfr_hci_write(codec, hci_write);
2936                         if (status < 0)
2937                                 return status;
2938                         hci_write = NULL;
2939                 }
2940
2941                 timeout = jiffies + msecs_to_jiffies(2000);
2942                 do {
2943                         dma_active = dsp_is_dma_active(codec, dma_chan);
2944                         if (!dma_active)
2945                                 break;
2946                         msleep(20);
2947                 } while (time_before(jiffies, timeout));
2948                 if (dma_active)
2949                         break;
2950
2951                 codec_dbg(codec, "+++++ DMA complete\n");
2952                 dma_set_state(dma_engine, DMA_STATE_STOP);
2953                 status = dma_reset(dma_engine);
2954
2955                 if (status < 0)
2956                         return status;
2957
2958                 data += run_size_words;
2959                 chip_addx += run_size_words*sizeof(u32);
2960                 words_to_write -= run_size_words;
2961         }
2962
2963         if (remainder_words != 0) {
2964                 status = chipio_write_multiple(codec, chip_addx_remainder,
2965                                         data_remainder, remainder_words);
2966         }
2967
2968         return status;
2969 }
2970
2971 /**
2972  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2973  *
2974  * @codec: the HDA codec
2975  * @fls_data: pointer to a fast load image
2976  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2977  *         no relocation
2978  * @sample_rate: sampling rate of the stream used for DSP download
2979  * @channels: channels of the stream used for DSP download
2980  * @ovly: TRUE if overlay format is required
2981  *
2982  * Returns zero or a negative error code.
2983  */
2984 static int dspxfr_image(struct hda_codec *codec,
2985                         const struct dsp_image_seg *fls_data,
2986                         unsigned int reloc,
2987                         unsigned int sample_rate,
2988                         unsigned short channels,
2989                         bool ovly)
2990 {
2991         struct ca0132_spec *spec = codec->spec;
2992         int status;
2993         unsigned short hda_format = 0;
2994         unsigned int response;
2995         unsigned char stream_id = 0;
2996         struct dma_engine *dma_engine;
2997         unsigned int dma_chan;
2998         unsigned int port_map_mask;
2999
3000         if (fls_data == NULL)
3001                 return -EINVAL;
3002
3003         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3004         if (!dma_engine)
3005                 return -ENOMEM;
3006
3007         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3008         if (!dma_engine->dmab) {
3009                 kfree(dma_engine);
3010                 return -ENOMEM;
3011         }
3012
3013         dma_engine->codec = codec;
3014         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3015         dma_engine->m_converter_format = hda_format;
3016         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3017                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3018
3019         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3020
3021         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3022                                         hda_format, &response);
3023
3024         if (status < 0) {
3025                 codec_dbg(codec, "set converter format fail\n");
3026                 goto exit;
3027         }
3028
3029         status = snd_hda_codec_load_dsp_prepare(codec,
3030                                 dma_engine->m_converter_format,
3031                                 dma_engine->buf_size,
3032                                 dma_engine->dmab);
3033         if (status < 0)
3034                 goto exit;
3035         spec->dsp_stream_id = status;
3036
3037         if (ovly) {
3038                 status = dspio_alloc_dma_chan(codec, &dma_chan);
3039                 if (status < 0) {
3040                         codec_dbg(codec, "alloc dmachan fail\n");
3041                         dma_chan = INVALID_DMA_CHANNEL;
3042                         goto exit;
3043                 }
3044         }
3045
3046         port_map_mask = 0;
3047         status = dsp_allocate_ports_format(codec, hda_format,
3048                                         &port_map_mask);
3049         if (status < 0) {
3050                 codec_dbg(codec, "alloc ports fail\n");
3051                 goto exit;
3052         }
3053
3054         stream_id = dma_get_stream_id(dma_engine);
3055         status = codec_set_converter_stream_channel(codec,
3056                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
3057         if (status < 0) {
3058                 codec_dbg(codec, "set stream chan fail\n");
3059                 goto exit;
3060         }
3061
3062         while ((fls_data != NULL) && !is_last(fls_data)) {
3063                 if (!is_valid(fls_data)) {
3064                         codec_dbg(codec, "FLS check fail\n");
3065                         status = -EINVAL;
3066                         goto exit;
3067                 }
3068                 status = dspxfr_one_seg(codec, fls_data, reloc,
3069                                         dma_engine, dma_chan,
3070                                         port_map_mask, ovly);
3071                 if (status < 0)
3072                         break;
3073
3074                 if (is_hci_prog_list_seg(fls_data))
3075                         fls_data = get_next_seg_ptr(fls_data);
3076
3077                 if ((fls_data != NULL) && !is_last(fls_data))
3078                         fls_data = get_next_seg_ptr(fls_data);
3079         }
3080
3081         if (port_map_mask != 0)
3082                 status = dsp_free_ports(codec);
3083
3084         if (status < 0)
3085                 goto exit;
3086
3087         status = codec_set_converter_stream_channel(codec,
3088                                 WIDGET_CHIP_CTRL, 0, 0, &response);
3089
3090 exit:
3091         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3092                 dspio_free_dma_chan(codec, dma_chan);
3093
3094         if (dma_engine->dmab->area)
3095                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3096         kfree(dma_engine->dmab);
3097         kfree(dma_engine);
3098
3099         return status;
3100 }
3101
3102 /*
3103  * CA0132 DSP download stuffs.
3104  */
3105 static void dspload_post_setup(struct hda_codec *codec)
3106 {
3107         struct ca0132_spec *spec = codec->spec;
3108         codec_dbg(codec, "---- dspload_post_setup ------\n");
3109         if (!ca0132_use_alt_functions(spec)) {
3110                 /*set DSP speaker to 2.0 configuration*/
3111                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3112                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3113
3114                 /*update write pointer*/
3115                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3116         }
3117 }
3118
3119 /**
3120  * dspload_image - Download DSP from a DSP Image Fast Load structure.
3121  *
3122  * @codec: the HDA codec
3123  * @fls: pointer to a fast load image
3124  * @ovly: TRUE if overlay format is required
3125  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3126  *         no relocation
3127  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3128  * @router_chans: number of audio router channels to be allocated (0 means use
3129  *                internal defaults; max is 32)
3130  *
3131  * Download DSP from a DSP Image Fast Load structure. This structure is a
3132  * linear, non-constant sized element array of structures, each of which
3133  * contain the count of the data to be loaded, the data itself, and the
3134  * corresponding starting chip address of the starting data location.
3135  * Returns zero or a negative error code.
3136  */
3137 static int dspload_image(struct hda_codec *codec,
3138                         const struct dsp_image_seg *fls,
3139                         bool ovly,
3140                         unsigned int reloc,
3141                         bool autostart,
3142                         int router_chans)
3143 {
3144         int status = 0;
3145         unsigned int sample_rate;
3146         unsigned short channels;
3147
3148         codec_dbg(codec, "---- dspload_image begin ------\n");
3149         if (router_chans == 0) {
3150                 if (!ovly)
3151                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3152                 else
3153                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3154         }
3155
3156         sample_rate = 48000;
3157         channels = (unsigned short)router_chans;
3158
3159         while (channels > 16) {
3160                 sample_rate *= 2;
3161                 channels /= 2;
3162         }
3163
3164         do {
3165                 codec_dbg(codec, "Ready to program DMA\n");
3166                 if (!ovly)
3167                         status = dsp_reset(codec);
3168
3169                 if (status < 0)
3170                         break;
3171
3172                 codec_dbg(codec, "dsp_reset() complete\n");
3173                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3174                                       ovly);
3175
3176                 if (status < 0)
3177                         break;
3178
3179                 codec_dbg(codec, "dspxfr_image() complete\n");
3180                 if (autostart && !ovly) {
3181                         dspload_post_setup(codec);
3182                         status = dsp_set_run_state(codec);
3183                 }
3184
3185                 codec_dbg(codec, "LOAD FINISHED\n");
3186         } while (0);
3187
3188         return status;
3189 }
3190
3191 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3192 static bool dspload_is_loaded(struct hda_codec *codec)
3193 {
3194         unsigned int data = 0;
3195         int status = 0;
3196
3197         status = chipio_read(codec, 0x40004, &data);
3198         if ((status < 0) || (data != 1))
3199                 return false;
3200
3201         return true;
3202 }
3203 #else
3204 #define dspload_is_loaded(codec)        false
3205 #endif
3206
3207 static bool dspload_wait_loaded(struct hda_codec *codec)
3208 {
3209         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3210
3211         do {
3212                 if (dspload_is_loaded(codec)) {
3213                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3214                         return true;
3215                 }
3216                 msleep(20);
3217         } while (time_before(jiffies, timeout));
3218
3219         codec_err(codec, "ca0132 failed to download DSP\n");
3220         return false;
3221 }
3222
3223 /*
3224  * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3225  * based cards, and has a second mmio region, region2, that's used for special
3226  * commands.
3227  */
3228
3229 /*
3230  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3231  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3232  * The first eight bits are just the number of the pin. So far, I've only seen
3233  * this number go to 7.
3234  * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3235  * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3236  * then off to send that bit.
3237  */
3238 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3239                 bool enable)
3240 {
3241         struct ca0132_spec *spec = codec->spec;
3242         unsigned short gpio_data;
3243
3244         gpio_data = gpio_pin & 0xF;
3245         gpio_data |= ((enable << 8) & 0x100);
3246
3247         writew(gpio_data, spec->mem_base + 0x320);
3248 }
3249
3250 /*
3251  * Special pci region2 commands that are only used by the AE-5. They follow
3252  * a set format, and require reads at certain points to seemingly 'clear'
3253  * the response data. My first tests didn't do these reads, and would cause
3254  * the card to get locked up until the memory was read. These commands
3255  * seem to work with three distinct values that I've taken to calling group,
3256  * target-id, and value.
3257  */
3258 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3259                 unsigned int target, unsigned int value)
3260 {
3261         struct ca0132_spec *spec = codec->spec;
3262         unsigned int write_val;
3263
3264         writel(0x0000007e, spec->mem_base + 0x210);
3265         readl(spec->mem_base + 0x210);
3266         writel(0x0000005a, spec->mem_base + 0x210);
3267         readl(spec->mem_base + 0x210);
3268         readl(spec->mem_base + 0x210);
3269
3270         writel(0x00800005, spec->mem_base + 0x20c);
3271         writel(group, spec->mem_base + 0x804);
3272
3273         writel(0x00800005, spec->mem_base + 0x20c);
3274         write_val = (target & 0xff);
3275         write_val |= (value << 8);
3276
3277
3278         writel(write_val, spec->mem_base + 0x204);
3279         /*
3280          * Need delay here or else it goes too fast and works inconsistently.
3281          */
3282         msleep(20);
3283
3284         readl(spec->mem_base + 0x860);
3285         readl(spec->mem_base + 0x854);
3286         readl(spec->mem_base + 0x840);
3287
3288         writel(0x00800004, spec->mem_base + 0x20c);
3289         writel(0x00000000, spec->mem_base + 0x210);
3290         readl(spec->mem_base + 0x210);
3291         readl(spec->mem_base + 0x210);
3292 }
3293
3294 /*
3295  * This second type of command is used for setting the sound filter type.
3296  */
3297 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3298                 unsigned int group, unsigned int target, unsigned int value)
3299 {
3300         struct ca0132_spec *spec = codec->spec;
3301         unsigned int write_val;
3302
3303         writel(0x0000007e, spec->mem_base + 0x210);
3304         readl(spec->mem_base + 0x210);
3305         writel(0x0000005a, spec->mem_base + 0x210);
3306         readl(spec->mem_base + 0x210);
3307         readl(spec->mem_base + 0x210);
3308
3309         writel(0x00800003, spec->mem_base + 0x20c);
3310         writel(group, spec->mem_base + 0x804);
3311
3312         writel(0x00800005, spec->mem_base + 0x20c);
3313         write_val = (target & 0xff);
3314         write_val |= (value << 8);
3315
3316
3317         writel(write_val, spec->mem_base + 0x204);
3318         msleep(20);
3319         readl(spec->mem_base + 0x860);
3320         readl(spec->mem_base + 0x854);
3321         readl(spec->mem_base + 0x840);
3322
3323         writel(0x00800004, spec->mem_base + 0x20c);
3324         writel(0x00000000, spec->mem_base + 0x210);
3325         readl(spec->mem_base + 0x210);
3326         readl(spec->mem_base + 0x210);
3327 }
3328
3329 /*
3330  * Setup GPIO for the other variants of Core3D.
3331  */
3332
3333 /*
3334  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3335  * the card shows as having no GPIO pins.
3336  */
3337 static void ca0132_gpio_init(struct hda_codec *codec)
3338 {
3339         struct ca0132_spec *spec = codec->spec;
3340
3341         switch (ca0132_quirk(spec)) {
3342         case QUIRK_SBZ:
3343         case QUIRK_AE5:
3344                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3345                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3346                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3347                 break;
3348         case QUIRK_R3DI:
3349                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3350                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3351                 break;
3352         default:
3353                 break;
3354         }
3355
3356 }
3357
3358 /* Sets the GPIO for audio output. */
3359 static void ca0132_gpio_setup(struct hda_codec *codec)
3360 {
3361         struct ca0132_spec *spec = codec->spec;
3362
3363         switch (ca0132_quirk(spec)) {
3364         case QUIRK_SBZ:
3365                 snd_hda_codec_write(codec, 0x01, 0,
3366                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3367                 snd_hda_codec_write(codec, 0x01, 0,
3368                                 AC_VERB_SET_GPIO_MASK, 0x07);
3369                 snd_hda_codec_write(codec, 0x01, 0,
3370                                 AC_VERB_SET_GPIO_DATA, 0x04);
3371                 snd_hda_codec_write(codec, 0x01, 0,
3372                                 AC_VERB_SET_GPIO_DATA, 0x06);
3373                 break;
3374         case QUIRK_R3DI:
3375                 snd_hda_codec_write(codec, 0x01, 0,
3376                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3377                 snd_hda_codec_write(codec, 0x01, 0,
3378                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3379                 snd_hda_codec_write(codec, 0x01, 0,
3380                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3381                 break;
3382         default:
3383                 break;
3384         }
3385 }
3386
3387 /*
3388  * GPIO control functions for the Recon3D integrated.
3389  */
3390
3391 enum r3di_gpio_bit {
3392         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3393         R3DI_MIC_SELECT_BIT = 1,
3394         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3395         R3DI_OUT_SELECT_BIT = 2,
3396         /*
3397          * I dunno what this actually does, but it stays on until the dsp
3398          * is downloaded.
3399          */
3400         R3DI_GPIO_DSP_DOWNLOADING = 3,
3401         /*
3402          * Same as above, no clue what it does, but it comes on after the dsp
3403          * is downloaded.
3404          */
3405         R3DI_GPIO_DSP_DOWNLOADED = 4
3406 };
3407
3408 enum r3di_mic_select {
3409         /* Set GPIO bit 1 to 0 for rear mic */
3410         R3DI_REAR_MIC = 0,
3411         /* Set GPIO bit 1 to 1 for front microphone*/
3412         R3DI_FRONT_MIC = 1
3413 };
3414
3415 enum r3di_out_select {
3416         /* Set GPIO bit 2 to 0 for headphone */
3417         R3DI_HEADPHONE_OUT = 0,
3418         /* Set GPIO bit 2 to 1 for speaker */
3419         R3DI_LINE_OUT = 1
3420 };
3421 enum r3di_dsp_status {
3422         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3423         R3DI_DSP_DOWNLOADING = 0,
3424         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3425         R3DI_DSP_DOWNLOADED = 1
3426 };
3427
3428
3429 static void r3di_gpio_mic_set(struct hda_codec *codec,
3430                 enum r3di_mic_select cur_mic)
3431 {
3432         unsigned int cur_gpio;
3433
3434         /* Get the current GPIO Data setup */
3435         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3436
3437         switch (cur_mic) {
3438         case R3DI_REAR_MIC:
3439                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3440                 break;
3441         case R3DI_FRONT_MIC:
3442                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3443                 break;
3444         }
3445         snd_hda_codec_write(codec, codec->core.afg, 0,
3446                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3447 }
3448
3449 static void r3di_gpio_out_set(struct hda_codec *codec,
3450                 enum r3di_out_select cur_out)
3451 {
3452         unsigned int cur_gpio;
3453
3454         /* Get the current GPIO Data setup */
3455         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3456
3457         switch (cur_out) {
3458         case R3DI_HEADPHONE_OUT:
3459                 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3460                 break;
3461         case R3DI_LINE_OUT:
3462                 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3463                 break;
3464         }
3465         snd_hda_codec_write(codec, codec->core.afg, 0,
3466                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3467 }
3468
3469 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3470                 enum r3di_dsp_status dsp_status)
3471 {
3472         unsigned int cur_gpio;
3473
3474         /* Get the current GPIO Data setup */
3475         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3476
3477         switch (dsp_status) {
3478         case R3DI_DSP_DOWNLOADING:
3479                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3480                 snd_hda_codec_write(codec, codec->core.afg, 0,
3481                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3482                 break;
3483         case R3DI_DSP_DOWNLOADED:
3484                 /* Set DOWNLOADING bit to 0. */
3485                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3486
3487                 snd_hda_codec_write(codec, codec->core.afg, 0,
3488                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3489
3490                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3491                 break;
3492         }
3493
3494         snd_hda_codec_write(codec, codec->core.afg, 0,
3495                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3496 }
3497
3498 /*
3499  * PCM callbacks
3500  */
3501 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3502                         struct hda_codec *codec,
3503                         unsigned int stream_tag,
3504                         unsigned int format,
3505                         struct snd_pcm_substream *substream)
3506 {
3507         struct ca0132_spec *spec = codec->spec;
3508
3509         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3510
3511         return 0;
3512 }
3513
3514 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3515                         struct hda_codec *codec,
3516                         struct snd_pcm_substream *substream)
3517 {
3518         struct ca0132_spec *spec = codec->spec;
3519
3520         if (spec->dsp_state == DSP_DOWNLOADING)
3521                 return 0;
3522
3523         /*If Playback effects are on, allow stream some time to flush
3524          *effects tail*/
3525         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3526                 msleep(50);
3527
3528         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3529
3530         return 0;
3531 }
3532
3533 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3534                         struct hda_codec *codec,
3535                         struct snd_pcm_substream *substream)
3536 {
3537         struct ca0132_spec *spec = codec->spec;
3538         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3539         struct snd_pcm_runtime *runtime = substream->runtime;
3540
3541         if (spec->dsp_state != DSP_DOWNLOADED)
3542                 return 0;
3543
3544         /* Add latency if playback enhancement and either effect is enabled. */
3545         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3546                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3547                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3548                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3549         }
3550
3551         /* Applying Speaker EQ adds latency as well. */
3552         if (spec->cur_out_type == SPEAKER_OUT)
3553                 latency += DSP_SPEAKER_OUT_LATENCY;
3554
3555         return (latency * runtime->rate) / 1000;
3556 }
3557
3558 /*
3559  * Digital out
3560  */
3561 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3562                                         struct hda_codec *codec,
3563                                         struct snd_pcm_substream *substream)
3564 {
3565         struct ca0132_spec *spec = codec->spec;
3566         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3567 }
3568
3569 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3570                         struct hda_codec *codec,
3571                         unsigned int stream_tag,
3572                         unsigned int format,
3573                         struct snd_pcm_substream *substream)
3574 {
3575         struct ca0132_spec *spec = codec->spec;
3576         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3577                                              stream_tag, format, substream);
3578 }
3579
3580 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3581                         struct hda_codec *codec,
3582                         struct snd_pcm_substream *substream)
3583 {
3584         struct ca0132_spec *spec = codec->spec;
3585         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3586 }
3587
3588 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3589                                          struct hda_codec *codec,
3590                                          struct snd_pcm_substream *substream)
3591 {
3592         struct ca0132_spec *spec = codec->spec;
3593         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3594 }
3595
3596 /*
3597  * Analog capture
3598  */
3599 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3600                                         struct hda_codec *codec,
3601                                         unsigned int stream_tag,
3602                                         unsigned int format,
3603                                         struct snd_pcm_substream *substream)
3604 {
3605         snd_hda_codec_setup_stream(codec, hinfo->nid,
3606                                    stream_tag, 0, format);
3607
3608         return 0;
3609 }
3610
3611 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3612                         struct hda_codec *codec,
3613                         struct snd_pcm_substream *substream)
3614 {
3615         struct ca0132_spec *spec = codec->spec;
3616
3617         if (spec->dsp_state == DSP_DOWNLOADING)
3618                 return 0;
3619
3620         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3621         return 0;
3622 }
3623
3624 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3625                         struct hda_codec *codec,
3626                         struct snd_pcm_substream *substream)
3627 {
3628         struct ca0132_spec *spec = codec->spec;
3629         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3630         struct snd_pcm_runtime *runtime = substream->runtime;
3631
3632         if (spec->dsp_state != DSP_DOWNLOADED)
3633                 return 0;
3634
3635         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3636                 latency += DSP_CRYSTAL_VOICE_LATENCY;
3637
3638         return (latency * runtime->rate) / 1000;
3639 }
3640
3641 /*
3642  * Controls stuffs.
3643  */
3644
3645 /*
3646  * Mixer controls helpers.
3647  */
3648 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3649         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3650           .name = xname, \
3651           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3652           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3653                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3654                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3655           .info = ca0132_volume_info, \
3656           .get = ca0132_volume_get, \
3657           .put = ca0132_volume_put, \
3658           .tlv = { .c = ca0132_volume_tlv }, \
3659           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3660
3661 /*
3662  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3663  * volume put, which is used for setting the DSP volume. This was done because
3664  * the ca0132 functions were taking too much time and causing lag.
3665  */
3666 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3667         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3668           .name = xname, \
3669           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3670           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3671                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3672                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3673           .info = snd_hda_mixer_amp_volume_info, \
3674           .get = snd_hda_mixer_amp_volume_get, \
3675           .put = ca0132_alt_volume_put, \
3676           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3677           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3678
3679 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3680         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3681           .name = xname, \
3682           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3683           .info = snd_hda_mixer_amp_switch_info, \
3684           .get = ca0132_switch_get, \
3685           .put = ca0132_switch_put, \
3686           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3687
3688 /* stereo */
3689 #define CA0132_CODEC_VOL(xname, nid, dir) \
3690         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3691 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3692         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3693 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3694         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3695
3696 /* lookup tables */
3697 /*
3698  * Lookup table with decibel values for the DSP. When volume is changed in
3699  * Windows, the DSP is also sent the dB value in floating point. In Windows,
3700  * these values have decimal points, probably because the Windows driver
3701  * actually uses floating point. We can't here, so I made a lookup table of
3702  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3703  * DAC's, and 9 is the maximum.
3704  */
3705 static const unsigned int float_vol_db_lookup[] = {
3706 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3707 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3708 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3709 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3710 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3711 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3712 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3713 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3714 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3715 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3716 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3717 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3718 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3719 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3720 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3721 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3722 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3723 };
3724
3725 /*
3726  * This table counts from float 0 to 1 in increments of .01, which is
3727  * useful for a few different sliders.
3728  */
3729 static const unsigned int float_zero_to_one_lookup[] = {
3730 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3731 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3732 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3733 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3734 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3735 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3736 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3737 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3738 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3739 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3740 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3741 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3742 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3743 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3744 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3745 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3746 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3747 };
3748
3749 /*
3750  * This table counts from float 10 to 1000, which is the range of the x-bass
3751  * crossover slider in Windows.
3752  */
3753 static const unsigned int float_xbass_xover_lookup[] = {
3754 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3755 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3756 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3757 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3758 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3759 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3760 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3761 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3762 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3763 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3764 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3765 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3766 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3767 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3768 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3769 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3770 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3771 };
3772
3773 /* The following are for tuning of products */
3774 #ifdef ENABLE_TUNING_CONTROLS
3775
3776 static unsigned int voice_focus_vals_lookup[] = {
3777 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3778 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3779 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3780 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3781 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3782 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3783 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3784 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3785 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3786 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3787 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3788 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3789 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3790 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3791 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3792 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3793 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3794 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3795 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3796 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3797 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3798 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3799 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3800 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3801 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3802 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3803 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3804 };
3805
3806 static unsigned int mic_svm_vals_lookup[] = {
3807 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3808 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3809 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3810 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3811 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3812 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3813 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3814 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3815 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3816 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3817 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3818 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3819 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3820 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3821 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3822 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3823 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3824 };
3825
3826 static unsigned int equalizer_vals_lookup[] = {
3827 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3828 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3829 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3830 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3831 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3832 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3833 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3834 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3835 0x41C00000
3836 };
3837
3838 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3839                           unsigned int *lookup, int idx)
3840 {
3841         int i = 0;
3842
3843         for (i = 0; i < TUNING_CTLS_COUNT; i++)
3844                 if (nid == ca0132_tuning_ctls[i].nid)
3845                         goto found;
3846
3847         return -EINVAL;
3848 found:
3849         snd_hda_power_up(codec);
3850         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3851                         ca0132_tuning_ctls[i].req,
3852                         &(lookup[idx]), sizeof(unsigned int));
3853         snd_hda_power_down(codec);
3854
3855         return 1;
3856 }
3857
3858 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3859                           struct snd_ctl_elem_value *ucontrol)
3860 {
3861         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3862         struct ca0132_spec *spec = codec->spec;
3863         hda_nid_t nid = get_amp_nid(kcontrol);
3864         long *valp = ucontrol->value.integer.value;
3865         int idx = nid - TUNING_CTL_START_NID;
3866
3867         *valp = spec->cur_ctl_vals[idx];
3868         return 0;
3869 }
3870
3871 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3872                               struct snd_ctl_elem_info *uinfo)
3873 {
3874         int chs = get_amp_channels(kcontrol);
3875         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3876         uinfo->count = chs == 3 ? 2 : 1;
3877         uinfo->value.integer.min = 20;
3878         uinfo->value.integer.max = 180;
3879         uinfo->value.integer.step = 1;
3880
3881         return 0;
3882 }
3883
3884 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3885                                 struct snd_ctl_elem_value *ucontrol)
3886 {
3887         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3888         struct ca0132_spec *spec = codec->spec;
3889         hda_nid_t nid = get_amp_nid(kcontrol);
3890         long *valp = ucontrol->value.integer.value;
3891         int idx;
3892
3893         idx = nid - TUNING_CTL_START_NID;
3894         /* any change? */
3895         if (spec->cur_ctl_vals[idx] == *valp)
3896                 return 0;
3897
3898         spec->cur_ctl_vals[idx] = *valp;
3899
3900         idx = *valp - 20;
3901         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3902
3903         return 1;
3904 }
3905
3906 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3907                               struct snd_ctl_elem_info *uinfo)
3908 {
3909         int chs = get_amp_channels(kcontrol);
3910         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3911         uinfo->count = chs == 3 ? 2 : 1;
3912         uinfo->value.integer.min = 0;
3913         uinfo->value.integer.max = 100;
3914         uinfo->value.integer.step = 1;
3915
3916         return 0;
3917 }
3918
3919 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3920                                 struct snd_ctl_elem_value *ucontrol)
3921 {
3922         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3923         struct ca0132_spec *spec = codec->spec;
3924         hda_nid_t nid = get_amp_nid(kcontrol);
3925         long *valp = ucontrol->value.integer.value;
3926         int idx;
3927
3928         idx = nid - TUNING_CTL_START_NID;
3929         /* any change? */
3930         if (spec->cur_ctl_vals[idx] == *valp)
3931                 return 0;
3932
3933         spec->cur_ctl_vals[idx] = *valp;
3934
3935         idx = *valp;
3936         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3937
3938         return 0;
3939 }
3940
3941 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3942                               struct snd_ctl_elem_info *uinfo)
3943 {
3944         int chs = get_amp_channels(kcontrol);
3945         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3946         uinfo->count = chs == 3 ? 2 : 1;
3947         uinfo->value.integer.min = 0;
3948         uinfo->value.integer.max = 48;
3949         uinfo->value.integer.step = 1;
3950
3951         return 0;
3952 }
3953
3954 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3955                                 struct snd_ctl_elem_value *ucontrol)
3956 {
3957         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3958         struct ca0132_spec *spec = codec->spec;
3959         hda_nid_t nid = get_amp_nid(kcontrol);
3960         long *valp = ucontrol->value.integer.value;
3961         int idx;
3962
3963         idx = nid - TUNING_CTL_START_NID;
3964         /* any change? */
3965         if (spec->cur_ctl_vals[idx] == *valp)
3966                 return 0;
3967
3968         spec->cur_ctl_vals[idx] = *valp;
3969
3970         idx = *valp;
3971         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3972
3973         return 1;
3974 }
3975
3976 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3977 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3978
3979 static int add_tuning_control(struct hda_codec *codec,
3980                                 hda_nid_t pnid, hda_nid_t nid,
3981                                 const char *name, int dir)
3982 {
3983         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3984         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3985         struct snd_kcontrol_new knew =
3986                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3987
3988         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3989                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3990         knew.tlv.c = 0;
3991         knew.tlv.p = 0;
3992         switch (pnid) {
3993         case VOICE_FOCUS:
3994                 knew.info = voice_focus_ctl_info;
3995                 knew.get = tuning_ctl_get;
3996                 knew.put = voice_focus_ctl_put;
3997                 knew.tlv.p = voice_focus_db_scale;
3998                 break;
3999         case MIC_SVM:
4000                 knew.info = mic_svm_ctl_info;
4001                 knew.get = tuning_ctl_get;
4002                 knew.put = mic_svm_ctl_put;
4003                 break;
4004         case EQUALIZER:
4005                 knew.info = equalizer_ctl_info;
4006                 knew.get = tuning_ctl_get;
4007                 knew.put = equalizer_ctl_put;
4008                 knew.tlv.p = eq_db_scale;
4009                 break;
4010         default:
4011                 return 0;
4012         }
4013         knew.private_value =
4014                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4015         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4016         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4017 }
4018
4019 static int add_tuning_ctls(struct hda_codec *codec)
4020 {
4021         int i;
4022         int err;
4023
4024         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4025                 err = add_tuning_control(codec,
4026                                         ca0132_tuning_ctls[i].parent_nid,
4027                                         ca0132_tuning_ctls[i].nid,
4028                                         ca0132_tuning_ctls[i].name,
4029                                         ca0132_tuning_ctls[i].direct);
4030                 if (err < 0)
4031                         return err;
4032         }
4033
4034         return 0;
4035 }
4036
4037 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4038 {
4039         struct ca0132_spec *spec = codec->spec;
4040         int i;
4041
4042         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4043         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4044         /* SVM level defaults to 0.74. */
4045         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4046
4047         /* EQ defaults to 0dB. */
4048         for (i = 2; i < TUNING_CTLS_COUNT; i++)
4049                 spec->cur_ctl_vals[i] = 24;
4050 }
4051 #endif /*ENABLE_TUNING_CONTROLS*/
4052
4053 /*
4054  * Select the active output.
4055  * If autodetect is enabled, output will be selected based on jack detection.
4056  * If jack inserted, headphone will be selected, else built-in speakers
4057  * If autodetect is disabled, output will be selected based on selection.
4058  */
4059 static int ca0132_select_out(struct hda_codec *codec)
4060 {
4061         struct ca0132_spec *spec = codec->spec;
4062         unsigned int pin_ctl;
4063         int jack_present;
4064         int auto_jack;
4065         unsigned int tmp;
4066         int err;
4067
4068         codec_dbg(codec, "ca0132_select_out\n");
4069
4070         snd_hda_power_up_pm(codec);
4071
4072         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4073
4074         if (auto_jack)
4075                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4076         else
4077                 jack_present =
4078                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4079
4080         if (jack_present)
4081                 spec->cur_out_type = HEADPHONE_OUT;
4082         else
4083                 spec->cur_out_type = SPEAKER_OUT;
4084
4085         if (spec->cur_out_type == SPEAKER_OUT) {
4086                 codec_dbg(codec, "ca0132_select_out speaker\n");
4087                 /*speaker out config*/
4088                 tmp = FLOAT_ONE;
4089                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4090                 if (err < 0)
4091                         goto exit;
4092                 /*enable speaker EQ*/
4093                 tmp = FLOAT_ONE;
4094                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4095                 if (err < 0)
4096                         goto exit;
4097
4098                 /* Setup EAPD */
4099                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4100                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4101                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4102                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4103                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4104                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4105                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4106                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4107
4108                 /* disable headphone node */
4109                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4110                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4111                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4112                                     pin_ctl & ~PIN_HP);
4113                 /* enable speaker node */
4114                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4115                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4116                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4117                                     pin_ctl | PIN_OUT);
4118         } else {
4119                 codec_dbg(codec, "ca0132_select_out hp\n");
4120                 /*headphone out config*/
4121                 tmp = FLOAT_ZERO;
4122                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4123                 if (err < 0)
4124                         goto exit;
4125                 /*disable speaker EQ*/
4126                 tmp = FLOAT_ZERO;
4127                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4128                 if (err < 0)
4129                         goto exit;
4130
4131                 /* Setup EAPD */
4132                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4133                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4134                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4135                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4136                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4137                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4138                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4139                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4140
4141                 /* disable speaker*/
4142                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4143                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4144                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4145                                     pin_ctl & ~PIN_HP);
4146                 /* enable headphone*/
4147                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4148                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4149                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4150                                     pin_ctl | PIN_HP);
4151         }
4152
4153 exit:
4154         snd_hda_power_down_pm(codec);
4155
4156         return err < 0 ? err : 0;
4157 }
4158
4159 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4160 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4161 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4162
4163 static void ae5_mmio_select_out(struct hda_codec *codec)
4164 {
4165         struct ca0132_spec *spec = codec->spec;
4166         unsigned int i;
4167
4168         for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4169                 ca0113_mmio_command_set(codec,
4170                         ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4171                         ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4172                         ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4173 }
4174
4175 /*
4176  * These are the commands needed to setup output on each of the different card
4177  * types.
4178  */
4179 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4180 {
4181         struct ca0132_spec *spec = codec->spec;
4182         unsigned int tmp;
4183
4184         switch (spec->cur_out_type) {
4185         case SPEAKER_OUT:
4186                 switch (ca0132_quirk(spec)) {
4187                 case QUIRK_SBZ:
4188                         ca0113_mmio_gpio_set(codec, 7, false);
4189                         ca0113_mmio_gpio_set(codec, 4, true);
4190                         ca0113_mmio_gpio_set(codec, 1, true);
4191                         chipio_set_control_param(codec, 0x0d, 0x18);
4192                         break;
4193                 case QUIRK_ZXR:
4194                         ca0113_mmio_gpio_set(codec, 2, true);
4195                         ca0113_mmio_gpio_set(codec, 3, true);
4196                         ca0113_mmio_gpio_set(codec, 5, false);
4197                         zxr_headphone_gain_set(codec, 0);
4198                         chipio_set_control_param(codec, 0x0d, 0x24);
4199                         break;
4200                 case QUIRK_R3DI:
4201                         chipio_set_control_param(codec, 0x0d, 0x24);
4202                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4203                         break;
4204                 case QUIRK_R3D:
4205                         chipio_set_control_param(codec, 0x0d, 0x24);
4206                         ca0113_mmio_gpio_set(codec, 1, true);
4207                         break;
4208                 case QUIRK_AE5:
4209                         ae5_mmio_select_out(codec);
4210                         ae5_headphone_gain_set(codec, 2);
4211                         tmp = FLOAT_ZERO;
4212                         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4213                         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4214                         chipio_set_control_param(codec, 0x0d, 0xa4);
4215                         chipio_write(codec, 0x18b03c, 0x00000012);
4216                         break;
4217                 default:
4218                         break;
4219                 }
4220                 break;
4221         case HEADPHONE_OUT:
4222                 switch (ca0132_quirk(spec)) {
4223                 case QUIRK_SBZ:
4224                         ca0113_mmio_gpio_set(codec, 7, true);
4225                         ca0113_mmio_gpio_set(codec, 4, true);
4226                         ca0113_mmio_gpio_set(codec, 1, false);
4227                         chipio_set_control_param(codec, 0x0d, 0x12);
4228                         break;
4229                 case QUIRK_ZXR:
4230                         ca0113_mmio_gpio_set(codec, 2, false);
4231                         ca0113_mmio_gpio_set(codec, 3, false);
4232                         ca0113_mmio_gpio_set(codec, 5, true);
4233                         zxr_headphone_gain_set(codec, spec->zxr_gain_set);
4234                         chipio_set_control_param(codec, 0x0d, 0x21);
4235                         break;
4236                 case QUIRK_R3DI:
4237                         chipio_set_control_param(codec, 0x0d, 0x21);
4238                         r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4239                         break;
4240                 case QUIRK_R3D:
4241                         chipio_set_control_param(codec, 0x0d, 0x21);
4242                         ca0113_mmio_gpio_set(codec, 0x1, false);
4243                         break;
4244                 case QUIRK_AE5:
4245                         ae5_mmio_select_out(codec);
4246                         ae5_headphone_gain_set(codec,
4247                                         spec->ae5_headphone_gain_val);
4248                         tmp = FLOAT_ONE;
4249                         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4250                         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4251                         chipio_set_control_param(codec, 0x0d, 0xa1);
4252                         chipio_write(codec, 0x18b03c, 0x00000012);
4253                         break;
4254                 default:
4255                         break;
4256                 }
4257                 break;
4258         case SURROUND_OUT:
4259                 switch (ca0132_quirk(spec)) {
4260                 case QUIRK_SBZ:
4261                         ca0113_mmio_gpio_set(codec, 7, false);
4262                         ca0113_mmio_gpio_set(codec, 4, true);
4263                         ca0113_mmio_gpio_set(codec, 1, true);
4264                         chipio_set_control_param(codec, 0x0d, 0x18);
4265                         break;
4266                 case QUIRK_ZXR:
4267                         ca0113_mmio_gpio_set(codec, 2, true);
4268                         ca0113_mmio_gpio_set(codec, 3, true);
4269                         ca0113_mmio_gpio_set(codec, 5, false);
4270                         zxr_headphone_gain_set(codec, 0);
4271                         chipio_set_control_param(codec, 0x0d, 0x24);
4272                         break;
4273                 case QUIRK_R3DI:
4274                         chipio_set_control_param(codec, 0x0d, 0x24);
4275                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4276                         break;
4277                 case QUIRK_R3D:
4278                         ca0113_mmio_gpio_set(codec, 1, true);
4279                         chipio_set_control_param(codec, 0x0d, 0x24);
4280                         break;
4281                 case QUIRK_AE5:
4282                         ae5_mmio_select_out(codec);
4283                         ae5_headphone_gain_set(codec, 2);
4284                         tmp = FLOAT_ZERO;
4285                         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4286                         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4287                         chipio_set_control_param(codec, 0x0d, 0xa4);
4288                         chipio_write(codec, 0x18b03c, 0x00000012);
4289                         break;
4290                 default:
4291                         break;
4292                 }
4293                 break;
4294         }
4295 }
4296
4297 /*
4298  * This function behaves similarly to the ca0132_select_out funciton above,
4299  * except with a few differences. It adds the ability to select the current
4300  * output with an enumerated control "output source" if the auto detect
4301  * mute switch is set to off. If the auto detect mute switch is enabled, it
4302  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4303  * It also adds the ability to auto-detect the front headphone port. The only
4304  * way to select surround is to disable auto detect, and set Surround with the
4305  * enumerated control.
4306  */
4307 static int ca0132_alt_select_out(struct hda_codec *codec)
4308 {
4309         struct ca0132_spec *spec = codec->spec;
4310         unsigned int pin_ctl;
4311         int jack_present;
4312         int auto_jack;
4313         unsigned int i;
4314         unsigned int tmp;
4315         int err;
4316         /* Default Headphone is rear headphone */
4317         hda_nid_t headphone_nid = spec->out_pins[1];
4318
4319         codec_dbg(codec, "%s\n", __func__);
4320
4321         snd_hda_power_up_pm(codec);
4322
4323         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4324
4325         /*
4326          * If headphone rear or front is plugged in, set to headphone.
4327          * If neither is plugged in, set to rear line out. Only if
4328          * hp/speaker auto detect is enabled.
4329          */
4330         if (auto_jack) {
4331                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4332                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4333
4334                 if (jack_present)
4335                         spec->cur_out_type = HEADPHONE_OUT;
4336                 else
4337                         spec->cur_out_type = SPEAKER_OUT;
4338         } else
4339                 spec->cur_out_type = spec->out_enum_val;
4340
4341         /* Begin DSP output switch */
4342         tmp = FLOAT_ONE;
4343         err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4344         if (err < 0)
4345                 goto exit;
4346
4347         ca0132_alt_select_out_quirk_handler(codec);
4348
4349         switch (spec->cur_out_type) {
4350         case SPEAKER_OUT:
4351                 codec_dbg(codec, "%s speaker\n", __func__);
4352
4353                 /* disable headphone node */
4354                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4355                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4356                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4357                                     pin_ctl & ~PIN_HP);
4358                 /* enable line-out node */
4359                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4360                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4361                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4362                                     pin_ctl | PIN_OUT);
4363                 /* Enable EAPD */
4364                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4365                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4366
4367                 /* If PlayEnhancement is enabled, set different source */
4368                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4369                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4370                 else
4371                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4372                 break;
4373         case HEADPHONE_OUT:
4374                 codec_dbg(codec, "%s hp\n", __func__);
4375
4376                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4377                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4378
4379                 /* disable speaker*/
4380                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4381                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4382                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4383                                 pin_ctl & ~PIN_HP);
4384
4385                 /* enable headphone, either front or rear */
4386
4387                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4388                         headphone_nid = spec->out_pins[2];
4389                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4390                         headphone_nid = spec->out_pins[1];
4391
4392                 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4393                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4394                 snd_hda_set_pin_ctl(codec, headphone_nid,
4395                                     pin_ctl | PIN_HP);
4396
4397                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4398                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4399                 else
4400                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4401                 break;
4402         case SURROUND_OUT:
4403                 codec_dbg(codec, "%s surround\n", __func__);
4404
4405                 /* enable line out node */
4406                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4407                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4408                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4409                                                 pin_ctl | PIN_OUT);
4410                 /* Disable headphone out */
4411                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4412                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4413                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4414                                     pin_ctl & ~PIN_HP);
4415                 /* Enable EAPD on line out */
4416                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4417                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4418                 /* enable center/lfe out node */
4419                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4420                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4421                 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4422                                     pin_ctl | PIN_OUT);
4423                 /* Now set rear surround node as out. */
4424                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4425                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4426                 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4427                                     pin_ctl | PIN_OUT);
4428
4429                 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4430                 break;
4431         }
4432         /*
4433          * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4434          * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4435          * enabled, we need to make sure X_BASS is off, otherwise everything
4436          * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4437          * effect should sort this out.
4438          */
4439         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4440                 ca0132_effects_set(codec, X_BASS,
4441                         spec->effects_switch[X_BASS - EFFECT_START_NID]);
4442
4443         /* run through the output dsp commands for the selected output. */
4444         for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4445                 err = dspio_set_uint_param(codec,
4446                 alt_out_presets[spec->cur_out_type].mids[i],
4447                 alt_out_presets[spec->cur_out_type].reqs[i],
4448                 alt_out_presets[spec->cur_out_type].vals[i]);
4449
4450                 if (err < 0)
4451                         goto exit;
4452         }
4453
4454 exit:
4455         snd_hda_power_down_pm(codec);
4456
4457         return err < 0 ? err : 0;
4458 }
4459
4460 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4461 {
4462         struct ca0132_spec *spec = container_of(
4463                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4464         struct hda_jack_tbl *jack;
4465
4466         if (ca0132_use_alt_functions(spec))
4467                 ca0132_alt_select_out(spec->codec);
4468         else
4469                 ca0132_select_out(spec->codec);
4470
4471         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4472         if (jack) {
4473                 jack->block_report = 0;
4474                 snd_hda_jack_report_sync(spec->codec);
4475         }
4476 }
4477
4478 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4479 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4480 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4481 static int stop_mic1(struct hda_codec *codec);
4482 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4483 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4484
4485 /*
4486  * Select the active VIP source
4487  */
4488 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4489 {
4490         struct ca0132_spec *spec = codec->spec;
4491         unsigned int tmp;
4492
4493         if (spec->dsp_state != DSP_DOWNLOADED)
4494                 return 0;
4495
4496         /* if CrystalVoice if off, vipsource should be 0 */
4497         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4498             (val == 0)) {
4499                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4500                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4501                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4502                 if (spec->cur_mic_type == DIGITAL_MIC)
4503                         tmp = FLOAT_TWO;
4504                 else
4505                         tmp = FLOAT_ONE;
4506                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4507                 tmp = FLOAT_ZERO;
4508                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4509         } else {
4510                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4511                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4512                 if (spec->cur_mic_type == DIGITAL_MIC)
4513                         tmp = FLOAT_TWO;
4514                 else
4515                         tmp = FLOAT_ONE;
4516                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4517                 tmp = FLOAT_ONE;
4518                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4519                 msleep(20);
4520                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4521         }
4522
4523         return 1;
4524 }
4525
4526 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4527 {
4528         struct ca0132_spec *spec = codec->spec;
4529         unsigned int tmp;
4530
4531         if (spec->dsp_state != DSP_DOWNLOADED)
4532                 return 0;
4533
4534         codec_dbg(codec, "%s\n", __func__);
4535
4536         chipio_set_stream_control(codec, 0x03, 0);
4537         chipio_set_stream_control(codec, 0x04, 0);
4538
4539         /* if CrystalVoice is off, vipsource should be 0 */
4540         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4541             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4542                 codec_dbg(codec, "%s: off.", __func__);
4543                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4544
4545                 tmp = FLOAT_ZERO;
4546                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4547
4548                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4549                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4550                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4551                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4552
4553
4554                 if (spec->in_enum_val == REAR_LINE_IN)
4555                         tmp = FLOAT_ZERO;
4556                 else {
4557                         if (ca0132_quirk(spec) == QUIRK_SBZ)
4558                                 tmp = FLOAT_THREE;
4559                         else
4560                                 tmp = FLOAT_ONE;
4561                 }
4562
4563                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4564
4565         } else {
4566                 codec_dbg(codec, "%s: on.", __func__);
4567                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4568                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4569                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4570                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4571
4572                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4573                         tmp = FLOAT_TWO;
4574                 else
4575                         tmp = FLOAT_ONE;
4576                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4577
4578                 tmp = FLOAT_ONE;
4579                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4580
4581                 msleep(20);
4582                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4583         }
4584
4585         chipio_set_stream_control(codec, 0x03, 1);
4586         chipio_set_stream_control(codec, 0x04, 1);
4587
4588         return 1;
4589 }
4590
4591 /*
4592  * Select the active microphone.
4593  * If autodetect is enabled, mic will be selected based on jack detection.
4594  * If jack inserted, ext.mic will be selected, else built-in mic
4595  * If autodetect is disabled, mic will be selected based on selection.
4596  */
4597 static int ca0132_select_mic(struct hda_codec *codec)
4598 {
4599         struct ca0132_spec *spec = codec->spec;
4600         int jack_present;
4601         int auto_jack;
4602
4603         codec_dbg(codec, "ca0132_select_mic\n");
4604
4605         snd_hda_power_up_pm(codec);
4606
4607         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4608
4609         if (auto_jack)
4610                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4611         else
4612                 jack_present =
4613                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4614
4615         if (jack_present)
4616                 spec->cur_mic_type = LINE_MIC_IN;
4617         else
4618                 spec->cur_mic_type = DIGITAL_MIC;
4619
4620         if (spec->cur_mic_type == DIGITAL_MIC) {
4621                 /* enable digital Mic */
4622                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4623                 ca0132_set_dmic(codec, 1);
4624                 ca0132_mic_boost_set(codec, 0);
4625                 /* set voice focus */
4626                 ca0132_effects_set(codec, VOICE_FOCUS,
4627                                    spec->effects_switch
4628                                    [VOICE_FOCUS - EFFECT_START_NID]);
4629         } else {
4630                 /* disable digital Mic */
4631                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4632                 ca0132_set_dmic(codec, 0);
4633                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4634                 /* disable voice focus */
4635                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4636         }
4637
4638         snd_hda_power_down_pm(codec);
4639
4640         return 0;
4641 }
4642
4643 /*
4644  * Select the active input.
4645  * Mic detection isn't used, because it's kind of pointless on the SBZ.
4646  * The front mic has no jack-detection, so the only way to switch to it
4647  * is to do it manually in alsamixer.
4648  */
4649 static int ca0132_alt_select_in(struct hda_codec *codec)
4650 {
4651         struct ca0132_spec *spec = codec->spec;
4652         unsigned int tmp;
4653
4654         codec_dbg(codec, "%s\n", __func__);
4655
4656         snd_hda_power_up_pm(codec);
4657
4658         chipio_set_stream_control(codec, 0x03, 0);
4659         chipio_set_stream_control(codec, 0x04, 0);
4660
4661         spec->cur_mic_type = spec->in_enum_val;
4662
4663         switch (spec->cur_mic_type) {
4664         case REAR_MIC:
4665                 switch (ca0132_quirk(spec)) {
4666                 case QUIRK_SBZ:
4667                 case QUIRK_R3D:
4668                         ca0113_mmio_gpio_set(codec, 0, false);
4669                         tmp = FLOAT_THREE;
4670                         break;
4671                 case QUIRK_ZXR:
4672                         tmp = FLOAT_THREE;
4673                         break;
4674                 case QUIRK_R3DI:
4675                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4676                         tmp = FLOAT_ONE;
4677                         break;
4678                 case QUIRK_AE5:
4679                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4680                         tmp = FLOAT_THREE;
4681                         break;
4682                 case QUIRK_AE7:
4683                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4684                         tmp = FLOAT_THREE;
4685                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
4686                                         SR_96_000);
4687                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
4688                                         SR_96_000);
4689                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
4690                         break;
4691                 default:
4692                         tmp = FLOAT_ONE;
4693                         break;
4694                 }
4695
4696                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4697                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4698                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4699                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4700
4701                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4702
4703                 chipio_set_stream_control(codec, 0x03, 1);
4704                 chipio_set_stream_control(codec, 0x04, 1);
4705                 switch (ca0132_quirk(spec)) {
4706                 case QUIRK_SBZ:
4707                         chipio_write(codec, 0x18B098, 0x0000000C);
4708                         chipio_write(codec, 0x18B09C, 0x0000000C);
4709                         break;
4710                 case QUIRK_ZXR:
4711                         chipio_write(codec, 0x18B098, 0x0000000C);
4712                         chipio_write(codec, 0x18B09C, 0x000000CC);
4713                         break;
4714                 case QUIRK_AE5:
4715                         chipio_write(codec, 0x18B098, 0x0000000C);
4716                         chipio_write(codec, 0x18B09C, 0x0000004C);
4717                         break;
4718                 default:
4719                         break;
4720                 }
4721                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4722                 break;
4723         case REAR_LINE_IN:
4724                 ca0132_mic_boost_set(codec, 0);
4725                 switch (ca0132_quirk(spec)) {
4726                 case QUIRK_SBZ:
4727                 case QUIRK_R3D:
4728                         ca0113_mmio_gpio_set(codec, 0, false);
4729                         break;
4730                 case QUIRK_R3DI:
4731                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4732                         break;
4733                 case QUIRK_AE5:
4734                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4735                         break;
4736                 case QUIRK_AE7:
4737                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
4738                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
4739                                         SR_96_000);
4740                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
4741                                         SR_96_000);
4742                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
4743                         break;
4744                 default:
4745                         break;
4746                 }
4747
4748                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4749                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4750                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4751                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4752
4753                 if (ca0132_quirk(spec) == QUIRK_AE7)
4754                         tmp = FLOAT_THREE;
4755                 else
4756                         tmp = FLOAT_ZERO;
4757                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4758
4759                 switch (ca0132_quirk(spec)) {
4760                 case QUIRK_SBZ:
4761                 case QUIRK_AE5:
4762                         chipio_write(codec, 0x18B098, 0x00000000);
4763                         chipio_write(codec, 0x18B09C, 0x00000000);
4764                         break;
4765                 default:
4766                         break;
4767                 }
4768                 chipio_set_stream_control(codec, 0x03, 1);
4769                 chipio_set_stream_control(codec, 0x04, 1);
4770                 break;
4771         case FRONT_MIC:
4772                 switch (ca0132_quirk(spec)) {
4773                 case QUIRK_SBZ:
4774                 case QUIRK_R3D:
4775                         ca0113_mmio_gpio_set(codec, 0, true);
4776                         ca0113_mmio_gpio_set(codec, 5, false);
4777                         tmp = FLOAT_THREE;
4778                         break;
4779                 case QUIRK_R3DI:
4780                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4781                         tmp = FLOAT_ONE;
4782                         break;
4783                 case QUIRK_AE5:
4784                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
4785                         tmp = FLOAT_THREE;
4786                         break;
4787                 default:
4788                         tmp = FLOAT_ONE;
4789                         break;
4790                 }
4791
4792                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4793                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4794                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4795                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4796
4797                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4798
4799                 chipio_set_stream_control(codec, 0x03, 1);
4800                 chipio_set_stream_control(codec, 0x04, 1);
4801
4802                 switch (ca0132_quirk(spec)) {
4803                 case QUIRK_SBZ:
4804                         chipio_write(codec, 0x18B098, 0x0000000C);
4805                         chipio_write(codec, 0x18B09C, 0x000000CC);
4806                         break;
4807                 case QUIRK_AE5:
4808                         chipio_write(codec, 0x18B098, 0x0000000C);
4809                         chipio_write(codec, 0x18B09C, 0x0000004C);
4810                         break;
4811                 default:
4812                         break;
4813                 }
4814                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4815                 break;
4816         }
4817         ca0132_cvoice_switch_set(codec);
4818
4819         snd_hda_power_down_pm(codec);
4820         return 0;
4821 }
4822
4823 /*
4824  * Check if VNODE settings take effect immediately.
4825  */
4826 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4827                                      hda_nid_t vnid,
4828                                      hda_nid_t *shared_nid)
4829 {
4830         struct ca0132_spec *spec = codec->spec;
4831         hda_nid_t nid;
4832
4833         switch (vnid) {
4834         case VNID_SPK:
4835                 nid = spec->shared_out_nid;
4836                 break;
4837         case VNID_MIC:
4838                 nid = spec->shared_mic_nid;
4839                 break;
4840         default:
4841                 return false;
4842         }
4843
4844         if (shared_nid)
4845                 *shared_nid = nid;
4846
4847         return true;
4848 }
4849
4850 /*
4851 * The following functions are control change helpers.
4852 * They return 0 if no changed.  Return 1 if changed.
4853 */
4854 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4855 {
4856         struct ca0132_spec *spec = codec->spec;
4857         unsigned int tmp;
4858
4859         /* based on CrystalVoice state to enable VoiceFX. */
4860         if (enable) {
4861                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4862                         FLOAT_ONE : FLOAT_ZERO;
4863         } else {
4864                 tmp = FLOAT_ZERO;
4865         }
4866
4867         dspio_set_uint_param(codec, ca0132_voicefx.mid,
4868                              ca0132_voicefx.reqs[0], tmp);
4869
4870         return 1;
4871 }
4872
4873 /*
4874  * Set the effects parameters
4875  */
4876 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4877 {
4878         struct ca0132_spec *spec = codec->spec;
4879         unsigned int on, tmp;
4880         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4881         int err = 0;
4882         int idx = nid - EFFECT_START_NID;
4883
4884         if ((idx < 0) || (idx >= num_fx))
4885                 return 0; /* no changed */
4886
4887         /* for out effect, qualify with PE */
4888         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4889                 /* if PE if off, turn off out effects. */
4890                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4891                         val = 0;
4892                 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4893                         val = 0;
4894         }
4895
4896         /* for in effect, qualify with CrystalVoice */
4897         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4898                 /* if CrystalVoice if off, turn off in effects. */
4899                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4900                         val = 0;
4901
4902                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4903                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4904                         val = 0;
4905
4906                 /* If Voice Focus on SBZ, set to two channel. */
4907                 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
4908                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4909                         if (spec->effects_switch[CRYSTAL_VOICE -
4910                                                  EFFECT_START_NID]) {
4911
4912                                 if (spec->effects_switch[VOICE_FOCUS -
4913                                                          EFFECT_START_NID]) {
4914                                         tmp = FLOAT_TWO;
4915                                         val = 1;
4916                                 } else
4917                                         tmp = FLOAT_ONE;
4918
4919                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4920                         }
4921                 }
4922                 /*
4923                  * For SBZ noise reduction, there's an extra command
4924                  * to module ID 0x47. No clue why.
4925                  */
4926                 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
4927                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4928                         if (spec->effects_switch[CRYSTAL_VOICE -
4929                                                  EFFECT_START_NID]) {
4930                                 if (spec->effects_switch[NOISE_REDUCTION -
4931                                                          EFFECT_START_NID])
4932                                         tmp = FLOAT_ONE;
4933                                 else
4934                                         tmp = FLOAT_ZERO;
4935                         } else
4936                                 tmp = FLOAT_ZERO;
4937
4938                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4939                 }
4940
4941                 /* If rear line in disable effects. */
4942                 if (ca0132_use_alt_functions(spec) &&
4943                                 spec->in_enum_val == REAR_LINE_IN)
4944                         val = 0;
4945         }
4946
4947         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4948                     nid, val);
4949
4950         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4951         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4952                                    ca0132_effects[idx].reqs[0], on);
4953
4954         if (err < 0)
4955                 return 0; /* no changed */
4956
4957         return 1;
4958 }
4959
4960 /*
4961  * Turn on/off Playback Enhancements
4962  */
4963 static int ca0132_pe_switch_set(struct hda_codec *codec)
4964 {
4965         struct ca0132_spec *spec = codec->spec;
4966         hda_nid_t nid;
4967         int i, ret = 0;
4968
4969         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4970                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4971
4972         if (ca0132_use_alt_functions(spec))
4973                 ca0132_alt_select_out(codec);
4974
4975         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4976         nid = OUT_EFFECT_START_NID;
4977         /* PE affects all out effects */
4978         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4979                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4980
4981         return ret;
4982 }
4983
4984 /* Check if Mic1 is streaming, if so, stop streaming */
4985 static int stop_mic1(struct hda_codec *codec)
4986 {
4987         struct ca0132_spec *spec = codec->spec;
4988         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4989                                                  AC_VERB_GET_CONV, 0);
4990         if (oldval != 0)
4991                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4992                                     AC_VERB_SET_CHANNEL_STREAMID,
4993                                     0);
4994         return oldval;
4995 }
4996
4997 /* Resume Mic1 streaming if it was stopped. */
4998 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4999 {
5000         struct ca0132_spec *spec = codec->spec;
5001         /* Restore the previous stream and channel */
5002         if (oldval != 0)
5003                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5004                                     AC_VERB_SET_CHANNEL_STREAMID,
5005                                     oldval);
5006 }
5007
5008 /*
5009  * Turn on/off CrystalVoice
5010  */
5011 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5012 {
5013         struct ca0132_spec *spec = codec->spec;
5014         hda_nid_t nid;
5015         int i, ret = 0;
5016         unsigned int oldval;
5017
5018         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5019                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5020
5021         i = IN_EFFECT_START_NID - EFFECT_START_NID;
5022         nid = IN_EFFECT_START_NID;
5023         /* CrystalVoice affects all in effects */
5024         for (; nid < IN_EFFECT_END_NID; nid++, i++)
5025                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5026
5027         /* including VoiceFX */
5028         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5029
5030         /* set correct vipsource */
5031         oldval = stop_mic1(codec);
5032         if (ca0132_use_alt_functions(spec))
5033                 ret |= ca0132_alt_set_vipsource(codec, 1);
5034         else
5035                 ret |= ca0132_set_vipsource(codec, 1);
5036         resume_mic1(codec, oldval);
5037         return ret;
5038 }
5039
5040 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5041 {
5042         struct ca0132_spec *spec = codec->spec;
5043         int ret = 0;
5044
5045         if (val) /* on */
5046                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5047                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5048         else /* off */
5049                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5050                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5051
5052         return ret;
5053 }
5054
5055 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5056 {
5057         struct ca0132_spec *spec = codec->spec;
5058         int ret = 0;
5059
5060         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5061                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5062         return ret;
5063 }
5064
5065 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5066 {
5067         unsigned int i;
5068
5069         for (i = 0; i < 4; i++)
5070                 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5071                                 ae5_headphone_gain_presets[val].vals[i]);
5072         return 0;
5073 }
5074
5075 /*
5076  * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5077  * amplifier to handle a 600 ohm load.
5078  */
5079 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5080 {
5081         ca0113_mmio_gpio_set(codec, 1, val);
5082
5083         return 0;
5084 }
5085
5086 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5087                                 struct snd_ctl_elem_value *ucontrol)
5088 {
5089         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5090         hda_nid_t nid = get_amp_nid(kcontrol);
5091         hda_nid_t shared_nid = 0;
5092         bool effective;
5093         int ret = 0;
5094         struct ca0132_spec *spec = codec->spec;
5095         int auto_jack;
5096
5097         if (nid == VNID_HP_SEL) {
5098                 auto_jack =
5099                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5100                 if (!auto_jack) {
5101                         if (ca0132_use_alt_functions(spec))
5102                                 ca0132_alt_select_out(codec);
5103                         else
5104                                 ca0132_select_out(codec);
5105                 }
5106                 return 1;
5107         }
5108
5109         if (nid == VNID_AMIC1_SEL) {
5110                 auto_jack =
5111                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5112                 if (!auto_jack)
5113                         ca0132_select_mic(codec);
5114                 return 1;
5115         }
5116
5117         if (nid == VNID_HP_ASEL) {
5118                 if (ca0132_use_alt_functions(spec))
5119                         ca0132_alt_select_out(codec);
5120                 else
5121                         ca0132_select_out(codec);
5122                 return 1;
5123         }
5124
5125         if (nid == VNID_AMIC1_ASEL) {
5126                 ca0132_select_mic(codec);
5127                 return 1;
5128         }
5129
5130         /* if effective conditions, then update hw immediately. */
5131         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5132         if (effective) {
5133                 int dir = get_amp_direction(kcontrol);
5134                 int ch = get_amp_channels(kcontrol);
5135                 unsigned long pval;
5136
5137                 mutex_lock(&codec->control_mutex);
5138                 pval = kcontrol->private_value;
5139                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5140                                                                 0, dir);
5141                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5142                 kcontrol->private_value = pval;
5143                 mutex_unlock(&codec->control_mutex);
5144         }
5145
5146         return ret;
5147 }
5148 /* End of control change helpers. */
5149 /*
5150  * Below I've added controls to mess with the effect levels, I've only enabled
5151  * them on the Sound Blaster Z, but they would probably also work on the
5152  * Chromebook. I figured they were probably tuned specifically for it, and left
5153  * out for a reason.
5154  */
5155
5156 /* Sets DSP effect level from the sliders above the controls */
5157 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5158                           const unsigned int *lookup, int idx)
5159 {
5160         int i = 0;
5161         unsigned int y;
5162         /*
5163          * For X_BASS, req 2 is actually crossover freq instead of
5164          * effect level
5165          */
5166         if (nid == X_BASS)
5167                 y = 2;
5168         else
5169                 y = 1;
5170
5171         snd_hda_power_up(codec);
5172         if (nid == XBASS_XOVER) {
5173                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5174                         if (ca0132_effects[i].nid == X_BASS)
5175                                 break;
5176
5177                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5178                                 ca0132_effects[i].reqs[1],
5179                                 &(lookup[idx - 1]), sizeof(unsigned int));
5180         } else {
5181                 /* Find the actual effect structure */
5182                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5183                         if (nid == ca0132_effects[i].nid)
5184                                 break;
5185
5186                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5187                                 ca0132_effects[i].reqs[y],
5188                                 &(lookup[idx]), sizeof(unsigned int));
5189         }
5190
5191         snd_hda_power_down(codec);
5192
5193         return 0;
5194 }
5195
5196 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5197                           struct snd_ctl_elem_value *ucontrol)
5198 {
5199         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5200         struct ca0132_spec *spec = codec->spec;
5201         long *valp = ucontrol->value.integer.value;
5202
5203         *valp = spec->xbass_xover_freq;
5204         return 0;
5205 }
5206
5207 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5208                           struct snd_ctl_elem_value *ucontrol)
5209 {
5210         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5211         struct ca0132_spec *spec = codec->spec;
5212         hda_nid_t nid = get_amp_nid(kcontrol);
5213         long *valp = ucontrol->value.integer.value;
5214         int idx = nid - OUT_EFFECT_START_NID;
5215
5216         *valp = spec->fx_ctl_val[idx];
5217         return 0;
5218 }
5219
5220 /*
5221  * The X-bass crossover starts at 10hz, so the min is 1. The
5222  * frequency is set in multiples of 10.
5223  */
5224 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5225                 struct snd_ctl_elem_info *uinfo)
5226 {
5227         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5228         uinfo->count = 1;
5229         uinfo->value.integer.min = 1;
5230         uinfo->value.integer.max = 100;
5231         uinfo->value.integer.step = 1;
5232
5233         return 0;
5234 }
5235
5236 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5237                 struct snd_ctl_elem_info *uinfo)
5238 {
5239         int chs = get_amp_channels(kcontrol);
5240
5241         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5242         uinfo->count = chs == 3 ? 2 : 1;
5243         uinfo->value.integer.min = 0;
5244         uinfo->value.integer.max = 100;
5245         uinfo->value.integer.step = 1;
5246
5247         return 0;
5248 }
5249
5250 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5251                                 struct snd_ctl_elem_value *ucontrol)
5252 {
5253         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5254         struct ca0132_spec *spec = codec->spec;
5255         hda_nid_t nid = get_amp_nid(kcontrol);
5256         long *valp = ucontrol->value.integer.value;
5257         int idx;
5258
5259         /* any change? */
5260         if (spec->xbass_xover_freq == *valp)
5261                 return 0;
5262
5263         spec->xbass_xover_freq = *valp;
5264
5265         idx = *valp;
5266         ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5267
5268         return 0;
5269 }
5270
5271 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5272                                 struct snd_ctl_elem_value *ucontrol)
5273 {
5274         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5275         struct ca0132_spec *spec = codec->spec;
5276         hda_nid_t nid = get_amp_nid(kcontrol);
5277         long *valp = ucontrol->value.integer.value;
5278         int idx;
5279
5280         idx = nid - EFFECT_START_NID;
5281         /* any change? */
5282         if (spec->fx_ctl_val[idx] == *valp)
5283                 return 0;
5284
5285         spec->fx_ctl_val[idx] = *valp;
5286
5287         idx = *valp;
5288         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5289
5290         return 0;
5291 }
5292
5293
5294 /*
5295  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5296  * only has off or full 30 dB, and didn't like making a volume slider that has
5297  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5298  */
5299 #define MIC_BOOST_NUM_OF_STEPS 4
5300 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5301
5302 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5303                                  struct snd_ctl_elem_info *uinfo)
5304 {
5305         char *sfx = "dB";
5306         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5307
5308         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5309         uinfo->count = 1;
5310         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5311         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5312                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5313         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5314         strcpy(uinfo->value.enumerated.name, namestr);
5315         return 0;
5316 }
5317
5318 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5319                                 struct snd_ctl_elem_value *ucontrol)
5320 {
5321         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5322         struct ca0132_spec *spec = codec->spec;
5323
5324         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5325         return 0;
5326 }
5327
5328 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5329                                 struct snd_ctl_elem_value *ucontrol)
5330 {
5331         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5332         struct ca0132_spec *spec = codec->spec;
5333         int sel = ucontrol->value.enumerated.item[0];
5334         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5335
5336         if (sel >= items)
5337                 return 0;
5338
5339         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5340                     sel);
5341
5342         spec->mic_boost_enum_val = sel;
5343
5344         if (spec->in_enum_val != REAR_LINE_IN)
5345                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5346
5347         return 1;
5348 }
5349
5350 /*
5351  * Sound BlasterX AE-5 Headphone Gain Controls.
5352  */
5353 #define AE5_HEADPHONE_GAIN_MAX 3
5354 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5355                                  struct snd_ctl_elem_info *uinfo)
5356 {
5357         char *sfx = " Ohms)";
5358         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5359
5360         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5361         uinfo->count = 1;
5362         uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5363         if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5364                 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5365         sprintf(namestr, "%s %s",
5366                 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5367                 sfx);
5368         strcpy(uinfo->value.enumerated.name, namestr);
5369         return 0;
5370 }
5371
5372 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5373                                 struct snd_ctl_elem_value *ucontrol)
5374 {
5375         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5376         struct ca0132_spec *spec = codec->spec;
5377
5378         ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5379         return 0;
5380 }
5381
5382 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5383                                 struct snd_ctl_elem_value *ucontrol)
5384 {
5385         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5386         struct ca0132_spec *spec = codec->spec;
5387         int sel = ucontrol->value.enumerated.item[0];
5388         unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5389
5390         if (sel >= items)
5391                 return 0;
5392
5393         codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5394                     sel);
5395
5396         spec->ae5_headphone_gain_val = sel;
5397
5398         if (spec->out_enum_val == HEADPHONE_OUT)
5399                 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5400
5401         return 1;
5402 }
5403
5404 /*
5405  * Sound BlasterX AE-5 sound filter enumerated control.
5406  */
5407 #define AE5_SOUND_FILTER_MAX 3
5408
5409 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5410                                  struct snd_ctl_elem_info *uinfo)
5411 {
5412         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5413
5414         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5415         uinfo->count = 1;
5416         uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5417         if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5418                 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5419         sprintf(namestr, "%s",
5420                         ae5_filter_presets[uinfo->value.enumerated.item].name);
5421         strcpy(uinfo->value.enumerated.name, namestr);
5422         return 0;
5423 }
5424
5425 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5426                                 struct snd_ctl_elem_value *ucontrol)
5427 {
5428         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5429         struct ca0132_spec *spec = codec->spec;
5430
5431         ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5432         return 0;
5433 }
5434
5435 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5436                                 struct snd_ctl_elem_value *ucontrol)
5437 {
5438         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5439         struct ca0132_spec *spec = codec->spec;
5440         int sel = ucontrol->value.enumerated.item[0];
5441         unsigned int items = AE5_SOUND_FILTER_MAX;
5442
5443         if (sel >= items)
5444                 return 0;
5445
5446         codec_dbg(codec, "ae5_sound_filter: %s\n",
5447                         ae5_filter_presets[sel].name);
5448
5449         spec->ae5_filter_val = sel;
5450
5451         ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5452                         ae5_filter_presets[sel].val);
5453
5454         return 1;
5455 }
5456
5457 /*
5458  * Input Select Control for alternative ca0132 codecs. This exists because
5459  * front microphone has no auto-detect, and we need a way to set the rear
5460  * as line-in
5461  */
5462 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5463                                  struct snd_ctl_elem_info *uinfo)
5464 {
5465         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5466         uinfo->count = 1;
5467         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5468         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5469                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5470         strcpy(uinfo->value.enumerated.name,
5471                         in_src_str[uinfo->value.enumerated.item]);
5472         return 0;
5473 }
5474
5475 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5476                                 struct snd_ctl_elem_value *ucontrol)
5477 {
5478         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5479         struct ca0132_spec *spec = codec->spec;
5480
5481         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5482         return 0;
5483 }
5484
5485 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5486                                 struct snd_ctl_elem_value *ucontrol)
5487 {
5488         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5489         struct ca0132_spec *spec = codec->spec;
5490         int sel = ucontrol->value.enumerated.item[0];
5491         unsigned int items = IN_SRC_NUM_OF_INPUTS;
5492
5493         if (sel >= items)
5494                 return 0;
5495
5496         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5497                     sel, in_src_str[sel]);
5498
5499         spec->in_enum_val = sel;
5500
5501         ca0132_alt_select_in(codec);
5502
5503         return 1;
5504 }
5505
5506 /* Sound Blaster Z Output Select Control */
5507 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5508                                  struct snd_ctl_elem_info *uinfo)
5509 {
5510         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5511         uinfo->count = 1;
5512         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5513         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5514                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5515         strcpy(uinfo->value.enumerated.name,
5516                         alt_out_presets[uinfo->value.enumerated.item].name);
5517         return 0;
5518 }
5519
5520 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5521                                 struct snd_ctl_elem_value *ucontrol)
5522 {
5523         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5524         struct ca0132_spec *spec = codec->spec;
5525
5526         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5527         return 0;
5528 }
5529
5530 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5531                                 struct snd_ctl_elem_value *ucontrol)
5532 {
5533         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5534         struct ca0132_spec *spec = codec->spec;
5535         int sel = ucontrol->value.enumerated.item[0];
5536         unsigned int items = NUM_OF_OUTPUTS;
5537         unsigned int auto_jack;
5538
5539         if (sel >= items)
5540                 return 0;
5541
5542         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5543                     sel, alt_out_presets[sel].name);
5544
5545         spec->out_enum_val = sel;
5546
5547         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5548
5549         if (!auto_jack)
5550                 ca0132_alt_select_out(codec);
5551
5552         return 1;
5553 }
5554
5555 /*
5556  * Smart Volume output setting control. Three different settings, Normal,
5557  * which takes the value from the smart volume slider. The two others, loud
5558  * and night, disregard the slider value and have uneditable values.
5559  */
5560 #define NUM_OF_SVM_SETTINGS 3
5561 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5562
5563 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5564                                  struct snd_ctl_elem_info *uinfo)
5565 {
5566         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5567         uinfo->count = 1;
5568         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5569         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5570                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5571         strcpy(uinfo->value.enumerated.name,
5572                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
5573         return 0;
5574 }
5575
5576 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5577                                 struct snd_ctl_elem_value *ucontrol)
5578 {
5579         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5580         struct ca0132_spec *spec = codec->spec;
5581
5582         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5583         return 0;
5584 }
5585
5586 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5587                                 struct snd_ctl_elem_value *ucontrol)
5588 {
5589         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5590         struct ca0132_spec *spec = codec->spec;
5591         int sel = ucontrol->value.enumerated.item[0];
5592         unsigned int items = NUM_OF_SVM_SETTINGS;
5593         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5594         unsigned int tmp;
5595
5596         if (sel >= items)
5597                 return 0;
5598
5599         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5600                     sel, out_svm_set_enum_str[sel]);
5601
5602         spec->smart_volume_setting = sel;
5603
5604         switch (sel) {
5605         case 0:
5606                 tmp = FLOAT_ZERO;
5607                 break;
5608         case 1:
5609                 tmp = FLOAT_ONE;
5610                 break;
5611         case 2:
5612                 tmp = FLOAT_TWO;
5613                 break;
5614         default:
5615                 tmp = FLOAT_ZERO;
5616                 break;
5617         }
5618         /* Req 2 is the Smart Volume Setting req. */
5619         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5620                         ca0132_effects[idx].reqs[2], tmp);
5621         return 1;
5622 }
5623
5624 /* Sound Blaster Z EQ preset controls */
5625 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5626                                  struct snd_ctl_elem_info *uinfo)
5627 {
5628         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5629
5630         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5631         uinfo->count = 1;
5632         uinfo->value.enumerated.items = items;
5633         if (uinfo->value.enumerated.item >= items)
5634                 uinfo->value.enumerated.item = items - 1;
5635         strcpy(uinfo->value.enumerated.name,
5636                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5637         return 0;
5638 }
5639
5640 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5641                                 struct snd_ctl_elem_value *ucontrol)
5642 {
5643         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5644         struct ca0132_spec *spec = codec->spec;
5645
5646         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5647         return 0;
5648 }
5649
5650 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5651                                 struct snd_ctl_elem_value *ucontrol)
5652 {
5653         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5654         struct ca0132_spec *spec = codec->spec;
5655         int i, err = 0;
5656         int sel = ucontrol->value.enumerated.item[0];
5657         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5658
5659         if (sel >= items)
5660                 return 0;
5661
5662         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5663                         ca0132_alt_eq_presets[sel].name);
5664         /*
5665          * Idx 0 is default.
5666          * Default needs to qualify with CrystalVoice state.
5667          */
5668         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5669                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5670                                 ca0132_alt_eq_enum.reqs[i],
5671                                 ca0132_alt_eq_presets[sel].vals[i]);
5672                 if (err < 0)
5673                         break;
5674         }
5675
5676         if (err >= 0)
5677                 spec->eq_preset_val = sel;
5678
5679         return 1;
5680 }
5681
5682 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5683                                  struct snd_ctl_elem_info *uinfo)
5684 {
5685         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5686
5687         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5688         uinfo->count = 1;
5689         uinfo->value.enumerated.items = items;
5690         if (uinfo->value.enumerated.item >= items)
5691                 uinfo->value.enumerated.item = items - 1;
5692         strcpy(uinfo->value.enumerated.name,
5693                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5694         return 0;
5695 }
5696
5697 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5698                                 struct snd_ctl_elem_value *ucontrol)
5699 {
5700         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5701         struct ca0132_spec *spec = codec->spec;
5702
5703         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5704         return 0;
5705 }
5706
5707 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5708                                 struct snd_ctl_elem_value *ucontrol)
5709 {
5710         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5711         struct ca0132_spec *spec = codec->spec;
5712         int i, err = 0;
5713         int sel = ucontrol->value.enumerated.item[0];
5714
5715         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5716                 return 0;
5717
5718         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5719                     sel, ca0132_voicefx_presets[sel].name);
5720
5721         /*
5722          * Idx 0 is default.
5723          * Default needs to qualify with CrystalVoice state.
5724          */
5725         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5726                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5727                                 ca0132_voicefx.reqs[i],
5728                                 ca0132_voicefx_presets[sel].vals[i]);
5729                 if (err < 0)
5730                         break;
5731         }
5732
5733         if (err >= 0) {
5734                 spec->voicefx_val = sel;
5735                 /* enable voice fx */
5736                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5737         }
5738
5739         return 1;
5740 }
5741
5742 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5743                                 struct snd_ctl_elem_value *ucontrol)
5744 {
5745         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5746         struct ca0132_spec *spec = codec->spec;
5747         hda_nid_t nid = get_amp_nid(kcontrol);
5748         int ch = get_amp_channels(kcontrol);
5749         long *valp = ucontrol->value.integer.value;
5750
5751         /* vnode */
5752         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5753                 if (ch & 1) {
5754                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5755                         valp++;
5756                 }
5757                 if (ch & 2) {
5758                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5759                         valp++;
5760                 }
5761                 return 0;
5762         }
5763
5764         /* effects, include PE and CrystalVoice */
5765         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5766                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5767                 return 0;
5768         }
5769
5770         /* mic boost */
5771         if (nid == spec->input_pins[0]) {
5772                 *valp = spec->cur_mic_boost;
5773                 return 0;
5774         }
5775
5776         if (nid == ZXR_HEADPHONE_GAIN) {
5777                 *valp = spec->zxr_gain_set;
5778                 return 0;
5779         }
5780
5781         return 0;
5782 }
5783
5784 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5785                              struct snd_ctl_elem_value *ucontrol)
5786 {
5787         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5788         struct ca0132_spec *spec = codec->spec;
5789         hda_nid_t nid = get_amp_nid(kcontrol);
5790         int ch = get_amp_channels(kcontrol);
5791         long *valp = ucontrol->value.integer.value;
5792         int changed = 1;
5793
5794         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5795                     nid, *valp);
5796
5797         snd_hda_power_up(codec);
5798         /* vnode */
5799         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5800                 if (ch & 1) {
5801                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5802                         valp++;
5803                 }
5804                 if (ch & 2) {
5805                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5806                         valp++;
5807                 }
5808                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5809                 goto exit;
5810         }
5811
5812         /* PE */
5813         if (nid == PLAY_ENHANCEMENT) {
5814                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5815                 changed = ca0132_pe_switch_set(codec);
5816                 goto exit;
5817         }
5818
5819         /* CrystalVoice */
5820         if (nid == CRYSTAL_VOICE) {
5821                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5822                 changed = ca0132_cvoice_switch_set(codec);
5823                 goto exit;
5824         }
5825
5826         /* out and in effects */
5827         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5828             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5829                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5830                 changed = ca0132_effects_set(codec, nid, *valp);
5831                 goto exit;
5832         }
5833
5834         /* mic boost */
5835         if (nid == spec->input_pins[0]) {
5836                 spec->cur_mic_boost = *valp;
5837                 if (ca0132_use_alt_functions(spec)) {
5838                         if (spec->in_enum_val != REAR_LINE_IN)
5839                                 changed = ca0132_mic_boost_set(codec, *valp);
5840                 } else {
5841                         /* Mic boost does not apply to Digital Mic */
5842                         if (spec->cur_mic_type != DIGITAL_MIC)
5843                                 changed = ca0132_mic_boost_set(codec, *valp);
5844                 }
5845
5846                 goto exit;
5847         }
5848
5849         if (nid == ZXR_HEADPHONE_GAIN) {
5850                 spec->zxr_gain_set = *valp;
5851                 if (spec->cur_out_type == HEADPHONE_OUT)
5852                         changed = zxr_headphone_gain_set(codec, *valp);
5853                 else
5854                         changed = 0;
5855
5856                 goto exit;
5857         }
5858
5859 exit:
5860         snd_hda_power_down(codec);
5861         return changed;
5862 }
5863
5864 /*
5865  * Volume related
5866  */
5867 /*
5868  * Sets the internal DSP decibel level to match the DAC for output, and the
5869  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5870  * all alternative codecs set DSP playback volume.
5871  */
5872 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5873 {
5874         struct ca0132_spec *spec = codec->spec;
5875         unsigned int dsp_dir;
5876         unsigned int lookup_val;
5877
5878         if (nid == VNID_SPK)
5879                 dsp_dir = DSP_VOL_OUT;
5880         else
5881                 dsp_dir = DSP_VOL_IN;
5882
5883         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5884
5885         dspio_set_uint_param(codec,
5886                 ca0132_alt_vol_ctls[dsp_dir].mid,
5887                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5888                 float_vol_db_lookup[lookup_val]);
5889
5890         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5891
5892         dspio_set_uint_param(codec,
5893                 ca0132_alt_vol_ctls[dsp_dir].mid,
5894                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5895                 float_vol_db_lookup[lookup_val]);
5896
5897         dspio_set_uint_param(codec,
5898                 ca0132_alt_vol_ctls[dsp_dir].mid,
5899                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5900 }
5901
5902 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5903                               struct snd_ctl_elem_info *uinfo)
5904 {
5905         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5906         struct ca0132_spec *spec = codec->spec;
5907         hda_nid_t nid = get_amp_nid(kcontrol);
5908         int ch = get_amp_channels(kcontrol);
5909         int dir = get_amp_direction(kcontrol);
5910         unsigned long pval;
5911         int err;
5912
5913         switch (nid) {
5914         case VNID_SPK:
5915                 /* follow shared_out info */
5916                 nid = spec->shared_out_nid;
5917                 mutex_lock(&codec->control_mutex);
5918                 pval = kcontrol->private_value;
5919                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5920                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5921                 kcontrol->private_value = pval;
5922                 mutex_unlock(&codec->control_mutex);
5923                 break;
5924         case VNID_MIC:
5925                 /* follow shared_mic info */
5926                 nid = spec->shared_mic_nid;
5927                 mutex_lock(&codec->control_mutex);
5928                 pval = kcontrol->private_value;
5929                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5930                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5931                 kcontrol->private_value = pval;
5932                 mutex_unlock(&codec->control_mutex);
5933                 break;
5934         default:
5935                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5936         }
5937         return err;
5938 }
5939
5940 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5941                                 struct snd_ctl_elem_value *ucontrol)
5942 {
5943         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5944         struct ca0132_spec *spec = codec->spec;
5945         hda_nid_t nid = get_amp_nid(kcontrol);
5946         int ch = get_amp_channels(kcontrol);
5947         long *valp = ucontrol->value.integer.value;
5948
5949         /* store the left and right volume */
5950         if (ch & 1) {
5951                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5952                 valp++;
5953         }
5954         if (ch & 2) {
5955                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5956                 valp++;
5957         }
5958         return 0;
5959 }
5960
5961 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5962                                 struct snd_ctl_elem_value *ucontrol)
5963 {
5964         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5965         struct ca0132_spec *spec = codec->spec;
5966         hda_nid_t nid = get_amp_nid(kcontrol);
5967         int ch = get_amp_channels(kcontrol);
5968         long *valp = ucontrol->value.integer.value;
5969         hda_nid_t shared_nid = 0;
5970         bool effective;
5971         int changed = 1;
5972
5973         /* store the left and right volume */
5974         if (ch & 1) {
5975                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5976                 valp++;
5977         }
5978         if (ch & 2) {
5979                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5980                 valp++;
5981         }
5982
5983         /* if effective conditions, then update hw immediately. */
5984         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5985         if (effective) {
5986                 int dir = get_amp_direction(kcontrol);
5987                 unsigned long pval;
5988
5989                 snd_hda_power_up(codec);
5990                 mutex_lock(&codec->control_mutex);
5991                 pval = kcontrol->private_value;
5992                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5993                                                                 0, dir);
5994                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5995                 kcontrol->private_value = pval;
5996                 mutex_unlock(&codec->control_mutex);
5997                 snd_hda_power_down(codec);
5998         }
5999
6000         return changed;
6001 }
6002
6003 /*
6004  * This function is the same as the one above, because using an if statement
6005  * inside of the above volume control for the DSP volume would cause too much
6006  * lag. This is a lot more smooth.
6007  */
6008 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6009                                 struct snd_ctl_elem_value *ucontrol)
6010 {
6011         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6012         struct ca0132_spec *spec = codec->spec;
6013         hda_nid_t nid = get_amp_nid(kcontrol);
6014         int ch = get_amp_channels(kcontrol);
6015         long *valp = ucontrol->value.integer.value;
6016         hda_nid_t vnid = 0;
6017         int changed;
6018
6019         switch (nid) {
6020         case 0x02:
6021                 vnid = VNID_SPK;
6022                 break;
6023         case 0x07:
6024                 vnid = VNID_MIC;
6025                 break;
6026         }
6027
6028         /* store the left and right volume */
6029         if (ch & 1) {
6030                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6031                 valp++;
6032         }
6033         if (ch & 2) {
6034                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6035                 valp++;
6036         }
6037
6038         snd_hda_power_up(codec);
6039         ca0132_alt_dsp_volume_put(codec, vnid);
6040         mutex_lock(&codec->control_mutex);
6041         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6042         mutex_unlock(&codec->control_mutex);
6043         snd_hda_power_down(codec);
6044
6045         return changed;
6046 }
6047
6048 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6049                              unsigned int size, unsigned int __user *tlv)
6050 {
6051         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6052         struct ca0132_spec *spec = codec->spec;
6053         hda_nid_t nid = get_amp_nid(kcontrol);
6054         int ch = get_amp_channels(kcontrol);
6055         int dir = get_amp_direction(kcontrol);
6056         unsigned long pval;
6057         int err;
6058
6059         switch (nid) {
6060         case VNID_SPK:
6061                 /* follow shared_out tlv */
6062                 nid = spec->shared_out_nid;
6063                 mutex_lock(&codec->control_mutex);
6064                 pval = kcontrol->private_value;
6065                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6066                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6067                 kcontrol->private_value = pval;
6068                 mutex_unlock(&codec->control_mutex);
6069                 break;
6070         case VNID_MIC:
6071                 /* follow shared_mic tlv */
6072                 nid = spec->shared_mic_nid;
6073                 mutex_lock(&codec->control_mutex);
6074                 pval = kcontrol->private_value;
6075                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6076                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6077                 kcontrol->private_value = pval;
6078                 mutex_unlock(&codec->control_mutex);
6079                 break;
6080         default:
6081                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6082         }
6083         return err;
6084 }
6085
6086 /* Add volume slider control for effect level */
6087 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6088                                         const char *pfx, int dir)
6089 {
6090         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6091         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6092         struct snd_kcontrol_new knew =
6093                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6094
6095         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6096
6097         knew.tlv.c = NULL;
6098
6099         switch (nid) {
6100         case XBASS_XOVER:
6101                 knew.info = ca0132_alt_xbass_xover_slider_info;
6102                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6103                 knew.put = ca0132_alt_xbass_xover_slider_put;
6104                 break;
6105         default:
6106                 knew.info = ca0132_alt_effect_slider_info;
6107                 knew.get = ca0132_alt_slider_ctl_get;
6108                 knew.put = ca0132_alt_effect_slider_put;
6109                 knew.private_value =
6110                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6111                 break;
6112         }
6113
6114         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6115 }
6116
6117 /*
6118  * Added FX: prefix for the alternative codecs, because otherwise the surround
6119  * effect would conflict with the Surround sound volume control. Also seems more
6120  * clear as to what the switches do. Left alone for others.
6121  */
6122 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6123                          const char *pfx, int dir)
6124 {
6125         struct ca0132_spec *spec = codec->spec;
6126         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6127         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6128         struct snd_kcontrol_new knew =
6129                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6130         /* If using alt_controls, add FX: prefix. But, don't add FX:
6131          * prefix to OutFX or InFX enable controls.
6132          */
6133         if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6134                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6135         else
6136                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6137
6138         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6139 }
6140
6141 static int add_voicefx(struct hda_codec *codec)
6142 {
6143         struct snd_kcontrol_new knew =
6144                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6145                                     VOICEFX, 1, 0, HDA_INPUT);
6146         knew.info = ca0132_voicefx_info;
6147         knew.get = ca0132_voicefx_get;
6148         knew.put = ca0132_voicefx_put;
6149         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6150 }
6151
6152 /* Create the EQ Preset control */
6153 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6154 {
6155         struct snd_kcontrol_new knew =
6156                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6157                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6158         knew.info = ca0132_alt_eq_preset_info;
6159         knew.get = ca0132_alt_eq_preset_get;
6160         knew.put = ca0132_alt_eq_preset_put;
6161         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6162                                 snd_ctl_new1(&knew, codec));
6163 }
6164
6165 /*
6166  * Add enumerated control for the three different settings of the smart volume
6167  * output effect. Normal just uses the slider value, and loud and night are
6168  * their own things that ignore that value.
6169  */
6170 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6171 {
6172         struct snd_kcontrol_new knew =
6173                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6174                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6175         knew.info = ca0132_alt_svm_setting_info;
6176         knew.get = ca0132_alt_svm_setting_get;
6177         knew.put = ca0132_alt_svm_setting_put;
6178         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6179                                 snd_ctl_new1(&knew, codec));
6180
6181 }
6182
6183 /*
6184  * Create an Output Select enumerated control for codecs with surround
6185  * out capabilities.
6186  */
6187 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6188 {
6189         struct snd_kcontrol_new knew =
6190                 HDA_CODEC_MUTE_MONO("Output Select",
6191                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6192         knew.info = ca0132_alt_output_select_get_info;
6193         knew.get = ca0132_alt_output_select_get;
6194         knew.put = ca0132_alt_output_select_put;
6195         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6196                                 snd_ctl_new1(&knew, codec));
6197 }
6198
6199 /*
6200  * Create an Input Source enumerated control for the alternate ca0132 codecs
6201  * because the front microphone has no auto-detect, and Line-in has to be set
6202  * somehow.
6203  */
6204 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6205 {
6206         struct snd_kcontrol_new knew =
6207                 HDA_CODEC_MUTE_MONO("Input Source",
6208                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6209         knew.info = ca0132_alt_input_source_info;
6210         knew.get = ca0132_alt_input_source_get;
6211         knew.put = ca0132_alt_input_source_put;
6212         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6213                                 snd_ctl_new1(&knew, codec));
6214 }
6215
6216 /*
6217  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6218  * more control than the original mic boost, which is either full 30dB or off.
6219  */
6220 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6221 {
6222         struct snd_kcontrol_new knew =
6223                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6224                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6225         knew.info = ca0132_alt_mic_boost_info;
6226         knew.get = ca0132_alt_mic_boost_get;
6227         knew.put = ca0132_alt_mic_boost_put;
6228         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6229                                 snd_ctl_new1(&knew, codec));
6230
6231 }
6232
6233 /*
6234  * Add headphone gain enumerated control for the AE-5. This switches between
6235  * three modes, low, medium, and high. When non-headphone outputs are selected,
6236  * it is automatically set to high. This is the same behavior as Windows.
6237  */
6238 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6239 {
6240         struct snd_kcontrol_new knew =
6241                 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6242                                     AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6243         knew.info = ae5_headphone_gain_info;
6244         knew.get = ae5_headphone_gain_get;
6245         knew.put = ae5_headphone_gain_put;
6246         return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6247                                 snd_ctl_new1(&knew, codec));
6248 }
6249
6250 /*
6251  * Add sound filter enumerated control for the AE-5. This adds three different
6252  * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6253  * read into it, it changes the DAC's interpolation filter.
6254  */
6255 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6256 {
6257         struct snd_kcontrol_new knew =
6258                 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6259                                     AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6260         knew.info = ae5_sound_filter_info;
6261         knew.get = ae5_sound_filter_get;
6262         knew.put = ae5_sound_filter_put;
6263         return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6264                                 snd_ctl_new1(&knew, codec));
6265 }
6266
6267 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6268 {
6269         struct snd_kcontrol_new knew =
6270                 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6271                                     ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6272
6273         return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6274                                 snd_ctl_new1(&knew, codec));
6275 }
6276
6277 /*
6278  * Need to create slave controls for the alternate codecs that have surround
6279  * capabilities.
6280  */
6281 static const char * const ca0132_alt_slave_pfxs[] = {
6282         "Front", "Surround", "Center", "LFE", NULL,
6283 };
6284
6285 /*
6286  * Also need special channel map, because the default one is incorrect.
6287  * I think this has to do with the pin for rear surround being 0x11,
6288  * and the center/lfe being 0x10. Usually the pin order is the opposite.
6289  */
6290 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6291         { .channels = 2,
6292           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6293         { .channels = 4,
6294           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6295                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6296         { .channels = 6,
6297           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6298                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6299                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6300         { }
6301 };
6302
6303 /* Add the correct chmap for streams with 6 channels. */
6304 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6305 {
6306         int err = 0;
6307         struct hda_pcm *pcm;
6308
6309         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6310                 struct hda_pcm_stream *hinfo =
6311                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6312                 struct snd_pcm_chmap *chmap;
6313                 const struct snd_pcm_chmap_elem *elem;
6314
6315                 elem = ca0132_alt_chmaps;
6316                 if (hinfo->channels_max == 6) {
6317                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
6318                                         SNDRV_PCM_STREAM_PLAYBACK,
6319                                         elem, hinfo->channels_max, 0, &chmap);
6320                         if (err < 0)
6321                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6322                 }
6323         }
6324 }
6325
6326 /*
6327  * When changing Node IDs for Mixer Controls below, make sure to update
6328  * Node IDs in ca0132_config() as well.
6329  */
6330 static const struct snd_kcontrol_new ca0132_mixer[] = {
6331         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6332         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6333         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6334         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6335         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6336         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6337         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6338         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6339         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6340                                0x12, 1, HDA_INPUT),
6341         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6342                                VNID_HP_SEL, 1, HDA_OUTPUT),
6343         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6344                                VNID_AMIC1_SEL, 1, HDA_INPUT),
6345         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6346                                VNID_HP_ASEL, 1, HDA_OUTPUT),
6347         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6348                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
6349         { } /* end */
6350 };
6351
6352 /*
6353  * Desktop specific control mixer. Removes auto-detect for mic, and adds
6354  * surround controls. Also sets both the Front Playback and Capture Volume
6355  * controls to alt so they set the DSP's decibel level.
6356  */
6357 static const struct snd_kcontrol_new desktop_mixer[] = {
6358         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6359         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6360         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6361         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6362         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6363         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6364         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6365         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6366         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6367         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6368         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6369         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6370         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6371                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
6372         { } /* end */
6373 };
6374
6375 /*
6376  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6377  * because it doesn't set decibel levels for the DSP for capture.
6378  */
6379 static const struct snd_kcontrol_new r3di_mixer[] = {
6380         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6381         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6382         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6383         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6384         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6385         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6386         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6387         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6388         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6389         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6390         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6391         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6392         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6393                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
6394         { } /* end */
6395 };
6396
6397 static int ca0132_build_controls(struct hda_codec *codec)
6398 {
6399         struct ca0132_spec *spec = codec->spec;
6400         int i, num_fx, num_sliders;
6401         int err = 0;
6402
6403         /* Add Mixer controls */
6404         for (i = 0; i < spec->num_mixers; i++) {
6405                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6406                 if (err < 0)
6407                         return err;
6408         }
6409         /* Setup vmaster with surround slaves for desktop ca0132 devices */
6410         if (ca0132_use_alt_functions(spec)) {
6411                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6412                                         spec->tlv);
6413                 snd_hda_add_vmaster(codec, "Master Playback Volume",
6414                                         spec->tlv, ca0132_alt_slave_pfxs,
6415                                         "Playback Volume");
6416                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6417                                             NULL, ca0132_alt_slave_pfxs,
6418                                             "Playback Switch",
6419                                             true, &spec->vmaster_mute.sw_kctl);
6420                 if (err < 0)
6421                         return err;
6422         }
6423
6424         /* Add in and out effects controls.
6425          * VoiceFX, PE and CrystalVoice are added separately.
6426          */
6427         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6428         for (i = 0; i < num_fx; i++) {
6429                 /* Desktop cards break if Echo Cancellation is used. */
6430                 if (ca0132_use_pci_mmio(spec)) {
6431                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6432                                                 OUT_EFFECTS_COUNT))
6433                                 continue;
6434                 }
6435
6436                 err = add_fx_switch(codec, ca0132_effects[i].nid,
6437                                     ca0132_effects[i].name,
6438                                     ca0132_effects[i].direct);
6439                 if (err < 0)
6440                         return err;
6441         }
6442         /*
6443          * If codec has use_alt_controls set to true, add effect level sliders,
6444          * EQ presets, and Smart Volume presets. Also, change names to add FX
6445          * prefix, and change PlayEnhancement and CrystalVoice to match.
6446          */
6447         if (ca0132_use_alt_controls(spec)) {
6448                 err = ca0132_alt_add_svm_enum(codec);
6449                 if (err < 0)
6450                         return err;
6451
6452                 err = add_ca0132_alt_eq_presets(codec);
6453                 if (err < 0)
6454                         return err;
6455
6456                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6457                                         "Enable OutFX", 0);
6458                 if (err < 0)
6459                         return err;
6460
6461                 err = add_fx_switch(codec, CRYSTAL_VOICE,
6462                                         "Enable InFX", 1);
6463                 if (err < 0)
6464                         return err;
6465
6466                 num_sliders = OUT_EFFECTS_COUNT - 1;
6467                 for (i = 0; i < num_sliders; i++) {
6468                         err = ca0132_alt_add_effect_slider(codec,
6469                                             ca0132_effects[i].nid,
6470                                             ca0132_effects[i].name,
6471                                             ca0132_effects[i].direct);
6472                         if (err < 0)
6473                                 return err;
6474                 }
6475
6476                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6477                                         "X-Bass Crossover", EFX_DIR_OUT);
6478
6479                 if (err < 0)
6480                         return err;
6481         } else {
6482                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6483                                         "PlayEnhancement", 0);
6484                 if (err < 0)
6485                         return err;
6486
6487                 err = add_fx_switch(codec, CRYSTAL_VOICE,
6488                                         "CrystalVoice", 1);
6489                 if (err < 0)
6490                         return err;
6491         }
6492         err = add_voicefx(codec);
6493         if (err < 0)
6494                 return err;
6495
6496         /*
6497          * If the codec uses alt_functions, you need the enumerated controls
6498          * to select the new outputs and inputs, plus add the new mic boost
6499          * setting control.
6500          */
6501         if (ca0132_use_alt_functions(spec)) {
6502                 err = ca0132_alt_add_output_enum(codec);
6503                 if (err < 0)
6504                         return err;
6505                 err = ca0132_alt_add_mic_boost_enum(codec);
6506                 if (err < 0)
6507                         return err;
6508                 /*
6509                  * ZxR only has microphone input, there is no front panel
6510                  * header on the card, and aux-in is handled by the DBPro board.
6511                  */
6512                 if (ca0132_quirk(spec) != QUIRK_ZXR) {
6513                         err = ca0132_alt_add_input_enum(codec);
6514                         if (err < 0)
6515                                 return err;
6516                 }
6517         }
6518
6519         if (ca0132_quirk(spec) == QUIRK_AE5) {
6520                 err = ae5_add_headphone_gain_enum(codec);
6521                 if (err < 0)
6522                         return err;
6523                 err = ae5_add_sound_filter_enum(codec);
6524                 if (err < 0)
6525                         return err;
6526         }
6527
6528         if (ca0132_quirk(spec) == QUIRK_ZXR) {
6529                 err = zxr_add_headphone_gain_switch(codec);
6530                 if (err < 0)
6531                         return err;
6532         }
6533 #ifdef ENABLE_TUNING_CONTROLS
6534         add_tuning_ctls(codec);
6535 #endif
6536
6537         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6538         if (err < 0)
6539                 return err;
6540
6541         if (spec->dig_out) {
6542                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6543                                                     spec->dig_out);
6544                 if (err < 0)
6545                         return err;
6546                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6547                 if (err < 0)
6548                         return err;
6549                 /* spec->multiout.share_spdif = 1; */
6550         }
6551
6552         if (spec->dig_in) {
6553                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6554                 if (err < 0)
6555                         return err;
6556         }
6557
6558         if (ca0132_use_alt_functions(spec))
6559                 ca0132_alt_add_chmap_ctls(codec);
6560
6561         return 0;
6562 }
6563
6564 static int dbpro_build_controls(struct hda_codec *codec)
6565 {
6566         struct ca0132_spec *spec = codec->spec;
6567         int err = 0;
6568
6569         if (spec->dig_out) {
6570                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6571                                 spec->dig_out);
6572                 if (err < 0)
6573                         return err;
6574         }
6575
6576         if (spec->dig_in) {
6577                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6578                 if (err < 0)
6579                         return err;
6580         }
6581
6582         return 0;
6583 }
6584
6585 /*
6586  * PCM
6587  */
6588 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
6589         .substreams = 1,
6590         .channels_min = 2,
6591         .channels_max = 6,
6592         .ops = {
6593                 .prepare = ca0132_playback_pcm_prepare,
6594                 .cleanup = ca0132_playback_pcm_cleanup,
6595                 .get_delay = ca0132_playback_pcm_delay,
6596         },
6597 };
6598
6599 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
6600         .substreams = 1,
6601         .channels_min = 2,
6602         .channels_max = 2,
6603         .ops = {
6604                 .prepare = ca0132_capture_pcm_prepare,
6605                 .cleanup = ca0132_capture_pcm_cleanup,
6606                 .get_delay = ca0132_capture_pcm_delay,
6607         },
6608 };
6609
6610 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
6611         .substreams = 1,
6612         .channels_min = 2,
6613         .channels_max = 2,
6614         .ops = {
6615                 .open = ca0132_dig_playback_pcm_open,
6616                 .close = ca0132_dig_playback_pcm_close,
6617                 .prepare = ca0132_dig_playback_pcm_prepare,
6618                 .cleanup = ca0132_dig_playback_pcm_cleanup
6619         },
6620 };
6621
6622 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
6623         .substreams = 1,
6624         .channels_min = 2,
6625         .channels_max = 2,
6626 };
6627
6628 static int ca0132_build_pcms(struct hda_codec *codec)
6629 {
6630         struct ca0132_spec *spec = codec->spec;
6631         struct hda_pcm *info;
6632
6633         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6634         if (!info)
6635                 return -ENOMEM;
6636         if (ca0132_use_alt_functions(spec)) {
6637                 info->own_chmap = true;
6638                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6639                         = ca0132_alt_chmaps;
6640         }
6641         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6642         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6643         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6644                 spec->multiout.max_channels;
6645         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6646         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6647         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6648
6649         /* With the DSP enabled, desktops don't use this ADC. */
6650         if (!ca0132_use_alt_functions(spec)) {
6651                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6652                 if (!info)
6653                         return -ENOMEM;
6654                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6655                         ca0132_pcm_analog_capture;
6656                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6657                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6658         }
6659
6660         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6661         if (!info)
6662                 return -ENOMEM;
6663         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6664         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6665         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6666
6667         if (!spec->dig_out && !spec->dig_in)
6668                 return 0;
6669
6670         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6671         if (!info)
6672                 return -ENOMEM;
6673         info->pcm_type = HDA_PCM_TYPE_SPDIF;
6674         if (spec->dig_out) {
6675                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6676                         ca0132_pcm_digital_playback;
6677                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6678         }
6679         if (spec->dig_in) {
6680                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6681                         ca0132_pcm_digital_capture;
6682                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6683         }
6684
6685         return 0;
6686 }
6687
6688 static int dbpro_build_pcms(struct hda_codec *codec)
6689 {
6690         struct ca0132_spec *spec = codec->spec;
6691         struct hda_pcm *info;
6692
6693         info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6694         if (!info)
6695                 return -ENOMEM;
6696         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6697         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6698         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6699
6700
6701         if (!spec->dig_out && !spec->dig_in)
6702                 return 0;
6703
6704         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6705         if (!info)
6706                 return -ENOMEM;
6707         info->pcm_type = HDA_PCM_TYPE_SPDIF;
6708         if (spec->dig_out) {
6709                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6710                         ca0132_pcm_digital_playback;
6711                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6712         }
6713         if (spec->dig_in) {
6714                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6715                         ca0132_pcm_digital_capture;
6716                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6717         }
6718
6719         return 0;
6720 }
6721
6722 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6723 {
6724         if (pin) {
6725                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6726                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6727                         snd_hda_codec_write(codec, pin, 0,
6728                                             AC_VERB_SET_AMP_GAIN_MUTE,
6729                                             AMP_OUT_UNMUTE);
6730         }
6731         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6732                 snd_hda_codec_write(codec, dac, 0,
6733                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6734 }
6735
6736 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6737 {
6738         if (pin) {
6739                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6740                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6741                         snd_hda_codec_write(codec, pin, 0,
6742                                             AC_VERB_SET_AMP_GAIN_MUTE,
6743                                             AMP_IN_UNMUTE(0));
6744         }
6745         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6746                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6747                                     AMP_IN_UNMUTE(0));
6748
6749                 /* init to 0 dB and unmute. */
6750                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6751                                          HDA_AMP_VOLMASK, 0x5a);
6752                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6753                                          HDA_AMP_MUTE, 0);
6754         }
6755 }
6756
6757 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6758 {
6759         unsigned int caps;
6760
6761         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6762                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6763         snd_hda_override_amp_caps(codec, nid, dir, caps);
6764 }
6765
6766 /*
6767  * Switch between Digital built-in mic and analog mic.
6768  */
6769 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6770 {
6771         struct ca0132_spec *spec = codec->spec;
6772         unsigned int tmp;
6773         u8 val;
6774         unsigned int oldval;
6775
6776         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6777
6778         oldval = stop_mic1(codec);
6779         ca0132_set_vipsource(codec, 0);
6780         if (enable) {
6781                 /* set DMic input as 2-ch */
6782                 tmp = FLOAT_TWO;
6783                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6784
6785                 val = spec->dmic_ctl;
6786                 val |= 0x80;
6787                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6788                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6789
6790                 if (!(spec->dmic_ctl & 0x20))
6791                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6792         } else {
6793                 /* set AMic input as mono */
6794                 tmp = FLOAT_ONE;
6795                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6796
6797                 val = spec->dmic_ctl;
6798                 /* clear bit7 and bit5 to disable dmic */
6799                 val &= 0x5f;
6800                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6801                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6802
6803                 if (!(spec->dmic_ctl & 0x20))
6804                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6805         }
6806         ca0132_set_vipsource(codec, 1);
6807         resume_mic1(codec, oldval);
6808 }
6809
6810 /*
6811  * Initialization for Digital Mic.
6812  */
6813 static void ca0132_init_dmic(struct hda_codec *codec)
6814 {
6815         struct ca0132_spec *spec = codec->spec;
6816         u8 val;
6817
6818         /* Setup Digital Mic here, but don't enable.
6819          * Enable based on jack detect.
6820          */
6821
6822         /* MCLK uses MPIO1, set to enable.
6823          * Bit 2-0: MPIO select
6824          * Bit   3: set to disable
6825          * Bit 7-4: reserved
6826          */
6827         val = 0x01;
6828         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6829                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6830
6831         /* Data1 uses MPIO3. Data2 not use
6832          * Bit 2-0: Data1 MPIO select
6833          * Bit   3: set disable Data1
6834          * Bit 6-4: Data2 MPIO select
6835          * Bit   7: set disable Data2
6836          */
6837         val = 0x83;
6838         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6839                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
6840
6841         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6842          * Bit 3-0: Channel mask
6843          * Bit   4: set for 48KHz, clear for 32KHz
6844          * Bit   5: mode
6845          * Bit   6: set to select Data2, clear for Data1
6846          * Bit   7: set to enable DMic, clear for AMic
6847          */
6848         if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
6849                 val = 0x33;
6850         else
6851                 val = 0x23;
6852         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6853         spec->dmic_ctl = val;
6854         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6855                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
6856 }
6857
6858 /*
6859  * Initialization for Analog Mic 2
6860  */
6861 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6862 {
6863         struct ca0132_spec *spec = codec->spec;
6864
6865         mutex_lock(&spec->chipio_mutex);
6866         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6867                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6868         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6869                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6870         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6871                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6872         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6873                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6874         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6875                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6876         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6877                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6878         mutex_unlock(&spec->chipio_mutex);
6879 }
6880
6881 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6882 {
6883         struct ca0132_spec *spec = codec->spec;
6884         int i;
6885
6886         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6887         snd_hda_codec_update_widgets(codec);
6888
6889         for (i = 0; i < spec->multiout.num_dacs; i++)
6890                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6891
6892         for (i = 0; i < spec->num_outputs; i++)
6893                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6894
6895         for (i = 0; i < spec->num_inputs; i++) {
6896                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6897                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6898         }
6899 }
6900
6901 /*
6902  * Creates a dummy stream to bind the output to. This seems to have to be done
6903  * after changing the main outputs source and destination streams.
6904  */
6905 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
6906 {
6907         struct ca0132_spec *spec = codec->spec;
6908         unsigned int stream_format;
6909
6910         stream_format = snd_hdac_calc_stream_format(48000, 2,
6911                         SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6912
6913         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6914                                         0, stream_format);
6915
6916         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6917 }
6918
6919 /*
6920  * Initialize mic for non-chromebook ca0132 implementations.
6921  */
6922 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
6923 {
6924         struct ca0132_spec *spec = codec->spec;
6925         unsigned int tmp;
6926
6927         /* Mic 1 Setup */
6928         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6929         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6930         if (ca0132_quirk(spec) == QUIRK_R3DI) {
6931                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6932                 tmp = FLOAT_ONE;
6933         } else
6934                 tmp = FLOAT_THREE;
6935         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6936
6937         /* Mic 2 setup (not present on desktop cards) */
6938         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6939         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6940         if (ca0132_quirk(spec) == QUIRK_R3DI)
6941                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6942         tmp = FLOAT_ZERO;
6943         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6944 }
6945
6946 /*
6947  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6948  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6949  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6950  * having an updated DAC, which changes the destination to that DAC.
6951  */
6952 static void sbz_connect_streams(struct hda_codec *codec)
6953 {
6954         struct ca0132_spec *spec = codec->spec;
6955
6956         mutex_lock(&spec->chipio_mutex);
6957
6958         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6959
6960         chipio_set_stream_channels(codec, 0x0C, 6);
6961         chipio_set_stream_control(codec, 0x0C, 1);
6962
6963         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6964         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6965
6966         /* Setup stream 0x14 with it's source and destination points */
6967         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6968         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6969         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6970         chipio_set_stream_channels(codec, 0x14, 2);
6971         chipio_set_stream_control(codec, 0x14, 1);
6972
6973         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6974
6975         mutex_unlock(&spec->chipio_mutex);
6976 }
6977
6978 /*
6979  * Write data through ChipIO to setup proper stream destinations.
6980  * Not sure how it exactly works, but it seems to direct data
6981  * to different destinations. Example is f8 to c0, e0 to c0.
6982  * All I know is, if you don't set these, you get no sound.
6983  */
6984 static void sbz_chipio_startup_data(struct hda_codec *codec)
6985 {
6986         struct ca0132_spec *spec = codec->spec;
6987
6988         mutex_lock(&spec->chipio_mutex);
6989         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6990
6991         /* These control audio output */
6992         chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6993         chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6994         chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6995         chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6996         /* Signal to update I think */
6997         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6998
6999         chipio_set_stream_channels(codec, 0x0C, 6);
7000         chipio_set_stream_control(codec, 0x0C, 1);
7001         /* No clue what these control */
7002         if (ca0132_quirk(spec) == QUIRK_SBZ) {
7003                 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
7004                 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
7005                 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
7006                 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
7007                 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
7008                 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
7009                 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
7010                 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
7011                 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
7012                 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
7013                 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
7014                 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
7015         } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
7016                 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
7017                 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
7018                 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
7019                 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
7020                 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7021                 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7022                 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7023                 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7024         }
7025         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7026
7027         codec_dbg(codec, "Startup Data exited, mutex released.\n");
7028         mutex_unlock(&spec->chipio_mutex);
7029 }
7030
7031 /*
7032  * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7033  * done after the DSP is loaded.
7034  */
7035 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
7036 {
7037         struct ca0132_spec *spec = codec->spec;
7038         unsigned int tmp, i;
7039
7040         /*
7041          * Gotta run these twice, or else mic works inconsistently. Not clear
7042          * why this is, but multiple tests have confirmed it.
7043          */
7044         for (i = 0; i < 2; i++) {
7045                 switch (ca0132_quirk(spec)) {
7046                 case QUIRK_SBZ:
7047                 case QUIRK_AE5:
7048                         tmp = 0x00000003;
7049                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7050                         tmp = 0x00000000;
7051                         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7052                         tmp = 0x00000001;
7053                         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7054                         tmp = 0x00000004;
7055                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7056                         tmp = 0x00000005;
7057                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7058                         tmp = 0x00000000;
7059                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7060                         break;
7061                 case QUIRK_R3D:
7062                 case QUIRK_R3DI:
7063                         tmp = 0x00000000;
7064                         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7065                         tmp = 0x00000001;
7066                         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7067                         tmp = 0x00000004;
7068                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7069                         tmp = 0x00000005;
7070                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7071                         tmp = 0x00000000;
7072                         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7073                         break;
7074                 default:
7075                         break;
7076                 }
7077                 msleep(100);
7078         }
7079 }
7080
7081 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7082 {
7083         struct ca0132_spec *spec = codec->spec;
7084         unsigned int tmp;
7085
7086         chipio_set_stream_control(codec, 0x03, 0);
7087         chipio_set_stream_control(codec, 0x04, 0);
7088
7089         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7090         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7091
7092         tmp = FLOAT_THREE;
7093         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7094
7095         chipio_set_stream_control(codec, 0x03, 1);
7096         chipio_set_stream_control(codec, 0x04, 1);
7097
7098         switch (ca0132_quirk(spec)) {
7099         case QUIRK_SBZ:
7100                 chipio_write(codec, 0x18b098, 0x0000000c);
7101                 chipio_write(codec, 0x18b09C, 0x0000000c);
7102                 break;
7103         case QUIRK_AE5:
7104                 chipio_write(codec, 0x18b098, 0x0000000c);
7105                 chipio_write(codec, 0x18b09c, 0x0000004c);
7106                 break;
7107         default:
7108                 break;
7109         }
7110 }
7111
7112 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7113 {
7114         struct ca0132_spec *spec = codec->spec;
7115
7116         chipio_8051_write_direct(codec, 0x93, 0x10);
7117         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7118                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7119         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7120                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7121
7122         writeb(0xff, spec->mem_base + 0x304);
7123         writeb(0xff, spec->mem_base + 0x304);
7124         writeb(0xff, spec->mem_base + 0x304);
7125         writeb(0xff, spec->mem_base + 0x304);
7126         writeb(0x00, spec->mem_base + 0x100);
7127         writeb(0xff, spec->mem_base + 0x304);
7128         writeb(0x00, spec->mem_base + 0x100);
7129         writeb(0xff, spec->mem_base + 0x304);
7130         writeb(0x00, spec->mem_base + 0x100);
7131         writeb(0xff, spec->mem_base + 0x304);
7132         writeb(0x00, spec->mem_base + 0x100);
7133         writeb(0xff, spec->mem_base + 0x304);
7134
7135         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7136         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7137         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7138 }
7139
7140 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7141 {
7142         /*
7143          * Param3 in the 8051's memory is represented by the ascii string 'mch'
7144          * which seems to be 'multichannel'. This is also mentioned in the
7145          * AE-5's registry values in Windows.
7146          */
7147         chipio_set_control_param(codec, 3, 0);
7148         /*
7149          * I believe ASI is 'audio serial interface' and that it's used to
7150          * change colors on the external LED strip connected to the AE-5.
7151          */
7152         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7153
7154         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7155         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7156
7157         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7158                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7159         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7160                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7161         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7162                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7163 }
7164
7165 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7166 {
7167         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7168                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7169         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7170                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7171
7172         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7173                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7174         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7175                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7176
7177         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7178                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7179         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7180                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7181
7182         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7183                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7184         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7185                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7186
7187         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7188                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7189         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7190                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7191 }
7192
7193 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7194 {
7195         struct ca0132_spec *spec = codec->spec;
7196
7197         mutex_lock(&spec->chipio_mutex);
7198
7199         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7200
7201         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7202
7203         chipio_set_stream_channels(codec, 0x0C, 6);
7204         chipio_set_stream_control(codec, 0x0C, 1);
7205
7206         chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7207
7208         chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7209         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7210         chipio_set_stream_channels(codec, 0x18, 6);
7211         chipio_set_stream_control(codec, 0x18, 1);
7212
7213         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7214
7215         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7216                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7217         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7218                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7219
7220         ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7221
7222         mutex_unlock(&spec->chipio_mutex);
7223 }
7224
7225 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7226 {
7227         struct ca0132_spec *spec = codec->spec;
7228
7229         mutex_lock(&spec->chipio_mutex);
7230
7231         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7232         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7233         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7234         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7235
7236         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7237         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7238         ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7239         ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7240         ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7241         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7242         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7243         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7244         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7245         ca0113_mmio_gpio_set(codec, 0, true);
7246         ca0113_mmio_gpio_set(codec, 1, true);
7247         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7248
7249         chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7250
7251         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7252         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7253
7254         mutex_unlock(&spec->chipio_mutex);
7255 }
7256
7257 /*
7258  * Setup default parameters for DSP
7259  */
7260 static void ca0132_setup_defaults(struct hda_codec *codec)
7261 {
7262         struct ca0132_spec *spec = codec->spec;
7263         unsigned int tmp;
7264         int num_fx;
7265         int idx, i;
7266
7267         if (spec->dsp_state != DSP_DOWNLOADED)
7268                 return;
7269
7270         /* out, in effects + voicefx */
7271         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7272         for (idx = 0; idx < num_fx; idx++) {
7273                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7274                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7275                                              ca0132_effects[idx].reqs[i],
7276                                              ca0132_effects[idx].def_vals[i]);
7277                 }
7278         }
7279
7280         /*remove DSP headroom*/
7281         tmp = FLOAT_ZERO;
7282         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7283
7284         /*set speaker EQ bypass attenuation*/
7285         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7286
7287         /* set AMic1 and AMic2 as mono mic */
7288         tmp = FLOAT_ONE;
7289         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7290         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7291
7292         /* set AMic1 as CrystalVoice input */
7293         tmp = FLOAT_ONE;
7294         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7295
7296         /* set WUH source */
7297         tmp = FLOAT_TWO;
7298         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7299 }
7300
7301 /*
7302  * Setup default parameters for Recon3D/Recon3Di DSP.
7303  */
7304
7305 static void r3d_setup_defaults(struct hda_codec *codec)
7306 {
7307         struct ca0132_spec *spec = codec->spec;
7308         unsigned int tmp;
7309         int num_fx;
7310         int idx, i;
7311
7312         if (spec->dsp_state != DSP_DOWNLOADED)
7313                 return;
7314
7315         ca0132_alt_dsp_scp_startup(codec);
7316         ca0132_alt_init_analog_mics(codec);
7317
7318         /*remove DSP headroom*/
7319         tmp = FLOAT_ZERO;
7320         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7321
7322         /* set WUH source */
7323         tmp = FLOAT_TWO;
7324         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7325         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7326
7327         /* Set speaker source? */
7328         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7329
7330         if (ca0132_quirk(spec) == QUIRK_R3DI)
7331                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7332
7333         /* Setup effect defaults */
7334         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7335         for (idx = 0; idx < num_fx; idx++) {
7336                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7337                         dspio_set_uint_param(codec,
7338                                         ca0132_effects[idx].mid,
7339                                         ca0132_effects[idx].reqs[i],
7340                                         ca0132_effects[idx].def_vals[i]);
7341                 }
7342         }
7343 }
7344
7345 /*
7346  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7347  * than the Chromebook setup.
7348  */
7349 static void sbz_setup_defaults(struct hda_codec *codec)
7350 {
7351         struct ca0132_spec *spec = codec->spec;
7352         unsigned int tmp;
7353         int num_fx;
7354         int idx, i;
7355
7356         if (spec->dsp_state != DSP_DOWNLOADED)
7357                 return;
7358
7359         ca0132_alt_dsp_scp_startup(codec);
7360         ca0132_alt_init_analog_mics(codec);
7361         sbz_connect_streams(codec);
7362         sbz_chipio_startup_data(codec);
7363
7364         chipio_set_stream_control(codec, 0x03, 1);
7365         chipio_set_stream_control(codec, 0x04, 1);
7366
7367         /*
7368          * Sets internal input loopback to off, used to have a switch to
7369          * enable input loopback, but turned out to be way too buggy.
7370          */
7371         tmp = FLOAT_ONE;
7372         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7373         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7374
7375         /*remove DSP headroom*/
7376         tmp = FLOAT_ZERO;
7377         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7378
7379         /* set WUH source */
7380         tmp = FLOAT_TWO;
7381         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7382         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7383
7384         /* Set speaker source? */
7385         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7386
7387         ca0132_alt_dsp_initial_mic_setup(codec);
7388
7389         /* out, in effects + voicefx */
7390         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7391         for (idx = 0; idx < num_fx; idx++) {
7392                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7393                         dspio_set_uint_param(codec,
7394                                         ca0132_effects[idx].mid,
7395                                         ca0132_effects[idx].reqs[i],
7396                                         ca0132_effects[idx].def_vals[i]);
7397                 }
7398         }
7399
7400         ca0132_alt_create_dummy_stream(codec);
7401 }
7402
7403 /*
7404  * Setup default parameters for the Sound BlasterX AE-5 DSP.
7405  */
7406 static void ae5_setup_defaults(struct hda_codec *codec)
7407 {
7408         struct ca0132_spec *spec = codec->spec;
7409         unsigned int tmp;
7410         int num_fx;
7411         int idx, i;
7412
7413         if (spec->dsp_state != DSP_DOWNLOADED)
7414                 return;
7415
7416         ca0132_alt_dsp_scp_startup(codec);
7417         ca0132_alt_init_analog_mics(codec);
7418         chipio_set_stream_control(codec, 0x03, 1);
7419         chipio_set_stream_control(codec, 0x04, 1);
7420
7421         /* New, unknown SCP req's */
7422         tmp = FLOAT_ZERO;
7423         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7424         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7425         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7426         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7427
7428         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7429         ca0113_mmio_gpio_set(codec, 0, false);
7430         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7431
7432         /* Internal loopback off */
7433         tmp = FLOAT_ONE;
7434         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7435         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7436
7437         /*remove DSP headroom*/
7438         tmp = FLOAT_ZERO;
7439         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7440
7441         /* set WUH source */
7442         tmp = FLOAT_TWO;
7443         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7444         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7445
7446         /* Set speaker source? */
7447         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7448
7449         ca0132_alt_dsp_initial_mic_setup(codec);
7450         ae5_post_dsp_register_set(codec);
7451         ae5_post_dsp_param_setup(codec);
7452         ae5_post_dsp_pll_setup(codec);
7453         ae5_post_dsp_stream_setup(codec);
7454         ae5_post_dsp_startup_data(codec);
7455
7456         /* out, in effects + voicefx */
7457         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7458         for (idx = 0; idx < num_fx; idx++) {
7459                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7460                         dspio_set_uint_param(codec,
7461                                         ca0132_effects[idx].mid,
7462                                         ca0132_effects[idx].reqs[i],
7463                                         ca0132_effects[idx].def_vals[i]);
7464                 }
7465         }
7466
7467         ca0132_alt_create_dummy_stream(codec);
7468 }
7469
7470 /*
7471  * Initialization of flags in chip
7472  */
7473 static void ca0132_init_flags(struct hda_codec *codec)
7474 {
7475         struct ca0132_spec *spec = codec->spec;
7476
7477         if (ca0132_use_alt_functions(spec)) {
7478                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7479                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7480                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7481                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7482                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7483                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7484                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7485                 chipio_set_control_flag(codec,
7486                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7487                 chipio_set_control_flag(codec,
7488                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7489         } else {
7490                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7491                 chipio_set_control_flag(codec,
7492                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7493                 chipio_set_control_flag(codec,
7494                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7495                 chipio_set_control_flag(codec,
7496                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7497                 chipio_set_control_flag(codec,
7498                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7499                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7500         }
7501 }
7502
7503 /*
7504  * Initialization of parameters in chip
7505  */
7506 static void ca0132_init_params(struct hda_codec *codec)
7507 {
7508         struct ca0132_spec *spec = codec->spec;
7509
7510         if (ca0132_use_alt_functions(spec)) {
7511                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7512                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7513                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7514                 chipio_set_control_param(codec, 0, 0);
7515                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7516         }
7517
7518         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7519         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7520 }
7521
7522 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7523 {
7524         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7525         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7526         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7527         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7528         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7529         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7530
7531         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7532         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7533         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7534 }
7535
7536 static bool ca0132_download_dsp_images(struct hda_codec *codec)
7537 {
7538         bool dsp_loaded = false;
7539         struct ca0132_spec *spec = codec->spec;
7540         const struct dsp_image_seg *dsp_os_image;
7541         const struct firmware *fw_entry = NULL;
7542         /*
7543          * Alternate firmwares for different variants. The Recon3Di apparently
7544          * can use the default firmware, but I'll leave the option in case
7545          * it needs it again.
7546          */
7547         switch (ca0132_quirk(spec)) {
7548         case QUIRK_SBZ:
7549         case QUIRK_R3D:
7550         case QUIRK_AE5:
7551                 if (reject_firmware(&fw_entry, DESKTOP_EFX_FILE,
7552                                         codec->card->dev) != 0)
7553                         codec_dbg(codec, "Desktop firmware not found.");
7554                 else
7555                         codec_dbg(codec, "Desktop firmware selected.");
7556                 break;
7557         case QUIRK_R3DI:
7558                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
7559                                         codec->card->dev) != 0)
7560                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
7561                 else
7562                         codec_dbg(codec, "Recon3Di firmware selected.");
7563                 break;
7564         default:
7565                 break;
7566         }
7567 /*(DEBLOBBED)*/
7568         if (!fw_entry) {
7569                 codec_dbg(codec, "Default firmware selected.");
7570                 if (reject_firmware(&fw_entry, EFX_FILE,
7571                                         codec->card->dev) != 0)
7572                         return false;
7573         }
7574
7575         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
7576         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
7577                 codec_err(codec, "ca0132 DSP load image failed\n");
7578                 goto exit_download;
7579         }
7580
7581         dsp_loaded = dspload_wait_loaded(codec);
7582
7583 exit_download:
7584         release_firmware(fw_entry);
7585
7586         return dsp_loaded;
7587 }
7588
7589 static void ca0132_download_dsp(struct hda_codec *codec)
7590 {
7591         struct ca0132_spec *spec = codec->spec;
7592
7593 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7594         return; /* NOP */
7595 #endif
7596
7597         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7598                 return; /* don't retry failures */
7599
7600         chipio_enable_clocks(codec);
7601         if (spec->dsp_state != DSP_DOWNLOADED) {
7602                 spec->dsp_state = DSP_DOWNLOADING;
7603
7604                 if (!ca0132_download_dsp_images(codec))
7605                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
7606                 else
7607                         spec->dsp_state = DSP_DOWNLOADED;
7608         }
7609
7610         /* For codecs using alt functions, this is already done earlier */
7611         if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
7612                 ca0132_set_dsp_msr(codec, true);
7613 }
7614
7615 static void ca0132_process_dsp_response(struct hda_codec *codec,
7616                                         struct hda_jack_callback *callback)
7617 {
7618         struct ca0132_spec *spec = codec->spec;
7619
7620         codec_dbg(codec, "ca0132_process_dsp_response\n");
7621         snd_hda_power_up_pm(codec);
7622         if (spec->wait_scp) {
7623                 if (dspio_get_response_data(codec) >= 0)
7624                         spec->wait_scp = 0;
7625         }
7626
7627         dspio_clear_response_queue(codec);
7628         snd_hda_power_down_pm(codec);
7629 }
7630
7631 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7632 {
7633         struct ca0132_spec *spec = codec->spec;
7634         struct hda_jack_tbl *tbl;
7635
7636         /* Delay enabling the HP amp, to let the mic-detection
7637          * state machine run.
7638          */
7639         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7640         if (tbl)
7641                 tbl->block_report = 1;
7642         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
7643 }
7644
7645 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7646 {
7647         struct ca0132_spec *spec = codec->spec;
7648
7649         if (ca0132_use_alt_functions(spec))
7650                 ca0132_alt_select_in(codec);
7651         else
7652                 ca0132_select_mic(codec);
7653 }
7654
7655 static void ca0132_init_unsol(struct hda_codec *codec)
7656 {
7657         struct ca0132_spec *spec = codec->spec;
7658         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7659         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
7660                                             amic_callback);
7661         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7662                                             ca0132_process_dsp_response);
7663         /* Front headphone jack detection */
7664         if (ca0132_use_alt_functions(spec))
7665                 snd_hda_jack_detect_enable_callback(codec,
7666                         spec->unsol_tag_front_hp, hp_callback);
7667 }
7668
7669 /*
7670  * Verbs tables.
7671  */
7672
7673 /* Sends before DSP download. */
7674 static struct hda_verb ca0132_base_init_verbs[] = {
7675         /*enable ct extension*/
7676         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
7677         {}
7678 };
7679
7680 /* Send at exit. */
7681 static struct hda_verb ca0132_base_exit_verbs[] = {
7682         /*set afg to D3*/
7683         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7684         /*disable ct extension*/
7685         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7686         {}
7687 };
7688
7689 /* Other verbs tables. Sends after DSP download. */
7690
7691 static struct hda_verb ca0132_init_verbs0[] = {
7692         /* chip init verbs */
7693         {0x15, 0x70D, 0xF0},
7694         {0x15, 0x70E, 0xFE},
7695         {0x15, 0x707, 0x75},
7696         {0x15, 0x707, 0xD3},
7697         {0x15, 0x707, 0x09},
7698         {0x15, 0x707, 0x53},
7699         {0x15, 0x707, 0xD4},
7700         {0x15, 0x707, 0xEF},
7701         {0x15, 0x707, 0x75},
7702         {0x15, 0x707, 0xD3},
7703         {0x15, 0x707, 0x09},
7704         {0x15, 0x707, 0x02},
7705         {0x15, 0x707, 0x37},
7706         {0x15, 0x707, 0x78},
7707         {0x15, 0x53C, 0xCE},
7708         {0x15, 0x575, 0xC9},
7709         {0x15, 0x53D, 0xCE},
7710         {0x15, 0x5B7, 0xC9},
7711         {0x15, 0x70D, 0xE8},
7712         {0x15, 0x70E, 0xFE},
7713         {0x15, 0x707, 0x02},
7714         {0x15, 0x707, 0x68},
7715         {0x15, 0x707, 0x62},
7716         {0x15, 0x53A, 0xCE},
7717         {0x15, 0x546, 0xC9},
7718         {0x15, 0x53B, 0xCE},
7719         {0x15, 0x5E8, 0xC9},
7720         {}
7721 };
7722
7723 /* Extra init verbs for desktop cards. */
7724 static struct hda_verb ca0132_init_verbs1[] = {
7725         {0x15, 0x70D, 0x20},
7726         {0x15, 0x70E, 0x19},
7727         {0x15, 0x707, 0x00},
7728         {0x15, 0x539, 0xCE},
7729         {0x15, 0x546, 0xC9},
7730         {0x15, 0x70D, 0xB7},
7731         {0x15, 0x70E, 0x09},
7732         {0x15, 0x707, 0x10},
7733         {0x15, 0x70D, 0xAF},
7734         {0x15, 0x70E, 0x09},
7735         {0x15, 0x707, 0x01},
7736         {0x15, 0x707, 0x05},
7737         {0x15, 0x70D, 0x73},
7738         {0x15, 0x70E, 0x09},
7739         {0x15, 0x707, 0x14},
7740         {0x15, 0x6FF, 0xC4},
7741         {}
7742 };
7743
7744 static void ca0132_init_chip(struct hda_codec *codec)
7745 {
7746         struct ca0132_spec *spec = codec->spec;
7747         int num_fx;
7748         int i;
7749         unsigned int on;
7750
7751         mutex_init(&spec->chipio_mutex);
7752
7753         spec->cur_out_type = SPEAKER_OUT;
7754         if (!ca0132_use_alt_functions(spec))
7755                 spec->cur_mic_type = DIGITAL_MIC;
7756         else
7757                 spec->cur_mic_type = REAR_MIC;
7758
7759         spec->cur_mic_boost = 0;
7760
7761         for (i = 0; i < VNODES_COUNT; i++) {
7762                 spec->vnode_lvol[i] = 0x5a;
7763                 spec->vnode_rvol[i] = 0x5a;
7764                 spec->vnode_lswitch[i] = 0;
7765                 spec->vnode_rswitch[i] = 0;
7766         }
7767
7768         /*
7769          * Default states for effects are in ca0132_effects[].
7770          */
7771         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7772         for (i = 0; i < num_fx; i++) {
7773                 on = (unsigned int)ca0132_effects[i].reqs[0];
7774                 spec->effects_switch[i] = on ? 1 : 0;
7775         }
7776         /*
7777          * Sets defaults for the effect slider controls, only for alternative
7778          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7779          */
7780         if (ca0132_use_alt_controls(spec)) {
7781                 spec->xbass_xover_freq = 8;
7782                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7783                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
7784         }
7785
7786         spec->voicefx_val = 0;
7787         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7788         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7789
7790         /*
7791          * The ZxR doesn't have a front panel header, and it's line-in is on
7792          * the daughter board. So, there is no input enum control, and we need
7793          * to make sure that spec->in_enum_val is set properly.
7794          */
7795         if (ca0132_quirk(spec) == QUIRK_ZXR)
7796                 spec->in_enum_val = REAR_MIC;
7797
7798 #ifdef ENABLE_TUNING_CONTROLS
7799         ca0132_init_tuning_defaults(codec);
7800 #endif
7801 }
7802
7803 /*
7804  * Recon3Di exit specific commands.
7805  */
7806 /* prevents popping noise on shutdown */
7807 static void r3di_gpio_shutdown(struct hda_codec *codec)
7808 {
7809         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7810 }
7811
7812 /*
7813  * Sound Blaster Z exit specific commands.
7814  */
7815 static void sbz_region2_exit(struct hda_codec *codec)
7816 {
7817         struct ca0132_spec *spec = codec->spec;
7818         unsigned int i;
7819
7820         for (i = 0; i < 4; i++)
7821                 writeb(0x0, spec->mem_base + 0x100);
7822         for (i = 0; i < 8; i++)
7823                 writeb(0xb3, spec->mem_base + 0x304);
7824
7825         ca0113_mmio_gpio_set(codec, 0, false);
7826         ca0113_mmio_gpio_set(codec, 1, false);
7827         ca0113_mmio_gpio_set(codec, 4, true);
7828         ca0113_mmio_gpio_set(codec, 5, false);
7829         ca0113_mmio_gpio_set(codec, 7, false);
7830 }
7831
7832 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7833 {
7834         static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7835         unsigned int i;
7836
7837         snd_hda_codec_write(codec, 0x11, 0,
7838                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7839
7840         for (i = 0; i < ARRAY_SIZE(pins); i++)
7841                 snd_hda_codec_write(codec, pins[i], 0,
7842                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7843 }
7844
7845 static void ca0132_clear_unsolicited(struct hda_codec *codec)
7846 {
7847         static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7848         unsigned int i;
7849
7850         for (i = 0; i < ARRAY_SIZE(pins); i++) {
7851                 snd_hda_codec_write(codec, pins[i], 0,
7852                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7853         }
7854 }
7855
7856 /* On shutdown, sends commands in sets of three */
7857 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7858                                                         int mask, int data)
7859 {
7860         if (dir >= 0)
7861                 snd_hda_codec_write(codec, 0x01, 0,
7862                                 AC_VERB_SET_GPIO_DIRECTION, dir);
7863         if (mask >= 0)
7864                 snd_hda_codec_write(codec, 0x01, 0,
7865                                 AC_VERB_SET_GPIO_MASK, mask);
7866
7867         if (data >= 0)
7868                 snd_hda_codec_write(codec, 0x01, 0,
7869                                 AC_VERB_SET_GPIO_DATA, data);
7870 }
7871
7872 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7873 {
7874         static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7875         unsigned int i;
7876
7877         for (i = 0; i < ARRAY_SIZE(pins); i++)
7878                 snd_hda_codec_write(codec, pins[i], 0,
7879                                 AC_VERB_SET_POWER_STATE, 0x03);
7880 }
7881
7882 static void sbz_exit_chip(struct hda_codec *codec)
7883 {
7884         chipio_set_stream_control(codec, 0x03, 0);
7885         chipio_set_stream_control(codec, 0x04, 0);
7886
7887         /* Mess with GPIO */
7888         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7889         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7890         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7891
7892         chipio_set_stream_control(codec, 0x14, 0);
7893         chipio_set_stream_control(codec, 0x0C, 0);
7894
7895         chipio_set_conn_rate(codec, 0x41, SR_192_000);
7896         chipio_set_conn_rate(codec, 0x91, SR_192_000);
7897
7898         chipio_write(codec, 0x18a020, 0x00000083);
7899
7900         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7901         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7902         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7903
7904         chipio_set_stream_control(codec, 0x0C, 0);
7905
7906         chipio_set_control_param(codec, 0x0D, 0x24);
7907
7908         ca0132_clear_unsolicited(codec);
7909         sbz_set_pin_ctl_default(codec);
7910
7911         snd_hda_codec_write(codec, 0x0B, 0,
7912                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7913
7914         sbz_region2_exit(codec);
7915 }
7916
7917 static void r3d_exit_chip(struct hda_codec *codec)
7918 {
7919         ca0132_clear_unsolicited(codec);
7920         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7921         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7922 }
7923
7924 static void ae5_exit_chip(struct hda_codec *codec)
7925 {
7926         chipio_set_stream_control(codec, 0x03, 0);
7927         chipio_set_stream_control(codec, 0x04, 0);
7928
7929         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7930         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7931         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7932         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7933         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7934         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7935         ca0113_mmio_gpio_set(codec, 0, false);
7936         ca0113_mmio_gpio_set(codec, 1, false);
7937
7938         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7939         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7940
7941         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7942
7943         chipio_set_stream_control(codec, 0x18, 0);
7944         chipio_set_stream_control(codec, 0x0c, 0);
7945
7946         snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7947 }
7948
7949 static void zxr_exit_chip(struct hda_codec *codec)
7950 {
7951         chipio_set_stream_control(codec, 0x03, 0);
7952         chipio_set_stream_control(codec, 0x04, 0);
7953         chipio_set_stream_control(codec, 0x14, 0);
7954         chipio_set_stream_control(codec, 0x0C, 0);
7955
7956         chipio_set_conn_rate(codec, 0x41, SR_192_000);
7957         chipio_set_conn_rate(codec, 0x91, SR_192_000);
7958
7959         chipio_write(codec, 0x18a020, 0x00000083);
7960
7961         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7962         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7963
7964         ca0132_clear_unsolicited(codec);
7965         sbz_set_pin_ctl_default(codec);
7966         snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7967
7968         ca0113_mmio_gpio_set(codec, 5, false);
7969         ca0113_mmio_gpio_set(codec, 2, false);
7970         ca0113_mmio_gpio_set(codec, 3, false);
7971         ca0113_mmio_gpio_set(codec, 0, false);
7972         ca0113_mmio_gpio_set(codec, 4, true);
7973         ca0113_mmio_gpio_set(codec, 0, true);
7974         ca0113_mmio_gpio_set(codec, 5, true);
7975         ca0113_mmio_gpio_set(codec, 2, false);
7976         ca0113_mmio_gpio_set(codec, 3, false);
7977 }
7978
7979 static void ca0132_exit_chip(struct hda_codec *codec)
7980 {
7981         /* put any chip cleanup stuffs here. */
7982
7983         if (dspload_is_loaded(codec))
7984                 dsp_reset(codec);
7985 }
7986
7987 /*
7988  * This fixes a problem that was hard to reproduce. Very rarely, I would
7989  * boot up, and there would be no sound, but the DSP indicated it had loaded
7990  * properly. I did a few memory dumps to see if anything was different, and
7991  * there were a few areas of memory uninitialized with a1a2a3a4. This function
7992  * checks if those areas are uninitialized, and if they are, it'll attempt to
7993  * reload the card 3 times. Usually it fixes by the second.
7994  */
7995 static void sbz_dsp_startup_check(struct hda_codec *codec)
7996 {
7997         struct ca0132_spec *spec = codec->spec;
7998         unsigned int dsp_data_check[4];
7999         unsigned int cur_address = 0x390;
8000         unsigned int i;
8001         unsigned int failure = 0;
8002         unsigned int reload = 3;
8003
8004         if (spec->startup_check_entered)
8005                 return;
8006
8007         spec->startup_check_entered = true;
8008
8009         for (i = 0; i < 4; i++) {
8010                 chipio_read(codec, cur_address, &dsp_data_check[i]);
8011                 cur_address += 0x4;
8012         }
8013         for (i = 0; i < 4; i++) {
8014                 if (dsp_data_check[i] == 0xa1a2a3a4)
8015                         failure = 1;
8016         }
8017
8018         codec_dbg(codec, "Startup Check: %d ", failure);
8019         if (failure)
8020                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8021         /*
8022          * While the failure condition is true, and we haven't reached our
8023          * three reload limit, continue trying to reload the driver and
8024          * fix the issue.
8025          */
8026         while (failure && (reload != 0)) {
8027                 codec_info(codec, "Reloading... Tries left: %d", reload);
8028                 sbz_exit_chip(codec);
8029                 spec->dsp_state = DSP_DOWNLOAD_INIT;
8030                 codec->patch_ops.init(codec);
8031                 failure = 0;
8032                 for (i = 0; i < 4; i++) {
8033                         chipio_read(codec, cur_address, &dsp_data_check[i]);
8034                         cur_address += 0x4;
8035                 }
8036                 for (i = 0; i < 4; i++) {
8037                         if (dsp_data_check[i] == 0xa1a2a3a4)
8038                                 failure = 1;
8039                 }
8040                 reload--;
8041         }
8042
8043         if (!failure && reload < 3)
8044                 codec_info(codec, "DSP fixed.");
8045
8046         if (!failure)
8047                 return;
8048
8049         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8050 }
8051
8052 /*
8053  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8054  * extra precision for decibel values. If you had the dB value in floating point
8055  * you would take the value after the decimal point, multiply by 64, and divide
8056  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8057  * implement fixed point or floating point dB volumes. For now, I'll set them
8058  * to 0 just incase a value has lingered from a boot into Windows.
8059  */
8060 static void ca0132_alt_vol_setup(struct hda_codec *codec)
8061 {
8062         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8063         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8064         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8065         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8066         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8067         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8068         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8069         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8070 }
8071
8072 /*
8073  * Extra commands that don't really fit anywhere else.
8074  */
8075 static void sbz_pre_dsp_setup(struct hda_codec *codec)
8076 {
8077         struct ca0132_spec *spec = codec->spec;
8078
8079         writel(0x00820680, spec->mem_base + 0x01C);
8080         writel(0x00820680, spec->mem_base + 0x01C);
8081
8082         chipio_write(codec, 0x18b0a4, 0x000000c2);
8083
8084         snd_hda_codec_write(codec, 0x11, 0,
8085                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8086 }
8087
8088 static void r3d_pre_dsp_setup(struct hda_codec *codec)
8089 {
8090         chipio_write(codec, 0x18b0a4, 0x000000c2);
8091
8092         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8093                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8094         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8095                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8096         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8097                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8098
8099         snd_hda_codec_write(codec, 0x11, 0,
8100                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8101 }
8102
8103 static void r3di_pre_dsp_setup(struct hda_codec *codec)
8104 {
8105         chipio_write(codec, 0x18b0a4, 0x000000c2);
8106
8107         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8108                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8109         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8110                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8111         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8112                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8113
8114         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8115                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8116         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8117                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8118         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8119                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8120         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8121                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8122
8123         snd_hda_codec_write(codec, 0x11, 0,
8124                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8125 }
8126
8127 /*
8128  * These are sent before the DSP is downloaded. Not sure
8129  * what they do, or if they're necessary. Could possibly
8130  * be removed. Figure they're better to leave in.
8131  */
8132 static void ca0132_mmio_init(struct hda_codec *codec)
8133 {
8134         struct ca0132_spec *spec = codec->spec;
8135
8136         if (ca0132_quirk(spec) == QUIRK_AE5)
8137                 writel(0x00000001, spec->mem_base + 0x400);
8138         else
8139                 writel(0x00000000, spec->mem_base + 0x400);
8140
8141         if (ca0132_quirk(spec) == QUIRK_AE5)
8142                 writel(0x00000001, spec->mem_base + 0x408);
8143         else
8144                 writel(0x00000000, spec->mem_base + 0x408);
8145
8146         if (ca0132_quirk(spec) == QUIRK_AE5)
8147                 writel(0x00000001, spec->mem_base + 0x40c);
8148         else
8149                 writel(0x00000000, spec->mem_base + 0x40C);
8150
8151         if (ca0132_quirk(spec) == QUIRK_ZXR)
8152                 writel(0x00880640, spec->mem_base + 0x01C);
8153         else
8154                 writel(0x00880680, spec->mem_base + 0x01C);
8155
8156         if (ca0132_quirk(spec) == QUIRK_AE5)
8157                 writel(0x00000080, spec->mem_base + 0xC0C);
8158         else
8159                 writel(0x00000083, spec->mem_base + 0xC0C);
8160
8161         writel(0x00000030, spec->mem_base + 0xC00);
8162         writel(0x00000000, spec->mem_base + 0xC04);
8163
8164         if (ca0132_quirk(spec) == QUIRK_AE5)
8165                 writel(0x00000000, spec->mem_base + 0xC0C);
8166         else
8167                 writel(0x00000003, spec->mem_base + 0xC0C);
8168
8169         writel(0x00000003, spec->mem_base + 0xC0C);
8170         writel(0x00000003, spec->mem_base + 0xC0C);
8171         writel(0x00000003, spec->mem_base + 0xC0C);
8172
8173         if (ca0132_quirk(spec) == QUIRK_AE5)
8174                 writel(0x00000001, spec->mem_base + 0xC08);
8175         else
8176                 writel(0x000000C1, spec->mem_base + 0xC08);
8177
8178         writel(0x000000F1, spec->mem_base + 0xC08);
8179         writel(0x00000001, spec->mem_base + 0xC08);
8180         writel(0x000000C7, spec->mem_base + 0xC08);
8181         writel(0x000000C1, spec->mem_base + 0xC08);
8182         writel(0x00000080, spec->mem_base + 0xC04);
8183
8184         if (ca0132_quirk(spec) == QUIRK_AE5) {
8185                 writel(0x00000000, spec->mem_base + 0x42c);
8186                 writel(0x00000000, spec->mem_base + 0x46c);
8187                 writel(0x00000000, spec->mem_base + 0x4ac);
8188                 writel(0x00000000, spec->mem_base + 0x4ec);
8189                 writel(0x00000000, spec->mem_base + 0x43c);
8190                 writel(0x00000000, spec->mem_base + 0x47c);
8191                 writel(0x00000000, spec->mem_base + 0x4bc);
8192                 writel(0x00000000, spec->mem_base + 0x4fc);
8193                 writel(0x00000600, spec->mem_base + 0x100);
8194                 writel(0x00000014, spec->mem_base + 0x410);
8195                 writel(0x0000060f, spec->mem_base + 0x100);
8196                 writel(0x0000070f, spec->mem_base + 0x100);
8197                 writel(0x00000aff, spec->mem_base + 0x830);
8198                 writel(0x00000000, spec->mem_base + 0x86c);
8199                 writel(0x0000006b, spec->mem_base + 0x800);
8200                 writel(0x00000001, spec->mem_base + 0x86c);
8201                 writel(0x0000006b, spec->mem_base + 0x800);
8202                 writel(0x00000057, spec->mem_base + 0x804);
8203                 writel(0x00800000, spec->mem_base + 0x20c);
8204         }
8205 }
8206
8207 /*
8208  * This function writes to some SFR's, does some region2 writes, and then
8209  * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8210  * what it does.
8211  */
8212 static void ae5_register_set(struct hda_codec *codec)
8213 {
8214         struct ca0132_spec *spec = codec->spec;
8215
8216         chipio_8051_write_direct(codec, 0x93, 0x10);
8217         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8218                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8219         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8220                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8221
8222         writeb(0x0f, spec->mem_base + 0x304);
8223         writeb(0x0f, spec->mem_base + 0x304);
8224         writeb(0x0f, spec->mem_base + 0x304);
8225         writeb(0x0f, spec->mem_base + 0x304);
8226         writeb(0x0e, spec->mem_base + 0x100);
8227         writeb(0x1f, spec->mem_base + 0x304);
8228         writeb(0x0c, spec->mem_base + 0x100);
8229         writeb(0x3f, spec->mem_base + 0x304);
8230         writeb(0x08, spec->mem_base + 0x100);
8231         writeb(0x7f, spec->mem_base + 0x304);
8232         writeb(0x00, spec->mem_base + 0x100);
8233         writeb(0xff, spec->mem_base + 0x304);
8234
8235         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8236
8237         chipio_8051_write_direct(codec, 0x90, 0x00);
8238         chipio_8051_write_direct(codec, 0x90, 0x10);
8239
8240         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8241
8242         chipio_write(codec, 0x18b0a4, 0x000000c2);
8243
8244         snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8245         snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8246 }
8247
8248 /*
8249  * Extra init functions for alternative ca0132 codecs. Done
8250  * here so they don't clutter up the main ca0132_init function
8251  * anymore than they have to.
8252  */
8253 static void ca0132_alt_init(struct hda_codec *codec)
8254 {
8255         struct ca0132_spec *spec = codec->spec;
8256
8257         ca0132_alt_vol_setup(codec);
8258
8259         switch (ca0132_quirk(spec)) {
8260         case QUIRK_SBZ:
8261                 codec_dbg(codec, "SBZ alt_init");
8262                 ca0132_gpio_init(codec);
8263                 sbz_pre_dsp_setup(codec);
8264                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8265                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8266                 break;
8267         case QUIRK_R3DI:
8268                 codec_dbg(codec, "R3DI alt_init");
8269                 ca0132_gpio_init(codec);
8270                 ca0132_gpio_setup(codec);
8271                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
8272                 r3di_pre_dsp_setup(codec);
8273                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8274                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8275                 break;
8276         case QUIRK_R3D:
8277                 r3d_pre_dsp_setup(codec);
8278                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8279                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8280                 break;
8281         case QUIRK_AE5:
8282                 ca0132_gpio_init(codec);
8283                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8284                                 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8285                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8286                                 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8287                 chipio_write(codec, 0x18b030, 0x00000020);
8288                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8289                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8290                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8291                 break;
8292         case QUIRK_ZXR:
8293                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8294                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8295                 break;
8296         default:
8297                 break;
8298         }
8299 }
8300
8301 static int ca0132_init(struct hda_codec *codec)
8302 {
8303         struct ca0132_spec *spec = codec->spec;
8304         struct auto_pin_cfg *cfg = &spec->autocfg;
8305         int i;
8306         bool dsp_loaded;
8307
8308         /*
8309          * If the DSP is already downloaded, and init has been entered again,
8310          * there's only two reasons for it. One, the codec has awaken from a
8311          * suspended state, and in that case dspload_is_loaded will return
8312          * false, and the init will be ran again. The other reason it gets
8313          * re entered is on startup for some reason it triggers a suspend and
8314          * resume state. In this case, it will check if the DSP is downloaded,
8315          * and not run the init function again. For codecs using alt_functions,
8316          * it will check if the DSP is loaded properly.
8317          */
8318         if (spec->dsp_state == DSP_DOWNLOADED) {
8319                 dsp_loaded = dspload_is_loaded(codec);
8320                 if (!dsp_loaded) {
8321                         spec->dsp_reload = true;
8322                         spec->dsp_state = DSP_DOWNLOAD_INIT;
8323                 } else {
8324                         if (ca0132_quirk(spec) == QUIRK_SBZ)
8325                                 sbz_dsp_startup_check(codec);
8326                         return 0;
8327                 }
8328         }
8329
8330         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8331                 spec->dsp_state = DSP_DOWNLOAD_INIT;
8332         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
8333
8334         if (ca0132_use_pci_mmio(spec))
8335                 ca0132_mmio_init(codec);
8336
8337         snd_hda_power_up_pm(codec);
8338
8339         if (ca0132_quirk(spec) == QUIRK_AE5)
8340                 ae5_register_set(codec);
8341
8342         ca0132_init_unsol(codec);
8343         ca0132_init_params(codec);
8344         ca0132_init_flags(codec);
8345
8346         snd_hda_sequence_write(codec, spec->base_init_verbs);
8347
8348         if (ca0132_use_alt_functions(spec))
8349                 ca0132_alt_init(codec);
8350
8351         ca0132_download_dsp(codec);
8352
8353         ca0132_refresh_widget_caps(codec);
8354
8355         switch (ca0132_quirk(spec)) {
8356         case QUIRK_R3DI:
8357         case QUIRK_R3D:
8358                 r3d_setup_defaults(codec);
8359                 break;
8360         case QUIRK_SBZ:
8361         case QUIRK_ZXR:
8362                 sbz_setup_defaults(codec);
8363                 break;
8364         case QUIRK_AE5:
8365                 ae5_setup_defaults(codec);
8366                 break;
8367         default:
8368                 ca0132_setup_defaults(codec);
8369                 ca0132_init_analog_mic2(codec);
8370                 ca0132_init_dmic(codec);
8371                 break;
8372         }
8373
8374         for (i = 0; i < spec->num_outputs; i++)
8375                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
8376
8377         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8378
8379         for (i = 0; i < spec->num_inputs; i++)
8380                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8381
8382         init_input(codec, cfg->dig_in_pin, spec->dig_in);
8383
8384         if (!ca0132_use_alt_functions(spec)) {
8385                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8386                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8387                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8388                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8389                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8390         }
8391
8392         if (ca0132_quirk(spec) == QUIRK_SBZ)
8393                 ca0132_gpio_setup(codec);
8394
8395         snd_hda_sequence_write(codec, spec->spec_init_verbs);
8396         if (ca0132_use_alt_functions(spec)) {
8397                 ca0132_alt_select_out(codec);
8398                 ca0132_alt_select_in(codec);
8399         } else {
8400                 ca0132_select_out(codec);
8401                 ca0132_select_mic(codec);
8402         }
8403
8404         snd_hda_jack_report_sync(codec);
8405
8406         /*
8407          * Re set the PlayEnhancement switch on a resume event, because the
8408          * controls will not be reloaded.
8409          */
8410         if (spec->dsp_reload) {
8411                 spec->dsp_reload = false;
8412                 ca0132_pe_switch_set(codec);
8413         }
8414
8415         snd_hda_power_down_pm(codec);
8416
8417         return 0;
8418 }
8419
8420 static int dbpro_init(struct hda_codec *codec)
8421 {
8422         struct ca0132_spec *spec = codec->spec;
8423         struct auto_pin_cfg *cfg = &spec->autocfg;
8424         unsigned int i;
8425
8426         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8427         init_input(codec, cfg->dig_in_pin, spec->dig_in);
8428
8429         for (i = 0; i < spec->num_inputs; i++)
8430                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8431
8432         return 0;
8433 }
8434
8435 static void ca0132_free(struct hda_codec *codec)
8436 {
8437         struct ca0132_spec *spec = codec->spec;
8438
8439         cancel_delayed_work_sync(&spec->unsol_hp_work);
8440         snd_hda_power_up(codec);
8441         switch (ca0132_quirk(spec)) {
8442         case QUIRK_SBZ:
8443                 sbz_exit_chip(codec);
8444                 break;
8445         case QUIRK_ZXR:
8446                 zxr_exit_chip(codec);
8447                 break;
8448         case QUIRK_R3D:
8449                 r3d_exit_chip(codec);
8450                 break;
8451         case QUIRK_AE5:
8452                 ae5_exit_chip(codec);
8453                 break;
8454         case QUIRK_R3DI:
8455                 r3di_gpio_shutdown(codec);
8456                 break;
8457         default:
8458                 break;
8459         }
8460
8461         snd_hda_sequence_write(codec, spec->base_exit_verbs);
8462         ca0132_exit_chip(codec);
8463
8464         snd_hda_power_down(codec);
8465 #ifdef CONFIG_PCI
8466         if (spec->mem_base)
8467                 pci_iounmap(codec->bus->pci, spec->mem_base);
8468 #endif
8469         kfree(spec->spec_init_verbs);
8470         kfree(codec->spec);
8471 }
8472
8473 static void dbpro_free(struct hda_codec *codec)
8474 {
8475         struct ca0132_spec *spec = codec->spec;
8476
8477         zxr_dbpro_power_state_shutdown(codec);
8478
8479         kfree(spec->spec_init_verbs);
8480         kfree(codec->spec);
8481 }
8482
8483 static void ca0132_reboot_notify(struct hda_codec *codec)
8484 {
8485         codec->patch_ops.free(codec);
8486 }
8487
8488 #ifdef CONFIG_PM
8489 static int ca0132_suspend(struct hda_codec *codec)
8490 {
8491         struct ca0132_spec *spec = codec->spec;
8492
8493         cancel_delayed_work_sync(&spec->unsol_hp_work);
8494         return 0;
8495 }
8496 #endif
8497
8498 static const struct hda_codec_ops ca0132_patch_ops = {
8499         .build_controls = ca0132_build_controls,
8500         .build_pcms = ca0132_build_pcms,
8501         .init = ca0132_init,
8502         .free = ca0132_free,
8503         .unsol_event = snd_hda_jack_unsol_event,
8504 #ifdef CONFIG_PM
8505         .suspend = ca0132_suspend,
8506 #endif
8507         .reboot_notify = ca0132_reboot_notify,
8508 };
8509
8510 static const struct hda_codec_ops dbpro_patch_ops = {
8511         .build_controls = dbpro_build_controls,
8512         .build_pcms = dbpro_build_pcms,
8513         .init = dbpro_init,
8514         .free = dbpro_free,
8515 };
8516
8517 static void ca0132_config(struct hda_codec *codec)
8518 {
8519         struct ca0132_spec *spec = codec->spec;
8520
8521         spec->dacs[0] = 0x2;
8522         spec->dacs[1] = 0x3;
8523         spec->dacs[2] = 0x4;
8524
8525         spec->multiout.dac_nids = spec->dacs;
8526         spec->multiout.num_dacs = 3;
8527
8528         if (!ca0132_use_alt_functions(spec))
8529                 spec->multiout.max_channels = 2;
8530         else
8531                 spec->multiout.max_channels = 6;
8532
8533         switch (ca0132_quirk(spec)) {
8534         case QUIRK_ALIENWARE:
8535                 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
8536                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
8537                 break;
8538         case QUIRK_SBZ:
8539                 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8540                 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8541                 break;
8542         case QUIRK_ZXR:
8543                 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8544                 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8545                 break;
8546         case QUIRK_R3D:
8547                 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8548                 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8549                 break;
8550         case QUIRK_R3DI:
8551                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8552                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8553                 break;
8554         case QUIRK_AE5:
8555                 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
8556                 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
8557                 break;
8558         default:
8559                 break;
8560         }
8561
8562         switch (ca0132_quirk(spec)) {
8563         case QUIRK_ALIENWARE:
8564                 spec->num_outputs = 2;
8565                 spec->out_pins[0] = 0x0b; /* speaker out */
8566                 spec->out_pins[1] = 0x0f;
8567                 spec->shared_out_nid = 0x2;
8568                 spec->unsol_tag_hp = 0x0f;
8569
8570                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8571                 spec->adcs[1] = 0x8; /* analog mic2 */
8572                 spec->adcs[2] = 0xa; /* what u hear */
8573
8574                 spec->num_inputs = 3;
8575                 spec->input_pins[0] = 0x12;
8576                 spec->input_pins[1] = 0x11;
8577                 spec->input_pins[2] = 0x13;
8578                 spec->shared_mic_nid = 0x7;
8579                 spec->unsol_tag_amic1 = 0x11;
8580                 break;
8581         case QUIRK_SBZ:
8582         case QUIRK_R3D:
8583                 spec->num_outputs = 2;
8584                 spec->out_pins[0] = 0x0B; /* Line out */
8585                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8586                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8587                 spec->out_pins[3] = 0x11; /* Rear surround */
8588                 spec->shared_out_nid = 0x2;
8589                 spec->unsol_tag_hp = spec->out_pins[1];
8590                 spec->unsol_tag_front_hp = spec->out_pins[2];
8591
8592                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8593                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8594                 spec->adcs[2] = 0xa; /* what u hear */
8595
8596                 spec->num_inputs = 2;
8597                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8598                 spec->input_pins[1] = 0x13; /* What U Hear */
8599                 spec->shared_mic_nid = 0x7;
8600                 spec->unsol_tag_amic1 = spec->input_pins[0];
8601
8602                 /* SPDIF I/O */
8603                 spec->dig_out = 0x05;
8604                 spec->multiout.dig_out_nid = spec->dig_out;
8605                 spec->dig_in = 0x09;
8606                 break;
8607         case QUIRK_ZXR:
8608                 spec->num_outputs = 2;
8609                 spec->out_pins[0] = 0x0B; /* Line out */
8610                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8611                 spec->out_pins[2] = 0x10; /* Center/LFE */
8612                 spec->out_pins[3] = 0x11; /* Rear surround */
8613                 spec->shared_out_nid = 0x2;
8614                 spec->unsol_tag_hp = spec->out_pins[1];
8615                 spec->unsol_tag_front_hp = spec->out_pins[2];
8616
8617                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8618                 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8619                 spec->adcs[2] = 0xa; /* what u hear */
8620
8621                 spec->num_inputs = 2;
8622                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8623                 spec->input_pins[1] = 0x13; /* What U Hear */
8624                 spec->shared_mic_nid = 0x7;
8625                 spec->unsol_tag_amic1 = spec->input_pins[0];
8626                 break;
8627         case QUIRK_ZXR_DBPRO:
8628                 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8629
8630                 spec->num_inputs = 1;
8631                 spec->input_pins[0] = 0x11; /* RCA Line-in */
8632
8633                 spec->dig_out = 0x05;
8634                 spec->multiout.dig_out_nid = spec->dig_out;
8635
8636                 spec->dig_in = 0x09;
8637                 break;
8638         case QUIRK_AE5:
8639                 spec->num_outputs = 2;
8640                 spec->out_pins[0] = 0x0B; /* Line out */
8641                 spec->out_pins[1] = 0x11; /* Rear headphone out */
8642                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8643                 spec->out_pins[3] = 0x0F; /* Rear surround */
8644                 spec->shared_out_nid = 0x2;
8645                 spec->unsol_tag_hp = spec->out_pins[1];
8646                 spec->unsol_tag_front_hp = spec->out_pins[2];
8647
8648                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8649                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8650                 spec->adcs[2] = 0xa; /* what u hear */
8651
8652                 spec->num_inputs = 2;
8653                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8654                 spec->input_pins[1] = 0x13; /* What U Hear */
8655                 spec->shared_mic_nid = 0x7;
8656                 spec->unsol_tag_amic1 = spec->input_pins[0];
8657
8658                 /* SPDIF I/O */
8659                 spec->dig_out = 0x05;
8660                 spec->multiout.dig_out_nid = spec->dig_out;
8661                 break;
8662         case QUIRK_R3DI:
8663                 spec->num_outputs = 2;
8664                 spec->out_pins[0] = 0x0B; /* Line out */
8665                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8666                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8667                 spec->out_pins[3] = 0x11; /* Rear surround */
8668                 spec->shared_out_nid = 0x2;
8669                 spec->unsol_tag_hp = spec->out_pins[1];
8670                 spec->unsol_tag_front_hp = spec->out_pins[2];
8671
8672                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8673                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8674                 spec->adcs[2] = 0x0a; /* what u hear */
8675
8676                 spec->num_inputs = 2;
8677                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8678                 spec->input_pins[1] = 0x13; /* What U Hear */
8679                 spec->shared_mic_nid = 0x7;
8680                 spec->unsol_tag_amic1 = spec->input_pins[0];
8681
8682                 /* SPDIF I/O */
8683                 spec->dig_out = 0x05;
8684                 spec->multiout.dig_out_nid = spec->dig_out;
8685                 break;
8686         default:
8687                 spec->num_outputs = 2;
8688                 spec->out_pins[0] = 0x0b; /* speaker out */
8689                 spec->out_pins[1] = 0x10; /* headphone out */
8690                 spec->shared_out_nid = 0x2;
8691                 spec->unsol_tag_hp = spec->out_pins[1];
8692
8693                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8694                 spec->adcs[1] = 0x8; /* analog mic2 */
8695                 spec->adcs[2] = 0xa; /* what u hear */
8696
8697                 spec->num_inputs = 3;
8698                 spec->input_pins[0] = 0x12;
8699                 spec->input_pins[1] = 0x11;
8700                 spec->input_pins[2] = 0x13;
8701                 spec->shared_mic_nid = 0x7;
8702                 spec->unsol_tag_amic1 = spec->input_pins[0];
8703
8704                 /* SPDIF I/O */
8705                 spec->dig_out = 0x05;
8706                 spec->multiout.dig_out_nid = spec->dig_out;
8707                 spec->dig_in = 0x09;
8708                 break;
8709         }
8710 }
8711
8712 static int ca0132_prepare_verbs(struct hda_codec *codec)
8713 {
8714 /* Verbs + terminator (an empty element) */
8715 #define NUM_SPEC_VERBS 2
8716         struct ca0132_spec *spec = codec->spec;
8717
8718         spec->chip_init_verbs = ca0132_init_verbs0;
8719         /*
8720          * Since desktop cards use pci_mmio, this can be used to determine
8721          * whether or not to use these verbs instead of a separate bool.
8722          */
8723         if (ca0132_use_pci_mmio(spec))
8724                 spec->desktop_init_verbs = ca0132_init_verbs1;
8725         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8726                                         sizeof(struct hda_verb),
8727                                         GFP_KERNEL);
8728         if (!spec->spec_init_verbs)
8729                 return -ENOMEM;
8730
8731         /* config EAPD */
8732         spec->spec_init_verbs[0].nid = 0x0b;
8733         spec->spec_init_verbs[0].param = 0x78D;
8734         spec->spec_init_verbs[0].verb = 0x00;
8735
8736         /* Previously commented configuration */
8737         /*
8738         spec->spec_init_verbs[2].nid = 0x0b;
8739         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8740         spec->spec_init_verbs[2].verb = 0x02;
8741
8742         spec->spec_init_verbs[3].nid = 0x10;
8743         spec->spec_init_verbs[3].param = 0x78D;
8744         spec->spec_init_verbs[3].verb = 0x02;
8745
8746         spec->spec_init_verbs[4].nid = 0x10;
8747         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
8748         spec->spec_init_verbs[4].verb = 0x02;
8749         */
8750
8751         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8752         return 0;
8753 }
8754
8755 /*
8756  * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8757  * Sound Blaster Z cards. However, they have different HDA codec subsystem
8758  * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8759  * daughter boards ID.
8760  */
8761 static void sbz_detect_quirk(struct hda_codec *codec)
8762 {
8763         struct ca0132_spec *spec = codec->spec;
8764
8765         switch (codec->core.subsystem_id) {
8766         case 0x11020033:
8767                 spec->quirk = QUIRK_ZXR;
8768                 break;
8769         case 0x1102003f:
8770                 spec->quirk = QUIRK_ZXR_DBPRO;
8771                 break;
8772         default:
8773                 spec->quirk = QUIRK_SBZ;
8774                 break;
8775         }
8776 }
8777
8778 static int patch_ca0132(struct hda_codec *codec)
8779 {
8780         struct ca0132_spec *spec;
8781         int err;
8782         const struct snd_pci_quirk *quirk;
8783
8784         codec_dbg(codec, "patch_ca0132\n");
8785
8786         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8787         if (!spec)
8788                 return -ENOMEM;
8789         codec->spec = spec;
8790         spec->codec = codec;
8791
8792         /* Detect codec quirk */
8793         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8794         if (quirk)
8795                 spec->quirk = quirk->value;
8796         else
8797                 spec->quirk = QUIRK_NONE;
8798         if (ca0132_quirk(spec) == QUIRK_SBZ)
8799                 sbz_detect_quirk(codec);
8800
8801         if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
8802                 codec->patch_ops = dbpro_patch_ops;
8803         else
8804                 codec->patch_ops = ca0132_patch_ops;
8805
8806         codec->pcm_format_first = 1;
8807         codec->no_sticky_stream = 1;
8808
8809
8810         spec->dsp_state = DSP_DOWNLOAD_INIT;
8811         spec->num_mixers = 1;
8812
8813         /* Set which mixers each quirk uses. */
8814         switch (ca0132_quirk(spec)) {
8815         case QUIRK_SBZ:
8816                 spec->mixers[0] = desktop_mixer;
8817                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8818                 break;
8819         case QUIRK_ZXR:
8820                 spec->mixers[0] = desktop_mixer;
8821                 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8822                 break;
8823         case QUIRK_ZXR_DBPRO:
8824                 break;
8825         case QUIRK_R3D:
8826                 spec->mixers[0] = desktop_mixer;
8827                 snd_hda_codec_set_name(codec, "Recon3D");
8828                 break;
8829         case QUIRK_R3DI:
8830                 spec->mixers[0] = r3di_mixer;
8831                 snd_hda_codec_set_name(codec, "Recon3Di");
8832                 break;
8833         case QUIRK_AE5:
8834                 spec->mixers[0] = desktop_mixer;
8835                 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8836                 break;
8837         default:
8838                 spec->mixers[0] = ca0132_mixer;
8839                 break;
8840         }
8841
8842         /* Setup whether or not to use alt functions/controls/pci_mmio */
8843         switch (ca0132_quirk(spec)) {
8844         case QUIRK_SBZ:
8845         case QUIRK_R3D:
8846         case QUIRK_AE5:
8847         case QUIRK_ZXR:
8848                 spec->use_alt_controls = true;
8849                 spec->use_alt_functions = true;
8850                 spec->use_pci_mmio = true;
8851                 break;
8852         case QUIRK_R3DI:
8853                 spec->use_alt_controls = true;
8854                 spec->use_alt_functions = true;
8855                 spec->use_pci_mmio = false;
8856                 break;
8857         default:
8858                 spec->use_alt_controls = false;
8859                 spec->use_alt_functions = false;
8860                 spec->use_pci_mmio = false;
8861                 break;
8862         }
8863
8864 #ifdef CONFIG_PCI
8865         if (spec->use_pci_mmio) {
8866                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8867                 if (spec->mem_base == NULL) {
8868                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8869                         spec->quirk = QUIRK_NONE;
8870                 }
8871         }
8872 #endif
8873
8874         spec->base_init_verbs = ca0132_base_init_verbs;
8875         spec->base_exit_verbs = ca0132_base_exit_verbs;
8876
8877         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8878
8879         ca0132_init_chip(codec);
8880
8881         ca0132_config(codec);
8882
8883         err = ca0132_prepare_verbs(codec);
8884         if (err < 0)
8885                 goto error;
8886
8887         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8888         if (err < 0)
8889                 goto error;
8890
8891         return 0;
8892
8893  error:
8894         ca0132_free(codec);
8895         return err;
8896 }
8897
8898 /*
8899  * patch entries
8900  */
8901 static struct hda_device_id snd_hda_id_ca0132[] = {
8902         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
8903         {} /* terminator */
8904 };
8905 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
8906
8907 MODULE_LICENSE("GPL");
8908 MODULE_DESCRIPTION("Creative Sound Core3D codec");
8909
8910 static struct hda_codec_driver ca0132_driver = {
8911         .id = snd_hda_id_ca0132,
8912 };
8913
8914 module_hda_codec_driver(ca0132_driver);