sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative CA0132 chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/mutex.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/io.h>
  33 #include <linux/pci.h>
  34 #include <asm/io.h>
  35 #include <sound/core.h>
  36 #include "hda_codec.h"
  37 #include "hda_local.h"
  38 #include "hda_auto_parser.h"
  39 #include "hda_jack.h"
  40
  41 #include "ca0132_regs.h"
  42
  43 /* Enable this to see controls for tuning purpose. */
  44 /*#define ENABLE_TUNING_CONTROLS*/
  45
  46 #ifdef ENABLE_TUNING_CONTROLS
  47 #include <sound/tlv.h>
  48 #endif
  49
  50 #define FLOAT_ZERO      0x00000000
  51 #define FLOAT_ONE       0x3f800000
  52 #define FLOAT_TWO       0x40000000
  53 #define FLOAT_THREE     0x40400000
  54 #define FLOAT_EIGHT     0x41000000
  55 #define FLOAT_MINUS_5   0xc0a00000
  56
  57 #define UNSOL_TAG_DSP   0x16
  58
  59 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  60 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  61
  62 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  63 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  64 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  65
  66 #define MASTERCONTROL                           0x80
  67 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  68 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  69
  70 #define WIDGET_CHIP_CTRL      0x15
  71 #define WIDGET_DSP_CTRL       0x16
  72
  73 #define MEM_CONNID_MICIN1     3
  74 #define MEM_CONNID_MICIN2     5
  75 #define MEM_CONNID_MICOUT1    12
  76 #define MEM_CONNID_MICOUT2    14
  77 #define MEM_CONNID_WUH        10
  78 #define MEM_CONNID_DSP        16
  79 #define MEM_CONNID_DMIC       100
  80
  81 #define SCP_SET    0
  82 #define SCP_GET    1
  83
  84 #define EFX_FILE   "/*(DEBLOBBED)*/"
  85 #define SBZ_EFX_FILE   "/*(DEBLOBBED)*/"
  86 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  87
  88 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  89 /*(DEBLOBBED)*/
  90 #endif
  91
  92 static const char *const dirstr[2] = { "Playback", "Capture" };
  93
  94 #define NUM_OF_OUTPUTS 3
  95 enum {
  96         SPEAKER_OUT,
  97         HEADPHONE_OUT,
  98         SURROUND_OUT
  99 };
 100
 101 enum {
 102         DIGITAL_MIC,
 103         LINE_MIC_IN
 104 };
 105
 106 /* Strings for Input Source Enum Control */
 107 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
 108 #define IN_SRC_NUM_OF_INPUTS 3
 109 enum {
 110         REAR_MIC,
 111         REAR_LINE_IN,
 112         FRONT_MIC,
 113 };
 114
 115 enum {
 116 #define VNODE_START_NID    0x80
 117         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 118         VNID_MIC,
 119         VNID_HP_SEL,
 120         VNID_AMIC1_SEL,
 121         VNID_HP_ASEL,
 122         VNID_AMIC1_ASEL,
 123         VNODE_END_NID,
 124 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 125
 126 #define EFFECT_START_NID    0x90
 127 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 128         SURROUND = OUT_EFFECT_START_NID,
 129         CRYSTALIZER,
 130         DIALOG_PLUS,
 131         SMART_VOLUME,
 132         X_BASS,
 133         EQUALIZER,
 134         OUT_EFFECT_END_NID,
 135 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 136
 137 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 138         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 139         VOICE_FOCUS,
 140         MIC_SVM,
 141         NOISE_REDUCTION,
 142         IN_EFFECT_END_NID,
 143 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 144
 145         VOICEFX = IN_EFFECT_END_NID,
 146         PLAY_ENHANCEMENT,
 147         CRYSTAL_VOICE,
 148         EFFECT_END_NID,
 149         OUTPUT_SOURCE_ENUM,
 150         INPUT_SOURCE_ENUM,
 151         XBASS_XOVER,
 152         EQ_PRESET_ENUM,
 153         SMART_VOLUME_ENUM,
 154         MIC_BOOST_ENUM
 155 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 156 };
 157
 158 /* Effects values size*/
 159 #define EFFECT_VALS_MAX_COUNT 12
 160
 161 /*
 162  * Default values for the effect slider controls, they are in order of their
 163  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 164  * X-bass.
 165  */
 166 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 167 /* Amount of effect level sliders for ca0132_alt controls. */
 168 #define EFFECT_LEVEL_SLIDERS 5
 169
 170 /* Latency introduced by DSP blocks in milliseconds. */
 171 #define DSP_CAPTURE_INIT_LATENCY        0
 172 #define DSP_CRYSTAL_VOICE_LATENCY       124
 173 #define DSP_PLAYBACK_INIT_LATENCY       13
 174 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 175 #define DSP_SPEAKER_OUT_LATENCY         7
 176
 177 struct ct_effect {
 178         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 179         hda_nid_t nid;
 180         int mid; /*effect module ID*/
 181         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 182         int direct; /* 0:output; 1:input*/
 183         int params; /* number of default non-on/off params */
 184         /*effect default values, 1st is on/off. */
 185         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 186 };
 187
 188 #define EFX_DIR_OUT 0
 189 #define EFX_DIR_IN  1
 190
 191 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 192         { .name = "Surround",
 193           .nid = SURROUND,
 194           .mid = 0x96,
 195           .reqs = {0, 1},
 196           .direct = EFX_DIR_OUT,
 197           .params = 1,
 198           .def_vals = {0x3F800000, 0x3F2B851F}
 199         },
 200         { .name = "Crystalizer",
 201           .nid = CRYSTALIZER,
 202           .mid = 0x96,
 203           .reqs = {7, 8},
 204           .direct = EFX_DIR_OUT,
 205           .params = 1,
 206           .def_vals = {0x3F800000, 0x3F266666}
 207         },
 208         { .name = "Dialog Plus",
 209           .nid = DIALOG_PLUS,
 210           .mid = 0x96,
 211           .reqs = {2, 3},
 212           .direct = EFX_DIR_OUT,
 213           .params = 1,
 214           .def_vals = {0x00000000, 0x3F000000}
 215         },
 216         { .name = "Smart Volume",
 217           .nid = SMART_VOLUME,
 218           .mid = 0x96,
 219           .reqs = {4, 5, 6},
 220           .direct = EFX_DIR_OUT,
 221           .params = 2,
 222           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 223         },
 224         { .name = "X-Bass",
 225           .nid = X_BASS,
 226           .mid = 0x96,
 227           .reqs = {24, 23, 25},
 228           .direct = EFX_DIR_OUT,
 229           .params = 2,
 230           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 231         },
 232         { .name = "Equalizer",
 233           .nid = EQUALIZER,
 234           .mid = 0x96,
 235           .reqs = {9, 10, 11, 12, 13, 14,
 236                         15, 16, 17, 18, 19, 20},
 237           .direct = EFX_DIR_OUT,
 238           .params = 11,
 239           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 240                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 241                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 242         },
 243         { .name = "Echo Cancellation",
 244           .nid = ECHO_CANCELLATION,
 245           .mid = 0x95,
 246           .reqs = {0, 1, 2, 3},
 247           .direct = EFX_DIR_IN,
 248           .params = 3,
 249           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 250         },
 251         { .name = "Voice Focus",
 252           .nid = VOICE_FOCUS,
 253           .mid = 0x95,
 254           .reqs = {6, 7, 8, 9},
 255           .direct = EFX_DIR_IN,
 256           .params = 3,
 257           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 258         },
 259         { .name = "Mic SVM",
 260           .nid = MIC_SVM,
 261           .mid = 0x95,
 262           .reqs = {44, 45},
 263           .direct = EFX_DIR_IN,
 264           .params = 1,
 265           .def_vals = {0x00000000, 0x3F3D70A4}
 266         },
 267         { .name = "Noise Reduction",
 268           .nid = NOISE_REDUCTION,
 269           .mid = 0x95,
 270           .reqs = {4, 5},
 271           .direct = EFX_DIR_IN,
 272           .params = 1,
 273           .def_vals = {0x3F800000, 0x3F000000}
 274         },
 275         { .name = "VoiceFX",
 276           .nid = VOICEFX,
 277           .mid = 0x95,
 278           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 279           .direct = EFX_DIR_IN,
 280           .params = 8,
 281           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 282                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 283                        0x00000000}
 284         }
 285 };
 286
 287 /* Tuning controls */
 288 #ifdef ENABLE_TUNING_CONTROLS
 289
 290 enum {
 291 #define TUNING_CTL_START_NID  0xC0
 292         WEDGE_ANGLE = TUNING_CTL_START_NID,
 293         SVM_LEVEL,
 294         EQUALIZER_BAND_0,
 295         EQUALIZER_BAND_1,
 296         EQUALIZER_BAND_2,
 297         EQUALIZER_BAND_3,
 298         EQUALIZER_BAND_4,
 299         EQUALIZER_BAND_5,
 300         EQUALIZER_BAND_6,
 301         EQUALIZER_BAND_7,
 302         EQUALIZER_BAND_8,
 303         EQUALIZER_BAND_9,
 304         TUNING_CTL_END_NID
 305 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 306 };
 307
 308 struct ct_tuning_ctl {
 309         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 310         hda_nid_t parent_nid;
 311         hda_nid_t nid;
 312         int mid; /*effect module ID*/
 313         int req; /*effect module request*/
 314         int direct; /* 0:output; 1:input*/
 315         unsigned int def_val;/*effect default values*/
 316 };
 317
 318 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 319         { .name = "Wedge Angle",
 320           .parent_nid = VOICE_FOCUS,
 321           .nid = WEDGE_ANGLE,
 322           .mid = 0x95,
 323           .req = 8,
 324           .direct = EFX_DIR_IN,
 325           .def_val = 0x41F00000
 326         },
 327         { .name = "SVM Level",
 328           .parent_nid = MIC_SVM,
 329           .nid = SVM_LEVEL,
 330           .mid = 0x95,
 331           .req = 45,
 332           .direct = EFX_DIR_IN,
 333           .def_val = 0x3F3D70A4
 334         },
 335         { .name = "EQ Band0",
 336           .parent_nid = EQUALIZER,
 337           .nid = EQUALIZER_BAND_0,
 338           .mid = 0x96,
 339           .req = 11,
 340           .direct = EFX_DIR_OUT,
 341           .def_val = 0x00000000
 342         },
 343         { .name = "EQ Band1",
 344           .parent_nid = EQUALIZER,
 345           .nid = EQUALIZER_BAND_1,
 346           .mid = 0x96,
 347           .req = 12,
 348           .direct = EFX_DIR_OUT,
 349           .def_val = 0x00000000
 350         },
 351         { .name = "EQ Band2",
 352           .parent_nid = EQUALIZER,
 353           .nid = EQUALIZER_BAND_2,
 354           .mid = 0x96,
 355           .req = 13,
 356           .direct = EFX_DIR_OUT,
 357           .def_val = 0x00000000
 358         },
 359         { .name = "EQ Band3",
 360           .parent_nid = EQUALIZER,
 361           .nid = EQUALIZER_BAND_3,
 362           .mid = 0x96,
 363           .req = 14,
 364           .direct = EFX_DIR_OUT,
 365           .def_val = 0x00000000
 366         },
 367         { .name = "EQ Band4",
 368           .parent_nid = EQUALIZER,
 369           .nid = EQUALIZER_BAND_4,
 370           .mid = 0x96,
 371           .req = 15,
 372           .direct = EFX_DIR_OUT,
 373           .def_val = 0x00000000
 374         },
 375         { .name = "EQ Band5",
 376           .parent_nid = EQUALIZER,
 377           .nid = EQUALIZER_BAND_5,
 378           .mid = 0x96,
 379           .req = 16,
 380           .direct = EFX_DIR_OUT,
 381           .def_val = 0x00000000
 382         },
 383         { .name = "EQ Band6",
 384           .parent_nid = EQUALIZER,
 385           .nid = EQUALIZER_BAND_6,
 386           .mid = 0x96,
 387           .req = 17,
 388           .direct = EFX_DIR_OUT,
 389           .def_val = 0x00000000
 390         },
 391         { .name = "EQ Band7",
 392           .parent_nid = EQUALIZER,
 393           .nid = EQUALIZER_BAND_7,
 394           .mid = 0x96,
 395           .req = 18,
 396           .direct = EFX_DIR_OUT,
 397           .def_val = 0x00000000
 398         },
 399         { .name = "EQ Band8",
 400           .parent_nid = EQUALIZER,
 401           .nid = EQUALIZER_BAND_8,
 402           .mid = 0x96,
 403           .req = 19,
 404           .direct = EFX_DIR_OUT,
 405           .def_val = 0x00000000
 406         },
 407         { .name = "EQ Band9",
 408           .parent_nid = EQUALIZER,
 409           .nid = EQUALIZER_BAND_9,
 410           .mid = 0x96,
 411           .req = 20,
 412           .direct = EFX_DIR_OUT,
 413           .def_val = 0x00000000
 414         }
 415 };
 416 #endif
 417
 418 /* Voice FX Presets */
 419 #define VOICEFX_MAX_PARAM_COUNT 9
 420
 421 struct ct_voicefx {
 422         char *name;
 423         hda_nid_t nid;
 424         int mid;
 425         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 426 };
 427
 428 struct ct_voicefx_preset {
 429         char *name; /*preset name*/
 430         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 431 };
 432
 433 static const struct ct_voicefx ca0132_voicefx = {
 434         .name = "VoiceFX Capture Switch",
 435         .nid = VOICEFX,
 436         .mid = 0x95,
 437         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 438 };
 439
 440 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 441         { .name = "Neutral",
 442           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 443                     0x44FA0000, 0x3F800000, 0x3F800000,
 444                     0x3F800000, 0x00000000, 0x00000000 }
 445         },
 446         { .name = "Female2Male",
 447           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 448                     0x44FA0000, 0x3F19999A, 0x3F866666,
 449                     0x3F800000, 0x00000000, 0x00000000 }
 450         },
 451         { .name = "Male2Female",
 452           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 453                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 454                     0x3F800000, 0x00000000, 0x00000000 }
 455         },
 456         { .name = "ScrappyKid",
 457           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 458                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 459                     0x3F800000, 0x00000000, 0x00000000 }
 460         },
 461         { .name = "Elderly",
 462           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 463                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 464                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 465         },
 466         { .name = "Orc",
 467           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 468                     0x45098000, 0x3F266666, 0x3FC00000,
 469                     0x3F800000, 0x00000000, 0x00000000 }
 470         },
 471         { .name = "Elf",
 472           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 473                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 474                     0x3F800000, 0x00000000, 0x00000000 }
 475         },
 476         { .name = "Dwarf",
 477           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 478                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 479                     0x3F800000, 0x00000000, 0x00000000 }
 480         },
 481         { .name = "AlienBrute",
 482           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 483                     0x451F6000, 0x3F266666, 0x3FA7D945,
 484                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 485         },
 486         { .name = "Robot",
 487           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 488                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 489                     0xBC07010E, 0x00000000, 0x00000000 }
 490         },
 491         { .name = "Marine",
 492           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 493                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 494                     0x3F0A3D71, 0x00000000, 0x00000000 }
 495         },
 496         { .name = "Emo",
 497           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 498                     0x44FA0000, 0x3F800000, 0x3F800000,
 499                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 500         },
 501         { .name = "DeepVoice",
 502           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 503                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 504                     0x3F800000, 0x00000000, 0x00000000 }
 505         },
 506         { .name = "Munchkin",
 507           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 508                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 509                     0x3F800000, 0x00000000, 0x00000000 }
 510         }
 511 };
 512
 513 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 514
 515 #define EQ_PRESET_MAX_PARAM_COUNT 11
 516
 517 struct ct_eq {
 518         char *name;
 519         hda_nid_t nid;
 520         int mid;
 521         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 522 };
 523
 524 struct ct_eq_preset {
 525         char *name; /*preset name*/
 526         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 527 };
 528
 529 static const struct ct_eq ca0132_alt_eq_enum = {
 530         .name = "FX: Equalizer Preset Switch",
 531         .nid = EQ_PRESET_ENUM,
 532         .mid = 0x96,
 533         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 534 };
 535
 536
 537 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 538         { .name = "Flat",
 539          .vals = { 0x00000000, 0x00000000, 0x00000000,
 540                    0x00000000, 0x00000000, 0x00000000,
 541                    0x00000000, 0x00000000, 0x00000000,
 542                    0x00000000, 0x00000000            }
 543         },
 544         { .name = "Acoustic",
 545          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 546                    0x40000000, 0x00000000, 0x00000000,
 547                    0x00000000, 0x00000000, 0x40000000,
 548                    0x40000000, 0x40000000            }
 549         },
 550         { .name = "Classical",
 551          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 552                    0x40C00000, 0x40466666, 0x00000000,
 553                    0x00000000, 0x00000000, 0x00000000,
 554                    0x40466666, 0x40466666            }
 555         },
 556         { .name = "Country",
 557          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 558                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 559                    0x00000000, 0x00000000, 0x40000000,
 560                    0x40466666, 0x40800000            }
 561         },
 562         { .name = "Dance",
 563          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 564                    0x40466666, 0x40866666, 0xBF99999A,
 565                    0xBF99999A, 0x00000000, 0x00000000,
 566                    0x40800000, 0x40800000            }
 567         },
 568         { .name = "Jazz",
 569          .vals = { 0x00000000, 0x00000000, 0x00000000,
 570                    0x3F8CCCCD, 0x40800000, 0x40800000,
 571                    0x40800000, 0x00000000, 0x3F8CCCCD,
 572                    0x40466666, 0x40466666            }
 573         },
 574         { .name = "New Age",
 575          .vals = { 0x00000000, 0x00000000, 0x40000000,
 576                    0x40000000, 0x00000000, 0x00000000,
 577                    0x00000000, 0x3F8CCCCD, 0x40000000,
 578                    0x40000000, 0x40000000            }
 579         },
 580         { .name = "Pop",
 581          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 582                    0x40000000, 0x40000000, 0x00000000,
 583                    0xBF99999A, 0xBF99999A, 0x00000000,
 584                    0x40466666, 0x40C00000            }
 585         },
 586         { .name = "Rock",
 587          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 588                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 589                    0xBF99999A, 0x00000000, 0x00000000,
 590                    0x40800000, 0x40800000            }
 591         },
 592         { .name = "Vocal",
 593          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 594                    0xBF99999A, 0x00000000, 0x40466666,
 595                    0x40800000, 0x40466666, 0x00000000,
 596                    0x00000000, 0x3F8CCCCD            }
 597         }
 598 };
 599
 600 /* DSP command sequences for ca0132_alt_select_out */
 601 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
 602 struct ca0132_alt_out_set {
 603         char *name; /*preset name*/
 604         unsigned char commands;
 605         unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
 606         unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
 607         unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
 608 };
 609
 610 static const struct ca0132_alt_out_set alt_out_presets[] = {
 611         { .name = "Line Out",
 612           .commands = 7,
 613           .mids = { 0x96, 0x96, 0x96, 0x8F,
 614                     0x96, 0x96, 0x96 },
 615           .reqs = { 0x19, 0x17, 0x18, 0x01,
 616                     0x1F, 0x15, 0x3A },
 617           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 618                     0x00000000, 0x00000000, 0x00000000,
 619                     0x00000000 }
 620         },
 621         { .name = "Headphone",
 622           .commands = 7,
 623           .mids = { 0x96, 0x96, 0x96, 0x8F,
 624                     0x96, 0x96, 0x96 },
 625           .reqs = { 0x19, 0x17, 0x18, 0x01,
 626                     0x1F, 0x15, 0x3A },
 627           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 628                     0x00000000, 0x00000000, 0x00000000,
 629                     0x00000000 }
 630         },
 631         { .name = "Surround",
 632           .commands = 8,
 633           .mids = { 0x96, 0x8F, 0x96, 0x96,
 634                     0x96, 0x96, 0x96, 0x96 },
 635           .reqs = { 0x18, 0x01, 0x1F, 0x15,
 636                     0x3A, 0x1A, 0x1B, 0x1C },
 637           .vals = { 0x00000000, 0x00000000, 0x00000000,
 638                     0x00000000, 0x00000000, 0x00000000,
 639                     0x00000000, 0x00000000 }
 640         }
 641 };
 642
 643 /*
 644  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 645  * and I don't know what the third req is, but it's always zero. I assume it's
 646  * some sort of update or set command to tell the DSP there's new volume info.
 647  */
 648 #define DSP_VOL_OUT 0
 649 #define DSP_VOL_IN  1
 650
 651 struct ct_dsp_volume_ctl {
 652         hda_nid_t vnid;
 653         int mid; /* module ID*/
 654         unsigned int reqs[3]; /* scp req ID */
 655 };
 656
 657 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 658         { .vnid = VNID_SPK,
 659           .mid = 0x32,
 660           .reqs = {3, 4, 2}
 661         },
 662         { .vnid = VNID_MIC,
 663           .mid = 0x37,
 664           .reqs = {2, 3, 1}
 665         }
 666 };
 667
 668 enum hda_cmd_vendor_io {
 669         /* for DspIO node */
 670         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 671         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 672
 673         VENDOR_DSPIO_STATUS                  = 0xF01,
 674         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 675         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 676         VENDOR_DSPIO_DSP_INIT                = 0x703,
 677         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 678         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 679
 680         /* for ChipIO node */
 681         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 682         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 683         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 684         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 685         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 686
 687         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 688         VENDOR_CHIPIO_STATUS                 = 0xF01,
 689         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 690         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 691
 692         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 693         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 694
 695         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 696         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 697
 698         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 699         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 700         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 701         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 702         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 703         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 704         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 705         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 706
 707         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 708         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 709         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 710         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 711
 712         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 713         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 714         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 715         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 716
 717         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 718         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 719         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 720         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 721         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 722         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 723
 724         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 725 };
 726
 727 /*
 728  *  Control flag IDs
 729  */
 730 enum control_flag_id {
 731         /* Connection manager stream setup is bypassed/enabled */
 732         CONTROL_FLAG_C_MGR                  = 0,
 733         /* DSP DMA is bypassed/enabled */
 734         CONTROL_FLAG_DMA                    = 1,
 735         /* 8051 'idle' mode is disabled/enabled */
 736         CONTROL_FLAG_IDLE_ENABLE            = 2,
 737         /* Tracker for the SPDIF-in path is bypassed/enabled */
 738         CONTROL_FLAG_TRACKER                = 3,
 739         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 740         CONTROL_FLAG_SPDIF2OUT              = 4,
 741         /* Digital Microphone is disabled/enabled */
 742         CONTROL_FLAG_DMIC                   = 5,
 743         /* ADC_B rate is 48 kHz/96 kHz */
 744         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 745         /* ADC_C rate is 48 kHz/96 kHz */
 746         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 747         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 748         CONTROL_FLAG_DAC_96KHZ              = 8,
 749         /* DSP rate is 48 kHz/96 kHz */
 750         CONTROL_FLAG_DSP_96KHZ              = 9,
 751         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 752         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 753         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 754         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 755         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 756         CONTROL_FLAG_DECODE_LOOP            = 12,
 757         /* De-emphasis filter on DAC-1 disabled/enabled */
 758         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 759         /* De-emphasis filter on DAC-2 disabled/enabled */
 760         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 761         /* De-emphasis filter on DAC-3 disabled/enabled */
 762         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 763         /* High-pass filter on ADC_B disabled/enabled */
 764         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 765         /* High-pass filter on ADC_C disabled/enabled */
 766         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 767         /* Common mode on Port_A disabled/enabled */
 768         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 769         /* Common mode on Port_D disabled/enabled */
 770         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 771         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 772         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 773         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 774         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 775         /* ASI rate is 48kHz/96kHz */
 776         CONTROL_FLAG_ASI_96KHZ              = 22,
 777         /* DAC power settings able to control attached ports no/yes */
 778         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 779         /* Clock Stop OK reporting is disabled/enabled */
 780         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 781         /* Number of control flags */
 782         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 783 };
 784
 785 /*
 786  * Control parameter IDs
 787  */
 788 enum control_param_id {
 789         /* 0: None, 1: Mic1In*/
 790         CONTROL_PARAM_VIP_SOURCE               = 1,
 791         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 792         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 793         /* Port A output stage gain setting to use when 16 Ohm output
 794          * impedance is selected*/
 795         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 796         /* Port D output stage gain setting to use when 16 Ohm output
 797          * impedance is selected*/
 798         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 799
 800         /* Stream Control */
 801
 802         /* Select stream with the given ID */
 803         CONTROL_PARAM_STREAM_ID                = 24,
 804         /* Source connection point for the selected stream */
 805         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 806         /* Destination connection point for the selected stream */
 807         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 808         /* Number of audio channels in the selected stream */
 809         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 810         /*Enable control for the selected stream */
 811         CONTROL_PARAM_STREAM_CONTROL           = 28,
 812
 813         /* Connection Point Control */
 814
 815         /* Select connection point with the given ID */
 816         CONTROL_PARAM_CONN_POINT_ID            = 29,
 817         /* Connection point sample rate */
 818         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 819
 820         /* Node Control */
 821
 822         /* Select HDA node with the given ID */
 823         CONTROL_PARAM_NODE_ID                  = 31
 824 };
 825
 826 /*
 827  *  Dsp Io Status codes
 828  */
 829 enum hda_vendor_status_dspio {
 830         /* Success */
 831         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 832         /* Busy, unable to accept new command, the host must retry */
 833         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 834         /* SCP command queue is full */
 835         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 836         /* SCP response queue is empty */
 837         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 838 };
 839
 840 /*
 841  *  Chip Io Status codes
 842  */
 843 enum hda_vendor_status_chipio {
 844         /* Success */
 845         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 846         /* Busy, unable to accept new command, the host must retry */
 847         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 848 };
 849
 850 /*
 851  *  CA0132 sample rate
 852  */
 853 enum ca0132_sample_rate {
 854         SR_6_000        = 0x00,
 855         SR_8_000        = 0x01,
 856         SR_9_600        = 0x02,
 857         SR_11_025       = 0x03,
 858         SR_16_000       = 0x04,
 859         SR_22_050       = 0x05,
 860         SR_24_000       = 0x06,
 861         SR_32_000       = 0x07,
 862         SR_44_100       = 0x08,
 863         SR_48_000       = 0x09,
 864         SR_88_200       = 0x0A,
 865         SR_96_000       = 0x0B,
 866         SR_144_000      = 0x0C,
 867         SR_176_400      = 0x0D,
 868         SR_192_000      = 0x0E,
 869         SR_384_000      = 0x0F,
 870
 871         SR_COUNT        = 0x10,
 872
 873         SR_RATE_UNKNOWN = 0x1F
 874 };
 875
 876 enum dsp_download_state {
 877         DSP_DOWNLOAD_FAILED = -1,
 878         DSP_DOWNLOAD_INIT   = 0,
 879         DSP_DOWNLOADING     = 1,
 880         DSP_DOWNLOADED      = 2
 881 };
 882
 883 /* retrieve parameters from hda format */
 884 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 885 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 886 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 887 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 888
 889 /*
 890  * CA0132 specific
 891  */
 892
 893 struct ca0132_spec {
 894         const struct snd_kcontrol_new *mixers[5];
 895         unsigned int num_mixers;
 896         const struct hda_verb *base_init_verbs;
 897         const struct hda_verb *base_exit_verbs;
 898         const struct hda_verb *chip_init_verbs;
 899         const struct hda_verb *desktop_init_verbs;
 900         struct hda_verb *spec_init_verbs;
 901         struct auto_pin_cfg autocfg;
 902
 903         /* Nodes configurations */
 904         struct hda_multi_out multiout;
 905         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 906         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 907         unsigned int num_outputs;
 908         hda_nid_t input_pins[AUTO_PIN_LAST];
 909         hda_nid_t adcs[AUTO_PIN_LAST];
 910         hda_nid_t dig_out;
 911         hda_nid_t dig_in;
 912         unsigned int num_inputs;
 913         hda_nid_t shared_mic_nid;
 914         hda_nid_t shared_out_nid;
 915         hda_nid_t unsol_tag_hp;
 916         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
 917         hda_nid_t unsol_tag_amic1;
 918
 919         /* chip access */
 920         struct mutex chipio_mutex; /* chip access mutex */
 921         u32 curr_chip_addx;
 922
 923         /* DSP download related */
 924         enum dsp_download_state dsp_state;
 925         unsigned int dsp_stream_id;
 926         unsigned int wait_scp;
 927         unsigned int wait_scp_header;
 928         unsigned int wait_num_data;
 929         unsigned int scp_resp_header;
 930         unsigned int scp_resp_data[4];
 931         unsigned int scp_resp_count;
 932         bool alt_firmware_present;
 933         bool startup_check_entered;
 934         bool dsp_reload;
 935
 936         /* mixer and effects related */
 937         unsigned char dmic_ctl;
 938         int cur_out_type;
 939         int cur_mic_type;
 940         long vnode_lvol[VNODES_COUNT];
 941         long vnode_rvol[VNODES_COUNT];
 942         long vnode_lswitch[VNODES_COUNT];
 943         long vnode_rswitch[VNODES_COUNT];
 944         long effects_switch[EFFECTS_COUNT];
 945         long voicefx_val;
 946         long cur_mic_boost;
 947         /* ca0132_alt control related values */
 948         unsigned char in_enum_val;
 949         unsigned char out_enum_val;
 950         unsigned char mic_boost_enum_val;
 951         unsigned char smart_volume_setting;
 952         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
 953         long xbass_xover_freq;
 954         long eq_preset_val;
 955         unsigned int tlv[4];
 956         struct hda_vmaster_mute_hook vmaster_mute;
 957
 958
 959         struct hda_codec *codec;
 960         struct delayed_work unsol_hp_work;
 961         int quirk;
 962
 963 #ifdef ENABLE_TUNING_CONTROLS
 964         long cur_ctl_vals[TUNING_CTLS_COUNT];
 965 #endif
 966         /*
 967          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
 968          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
 969          * things.
 970          */
 971         bool use_pci_mmio;
 972         void __iomem *mem_base;
 973
 974         /*
 975          * Whether or not to use the alt functions like alt_select_out,
 976          * alt_select_in, etc. Only used on desktop codecs for now, because of
 977          * surround sound support.
 978          */
 979         bool use_alt_functions;
 980
 981         /*
 982          * Whether or not to use alt controls:  volume effect sliders, EQ
 983          * presets, smart volume presets, and new control names with FX prefix.
 984          * Renames PlayEnhancement and CrystalVoice too.
 985          */
 986         bool use_alt_controls;
 987 };
 988
 989 /*
 990  * CA0132 quirks table
 991  */
 992 enum {
 993         QUIRK_NONE,
 994         QUIRK_ALIENWARE,
 995         QUIRK_ALIENWARE_M17XR4,
 996         QUIRK_SBZ,
 997         QUIRK_R3DI,
 998         QUIRK_R3D,
 999 };
1000
1001 static const struct hda_pintbl alienware_pincfgs[] = {
1002         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1003         { 0x0c, 0x411111f0 }, /* N/A */
1004         { 0x0d, 0x411111f0 }, /* N/A */
1005         { 0x0e, 0x411111f0 }, /* N/A */
1006         { 0x0f, 0x0321101f }, /* HP */
1007         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1008         { 0x11, 0x03a11021 }, /* Mic */
1009         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1010         { 0x13, 0x411111f0 }, /* N/A */
1011         { 0x18, 0x411111f0 }, /* N/A */
1012         {}
1013 };
1014
1015 /* Sound Blaster Z pin configs taken from Windows Driver */
1016 static const struct hda_pintbl sbz_pincfgs[] = {
1017         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1018         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1019         { 0x0d, 0x014510f0 }, /* Digital Out */
1020         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1021         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1022         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1023         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1024         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1025         { 0x13, 0x908700f0 }, /* What U Hear In*/
1026         { 0x18, 0x50d000f0 }, /* N/A */
1027         {}
1028 };
1029
1030 /* Recon3D pin configs taken from Windows Driver */
1031 static const struct hda_pintbl r3d_pincfgs[] = {
1032         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1033         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1034         { 0x0d, 0x014510f0 }, /* Digital Out */
1035         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1036         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1037         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1038         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1039         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1040         { 0x13, 0x908700f0 }, /* What U Hear In*/
1041         { 0x18, 0x50d000f0 }, /* N/A */
1042         {}
1043 };
1044
1045 /* Recon3D integrated pin configs taken from Windows Driver */
1046 static const struct hda_pintbl r3di_pincfgs[] = {
1047         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1048         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1049         { 0x0d, 0x014510f0 }, /* Digital Out */
1050         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1051         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1052         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1053         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1054         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1055         { 0x13, 0x908700f0 }, /* What U Hear In*/
1056         { 0x18, 0x500000f0 }, /* N/A */
1057         {}
1058 };
1059
1060 static const struct snd_pci_quirk ca0132_quirks[] = {
1061         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1062         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1063         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1064         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1065         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1066         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1067         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1068         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1069         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1070         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1071         SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1072         SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1073         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1074         {}
1075 };
1076
1077 /*
1078  * CA0132 codec access
1079  */
1080 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1081                 unsigned int verb, unsigned int parm, unsigned int *res)
1082 {
1083         unsigned int response;
1084         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1085         *res = response;
1086
1087         return ((response == -1) ? -1 : 0);
1088 }
1089
1090 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1091                 unsigned short converter_format, unsigned int *res)
1092 {
1093         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1094                                 converter_format & 0xffff, res);
1095 }
1096
1097 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1098                                 hda_nid_t nid, unsigned char stream,
1099                                 unsigned char channel, unsigned int *res)
1100 {
1101         unsigned char converter_stream_channel = 0;
1102
1103         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1104         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1105                                 converter_stream_channel, res);
1106 }
1107
1108 /* Chip access helper function */
1109 static int chipio_send(struct hda_codec *codec,
1110                        unsigned int reg,
1111                        unsigned int data)
1112 {
1113         unsigned int res;
1114         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1115
1116         /* send bits of data specified by reg */
1117         do {
1118                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1119                                          reg, data);
1120                 if (res == VENDOR_STATUS_CHIPIO_OK)
1121                         return 0;
1122                 msleep(20);
1123         } while (time_before(jiffies, timeout));
1124
1125         return -EIO;
1126 }
1127
1128 /*
1129  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1130  */
1131 static int chipio_write_address(struct hda_codec *codec,
1132                                 unsigned int chip_addx)
1133 {
1134         struct ca0132_spec *spec = codec->spec;
1135         int res;
1136
1137         if (spec->curr_chip_addx == chip_addx)
1138                         return 0;
1139
1140         /* send low 16 bits of the address */
1141         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1142                           chip_addx & 0xffff);
1143
1144         if (res != -EIO) {
1145                 /* send high 16 bits of the address */
1146                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1147                                   chip_addx >> 16);
1148         }
1149
1150         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1151
1152         return res;
1153 }
1154
1155 /*
1156  * Write data through the vendor widget -- NOT protected by the Mutex!
1157  */
1158 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1159 {
1160         struct ca0132_spec *spec = codec->spec;
1161         int res;
1162
1163         /* send low 16 bits of the data */
1164         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1165
1166         if (res != -EIO) {
1167                 /* send high 16 bits of the data */
1168                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1169                                   data >> 16);
1170         }
1171
1172         /*If no error encountered, automatically increment the address
1173         as per chip behaviour*/
1174         spec->curr_chip_addx = (res != -EIO) ?
1175                                         (spec->curr_chip_addx + 4) : ~0U;
1176         return res;
1177 }
1178
1179 /*
1180  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1181  */
1182 static int chipio_write_data_multiple(struct hda_codec *codec,
1183                                       const u32 *data,
1184                                       unsigned int count)
1185 {
1186         int status = 0;
1187
1188         if (data == NULL) {
1189                 codec_dbg(codec, "chipio_write_data null ptr\n");
1190                 return -EINVAL;
1191         }
1192
1193         while ((count-- != 0) && (status == 0))
1194                 status = chipio_write_data(codec, *data++);
1195
1196         return status;
1197 }
1198
1199
1200 /*
1201  * Read data through the vendor widget -- NOT protected by the Mutex!
1202  */
1203 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1204 {
1205         struct ca0132_spec *spec = codec->spec;
1206         int res;
1207
1208         /* post read */
1209         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1210
1211         if (res != -EIO) {
1212                 /* read status */
1213                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1214         }
1215
1216         if (res != -EIO) {
1217                 /* read data */
1218                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1219                                            VENDOR_CHIPIO_HIC_READ_DATA,
1220                                            0);
1221         }
1222
1223         /*If no error encountered, automatically increment the address
1224         as per chip behaviour*/
1225         spec->curr_chip_addx = (res != -EIO) ?
1226                                         (spec->curr_chip_addx + 4) : ~0U;
1227         return res;
1228 }
1229
1230 /*
1231  * Write given value to the given address through the chip I/O widget.
1232  * protected by the Mutex
1233  */
1234 static int chipio_write(struct hda_codec *codec,
1235                 unsigned int chip_addx, const unsigned int data)
1236 {
1237         struct ca0132_spec *spec = codec->spec;
1238         int err;
1239
1240         mutex_lock(&spec->chipio_mutex);
1241
1242         /* write the address, and if successful proceed to write data */
1243         err = chipio_write_address(codec, chip_addx);
1244         if (err < 0)
1245                 goto exit;
1246
1247         err = chipio_write_data(codec, data);
1248         if (err < 0)
1249                 goto exit;
1250
1251 exit:
1252         mutex_unlock(&spec->chipio_mutex);
1253         return err;
1254 }
1255
1256 /*
1257  * Write given value to the given address through the chip I/O widget.
1258  * not protected by the Mutex
1259  */
1260 static int chipio_write_no_mutex(struct hda_codec *codec,
1261                 unsigned int chip_addx, const unsigned int data)
1262 {
1263         int err;
1264
1265
1266         /* write the address, and if successful proceed to write data */
1267         err = chipio_write_address(codec, chip_addx);
1268         if (err < 0)
1269                 goto exit;
1270
1271         err = chipio_write_data(codec, data);
1272         if (err < 0)
1273                 goto exit;
1274
1275 exit:
1276         return err;
1277 }
1278
1279 /*
1280  * Write multiple values to the given address through the chip I/O widget.
1281  * protected by the Mutex
1282  */
1283 static int chipio_write_multiple(struct hda_codec *codec,
1284                                  u32 chip_addx,
1285                                  const u32 *data,
1286                                  unsigned int count)
1287 {
1288         struct ca0132_spec *spec = codec->spec;
1289         int status;
1290
1291         mutex_lock(&spec->chipio_mutex);
1292         status = chipio_write_address(codec, chip_addx);
1293         if (status < 0)
1294                 goto error;
1295
1296         status = chipio_write_data_multiple(codec, data, count);
1297 error:
1298         mutex_unlock(&spec->chipio_mutex);
1299
1300         return status;
1301 }
1302
1303 /*
1304  * Read the given address through the chip I/O widget
1305  * protected by the Mutex
1306  */
1307 static int chipio_read(struct hda_codec *codec,
1308                 unsigned int chip_addx, unsigned int *data)
1309 {
1310         struct ca0132_spec *spec = codec->spec;
1311         int err;
1312
1313         mutex_lock(&spec->chipio_mutex);
1314
1315         /* write the address, and if successful proceed to write data */
1316         err = chipio_write_address(codec, chip_addx);
1317         if (err < 0)
1318                 goto exit;
1319
1320         err = chipio_read_data(codec, data);
1321         if (err < 0)
1322                 goto exit;
1323
1324 exit:
1325         mutex_unlock(&spec->chipio_mutex);
1326         return err;
1327 }
1328
1329 /*
1330  * Set chip control flags through the chip I/O widget.
1331  */
1332 static void chipio_set_control_flag(struct hda_codec *codec,
1333                                     enum control_flag_id flag_id,
1334                                     bool flag_state)
1335 {
1336         unsigned int val;
1337         unsigned int flag_bit;
1338
1339         flag_bit = (flag_state ? 1 : 0);
1340         val = (flag_bit << 7) | (flag_id);
1341         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1342                             VENDOR_CHIPIO_FLAG_SET, val);
1343 }
1344
1345 /*
1346  * Set chip parameters through the chip I/O widget.
1347  */
1348 static void chipio_set_control_param(struct hda_codec *codec,
1349                 enum control_param_id param_id, int param_val)
1350 {
1351         struct ca0132_spec *spec = codec->spec;
1352         int val;
1353
1354         if ((param_id < 32) && (param_val < 8)) {
1355                 val = (param_val << 5) | (param_id);
1356                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1357                                     VENDOR_CHIPIO_PARAM_SET, val);
1358         } else {
1359                 mutex_lock(&spec->chipio_mutex);
1360                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1361                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1362                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1363                                             param_id);
1364                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1365                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1366                                             param_val);
1367                 }
1368                 mutex_unlock(&spec->chipio_mutex);
1369         }
1370 }
1371
1372 /*
1373  * Set chip parameters through the chip I/O widget. NO MUTEX.
1374  */
1375 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1376                 enum control_param_id param_id, int param_val)
1377 {
1378         int val;
1379
1380         if ((param_id < 32) && (param_val < 8)) {
1381                 val = (param_val << 5) | (param_id);
1382                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1383                                     VENDOR_CHIPIO_PARAM_SET, val);
1384         } else {
1385                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1386                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1387                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1388                                             param_id);
1389                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1390                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1391                                             param_val);
1392                 }
1393         }
1394 }
1395 /*
1396  * Connect stream to a source point, and then connect
1397  * that source point to a destination point.
1398  */
1399 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1400                                 int streamid, int source_point, int dest_point)
1401 {
1402         chipio_set_control_param_no_mutex(codec,
1403                         CONTROL_PARAM_STREAM_ID, streamid);
1404         chipio_set_control_param_no_mutex(codec,
1405                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1406         chipio_set_control_param_no_mutex(codec,
1407                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1408 }
1409
1410 /*
1411  * Set number of channels in the selected stream.
1412  */
1413 static void chipio_set_stream_channels(struct hda_codec *codec,
1414                                 int streamid, unsigned int channels)
1415 {
1416         chipio_set_control_param_no_mutex(codec,
1417                         CONTROL_PARAM_STREAM_ID, streamid);
1418         chipio_set_control_param_no_mutex(codec,
1419                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1420 }
1421
1422 /*
1423  * Enable/Disable audio stream.
1424  */
1425 static void chipio_set_stream_control(struct hda_codec *codec,
1426                                 int streamid, int enable)
1427 {
1428         chipio_set_control_param_no_mutex(codec,
1429                         CONTROL_PARAM_STREAM_ID, streamid);
1430         chipio_set_control_param_no_mutex(codec,
1431                         CONTROL_PARAM_STREAM_CONTROL, enable);
1432 }
1433
1434
1435 /*
1436  * Set sampling rate of the connection point. NO MUTEX.
1437  */
1438 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1439                                 int connid, enum ca0132_sample_rate rate)
1440 {
1441         chipio_set_control_param_no_mutex(codec,
1442                         CONTROL_PARAM_CONN_POINT_ID, connid);
1443         chipio_set_control_param_no_mutex(codec,
1444                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1445 }
1446
1447 /*
1448  * Set sampling rate of the connection point.
1449  */
1450 static void chipio_set_conn_rate(struct hda_codec *codec,
1451                                 int connid, enum ca0132_sample_rate rate)
1452 {
1453         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1454         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1455                                  rate);
1456 }
1457
1458 /*
1459  * Enable clocks.
1460  */
1461 static void chipio_enable_clocks(struct hda_codec *codec)
1462 {
1463         struct ca0132_spec *spec = codec->spec;
1464
1465         mutex_lock(&spec->chipio_mutex);
1466         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1468         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1470         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1471                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1472         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1474         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1476         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1477                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1478         mutex_unlock(&spec->chipio_mutex);
1479 }
1480
1481 /*
1482  * CA0132 DSP IO stuffs
1483  */
1484 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1485                       unsigned int data)
1486 {
1487         int res;
1488         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1489
1490         /* send bits of data specified by reg to dsp */
1491         do {
1492                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1493                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1494                         return res;
1495                 msleep(20);
1496         } while (time_before(jiffies, timeout));
1497
1498         return -EIO;
1499 }
1500
1501 /*
1502  * Wait for DSP to be ready for commands
1503  */
1504 static void dspio_write_wait(struct hda_codec *codec)
1505 {
1506         int status;
1507         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1508
1509         do {
1510                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1511                                                 VENDOR_DSPIO_STATUS, 0);
1512                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1513                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1514                         break;
1515                 msleep(1);
1516         } while (time_before(jiffies, timeout));
1517 }
1518
1519 /*
1520  * Write SCP data to DSP
1521  */
1522 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1523 {
1524         struct ca0132_spec *spec = codec->spec;
1525         int status;
1526
1527         dspio_write_wait(codec);
1528
1529         mutex_lock(&spec->chipio_mutex);
1530         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1531                             scp_data & 0xffff);
1532         if (status < 0)
1533                 goto error;
1534
1535         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1536                                     scp_data >> 16);
1537         if (status < 0)
1538                 goto error;
1539
1540         /* OK, now check if the write itself has executed*/
1541         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1542                                     VENDOR_DSPIO_STATUS, 0);
1543 error:
1544         mutex_unlock(&spec->chipio_mutex);
1545
1546         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1547                         -EIO : 0;
1548 }
1549
1550 /*
1551  * Write multiple SCP data to DSP
1552  */
1553 static int dspio_write_multiple(struct hda_codec *codec,
1554                                 unsigned int *buffer, unsigned int size)
1555 {
1556         int status = 0;
1557         unsigned int count;
1558
1559         if (buffer == NULL)
1560                 return -EINVAL;
1561
1562         count = 0;
1563         while (count < size) {
1564                 status = dspio_write(codec, *buffer++);
1565                 if (status != 0)
1566                         break;
1567                 count++;
1568         }
1569
1570         return status;
1571 }
1572
1573 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1574 {
1575         int status;
1576
1577         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1578         if (status == -EIO)
1579                 return status;
1580
1581         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1582         if (status == -EIO ||
1583             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1584                 return -EIO;
1585
1586         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1587                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1588
1589         return 0;
1590 }
1591
1592 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1593                                unsigned int *buf_size, unsigned int size_count)
1594 {
1595         int status = 0;
1596         unsigned int size = *buf_size;
1597         unsigned int count;
1598         unsigned int skip_count;
1599         unsigned int dummy;
1600
1601         if (buffer == NULL)
1602                 return -1;
1603
1604         count = 0;
1605         while (count < size && count < size_count) {
1606                 status = dspio_read(codec, buffer++);
1607                 if (status != 0)
1608                         break;
1609                 count++;
1610         }
1611
1612         skip_count = count;
1613         if (status == 0) {
1614                 while (skip_count < size) {
1615                         status = dspio_read(codec, &dummy);
1616                         if (status != 0)
1617                                 break;
1618                         skip_count++;
1619                 }
1620         }
1621         *buf_size = count;
1622
1623         return status;
1624 }
1625
1626 /*
1627  * Construct the SCP header using corresponding fields
1628  */
1629 static inline unsigned int
1630 make_scp_header(unsigned int target_id, unsigned int source_id,
1631                 unsigned int get_flag, unsigned int req,
1632                 unsigned int device_flag, unsigned int resp_flag,
1633                 unsigned int error_flag, unsigned int data_size)
1634 {
1635         unsigned int header = 0;
1636
1637         header = (data_size & 0x1f) << 27;
1638         header |= (error_flag & 0x01) << 26;
1639         header |= (resp_flag & 0x01) << 25;
1640         header |= (device_flag & 0x01) << 24;
1641         header |= (req & 0x7f) << 17;
1642         header |= (get_flag & 0x01) << 16;
1643         header |= (source_id & 0xff) << 8;
1644         header |= target_id & 0xff;
1645
1646         return header;
1647 }
1648
1649 /*
1650  * Extract corresponding fields from SCP header
1651  */
1652 static inline void
1653 extract_scp_header(unsigned int header,
1654                    unsigned int *target_id, unsigned int *source_id,
1655                    unsigned int *get_flag, unsigned int *req,
1656                    unsigned int *device_flag, unsigned int *resp_flag,
1657                    unsigned int *error_flag, unsigned int *data_size)
1658 {
1659         if (data_size)
1660                 *data_size = (header >> 27) & 0x1f;
1661         if (error_flag)
1662                 *error_flag = (header >> 26) & 0x01;
1663         if (resp_flag)
1664                 *resp_flag = (header >> 25) & 0x01;
1665         if (device_flag)
1666                 *device_flag = (header >> 24) & 0x01;
1667         if (req)
1668                 *req = (header >> 17) & 0x7f;
1669         if (get_flag)
1670                 *get_flag = (header >> 16) & 0x01;
1671         if (source_id)
1672                 *source_id = (header >> 8) & 0xff;
1673         if (target_id)
1674                 *target_id = header & 0xff;
1675 }
1676
1677 #define SCP_MAX_DATA_WORDS  (16)
1678
1679 /* Structure to contain any SCP message */
1680 struct scp_msg {
1681         unsigned int hdr;
1682         unsigned int data[SCP_MAX_DATA_WORDS];
1683 };
1684
1685 static void dspio_clear_response_queue(struct hda_codec *codec)
1686 {
1687         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1688         unsigned int dummy = 0;
1689         int status;
1690
1691         /* clear all from the response queue */
1692         do {
1693                 status = dspio_read(codec, &dummy);
1694         } while (status == 0 && time_before(jiffies, timeout));
1695 }
1696
1697 static int dspio_get_response_data(struct hda_codec *codec)
1698 {
1699         struct ca0132_spec *spec = codec->spec;
1700         unsigned int data = 0;
1701         unsigned int count;
1702
1703         if (dspio_read(codec, &data) < 0)
1704                 return -EIO;
1705
1706         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1707                 spec->scp_resp_header = data;
1708                 spec->scp_resp_count = data >> 27;
1709                 count = spec->wait_num_data;
1710                 dspio_read_multiple(codec, spec->scp_resp_data,
1711                                     &spec->scp_resp_count, count);
1712                 return 0;
1713         }
1714
1715         return -EIO;
1716 }
1717
1718 /*
1719  * Send SCP message to DSP
1720  */
1721 static int dspio_send_scp_message(struct hda_codec *codec,
1722                                   unsigned char *send_buf,
1723                                   unsigned int send_buf_size,
1724                                   unsigned char *return_buf,
1725                                   unsigned int return_buf_size,
1726                                   unsigned int *bytes_returned)
1727 {
1728         struct ca0132_spec *spec = codec->spec;
1729         int status = -1;
1730         unsigned int scp_send_size = 0;
1731         unsigned int total_size;
1732         bool waiting_for_resp = false;
1733         unsigned int header;
1734         struct scp_msg *ret_msg;
1735         unsigned int resp_src_id, resp_target_id;
1736         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1737
1738         if (bytes_returned)
1739                 *bytes_returned = 0;
1740
1741         /* get scp header from buffer */
1742         header = *((unsigned int *)send_buf);
1743         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1744                            &device_flag, NULL, NULL, &data_size);
1745         scp_send_size = data_size + 1;
1746         total_size = (scp_send_size * 4);
1747
1748         if (send_buf_size < total_size)
1749                 return -EINVAL;
1750
1751         if (get_flag || device_flag) {
1752                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1753                         return -EINVAL;
1754
1755                 spec->wait_scp_header = *((unsigned int *)send_buf);
1756
1757                 /* swap source id with target id */
1758                 resp_target_id = src_id;
1759                 resp_src_id = target_id;
1760                 spec->wait_scp_header &= 0xffff0000;
1761                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1762                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1763                 spec->wait_scp = 1;
1764                 waiting_for_resp = true;
1765         }
1766
1767         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1768                                       scp_send_size);
1769         if (status < 0) {
1770                 spec->wait_scp = 0;
1771                 return status;
1772         }
1773
1774         if (waiting_for_resp) {
1775                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1776                 memset(return_buf, 0, return_buf_size);
1777                 do {
1778                         msleep(20);
1779                 } while (spec->wait_scp && time_before(jiffies, timeout));
1780                 waiting_for_resp = false;
1781                 if (!spec->wait_scp) {
1782                         ret_msg = (struct scp_msg *)return_buf;
1783                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1784                         memcpy(&ret_msg->data, spec->scp_resp_data,
1785                                spec->wait_num_data);
1786                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1787                         status = 0;
1788                 } else {
1789                         status = -EIO;
1790                 }
1791                 spec->wait_scp = 0;
1792         }
1793
1794         return status;
1795 }
1796
1797 /**
1798  * Prepare and send the SCP message to DSP
1799  * @codec: the HDA codec
1800  * @mod_id: ID of the DSP module to send the command
1801  * @req: ID of request to send to the DSP module
1802  * @dir: SET or GET
1803  * @data: pointer to the data to send with the request, request specific
1804  * @len: length of the data, in bytes
1805  * @reply: point to the buffer to hold data returned for a reply
1806  * @reply_len: length of the reply buffer returned from GET
1807  *
1808  * Returns zero or a negative error code.
1809  */
1810 static int dspio_scp(struct hda_codec *codec,
1811                 int mod_id, int src_id, int req, int dir, const void *data,
1812                 unsigned int len, void *reply, unsigned int *reply_len)
1813 {
1814         int status = 0;
1815         struct scp_msg scp_send, scp_reply;
1816         unsigned int ret_bytes, send_size, ret_size;
1817         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1818         unsigned int reply_data_size;
1819
1820         memset(&scp_send, 0, sizeof(scp_send));
1821         memset(&scp_reply, 0, sizeof(scp_reply));
1822
1823         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1824                 return -EINVAL;
1825
1826         if (dir == SCP_GET && reply == NULL) {
1827                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1828                 return -EINVAL;
1829         }
1830
1831         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1832                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1833                 return -EINVAL;
1834         }
1835
1836         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1837                                        0, 0, 0, len/sizeof(unsigned int));
1838         if (data != NULL && len > 0) {
1839                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1840                 memcpy(scp_send.data, data, len);
1841         }
1842
1843         ret_bytes = 0;
1844         send_size = sizeof(unsigned int) + len;
1845         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1846                                         send_size, (unsigned char *)&scp_reply,
1847                                         sizeof(scp_reply), &ret_bytes);
1848
1849         if (status < 0) {
1850                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1851                 return status;
1852         }
1853
1854         /* extract send and reply headers members */
1855         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1856                            NULL, NULL, NULL, NULL, NULL);
1857         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1858                            &reply_resp_flag, &reply_error_flag,
1859                            &reply_data_size);
1860
1861         if (!send_get_flag)
1862                 return 0;
1863
1864         if (reply_resp_flag && !reply_error_flag) {
1865                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1866                                         / sizeof(unsigned int);
1867
1868                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1869                         codec_dbg(codec, "reply too long for buf\n");
1870                         return -EINVAL;
1871                 } else if (ret_size != reply_data_size) {
1872                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1873                         return -EINVAL;
1874                 } else if (!reply) {
1875                         codec_dbg(codec, "NULL reply\n");
1876                         return -EINVAL;
1877                 } else {
1878                         *reply_len = ret_size*sizeof(unsigned int);
1879                         memcpy(reply, scp_reply.data, *reply_len);
1880                 }
1881         } else {
1882                 codec_dbg(codec, "reply ill-formed or errflag set\n");
1883                 return -EIO;
1884         }
1885
1886         return status;
1887 }
1888
1889 /*
1890  * Set DSP parameters
1891  */
1892 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1893                         int src_id, int req, const void *data, unsigned int len)
1894 {
1895         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1896                         NULL);
1897 }
1898
1899 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1900                         int req, const unsigned int data)
1901 {
1902         return dspio_set_param(codec, mod_id, 0x20, req, &data,
1903                         sizeof(unsigned int));
1904 }
1905
1906 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1907                         int req, const unsigned int data)
1908 {
1909         return dspio_set_param(codec, mod_id, 0x00, req, &data,
1910                         sizeof(unsigned int));
1911 }
1912
1913 /*
1914  * Allocate a DSP DMA channel via an SCP message
1915  */
1916 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1917 {
1918         int status = 0;
1919         unsigned int size = sizeof(*dma_chan);
1920
1921         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1922         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1923                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1924                         dma_chan, &size);
1925
1926         if (status < 0) {
1927                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1928                 return status;
1929         }
1930
1931         if ((*dma_chan + 1) == 0) {
1932                 codec_dbg(codec, "no free dma channels to allocate\n");
1933                 return -EBUSY;
1934         }
1935
1936         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1937         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1938
1939         return status;
1940 }
1941
1942 /*
1943  * Free a DSP DMA via an SCP message
1944  */
1945 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1946 {
1947         int status = 0;
1948         unsigned int dummy = 0;
1949
1950         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1951         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1952
1953         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1954                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1955                         sizeof(dma_chan), NULL, &dummy);
1956
1957         if (status < 0) {
1958                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1959                 return status;
1960         }
1961
1962         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1963
1964         return status;
1965 }
1966
1967 /*
1968  * (Re)start the DSP
1969  */
1970 static int dsp_set_run_state(struct hda_codec *codec)
1971 {
1972         unsigned int dbg_ctrl_reg;
1973         unsigned int halt_state;
1974         int err;
1975
1976         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1977         if (err < 0)
1978                 return err;
1979
1980         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1981                       DSP_DBGCNTL_STATE_LOBIT;
1982
1983         if (halt_state != 0) {
1984                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1985                                   DSP_DBGCNTL_SS_MASK);
1986                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1987                                    dbg_ctrl_reg);
1988                 if (err < 0)
1989                         return err;
1990
1991                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1992                                 DSP_DBGCNTL_EXEC_MASK;
1993                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1994                                    dbg_ctrl_reg);
1995                 if (err < 0)
1996                         return err;
1997         }
1998
1999         return 0;
2000 }
2001
2002 /*
2003  * Reset the DSP
2004  */
2005 static int dsp_reset(struct hda_codec *codec)
2006 {
2007         unsigned int res;
2008         int retry = 20;
2009
2010         codec_dbg(codec, "dsp_reset\n");
2011         do {
2012                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2013                 retry--;
2014         } while (res == -EIO && retry);
2015
2016         if (!retry) {
2017                 codec_dbg(codec, "dsp_reset timeout\n");
2018                 return -EIO;
2019         }
2020
2021         return 0;
2022 }
2023
2024 /*
2025  * Convert chip address to DSP address
2026  */
2027 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2028                                         bool *code, bool *yram)
2029 {
2030         *code = *yram = false;
2031
2032         if (UC_RANGE(chip_addx, 1)) {
2033                 *code = true;
2034                 return UC_OFF(chip_addx);
2035         } else if (X_RANGE_ALL(chip_addx, 1)) {
2036                 return X_OFF(chip_addx);
2037         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2038                 *yram = true;
2039                 return Y_OFF(chip_addx);
2040         }
2041
2042         return INVALID_CHIP_ADDRESS;
2043 }
2044
2045 /*
2046  * Check if the DSP DMA is active
2047  */
2048 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2049 {
2050         unsigned int dma_chnlstart_reg;
2051
2052         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2053
2054         return ((dma_chnlstart_reg & (1 <<
2055                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2056 }
2057
2058 static int dsp_dma_setup_common(struct hda_codec *codec,
2059                                 unsigned int chip_addx,
2060                                 unsigned int dma_chan,
2061                                 unsigned int port_map_mask,
2062                                 bool ovly)
2063 {
2064         int status = 0;
2065         unsigned int chnl_prop;
2066         unsigned int dsp_addx;
2067         unsigned int active;
2068         bool code, yram;
2069
2070         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2071
2072         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2073                 codec_dbg(codec, "dma chan num invalid\n");
2074                 return -EINVAL;
2075         }
2076
2077         if (dsp_is_dma_active(codec, dma_chan)) {
2078                 codec_dbg(codec, "dma already active\n");
2079                 return -EBUSY;
2080         }
2081
2082         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2083
2084         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2085                 codec_dbg(codec, "invalid chip addr\n");
2086                 return -ENXIO;
2087         }
2088
2089         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2090         active = 0;
2091
2092         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2093
2094         if (ovly) {
2095                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2096                                      &chnl_prop);
2097
2098                 if (status < 0) {
2099                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2100                         return status;
2101                 }
2102                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2103         }
2104
2105         if (!code)
2106                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2107         else
2108                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2109
2110         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2111
2112         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2113         if (status < 0) {
2114                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2115                 return status;
2116         }
2117         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2118
2119         if (ovly) {
2120                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2121                                      &active);
2122
2123                 if (status < 0) {
2124                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2125                         return status;
2126                 }
2127                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2128         }
2129
2130         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2131                 DSPDMAC_ACTIVE_AAR_MASK;
2132
2133         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2134         if (status < 0) {
2135                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2136                 return status;
2137         }
2138
2139         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2140
2141         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2142                               port_map_mask);
2143         if (status < 0) {
2144                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2145                 return status;
2146         }
2147         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2148
2149         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2150                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2151         if (status < 0) {
2152                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2153                 return status;
2154         }
2155         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2156
2157         codec_dbg(codec,
2158                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2159                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2160                    chip_addx, dsp_addx, dma_chan,
2161                    port_map_mask, chnl_prop, active);
2162
2163         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2164
2165         return 0;
2166 }
2167
2168 /*
2169  * Setup the DSP DMA per-transfer-specific registers
2170  */
2171 static int dsp_dma_setup(struct hda_codec *codec,
2172                         unsigned int chip_addx,
2173                         unsigned int count,
2174                         unsigned int dma_chan)
2175 {
2176         int status = 0;
2177         bool code, yram;
2178         unsigned int dsp_addx;
2179         unsigned int addr_field;
2180         unsigned int incr_field;
2181         unsigned int base_cnt;
2182         unsigned int cur_cnt;
2183         unsigned int dma_cfg = 0;
2184         unsigned int adr_ofs = 0;
2185         unsigned int xfr_cnt = 0;
2186         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2187                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2188
2189         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2190
2191         if (count > max_dma_count) {
2192                 codec_dbg(codec, "count too big\n");
2193                 return -EINVAL;
2194         }
2195
2196         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2197         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2198                 codec_dbg(codec, "invalid chip addr\n");
2199                 return -ENXIO;
2200         }
2201
2202         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2203
2204         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2205         incr_field   = 0;
2206
2207         if (!code) {
2208                 addr_field <<= 1;
2209                 if (yram)
2210                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2211
2212                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2213         }
2214
2215         dma_cfg = addr_field + incr_field;
2216         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2217                                 dma_cfg);
2218         if (status < 0) {
2219                 codec_dbg(codec, "write DMACFG Reg fail\n");
2220                 return status;
2221         }
2222         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2223
2224         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2225                                                         (code ? 0 : 1));
2226
2227         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2228                                 adr_ofs);
2229         if (status < 0) {
2230                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2231                 return status;
2232         }
2233         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2234
2235         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2236
2237         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2238
2239         xfr_cnt = base_cnt | cur_cnt;
2240
2241         status = chipio_write(codec,
2242                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2243         if (status < 0) {
2244                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2245                 return status;
2246         }
2247         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2248
2249         codec_dbg(codec,
2250                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2251                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2252                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2253
2254         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2255
2256         return 0;
2257 }
2258
2259 /*
2260  * Start the DSP DMA
2261  */
2262 static int dsp_dma_start(struct hda_codec *codec,
2263                          unsigned int dma_chan, bool ovly)
2264 {
2265         unsigned int reg = 0;
2266         int status = 0;
2267
2268         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2269
2270         if (ovly) {
2271                 status = chipio_read(codec,
2272                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2273
2274                 if (status < 0) {
2275                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2276                         return status;
2277                 }
2278                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2279
2280                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2281                                 DSPDMAC_CHNLSTART_DIS_MASK);
2282         }
2283
2284         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2285                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2286         if (status < 0) {
2287                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2288                 return status;
2289         }
2290         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2291
2292         return status;
2293 }
2294
2295 /*
2296  * Stop the DSP DMA
2297  */
2298 static int dsp_dma_stop(struct hda_codec *codec,
2299                         unsigned int dma_chan, bool ovly)
2300 {
2301         unsigned int reg = 0;
2302         int status = 0;
2303
2304         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2305
2306         if (ovly) {
2307                 status = chipio_read(codec,
2308                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2309
2310                 if (status < 0) {
2311                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2312                         return status;
2313                 }
2314                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2315                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2316                                 DSPDMAC_CHNLSTART_DIS_MASK);
2317         }
2318
2319         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2320                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2321         if (status < 0) {
2322                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2323                 return status;
2324         }
2325         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2326
2327         return status;
2328 }
2329
2330 /**
2331  * Allocate router ports
2332  *
2333  * @codec: the HDA codec
2334  * @num_chans: number of channels in the stream
2335  * @ports_per_channel: number of ports per channel
2336  * @start_device: start device
2337  * @port_map: pointer to the port list to hold the allocated ports
2338  *
2339  * Returns zero or a negative error code.
2340  */
2341 static int dsp_allocate_router_ports(struct hda_codec *codec,
2342                                      unsigned int num_chans,
2343                                      unsigned int ports_per_channel,
2344                                      unsigned int start_device,
2345                                      unsigned int *port_map)
2346 {
2347         int status = 0;
2348         int res;
2349         u8 val;
2350
2351         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2352         if (status < 0)
2353                 return status;
2354
2355         val = start_device << 6;
2356         val |= (ports_per_channel - 1) << 4;
2357         val |= num_chans - 1;
2358
2359         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2360                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2361                             val);
2362
2363         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2364                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2365                             MEM_CONNID_DSP);
2366
2367         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2368         if (status < 0)
2369                 return status;
2370
2371         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2372                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2373
2374         *port_map = res;
2375
2376         return (res < 0) ? res : 0;
2377 }
2378
2379 /*
2380  * Free router ports
2381  */
2382 static int dsp_free_router_ports(struct hda_codec *codec)
2383 {
2384         int status = 0;
2385
2386         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2387         if (status < 0)
2388                 return status;
2389
2390         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2391                             VENDOR_CHIPIO_PORT_FREE_SET,
2392                             MEM_CONNID_DSP);
2393
2394         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2395
2396         return status;
2397 }
2398
2399 /*
2400  * Allocate DSP ports for the download stream
2401  */
2402 static int dsp_allocate_ports(struct hda_codec *codec,
2403                         unsigned int num_chans,
2404                         unsigned int rate_multi, unsigned int *port_map)
2405 {
2406         int status;
2407
2408         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2409
2410         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2411                 codec_dbg(codec, "bad rate multiple\n");
2412                 return -EINVAL;
2413         }
2414
2415         status = dsp_allocate_router_ports(codec, num_chans,
2416                                            rate_multi, 0, port_map);
2417
2418         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2419
2420         return status;
2421 }
2422
2423 static int dsp_allocate_ports_format(struct hda_codec *codec,
2424                         const unsigned short fmt,
2425                         unsigned int *port_map)
2426 {
2427         int status;
2428         unsigned int num_chans;
2429
2430         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2431         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2432         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2433
2434         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2435                 codec_dbg(codec, "bad rate multiple\n");
2436                 return -EINVAL;
2437         }
2438
2439         num_chans = get_hdafmt_chs(fmt) + 1;
2440
2441         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2442
2443         return status;
2444 }
2445
2446 /*
2447  * free DSP ports
2448  */
2449 static int dsp_free_ports(struct hda_codec *codec)
2450 {
2451         int status;
2452
2453         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2454
2455         status = dsp_free_router_ports(codec);
2456         if (status < 0) {
2457                 codec_dbg(codec, "free router ports fail\n");
2458                 return status;
2459         }
2460         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2461
2462         return status;
2463 }
2464
2465 /*
2466  *  HDA DMA engine stuffs for DSP code download
2467  */
2468 struct dma_engine {
2469         struct hda_codec *codec;
2470         unsigned short m_converter_format;
2471         struct snd_dma_buffer *dmab;
2472         unsigned int buf_size;
2473 };
2474
2475
2476 enum dma_state {
2477         DMA_STATE_STOP  = 0,
2478         DMA_STATE_RUN   = 1
2479 };
2480
2481 static int dma_convert_to_hda_format(struct hda_codec *codec,
2482                 unsigned int sample_rate,
2483                 unsigned short channels,
2484                 unsigned short *hda_format)
2485 {
2486         unsigned int format_val;
2487
2488         format_val = snd_hdac_calc_stream_format(sample_rate,
2489                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2490
2491         if (hda_format)
2492                 *hda_format = (unsigned short)format_val;
2493
2494         return 0;
2495 }
2496
2497 /*
2498  *  Reset DMA for DSP download
2499  */
2500 static int dma_reset(struct dma_engine *dma)
2501 {
2502         struct hda_codec *codec = dma->codec;
2503         struct ca0132_spec *spec = codec->spec;
2504         int status;
2505
2506         if (dma->dmab->area)
2507                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2508
2509         status = snd_hda_codec_load_dsp_prepare(codec,
2510                         dma->m_converter_format,
2511                         dma->buf_size,
2512                         dma->dmab);
2513         if (status < 0)
2514                 return status;
2515         spec->dsp_stream_id = status;
2516         return 0;
2517 }
2518
2519 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2520 {
2521         bool cmd;
2522
2523         switch (state) {
2524         case DMA_STATE_STOP:
2525                 cmd = false;
2526                 break;
2527         case DMA_STATE_RUN:
2528                 cmd = true;
2529                 break;
2530         default:
2531                 return 0;
2532         }
2533
2534         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2535         return 0;
2536 }
2537
2538 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2539 {
2540         return dma->dmab->bytes;
2541 }
2542
2543 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2544 {
2545         return dma->dmab->area;
2546 }
2547
2548 static int dma_xfer(struct dma_engine *dma,
2549                 const unsigned int *data,
2550                 unsigned int count)
2551 {
2552         memcpy(dma->dmab->area, data, count);
2553         return 0;
2554 }
2555
2556 static void dma_get_converter_format(
2557                 struct dma_engine *dma,
2558                 unsigned short *format)
2559 {
2560         if (format)
2561                 *format = dma->m_converter_format;
2562 }
2563
2564 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2565 {
2566         struct ca0132_spec *spec = dma->codec->spec;
2567
2568         return spec->dsp_stream_id;
2569 }
2570
2571 struct dsp_image_seg {
2572         u32 magic;
2573         u32 chip_addr;
2574         u32 count;
2575         u32 data[0];
2576 };
2577
2578 static const u32 g_magic_value = 0x4c46584d;
2579 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2580
2581 static bool is_valid(const struct dsp_image_seg *p)
2582 {
2583         return p->magic == g_magic_value;
2584 }
2585
2586 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2587 {
2588         return g_chip_addr_magic_value == p->chip_addr;
2589 }
2590
2591 static bool is_last(const struct dsp_image_seg *p)
2592 {
2593         return p->count == 0;
2594 }
2595
2596 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2597 {
2598         return sizeof(*p) + p->count*sizeof(u32);
2599 }
2600
2601 static const struct dsp_image_seg *get_next_seg_ptr(
2602                                 const struct dsp_image_seg *p)
2603 {
2604         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2605 }
2606
2607 /*
2608  * CA0132 chip DSP transfer stuffs.  For DSP download.
2609  */
2610 #define INVALID_DMA_CHANNEL (~0U)
2611
2612 /*
2613  * Program a list of address/data pairs via the ChipIO widget.
2614  * The segment data is in the format of successive pairs of words.
2615  * These are repeated as indicated by the segment's count field.
2616  */
2617 static int dspxfr_hci_write(struct hda_codec *codec,
2618                         const struct dsp_image_seg *fls)
2619 {
2620         int status;
2621         const u32 *data;
2622         unsigned int count;
2623
2624         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2625                 codec_dbg(codec, "hci_write invalid params\n");
2626                 return -EINVAL;
2627         }
2628
2629         count = fls->count;
2630         data = (u32 *)(fls->data);
2631         while (count >= 2) {
2632                 status = chipio_write(codec, data[0], data[1]);
2633                 if (status < 0) {
2634                         codec_dbg(codec, "hci_write chipio failed\n");
2635                         return status;
2636                 }
2637                 count -= 2;
2638                 data  += 2;
2639         }
2640         return 0;
2641 }
2642
2643 /**
2644  * Write a block of data into DSP code or data RAM using pre-allocated
2645  * DMA engine.
2646  *
2647  * @codec: the HDA codec
2648  * @fls: pointer to a fast load image
2649  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2650  *         no relocation
2651  * @dma_engine: pointer to DMA engine to be used for DSP download
2652  * @dma_chan: The number of DMA channels used for DSP download
2653  * @port_map_mask: port mapping
2654  * @ovly: TRUE if overlay format is required
2655  *
2656  * Returns zero or a negative error code.
2657  */
2658 static int dspxfr_one_seg(struct hda_codec *codec,
2659                         const struct dsp_image_seg *fls,
2660                         unsigned int reloc,
2661                         struct dma_engine *dma_engine,
2662                         unsigned int dma_chan,
2663                         unsigned int port_map_mask,
2664                         bool ovly)
2665 {
2666         int status = 0;
2667         bool comm_dma_setup_done = false;
2668         const unsigned int *data;
2669         unsigned int chip_addx;
2670         unsigned int words_to_write;
2671         unsigned int buffer_size_words;
2672         unsigned char *buffer_addx;
2673         unsigned short hda_format;
2674         unsigned int sample_rate_div;
2675         unsigned int sample_rate_mul;
2676         unsigned int num_chans;
2677         unsigned int hda_frame_size_words;
2678         unsigned int remainder_words;
2679         const u32 *data_remainder;
2680         u32 chip_addx_remainder;
2681         unsigned int run_size_words;
2682         const struct dsp_image_seg *hci_write = NULL;
2683         unsigned long timeout;
2684         bool dma_active;
2685
2686         if (fls == NULL)
2687                 return -EINVAL;
2688         if (is_hci_prog_list_seg(fls)) {
2689                 hci_write = fls;
2690                 fls = get_next_seg_ptr(fls);
2691         }
2692
2693         if (hci_write && (!fls || is_last(fls))) {
2694                 codec_dbg(codec, "hci_write\n");
2695                 return dspxfr_hci_write(codec, hci_write);
2696         }
2697
2698         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2699                 codec_dbg(codec, "Invalid Params\n");
2700                 return -EINVAL;
2701         }
2702
2703         data = fls->data;
2704         chip_addx = fls->chip_addr,
2705         words_to_write = fls->count;
2706
2707         if (!words_to_write)
2708                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2709         if (reloc)
2710                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2711
2712         if (!UC_RANGE(chip_addx, words_to_write) &&
2713             !X_RANGE_ALL(chip_addx, words_to_write) &&
2714             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2715                 codec_dbg(codec, "Invalid chip_addx Params\n");
2716                 return -EINVAL;
2717         }
2718
2719         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2720                                         sizeof(u32);
2721
2722         buffer_addx = dma_get_buffer_addr(dma_engine);
2723
2724         if (buffer_addx == NULL) {
2725                 codec_dbg(codec, "dma_engine buffer NULL\n");
2726                 return -EINVAL;
2727         }
2728
2729         dma_get_converter_format(dma_engine, &hda_format);
2730         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2731         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2732         num_chans = get_hdafmt_chs(hda_format) + 1;
2733
2734         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2735                         (num_chans * sample_rate_mul / sample_rate_div));
2736
2737         if (hda_frame_size_words == 0) {
2738                 codec_dbg(codec, "frmsz zero\n");
2739                 return -EINVAL;
2740         }
2741
2742         buffer_size_words = min(buffer_size_words,
2743                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2744                                 65536 : 32768));
2745         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2746         codec_dbg(codec,
2747                    "chpadr=0x%08x frmsz=%u nchan=%u "
2748                    "rate_mul=%u div=%u bufsz=%u\n",
2749                    chip_addx, hda_frame_size_words, num_chans,
2750                    sample_rate_mul, sample_rate_div, buffer_size_words);
2751
2752         if (buffer_size_words < hda_frame_size_words) {
2753                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2754                 return -EINVAL;
2755         }
2756
2757         remainder_words = words_to_write % hda_frame_size_words;
2758         data_remainder = data;
2759         chip_addx_remainder = chip_addx;
2760
2761         data += remainder_words;
2762         chip_addx += remainder_words*sizeof(u32);
2763         words_to_write -= remainder_words;
2764
2765         while (words_to_write != 0) {
2766                 run_size_words = min(buffer_size_words, words_to_write);
2767                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2768                             words_to_write, run_size_words, remainder_words);
2769                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2770                 if (!comm_dma_setup_done) {
2771                         status = dsp_dma_stop(codec, dma_chan, ovly);
2772                         if (status < 0)
2773                                 return status;
2774                         status = dsp_dma_setup_common(codec, chip_addx,
2775                                                 dma_chan, port_map_mask, ovly);
2776                         if (status < 0)
2777                                 return status;
2778                         comm_dma_setup_done = true;
2779                 }
2780
2781                 status = dsp_dma_setup(codec, chip_addx,
2782                                                 run_size_words, dma_chan);
2783                 if (status < 0)
2784                         return status;
2785                 status = dsp_dma_start(codec, dma_chan, ovly);
2786                 if (status < 0)
2787                         return status;
2788                 if (!dsp_is_dma_active(codec, dma_chan)) {
2789                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2790                         return -EIO;
2791                 }
2792                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2793                 if (status < 0)
2794                         return status;
2795                 if (remainder_words != 0) {
2796                         status = chipio_write_multiple(codec,
2797                                                 chip_addx_remainder,
2798                                                 data_remainder,
2799                                                 remainder_words);
2800                         if (status < 0)
2801                                 return status;
2802                         remainder_words = 0;
2803                 }
2804                 if (hci_write) {
2805                         status = dspxfr_hci_write(codec, hci_write);
2806                         if (status < 0)
2807                                 return status;
2808                         hci_write = NULL;
2809                 }
2810
2811                 timeout = jiffies + msecs_to_jiffies(2000);
2812                 do {
2813                         dma_active = dsp_is_dma_active(codec, dma_chan);
2814                         if (!dma_active)
2815                                 break;
2816                         msleep(20);
2817                 } while (time_before(jiffies, timeout));
2818                 if (dma_active)
2819                         break;
2820
2821                 codec_dbg(codec, "+++++ DMA complete\n");
2822                 dma_set_state(dma_engine, DMA_STATE_STOP);
2823                 status = dma_reset(dma_engine);
2824
2825                 if (status < 0)
2826                         return status;
2827
2828                 data += run_size_words;
2829                 chip_addx += run_size_words*sizeof(u32);
2830                 words_to_write -= run_size_words;
2831         }
2832
2833         if (remainder_words != 0) {
2834                 status = chipio_write_multiple(codec, chip_addx_remainder,
2835                                         data_remainder, remainder_words);
2836         }
2837
2838         return status;
2839 }
2840
2841 /**
2842  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2843  *
2844  * @codec: the HDA codec
2845  * @fls_data: pointer to a fast load image
2846  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2847  *         no relocation
2848  * @sample_rate: sampling rate of the stream used for DSP download
2849  * @channels: channels of the stream used for DSP download
2850  * @ovly: TRUE if overlay format is required
2851  *
2852  * Returns zero or a negative error code.
2853  */
2854 static int dspxfr_image(struct hda_codec *codec,
2855                         const struct dsp_image_seg *fls_data,
2856                         unsigned int reloc,
2857                         unsigned int sample_rate,
2858                         unsigned short channels,
2859                         bool ovly)
2860 {
2861         struct ca0132_spec *spec = codec->spec;
2862         int status;
2863         unsigned short hda_format = 0;
2864         unsigned int response;
2865         unsigned char stream_id = 0;
2866         struct dma_engine *dma_engine;
2867         unsigned int dma_chan;
2868         unsigned int port_map_mask;
2869
2870         if (fls_data == NULL)
2871                 return -EINVAL;
2872
2873         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2874         if (!dma_engine)
2875                 return -ENOMEM;
2876
2877         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2878         if (!dma_engine->dmab) {
2879                 kfree(dma_engine);
2880                 return -ENOMEM;
2881         }
2882
2883         dma_engine->codec = codec;
2884         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2885         dma_engine->m_converter_format = hda_format;
2886         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2887                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2888
2889         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2890
2891         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2892                                         hda_format, &response);
2893
2894         if (status < 0) {
2895                 codec_dbg(codec, "set converter format fail\n");
2896                 goto exit;
2897         }
2898
2899         status = snd_hda_codec_load_dsp_prepare(codec,
2900                                 dma_engine->m_converter_format,
2901                                 dma_engine->buf_size,
2902                                 dma_engine->dmab);
2903         if (status < 0)
2904                 goto exit;
2905         spec->dsp_stream_id = status;
2906
2907         if (ovly) {
2908                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2909                 if (status < 0) {
2910                         codec_dbg(codec, "alloc dmachan fail\n");
2911                         dma_chan = INVALID_DMA_CHANNEL;
2912                         goto exit;
2913                 }
2914         }
2915
2916         port_map_mask = 0;
2917         status = dsp_allocate_ports_format(codec, hda_format,
2918                                         &port_map_mask);
2919         if (status < 0) {
2920                 codec_dbg(codec, "alloc ports fail\n");
2921                 goto exit;
2922         }
2923
2924         stream_id = dma_get_stream_id(dma_engine);
2925         status = codec_set_converter_stream_channel(codec,
2926                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2927         if (status < 0) {
2928                 codec_dbg(codec, "set stream chan fail\n");
2929                 goto exit;
2930         }
2931
2932         while ((fls_data != NULL) && !is_last(fls_data)) {
2933                 if (!is_valid(fls_data)) {
2934                         codec_dbg(codec, "FLS check fail\n");
2935                         status = -EINVAL;
2936                         goto exit;
2937                 }
2938                 status = dspxfr_one_seg(codec, fls_data, reloc,
2939                                         dma_engine, dma_chan,
2940                                         port_map_mask, ovly);
2941                 if (status < 0)
2942                         break;
2943
2944                 if (is_hci_prog_list_seg(fls_data))
2945                         fls_data = get_next_seg_ptr(fls_data);
2946
2947                 if ((fls_data != NULL) && !is_last(fls_data))
2948                         fls_data = get_next_seg_ptr(fls_data);
2949         }
2950
2951         if (port_map_mask != 0)
2952                 status = dsp_free_ports(codec);
2953
2954         if (status < 0)
2955                 goto exit;
2956
2957         status = codec_set_converter_stream_channel(codec,
2958                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2959
2960 exit:
2961         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2962                 dspio_free_dma_chan(codec, dma_chan);
2963
2964         if (dma_engine->dmab->area)
2965                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2966         kfree(dma_engine->dmab);
2967         kfree(dma_engine);
2968
2969         return status;
2970 }
2971
2972 /*
2973  * CA0132 DSP download stuffs.
2974  */
2975 static void dspload_post_setup(struct hda_codec *codec)
2976 {
2977         struct ca0132_spec *spec = codec->spec;
2978         codec_dbg(codec, "---- dspload_post_setup ------\n");
2979         if (!spec->use_alt_functions) {
2980                 /*set DSP speaker to 2.0 configuration*/
2981                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2982                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2983
2984                 /*update write pointer*/
2985                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2986         }
2987 }
2988
2989 /**
2990  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2991  *
2992  * @codec: the HDA codec
2993  * @fls: pointer to a fast load image
2994  * @ovly: TRUE if overlay format is required
2995  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2996  *         no relocation
2997  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2998  * @router_chans: number of audio router channels to be allocated (0 means use
2999  *                internal defaults; max is 32)
3000  *
3001  * Download DSP from a DSP Image Fast Load structure. This structure is a
3002  * linear, non-constant sized element array of structures, each of which
3003  * contain the count of the data to be loaded, the data itself, and the
3004  * corresponding starting chip address of the starting data location.
3005  * Returns zero or a negative error code.
3006  */
3007 static int dspload_image(struct hda_codec *codec,
3008                         const struct dsp_image_seg *fls,
3009                         bool ovly,
3010                         unsigned int reloc,
3011                         bool autostart,
3012                         int router_chans)
3013 {
3014         int status = 0;
3015         unsigned int sample_rate;
3016         unsigned short channels;
3017
3018         codec_dbg(codec, "---- dspload_image begin ------\n");
3019         if (router_chans == 0) {
3020                 if (!ovly)
3021                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3022                 else
3023                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3024         }
3025
3026         sample_rate = 48000;
3027         channels = (unsigned short)router_chans;
3028
3029         while (channels > 16) {
3030                 sample_rate *= 2;
3031                 channels /= 2;
3032         }
3033
3034         do {
3035                 codec_dbg(codec, "Ready to program DMA\n");
3036                 if (!ovly)
3037                         status = dsp_reset(codec);
3038
3039                 if (status < 0)
3040                         break;
3041
3042                 codec_dbg(codec, "dsp_reset() complete\n");
3043                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3044                                       ovly);
3045
3046                 if (status < 0)
3047                         break;
3048
3049                 codec_dbg(codec, "dspxfr_image() complete\n");
3050                 if (autostart && !ovly) {
3051                         dspload_post_setup(codec);
3052                         status = dsp_set_run_state(codec);
3053                 }
3054
3055                 codec_dbg(codec, "LOAD FINISHED\n");
3056         } while (0);
3057
3058         return status;
3059 }
3060
3061 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3062 static bool dspload_is_loaded(struct hda_codec *codec)
3063 {
3064         unsigned int data = 0;
3065         int status = 0;
3066
3067         status = chipio_read(codec, 0x40004, &data);
3068         if ((status < 0) || (data != 1))
3069                 return false;
3070
3071         return true;
3072 }
3073 #else
3074 #define dspload_is_loaded(codec)        false
3075 #endif
3076
3077 static bool dspload_wait_loaded(struct hda_codec *codec)
3078 {
3079         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3080
3081         do {
3082                 if (dspload_is_loaded(codec)) {
3083                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3084                         return true;
3085                 }
3086                 msleep(20);
3087         } while (time_before(jiffies, timeout));
3088
3089         codec_err(codec, "ca0132 failed to download DSP\n");
3090         return false;
3091 }
3092
3093 /*
3094  * Setup GPIO for the other variants of Core3D.
3095  */
3096
3097 /*
3098  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3099  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3100  * The first eight bits are just the number of the pin. So far, I've only seen
3101  * this number go to 7.
3102  */
3103 static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3104                 bool enable)
3105 {
3106         struct ca0132_spec *spec = codec->spec;
3107         unsigned short gpio_data;
3108
3109         gpio_data = gpio_pin & 0xF;
3110         gpio_data |= ((enable << 8) & 0x100);
3111
3112         writew(gpio_data, spec->mem_base + 0x320);
3113 }
3114
3115 /*
3116  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3117  * the card shows as having no GPIO pins.
3118  */
3119 static void ca0132_gpio_init(struct hda_codec *codec)
3120 {
3121         struct ca0132_spec *spec = codec->spec;
3122
3123         switch (spec->quirk) {
3124         case QUIRK_SBZ:
3125                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3126                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3127                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3128                 break;
3129         case QUIRK_R3DI:
3130                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3131                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3132                 break;
3133         }
3134
3135 }
3136
3137 /* Sets the GPIO for audio output. */
3138 static void ca0132_gpio_setup(struct hda_codec *codec)
3139 {
3140         struct ca0132_spec *spec = codec->spec;
3141
3142         switch (spec->quirk) {
3143         case QUIRK_SBZ:
3144                 snd_hda_codec_write(codec, 0x01, 0,
3145                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3146                 snd_hda_codec_write(codec, 0x01, 0,
3147                                 AC_VERB_SET_GPIO_MASK, 0x07);
3148                 snd_hda_codec_write(codec, 0x01, 0,
3149                                 AC_VERB_SET_GPIO_DATA, 0x04);
3150                 snd_hda_codec_write(codec, 0x01, 0,
3151                                 AC_VERB_SET_GPIO_DATA, 0x06);
3152                 break;
3153         case QUIRK_R3DI:
3154                 snd_hda_codec_write(codec, 0x01, 0,
3155                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3156                 snd_hda_codec_write(codec, 0x01, 0,
3157                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3158                 snd_hda_codec_write(codec, 0x01, 0,
3159                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3160                 break;
3161         }
3162 }
3163
3164 /*
3165  * GPIO control functions for the Recon3D integrated.
3166  */
3167
3168 enum r3di_gpio_bit {
3169         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3170         R3DI_MIC_SELECT_BIT = 1,
3171         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3172         R3DI_OUT_SELECT_BIT = 2,
3173         /*
3174          * I dunno what this actually does, but it stays on until the dsp
3175          * is downloaded.
3176          */
3177         R3DI_GPIO_DSP_DOWNLOADING = 3,
3178         /*
3179          * Same as above, no clue what it does, but it comes on after the dsp
3180          * is downloaded.
3181          */
3182         R3DI_GPIO_DSP_DOWNLOADED = 4
3183 };
3184
3185 enum r3di_mic_select {
3186         /* Set GPIO bit 1 to 0 for rear mic */
3187         R3DI_REAR_MIC = 0,
3188         /* Set GPIO bit 1 to 1 for front microphone*/
3189         R3DI_FRONT_MIC = 1
3190 };
3191
3192 enum r3di_out_select {
3193         /* Set GPIO bit 2 to 0 for headphone */
3194         R3DI_HEADPHONE_OUT = 0,
3195         /* Set GPIO bit 2 to 1 for speaker */
3196         R3DI_LINE_OUT = 1
3197 };
3198 enum r3di_dsp_status {
3199         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3200         R3DI_DSP_DOWNLOADING = 0,
3201         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3202         R3DI_DSP_DOWNLOADED = 1
3203 };
3204
3205
3206 static void r3di_gpio_mic_set(struct hda_codec *codec,
3207                 enum r3di_mic_select cur_mic)
3208 {
3209         unsigned int cur_gpio;
3210
3211         /* Get the current GPIO Data setup */
3212         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3213
3214         switch (cur_mic) {
3215         case R3DI_REAR_MIC:
3216                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3217                 break;
3218         case R3DI_FRONT_MIC:
3219                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3220                 break;
3221         }
3222         snd_hda_codec_write(codec, codec->core.afg, 0,
3223                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3224 }
3225
3226 static void r3di_gpio_out_set(struct hda_codec *codec,
3227                 enum r3di_out_select cur_out)
3228 {
3229         unsigned int cur_gpio;
3230
3231         /* Get the current GPIO Data setup */
3232         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3233
3234         switch (cur_out) {
3235         case R3DI_HEADPHONE_OUT:
3236                 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3237                 break;
3238         case R3DI_LINE_OUT:
3239                 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3240                 break;
3241         }
3242         snd_hda_codec_write(codec, codec->core.afg, 0,
3243                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3244 }
3245
3246 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3247                 enum r3di_dsp_status dsp_status)
3248 {
3249         unsigned int cur_gpio;
3250
3251         /* Get the current GPIO Data setup */
3252         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3253
3254         switch (dsp_status) {
3255         case R3DI_DSP_DOWNLOADING:
3256                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3257                 snd_hda_codec_write(codec, codec->core.afg, 0,
3258                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3259                 break;
3260         case R3DI_DSP_DOWNLOADED:
3261                 /* Set DOWNLOADING bit to 0. */
3262                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3263
3264                 snd_hda_codec_write(codec, codec->core.afg, 0,
3265                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3266
3267                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3268                 break;
3269         }
3270
3271         snd_hda_codec_write(codec, codec->core.afg, 0,
3272                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3273 }
3274
3275 /*
3276  * PCM callbacks
3277  */
3278 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3279                         struct hda_codec *codec,
3280                         unsigned int stream_tag,
3281                         unsigned int format,
3282                         struct snd_pcm_substream *substream)
3283 {
3284         struct ca0132_spec *spec = codec->spec;
3285
3286         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3287
3288         return 0;
3289 }
3290
3291 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3292                         struct hda_codec *codec,
3293                         struct snd_pcm_substream *substream)
3294 {
3295         struct ca0132_spec *spec = codec->spec;
3296
3297         if (spec->dsp_state == DSP_DOWNLOADING)
3298                 return 0;
3299
3300         /*If Playback effects are on, allow stream some time to flush
3301          *effects tail*/
3302         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3303                 msleep(50);
3304
3305         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3306
3307         return 0;
3308 }
3309
3310 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3311                         struct hda_codec *codec,
3312                         struct snd_pcm_substream *substream)
3313 {
3314         struct ca0132_spec *spec = codec->spec;
3315         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3316         struct snd_pcm_runtime *runtime = substream->runtime;
3317
3318         if (spec->dsp_state != DSP_DOWNLOADED)
3319                 return 0;
3320
3321         /* Add latency if playback enhancement and either effect is enabled. */
3322         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3323                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3324                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3325                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3326         }
3327
3328         /* Applying Speaker EQ adds latency as well. */
3329         if (spec->cur_out_type == SPEAKER_OUT)
3330                 latency += DSP_SPEAKER_OUT_LATENCY;
3331
3332         return (latency * runtime->rate) / 1000;
3333 }
3334
3335 /*
3336  * Digital out
3337  */
3338 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3339                                         struct hda_codec *codec,
3340                                         struct snd_pcm_substream *substream)
3341 {
3342         struct ca0132_spec *spec = codec->spec;
3343         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3344 }
3345
3346 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3347                         struct hda_codec *codec,
3348                         unsigned int stream_tag,
3349                         unsigned int format,
3350                         struct snd_pcm_substream *substream)
3351 {
3352         struct ca0132_spec *spec = codec->spec;
3353         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3354                                              stream_tag, format, substream);
3355 }
3356
3357 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3358                         struct hda_codec *codec,
3359                         struct snd_pcm_substream *substream)
3360 {
3361         struct ca0132_spec *spec = codec->spec;
3362         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3363 }
3364
3365 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3366                                          struct hda_codec *codec,
3367                                          struct snd_pcm_substream *substream)
3368 {
3369         struct ca0132_spec *spec = codec->spec;
3370         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3371 }
3372
3373 /*
3374  * Analog capture
3375  */
3376 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3377                                         struct hda_codec *codec,
3378                                         unsigned int stream_tag,
3379                                         unsigned int format,
3380                                         struct snd_pcm_substream *substream)
3381 {
3382         snd_hda_codec_setup_stream(codec, hinfo->nid,
3383                                    stream_tag, 0, format);
3384
3385         return 0;
3386 }
3387
3388 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3389                         struct hda_codec *codec,
3390                         struct snd_pcm_substream *substream)
3391 {
3392         struct ca0132_spec *spec = codec->spec;
3393
3394         if (spec->dsp_state == DSP_DOWNLOADING)
3395                 return 0;
3396
3397         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3398         return 0;
3399 }
3400
3401 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3402                         struct hda_codec *codec,
3403                         struct snd_pcm_substream *substream)
3404 {
3405         struct ca0132_spec *spec = codec->spec;
3406         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3407         struct snd_pcm_runtime *runtime = substream->runtime;
3408
3409         if (spec->dsp_state != DSP_DOWNLOADED)
3410                 return 0;
3411
3412         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3413                 latency += DSP_CRYSTAL_VOICE_LATENCY;
3414
3415         return (latency * runtime->rate) / 1000;
3416 }
3417
3418 /*
3419  * Controls stuffs.
3420  */
3421
3422 /*
3423  * Mixer controls helpers.
3424  */
3425 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3426         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3427           .name = xname, \
3428           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3429           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3430                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3431                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3432           .info = ca0132_volume_info, \
3433           .get = ca0132_volume_get, \
3434           .put = ca0132_volume_put, \
3435           .tlv = { .c = ca0132_volume_tlv }, \
3436           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3437
3438 /*
3439  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3440  * volume put, which is used for setting the DSP volume. This was done because
3441  * the ca0132 functions were taking too much time and causing lag.
3442  */
3443 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3444         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3445           .name = xname, \
3446           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3447           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3448                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3449                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3450           .info = snd_hda_mixer_amp_volume_info, \
3451           .get = snd_hda_mixer_amp_volume_get, \
3452           .put = ca0132_alt_volume_put, \
3453           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3454           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3455
3456 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3457         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3458           .name = xname, \
3459           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3460           .info = snd_hda_mixer_amp_switch_info, \
3461           .get = ca0132_switch_get, \
3462           .put = ca0132_switch_put, \
3463           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3464
3465 /* stereo */
3466 #define CA0132_CODEC_VOL(xname, nid, dir) \
3467         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3468 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3469         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3470 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3471         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3472
3473 /* lookup tables */
3474 /*
3475  * Lookup table with decibel values for the DSP. When volume is changed in
3476  * Windows, the DSP is also sent the dB value in floating point. In Windows,
3477  * these values have decimal points, probably because the Windows driver
3478  * actually uses floating point. We can't here, so I made a lookup table of
3479  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3480  * DAC's, and 9 is the maximum.
3481  */
3482 static const unsigned int float_vol_db_lookup[] = {
3483 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3484 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3485 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3486 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3487 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3488 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3489 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3490 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3491 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3492 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3493 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3494 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3495 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3496 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3497 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3498 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3499 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3500 };
3501
3502 /*
3503  * This table counts from float 0 to 1 in increments of .01, which is
3504  * useful for a few different sliders.
3505  */
3506 static const unsigned int float_zero_to_one_lookup[] = {
3507 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3508 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3509 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3510 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3511 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3512 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3513 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3514 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3515 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3516 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3517 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3518 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3519 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3520 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3521 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3522 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3523 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3524 };
3525
3526 /*
3527  * This table counts from float 10 to 1000, which is the range of the x-bass
3528  * crossover slider in Windows.
3529  */
3530 static const unsigned int float_xbass_xover_lookup[] = {
3531 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3532 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3533 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3534 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3535 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3536 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3537 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3538 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3539 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3540 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3541 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3542 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3543 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3544 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3545 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3546 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3547 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3548 };
3549
3550 /* The following are for tuning of products */
3551 #ifdef ENABLE_TUNING_CONTROLS
3552
3553 static unsigned int voice_focus_vals_lookup[] = {
3554 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3555 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3556 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3557 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3558 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3559 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3560 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3561 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3562 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3563 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3564 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3565 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3566 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3567 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3568 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3569 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3570 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3571 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3572 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3573 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3574 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3575 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3576 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3577 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3578 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3579 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3580 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3581 };
3582
3583 static unsigned int mic_svm_vals_lookup[] = {
3584 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3585 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3586 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3587 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3588 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3589 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3590 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3591 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3592 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3593 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3594 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3595 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3596 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3597 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3598 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3599 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3600 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3601 };
3602
3603 static unsigned int equalizer_vals_lookup[] = {
3604 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3605 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3606 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3607 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3608 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3609 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3610 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3611 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3612 0x41C00000
3613 };
3614
3615 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3616                           unsigned int *lookup, int idx)
3617 {
3618         int i = 0;
3619
3620         for (i = 0; i < TUNING_CTLS_COUNT; i++)
3621                 if (nid == ca0132_tuning_ctls[i].nid)
3622                         goto found;
3623
3624         return -EINVAL;
3625 found:
3626         snd_hda_power_up(codec);
3627         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3628                         ca0132_tuning_ctls[i].req,
3629                         &(lookup[idx]), sizeof(unsigned int));
3630         snd_hda_power_down(codec);
3631
3632         return 1;
3633 }
3634
3635 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3636                           struct snd_ctl_elem_value *ucontrol)
3637 {
3638         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3639         struct ca0132_spec *spec = codec->spec;
3640         hda_nid_t nid = get_amp_nid(kcontrol);
3641         long *valp = ucontrol->value.integer.value;
3642         int idx = nid - TUNING_CTL_START_NID;
3643
3644         *valp = spec->cur_ctl_vals[idx];
3645         return 0;
3646 }
3647
3648 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3649                               struct snd_ctl_elem_info *uinfo)
3650 {
3651         int chs = get_amp_channels(kcontrol);
3652         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3653         uinfo->count = chs == 3 ? 2 : 1;
3654         uinfo->value.integer.min = 20;
3655         uinfo->value.integer.max = 180;
3656         uinfo->value.integer.step = 1;
3657
3658         return 0;
3659 }
3660
3661 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3662                                 struct snd_ctl_elem_value *ucontrol)
3663 {
3664         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3665         struct ca0132_spec *spec = codec->spec;
3666         hda_nid_t nid = get_amp_nid(kcontrol);
3667         long *valp = ucontrol->value.integer.value;
3668         int idx;
3669
3670         idx = nid - TUNING_CTL_START_NID;
3671         /* any change? */
3672         if (spec->cur_ctl_vals[idx] == *valp)
3673                 return 0;
3674
3675         spec->cur_ctl_vals[idx] = *valp;
3676
3677         idx = *valp - 20;
3678         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3679
3680         return 1;
3681 }
3682
3683 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3684                               struct snd_ctl_elem_info *uinfo)
3685 {
3686         int chs = get_amp_channels(kcontrol);
3687         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3688         uinfo->count = chs == 3 ? 2 : 1;
3689         uinfo->value.integer.min = 0;
3690         uinfo->value.integer.max = 100;
3691         uinfo->value.integer.step = 1;
3692
3693         return 0;
3694 }
3695
3696 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3697                                 struct snd_ctl_elem_value *ucontrol)
3698 {
3699         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3700         struct ca0132_spec *spec = codec->spec;
3701         hda_nid_t nid = get_amp_nid(kcontrol);
3702         long *valp = ucontrol->value.integer.value;
3703         int idx;
3704
3705         idx = nid - TUNING_CTL_START_NID;
3706         /* any change? */
3707         if (spec->cur_ctl_vals[idx] == *valp)
3708                 return 0;
3709
3710         spec->cur_ctl_vals[idx] = *valp;
3711
3712         idx = *valp;
3713         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3714
3715         return 0;
3716 }
3717
3718 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3719                               struct snd_ctl_elem_info *uinfo)
3720 {
3721         int chs = get_amp_channels(kcontrol);
3722         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3723         uinfo->count = chs == 3 ? 2 : 1;
3724         uinfo->value.integer.min = 0;
3725         uinfo->value.integer.max = 48;
3726         uinfo->value.integer.step = 1;
3727
3728         return 0;
3729 }
3730
3731 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3732                                 struct snd_ctl_elem_value *ucontrol)
3733 {
3734         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3735         struct ca0132_spec *spec = codec->spec;
3736         hda_nid_t nid = get_amp_nid(kcontrol);
3737         long *valp = ucontrol->value.integer.value;
3738         int idx;
3739
3740         idx = nid - TUNING_CTL_START_NID;
3741         /* any change? */
3742         if (spec->cur_ctl_vals[idx] == *valp)
3743                 return 0;
3744
3745         spec->cur_ctl_vals[idx] = *valp;
3746
3747         idx = *valp;
3748         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3749
3750         return 1;
3751 }
3752
3753 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3754 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3755
3756 static int add_tuning_control(struct hda_codec *codec,
3757                                 hda_nid_t pnid, hda_nid_t nid,
3758                                 const char *name, int dir)
3759 {
3760         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3761         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3762         struct snd_kcontrol_new knew =
3763                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3764
3765         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3766                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3767         knew.tlv.c = 0;
3768         knew.tlv.p = 0;
3769         switch (pnid) {
3770         case VOICE_FOCUS:
3771                 knew.info = voice_focus_ctl_info;
3772                 knew.get = tuning_ctl_get;
3773                 knew.put = voice_focus_ctl_put;
3774                 knew.tlv.p = voice_focus_db_scale;
3775                 break;
3776         case MIC_SVM:
3777                 knew.info = mic_svm_ctl_info;
3778                 knew.get = tuning_ctl_get;
3779                 knew.put = mic_svm_ctl_put;
3780                 break;
3781         case EQUALIZER:
3782                 knew.info = equalizer_ctl_info;
3783                 knew.get = tuning_ctl_get;
3784                 knew.put = equalizer_ctl_put;
3785                 knew.tlv.p = eq_db_scale;
3786                 break;
3787         default:
3788                 return 0;
3789         }
3790         knew.private_value =
3791                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3792         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3793         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3794 }
3795
3796 static int add_tuning_ctls(struct hda_codec *codec)
3797 {
3798         int i;
3799         int err;
3800
3801         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3802                 err = add_tuning_control(codec,
3803                                         ca0132_tuning_ctls[i].parent_nid,
3804                                         ca0132_tuning_ctls[i].nid,
3805                                         ca0132_tuning_ctls[i].name,
3806                                         ca0132_tuning_ctls[i].direct);
3807                 if (err < 0)
3808                         return err;
3809         }
3810
3811         return 0;
3812 }
3813
3814 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3815 {
3816         struct ca0132_spec *spec = codec->spec;
3817         int i;
3818
3819         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3820         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3821         /* SVM level defaults to 0.74. */
3822         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3823
3824         /* EQ defaults to 0dB. */
3825         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3826                 spec->cur_ctl_vals[i] = 24;
3827 }
3828 #endif /*ENABLE_TUNING_CONTROLS*/
3829
3830 /*
3831  * Select the active output.
3832  * If autodetect is enabled, output will be selected based on jack detection.
3833  * If jack inserted, headphone will be selected, else built-in speakers
3834  * If autodetect is disabled, output will be selected based on selection.
3835  */
3836 static int ca0132_select_out(struct hda_codec *codec)
3837 {
3838         struct ca0132_spec *spec = codec->spec;
3839         unsigned int pin_ctl;
3840         int jack_present;
3841         int auto_jack;
3842         unsigned int tmp;
3843         int err;
3844
3845         codec_dbg(codec, "ca0132_select_out\n");
3846
3847         snd_hda_power_up_pm(codec);
3848
3849         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3850
3851         if (auto_jack)
3852                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3853         else
3854                 jack_present =
3855                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3856
3857         if (jack_present)
3858                 spec->cur_out_type = HEADPHONE_OUT;
3859         else
3860                 spec->cur_out_type = SPEAKER_OUT;
3861
3862         if (spec->cur_out_type == SPEAKER_OUT) {
3863                 codec_dbg(codec, "ca0132_select_out speaker\n");
3864                 /*speaker out config*/
3865                 tmp = FLOAT_ONE;
3866                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3867                 if (err < 0)
3868                         goto exit;
3869                 /*enable speaker EQ*/
3870                 tmp = FLOAT_ONE;
3871                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3872                 if (err < 0)
3873                         goto exit;
3874
3875                 /* Setup EAPD */
3876                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3877                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3878                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3879                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3880                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3881                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3882                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3883                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3884
3885                 /* disable headphone node */
3886                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3887                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3888                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3889                                     pin_ctl & ~PIN_HP);
3890                 /* enable speaker node */
3891                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3892                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3893                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3894                                     pin_ctl | PIN_OUT);
3895         } else {
3896                 codec_dbg(codec, "ca0132_select_out hp\n");
3897                 /*headphone out config*/
3898                 tmp = FLOAT_ZERO;
3899                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3900                 if (err < 0)
3901                         goto exit;
3902                 /*disable speaker EQ*/
3903                 tmp = FLOAT_ZERO;
3904                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3905                 if (err < 0)
3906                         goto exit;
3907
3908                 /* Setup EAPD */
3909                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3910                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3911                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3912                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3913                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3914                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3915                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3916                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3917
3918                 /* disable speaker*/
3919                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3920                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3921                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3922                                     pin_ctl & ~PIN_HP);
3923                 /* enable headphone*/
3924                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3925                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3926                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3927                                     pin_ctl | PIN_HP);
3928         }
3929
3930 exit:
3931         snd_hda_power_down_pm(codec);
3932
3933         return err < 0 ? err : 0;
3934 }
3935
3936 /*
3937  * This function behaves similarly to the ca0132_select_out funciton above,
3938  * except with a few differences. It adds the ability to select the current
3939  * output with an enumerated control "output source" if the auto detect
3940  * mute switch is set to off. If the auto detect mute switch is enabled, it
3941  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3942  * It also adds the ability to auto-detect the front headphone port. The only
3943  * way to select surround is to disable auto detect, and set Surround with the
3944  * enumerated control.
3945  */
3946 static int ca0132_alt_select_out(struct hda_codec *codec)
3947 {
3948         struct ca0132_spec *spec = codec->spec;
3949         unsigned int pin_ctl;
3950         int jack_present;
3951         int auto_jack;
3952         unsigned int i;
3953         unsigned int tmp;
3954         int err;
3955         /* Default Headphone is rear headphone */
3956         hda_nid_t headphone_nid = spec->out_pins[1];
3957
3958         codec_dbg(codec, "%s\n", __func__);
3959
3960         snd_hda_power_up_pm(codec);
3961
3962         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3963
3964         /*
3965          * If headphone rear or front is plugged in, set to headphone.
3966          * If neither is plugged in, set to rear line out. Only if
3967          * hp/speaker auto detect is enabled.
3968          */
3969         if (auto_jack) {
3970                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3971                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3972
3973                 if (jack_present)
3974                         spec->cur_out_type = HEADPHONE_OUT;
3975                 else
3976                         spec->cur_out_type = SPEAKER_OUT;
3977         } else
3978                 spec->cur_out_type = spec->out_enum_val;
3979
3980         /* Begin DSP output switch */
3981         tmp = FLOAT_ONE;
3982         err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3983         if (err < 0)
3984                 goto exit;
3985
3986         switch (spec->cur_out_type) {
3987         case SPEAKER_OUT:
3988                 codec_dbg(codec, "%s speaker\n", __func__);
3989                 /*speaker out config*/
3990                 switch (spec->quirk) {
3991                 case QUIRK_SBZ:
3992                         ca0132_mmio_gpio_set(codec, 7, false);
3993                         ca0132_mmio_gpio_set(codec, 4, true);
3994                         ca0132_mmio_gpio_set(codec, 1, true);
3995                         chipio_set_control_param(codec, 0x0D, 0x18);
3996                         break;
3997                 case QUIRK_R3DI:
3998                         chipio_set_control_param(codec, 0x0D, 0x24);
3999                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4000                         break;
4001                 case QUIRK_R3D:
4002                         chipio_set_control_param(codec, 0x0D, 0x24);
4003                         ca0132_mmio_gpio_set(codec, 1, true);
4004                         break;
4005                 }
4006
4007                 /* disable headphone node */
4008                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4009                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4010                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4011                                     pin_ctl & ~PIN_HP);
4012                 /* enable line-out node */
4013                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4014                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4015                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4016                                     pin_ctl | PIN_OUT);
4017                 /* Enable EAPD */
4018                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4019                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4020
4021                 /* If PlayEnhancement is enabled, set different source */
4022                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4023                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4024                 else
4025                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4026                 break;
4027         case HEADPHONE_OUT:
4028                 codec_dbg(codec, "%s hp\n", __func__);
4029                 /* Headphone out config*/
4030                 switch (spec->quirk) {
4031                 case QUIRK_SBZ:
4032                         ca0132_mmio_gpio_set(codec, 7, true);
4033                         ca0132_mmio_gpio_set(codec, 4, true);
4034                         ca0132_mmio_gpio_set(codec, 1, false);
4035                         chipio_set_control_param(codec, 0x0D, 0x12);
4036                         break;
4037                 case QUIRK_R3DI:
4038                         chipio_set_control_param(codec, 0x0D, 0x21);
4039                         r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4040                         break;
4041                 case QUIRK_R3D:
4042                         chipio_set_control_param(codec, 0x0D, 0x21);
4043                         ca0132_mmio_gpio_set(codec, 0x1, false);
4044                         break;
4045                 }
4046
4047                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4048                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4049
4050                 /* disable speaker*/
4051                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4052                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4053                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4054                                 pin_ctl & ~PIN_HP);
4055
4056                 /* enable headphone, either front or rear */
4057
4058                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4059                         headphone_nid = spec->out_pins[2];
4060                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4061                         headphone_nid = spec->out_pins[1];
4062
4063                 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4064                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4065                 snd_hda_set_pin_ctl(codec, headphone_nid,
4066                                     pin_ctl | PIN_HP);
4067
4068                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4069                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4070                 else
4071                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4072                 break;
4073         case SURROUND_OUT:
4074                 codec_dbg(codec, "%s surround\n", __func__);
4075                 /* Surround out config*/
4076                 switch (spec->quirk) {
4077                 case QUIRK_SBZ:
4078                         ca0132_mmio_gpio_set(codec, 7, false);
4079                         ca0132_mmio_gpio_set(codec, 4, true);
4080                         ca0132_mmio_gpio_set(codec, 1, true);
4081                         chipio_set_control_param(codec, 0x0D, 0x18);
4082                         break;
4083                 case QUIRK_R3DI:
4084                         chipio_set_control_param(codec, 0x0D, 0x24);
4085                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4086                         break;
4087                 case QUIRK_R3D:
4088                         ca0132_mmio_gpio_set(codec, 1, true);
4089                         chipio_set_control_param(codec, 0x0D, 0x24);
4090                         break;
4091                 }
4092                 /* enable line out node */
4093                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4094                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4095                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4096                                                 pin_ctl | PIN_OUT);
4097                 /* Disable headphone out */
4098                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4099                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4100                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4101                                     pin_ctl & ~PIN_HP);
4102                 /* Enable EAPD on line out */
4103                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4104                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4105                 /* enable center/lfe out node */
4106                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4107                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4108                 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4109                                     pin_ctl | PIN_OUT);
4110                 /* Now set rear surround node as out. */
4111                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4112                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4113                 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4114                                     pin_ctl | PIN_OUT);
4115
4116                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4117                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4118                 else
4119                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4120                 break;
4121         }
4122
4123         /* run through the output dsp commands for line-out */
4124         for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4125                 err = dspio_set_uint_param(codec,
4126                 alt_out_presets[spec->cur_out_type].mids[i],
4127                 alt_out_presets[spec->cur_out_type].reqs[i],
4128                 alt_out_presets[spec->cur_out_type].vals[i]);
4129
4130                 if (err < 0)
4131                         goto exit;
4132         }
4133
4134 exit:
4135         snd_hda_power_down_pm(codec);
4136
4137         return err < 0 ? err : 0;
4138 }
4139
4140 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4141 {
4142         struct ca0132_spec *spec = container_of(
4143                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4144         struct hda_jack_tbl *jack;
4145
4146         if (spec->use_alt_functions)
4147                 ca0132_alt_select_out(spec->codec);
4148         else
4149                 ca0132_select_out(spec->codec);
4150
4151         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4152         if (jack) {
4153                 jack->block_report = 0;
4154                 snd_hda_jack_report_sync(spec->codec);
4155         }
4156 }
4157
4158 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4159 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4160 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4161 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4162 static int stop_mic1(struct hda_codec *codec);
4163 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4164 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4165
4166 /*
4167  * Select the active VIP source
4168  */
4169 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4170 {
4171         struct ca0132_spec *spec = codec->spec;
4172         unsigned int tmp;
4173
4174         if (spec->dsp_state != DSP_DOWNLOADED)
4175                 return 0;
4176
4177         /* if CrystalVoice if off, vipsource should be 0 */
4178         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4179             (val == 0)) {
4180                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4181                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4182                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4183                 if (spec->cur_mic_type == DIGITAL_MIC)
4184                         tmp = FLOAT_TWO;
4185                 else
4186                         tmp = FLOAT_ONE;
4187                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4188                 tmp = FLOAT_ZERO;
4189                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4190         } else {
4191                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4192                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4193                 if (spec->cur_mic_type == DIGITAL_MIC)
4194                         tmp = FLOAT_TWO;
4195                 else
4196                         tmp = FLOAT_ONE;
4197                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4198                 tmp = FLOAT_ONE;
4199                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4200                 msleep(20);
4201                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4202         }
4203
4204         return 1;
4205 }
4206
4207 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4208 {
4209         struct ca0132_spec *spec = codec->spec;
4210         unsigned int tmp;
4211
4212         if (spec->dsp_state != DSP_DOWNLOADED)
4213                 return 0;
4214
4215         codec_dbg(codec, "%s\n", __func__);
4216
4217         chipio_set_stream_control(codec, 0x03, 0);
4218         chipio_set_stream_control(codec, 0x04, 0);
4219
4220         /* if CrystalVoice is off, vipsource should be 0 */
4221         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4222             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4223                 codec_dbg(codec, "%s: off.", __func__);
4224                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4225
4226                 tmp = FLOAT_ZERO;
4227                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4228
4229                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4230                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4231                 if (spec->quirk == QUIRK_R3DI)
4232                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4233
4234
4235                 if (spec->in_enum_val == REAR_LINE_IN)
4236                         tmp = FLOAT_ZERO;
4237                 else {
4238                         if (spec->quirk == QUIRK_SBZ)
4239                                 tmp = FLOAT_THREE;
4240                         else
4241                                 tmp = FLOAT_ONE;
4242                 }
4243
4244                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4245
4246         } else {
4247                 codec_dbg(codec, "%s: on.", __func__);
4248                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4249                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4250                 if (spec->quirk == QUIRK_R3DI)
4251                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4252
4253                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4254                         tmp = FLOAT_TWO;
4255                 else
4256                         tmp = FLOAT_ONE;
4257                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4258
4259                 tmp = FLOAT_ONE;
4260                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4261
4262                 msleep(20);
4263                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4264         }
4265
4266         chipio_set_stream_control(codec, 0x03, 1);
4267         chipio_set_stream_control(codec, 0x04, 1);
4268
4269         return 1;
4270 }
4271
4272 /*
4273  * Select the active microphone.
4274  * If autodetect is enabled, mic will be selected based on jack detection.
4275  * If jack inserted, ext.mic will be selected, else built-in mic
4276  * If autodetect is disabled, mic will be selected based on selection.
4277  */
4278 static int ca0132_select_mic(struct hda_codec *codec)
4279 {
4280         struct ca0132_spec *spec = codec->spec;
4281         int jack_present;
4282         int auto_jack;
4283
4284         codec_dbg(codec, "ca0132_select_mic\n");
4285
4286         snd_hda_power_up_pm(codec);
4287
4288         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4289
4290         if (auto_jack)
4291                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4292         else
4293                 jack_present =
4294                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4295
4296         if (jack_present)
4297                 spec->cur_mic_type = LINE_MIC_IN;
4298         else
4299                 spec->cur_mic_type = DIGITAL_MIC;
4300
4301         if (spec->cur_mic_type == DIGITAL_MIC) {
4302                 /* enable digital Mic */
4303                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4304                 ca0132_set_dmic(codec, 1);
4305                 ca0132_mic_boost_set(codec, 0);
4306                 /* set voice focus */
4307                 ca0132_effects_set(codec, VOICE_FOCUS,
4308                                    spec->effects_switch
4309                                    [VOICE_FOCUS - EFFECT_START_NID]);
4310         } else {
4311                 /* disable digital Mic */
4312                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4313                 ca0132_set_dmic(codec, 0);
4314                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4315                 /* disable voice focus */
4316                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4317         }
4318
4319         snd_hda_power_down_pm(codec);
4320
4321         return 0;
4322 }
4323
4324 /*
4325  * Select the active input.
4326  * Mic detection isn't used, because it's kind of pointless on the SBZ.
4327  * The front mic has no jack-detection, so the only way to switch to it
4328  * is to do it manually in alsamixer.
4329  */
4330 static int ca0132_alt_select_in(struct hda_codec *codec)
4331 {
4332         struct ca0132_spec *spec = codec->spec;
4333         unsigned int tmp;
4334
4335         codec_dbg(codec, "%s\n", __func__);
4336
4337         snd_hda_power_up_pm(codec);
4338
4339         chipio_set_stream_control(codec, 0x03, 0);
4340         chipio_set_stream_control(codec, 0x04, 0);
4341
4342         spec->cur_mic_type = spec->in_enum_val;
4343
4344         switch (spec->cur_mic_type) {
4345         case REAR_MIC:
4346                 switch (spec->quirk) {
4347                 case QUIRK_SBZ:
4348                 case QUIRK_R3D:
4349                         ca0132_mmio_gpio_set(codec, 0, false);
4350                         tmp = FLOAT_THREE;
4351                         break;
4352                 case QUIRK_R3DI:
4353                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4354                         tmp = FLOAT_ONE;
4355                         break;
4356                 default:
4357                         tmp = FLOAT_ONE;
4358                         break;
4359                 }
4360
4361                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4362                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4363                 if (spec->quirk == QUIRK_R3DI)
4364                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4365
4366                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4367
4368                 chipio_set_stream_control(codec, 0x03, 1);
4369                 chipio_set_stream_control(codec, 0x04, 1);
4370
4371                 if (spec->quirk == QUIRK_SBZ) {
4372                         chipio_write(codec, 0x18B098, 0x0000000C);
4373                         chipio_write(codec, 0x18B09C, 0x0000000C);
4374                 }
4375                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4376                 break;
4377         case REAR_LINE_IN:
4378                 ca0132_mic_boost_set(codec, 0);
4379                 switch (spec->quirk) {
4380                 case QUIRK_SBZ:
4381                 case QUIRK_R3D:
4382                         ca0132_mmio_gpio_set(codec, 0, false);
4383                         break;
4384                 case QUIRK_R3DI:
4385                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4386                         break;
4387                 }
4388
4389                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4390                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4391                 if (spec->quirk == QUIRK_R3DI)
4392                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4393
4394                 tmp = FLOAT_ZERO;
4395                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4396
4397                 if (spec->quirk == QUIRK_SBZ) {
4398                         chipio_write(codec, 0x18B098, 0x00000000);
4399                         chipio_write(codec, 0x18B09C, 0x00000000);
4400                 }
4401
4402                 chipio_set_stream_control(codec, 0x03, 1);
4403                 chipio_set_stream_control(codec, 0x04, 1);
4404                 break;
4405         case FRONT_MIC:
4406                 switch (spec->quirk) {
4407                 case QUIRK_SBZ:
4408                 case QUIRK_R3D:
4409                         ca0132_mmio_gpio_set(codec, 0, true);
4410                         ca0132_mmio_gpio_set(codec, 5, false);
4411                         tmp = FLOAT_THREE;
4412                         break;
4413                 case QUIRK_R3DI:
4414                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4415                         tmp = FLOAT_ONE;
4416                         break;
4417                 default:
4418                         tmp = FLOAT_ONE;
4419                         break;
4420                 }
4421
4422                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4423                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4424                 if (spec->quirk == QUIRK_R3DI)
4425                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4426
4427                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4428
4429                 chipio_set_stream_control(codec, 0x03, 1);
4430                 chipio_set_stream_control(codec, 0x04, 1);
4431
4432                 if (spec->quirk == QUIRK_SBZ) {
4433                         chipio_write(codec, 0x18B098, 0x0000000C);
4434                         chipio_write(codec, 0x18B09C, 0x000000CC);
4435                 }
4436                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4437                 break;
4438         }
4439         ca0132_cvoice_switch_set(codec);
4440
4441         snd_hda_power_down_pm(codec);
4442         return 0;
4443
4444 }
4445
4446 /*
4447  * Check if VNODE settings take effect immediately.
4448  */
4449 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4450                                      hda_nid_t vnid,
4451                                      hda_nid_t *shared_nid)
4452 {
4453         struct ca0132_spec *spec = codec->spec;
4454         hda_nid_t nid;
4455
4456         switch (vnid) {
4457         case VNID_SPK:
4458                 nid = spec->shared_out_nid;
4459                 break;
4460         case VNID_MIC:
4461                 nid = spec->shared_mic_nid;
4462                 break;
4463         default:
4464                 return false;
4465         }
4466
4467         if (shared_nid)
4468                 *shared_nid = nid;
4469
4470         return true;
4471 }
4472
4473 /*
4474 * The following functions are control change helpers.
4475 * They return 0 if no changed.  Return 1 if changed.
4476 */
4477 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4478 {
4479         struct ca0132_spec *spec = codec->spec;
4480         unsigned int tmp;
4481
4482         /* based on CrystalVoice state to enable VoiceFX. */
4483         if (enable) {
4484                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4485                         FLOAT_ONE : FLOAT_ZERO;
4486         } else {
4487                 tmp = FLOAT_ZERO;
4488         }
4489
4490         dspio_set_uint_param(codec, ca0132_voicefx.mid,
4491                              ca0132_voicefx.reqs[0], tmp);
4492
4493         return 1;
4494 }
4495
4496 /*
4497  * Set the effects parameters
4498  */
4499 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4500 {
4501         struct ca0132_spec *spec = codec->spec;
4502         unsigned int on, tmp;
4503         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4504         int err = 0;
4505         int idx = nid - EFFECT_START_NID;
4506
4507         if ((idx < 0) || (idx >= num_fx))
4508                 return 0; /* no changed */
4509
4510         /* for out effect, qualify with PE */
4511         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4512                 /* if PE if off, turn off out effects. */
4513                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4514                         val = 0;
4515         }
4516
4517         /* for in effect, qualify with CrystalVoice */
4518         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4519                 /* if CrystalVoice if off, turn off in effects. */
4520                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4521                         val = 0;
4522
4523                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4524                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4525                         val = 0;
4526
4527                 /* If Voice Focus on SBZ, set to two channel. */
4528                 if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio)
4529                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4530                         if (spec->effects_switch[CRYSTAL_VOICE -
4531                                                  EFFECT_START_NID]) {
4532
4533                                 if (spec->effects_switch[VOICE_FOCUS -
4534                                                          EFFECT_START_NID]) {
4535                                         tmp = FLOAT_TWO;
4536                                         val = 1;
4537                                 } else
4538                                         tmp = FLOAT_ONE;
4539
4540                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4541                         }
4542                 }
4543                 /*
4544                  * For SBZ noise reduction, there's an extra command
4545                  * to module ID 0x47. No clue why.
4546                  */
4547                 if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio)
4548                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4549                         if (spec->effects_switch[CRYSTAL_VOICE -
4550                                                  EFFECT_START_NID]) {
4551                                 if (spec->effects_switch[NOISE_REDUCTION -
4552                                                          EFFECT_START_NID])
4553                                         tmp = FLOAT_ONE;
4554                                 else
4555                                         tmp = FLOAT_ZERO;
4556                         } else
4557                                 tmp = FLOAT_ZERO;
4558
4559                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4560                 }
4561
4562                 /* If rear line in disable effects. */
4563                 if (spec->use_alt_functions &&
4564                                 spec->in_enum_val == REAR_LINE_IN)
4565                         val = 0;
4566         }
4567
4568         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4569                     nid, val);
4570
4571         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4572         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4573                                    ca0132_effects[idx].reqs[0], on);
4574
4575         if (err < 0)
4576                 return 0; /* no changed */
4577
4578         return 1;
4579 }
4580
4581 /*
4582  * Turn on/off Playback Enhancements
4583  */
4584 static int ca0132_pe_switch_set(struct hda_codec *codec)
4585 {
4586         struct ca0132_spec *spec = codec->spec;
4587         hda_nid_t nid;
4588         int i, ret = 0;
4589
4590         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4591                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4592
4593         if (spec->use_alt_functions)
4594                 ca0132_alt_select_out(codec);
4595
4596         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4597         nid = OUT_EFFECT_START_NID;
4598         /* PE affects all out effects */
4599         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4600                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4601
4602         return ret;
4603 }
4604
4605 /* Check if Mic1 is streaming, if so, stop streaming */
4606 static int stop_mic1(struct hda_codec *codec)
4607 {
4608         struct ca0132_spec *spec = codec->spec;
4609         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4610                                                  AC_VERB_GET_CONV, 0);
4611         if (oldval != 0)
4612                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4613                                     AC_VERB_SET_CHANNEL_STREAMID,
4614                                     0);
4615         return oldval;
4616 }
4617
4618 /* Resume Mic1 streaming if it was stopped. */
4619 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4620 {
4621         struct ca0132_spec *spec = codec->spec;
4622         /* Restore the previous stream and channel */
4623         if (oldval != 0)
4624                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4625                                     AC_VERB_SET_CHANNEL_STREAMID,
4626                                     oldval);
4627 }
4628
4629 /*
4630  * Turn on/off CrystalVoice
4631  */
4632 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4633 {
4634         struct ca0132_spec *spec = codec->spec;
4635         hda_nid_t nid;
4636         int i, ret = 0;
4637         unsigned int oldval;
4638
4639         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4640                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4641
4642         i = IN_EFFECT_START_NID - EFFECT_START_NID;
4643         nid = IN_EFFECT_START_NID;
4644         /* CrystalVoice affects all in effects */
4645         for (; nid < IN_EFFECT_END_NID; nid++, i++)
4646                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4647
4648         /* including VoiceFX */
4649         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4650
4651         /* set correct vipsource */
4652         oldval = stop_mic1(codec);
4653         if (spec->use_alt_functions)
4654                 ret |= ca0132_alt_set_vipsource(codec, 1);
4655         else
4656                 ret |= ca0132_set_vipsource(codec, 1);
4657         resume_mic1(codec, oldval);
4658         return ret;
4659 }
4660
4661 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4662 {
4663         struct ca0132_spec *spec = codec->spec;
4664         int ret = 0;
4665
4666         if (val) /* on */
4667                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4668                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4669         else /* off */
4670                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4671                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4672
4673         return ret;
4674 }
4675
4676 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4677 {
4678         struct ca0132_spec *spec = codec->spec;
4679         int ret = 0;
4680
4681         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4682                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4683         return ret;
4684 }
4685
4686 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4687                                 struct snd_ctl_elem_value *ucontrol)
4688 {
4689         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4690         hda_nid_t nid = get_amp_nid(kcontrol);
4691         hda_nid_t shared_nid = 0;
4692         bool effective;
4693         int ret = 0;
4694         struct ca0132_spec *spec = codec->spec;
4695         int auto_jack;
4696
4697         if (nid == VNID_HP_SEL) {
4698                 auto_jack =
4699                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4700                 if (!auto_jack) {
4701                         if (spec->use_alt_functions)
4702                                 ca0132_alt_select_out(codec);
4703                         else
4704                                 ca0132_select_out(codec);
4705                 }
4706                 return 1;
4707         }
4708
4709         if (nid == VNID_AMIC1_SEL) {
4710                 auto_jack =
4711                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4712                 if (!auto_jack)
4713                         ca0132_select_mic(codec);
4714                 return 1;
4715         }
4716
4717         if (nid == VNID_HP_ASEL) {
4718                 if (spec->use_alt_functions)
4719                         ca0132_alt_select_out(codec);
4720                 else
4721                         ca0132_select_out(codec);
4722                 return 1;
4723         }
4724
4725         if (nid == VNID_AMIC1_ASEL) {
4726                 ca0132_select_mic(codec);
4727                 return 1;
4728         }
4729
4730         /* if effective conditions, then update hw immediately. */
4731         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4732         if (effective) {
4733                 int dir = get_amp_direction(kcontrol);
4734                 int ch = get_amp_channels(kcontrol);
4735                 unsigned long pval;
4736
4737                 mutex_lock(&codec->control_mutex);
4738                 pval = kcontrol->private_value;
4739                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4740                                                                 0, dir);
4741                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4742                 kcontrol->private_value = pval;
4743                 mutex_unlock(&codec->control_mutex);
4744         }
4745
4746         return ret;
4747 }
4748 /* End of control change helpers. */
4749 /*
4750  * Below I've added controls to mess with the effect levels, I've only enabled
4751  * them on the Sound Blaster Z, but they would probably also work on the
4752  * Chromebook. I figured they were probably tuned specifically for it, and left
4753  * out for a reason.
4754  */
4755
4756 /* Sets DSP effect level from the sliders above the controls */
4757 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4758                           const unsigned int *lookup, int idx)
4759 {
4760         int i = 0;
4761         unsigned int y;
4762         /*
4763          * For X_BASS, req 2 is actually crossover freq instead of
4764          * effect level
4765          */
4766         if (nid == X_BASS)
4767                 y = 2;
4768         else
4769                 y = 1;
4770
4771         snd_hda_power_up(codec);
4772         if (nid == XBASS_XOVER) {
4773                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4774                         if (ca0132_effects[i].nid == X_BASS)
4775                                 break;
4776
4777                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4778                                 ca0132_effects[i].reqs[1],
4779                                 &(lookup[idx - 1]), sizeof(unsigned int));
4780         } else {
4781                 /* Find the actual effect structure */
4782                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4783                         if (nid == ca0132_effects[i].nid)
4784                                 break;
4785
4786                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4787                                 ca0132_effects[i].reqs[y],
4788                                 &(lookup[idx]), sizeof(unsigned int));
4789         }
4790
4791         snd_hda_power_down(codec);
4792
4793         return 0;
4794 }
4795
4796 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4797                           struct snd_ctl_elem_value *ucontrol)
4798 {
4799         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4800         struct ca0132_spec *spec = codec->spec;
4801         long *valp = ucontrol->value.integer.value;
4802
4803         *valp = spec->xbass_xover_freq;
4804         return 0;
4805 }
4806
4807 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4808                           struct snd_ctl_elem_value *ucontrol)
4809 {
4810         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4811         struct ca0132_spec *spec = codec->spec;
4812         hda_nid_t nid = get_amp_nid(kcontrol);
4813         long *valp = ucontrol->value.integer.value;
4814         int idx = nid - OUT_EFFECT_START_NID;
4815
4816         *valp = spec->fx_ctl_val[idx];
4817         return 0;
4818 }
4819
4820 /*
4821  * The X-bass crossover starts at 10hz, so the min is 1. The
4822  * frequency is set in multiples of 10.
4823  */
4824 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4825                 struct snd_ctl_elem_info *uinfo)
4826 {
4827         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4828         uinfo->count = 1;
4829         uinfo->value.integer.min = 1;
4830         uinfo->value.integer.max = 100;
4831         uinfo->value.integer.step = 1;
4832
4833         return 0;
4834 }
4835
4836 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4837                 struct snd_ctl_elem_info *uinfo)
4838 {
4839         int chs = get_amp_channels(kcontrol);
4840
4841         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4842         uinfo->count = chs == 3 ? 2 : 1;
4843         uinfo->value.integer.min = 0;
4844         uinfo->value.integer.max = 100;
4845         uinfo->value.integer.step = 1;
4846
4847         return 0;
4848 }
4849
4850 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4851                                 struct snd_ctl_elem_value *ucontrol)
4852 {
4853         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4854         struct ca0132_spec *spec = codec->spec;
4855         hda_nid_t nid = get_amp_nid(kcontrol);
4856         long *valp = ucontrol->value.integer.value;
4857         int idx;
4858
4859         /* any change? */
4860         if (spec->xbass_xover_freq == *valp)
4861                 return 0;
4862
4863         spec->xbass_xover_freq = *valp;
4864
4865         idx = *valp;
4866         ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4867
4868         return 0;
4869 }
4870
4871 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4872                                 struct snd_ctl_elem_value *ucontrol)
4873 {
4874         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4875         struct ca0132_spec *spec = codec->spec;
4876         hda_nid_t nid = get_amp_nid(kcontrol);
4877         long *valp = ucontrol->value.integer.value;
4878         int idx;
4879
4880         idx = nid - EFFECT_START_NID;
4881         /* any change? */
4882         if (spec->fx_ctl_val[idx] == *valp)
4883                 return 0;
4884
4885         spec->fx_ctl_val[idx] = *valp;
4886
4887         idx = *valp;
4888         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4889
4890         return 0;
4891 }
4892
4893
4894 /*
4895  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4896  * only has off or full 30 dB, and didn't like making a volume slider that has
4897  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4898  */
4899 #define MIC_BOOST_NUM_OF_STEPS 4
4900 #define MIC_BOOST_ENUM_MAX_STRLEN 10
4901
4902 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4903                                  struct snd_ctl_elem_info *uinfo)
4904 {
4905         char *sfx = "dB";
4906         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4907
4908         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4909         uinfo->count = 1;
4910         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4911         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4912                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4913         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4914         strcpy(uinfo->value.enumerated.name, namestr);
4915         return 0;
4916 }
4917
4918 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4919                                 struct snd_ctl_elem_value *ucontrol)
4920 {
4921         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4922         struct ca0132_spec *spec = codec->spec;
4923
4924         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4925         return 0;
4926 }
4927
4928 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4929                                 struct snd_ctl_elem_value *ucontrol)
4930 {
4931         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4932         struct ca0132_spec *spec = codec->spec;
4933         int sel = ucontrol->value.enumerated.item[0];
4934         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4935
4936         if (sel >= items)
4937                 return 0;
4938
4939         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4940                     sel);
4941
4942         spec->mic_boost_enum_val = sel;
4943
4944         if (spec->in_enum_val != REAR_LINE_IN)
4945                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4946
4947         return 1;
4948 }
4949
4950
4951 /*
4952  * Input Select Control for alternative ca0132 codecs. This exists because
4953  * front microphone has no auto-detect, and we need a way to set the rear
4954  * as line-in
4955  */
4956 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4957                                  struct snd_ctl_elem_info *uinfo)
4958 {
4959         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4960         uinfo->count = 1;
4961         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4962         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4963                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4964         strcpy(uinfo->value.enumerated.name,
4965                         in_src_str[uinfo->value.enumerated.item]);
4966         return 0;
4967 }
4968
4969 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4970                                 struct snd_ctl_elem_value *ucontrol)
4971 {
4972         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4973         struct ca0132_spec *spec = codec->spec;
4974
4975         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4976         return 0;
4977 }
4978
4979 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4980                                 struct snd_ctl_elem_value *ucontrol)
4981 {
4982         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4983         struct ca0132_spec *spec = codec->spec;
4984         int sel = ucontrol->value.enumerated.item[0];
4985         unsigned int items = IN_SRC_NUM_OF_INPUTS;
4986
4987         if (sel >= items)
4988                 return 0;
4989
4990         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4991                     sel, in_src_str[sel]);
4992
4993         spec->in_enum_val = sel;
4994
4995         ca0132_alt_select_in(codec);
4996
4997         return 1;
4998 }
4999
5000 /* Sound Blaster Z Output Select Control */
5001 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5002                                  struct snd_ctl_elem_info *uinfo)
5003 {
5004         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5005         uinfo->count = 1;
5006         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5007         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5008                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5009         strcpy(uinfo->value.enumerated.name,
5010                         alt_out_presets[uinfo->value.enumerated.item].name);
5011         return 0;
5012 }
5013
5014 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5015                                 struct snd_ctl_elem_value *ucontrol)
5016 {
5017         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5018         struct ca0132_spec *spec = codec->spec;
5019
5020         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5021         return 0;
5022 }
5023
5024 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5025                                 struct snd_ctl_elem_value *ucontrol)
5026 {
5027         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5028         struct ca0132_spec *spec = codec->spec;
5029         int sel = ucontrol->value.enumerated.item[0];
5030         unsigned int items = NUM_OF_OUTPUTS;
5031         unsigned int auto_jack;
5032
5033         if (sel >= items)
5034                 return 0;
5035
5036         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5037                     sel, alt_out_presets[sel].name);
5038
5039         spec->out_enum_val = sel;
5040
5041         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5042
5043         if (!auto_jack)
5044                 ca0132_alt_select_out(codec);
5045
5046         return 1;
5047 }
5048
5049 /*
5050  * Smart Volume output setting control. Three different settings, Normal,
5051  * which takes the value from the smart volume slider. The two others, loud
5052  * and night, disregard the slider value and have uneditable values.
5053  */
5054 #define NUM_OF_SVM_SETTINGS 3
5055 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5056
5057 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5058                                  struct snd_ctl_elem_info *uinfo)
5059 {
5060         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5061         uinfo->count = 1;
5062         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5063         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5064                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5065         strcpy(uinfo->value.enumerated.name,
5066                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
5067         return 0;
5068 }
5069
5070 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5071                                 struct snd_ctl_elem_value *ucontrol)
5072 {
5073         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5074         struct ca0132_spec *spec = codec->spec;
5075
5076         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5077         return 0;
5078 }
5079
5080 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5081                                 struct snd_ctl_elem_value *ucontrol)
5082 {
5083         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5084         struct ca0132_spec *spec = codec->spec;
5085         int sel = ucontrol->value.enumerated.item[0];
5086         unsigned int items = NUM_OF_SVM_SETTINGS;
5087         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5088         unsigned int tmp;
5089
5090         if (sel >= items)
5091                 return 0;
5092
5093         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5094                     sel, out_svm_set_enum_str[sel]);
5095
5096         spec->smart_volume_setting = sel;
5097
5098         switch (sel) {
5099         case 0:
5100                 tmp = FLOAT_ZERO;
5101                 break;
5102         case 1:
5103                 tmp = FLOAT_ONE;
5104                 break;
5105         case 2:
5106                 tmp = FLOAT_TWO;
5107                 break;
5108         default:
5109                 tmp = FLOAT_ZERO;
5110                 break;
5111         }
5112         /* Req 2 is the Smart Volume Setting req. */
5113         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5114                         ca0132_effects[idx].reqs[2], tmp);
5115         return 1;
5116 }
5117
5118 /* Sound Blaster Z EQ preset controls */
5119 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5120                                  struct snd_ctl_elem_info *uinfo)
5121 {
5122         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5123
5124         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5125         uinfo->count = 1;
5126         uinfo->value.enumerated.items = items;
5127         if (uinfo->value.enumerated.item >= items)
5128                 uinfo->value.enumerated.item = items - 1;
5129         strcpy(uinfo->value.enumerated.name,
5130                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5131         return 0;
5132 }
5133
5134 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5135                                 struct snd_ctl_elem_value *ucontrol)
5136 {
5137         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5138         struct ca0132_spec *spec = codec->spec;
5139
5140         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5141         return 0;
5142 }
5143
5144 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5145                                 struct snd_ctl_elem_value *ucontrol)
5146 {
5147         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5148         struct ca0132_spec *spec = codec->spec;
5149         int i, err = 0;
5150         int sel = ucontrol->value.enumerated.item[0];
5151         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5152
5153         if (sel >= items)
5154                 return 0;
5155
5156         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5157                         ca0132_alt_eq_presets[sel].name);
5158         /*
5159          * Idx 0 is default.
5160          * Default needs to qualify with CrystalVoice state.
5161          */
5162         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5163                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5164                                 ca0132_alt_eq_enum.reqs[i],
5165                                 ca0132_alt_eq_presets[sel].vals[i]);
5166                 if (err < 0)
5167                         break;
5168         }
5169
5170         if (err >= 0)
5171                 spec->eq_preset_val = sel;
5172
5173         return 1;
5174 }
5175
5176 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5177                                  struct snd_ctl_elem_info *uinfo)
5178 {
5179         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5180
5181         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5182         uinfo->count = 1;
5183         uinfo->value.enumerated.items = items;
5184         if (uinfo->value.enumerated.item >= items)
5185                 uinfo->value.enumerated.item = items - 1;
5186         strcpy(uinfo->value.enumerated.name,
5187                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5188         return 0;
5189 }
5190
5191 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5192                                 struct snd_ctl_elem_value *ucontrol)
5193 {
5194         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5195         struct ca0132_spec *spec = codec->spec;
5196
5197         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5198         return 0;
5199 }
5200
5201 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5202                                 struct snd_ctl_elem_value *ucontrol)
5203 {
5204         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5205         struct ca0132_spec *spec = codec->spec;
5206         int i, err = 0;
5207         int sel = ucontrol->value.enumerated.item[0];
5208
5209         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5210                 return 0;
5211
5212         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5213                     sel, ca0132_voicefx_presets[sel].name);
5214
5215         /*
5216          * Idx 0 is default.
5217          * Default needs to qualify with CrystalVoice state.
5218          */
5219         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5220                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5221                                 ca0132_voicefx.reqs[i],
5222                                 ca0132_voicefx_presets[sel].vals[i]);
5223                 if (err < 0)
5224                         break;
5225         }
5226
5227         if (err >= 0) {
5228                 spec->voicefx_val = sel;
5229                 /* enable voice fx */
5230                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5231         }
5232
5233         return 1;
5234 }
5235
5236 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5237                                 struct snd_ctl_elem_value *ucontrol)
5238 {
5239         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5240         struct ca0132_spec *spec = codec->spec;
5241         hda_nid_t nid = get_amp_nid(kcontrol);
5242         int ch = get_amp_channels(kcontrol);
5243         long *valp = ucontrol->value.integer.value;
5244
5245         /* vnode */
5246         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5247                 if (ch & 1) {
5248                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5249                         valp++;
5250                 }
5251                 if (ch & 2) {
5252                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5253                         valp++;
5254                 }
5255                 return 0;
5256         }
5257
5258         /* effects, include PE and CrystalVoice */
5259         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5260                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5261                 return 0;
5262         }
5263
5264         /* mic boost */
5265         if (nid == spec->input_pins[0]) {
5266                 *valp = spec->cur_mic_boost;
5267                 return 0;
5268         }
5269
5270         return 0;
5271 }
5272
5273 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5274                              struct snd_ctl_elem_value *ucontrol)
5275 {
5276         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5277         struct ca0132_spec *spec = codec->spec;
5278         hda_nid_t nid = get_amp_nid(kcontrol);
5279         int ch = get_amp_channels(kcontrol);
5280         long *valp = ucontrol->value.integer.value;
5281         int changed = 1;
5282
5283         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5284                     nid, *valp);
5285
5286         snd_hda_power_up(codec);
5287         /* vnode */
5288         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5289                 if (ch & 1) {
5290                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5291                         valp++;
5292                 }
5293                 if (ch & 2) {
5294                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5295                         valp++;
5296                 }
5297                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5298                 goto exit;
5299         }
5300
5301         /* PE */
5302         if (nid == PLAY_ENHANCEMENT) {
5303                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5304                 changed = ca0132_pe_switch_set(codec);
5305                 goto exit;
5306         }
5307
5308         /* CrystalVoice */
5309         if (nid == CRYSTAL_VOICE) {
5310                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5311                 changed = ca0132_cvoice_switch_set(codec);
5312                 goto exit;
5313         }
5314
5315         /* out and in effects */
5316         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5317             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5318                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5319                 changed = ca0132_effects_set(codec, nid, *valp);
5320                 goto exit;
5321         }
5322
5323         /* mic boost */
5324         if (nid == spec->input_pins[0]) {
5325                 spec->cur_mic_boost = *valp;
5326                 if (spec->use_alt_functions) {
5327                         if (spec->in_enum_val != REAR_LINE_IN)
5328                                 changed = ca0132_mic_boost_set(codec, *valp);
5329                 } else {
5330                         /* Mic boost does not apply to Digital Mic */
5331                         if (spec->cur_mic_type != DIGITAL_MIC)
5332                                 changed = ca0132_mic_boost_set(codec, *valp);
5333                 }
5334
5335                 goto exit;
5336         }
5337
5338 exit:
5339         snd_hda_power_down(codec);
5340         return changed;
5341 }
5342
5343 /*
5344  * Volume related
5345  */
5346 /*
5347  * Sets the internal DSP decibel level to match the DAC for output, and the
5348  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5349  * all alternative codecs set DSP playback volume.
5350  */
5351 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5352 {
5353         struct ca0132_spec *spec = codec->spec;
5354         unsigned int dsp_dir;
5355         unsigned int lookup_val;
5356
5357         if (nid == VNID_SPK)
5358                 dsp_dir = DSP_VOL_OUT;
5359         else
5360                 dsp_dir = DSP_VOL_IN;
5361
5362         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5363
5364         dspio_set_uint_param(codec,
5365                 ca0132_alt_vol_ctls[dsp_dir].mid,
5366                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5367                 float_vol_db_lookup[lookup_val]);
5368
5369         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5370
5371         dspio_set_uint_param(codec,
5372                 ca0132_alt_vol_ctls[dsp_dir].mid,
5373                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5374                 float_vol_db_lookup[lookup_val]);
5375
5376         dspio_set_uint_param(codec,
5377                 ca0132_alt_vol_ctls[dsp_dir].mid,
5378                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5379 }
5380
5381 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5382                               struct snd_ctl_elem_info *uinfo)
5383 {
5384         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5385         struct ca0132_spec *spec = codec->spec;
5386         hda_nid_t nid = get_amp_nid(kcontrol);
5387         int ch = get_amp_channels(kcontrol);
5388         int dir = get_amp_direction(kcontrol);
5389         unsigned long pval;
5390         int err;
5391
5392         switch (nid) {
5393         case VNID_SPK:
5394                 /* follow shared_out info */
5395                 nid = spec->shared_out_nid;
5396                 mutex_lock(&codec->control_mutex);
5397                 pval = kcontrol->private_value;
5398                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5399                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5400                 kcontrol->private_value = pval;
5401                 mutex_unlock(&codec->control_mutex);
5402                 break;
5403         case VNID_MIC:
5404                 /* follow shared_mic info */
5405                 nid = spec->shared_mic_nid;
5406                 mutex_lock(&codec->control_mutex);
5407                 pval = kcontrol->private_value;
5408                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5409                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5410                 kcontrol->private_value = pval;
5411                 mutex_unlock(&codec->control_mutex);
5412                 break;
5413         default:
5414                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5415         }
5416         return err;
5417 }
5418
5419 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5420                                 struct snd_ctl_elem_value *ucontrol)
5421 {
5422         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5423         struct ca0132_spec *spec = codec->spec;
5424         hda_nid_t nid = get_amp_nid(kcontrol);
5425         int ch = get_amp_channels(kcontrol);
5426         long *valp = ucontrol->value.integer.value;
5427
5428         /* store the left and right volume */
5429         if (ch & 1) {
5430                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5431                 valp++;
5432         }
5433         if (ch & 2) {
5434                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5435                 valp++;
5436         }
5437         return 0;
5438 }
5439
5440 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5441                                 struct snd_ctl_elem_value *ucontrol)
5442 {
5443         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5444         struct ca0132_spec *spec = codec->spec;
5445         hda_nid_t nid = get_amp_nid(kcontrol);
5446         int ch = get_amp_channels(kcontrol);
5447         long *valp = ucontrol->value.integer.value;
5448         hda_nid_t shared_nid = 0;
5449         bool effective;
5450         int changed = 1;
5451
5452         /* store the left and right volume */
5453         if (ch & 1) {
5454                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5455                 valp++;
5456         }
5457         if (ch & 2) {
5458                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5459                 valp++;
5460         }
5461
5462         /* if effective conditions, then update hw immediately. */
5463         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5464         if (effective) {
5465                 int dir = get_amp_direction(kcontrol);
5466                 unsigned long pval;
5467
5468                 snd_hda_power_up(codec);
5469                 mutex_lock(&codec->control_mutex);
5470                 pval = kcontrol->private_value;
5471                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5472                                                                 0, dir);
5473                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5474                 kcontrol->private_value = pval;
5475                 mutex_unlock(&codec->control_mutex);
5476                 snd_hda_power_down(codec);
5477         }
5478
5479         return changed;
5480 }
5481
5482 /*
5483  * This function is the same as the one above, because using an if statement
5484  * inside of the above volume control for the DSP volume would cause too much
5485  * lag. This is a lot more smooth.
5486  */
5487 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5488                                 struct snd_ctl_elem_value *ucontrol)
5489 {
5490         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5491         struct ca0132_spec *spec = codec->spec;
5492         hda_nid_t nid = get_amp_nid(kcontrol);
5493         int ch = get_amp_channels(kcontrol);
5494         long *valp = ucontrol->value.integer.value;
5495         hda_nid_t vnid = 0;
5496         int changed = 1;
5497
5498         switch (nid) {
5499         case 0x02:
5500                 vnid = VNID_SPK;
5501                 break;
5502         case 0x07:
5503                 vnid = VNID_MIC;
5504                 break;
5505         }
5506
5507         /* store the left and right volume */
5508         if (ch & 1) {
5509                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5510                 valp++;
5511         }
5512         if (ch & 2) {
5513                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5514                 valp++;
5515         }
5516
5517         snd_hda_power_up(codec);
5518         ca0132_alt_dsp_volume_put(codec, vnid);
5519         mutex_lock(&codec->control_mutex);
5520         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5521         mutex_unlock(&codec->control_mutex);
5522         snd_hda_power_down(codec);
5523
5524         return changed;
5525 }
5526
5527 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5528                              unsigned int size, unsigned int __user *tlv)
5529 {
5530         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5531         struct ca0132_spec *spec = codec->spec;
5532         hda_nid_t nid = get_amp_nid(kcontrol);
5533         int ch = get_amp_channels(kcontrol);
5534         int dir = get_amp_direction(kcontrol);
5535         unsigned long pval;
5536         int err;
5537
5538         switch (nid) {
5539         case VNID_SPK:
5540                 /* follow shared_out tlv */
5541                 nid = spec->shared_out_nid;
5542                 mutex_lock(&codec->control_mutex);
5543                 pval = kcontrol->private_value;
5544                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5545                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5546                 kcontrol->private_value = pval;
5547                 mutex_unlock(&codec->control_mutex);
5548                 break;
5549         case VNID_MIC:
5550                 /* follow shared_mic tlv */
5551                 nid = spec->shared_mic_nid;
5552                 mutex_lock(&codec->control_mutex);
5553                 pval = kcontrol->private_value;
5554                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5555                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5556                 kcontrol->private_value = pval;
5557                 mutex_unlock(&codec->control_mutex);
5558                 break;
5559         default:
5560                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5561         }
5562         return err;
5563 }
5564
5565 /* Add volume slider control for effect level */
5566 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5567                                         const char *pfx, int dir)
5568 {
5569         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5570         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5571         struct snd_kcontrol_new knew =
5572                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5573
5574         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5575
5576         knew.tlv.c = NULL;
5577
5578         switch (nid) {
5579         case XBASS_XOVER:
5580                 knew.info = ca0132_alt_xbass_xover_slider_info;
5581                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5582                 knew.put = ca0132_alt_xbass_xover_slider_put;
5583                 break;
5584         default:
5585                 knew.info = ca0132_alt_effect_slider_info;
5586                 knew.get = ca0132_alt_slider_ctl_get;
5587                 knew.put = ca0132_alt_effect_slider_put;
5588                 knew.private_value =
5589                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5590                 break;
5591         }
5592
5593         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5594 }
5595
5596 /*
5597  * Added FX: prefix for the alternative codecs, because otherwise the surround
5598  * effect would conflict with the Surround sound volume control. Also seems more
5599  * clear as to what the switches do. Left alone for others.
5600  */
5601 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5602                          const char *pfx, int dir)
5603 {
5604         struct ca0132_spec *spec = codec->spec;
5605         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5606         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5607         struct snd_kcontrol_new knew =
5608                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5609         /* If using alt_controls, add FX: prefix. But, don't add FX:
5610          * prefix to OutFX or InFX enable controls.
5611          */
5612         if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5613                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5614         else
5615                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5616
5617         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5618 }
5619
5620 static int add_voicefx(struct hda_codec *codec)
5621 {
5622         struct snd_kcontrol_new knew =
5623                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5624                                     VOICEFX, 1, 0, HDA_INPUT);
5625         knew.info = ca0132_voicefx_info;
5626         knew.get = ca0132_voicefx_get;
5627         knew.put = ca0132_voicefx_put;
5628         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5629 }
5630
5631 /* Create the EQ Preset control */
5632 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5633 {
5634         struct snd_kcontrol_new knew =
5635                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5636                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5637         knew.info = ca0132_alt_eq_preset_info;
5638         knew.get = ca0132_alt_eq_preset_get;
5639         knew.put = ca0132_alt_eq_preset_put;
5640         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5641                                 snd_ctl_new1(&knew, codec));
5642 }
5643
5644 /*
5645  * Add enumerated control for the three different settings of the smart volume
5646  * output effect. Normal just uses the slider value, and loud and night are
5647  * their own things that ignore that value.
5648  */
5649 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5650 {
5651         struct snd_kcontrol_new knew =
5652                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5653                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5654         knew.info = ca0132_alt_svm_setting_info;
5655         knew.get = ca0132_alt_svm_setting_get;
5656         knew.put = ca0132_alt_svm_setting_put;
5657         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5658                                 snd_ctl_new1(&knew, codec));
5659
5660 }
5661
5662 /*
5663  * Create an Output Select enumerated control for codecs with surround
5664  * out capabilities.
5665  */
5666 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5667 {
5668         struct snd_kcontrol_new knew =
5669                 HDA_CODEC_MUTE_MONO("Output Select",
5670                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5671         knew.info = ca0132_alt_output_select_get_info;
5672         knew.get = ca0132_alt_output_select_get;
5673         knew.put = ca0132_alt_output_select_put;
5674         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5675                                 snd_ctl_new1(&knew, codec));
5676 }
5677
5678 /*
5679  * Create an Input Source enumerated control for the alternate ca0132 codecs
5680  * because the front microphone has no auto-detect, and Line-in has to be set
5681  * somehow.
5682  */
5683 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5684 {
5685         struct snd_kcontrol_new knew =
5686                 HDA_CODEC_MUTE_MONO("Input Source",
5687                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5688         knew.info = ca0132_alt_input_source_info;
5689         knew.get = ca0132_alt_input_source_get;
5690         knew.put = ca0132_alt_input_source_put;
5691         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5692                                 snd_ctl_new1(&knew, codec));
5693 }
5694
5695 /*
5696  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5697  * more control than the original mic boost, which is either full 30dB or off.
5698  */
5699 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5700 {
5701         struct snd_kcontrol_new knew =
5702                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5703                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5704         knew.info = ca0132_alt_mic_boost_info;
5705         knew.get = ca0132_alt_mic_boost_get;
5706         knew.put = ca0132_alt_mic_boost_put;
5707         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5708                                 snd_ctl_new1(&knew, codec));
5709
5710 }
5711
5712 /*
5713  * Need to create slave controls for the alternate codecs that have surround
5714  * capabilities.
5715  */
5716 static const char * const ca0132_alt_slave_pfxs[] = {
5717         "Front", "Surround", "Center", "LFE", NULL,
5718 };
5719
5720 /*
5721  * Also need special channel map, because the default one is incorrect.
5722  * I think this has to do with the pin for rear surround being 0x11,
5723  * and the center/lfe being 0x10. Usually the pin order is the opposite.
5724  */
5725 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5726         { .channels = 2,
5727           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5728         { .channels = 4,
5729           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5730                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5731         { .channels = 6,
5732           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5733                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5734                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5735         { }
5736 };
5737
5738 /* Add the correct chmap for streams with 6 channels. */
5739 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5740 {
5741         int err = 0;
5742         struct hda_pcm *pcm;
5743
5744         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5745                 struct hda_pcm_stream *hinfo =
5746                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5747                 struct snd_pcm_chmap *chmap;
5748                 const struct snd_pcm_chmap_elem *elem;
5749
5750                 elem = ca0132_alt_chmaps;
5751                 if (hinfo->channels_max == 6) {
5752                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
5753                                         SNDRV_PCM_STREAM_PLAYBACK,
5754                                         elem, hinfo->channels_max, 0, &chmap);
5755                         if (err < 0)
5756                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5757                 }
5758         }
5759 }
5760
5761 /*
5762  * When changing Node IDs for Mixer Controls below, make sure to update
5763  * Node IDs in ca0132_config() as well.
5764  */
5765 static const struct snd_kcontrol_new ca0132_mixer[] = {
5766         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5767         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5768         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5769         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5770         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5771         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5772         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5773         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5774         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5775                                0x12, 1, HDA_INPUT),
5776         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5777                                VNID_HP_SEL, 1, HDA_OUTPUT),
5778         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5779                                VNID_AMIC1_SEL, 1, HDA_INPUT),
5780         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5781                                VNID_HP_ASEL, 1, HDA_OUTPUT),
5782         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5783                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
5784         { } /* end */
5785 };
5786
5787 /*
5788  * Desktop specific control mixer. Removes auto-detect for mic, and adds
5789  * surround controls. Also sets both the Front Playback and Capture Volume
5790  * controls to alt so they set the DSP's decibel level.
5791  */
5792 static const struct snd_kcontrol_new desktop_mixer[] = {
5793         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5794         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5795         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5796         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5797         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5798         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5799         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5800         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5801         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5802         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5803         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5804         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5805         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5806                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5807         { } /* end */
5808 };
5809
5810 /*
5811  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5812  * because it doesn't set decibel levels for the DSP for capture.
5813  */
5814 static const struct snd_kcontrol_new r3di_mixer[] = {
5815         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5816         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5817         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5818         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5819         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5820         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5821         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5822         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5823         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5824         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5825         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5826         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5827         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5828                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5829         { } /* end */
5830 };
5831
5832 static int ca0132_build_controls(struct hda_codec *codec)
5833 {
5834         struct ca0132_spec *spec = codec->spec;
5835         int i, num_fx, num_sliders;
5836         int err = 0;
5837
5838         /* Add Mixer controls */
5839         for (i = 0; i < spec->num_mixers; i++) {
5840                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5841                 if (err < 0)
5842                         return err;
5843         }
5844         /* Setup vmaster with surround slaves for desktop ca0132 devices */
5845         if (spec->use_alt_functions) {
5846                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5847                                         spec->tlv);
5848                 snd_hda_add_vmaster(codec, "Master Playback Volume",
5849                                         spec->tlv, ca0132_alt_slave_pfxs,
5850                                         "Playback Volume");
5851                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5852                                             NULL, ca0132_alt_slave_pfxs,
5853                                             "Playback Switch",
5854                                             true, &spec->vmaster_mute.sw_kctl);
5855
5856         }
5857
5858         /* Add in and out effects controls.
5859          * VoiceFX, PE and CrystalVoice are added separately.
5860          */
5861         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5862         for (i = 0; i < num_fx; i++) {
5863                 /* Desktop cards break if Echo Cancellation is used. */
5864                 if (spec->use_pci_mmio) {
5865                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5866                                                 OUT_EFFECTS_COUNT))
5867                                 continue;
5868                 }
5869
5870                 err = add_fx_switch(codec, ca0132_effects[i].nid,
5871                                     ca0132_effects[i].name,
5872                                     ca0132_effects[i].direct);
5873                 if (err < 0)
5874                         return err;
5875         }
5876         /*
5877          * If codec has use_alt_controls set to true, add effect level sliders,
5878          * EQ presets, and Smart Volume presets. Also, change names to add FX
5879          * prefix, and change PlayEnhancement and CrystalVoice to match.
5880          */
5881         if (spec->use_alt_controls) {
5882                 ca0132_alt_add_svm_enum(codec);
5883                 add_ca0132_alt_eq_presets(codec);
5884                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5885                                         "Enable OutFX", 0);
5886                 if (err < 0)
5887                         return err;
5888
5889                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5890                                         "Enable InFX", 1);
5891                 if (err < 0)
5892                         return err;
5893
5894                 num_sliders = OUT_EFFECTS_COUNT - 1;
5895                 for (i = 0; i < num_sliders; i++) {
5896                         err = ca0132_alt_add_effect_slider(codec,
5897                                             ca0132_effects[i].nid,
5898                                             ca0132_effects[i].name,
5899                                             ca0132_effects[i].direct);
5900                         if (err < 0)
5901                                 return err;
5902                 }
5903
5904                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5905                                         "X-Bass Crossover", EFX_DIR_OUT);
5906
5907                 if (err < 0)
5908                         return err;
5909         } else {
5910                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5911                                         "PlayEnhancement", 0);
5912                 if (err < 0)
5913                         return err;
5914
5915                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5916                                         "CrystalVoice", 1);
5917                 if (err < 0)
5918                         return err;
5919         }
5920         add_voicefx(codec);
5921
5922         /*
5923          * If the codec uses alt_functions, you need the enumerated controls
5924          * to select the new outputs and inputs, plus add the new mic boost
5925          * setting control.
5926          */
5927         if (spec->use_alt_functions) {
5928                 ca0132_alt_add_output_enum(codec);
5929                 ca0132_alt_add_input_enum(codec);
5930                 ca0132_alt_add_mic_boost_enum(codec);
5931         }
5932 #ifdef ENABLE_TUNING_CONTROLS
5933         add_tuning_ctls(codec);
5934 #endif
5935
5936         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5937         if (err < 0)
5938                 return err;
5939
5940         if (spec->dig_out) {
5941                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5942                                                     spec->dig_out);
5943                 if (err < 0)
5944                         return err;
5945                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5946                 if (err < 0)
5947                         return err;
5948                 /* spec->multiout.share_spdif = 1; */
5949         }
5950
5951         if (spec->dig_in) {
5952                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5953                 if (err < 0)
5954                         return err;
5955         }
5956
5957         if (spec->use_alt_functions)
5958                 ca0132_alt_add_chmap_ctls(codec);
5959
5960         return 0;
5961 }
5962
5963 /*
5964  * PCM
5965  */
5966 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5967         .substreams = 1,
5968         .channels_min = 2,
5969         .channels_max = 6,
5970         .ops = {
5971                 .prepare = ca0132_playback_pcm_prepare,
5972                 .cleanup = ca0132_playback_pcm_cleanup,
5973                 .get_delay = ca0132_playback_pcm_delay,
5974         },
5975 };
5976
5977 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5978         .substreams = 1,
5979         .channels_min = 2,
5980         .channels_max = 2,
5981         .ops = {
5982                 .prepare = ca0132_capture_pcm_prepare,
5983                 .cleanup = ca0132_capture_pcm_cleanup,
5984                 .get_delay = ca0132_capture_pcm_delay,
5985         },
5986 };
5987
5988 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5989         .substreams = 1,
5990         .channels_min = 2,
5991         .channels_max = 2,
5992         .ops = {
5993                 .open = ca0132_dig_playback_pcm_open,
5994                 .close = ca0132_dig_playback_pcm_close,
5995                 .prepare = ca0132_dig_playback_pcm_prepare,
5996                 .cleanup = ca0132_dig_playback_pcm_cleanup
5997         },
5998 };
5999
6000 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
6001         .substreams = 1,
6002         .channels_min = 2,
6003         .channels_max = 2,
6004 };
6005
6006 static int ca0132_build_pcms(struct hda_codec *codec)
6007 {
6008         struct ca0132_spec *spec = codec->spec;
6009         struct hda_pcm *info;
6010
6011         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6012         if (!info)
6013                 return -ENOMEM;
6014         if (spec->use_alt_functions) {
6015                 info->own_chmap = true;
6016                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6017                         = ca0132_alt_chmaps;
6018         }
6019         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6020         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6021         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6022                 spec->multiout.max_channels;
6023         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6024         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6025         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6026
6027         /* With the DSP enabled, desktops don't use this ADC. */
6028         if (!spec->use_alt_functions) {
6029                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6030                 if (!info)
6031                         return -ENOMEM;
6032                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6033                         ca0132_pcm_analog_capture;
6034                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6035                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6036         }
6037
6038         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6039         if (!info)
6040                 return -ENOMEM;
6041         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6042         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6043         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6044
6045         if (!spec->dig_out && !spec->dig_in)
6046                 return 0;
6047
6048         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6049         if (!info)
6050                 return -ENOMEM;
6051         info->pcm_type = HDA_PCM_TYPE_SPDIF;
6052         if (spec->dig_out) {
6053                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6054                         ca0132_pcm_digital_playback;
6055                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6056         }
6057         if (spec->dig_in) {
6058                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6059                         ca0132_pcm_digital_capture;
6060                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6061         }
6062
6063         return 0;
6064 }
6065
6066 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6067 {
6068         if (pin) {
6069                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6070                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6071                         snd_hda_codec_write(codec, pin, 0,
6072                                             AC_VERB_SET_AMP_GAIN_MUTE,
6073                                             AMP_OUT_UNMUTE);
6074         }
6075         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6076                 snd_hda_codec_write(codec, dac, 0,
6077                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6078 }
6079
6080 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6081 {
6082         if (pin) {
6083                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6084                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6085                         snd_hda_codec_write(codec, pin, 0,
6086                                             AC_VERB_SET_AMP_GAIN_MUTE,
6087                                             AMP_IN_UNMUTE(0));
6088         }
6089         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6090                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6091                                     AMP_IN_UNMUTE(0));
6092
6093                 /* init to 0 dB and unmute. */
6094                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6095                                          HDA_AMP_VOLMASK, 0x5a);
6096                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6097                                          HDA_AMP_MUTE, 0);
6098         }
6099 }
6100
6101 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6102 {
6103         unsigned int caps;
6104
6105         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6106                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6107         snd_hda_override_amp_caps(codec, nid, dir, caps);
6108 }
6109
6110 /*
6111  * Switch between Digital built-in mic and analog mic.
6112  */
6113 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6114 {
6115         struct ca0132_spec *spec = codec->spec;
6116         unsigned int tmp;
6117         u8 val;
6118         unsigned int oldval;
6119
6120         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6121
6122         oldval = stop_mic1(codec);
6123         ca0132_set_vipsource(codec, 0);
6124         if (enable) {
6125                 /* set DMic input as 2-ch */
6126                 tmp = FLOAT_TWO;
6127                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6128
6129                 val = spec->dmic_ctl;
6130                 val |= 0x80;
6131                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6132                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6133
6134                 if (!(spec->dmic_ctl & 0x20))
6135                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6136         } else {
6137                 /* set AMic input as mono */
6138                 tmp = FLOAT_ONE;
6139                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6140
6141                 val = spec->dmic_ctl;
6142                 /* clear bit7 and bit5 to disable dmic */
6143                 val &= 0x5f;
6144                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6145                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6146
6147                 if (!(spec->dmic_ctl & 0x20))
6148                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6149         }
6150         ca0132_set_vipsource(codec, 1);
6151         resume_mic1(codec, oldval);
6152 }
6153
6154 /*
6155  * Initialization for Digital Mic.
6156  */
6157 static void ca0132_init_dmic(struct hda_codec *codec)
6158 {
6159         struct ca0132_spec *spec = codec->spec;
6160         u8 val;
6161
6162         /* Setup Digital Mic here, but don't enable.
6163          * Enable based on jack detect.
6164          */
6165
6166         /* MCLK uses MPIO1, set to enable.
6167          * Bit 2-0: MPIO select
6168          * Bit   3: set to disable
6169          * Bit 7-4: reserved
6170          */
6171         val = 0x01;
6172         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6173                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6174
6175         /* Data1 uses MPIO3. Data2 not use
6176          * Bit 2-0: Data1 MPIO select
6177          * Bit   3: set disable Data1
6178          * Bit 6-4: Data2 MPIO select
6179          * Bit   7: set disable Data2
6180          */
6181         val = 0x83;
6182         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6183                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
6184
6185         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6186          * Bit 3-0: Channel mask
6187          * Bit   4: set for 48KHz, clear for 32KHz
6188          * Bit   5: mode
6189          * Bit   6: set to select Data2, clear for Data1
6190          * Bit   7: set to enable DMic, clear for AMic
6191          */
6192         if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6193                 val = 0x33;
6194         else
6195                 val = 0x23;
6196         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6197         spec->dmic_ctl = val;
6198         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6199                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
6200 }
6201
6202 /*
6203  * Initialization for Analog Mic 2
6204  */
6205 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6206 {
6207         struct ca0132_spec *spec = codec->spec;
6208
6209         mutex_lock(&spec->chipio_mutex);
6210         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6211                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6212         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6213                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6214         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6215                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6216         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6217                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6218         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6219                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6220         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6221                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6222         mutex_unlock(&spec->chipio_mutex);
6223 }
6224
6225 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6226 {
6227         struct ca0132_spec *spec = codec->spec;
6228         int i;
6229
6230         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6231         snd_hda_codec_update_widgets(codec);
6232
6233         for (i = 0; i < spec->multiout.num_dacs; i++)
6234                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6235
6236         for (i = 0; i < spec->num_outputs; i++)
6237                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6238
6239         for (i = 0; i < spec->num_inputs; i++) {
6240                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6241                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6242         }
6243 }
6244
6245 /*
6246  * Recon3D r3d_setup_defaults sub functions.
6247  */
6248
6249 static void r3d_dsp_scp_startup(struct hda_codec *codec)
6250 {
6251         unsigned int tmp;
6252
6253         tmp = 0x00000000;
6254         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6255
6256         tmp = 0x00000001;
6257         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6258
6259         tmp = 0x00000004;
6260         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6261
6262         tmp = 0x00000005;
6263         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6264
6265         tmp = 0x00000000;
6266         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6267
6268 }
6269
6270 static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6271 {
6272         unsigned int tmp;
6273
6274         /* Mic 1 Setup */
6275         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6276         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6277         /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6278         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6279         tmp = FLOAT_ONE;
6280         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6281
6282         /* Mic 2 Setup, even though it isn't connected on SBZ */
6283         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6284         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6285         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6286         tmp = FLOAT_ZERO;
6287         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6288 }
6289
6290 /*
6291  * Initialize Sound Blaster Z analog microphones.
6292  */
6293 static void sbz_init_analog_mics(struct hda_codec *codec)
6294 {
6295         unsigned int tmp;
6296
6297         /* Mic 1 Setup */
6298         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6299         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6300         tmp = FLOAT_THREE;
6301         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6302
6303         /* Mic 2 Setup, even though it isn't connected on SBZ */
6304         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6305         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6306         tmp = FLOAT_ZERO;
6307         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6308
6309 }
6310
6311 /*
6312  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6313  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6314  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6315  * having an updated DAC, which changes the destination to that DAC.
6316  */
6317 static void sbz_connect_streams(struct hda_codec *codec)
6318 {
6319         struct ca0132_spec *spec = codec->spec;
6320
6321         mutex_lock(&spec->chipio_mutex);
6322
6323         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6324
6325         chipio_set_stream_channels(codec, 0x0C, 6);
6326         chipio_set_stream_control(codec, 0x0C, 1);
6327
6328         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6329         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6330
6331         /* Setup stream 0x14 with it's source and destination points */
6332         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6333         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6334         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6335         chipio_set_stream_channels(codec, 0x14, 2);
6336         chipio_set_stream_control(codec, 0x14, 1);
6337
6338         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6339
6340         mutex_unlock(&spec->chipio_mutex);
6341
6342 }
6343
6344 /*
6345  * Write data through ChipIO to setup proper stream destinations.
6346  * Not sure how it exactly works, but it seems to direct data
6347  * to different destinations. Example is f8 to c0, e0 to c0.
6348  * All I know is, if you don't set these, you get no sound.
6349  */
6350 static void sbz_chipio_startup_data(struct hda_codec *codec)
6351 {
6352         struct ca0132_spec *spec = codec->spec;
6353
6354         mutex_lock(&spec->chipio_mutex);
6355         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6356
6357         /* These control audio output */
6358         chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6359         chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6360         chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6361         chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6362         /* Signal to update I think */
6363         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6364
6365         chipio_set_stream_channels(codec, 0x0C, 6);
6366         chipio_set_stream_control(codec, 0x0C, 1);
6367         /* No clue what these control */
6368         chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6369         chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6370         chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6371         chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6372         chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6373         chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6374         chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6375         chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6376         chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6377         chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6378         chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6379         chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6380
6381         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6382
6383         codec_dbg(codec, "Startup Data exited, mutex released.\n");
6384         mutex_unlock(&spec->chipio_mutex);
6385 }
6386
6387 /*
6388  * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6389  * without a 0x20 source like normal.
6390  */
6391 static void sbz_dsp_scp_startup(struct hda_codec *codec)
6392 {
6393         unsigned int tmp;
6394
6395         tmp = 0x00000003;
6396         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6397
6398         tmp = 0x00000000;
6399         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6400
6401         tmp = 0x00000001;
6402         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6403
6404         tmp = 0x00000004;
6405         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6406
6407         tmp = 0x00000005;
6408         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6409
6410         tmp = 0x00000000;
6411         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6412
6413 }
6414
6415 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6416 {
6417         unsigned int tmp;
6418
6419         chipio_set_stream_control(codec, 0x03, 0);
6420         chipio_set_stream_control(codec, 0x04, 0);
6421
6422         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6423         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6424
6425         tmp = FLOAT_THREE;
6426         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6427
6428         chipio_set_stream_control(codec, 0x03, 1);
6429         chipio_set_stream_control(codec, 0x04, 1);
6430
6431         chipio_write(codec, 0x18b098, 0x0000000c);
6432         chipio_write(codec, 0x18b09C, 0x0000000c);
6433 }
6434
6435 /*
6436  * Setup default parameters for DSP
6437  */
6438 static void ca0132_setup_defaults(struct hda_codec *codec)
6439 {
6440         struct ca0132_spec *spec = codec->spec;
6441         unsigned int tmp;
6442         int num_fx;
6443         int idx, i;
6444
6445         if (spec->dsp_state != DSP_DOWNLOADED)
6446                 return;
6447
6448         /* out, in effects + voicefx */
6449         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6450         for (idx = 0; idx < num_fx; idx++) {
6451                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6452                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6453                                              ca0132_effects[idx].reqs[i],
6454                                              ca0132_effects[idx].def_vals[i]);
6455                 }
6456         }
6457
6458         /*remove DSP headroom*/
6459         tmp = FLOAT_ZERO;
6460         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6461
6462         /*set speaker EQ bypass attenuation*/
6463         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6464
6465         /* set AMic1 and AMic2 as mono mic */
6466         tmp = FLOAT_ONE;
6467         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6468         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6469
6470         /* set AMic1 as CrystalVoice input */
6471         tmp = FLOAT_ONE;
6472         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6473
6474         /* set WUH source */
6475         tmp = FLOAT_TWO;
6476         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6477 }
6478
6479 /*
6480  * Setup default parameters for Recon3D/Recon3Di DSP.
6481  */
6482
6483 static void r3d_setup_defaults(struct hda_codec *codec)
6484 {
6485         struct ca0132_spec *spec = codec->spec;
6486         unsigned int tmp;
6487         int num_fx;
6488         int idx, i;
6489
6490         if (spec->dsp_state != DSP_DOWNLOADED)
6491                 return;
6492
6493         r3d_dsp_scp_startup(codec);
6494
6495         r3d_dsp_initial_mic_setup(codec);
6496
6497         /*remove DSP headroom*/
6498         tmp = FLOAT_ZERO;
6499         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6500
6501         /* set WUH source */
6502         tmp = FLOAT_TWO;
6503         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6504         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6505
6506         /* Set speaker source? */
6507         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6508
6509         if (spec->quirk == QUIRK_R3DI)
6510                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6511
6512         /* Setup effect defaults */
6513         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6514         for (idx = 0; idx < num_fx; idx++) {
6515                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6516                         dspio_set_uint_param(codec,
6517                                         ca0132_effects[idx].mid,
6518                                         ca0132_effects[idx].reqs[i],
6519                                         ca0132_effects[idx].def_vals[i]);
6520                 }
6521         }
6522 }
6523
6524 /*
6525  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6526  * than the Chromebook setup.
6527  */
6528 static void sbz_setup_defaults(struct hda_codec *codec)
6529 {
6530         struct ca0132_spec *spec = codec->spec;
6531         unsigned int tmp, stream_format;
6532         int num_fx;
6533         int idx, i;
6534
6535         if (spec->dsp_state != DSP_DOWNLOADED)
6536                 return;
6537
6538         sbz_dsp_scp_startup(codec);
6539
6540         sbz_init_analog_mics(codec);
6541
6542         sbz_connect_streams(codec);
6543
6544         sbz_chipio_startup_data(codec);
6545
6546         chipio_set_stream_control(codec, 0x03, 1);
6547         chipio_set_stream_control(codec, 0x04, 1);
6548
6549         /*
6550          * Sets internal input loopback to off, used to have a switch to
6551          * enable input loopback, but turned out to be way too buggy.
6552          */
6553         tmp = FLOAT_ONE;
6554         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6555         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6556
6557         /*remove DSP headroom*/
6558         tmp = FLOAT_ZERO;
6559         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6560
6561         /* set WUH source */
6562         tmp = FLOAT_TWO;
6563         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6564         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6565
6566         /* Set speaker source? */
6567         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6568
6569         sbz_dsp_initial_mic_setup(codec);
6570
6571
6572         /* out, in effects + voicefx */
6573         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6574         for (idx = 0; idx < num_fx; idx++) {
6575                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6576                         dspio_set_uint_param(codec,
6577                                         ca0132_effects[idx].mid,
6578                                         ca0132_effects[idx].reqs[i],
6579                                         ca0132_effects[idx].def_vals[i]);
6580                 }
6581         }
6582
6583         /*
6584          * Have to make a stream to bind the sound output to, otherwise
6585          * you'll get dead audio. Before I did this, it would bind to an
6586          * audio input, and would never work
6587          */
6588         stream_format = snd_hdac_calc_stream_format(48000, 2,
6589                         SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6590
6591         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6592                                         0, stream_format);
6593
6594         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6595
6596         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6597                                         0, stream_format);
6598
6599         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6600 }
6601
6602 /*
6603  * Initialization of flags in chip
6604  */
6605 static void ca0132_init_flags(struct hda_codec *codec)
6606 {
6607         struct ca0132_spec *spec = codec->spec;
6608
6609         if (spec->use_alt_functions) {
6610                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6611                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6612                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6613                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6614                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6615                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6616                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6617                 chipio_set_control_flag(codec,
6618                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6619                 chipio_set_control_flag(codec,
6620                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6621         } else {
6622                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6623                 chipio_set_control_flag(codec,
6624                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6625                 chipio_set_control_flag(codec,
6626                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6627                 chipio_set_control_flag(codec,
6628                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6629                 chipio_set_control_flag(codec,
6630                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6631                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6632         }
6633 }
6634
6635 /*
6636  * Initialization of parameters in chip
6637  */
6638 static void ca0132_init_params(struct hda_codec *codec)
6639 {
6640         struct ca0132_spec *spec = codec->spec;
6641
6642         if (spec->use_alt_functions) {
6643                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6644                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6645                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6646                 chipio_set_control_param(codec, 0, 0);
6647                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6648         }
6649
6650         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6651         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6652 }
6653
6654 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6655 {
6656         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6657         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6658         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6659         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6660         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6661         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6662
6663         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6664         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6665         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6666 }
6667
6668 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6669 {
6670         bool dsp_loaded = false;
6671         struct ca0132_spec *spec = codec->spec;
6672         const struct dsp_image_seg *dsp_os_image;
6673         const struct firmware *fw_entry;
6674         /*
6675          * Alternate firmwares for different variants. The Recon3Di apparently
6676          * can use the default firmware, but I'll leave the option in case
6677          * it needs it again.
6678          */
6679         switch (spec->quirk) {
6680         case QUIRK_SBZ:
6681                 if (reject_firmware(&fw_entry, SBZ_EFX_FILE,
6682                                         codec->card->dev) != 0) {
6683                         codec_dbg(codec, "SBZ alt firmware not detected. ");
6684                         spec->alt_firmware_present = false;
6685                 } else {
6686                         codec_dbg(codec, "Sound Blaster Z firmware selected.");
6687                         spec->alt_firmware_present = true;
6688                 }
6689                 break;
6690         case QUIRK_R3DI:
6691                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
6692                                         codec->card->dev) != 0) {
6693                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
6694                         spec->alt_firmware_present = false;
6695                 } else {
6696                         codec_dbg(codec, "Recon3Di firmware selected.");
6697                         spec->alt_firmware_present = true;
6698                 }
6699                 break;
6700         default:
6701                 spec->alt_firmware_present = false;
6702                 break;
6703         }
6704 /*(DEBLOBBED)*/
6705         if (!spec->alt_firmware_present) {
6706                 codec_dbg(codec, "Default firmware selected.");
6707                 if (reject_firmware(&fw_entry, EFX_FILE,
6708                                         codec->card->dev) != 0)
6709                         return false;
6710         }
6711
6712         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6713         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6714                 codec_err(codec, "ca0132 DSP load image failed\n");
6715                 goto exit_download;
6716         }
6717
6718         dsp_loaded = dspload_wait_loaded(codec);
6719
6720 exit_download:
6721         release_firmware(fw_entry);
6722
6723         return dsp_loaded;
6724 }
6725
6726 static void ca0132_download_dsp(struct hda_codec *codec)
6727 {
6728         struct ca0132_spec *spec = codec->spec;
6729
6730 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6731         return; /* NOP */
6732 #endif
6733
6734         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6735                 return; /* don't retry failures */
6736
6737         chipio_enable_clocks(codec);
6738         if (spec->dsp_state != DSP_DOWNLOADED) {
6739                 spec->dsp_state = DSP_DOWNLOADING;
6740
6741                 if (!ca0132_download_dsp_images(codec))
6742                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
6743                 else
6744                         spec->dsp_state = DSP_DOWNLOADED;
6745         }
6746
6747         /* For codecs using alt functions, this is already done earlier */
6748         if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6749                 ca0132_set_dsp_msr(codec, true);
6750 }
6751
6752 static void ca0132_process_dsp_response(struct hda_codec *codec,
6753                                         struct hda_jack_callback *callback)
6754 {
6755         struct ca0132_spec *spec = codec->spec;
6756
6757         codec_dbg(codec, "ca0132_process_dsp_response\n");
6758         snd_hda_power_up_pm(codec);
6759         if (spec->wait_scp) {
6760                 if (dspio_get_response_data(codec) >= 0)
6761                         spec->wait_scp = 0;
6762         }
6763
6764         dspio_clear_response_queue(codec);
6765         snd_hda_power_down_pm(codec);
6766 }
6767
6768 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6769 {
6770         struct ca0132_spec *spec = codec->spec;
6771         struct hda_jack_tbl *tbl;
6772
6773         /* Delay enabling the HP amp, to let the mic-detection
6774          * state machine run.
6775          */
6776         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6777         if (tbl)
6778                 tbl->block_report = 1;
6779         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6780 }
6781
6782 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6783 {
6784         struct ca0132_spec *spec = codec->spec;
6785
6786         if (spec->use_alt_functions)
6787                 ca0132_alt_select_in(codec);
6788         else
6789                 ca0132_select_mic(codec);
6790 }
6791
6792 static void ca0132_init_unsol(struct hda_codec *codec)
6793 {
6794         struct ca0132_spec *spec = codec->spec;
6795         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6796         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6797                                             amic_callback);
6798         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6799                                             ca0132_process_dsp_response);
6800         /* Front headphone jack detection */
6801         if (spec->use_alt_functions)
6802                 snd_hda_jack_detect_enable_callback(codec,
6803                         spec->unsol_tag_front_hp, hp_callback);
6804 }
6805
6806 /*
6807  * Verbs tables.
6808  */
6809
6810 /* Sends before DSP download. */
6811 static struct hda_verb ca0132_base_init_verbs[] = {
6812         /*enable ct extension*/
6813         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6814         {}
6815 };
6816
6817 /* Send at exit. */
6818 static struct hda_verb ca0132_base_exit_verbs[] = {
6819         /*set afg to D3*/
6820         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6821         /*disable ct extension*/
6822         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6823         {}
6824 };
6825
6826 /* Other verbs tables. Sends after DSP download. */
6827
6828 static struct hda_verb ca0132_init_verbs0[] = {
6829         /* chip init verbs */
6830         {0x15, 0x70D, 0xF0},
6831         {0x15, 0x70E, 0xFE},
6832         {0x15, 0x707, 0x75},
6833         {0x15, 0x707, 0xD3},
6834         {0x15, 0x707, 0x09},
6835         {0x15, 0x707, 0x53},
6836         {0x15, 0x707, 0xD4},
6837         {0x15, 0x707, 0xEF},
6838         {0x15, 0x707, 0x75},
6839         {0x15, 0x707, 0xD3},
6840         {0x15, 0x707, 0x09},
6841         {0x15, 0x707, 0x02},
6842         {0x15, 0x707, 0x37},
6843         {0x15, 0x707, 0x78},
6844         {0x15, 0x53C, 0xCE},
6845         {0x15, 0x575, 0xC9},
6846         {0x15, 0x53D, 0xCE},
6847         {0x15, 0x5B7, 0xC9},
6848         {0x15, 0x70D, 0xE8},
6849         {0x15, 0x70E, 0xFE},
6850         {0x15, 0x707, 0x02},
6851         {0x15, 0x707, 0x68},
6852         {0x15, 0x707, 0x62},
6853         {0x15, 0x53A, 0xCE},
6854         {0x15, 0x546, 0xC9},
6855         {0x15, 0x53B, 0xCE},
6856         {0x15, 0x5E8, 0xC9},
6857         {}
6858 };
6859
6860 /* Extra init verbs for desktop cards. */
6861 static struct hda_verb ca0132_init_verbs1[] = {
6862         {0x15, 0x70D, 0x20},
6863         {0x15, 0x70E, 0x19},
6864         {0x15, 0x707, 0x00},
6865         {0x15, 0x539, 0xCE},
6866         {0x15, 0x546, 0xC9},
6867         {0x15, 0x70D, 0xB7},
6868         {0x15, 0x70E, 0x09},
6869         {0x15, 0x707, 0x10},
6870         {0x15, 0x70D, 0xAF},
6871         {0x15, 0x70E, 0x09},
6872         {0x15, 0x707, 0x01},
6873         {0x15, 0x707, 0x05},
6874         {0x15, 0x70D, 0x73},
6875         {0x15, 0x70E, 0x09},
6876         {0x15, 0x707, 0x14},
6877         {0x15, 0x6FF, 0xC4},
6878         {}
6879 };
6880
6881 static void ca0132_init_chip(struct hda_codec *codec)
6882 {
6883         struct ca0132_spec *spec = codec->spec;
6884         int num_fx;
6885         int i;
6886         unsigned int on;
6887
6888         mutex_init(&spec->chipio_mutex);
6889
6890         spec->cur_out_type = SPEAKER_OUT;
6891         if (!spec->use_alt_functions)
6892                 spec->cur_mic_type = DIGITAL_MIC;
6893         else
6894                 spec->cur_mic_type = REAR_MIC;
6895
6896         spec->cur_mic_boost = 0;
6897
6898         for (i = 0; i < VNODES_COUNT; i++) {
6899                 spec->vnode_lvol[i] = 0x5a;
6900                 spec->vnode_rvol[i] = 0x5a;
6901                 spec->vnode_lswitch[i] = 0;
6902                 spec->vnode_rswitch[i] = 0;
6903         }
6904
6905         /*
6906          * Default states for effects are in ca0132_effects[].
6907          */
6908         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6909         for (i = 0; i < num_fx; i++) {
6910                 on = (unsigned int)ca0132_effects[i].reqs[0];
6911                 spec->effects_switch[i] = on ? 1 : 0;
6912         }
6913         /*
6914          * Sets defaults for the effect slider controls, only for alternative
6915          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6916          */
6917         if (spec->use_alt_controls) {
6918                 spec->xbass_xover_freq = 8;
6919                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6920                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
6921         }
6922
6923         spec->voicefx_val = 0;
6924         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6925         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6926
6927 #ifdef ENABLE_TUNING_CONTROLS
6928         ca0132_init_tuning_defaults(codec);
6929 #endif
6930 }
6931
6932 /*
6933  * Recon3Di exit specific commands.
6934  */
6935 /* prevents popping noise on shutdown */
6936 static void r3di_gpio_shutdown(struct hda_codec *codec)
6937 {
6938         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6939 }
6940
6941 /*
6942  * Sound Blaster Z exit specific commands.
6943  */
6944 static void sbz_region2_exit(struct hda_codec *codec)
6945 {
6946         struct ca0132_spec *spec = codec->spec;
6947         unsigned int i;
6948
6949         for (i = 0; i < 4; i++)
6950                 writeb(0x0, spec->mem_base + 0x100);
6951         for (i = 0; i < 8; i++)
6952                 writeb(0xb3, spec->mem_base + 0x304);
6953
6954         ca0132_mmio_gpio_set(codec, 0, false);
6955         ca0132_mmio_gpio_set(codec, 1, false);
6956         ca0132_mmio_gpio_set(codec, 4, true);
6957         ca0132_mmio_gpio_set(codec, 5, false);
6958         ca0132_mmio_gpio_set(codec, 7, false);
6959 }
6960
6961 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6962 {
6963         hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6964         unsigned int i;
6965
6966         snd_hda_codec_write(codec, 0x11, 0,
6967                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6968
6969         for (i = 0; i < 5; i++)
6970                 snd_hda_codec_write(codec, pins[i], 0,
6971                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6972 }
6973
6974 static void ca0132_clear_unsolicited(struct hda_codec *codec)
6975 {
6976         hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6977         unsigned int i;
6978
6979         for (i = 0; i < 7; i++) {
6980                 snd_hda_codec_write(codec, pins[i], 0,
6981                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6982         }
6983 }
6984
6985 /* On shutdown, sends commands in sets of three */
6986 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6987                                                         int mask, int data)
6988 {
6989         if (dir >= 0)
6990                 snd_hda_codec_write(codec, 0x01, 0,
6991                                 AC_VERB_SET_GPIO_DIRECTION, dir);
6992         if (mask >= 0)
6993                 snd_hda_codec_write(codec, 0x01, 0,
6994                                 AC_VERB_SET_GPIO_MASK, mask);
6995
6996         if (data >= 0)
6997                 snd_hda_codec_write(codec, 0x01, 0,
6998                                 AC_VERB_SET_GPIO_DATA, data);
6999 }
7000
7001 static void sbz_exit_chip(struct hda_codec *codec)
7002 {
7003         chipio_set_stream_control(codec, 0x03, 0);
7004         chipio_set_stream_control(codec, 0x04, 0);
7005
7006         /* Mess with GPIO */
7007         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7008         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7009         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7010
7011         chipio_set_stream_control(codec, 0x14, 0);
7012         chipio_set_stream_control(codec, 0x0C, 0);
7013
7014         chipio_set_conn_rate(codec, 0x41, SR_192_000);
7015         chipio_set_conn_rate(codec, 0x91, SR_192_000);
7016
7017         chipio_write(codec, 0x18a020, 0x00000083);
7018
7019         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7020         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7021         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7022
7023         chipio_set_stream_control(codec, 0x0C, 0);
7024
7025         chipio_set_control_param(codec, 0x0D, 0x24);
7026
7027         ca0132_clear_unsolicited(codec);
7028         sbz_set_pin_ctl_default(codec);
7029
7030         snd_hda_codec_write(codec, 0x0B, 0,
7031                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7032
7033         sbz_region2_exit(codec);
7034 }
7035
7036 static void r3d_exit_chip(struct hda_codec *codec)
7037 {
7038         ca0132_clear_unsolicited(codec);
7039         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7040         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7041 }
7042
7043 static void ca0132_exit_chip(struct hda_codec *codec)
7044 {
7045         /* put any chip cleanup stuffs here. */
7046
7047         if (dspload_is_loaded(codec))
7048                 dsp_reset(codec);
7049 }
7050
7051 /*
7052  * This fixes a problem that was hard to reproduce. Very rarely, I would
7053  * boot up, and there would be no sound, but the DSP indicated it had loaded
7054  * properly. I did a few memory dumps to see if anything was different, and
7055  * there were a few areas of memory uninitialized with a1a2a3a4. This function
7056  * checks if those areas are uninitialized, and if they are, it'll attempt to
7057  * reload the card 3 times. Usually it fixes by the second.
7058  */
7059 static void sbz_dsp_startup_check(struct hda_codec *codec)
7060 {
7061         struct ca0132_spec *spec = codec->spec;
7062         unsigned int dsp_data_check[4];
7063         unsigned int cur_address = 0x390;
7064         unsigned int i;
7065         unsigned int failure = 0;
7066         unsigned int reload = 3;
7067
7068         if (spec->startup_check_entered)
7069                 return;
7070
7071         spec->startup_check_entered = true;
7072
7073         for (i = 0; i < 4; i++) {
7074                 chipio_read(codec, cur_address, &dsp_data_check[i]);
7075                 cur_address += 0x4;
7076         }
7077         for (i = 0; i < 4; i++) {
7078                 if (dsp_data_check[i] == 0xa1a2a3a4)
7079                         failure = 1;
7080         }
7081
7082         codec_dbg(codec, "Startup Check: %d ", failure);
7083         if (failure)
7084                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7085         /*
7086          * While the failure condition is true, and we haven't reached our
7087          * three reload limit, continue trying to reload the driver and
7088          * fix the issue.
7089          */
7090         while (failure && (reload != 0)) {
7091                 codec_info(codec, "Reloading... Tries left: %d", reload);
7092                 sbz_exit_chip(codec);
7093                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7094                 codec->patch_ops.init(codec);
7095                 failure = 0;
7096                 for (i = 0; i < 4; i++) {
7097                         chipio_read(codec, cur_address, &dsp_data_check[i]);
7098                         cur_address += 0x4;
7099                 }
7100                 for (i = 0; i < 4; i++) {
7101                         if (dsp_data_check[i] == 0xa1a2a3a4)
7102                                 failure = 1;
7103                 }
7104                 reload--;
7105         }
7106
7107         if (!failure && reload < 3)
7108                 codec_info(codec, "DSP fixed.");
7109
7110         if (!failure)
7111                 return;
7112
7113         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7114 }
7115
7116 /*
7117  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7118  * extra precision for decibel values. If you had the dB value in floating point
7119  * you would take the value after the decimal point, multiply by 64, and divide
7120  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7121  * implement fixed point or floating point dB volumes. For now, I'll set them
7122  * to 0 just incase a value has lingered from a boot into Windows.
7123  */
7124 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7125 {
7126         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7127         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7128         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7129         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7130         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7131         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7132         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7133         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7134 }
7135
7136 /*
7137  * Extra commands that don't really fit anywhere else.
7138  */
7139 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7140 {
7141         struct ca0132_spec *spec = codec->spec;
7142
7143         writel(0x00820680, spec->mem_base + 0x01C);
7144         writel(0x00820680, spec->mem_base + 0x01C);
7145
7146         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7147         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7148         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7149         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7150
7151         chipio_write(codec, 0x18b0a4, 0x000000c2);
7152
7153         snd_hda_codec_write(codec, 0x11, 0,
7154                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7155 }
7156
7157 static void r3d_pre_dsp_setup(struct hda_codec *codec)
7158 {
7159
7160         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7161         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7162         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7163         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7164
7165         chipio_write(codec, 0x18b0a4, 0x000000c2);
7166
7167         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7168                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7169         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7170                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7171         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7172                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7173
7174         snd_hda_codec_write(codec, 0x11, 0,
7175                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7176 }
7177
7178 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7179 {
7180         chipio_write(codec, 0x18b0a4, 0x000000c2);
7181
7182         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7183                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7184         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7185                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7186         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7187                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7188
7189         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7190                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7191         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7192                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7193         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7194                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7195         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7196                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7197
7198         snd_hda_codec_write(codec, 0x11, 0,
7199                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7200 }
7201
7202 /*
7203  * These are sent before the DSP is downloaded. Not sure
7204  * what they do, or if they're necessary. Could possibly
7205  * be removed. Figure they're better to leave in.
7206  */
7207 static void ca0132_mmio_init(struct hda_codec *codec)
7208 {
7209         struct ca0132_spec *spec = codec->spec;
7210
7211         writel(0x00000000, spec->mem_base + 0x400);
7212         writel(0x00000000, spec->mem_base + 0x408);
7213         writel(0x00000000, spec->mem_base + 0x40C);
7214         writel(0x00880680, spec->mem_base + 0x01C);
7215         writel(0x00000083, spec->mem_base + 0xC0C);
7216         writel(0x00000030, spec->mem_base + 0xC00);
7217         writel(0x00000000, spec->mem_base + 0xC04);
7218         writel(0x00000003, spec->mem_base + 0xC0C);
7219         writel(0x00000003, spec->mem_base + 0xC0C);
7220         writel(0x00000003, spec->mem_base + 0xC0C);
7221         writel(0x00000003, spec->mem_base + 0xC0C);
7222         writel(0x000000C1, spec->mem_base + 0xC08);
7223         writel(0x000000F1, spec->mem_base + 0xC08);
7224         writel(0x00000001, spec->mem_base + 0xC08);
7225         writel(0x000000C7, spec->mem_base + 0xC08);
7226         writel(0x000000C1, spec->mem_base + 0xC08);
7227         writel(0x00000080, spec->mem_base + 0xC04);
7228 }
7229
7230 /*
7231  * Extra init functions for alternative ca0132 codecs. Done
7232  * here so they don't clutter up the main ca0132_init function
7233  * anymore than they have to.
7234  */
7235 static void ca0132_alt_init(struct hda_codec *codec)
7236 {
7237         struct ca0132_spec *spec = codec->spec;
7238
7239         ca0132_alt_vol_setup(codec);
7240
7241         switch (spec->quirk) {
7242         case QUIRK_SBZ:
7243                 codec_dbg(codec, "SBZ alt_init");
7244                 ca0132_gpio_init(codec);
7245                 sbz_pre_dsp_setup(codec);
7246                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7247                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7248                 break;
7249         case QUIRK_R3DI:
7250                 codec_dbg(codec, "R3DI alt_init");
7251                 ca0132_gpio_init(codec);
7252                 ca0132_gpio_setup(codec);
7253                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7254                 r3di_pre_dsp_setup(codec);
7255                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7256                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7257                 break;
7258         case QUIRK_R3D:
7259                 r3d_pre_dsp_setup(codec);
7260                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7261                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7262                 break;
7263         }
7264 }
7265
7266 static int ca0132_init(struct hda_codec *codec)
7267 {
7268         struct ca0132_spec *spec = codec->spec;
7269         struct auto_pin_cfg *cfg = &spec->autocfg;
7270         int i;
7271         bool dsp_loaded;
7272
7273         /*
7274          * If the DSP is already downloaded, and init has been entered again,
7275          * there's only two reasons for it. One, the codec has awaken from a
7276          * suspended state, and in that case dspload_is_loaded will return
7277          * false, and the init will be ran again. The other reason it gets
7278          * re entered is on startup for some reason it triggers a suspend and
7279          * resume state. In this case, it will check if the DSP is downloaded,
7280          * and not run the init function again. For codecs using alt_functions,
7281          * it will check if the DSP is loaded properly.
7282          */
7283         if (spec->dsp_state == DSP_DOWNLOADED) {
7284                 dsp_loaded = dspload_is_loaded(codec);
7285                 if (!dsp_loaded) {
7286                         spec->dsp_reload = true;
7287                         spec->dsp_state = DSP_DOWNLOAD_INIT;
7288                 } else {
7289                         if (spec->quirk == QUIRK_SBZ)
7290                                 sbz_dsp_startup_check(codec);
7291                         return 0;
7292                 }
7293         }
7294
7295         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7296                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7297         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7298
7299         if (spec->use_pci_mmio)
7300                 ca0132_mmio_init(codec);
7301
7302         snd_hda_power_up_pm(codec);
7303
7304         ca0132_init_unsol(codec);
7305         ca0132_init_params(codec);
7306         ca0132_init_flags(codec);
7307
7308         snd_hda_sequence_write(codec, spec->base_init_verbs);
7309
7310         if (spec->use_alt_functions)
7311                 ca0132_alt_init(codec);
7312
7313         ca0132_download_dsp(codec);
7314
7315         ca0132_refresh_widget_caps(codec);
7316
7317         switch (spec->quirk) {
7318         case QUIRK_R3DI:
7319         case QUIRK_R3D:
7320                 r3d_setup_defaults(codec);
7321                 break;
7322         case QUIRK_SBZ:
7323                 sbz_setup_defaults(codec);
7324                 break;
7325         default:
7326                 ca0132_setup_defaults(codec);
7327                 ca0132_init_analog_mic2(codec);
7328                 ca0132_init_dmic(codec);
7329                 break;
7330         }
7331
7332         for (i = 0; i < spec->num_outputs; i++)
7333                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7334
7335         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7336
7337         for (i = 0; i < spec->num_inputs; i++)
7338                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7339
7340         init_input(codec, cfg->dig_in_pin, spec->dig_in);
7341
7342         if (!spec->use_alt_functions) {
7343                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7344                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7345                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7346                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7347                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7348         }
7349
7350         if (spec->quirk == QUIRK_SBZ)
7351                 ca0132_gpio_setup(codec);
7352
7353         snd_hda_sequence_write(codec, spec->spec_init_verbs);
7354         if (spec->use_alt_functions) {
7355                 ca0132_alt_select_out(codec);
7356                 ca0132_alt_select_in(codec);
7357         } else {
7358                 ca0132_select_out(codec);
7359                 ca0132_select_mic(codec);
7360         }
7361
7362         snd_hda_jack_report_sync(codec);
7363
7364         /*
7365          * Re set the PlayEnhancement switch on a resume event, because the
7366          * controls will not be reloaded.
7367          */
7368         if (spec->dsp_reload) {
7369                 spec->dsp_reload = false;
7370                 ca0132_pe_switch_set(codec);
7371         }
7372
7373         snd_hda_power_down_pm(codec);
7374
7375         return 0;
7376 }
7377
7378 static void ca0132_free(struct hda_codec *codec)
7379 {
7380         struct ca0132_spec *spec = codec->spec;
7381
7382         cancel_delayed_work_sync(&spec->unsol_hp_work);
7383         snd_hda_power_up(codec);
7384         switch (spec->quirk) {
7385         case QUIRK_SBZ:
7386                 sbz_exit_chip(codec);
7387                 break;
7388         case QUIRK_R3D:
7389                 r3d_exit_chip(codec);
7390                 break;
7391         case QUIRK_R3DI:
7392                 r3di_gpio_shutdown(codec);
7393                 break;
7394         }
7395
7396         snd_hda_sequence_write(codec, spec->base_exit_verbs);
7397         ca0132_exit_chip(codec);
7398
7399         snd_hda_power_down(codec);
7400 #ifdef CONFIG_PCI
7401         if (spec->mem_base)
7402                 pci_iounmap(codec->bus->pci, spec->mem_base);
7403 #endif
7404         kfree(spec->spec_init_verbs);
7405         kfree(codec->spec);
7406 }
7407
7408 static void ca0132_reboot_notify(struct hda_codec *codec)
7409 {
7410         codec->patch_ops.free(codec);
7411 }
7412
7413 #ifdef CONFIG_PM
7414 static int ca0132_suspend(struct hda_codec *codec)
7415 {
7416         struct ca0132_spec *spec = codec->spec;
7417
7418         cancel_delayed_work_sync(&spec->unsol_hp_work);
7419         return 0;
7420 }
7421 #endif
7422
7423 static const struct hda_codec_ops ca0132_patch_ops = {
7424         .build_controls = ca0132_build_controls,
7425         .build_pcms = ca0132_build_pcms,
7426         .init = ca0132_init,
7427         .free = ca0132_free,
7428         .unsol_event = snd_hda_jack_unsol_event,
7429 #ifdef CONFIG_PM
7430         .suspend = ca0132_suspend,
7431 #endif
7432         .reboot_notify = ca0132_reboot_notify,
7433 };
7434
7435 static void ca0132_config(struct hda_codec *codec)
7436 {
7437         struct ca0132_spec *spec = codec->spec;
7438
7439         spec->dacs[0] = 0x2;
7440         spec->dacs[1] = 0x3;
7441         spec->dacs[2] = 0x4;
7442
7443         spec->multiout.dac_nids = spec->dacs;
7444         spec->multiout.num_dacs = 3;
7445
7446         if (!spec->use_alt_functions)
7447                 spec->multiout.max_channels = 2;
7448         else
7449                 spec->multiout.max_channels = 6;
7450
7451         switch (spec->quirk) {
7452         case QUIRK_ALIENWARE:
7453                 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7454                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7455
7456                 spec->num_outputs = 2;
7457                 spec->out_pins[0] = 0x0b; /* speaker out */
7458                 spec->out_pins[1] = 0x0f;
7459                 spec->shared_out_nid = 0x2;
7460                 spec->unsol_tag_hp = 0x0f;
7461
7462                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7463                 spec->adcs[1] = 0x8; /* analog mic2 */
7464                 spec->adcs[2] = 0xa; /* what u hear */
7465
7466                 spec->num_inputs = 3;
7467                 spec->input_pins[0] = 0x12;
7468                 spec->input_pins[1] = 0x11;
7469                 spec->input_pins[2] = 0x13;
7470                 spec->shared_mic_nid = 0x7;
7471                 spec->unsol_tag_amic1 = 0x11;
7472                 break;
7473         case QUIRK_SBZ:
7474         case QUIRK_R3D:
7475                 if (spec->quirk == QUIRK_SBZ) {
7476                         codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7477                         snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7478                 }
7479                 if (spec->quirk == QUIRK_R3D) {
7480                         codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7481                         snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7482                 }
7483
7484                 spec->num_outputs = 2;
7485                 spec->out_pins[0] = 0x0B; /* Line out */
7486                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7487                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7488                 spec->out_pins[3] = 0x11; /* Rear surround */
7489                 spec->shared_out_nid = 0x2;
7490                 spec->unsol_tag_hp = spec->out_pins[1];
7491                 spec->unsol_tag_front_hp = spec->out_pins[2];
7492
7493                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7494                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7495                 spec->adcs[2] = 0xa; /* what u hear */
7496
7497                 spec->num_inputs = 2;
7498                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7499                 spec->input_pins[1] = 0x13; /* What U Hear */
7500                 spec->shared_mic_nid = 0x7;
7501                 spec->unsol_tag_amic1 = spec->input_pins[0];
7502
7503                 /* SPDIF I/O */
7504                 spec->dig_out = 0x05;
7505                 spec->multiout.dig_out_nid = spec->dig_out;
7506                 spec->dig_in = 0x09;
7507                 break;
7508         case QUIRK_R3DI:
7509                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7510                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7511
7512                 spec->num_outputs = 2;
7513                 spec->out_pins[0] = 0x0B; /* Line out */
7514                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7515                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7516                 spec->out_pins[3] = 0x11; /* Rear surround */
7517                 spec->shared_out_nid = 0x2;
7518                 spec->unsol_tag_hp = spec->out_pins[1];
7519                 spec->unsol_tag_front_hp = spec->out_pins[2];
7520
7521                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7522                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7523                 spec->adcs[2] = 0x0a; /* what u hear */
7524
7525                 spec->num_inputs = 2;
7526                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7527                 spec->input_pins[1] = 0x13; /* What U Hear */
7528                 spec->shared_mic_nid = 0x7;
7529                 spec->unsol_tag_amic1 = spec->input_pins[0];
7530
7531                 /* SPDIF I/O */
7532                 spec->dig_out = 0x05;
7533                 spec->multiout.dig_out_nid = spec->dig_out;
7534                 break;
7535         default:
7536                 spec->num_outputs = 2;
7537                 spec->out_pins[0] = 0x0b; /* speaker out */
7538                 spec->out_pins[1] = 0x10; /* headphone out */
7539                 spec->shared_out_nid = 0x2;
7540                 spec->unsol_tag_hp = spec->out_pins[1];
7541
7542                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7543                 spec->adcs[1] = 0x8; /* analog mic2 */
7544                 spec->adcs[2] = 0xa; /* what u hear */
7545
7546                 spec->num_inputs = 3;
7547                 spec->input_pins[0] = 0x12;
7548                 spec->input_pins[1] = 0x11;
7549                 spec->input_pins[2] = 0x13;
7550                 spec->shared_mic_nid = 0x7;
7551                 spec->unsol_tag_amic1 = spec->input_pins[0];
7552
7553                 /* SPDIF I/O */
7554                 spec->dig_out = 0x05;
7555                 spec->multiout.dig_out_nid = spec->dig_out;
7556                 spec->dig_in = 0x09;
7557                 break;
7558         }
7559 }
7560
7561 static int ca0132_prepare_verbs(struct hda_codec *codec)
7562 {
7563 /* Verbs + terminator (an empty element) */
7564 #define NUM_SPEC_VERBS 2
7565         struct ca0132_spec *spec = codec->spec;
7566
7567         spec->chip_init_verbs = ca0132_init_verbs0;
7568         if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
7569                 spec->desktop_init_verbs = ca0132_init_verbs1;
7570         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7571                                         sizeof(struct hda_verb),
7572                                         GFP_KERNEL);
7573         if (!spec->spec_init_verbs)
7574                 return -ENOMEM;
7575
7576         /* config EAPD */
7577         spec->spec_init_verbs[0].nid = 0x0b;
7578         spec->spec_init_verbs[0].param = 0x78D;
7579         spec->spec_init_verbs[0].verb = 0x00;
7580
7581         /* Previously commented configuration */
7582         /*
7583         spec->spec_init_verbs[2].nid = 0x0b;
7584         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7585         spec->spec_init_verbs[2].verb = 0x02;
7586
7587         spec->spec_init_verbs[3].nid = 0x10;
7588         spec->spec_init_verbs[3].param = 0x78D;
7589         spec->spec_init_verbs[3].verb = 0x02;
7590
7591         spec->spec_init_verbs[4].nid = 0x10;
7592         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7593         spec->spec_init_verbs[4].verb = 0x02;
7594         */
7595
7596         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7597         return 0;
7598 }
7599
7600 static int patch_ca0132(struct hda_codec *codec)
7601 {
7602         struct ca0132_spec *spec;
7603         int err;
7604         const struct snd_pci_quirk *quirk;
7605
7606         codec_dbg(codec, "patch_ca0132\n");
7607
7608         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7609         if (!spec)
7610                 return -ENOMEM;
7611         codec->spec = spec;
7612         spec->codec = codec;
7613
7614         codec->patch_ops = ca0132_patch_ops;
7615         codec->pcm_format_first = 1;
7616         codec->no_sticky_stream = 1;
7617
7618         /* Detect codec quirk */
7619         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7620         if (quirk)
7621                 spec->quirk = quirk->value;
7622         else
7623                 spec->quirk = QUIRK_NONE;
7624
7625         spec->dsp_state = DSP_DOWNLOAD_INIT;
7626         spec->num_mixers = 1;
7627
7628         /* Set which mixers each quirk uses. */
7629         switch (spec->quirk) {
7630         case QUIRK_SBZ:
7631                 spec->mixers[0] = desktop_mixer;
7632                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7633                 break;
7634         case QUIRK_R3D:
7635                 spec->mixers[0] = desktop_mixer;
7636                 snd_hda_codec_set_name(codec, "Recon3D");
7637                 break;
7638         case QUIRK_R3DI:
7639                 spec->mixers[0] = r3di_mixer;
7640                 snd_hda_codec_set_name(codec, "Recon3Di");
7641                 break;
7642         default:
7643                 spec->mixers[0] = ca0132_mixer;
7644                 break;
7645         }
7646
7647         /* Setup whether or not to use alt functions/controls/pci_mmio */
7648         switch (spec->quirk) {
7649         case QUIRK_SBZ:
7650         case QUIRK_R3D:
7651                 spec->use_alt_controls = true;
7652                 spec->use_alt_functions = true;
7653                 spec->use_pci_mmio = true;
7654                 break;
7655         case QUIRK_R3DI:
7656                 spec->use_alt_controls = true;
7657                 spec->use_alt_functions = true;
7658                 spec->use_pci_mmio = false;
7659                 break;
7660         default:
7661                 spec->use_alt_controls = false;
7662                 spec->use_alt_functions = false;
7663                 spec->use_pci_mmio = false;
7664                 break;
7665         }
7666
7667         if (spec->use_pci_mmio) {
7668                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7669                 if (spec->mem_base == NULL) {
7670                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7671                         spec->quirk = QUIRK_NONE;
7672                 }
7673         }
7674
7675         spec->base_init_verbs = ca0132_base_init_verbs;
7676         spec->base_exit_verbs = ca0132_base_exit_verbs;
7677
7678         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7679
7680         ca0132_init_chip(codec);
7681
7682         ca0132_config(codec);
7683
7684         err = ca0132_prepare_verbs(codec);
7685         if (err < 0)
7686                 goto error;
7687
7688         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7689         if (err < 0)
7690                 goto error;
7691
7692         return 0;
7693
7694  error:
7695         ca0132_free(codec);
7696         return err;
7697 }
7698
7699 /*
7700  * patch entries
7701  */
7702 static struct hda_device_id snd_hda_id_ca0132[] = {
7703         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7704         {} /* terminator */
7705 };
7706 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7707
7708 MODULE_LICENSE("GPL");
7709 MODULE_DESCRIPTION("Creative Sound Core3D codec");
7710
7711 static struct hda_codec_driver ca0132_driver = {
7712         .id = snd_hda_id_ca0132,
7713 };
7714
7715 module_hda_codec_driver(ca0132_driver);