3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/clocksource.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mutex.h>
31 #include <linux/of_device.h>
32 #include <linux/slab.h>
33 #include <linux/time.h>
35 #include <sound/core.h>
36 #include <sound/initval.h>
38 #include "hda_codec.h"
39 #include "hda_controller.h"
41 /* Defines for Nvidia Tegra HDA support */
42 #define HDA_BAR0 0x8000
44 #define HDA_CFG_CMD 0x1004
45 #define HDA_CFG_BAR0 0x1010
47 #define HDA_ENABLE_IO_SPACE (1 << 0)
48 #define HDA_ENABLE_MEM_SPACE (1 << 1)
49 #define HDA_ENABLE_BUS_MASTER (1 << 2)
50 #define HDA_ENABLE_SERR (1 << 8)
51 #define HDA_DISABLE_INTR (1 << 10)
52 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
53 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
56 #define HDA_IPFS_CONFIG 0x180
57 #define HDA_IPFS_EN_FPCI 0x1
59 #define HDA_IPFS_FPCI_BAR0 0x80
60 #define HDA_FPCI_BAR0_START 0x40
62 #define HDA_IPFS_INTR_MASK 0x188
63 #define HDA_IPFS_EN_INTR (1 << 16)
65 /* max number of SDs */
66 #define NUM_CAPTURE_SD 1
67 #define NUM_PLAYBACK_SD 1
73 struct clk *hda2codec_2x_clk;
74 struct clk *hda2hdmi_clk;
76 struct work_struct probe_work;
80 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
81 module_param(power_save, bint, 0644);
82 MODULE_PARM_DESC(power_save,
83 "Automatic power-saving timeout (in seconds, 0 = disable).");
89 * DMA page allocation ops.
91 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
92 struct snd_dma_buffer *buf)
94 return snd_dma_alloc_pages(type, bus->dev, size, buf);
97 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
99 snd_dma_free_pages(buf);
102 static int substream_alloc_pages(struct azx *chip,
103 struct snd_pcm_substream *substream,
106 return snd_pcm_lib_malloc_pages(substream, size);
109 static int substream_free_pages(struct azx *chip,
110 struct snd_pcm_substream *substream)
112 return snd_pcm_lib_free_pages(substream);
116 * Register access ops. Tegra HDA register access is DWORD only.
118 static void hda_tegra_writel(u32 value, u32 __iomem *addr)
123 static u32 hda_tegra_readl(u32 __iomem *addr)
128 static void hda_tegra_writew(u16 value, u16 __iomem *addr)
130 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
131 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
134 v = readl(dword_addr);
135 v &= ~(0xffff << shift);
137 writel(v, dword_addr);
140 static u16 hda_tegra_readw(u16 __iomem *addr)
142 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
143 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
146 v = readl(dword_addr);
147 return (v >> shift) & 0xffff;
150 static void hda_tegra_writeb(u8 value, u8 __iomem *addr)
152 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
153 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
156 v = readl(dword_addr);
157 v &= ~(0xff << shift);
159 writel(v, dword_addr);
162 static u8 hda_tegra_readb(u8 __iomem *addr)
164 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
165 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
168 v = readl(dword_addr);
169 return (v >> shift) & 0xff;
172 static const struct hdac_io_ops hda_tegra_io_ops = {
173 .reg_writel = hda_tegra_writel,
174 .reg_readl = hda_tegra_readl,
175 .reg_writew = hda_tegra_writew,
176 .reg_readw = hda_tegra_readw,
177 .reg_writeb = hda_tegra_writeb,
178 .reg_readb = hda_tegra_readb,
179 .dma_alloc_pages = dma_alloc_pages,
180 .dma_free_pages = dma_free_pages,
183 static const struct hda_controller_ops hda_tegra_ops = {
184 .substream_alloc_pages = substream_alloc_pages,
185 .substream_free_pages = substream_free_pages,
188 static void hda_tegra_init(struct hda_tegra *hda)
192 /* Enable PCI access */
193 v = readl(hda->regs + HDA_IPFS_CONFIG);
194 v |= HDA_IPFS_EN_FPCI;
195 writel(v, hda->regs + HDA_IPFS_CONFIG);
197 /* Enable MEM/IO space and bus master */
198 v = readl(hda->regs + HDA_CFG_CMD);
199 v &= ~HDA_DISABLE_INTR;
200 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
201 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
202 writel(v, hda->regs + HDA_CFG_CMD);
204 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
205 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
206 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
208 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
209 v |= HDA_IPFS_EN_INTR;
210 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
213 static int hda_tegra_enable_clocks(struct hda_tegra *data)
217 rc = clk_prepare_enable(data->hda_clk);
220 rc = clk_prepare_enable(data->hda2codec_2x_clk);
223 rc = clk_prepare_enable(data->hda2hdmi_clk);
225 goto disable_codec_2x;
230 clk_disable_unprepare(data->hda2codec_2x_clk);
232 clk_disable_unprepare(data->hda_clk);
236 #ifdef CONFIG_PM_SLEEP
237 static void hda_tegra_disable_clocks(struct hda_tegra *data)
239 clk_disable_unprepare(data->hda2hdmi_clk);
240 clk_disable_unprepare(data->hda2codec_2x_clk);
241 clk_disable_unprepare(data->hda_clk);
247 static int hda_tegra_suspend(struct device *dev)
249 struct snd_card *card = dev_get_drvdata(dev);
250 struct azx *chip = card->private_data;
251 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
252 struct hdac_bus *bus = azx_bus(chip);
254 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
257 synchronize_irq(bus->irq);
258 azx_enter_link_reset(chip);
259 hda_tegra_disable_clocks(hda);
264 static int hda_tegra_resume(struct device *dev)
266 struct snd_card *card = dev_get_drvdata(dev);
267 struct azx *chip = card->private_data;
268 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
270 hda_tegra_enable_clocks(hda);
274 azx_init_chip(chip, 1);
276 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
280 #endif /* CONFIG_PM_SLEEP */
282 static const struct dev_pm_ops hda_tegra_pm = {
283 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
286 static int hda_tegra_dev_disconnect(struct snd_device *device)
288 struct azx *chip = device->device_data;
290 chip->bus.shutdown = 1;
297 static int hda_tegra_dev_free(struct snd_device *device)
299 struct azx *chip = device->device_data;
300 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
302 cancel_work_sync(&hda->probe_work);
303 if (azx_bus(chip)->chip_init) {
304 azx_stop_all_streams(chip);
308 azx_free_stream_pages(chip);
309 azx_free_streams(chip);
310 snd_hdac_bus_exit(azx_bus(chip));
315 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
317 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
318 struct hdac_bus *bus = azx_bus(chip);
319 struct device *dev = hda->dev;
320 struct resource *res;
323 hda->hda_clk = devm_clk_get(dev, "hda");
324 if (IS_ERR(hda->hda_clk)) {
325 dev_err(dev, "failed to get hda clock\n");
326 return PTR_ERR(hda->hda_clk);
328 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
329 if (IS_ERR(hda->hda2codec_2x_clk)) {
330 dev_err(dev, "failed to get hda2codec_2x clock\n");
331 return PTR_ERR(hda->hda2codec_2x_clk);
333 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
334 if (IS_ERR(hda->hda2hdmi_clk)) {
335 dev_err(dev, "failed to get hda2hdmi clock\n");
336 return PTR_ERR(hda->hda2hdmi_clk);
339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340 hda->regs = devm_ioremap_resource(dev, res);
341 if (IS_ERR(hda->regs))
342 return PTR_ERR(hda->regs);
344 bus->remap_addr = hda->regs + HDA_BAR0;
345 bus->addr = res->start + HDA_BAR0;
347 err = hda_tegra_enable_clocks(hda);
349 dev_err(dev, "failed to get enable clocks\n");
358 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
360 struct hdac_bus *bus = azx_bus(chip);
361 struct snd_card *card = chip->card;
364 int irq_id = platform_get_irq(pdev, 0);
369 err = hda_tegra_init_chip(chip, pdev);
373 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
374 IRQF_SHARED, KBUILD_MODNAME, chip);
376 dev_err(chip->card->dev,
377 "unable to request IRQ %d, disabling device\n",
383 synchronize_irq(bus->irq);
385 gcap = azx_readw(chip, GCAP);
386 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
388 /* read number of streams from GCAP register instead of using
391 chip->capture_streams = (gcap >> 8) & 0x0f;
392 chip->playback_streams = (gcap >> 12) & 0x0f;
393 if (!chip->playback_streams && !chip->capture_streams) {
394 /* gcap didn't give any info, switching to old method */
395 chip->playback_streams = NUM_PLAYBACK_SD;
396 chip->capture_streams = NUM_CAPTURE_SD;
398 chip->capture_index_offset = 0;
399 chip->playback_index_offset = chip->capture_streams;
400 chip->num_streams = chip->playback_streams + chip->capture_streams;
402 /* initialize streams */
403 err = azx_init_streams(chip);
405 dev_err(card->dev, "failed to initialize streams: %d\n", err);
409 err = azx_alloc_stream_pages(chip);
411 dev_err(card->dev, "failed to allocate stream pages: %d\n",
416 /* initialize chip */
417 azx_init_chip(chip, 1);
419 /* codec detection */
420 if (!bus->codec_mask) {
421 dev_err(card->dev, "no codecs found!\n");
425 strcpy(card->driver, "tegra-hda");
426 strcpy(card->shortname, "tegra-hda");
427 snprintf(card->longname, sizeof(card->longname),
428 "%s at 0x%lx irq %i",
429 card->shortname, bus->addr, bus->irq);
438 static void hda_tegra_probe_work(struct work_struct *work);
440 static int hda_tegra_create(struct snd_card *card,
441 unsigned int driver_caps,
442 struct hda_tegra *hda)
444 static struct snd_device_ops ops = {
445 .dev_disconnect = hda_tegra_dev_disconnect,
446 .dev_free = hda_tegra_dev_free,
453 mutex_init(&chip->open_mutex);
455 chip->ops = &hda_tegra_ops;
456 chip->driver_caps = driver_caps;
457 chip->driver_type = driver_caps & 0xff;
459 INIT_LIST_HEAD(&chip->pcm_list);
461 chip->codec_probe_mask = -1;
463 chip->single_cmd = false;
466 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
468 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
472 chip->bus.needs_damn_long_delay = 1;
474 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
476 dev_err(card->dev, "Error creating device\n");
483 static const struct of_device_id hda_tegra_match[] = {
484 { .compatible = "nvidia,tegra30-hda" },
487 MODULE_DEVICE_TABLE(of, hda_tegra_match);
489 static int hda_tegra_probe(struct platform_device *pdev)
491 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR;
492 struct snd_card *card;
494 struct hda_tegra *hda;
497 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
500 hda->dev = &pdev->dev;
503 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
504 THIS_MODULE, 0, &card);
506 dev_err(&pdev->dev, "Error creating card!\n");
510 err = hda_tegra_create(card, driver_flags, hda);
513 card->private_data = chip;
515 dev_set_drvdata(&pdev->dev, card);
516 schedule_work(&hda->probe_work);
525 static void hda_tegra_probe_work(struct work_struct *work)
527 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
528 struct azx *chip = &hda->chip;
529 struct platform_device *pdev = to_platform_device(hda->dev);
532 err = hda_tegra_first_init(chip, pdev);
536 /* create codec instances */
537 err = azx_probe_codecs(chip, 0);
541 err = azx_codec_configure(chip);
545 err = snd_card_register(chip->card);
550 snd_hda_set_power_save(&chip->bus, power_save * 1000);
553 return; /* no error return from async probe */
556 static int hda_tegra_remove(struct platform_device *pdev)
558 return snd_card_free(dev_get_drvdata(&pdev->dev));
561 static void hda_tegra_shutdown(struct platform_device *pdev)
563 struct snd_card *card = dev_get_drvdata(&pdev->dev);
568 chip = card->private_data;
569 if (chip && chip->running)
573 static struct platform_driver tegra_platform_hda = {
577 .of_match_table = hda_tegra_match,
579 .probe = hda_tegra_probe,
580 .remove = hda_tegra_remove,
581 .shutdown = hda_tegra_shutdown,
583 module_platform_driver(tegra_platform_hda);
585 MODULE_DESCRIPTION("Tegra HDA bus driver");
586 MODULE_LICENSE("GPL v2");