1 // SPDX-License-Identifier: GPL-2.0-only
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/time.h>
23 #include <linux/string.h>
24 #include <linux/pm_runtime.h>
26 #include <sound/core.h>
27 #include <sound/initval.h>
29 #include <sound/hda_codec.h>
30 #include "hda_controller.h"
32 /* Defines for Nvidia Tegra HDA support */
33 #define HDA_BAR0 0x8000
35 #define HDA_CFG_CMD 0x1004
36 #define HDA_CFG_BAR0 0x1010
38 #define HDA_ENABLE_IO_SPACE (1 << 0)
39 #define HDA_ENABLE_MEM_SPACE (1 << 1)
40 #define HDA_ENABLE_BUS_MASTER (1 << 2)
41 #define HDA_ENABLE_SERR (1 << 8)
42 #define HDA_DISABLE_INTR (1 << 10)
43 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
44 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
47 #define HDA_IPFS_CONFIG 0x180
48 #define HDA_IPFS_EN_FPCI 0x1
50 #define HDA_IPFS_FPCI_BAR0 0x80
51 #define HDA_FPCI_BAR0_START 0x40
53 #define HDA_IPFS_INTR_MASK 0x188
54 #define HDA_IPFS_EN_INTR (1 << 16)
57 #define FPCI_DBG_CFG_2 0x10F4
58 #define FPCI_GCAP_NSDO_SHIFT 18
59 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
61 /* max number of SDs */
62 #define NUM_CAPTURE_SD 1
63 #define NUM_PLAYBACK_SD 1
66 * Tegra194 does not reflect correct number of SDO lines. Below macro
67 * is used to update the GCAP register to workaround the issue.
69 #define TEGRA194_NUM_SDO_LINES 4
71 struct hda_tegra_soc {
72 bool has_hda2codec_2x_reset;
78 struct reset_control_bulk_data resets[3];
79 struct clk_bulk_data clocks[3];
83 struct work_struct probe_work;
84 const struct hda_tegra_soc *soc;
88 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
89 module_param(power_save, bint, 0644);
90 MODULE_PARM_DESC(power_save,
91 "Automatic power-saving timeout (in seconds, 0 = disable).");
96 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
98 static void hda_tegra_init(struct hda_tegra *hda)
102 /* Enable PCI access */
103 v = readl(hda->regs + HDA_IPFS_CONFIG);
104 v |= HDA_IPFS_EN_FPCI;
105 writel(v, hda->regs + HDA_IPFS_CONFIG);
107 /* Enable MEM/IO space and bus master */
108 v = readl(hda->regs + HDA_CFG_CMD);
109 v &= ~HDA_DISABLE_INTR;
110 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
111 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
112 writel(v, hda->regs + HDA_CFG_CMD);
114 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
115 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
116 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
118 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
119 v |= HDA_IPFS_EN_INTR;
120 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
126 static int __maybe_unused hda_tegra_suspend(struct device *dev)
128 struct snd_card *card = dev_get_drvdata(dev);
131 rc = pm_runtime_force_suspend(dev);
134 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
139 static int __maybe_unused hda_tegra_resume(struct device *dev)
141 struct snd_card *card = dev_get_drvdata(dev);
144 rc = pm_runtime_force_resume(dev);
147 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
152 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
154 struct snd_card *card = dev_get_drvdata(dev);
155 struct azx *chip = card->private_data;
156 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
158 if (chip && chip->running) {
159 /* enable controller wake up event */
160 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
164 azx_enter_link_reset(chip);
166 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
171 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
173 struct snd_card *card = dev_get_drvdata(dev);
174 struct azx *chip = card->private_data;
175 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
178 if (!chip->running) {
179 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
184 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
189 azx_init_chip(chip, 1);
190 /* disable controller wake up event*/
191 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
194 usleep_range(10, 100);
196 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
204 static const struct dev_pm_ops hda_tegra_pm = {
205 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
206 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
207 hda_tegra_runtime_resume,
211 static int hda_tegra_dev_disconnect(struct snd_device *device)
213 struct azx *chip = device->device_data;
215 chip->bus.shutdown = 1;
222 static int hda_tegra_dev_free(struct snd_device *device)
224 struct azx *chip = device->device_data;
225 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
227 cancel_work_sync(&hda->probe_work);
228 if (azx_bus(chip)->chip_init) {
229 azx_stop_all_streams(chip);
233 azx_free_stream_pages(chip);
234 azx_free_streams(chip);
235 snd_hdac_bus_exit(azx_bus(chip));
240 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
242 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
243 struct hdac_bus *bus = azx_bus(chip);
244 struct resource *res;
246 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
247 if (IS_ERR(hda->regs))
248 return PTR_ERR(hda->regs);
250 bus->remap_addr = hda->regs + HDA_BAR0;
251 bus->addr = res->start + HDA_BAR0;
258 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
260 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
261 struct hdac_bus *bus = azx_bus(chip);
262 struct snd_card *card = chip->card;
265 int irq_id = platform_get_irq(pdev, 0);
266 const char *sname, *drv_name = "tegra-hda";
267 struct device_node *np = pdev->dev.of_node;
272 err = hda_tegra_init_chip(chip, pdev);
276 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
277 IRQF_SHARED, KBUILD_MODNAME, chip);
279 dev_err(chip->card->dev,
280 "unable to request IRQ %d, disabling device\n",
285 bus->dma_stop_delay = 100;
286 card->sync_irq = bus->irq;
289 * Tegra194 has 4 SDO lines and the STRIPE can be used to
290 * indicate how many of the SDO lines the stream should be
291 * striped. But GCAP register does not reflect the true
292 * capability of HW. Below workaround helps to fix this.
294 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
295 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
297 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
300 dev_info(card->dev, "Override SDO lines to %u\n",
301 TEGRA194_NUM_SDO_LINES);
303 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
304 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
305 writel(val, hda->regs + FPCI_DBG_CFG_2);
308 gcap = azx_readw(chip, GCAP);
309 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
311 chip->align_buffer_size = 1;
313 /* read number of streams from GCAP register instead of using
316 chip->capture_streams = (gcap >> 8) & 0x0f;
317 chip->playback_streams = (gcap >> 12) & 0x0f;
318 if (!chip->playback_streams && !chip->capture_streams) {
319 /* gcap didn't give any info, switching to old method */
320 chip->playback_streams = NUM_PLAYBACK_SD;
321 chip->capture_streams = NUM_CAPTURE_SD;
323 chip->capture_index_offset = 0;
324 chip->playback_index_offset = chip->capture_streams;
325 chip->num_streams = chip->playback_streams + chip->capture_streams;
327 /* initialize streams */
328 err = azx_init_streams(chip);
330 dev_err(card->dev, "failed to initialize streams: %d\n", err);
334 err = azx_alloc_stream_pages(chip);
336 dev_err(card->dev, "failed to allocate stream pages: %d\n",
341 /* initialize chip */
342 azx_init_chip(chip, 1);
345 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
346 * 4 SDO lines due to legacy design limitation. Following
347 * is, from HD Audio Specification (Revision 1.0a), used to
348 * control striping of the stream across multiple SDO lines
349 * for sample rates <= 48K.
351 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
353 * Due to legacy design issue it is recommended that above
354 * ratio must be greater than 8. Since number of SDO lines is
355 * in powers of 2, next available ratio is 16 which can be
356 * used as a limiting factor here.
358 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
359 chip->bus.core.sdo_limit = 16;
361 /* codec detection */
362 if (!bus->codec_mask) {
363 dev_err(card->dev, "no codecs found!\n");
368 strncpy(card->driver, drv_name, sizeof(card->driver));
369 /* shortname for card */
370 sname = of_get_property(np, "nvidia,model", NULL);
373 if (strlen(sname) > sizeof(card->shortname))
374 dev_info(card->dev, "truncating shortname for card\n");
375 strncpy(card->shortname, sname, sizeof(card->shortname));
377 /* longname for card */
378 snprintf(card->longname, sizeof(card->longname),
379 "%s at 0x%lx irq %i",
380 card->shortname, bus->addr, bus->irq);
389 static void hda_tegra_probe_work(struct work_struct *work);
391 static int hda_tegra_create(struct snd_card *card,
392 unsigned int driver_caps,
393 struct hda_tegra *hda)
395 static const struct snd_device_ops ops = {
396 .dev_disconnect = hda_tegra_dev_disconnect,
397 .dev_free = hda_tegra_dev_free,
404 mutex_init(&chip->open_mutex);
406 chip->ops = &hda_tegra_ops;
407 chip->driver_caps = driver_caps;
408 chip->driver_type = driver_caps & 0xff;
410 INIT_LIST_HEAD(&chip->pcm_list);
412 chip->codec_probe_mask = -1;
414 chip->single_cmd = false;
417 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
419 err = azx_bus_init(chip, NULL);
423 chip->bus.core.sync_write = 0;
424 chip->bus.core.needs_damn_long_delay = 1;
425 chip->bus.core.aligned_mmio = 1;
427 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
429 dev_err(card->dev, "Error creating device\n");
436 static const struct hda_tegra_soc tegra30_data = {
437 .has_hda2codec_2x_reset = true,
440 static const struct hda_tegra_soc tegra194_data = {
441 .has_hda2codec_2x_reset = false,
444 static const struct of_device_id hda_tegra_match[] = {
445 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
446 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
449 MODULE_DEVICE_TABLE(of, hda_tegra_match);
451 static int hda_tegra_probe(struct platform_device *pdev)
453 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
454 AZX_DCAPS_PM_RUNTIME |
455 AZX_DCAPS_4K_BDLE_BOUNDARY;
456 struct snd_card *card;
458 struct hda_tegra *hda;
461 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
464 hda->dev = &pdev->dev;
467 hda->soc = of_device_get_match_data(&pdev->dev);
469 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
470 THIS_MODULE, 0, &card);
472 dev_err(&pdev->dev, "Error creating card!\n");
476 hda->resets[hda->nresets++].id = "hda";
477 hda->resets[hda->nresets++].id = "hda2hdmi";
479 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
480 * be updated to reflect this, but to have backward compatibility
481 * below is necessary.
483 if (hda->soc->has_hda2codec_2x_reset)
484 hda->resets[hda->nresets++].id = "hda2codec_2x";
486 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
491 hda->clocks[hda->nclocks++].id = "hda";
492 hda->clocks[hda->nclocks++].id = "hda2hdmi";
493 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
495 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
499 err = hda_tegra_create(card, driver_flags, hda);
502 card->private_data = chip;
504 dev_set_drvdata(&pdev->dev, card);
506 pm_runtime_enable(hda->dev);
507 if (!azx_has_pm_runtime(chip))
508 pm_runtime_forbid(hda->dev);
510 schedule_work(&hda->probe_work);
519 static void hda_tegra_probe_work(struct work_struct *work)
521 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
522 struct azx *chip = &hda->chip;
523 struct platform_device *pdev = to_platform_device(hda->dev);
526 pm_runtime_get_sync(hda->dev);
527 err = hda_tegra_first_init(chip, pdev);
531 /* create codec instances */
532 err = azx_probe_codecs(chip, 8);
536 err = azx_codec_configure(chip);
540 err = snd_card_register(chip->card);
545 snd_hda_set_power_save(&chip->bus, power_save * 1000);
548 pm_runtime_put(hda->dev);
549 return; /* no error return from async probe */
552 static int hda_tegra_remove(struct platform_device *pdev)
556 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
557 pm_runtime_disable(&pdev->dev);
562 static void hda_tegra_shutdown(struct platform_device *pdev)
564 struct snd_card *card = dev_get_drvdata(&pdev->dev);
569 chip = card->private_data;
570 if (chip && chip->running)
574 static struct platform_driver tegra_platform_hda = {
578 .of_match_table = hda_tegra_match,
580 .probe = hda_tegra_probe,
581 .remove = hda_tegra_remove,
582 .shutdown = hda_tegra_shutdown,
584 module_platform_driver(tegra_platform_hda);
586 MODULE_DESCRIPTION("Tegra HDA bus driver");
587 MODULE_LICENSE("GPL v2");