sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81         POS_FIX_FIFO,
  82 };
  83
  84 /* Defines for ATI HD Audio support in SB450 south bridge */
  85 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  86 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  87
  88 /* Defines for Nvidia HDA support */
  89 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  90 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  91 #define NVIDIA_HDA_ISTRM_COH          0x4d
  92 #define NVIDIA_HDA_OSTRM_COH          0x4c
  93 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  94
  95 /* Defines for Intel SCH HDA snoop control */
  96 #define INTEL_HDA_CGCTL  0x48
  97 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  98 #define INTEL_SCH_HDA_DEVC      0x78
  99 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 100
 101 /* Define IN stream 0 FIFO size offset in VIA controller */
 102 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 103 /* Define VIA HD Audio Device ID*/
 104 #define VIA_HDAC_DEVICE_ID              0x3288
 105
 106 /* max number of SDs */
 107 /* ICH, ATI and VIA have 4 playback and 4 capture */
 108 #define ICH6_NUM_CAPTURE        4
 109 #define ICH6_NUM_PLAYBACK       4
 110
 111 /* ULI has 6 playback and 5 capture */
 112 #define ULI_NUM_CAPTURE         5
 113 #define ULI_NUM_PLAYBACK        6
 114
 115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 116 #define ATIHDMI_NUM_CAPTURE     0
 117 #define ATIHDMI_NUM_PLAYBACK    8
 118
 119 /* TERA has 4 playback and 3 capture */
 120 #define TERA_NUM_CAPTURE        3
 121 #define TERA_NUM_PLAYBACK       4
 122
 123
 124 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 125 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 126 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 127 static char *model[SNDRV_CARDS];
 128 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 131 static int probe_only[SNDRV_CARDS];
 132 static int jackpoll_ms[SNDRV_CARDS];
 133 static int single_cmd = -1;
 134 static int enable_msi = -1;
 135 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 136 static char *patch[SNDRV_CARDS];
 137 #endif
 138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 139 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 140                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 141 #endif
 142
 143 module_param_array(index, int, NULL, 0444);
 144 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 145 module_param_array(id, charp, NULL, 0444);
 146 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 147 module_param_array(enable, bool, NULL, 0444);
 148 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 149 module_param_array(model, charp, NULL, 0444);
 150 MODULE_PARM_DESC(model, "Use the given board model.");
 151 module_param_array(position_fix, int, NULL, 0444);
 152 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 153                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 154 module_param_array(bdl_pos_adj, int, NULL, 0644);
 155 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 156 module_param_array(probe_mask, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 158 module_param_array(probe_only, int, NULL, 0444);
 159 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 160 module_param_array(jackpoll_ms, int, NULL, 0444);
 161 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 162 module_param(single_cmd, bint, 0444);
 163 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 164                  "(for debugging only).");
 165 module_param(enable_msi, bint, 0444);
 166 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 167 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 168 module_param_array(patch, charp, NULL, 0444);
 169 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 170 #endif
 171 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 172 module_param_array(beep_mode, bool, NULL, 0444);
 173 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 174                             "(0=off, 1=on) (default=1).");
 175 #endif
 176
 177 #ifdef CONFIG_PM
 178 static int param_set_xint(const char *val, const struct kernel_param *kp);
 179 static const struct kernel_param_ops param_ops_xint = {
 180         .set = param_set_xint,
 181         .get = param_get_int,
 182 };
 183 #define param_check_xint param_check_int
 184
 185 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 186 module_param(power_save, xint, 0644);
 187 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 188                  "(in second, 0 = disable).");
 189
 190 static bool pm_blacklist = true;
 191 module_param(pm_blacklist, bool, 0644);
 192 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 193
 194 /* reset the HD-audio controller in power save mode.
 195  * this may give more power-saving, but will take longer time to
 196  * wake up.
 197  */
 198 static bool power_save_controller = 1;
 199 module_param(power_save_controller, bool, 0644);
 200 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 201 #else
 202 #define power_save      0
 203 #endif /* CONFIG_PM */
 204
 205 static int align_buffer_size = -1;
 206 module_param(align_buffer_size, bint, 0644);
 207 MODULE_PARM_DESC(align_buffer_size,
 208                 "Force buffer and period sizes to be multiple of 128 bytes.");
 209
 210 #ifdef CONFIG_X86
 211 static int hda_snoop = -1;
 212 module_param_named(snoop, hda_snoop, bint, 0444);
 213 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 214 #else
 215 #define hda_snoop               true
 216 #endif
 217
 218
 219 MODULE_LICENSE("GPL");
 220 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 221                          "{Intel, ICH6M},"
 222                          "{Intel, ICH7},"
 223                          "{Intel, ESB2},"
 224                          "{Intel, ICH8},"
 225                          "{Intel, ICH9},"
 226                          "{Intel, ICH10},"
 227                          "{Intel, PCH},"
 228                          "{Intel, CPT},"
 229                          "{Intel, PPT},"
 230                          "{Intel, LPT},"
 231                          "{Intel, LPT_LP},"
 232                          "{Intel, WPT_LP},"
 233                          "{Intel, SPT},"
 234                          "{Intel, SPT_LP},"
 235                          "{Intel, HPT},"
 236                          "{Intel, PBG},"
 237                          "{Intel, SCH},"
 238                          "{ATI, SB450},"
 239                          "{ATI, SB600},"
 240                          "{ATI, RS600},"
 241                          "{ATI, RS690},"
 242                          "{ATI, RS780},"
 243                          "{ATI, R600},"
 244                          "{ATI, RV630},"
 245                          "{ATI, RV610},"
 246                          "{ATI, RV670},"
 247                          "{ATI, RV635},"
 248                          "{ATI, RV620},"
 249                          "{ATI, RV770},"
 250                          "{VIA, VT8251},"
 251                          "{VIA, VT8237A},"
 252                          "{SiS, SIS966},"
 253                          "{ULI, M5461}}");
 254 MODULE_DESCRIPTION("Intel HDA driver");
 255
 256 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 257 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 258 #define SUPPORT_VGA_SWITCHEROO
 259 #endif
 260 #endif
 261
 262
 263 /*
 264  */
 265
 266 /* driver types */
 267 enum {
 268         AZX_DRIVER_ICH,
 269         AZX_DRIVER_PCH,
 270         AZX_DRIVER_SCH,
 271         AZX_DRIVER_SKL,
 272         AZX_DRIVER_HDMI,
 273         AZX_DRIVER_ATI,
 274         AZX_DRIVER_ATIHDMI,
 275         AZX_DRIVER_ATIHDMI_NS,
 276         AZX_DRIVER_VIA,
 277         AZX_DRIVER_SIS,
 278         AZX_DRIVER_ULI,
 279         AZX_DRIVER_NVIDIA,
 280         AZX_DRIVER_TERA,
 281         AZX_DRIVER_CTX,
 282         AZX_DRIVER_CTHDA,
 283         AZX_DRIVER_CMEDIA,
 284         AZX_DRIVER_GENERIC,
 285         AZX_NUM_DRIVERS, /* keep this as last entry */
 286 };
 287
 288 #define azx_get_snoop_type(chip) \
 289         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 290 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 291
 292 /* quirks for old Intel chipsets */
 293 #define AZX_DCAPS_INTEL_ICH \
 294         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 295
 296 /* quirks for Intel PCH */
 297 #define AZX_DCAPS_INTEL_PCH_BASE \
 298         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 302 #define AZX_DCAPS_INTEL_PCH_NOPM \
 303         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 304
 305 /* PCH for HSW/BDW; with runtime PM */
 306 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 307 #define AZX_DCAPS_INTEL_PCH \
 308         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 309
 310 /* HSW HDMI */
 311 #define AZX_DCAPS_INTEL_HASWELL \
 312         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 313          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 314          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 315
 316 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 317 #define AZX_DCAPS_INTEL_BROADWELL \
 318         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 320          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 321
 322 #define AZX_DCAPS_INTEL_BAYTRAIL \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 324          AZX_DCAPS_I915_POWERWELL)
 325
 326 #define AZX_DCAPS_INTEL_BRASWELL \
 327         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 328          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 329
 330 #define AZX_DCAPS_INTEL_SKYLAKE \
 331         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 332          AZX_DCAPS_SYNC_WRITE |\
 333          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 334          AZX_DCAPS_I915_POWERWELL)
 335
 336 #define AZX_DCAPS_INTEL_BROXTON                 AZX_DCAPS_INTEL_SKYLAKE
 337
 338 /* quirks for ATI SB / AMD Hudson */
 339 #define AZX_DCAPS_PRESET_ATI_SB \
 340         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 341          AZX_DCAPS_SNOOP_TYPE(ATI))
 342
 343 /* quirks for ATI/AMD HDMI */
 344 #define AZX_DCAPS_PRESET_ATI_HDMI \
 345         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 346          AZX_DCAPS_NO_MSI64)
 347
 348 /* quirks for ATI HDMI with snoop off */
 349 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 350         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 351
 352 /* quirks for AMD SB */
 353 #define AZX_DCAPS_PRESET_AMD_SB \
 354         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 355          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 356
 357 /* quirks for Nvidia */
 358 #define AZX_DCAPS_PRESET_NVIDIA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 360          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 361
 362 #define AZX_DCAPS_PRESET_CTHDA \
 363         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 364          AZX_DCAPS_NO_64BIT |\
 365          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 366
 367 /*
 368  * vga_switcheroo support
 369  */
 370 #ifdef SUPPORT_VGA_SWITCHEROO
 371 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 372 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 373 #else
 374 #define use_vga_switcheroo(chip)        0
 375 #define needs_eld_notify_link(chip)     false
 376 #endif
 377
 378 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 379                                         ((pci)->device == 0x0c0c) || \
 380                                         ((pci)->device == 0x0d0c) || \
 381                                         ((pci)->device == 0x160c))
 382
 383 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 384 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 385 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 386
 387 static char *driver_short_names[] = {
 388         [AZX_DRIVER_ICH] = "HDA Intel",
 389         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 390         [AZX_DRIVER_SCH] = "HDA Intel MID",
 391         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 392         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 393         [AZX_DRIVER_ATI] = "HDA ATI SB",
 394         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 395         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 396         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 397         [AZX_DRIVER_SIS] = "HDA SIS966",
 398         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 399         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 400         [AZX_DRIVER_TERA] = "HDA Teradici",
 401         [AZX_DRIVER_CTX] = "HDA Creative",
 402         [AZX_DRIVER_CTHDA] = "HDA Creative",
 403         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 404         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 405 };
 406
 407 #ifdef CONFIG_X86
 408 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 409 {
 410         int pages;
 411
 412         if (azx_snoop(chip))
 413                 return;
 414         if (!dmab || !dmab->area || !dmab->bytes)
 415                 return;
 416
 417 #ifdef CONFIG_SND_DMA_SGBUF
 418         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 419                 struct snd_sg_buf *sgbuf = dmab->private_data;
 420                 if (!chip->uc_buffer)
 421                         return; /* deal with only CORB/RIRB buffers */
 422                 if (on)
 423                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 424                 else
 425                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 426                 return;
 427         }
 428 #endif
 429
 430         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 431         if (on)
 432                 set_memory_wc((unsigned long)dmab->area, pages);
 433         else
 434                 set_memory_wb((unsigned long)dmab->area, pages);
 435 }
 436
 437 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 438                                  bool on)
 439 {
 440         __mark_pages_wc(chip, buf, on);
 441 }
 442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 443                                    struct snd_pcm_substream *substream, bool on)
 444 {
 445         if (azx_dev->wc_marked != on) {
 446                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 447                 azx_dev->wc_marked = on;
 448         }
 449 }
 450 #else
 451 /* NOP for other archs */
 452 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 453                                  bool on)
 454 {
 455 }
 456 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 457                                    struct snd_pcm_substream *substream, bool on)
 458 {
 459 }
 460 #endif
 461
 462 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 463 static void set_default_power_save(struct azx *chip);
 464
 465 /*
 466  * initialize the PCI registers
 467  */
 468 /* update bits in a PCI register byte */
 469 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 470                             unsigned char mask, unsigned char val)
 471 {
 472         unsigned char data;
 473
 474         pci_read_config_byte(pci, reg, &data);
 475         data &= ~mask;
 476         data |= (val & mask);
 477         pci_write_config_byte(pci, reg, data);
 478 }
 479
 480 static void azx_init_pci(struct azx *chip)
 481 {
 482         int snoop_type = azx_get_snoop_type(chip);
 483
 484         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 485          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 486          * Ensuring these bits are 0 clears playback static on some HD Audio
 487          * codecs.
 488          * The PCI register TCSEL is defined in the Intel manuals.
 489          */
 490         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 491                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 492                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 493         }
 494
 495         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 496          * we need to enable snoop.
 497          */
 498         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 499                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 500                         azx_snoop(chip));
 501                 update_pci_byte(chip->pci,
 502                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 503                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 504         }
 505
 506         /* For NVIDIA HDA, enable snoop */
 507         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 508                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 509                         azx_snoop(chip));
 510                 update_pci_byte(chip->pci,
 511                                 NVIDIA_HDA_TRANSREG_ADDR,
 512                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 513                 update_pci_byte(chip->pci,
 514                                 NVIDIA_HDA_ISTRM_COH,
 515                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 516                 update_pci_byte(chip->pci,
 517                                 NVIDIA_HDA_OSTRM_COH,
 518                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 519         }
 520
 521         /* Enable SCH/PCH snoop if needed */
 522         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 523                 unsigned short snoop;
 524                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 525                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 526                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 527                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 528                         if (!azx_snoop(chip))
 529                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 530                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 531                         pci_read_config_word(chip->pci,
 532                                 INTEL_SCH_HDA_DEVC, &snoop);
 533                 }
 534                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 535                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 536                         "Disabled" : "Enabled");
 537         }
 538 }
 539
 540 /*
 541  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 542  * and makes an audio stream sensitive to system latencies when
 543  * 24/32 bits are playing.
 544  * Adjusting threshold of DMA fifo to force the DMA request
 545  * sooner to improve latency tolerance at the expense of power.
 546  */
 547 static void bxt_reduce_dma_latency(struct azx *chip)
 548 {
 549         u32 val;
 550
 551         val = azx_readl(chip, VS_EM4L);
 552         val &= (0x3 << 20);
 553         azx_writel(chip, VS_EM4L, val);
 554 }
 555
 556 /*
 557  * ML_LCAP bits:
 558  *  bit 0: 6 MHz Supported
 559  *  bit 1: 12 MHz Supported
 560  *  bit 2: 24 MHz Supported
 561  *  bit 3: 48 MHz Supported
 562  *  bit 4: 96 MHz Supported
 563  *  bit 5: 192 MHz Supported
 564  */
 565 static int intel_get_lctl_scf(struct azx *chip)
 566 {
 567         struct hdac_bus *bus = azx_bus(chip);
 568         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 569         u32 val, t;
 570         int i;
 571
 572         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 573
 574         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 575                 t = preferred_bits[i];
 576                 if (val & (1 << t))
 577                         return t;
 578         }
 579
 580         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 581         return 0;
 582 }
 583
 584 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 585 {
 586         struct hdac_bus *bus = azx_bus(chip);
 587         u32 val;
 588         int timeout;
 589
 590         /*
 591          * the codecs are sharing the first link setting by default
 592          * If other links are enabled for stream, they need similar fix
 593          */
 594         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 595         val &= ~AZX_MLCTL_SPA;
 596         val |= state << AZX_MLCTL_SPA_SHIFT;
 597         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 598         /* wait for CPA */
 599         timeout = 50;
 600         while (timeout) {
 601                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 602                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 603                         return 0;
 604                 timeout--;
 605                 udelay(10);
 606         }
 607
 608         return -1;
 609 }
 610
 611 static void intel_init_lctl(struct azx *chip)
 612 {
 613         struct hdac_bus *bus = azx_bus(chip);
 614         u32 val;
 615         int ret;
 616
 617         /* 0. check lctl register value is correct or not */
 618         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 619         /* if SCF is already set, let's use it */
 620         if ((val & ML_LCTL_SCF_MASK) != 0)
 621                 return;
 622
 623         /*
 624          * Before operating on SPA, CPA must match SPA.
 625          * Any deviation may result in undefined behavior.
 626          */
 627         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 628                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 629                 return;
 630
 631         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 632         ret = intel_ml_lctl_set_power(chip, 0);
 633         udelay(100);
 634         if (ret)
 635                 goto set_spa;
 636
 637         /* 2. update SCF to select a properly audio clock*/
 638         val &= ~ML_LCTL_SCF_MASK;
 639         val |= intel_get_lctl_scf(chip);
 640         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 641
 642 set_spa:
 643         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 644         intel_ml_lctl_set_power(chip, 1);
 645         udelay(100);
 646 }
 647
 648 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 649 {
 650         struct hdac_bus *bus = azx_bus(chip);
 651         struct pci_dev *pci = chip->pci;
 652         u32 val;
 653
 654         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 655                 snd_hdac_set_codec_wakeup(bus, true);
 656         if (chip->driver_type == AZX_DRIVER_SKL) {
 657                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 658                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 659                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 660         }
 661         azx_init_chip(chip, full_reset);
 662         if (chip->driver_type == AZX_DRIVER_SKL) {
 663                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 664                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 665                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 666         }
 667         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 668                 snd_hdac_set_codec_wakeup(bus, false);
 669
 670         /* reduce dma latency to avoid noise */
 671         if (IS_BXT(pci))
 672                 bxt_reduce_dma_latency(chip);
 673
 674         if (bus->mlcap != NULL)
 675                 intel_init_lctl(chip);
 676 }
 677
 678 /* calculate runtime delay from LPIB */
 679 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 680                                    unsigned int pos)
 681 {
 682         struct snd_pcm_substream *substream = azx_dev->core.substream;
 683         int stream = substream->stream;
 684         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 685         int delay;
 686
 687         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 688                 delay = pos - lpib_pos;
 689         else
 690                 delay = lpib_pos - pos;
 691         if (delay < 0) {
 692                 if (delay >= azx_dev->core.delay_negative_threshold)
 693                         delay = 0;
 694                 else
 695                         delay += azx_dev->core.bufsize;
 696         }
 697
 698         if (delay >= azx_dev->core.period_bytes) {
 699                 dev_info(chip->card->dev,
 700                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 701                          delay, azx_dev->core.period_bytes);
 702                 delay = 0;
 703                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 704                 chip->get_delay[stream] = NULL;
 705         }
 706
 707         return bytes_to_frames(substream->runtime, delay);
 708 }
 709
 710 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 711
 712 /* called from IRQ */
 713 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 714 {
 715         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 716         int ok;
 717
 718         ok = azx_position_ok(chip, azx_dev);
 719         if (ok == 1) {
 720                 azx_dev->irq_pending = 0;
 721                 return ok;
 722         } else if (ok == 0) {
 723                 /* bogus IRQ, process it later */
 724                 azx_dev->irq_pending = 1;
 725                 schedule_work(&hda->irq_pending_work);
 726         }
 727         return 0;
 728 }
 729
 730 /* Enable/disable i915 display power for the link */
 731 static int azx_intel_link_power(struct azx *chip, bool enable)
 732 {
 733         struct hdac_bus *bus = azx_bus(chip);
 734
 735         return snd_hdac_display_power(bus, enable);
 736 }
 737
 738 /*
 739  * Check whether the current DMA position is acceptable for updating
 740  * periods.  Returns non-zero if it's OK.
 741  *
 742  * Many HD-audio controllers appear pretty inaccurate about
 743  * the update-IRQ timing.  The IRQ is issued before actually the
 744  * data is processed.  So, we need to process it afterwords in a
 745  * workqueue.
 746  *
 747  * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
 748  */
 749 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 750 {
 751         struct snd_pcm_substream *substream = azx_dev->core.substream;
 752         struct snd_pcm_runtime *runtime = substream->runtime;
 753         int stream = substream->stream;
 754         u32 wallclk;
 755         unsigned int pos;
 756         snd_pcm_uframes_t hwptr, target;
 757
 758         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 759         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 760                 return -1;      /* bogus (too early) interrupt */
 761
 762         if (chip->get_position[stream])
 763                 pos = chip->get_position[stream](chip, azx_dev);
 764         else { /* use the position buffer as default */
 765                 pos = azx_get_pos_posbuf(chip, azx_dev);
 766                 if (!pos || pos == (u32)-1) {
 767                         dev_info(chip->card->dev,
 768                                  "Invalid position buffer, using LPIB read method instead.\n");
 769                         chip->get_position[stream] = azx_get_pos_lpib;
 770                         if (chip->get_position[0] == azx_get_pos_lpib &&
 771                             chip->get_position[1] == azx_get_pos_lpib)
 772                                 azx_bus(chip)->use_posbuf = false;
 773                         pos = azx_get_pos_lpib(chip, azx_dev);
 774                         chip->get_delay[stream] = NULL;
 775                 } else {
 776                         chip->get_position[stream] = azx_get_pos_posbuf;
 777                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 778                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 779                 }
 780         }
 781
 782         if (pos >= azx_dev->core.bufsize)
 783                 pos = 0;
 784
 785         if (WARN_ONCE(!azx_dev->core.period_bytes,
 786                       "hda-intel: zero azx_dev->period_bytes"))
 787                 return -1; /* this shouldn't happen! */
 788         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 789             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 790                 /* NG - it's below the first next period boundary */
 791                 return chip->bdl_pos_adj ? 0 : -1;
 792         azx_dev->core.start_wallclk += wallclk;
 793
 794         if (azx_dev->core.no_period_wakeup)
 795                 return 1; /* OK, no need to check period boundary */
 796
 797         if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
 798                 return 1; /* OK, already in hwptr updating process */
 799
 800         /* check whether the period gets really elapsed */
 801         pos = bytes_to_frames(runtime, pos);
 802         hwptr = runtime->hw_ptr_base + pos;
 803         if (hwptr < runtime->status->hw_ptr)
 804                 hwptr += runtime->buffer_size;
 805         target = runtime->hw_ptr_interrupt + runtime->period_size;
 806         if (hwptr < target) {
 807                 /* too early wakeup, process it later */
 808                 return chip->bdl_pos_adj ? 0 : -1;
 809         }
 810
 811         return 1; /* OK, it's fine */
 812 }
 813
 814 /*
 815  * The work for pending PCM period updates.
 816  */
 817 static void azx_irq_pending_work(struct work_struct *work)
 818 {
 819         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 820         struct azx *chip = &hda->chip;
 821         struct hdac_bus *bus = azx_bus(chip);
 822         struct hdac_stream *s;
 823         int pending, ok;
 824
 825         if (!hda->irq_pending_warned) {
 826                 dev_info(chip->card->dev,
 827                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 828                          chip->card->number);
 829                 hda->irq_pending_warned = 1;
 830         }
 831
 832         for (;;) {
 833                 pending = 0;
 834                 spin_lock_irq(&bus->reg_lock);
 835                 list_for_each_entry(s, &bus->stream_list, list) {
 836                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 837                         if (!azx_dev->irq_pending ||
 838                             !s->substream ||
 839                             !s->running)
 840                                 continue;
 841                         ok = azx_position_ok(chip, azx_dev);
 842                         if (ok > 0) {
 843                                 azx_dev->irq_pending = 0;
 844                                 spin_unlock(&bus->reg_lock);
 845                                 snd_pcm_period_elapsed(s->substream);
 846                                 spin_lock(&bus->reg_lock);
 847                         } else if (ok < 0) {
 848                                 pending = 0;    /* too early */
 849                         } else
 850                                 pending++;
 851                 }
 852                 spin_unlock_irq(&bus->reg_lock);
 853                 if (!pending)
 854                         return;
 855                 msleep(1);
 856         }
 857 }
 858
 859 /* clear irq_pending flags and assure no on-going workq */
 860 static void azx_clear_irq_pending(struct azx *chip)
 861 {
 862         struct hdac_bus *bus = azx_bus(chip);
 863         struct hdac_stream *s;
 864
 865         spin_lock_irq(&bus->reg_lock);
 866         list_for_each_entry(s, &bus->stream_list, list) {
 867                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 868                 azx_dev->irq_pending = 0;
 869         }
 870         spin_unlock_irq(&bus->reg_lock);
 871 }
 872
 873 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 874 {
 875         struct hdac_bus *bus = azx_bus(chip);
 876
 877         if (request_irq(chip->pci->irq, azx_interrupt,
 878                         chip->msi ? 0 : IRQF_SHARED,
 879                         chip->card->irq_descr, chip)) {
 880                 dev_err(chip->card->dev,
 881                         "unable to grab IRQ %d, disabling device\n",
 882                         chip->pci->irq);
 883                 if (do_disconnect)
 884                         snd_card_disconnect(chip->card);
 885                 return -1;
 886         }
 887         bus->irq = chip->pci->irq;
 888         pci_intx(chip->pci, !chip->msi);
 889         return 0;
 890 }
 891
 892 /* get the current DMA position with correction on VIA chips */
 893 static unsigned int azx_via_get_position(struct azx *chip,
 894                                          struct azx_dev *azx_dev)
 895 {
 896         unsigned int link_pos, mini_pos, bound_pos;
 897         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 898         unsigned int fifo_size;
 899
 900         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 901         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 902                 /* Playback, no problem using link position */
 903                 return link_pos;
 904         }
 905
 906         /* Capture */
 907         /* For new chipset,
 908          * use mod to get the DMA position just like old chipset
 909          */
 910         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 911         mod_dma_pos %= azx_dev->core.period_bytes;
 912
 913         /* azx_dev->fifo_size can't get FIFO size of in stream.
 914          * Get from base address + offset.
 915          */
 916         fifo_size = readw(azx_bus(chip)->remap_addr +
 917                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 918
 919         if (azx_dev->insufficient) {
 920                 /* Link position never gather than FIFO size */
 921                 if (link_pos <= fifo_size)
 922                         return 0;
 923
 924                 azx_dev->insufficient = 0;
 925         }
 926
 927         if (link_pos <= fifo_size)
 928                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 929         else
 930                 mini_pos = link_pos - fifo_size;
 931
 932         /* Find nearest previous boudary */
 933         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 934         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 935         if (mod_link_pos >= fifo_size)
 936                 bound_pos = link_pos - mod_link_pos;
 937         else if (mod_dma_pos >= mod_mini_pos)
 938                 bound_pos = mini_pos - mod_mini_pos;
 939         else {
 940                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 941                 if (bound_pos >= azx_dev->core.bufsize)
 942                         bound_pos = 0;
 943         }
 944
 945         /* Calculate real DMA position we want */
 946         return bound_pos + mod_dma_pos;
 947 }
 948
 949 #define AMD_FIFO_SIZE   32
 950
 951 /* get the current DMA position with FIFO size correction */
 952 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 953 {
 954         struct snd_pcm_substream *substream = azx_dev->core.substream;
 955         struct snd_pcm_runtime *runtime = substream->runtime;
 956         unsigned int pos, delay;
 957
 958         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 959         if (!runtime)
 960                 return pos;
 961
 962         runtime->delay = AMD_FIFO_SIZE;
 963         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 964         if (azx_dev->insufficient) {
 965                 if (pos < delay) {
 966                         delay = pos;
 967                         runtime->delay = bytes_to_frames(runtime, pos);
 968                 } else {
 969                         azx_dev->insufficient = 0;
 970                 }
 971         }
 972
 973         /* correct the DMA position for capture stream */
 974         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 975                 if (pos < delay)
 976                         pos += azx_dev->core.bufsize;
 977                 pos -= delay;
 978         }
 979
 980         return pos;
 981 }
 982
 983 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 984                                    unsigned int pos)
 985 {
 986         struct snd_pcm_substream *substream = azx_dev->core.substream;
 987
 988         /* just read back the calculated value in the above */
 989         return substream->runtime->delay;
 990 }
 991
 992 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 993                                          struct azx_dev *azx_dev)
 994 {
 995         return _snd_hdac_chip_readl(azx_bus(chip),
 996                                     AZX_REG_VS_SDXDPIB_XBASE +
 997                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 998                                      azx_dev->core.index));
 999 }
1000
1001 /* get the current DMA position with correction on SKL+ chips */
1002 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
1003 {
1004         /* DPIB register gives a more accurate position for playback */
1005         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1006                 return azx_skl_get_dpib_pos(chip, azx_dev);
1007
1008         /* read of DPIB fetches the actual posbuf */
1009         azx_skl_get_dpib_pos(chip, azx_dev);
1010         return azx_get_pos_posbuf(chip, azx_dev);
1011 }
1012
1013 #ifdef CONFIG_PM
1014 static DEFINE_MUTEX(card_list_lock);
1015 static LIST_HEAD(card_list);
1016
1017 static void azx_add_card_list(struct azx *chip)
1018 {
1019         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1020         mutex_lock(&card_list_lock);
1021         list_add(&hda->list, &card_list);
1022         mutex_unlock(&card_list_lock);
1023 }
1024
1025 static void azx_del_card_list(struct azx *chip)
1026 {
1027         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1028         mutex_lock(&card_list_lock);
1029         list_del_init(&hda->list);
1030         mutex_unlock(&card_list_lock);
1031 }
1032
1033 /* trigger power-save check at writing parameter */
1034 static int param_set_xint(const char *val, const struct kernel_param *kp)
1035 {
1036         struct hda_intel *hda;
1037         struct azx *chip;
1038         int prev = power_save;
1039         int ret = param_set_int(val, kp);
1040
1041         if (ret || prev == power_save)
1042                 return ret;
1043
1044         mutex_lock(&card_list_lock);
1045         list_for_each_entry(hda, &card_list, list) {
1046                 chip = &hda->chip;
1047                 if (!hda->probe_continued || chip->disabled)
1048                         continue;
1049                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1050         }
1051         mutex_unlock(&card_list_lock);
1052         return 0;
1053 }
1054 #else
1055 #define azx_add_card_list(chip) /* NOP */
1056 #define azx_del_card_list(chip) /* NOP */
1057 #endif /* CONFIG_PM */
1058
1059 #ifdef CONFIG_PM_SLEEP
1060 /*
1061  * power management
1062  */
1063 static int azx_suspend(struct device *dev)
1064 {
1065         struct snd_card *card = dev_get_drvdata(dev);
1066         struct azx *chip;
1067         struct hda_intel *hda;
1068         struct hdac_bus *bus;
1069
1070         if (!card)
1071                 return 0;
1072
1073         chip = card->private_data;
1074         hda = container_of(chip, struct hda_intel, chip);
1075         if (chip->disabled || hda->init_failed || !chip->running)
1076                 return 0;
1077
1078         bus = azx_bus(chip);
1079         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1080         azx_clear_irq_pending(chip);
1081         azx_stop_chip(chip);
1082         azx_enter_link_reset(chip);
1083         if (bus->irq >= 0) {
1084                 free_irq(bus->irq, chip);
1085                 bus->irq = -1;
1086         }
1087
1088         if (chip->msi)
1089                 pci_disable_msi(chip->pci);
1090         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1091                 && hda->need_i915_power)
1092                 snd_hdac_display_power(bus, false);
1093
1094         trace_azx_suspend(chip);
1095         return 0;
1096 }
1097
1098 static int azx_resume(struct device *dev)
1099 {
1100         struct pci_dev *pci = to_pci_dev(dev);
1101         struct snd_card *card = dev_get_drvdata(dev);
1102         struct azx *chip;
1103         struct hda_intel *hda;
1104         struct hdac_bus *bus;
1105
1106         if (!card)
1107                 return 0;
1108
1109         chip = card->private_data;
1110         hda = container_of(chip, struct hda_intel, chip);
1111         bus = azx_bus(chip);
1112         if (chip->disabled || hda->init_failed || !chip->running)
1113                 return 0;
1114
1115         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1116                 snd_hdac_display_power(bus, true);
1117                 if (hda->need_i915_power)
1118                         snd_hdac_i915_set_bclk(bus);
1119         }
1120
1121         if (chip->msi)
1122                 if (pci_enable_msi(pci) < 0)
1123                         chip->msi = 0;
1124         if (azx_acquire_irq(chip, 1) < 0)
1125                 return -EIO;
1126         azx_init_pci(chip);
1127
1128         hda_intel_init_chip(chip, true);
1129
1130         /* power down again for link-controlled chips */
1131         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1132             !hda->need_i915_power)
1133                 snd_hdac_display_power(bus, false);
1134
1135         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1136
1137         trace_azx_resume(chip);
1138         return 0;
1139 }
1140
1141 /* put codec down to D3 at hibernation for Intel SKL+;
1142  * otherwise BIOS may still access the codec and screw up the driver
1143  */
1144 static int azx_freeze_noirq(struct device *dev)
1145 {
1146         struct snd_card *card = dev_get_drvdata(dev);
1147         struct azx *chip = card->private_data;
1148         struct pci_dev *pci = to_pci_dev(dev);
1149
1150         if (chip->driver_type == AZX_DRIVER_SKL)
1151                 pci_set_power_state(pci, PCI_D3hot);
1152
1153         return 0;
1154 }
1155
1156 static int azx_thaw_noirq(struct device *dev)
1157 {
1158         struct snd_card *card = dev_get_drvdata(dev);
1159         struct azx *chip = card->private_data;
1160         struct pci_dev *pci = to_pci_dev(dev);
1161
1162         if (chip->driver_type == AZX_DRIVER_SKL)
1163                 pci_set_power_state(pci, PCI_D0);
1164
1165         return 0;
1166 }
1167 #endif /* CONFIG_PM_SLEEP */
1168
1169 #ifdef CONFIG_PM
1170 static int azx_runtime_suspend(struct device *dev)
1171 {
1172         struct snd_card *card = dev_get_drvdata(dev);
1173         struct azx *chip;
1174         struct hda_intel *hda;
1175
1176         if (!card)
1177                 return 0;
1178
1179         chip = card->private_data;
1180         hda = container_of(chip, struct hda_intel, chip);
1181         if (chip->disabled || hda->init_failed)
1182                 return 0;
1183
1184         if (!azx_has_pm_runtime(chip))
1185                 return 0;
1186
1187         /* enable controller wake up event */
1188         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1189                   STATESTS_INT_MASK);
1190
1191         azx_stop_chip(chip);
1192         azx_enter_link_reset(chip);
1193         azx_clear_irq_pending(chip);
1194         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1195                 && hda->need_i915_power)
1196                 snd_hdac_display_power(azx_bus(chip), false);
1197
1198         trace_azx_runtime_suspend(chip);
1199         return 0;
1200 }
1201
1202 static int azx_runtime_resume(struct device *dev)
1203 {
1204         struct snd_card *card = dev_get_drvdata(dev);
1205         struct azx *chip;
1206         struct hda_intel *hda;
1207         struct hdac_bus *bus;
1208         struct hda_codec *codec;
1209         int status;
1210
1211         if (!card)
1212                 return 0;
1213
1214         chip = card->private_data;
1215         hda = container_of(chip, struct hda_intel, chip);
1216         bus = azx_bus(chip);
1217         if (chip->disabled || hda->init_failed)
1218                 return 0;
1219
1220         if (!azx_has_pm_runtime(chip))
1221                 return 0;
1222
1223         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1224                 snd_hdac_display_power(bus, true);
1225                 if (hda->need_i915_power)
1226                         snd_hdac_i915_set_bclk(bus);
1227         }
1228
1229         /* Read STATESTS before controller reset */
1230         status = azx_readw(chip, STATESTS);
1231
1232         azx_init_pci(chip);
1233         hda_intel_init_chip(chip, true);
1234
1235         if (status) {
1236                 list_for_each_codec(codec, &chip->bus)
1237                         if (status & (1 << codec->addr))
1238                                 schedule_delayed_work(&codec->jackpoll_work,
1239                                                       codec->jackpoll_interval);
1240         }
1241
1242         /* disable controller Wake Up event*/
1243         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1244                         ~STATESTS_INT_MASK);
1245
1246         /* power down again for link-controlled chips */
1247         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1248             !hda->need_i915_power)
1249                 snd_hdac_display_power(bus, false);
1250
1251         trace_azx_runtime_resume(chip);
1252         return 0;
1253 }
1254
1255 static int azx_runtime_idle(struct device *dev)
1256 {
1257         struct snd_card *card = dev_get_drvdata(dev);
1258         struct azx *chip;
1259         struct hda_intel *hda;
1260
1261         if (!card)
1262                 return 0;
1263
1264         chip = card->private_data;
1265         hda = container_of(chip, struct hda_intel, chip);
1266         if (chip->disabled || hda->init_failed)
1267                 return 0;
1268
1269         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1270             azx_bus(chip)->codec_powered || !chip->running)
1271                 return -EBUSY;
1272
1273         /* ELD notification gets broken when HD-audio bus is off */
1274         if (needs_eld_notify_link(hda))
1275                 return -EBUSY;
1276
1277         return 0;
1278 }
1279
1280 static const struct dev_pm_ops azx_pm = {
1281         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1282 #ifdef CONFIG_PM_SLEEP
1283         .freeze_noirq = azx_freeze_noirq,
1284         .thaw_noirq = azx_thaw_noirq,
1285 #endif
1286         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1287 };
1288
1289 #define AZX_PM_OPS      &azx_pm
1290 #else
1291 #define AZX_PM_OPS      NULL
1292 #endif /* CONFIG_PM */
1293
1294
1295 static int azx_probe_continue(struct azx *chip);
1296
1297 #ifdef SUPPORT_VGA_SWITCHEROO
1298 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1299
1300 static void azx_vs_set_state(struct pci_dev *pci,
1301                              enum vga_switcheroo_state state)
1302 {
1303         struct snd_card *card = pci_get_drvdata(pci);
1304         struct azx *chip = card->private_data;
1305         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1306         struct hda_codec *codec;
1307         bool disabled;
1308
1309         wait_for_completion(&hda->probe_wait);
1310         if (hda->init_failed)
1311                 return;
1312
1313         disabled = (state == VGA_SWITCHEROO_OFF);
1314         if (chip->disabled == disabled)
1315                 return;
1316
1317         if (!hda->probe_continued) {
1318                 chip->disabled = disabled;
1319                 if (!disabled) {
1320                         dev_info(chip->card->dev,
1321                                  "Start delayed initialization\n");
1322                         if (azx_probe_continue(chip) < 0) {
1323                                 dev_err(chip->card->dev, "initialization error\n");
1324                                 hda->init_failed = true;
1325                         }
1326                 }
1327         } else {
1328                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1329                          disabled ? "Disabling" : "Enabling");
1330                 if (disabled) {
1331                         list_for_each_codec(codec, &chip->bus) {
1332                                 pm_runtime_suspend(hda_codec_dev(codec));
1333                                 pm_runtime_disable(hda_codec_dev(codec));
1334                         }
1335                         pm_runtime_suspend(card->dev);
1336                         pm_runtime_disable(card->dev);
1337                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1338                          * however we have no ACPI handle, so pci/acpi can't put us there,
1339                          * put ourselves there */
1340                         pci->current_state = PCI_D3cold;
1341                         chip->disabled = true;
1342                         if (snd_hda_lock_devices(&chip->bus))
1343                                 dev_warn(chip->card->dev,
1344                                          "Cannot lock devices!\n");
1345                 } else {
1346                         snd_hda_unlock_devices(&chip->bus);
1347                         chip->disabled = false;
1348                         pm_runtime_enable(card->dev);
1349                         list_for_each_codec(codec, &chip->bus) {
1350                                 pm_runtime_enable(hda_codec_dev(codec));
1351                                 pm_runtime_resume(hda_codec_dev(codec));
1352                         }
1353                 }
1354         }
1355 }
1356
1357 static bool azx_vs_can_switch(struct pci_dev *pci)
1358 {
1359         struct snd_card *card = pci_get_drvdata(pci);
1360         struct azx *chip = card->private_data;
1361         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1362
1363         wait_for_completion(&hda->probe_wait);
1364         if (hda->init_failed)
1365                 return false;
1366         if (chip->disabled || !hda->probe_continued)
1367                 return true;
1368         if (snd_hda_lock_devices(&chip->bus))
1369                 return false;
1370         snd_hda_unlock_devices(&chip->bus);
1371         return true;
1372 }
1373
1374 /*
1375  * The discrete GPU cannot power down unless the HDA controller runtime
1376  * suspends, so activate runtime PM on codecs even if power_save == 0.
1377  */
1378 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1379 {
1380         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1381         struct hda_codec *codec;
1382
1383         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1384                 list_for_each_codec(codec, &chip->bus)
1385                         codec->auto_runtime_pm = 1;
1386                 /* reset the power save setup */
1387                 if (chip->running)
1388                         set_default_power_save(chip);
1389         }
1390 }
1391
1392 static void azx_vs_gpu_bound(struct pci_dev *pci,
1393                              enum vga_switcheroo_client_id client_id)
1394 {
1395         struct snd_card *card = pci_get_drvdata(pci);
1396         struct azx *chip = card->private_data;
1397         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1398
1399         if (client_id == VGA_SWITCHEROO_DIS)
1400                 hda->need_eld_notify_link = 0;
1401         setup_vga_switcheroo_runtime_pm(chip);
1402 }
1403
1404 static void init_vga_switcheroo(struct azx *chip)
1405 {
1406         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1407         struct pci_dev *p = get_bound_vga(chip->pci);
1408         if (p) {
1409                 dev_info(chip->card->dev,
1410                          "Handle vga_switcheroo audio client\n");
1411                 hda->use_vga_switcheroo = 1;
1412                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1413                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1414                 pci_dev_put(p);
1415         }
1416 }
1417
1418 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1419         .set_gpu_state = azx_vs_set_state,
1420         .can_switch = azx_vs_can_switch,
1421         .gpu_bound = azx_vs_gpu_bound,
1422 };
1423
1424 static int register_vga_switcheroo(struct azx *chip)
1425 {
1426         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1427         struct pci_dev *p;
1428         int err;
1429
1430         if (!hda->use_vga_switcheroo)
1431                 return 0;
1432
1433         p = get_bound_vga(chip->pci);
1434         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1435         pci_dev_put(p);
1436
1437         if (err < 0)
1438                 return err;
1439         hda->vga_switcheroo_registered = 1;
1440
1441         return 0;
1442 }
1443 #else
1444 #define init_vga_switcheroo(chip)               /* NOP */
1445 #define register_vga_switcheroo(chip)           0
1446 #define check_hdmi_disabled(pci)        false
1447 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1448 #endif /* SUPPORT_VGA_SWITCHER */
1449
1450 /*
1451  * destructor
1452  */
1453 static int azx_free(struct azx *chip)
1454 {
1455         struct pci_dev *pci = chip->pci;
1456         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1457         struct hdac_bus *bus = azx_bus(chip);
1458
1459         if (azx_has_pm_runtime(chip) && chip->running)
1460                 pm_runtime_get_noresume(&pci->dev);
1461         chip->running = 0;
1462
1463         azx_del_card_list(chip);
1464
1465         hda->init_failed = 1; /* to be sure */
1466         complete_all(&hda->probe_wait);
1467
1468         if (use_vga_switcheroo(hda)) {
1469                 if (chip->disabled && hda->probe_continued)
1470                         snd_hda_unlock_devices(&chip->bus);
1471                 if (hda->vga_switcheroo_registered)
1472                         vga_switcheroo_unregister_client(chip->pci);
1473         }
1474
1475         if (bus->chip_init) {
1476                 azx_clear_irq_pending(chip);
1477                 azx_stop_all_streams(chip);
1478                 azx_stop_chip(chip);
1479         }
1480
1481         if (bus->irq >= 0)
1482                 free_irq(bus->irq, (void*)chip);
1483         if (chip->msi)
1484                 pci_disable_msi(chip->pci);
1485         iounmap(bus->remap_addr);
1486
1487         azx_free_stream_pages(chip);
1488         azx_free_streams(chip);
1489         snd_hdac_bus_exit(bus);
1490
1491         if (chip->region_requested)
1492                 pci_release_regions(chip->pci);
1493
1494         pci_disable_device(chip->pci);
1495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1496         release_firmware(chip->fw);
1497 #endif
1498
1499         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1500                 if (hda->need_i915_power)
1501                         snd_hdac_display_power(bus, false);
1502         }
1503         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1504                 snd_hdac_i915_exit(bus);
1505         kfree(hda);
1506
1507         return 0;
1508 }
1509
1510 static int azx_dev_disconnect(struct snd_device *device)
1511 {
1512         struct azx *chip = device->device_data;
1513         struct hdac_bus *bus = azx_bus(chip);
1514
1515         chip->bus.shutdown = 1;
1516         cancel_work_sync(&bus->unsol_work);
1517
1518         return 0;
1519 }
1520
1521 static int azx_dev_free(struct snd_device *device)
1522 {
1523         return azx_free(device->device_data);
1524 }
1525
1526 #ifdef SUPPORT_VGA_SWITCHEROO
1527 /*
1528  * Check of disabled HDMI controller by vga_switcheroo
1529  */
1530 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1531 {
1532         struct pci_dev *p;
1533
1534         /* check only discrete GPU */
1535         switch (pci->vendor) {
1536         case PCI_VENDOR_ID_ATI:
1537         case PCI_VENDOR_ID_AMD:
1538         case PCI_VENDOR_ID_NVIDIA:
1539                 if (pci->devfn == 1) {
1540                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1541                                                         pci->bus->number, 0);
1542                         if (p) {
1543                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1544                                         return p;
1545                                 pci_dev_put(p);
1546                         }
1547                 }
1548                 break;
1549         }
1550         return NULL;
1551 }
1552
1553 static bool check_hdmi_disabled(struct pci_dev *pci)
1554 {
1555         bool vga_inactive = false;
1556         struct pci_dev *p = get_bound_vga(pci);
1557
1558         if (p) {
1559                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1560                         vga_inactive = true;
1561                 pci_dev_put(p);
1562         }
1563         return vga_inactive;
1564 }
1565 #endif /* SUPPORT_VGA_SWITCHEROO */
1566
1567 /*
1568  * white/black-listing for position_fix
1569  */
1570 static struct snd_pci_quirk position_fix_list[] = {
1571         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1572         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1573         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1574         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1575         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1576         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1577         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1578         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1579         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1580         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1581         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1582         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1583         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1584         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1585         {}
1586 };
1587
1588 static int check_position_fix(struct azx *chip, int fix)
1589 {
1590         const struct snd_pci_quirk *q;
1591
1592         switch (fix) {
1593         case POS_FIX_AUTO:
1594         case POS_FIX_LPIB:
1595         case POS_FIX_POSBUF:
1596         case POS_FIX_VIACOMBO:
1597         case POS_FIX_COMBO:
1598         case POS_FIX_SKL:
1599         case POS_FIX_FIFO:
1600                 return fix;
1601         }
1602
1603         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1604         if (q) {
1605                 dev_info(chip->card->dev,
1606                          "position_fix set to %d for device %04x:%04x\n",
1607                          q->value, q->subvendor, q->subdevice);
1608                 return q->value;
1609         }
1610
1611         /* Check VIA/ATI HD Audio Controller exist */
1612         if (chip->driver_type == AZX_DRIVER_VIA) {
1613                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1614                 return POS_FIX_VIACOMBO;
1615         }
1616         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1617                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1618                 return POS_FIX_FIFO;
1619         }
1620         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1621                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1622                 return POS_FIX_LPIB;
1623         }
1624         if (chip->driver_type == AZX_DRIVER_SKL) {
1625                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1626                 return POS_FIX_SKL;
1627         }
1628         return POS_FIX_AUTO;
1629 }
1630
1631 static void assign_position_fix(struct azx *chip, int fix)
1632 {
1633         static azx_get_pos_callback_t callbacks[] = {
1634                 [POS_FIX_AUTO] = NULL,
1635                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1636                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1637                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1638                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1639                 [POS_FIX_SKL] = azx_get_pos_skl,
1640                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1641         };
1642
1643         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1644
1645         /* combo mode uses LPIB only for playback */
1646         if (fix == POS_FIX_COMBO)
1647                 chip->get_position[1] = NULL;
1648
1649         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1650             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1651                 chip->get_delay[0] = chip->get_delay[1] =
1652                         azx_get_delay_from_lpib;
1653         }
1654
1655         if (fix == POS_FIX_FIFO)
1656                 chip->get_delay[0] = chip->get_delay[1] =
1657                         azx_get_delay_from_fifo;
1658 }
1659
1660 /*
1661  * black-lists for probe_mask
1662  */
1663 static struct snd_pci_quirk probe_mask_list[] = {
1664         /* Thinkpad often breaks the controller communication when accessing
1665          * to the non-working (or non-existing) modem codec slot.
1666          */
1667         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1668         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1669         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1670         /* broken BIOS */
1671         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1672         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1673         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1674         /* forced codec slots */
1675         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1676         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1677         SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1678         /* WinFast VP200 H (Teradici) user reported broken communication */
1679         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1680         {}
1681 };
1682
1683 #define AZX_FORCE_CODEC_MASK    0x100
1684
1685 static void check_probe_mask(struct azx *chip, int dev)
1686 {
1687         const struct snd_pci_quirk *q;
1688
1689         chip->codec_probe_mask = probe_mask[dev];
1690         if (chip->codec_probe_mask == -1) {
1691                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1692                 if (q) {
1693                         dev_info(chip->card->dev,
1694                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1695                                  q->value, q->subvendor, q->subdevice);
1696                         chip->codec_probe_mask = q->value;
1697                 }
1698         }
1699
1700         /* check forced option */
1701         if (chip->codec_probe_mask != -1 &&
1702             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1703                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1704                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1705                          (int)azx_bus(chip)->codec_mask);
1706         }
1707 }
1708
1709 /*
1710  * white/black-list for enable_msi
1711  */
1712 static struct snd_pci_quirk msi_black_list[] = {
1713         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1714         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1715         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1716         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1717         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1718         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1719         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1720         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1721         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1722         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1723         {}
1724 };
1725
1726 static void check_msi(struct azx *chip)
1727 {
1728         const struct snd_pci_quirk *q;
1729
1730         if (enable_msi >= 0) {
1731                 chip->msi = !!enable_msi;
1732                 return;
1733         }
1734         chip->msi = 1;  /* enable MSI as default */
1735         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1736         if (q) {
1737                 dev_info(chip->card->dev,
1738                          "msi for device %04x:%04x set to %d\n",
1739                          q->subvendor, q->subdevice, q->value);
1740                 chip->msi = q->value;
1741                 return;
1742         }
1743
1744         /* NVidia chipsets seem to cause troubles with MSI */
1745         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1746                 dev_info(chip->card->dev, "Disabling MSI\n");
1747                 chip->msi = 0;
1748         }
1749 }
1750
1751 /* check the snoop mode availability */
1752 static void azx_check_snoop_available(struct azx *chip)
1753 {
1754         int snoop = hda_snoop;
1755
1756         if (snoop >= 0) {
1757                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1758                          snoop ? "snoop" : "non-snoop");
1759                 chip->snoop = snoop;
1760                 chip->uc_buffer = !snoop;
1761                 return;
1762         }
1763
1764         snoop = true;
1765         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1766             chip->driver_type == AZX_DRIVER_VIA) {
1767                 /* force to non-snoop mode for a new VIA controller
1768                  * when BIOS is set
1769                  */
1770                 u8 val;
1771                 pci_read_config_byte(chip->pci, 0x42, &val);
1772                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1773                                       chip->pci->revision == 0x20))
1774                         snoop = false;
1775         }
1776
1777         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1778                 snoop = false;
1779
1780         chip->snoop = snoop;
1781         if (!snoop) {
1782                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1783                 /* C-Media requires non-cached pages only for CORB/RIRB */
1784                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1785                         chip->uc_buffer = true;
1786         }
1787 }
1788
1789 static void azx_probe_work(struct work_struct *work)
1790 {
1791         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1792         azx_probe_continue(&hda->chip);
1793 }
1794
1795 static int default_bdl_pos_adj(struct azx *chip)
1796 {
1797         /* some exceptions: Atoms seem problematic with value 1 */
1798         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1799                 switch (chip->pci->device) {
1800                 case 0x0f04: /* Baytrail */
1801                 case 0x2284: /* Braswell */
1802                         return 32;
1803                 }
1804         }
1805
1806         switch (chip->driver_type) {
1807         case AZX_DRIVER_ICH:
1808         case AZX_DRIVER_PCH:
1809                 return 1;
1810         default:
1811                 return 32;
1812         }
1813 }
1814
1815 /*
1816  * constructor
1817  */
1818 static const struct hdac_io_ops pci_hda_io_ops;
1819 static const struct hda_controller_ops pci_hda_ops;
1820
1821 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1822                       int dev, unsigned int driver_caps,
1823                       struct azx **rchip)
1824 {
1825         static struct snd_device_ops ops = {
1826                 .dev_disconnect = azx_dev_disconnect,
1827                 .dev_free = azx_dev_free,
1828         };
1829         struct hda_intel *hda;
1830         struct azx *chip;
1831         int err;
1832
1833         *rchip = NULL;
1834
1835         err = pci_enable_device(pci);
1836         if (err < 0)
1837                 return err;
1838
1839         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1840         if (!hda) {
1841                 pci_disable_device(pci);
1842                 return -ENOMEM;
1843         }
1844
1845         chip = &hda->chip;
1846         mutex_init(&chip->open_mutex);
1847         chip->card = card;
1848         chip->pci = pci;
1849         chip->ops = &pci_hda_ops;
1850         chip->driver_caps = driver_caps;
1851         chip->driver_type = driver_caps & 0xff;
1852         check_msi(chip);
1853         chip->dev_index = dev;
1854         chip->jackpoll_ms = jackpoll_ms;
1855         INIT_LIST_HEAD(&chip->pcm_list);
1856         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1857         INIT_LIST_HEAD(&hda->list);
1858         init_vga_switcheroo(chip);
1859         init_completion(&hda->probe_wait);
1860
1861         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1862
1863         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1864                 chip->fallback_to_single_cmd = 1;
1865         else /* explicitly set to single_cmd or not */
1866                 chip->single_cmd = single_cmd;
1867
1868         azx_check_snoop_available(chip);
1869
1870         if (bdl_pos_adj[dev] < 0)
1871                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1872         else
1873                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1874
1875         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1876         if (IS_CFL(pci) || IS_CNL(pci))
1877                 chip->polling_mode = 1;
1878
1879         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1880         if (err < 0) {
1881                 kfree(hda);
1882                 pci_disable_device(pci);
1883                 return err;
1884         }
1885
1886         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1887                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1888                 chip->bus.needs_damn_long_delay = 1;
1889         }
1890
1891         check_probe_mask(chip, dev);
1892
1893         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1894         if (err < 0) {
1895                 dev_err(card->dev, "Error creating device [card]!\n");
1896                 azx_free(chip);
1897                 return err;
1898         }
1899
1900         /* continue probing in work context as may trigger request module */
1901         INIT_WORK(&hda->probe_work, azx_probe_work);
1902
1903         *rchip = chip;
1904
1905         return 0;
1906 }
1907
1908 static int azx_first_init(struct azx *chip)
1909 {
1910         int dev = chip->dev_index;
1911         struct pci_dev *pci = chip->pci;
1912         struct snd_card *card = chip->card;
1913         struct hdac_bus *bus = azx_bus(chip);
1914         int err;
1915         unsigned short gcap;
1916         unsigned int dma_bits = 64;
1917
1918 #if BITS_PER_LONG != 64
1919         /* Fix up base address on ULI M5461 */
1920         if (chip->driver_type == AZX_DRIVER_ULI) {
1921                 u16 tmp3;
1922                 pci_read_config_word(pci, 0x40, &tmp3);
1923                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1924                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1925         }
1926 #endif
1927
1928         err = pci_request_regions(pci, "ICH HD audio");
1929         if (err < 0)
1930                 return err;
1931         chip->region_requested = 1;
1932
1933         bus->addr = pci_resource_start(pci, 0);
1934         bus->remap_addr = pci_ioremap_bar(pci, 0);
1935         if (bus->remap_addr == NULL) {
1936                 dev_err(card->dev, "ioremap error\n");
1937                 return -ENXIO;
1938         }
1939
1940         if (chip->driver_type == AZX_DRIVER_SKL)
1941                 snd_hdac_bus_parse_capabilities(bus);
1942
1943         /*
1944          * Some Intel CPUs has always running timer (ART) feature and
1945          * controller may have Global time sync reporting capability, so
1946          * check both of these before declaring synchronized time reporting
1947          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1948          */
1949         chip->gts_present = false;
1950
1951 #ifdef CONFIG_X86
1952         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1953                 chip->gts_present = true;
1954 #endif
1955
1956         if (chip->msi) {
1957                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1958                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1959                         pci->no_64bit_msi = true;
1960                 }
1961                 if (pci_enable_msi(pci) < 0)
1962                         chip->msi = 0;
1963         }
1964
1965         pci_set_master(pci);
1966         synchronize_irq(bus->irq);
1967
1968         gcap = azx_readw(chip, GCAP);
1969         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1970
1971         /* AMD devices support 40 or 48bit DMA, take the safe one */
1972         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1973                 dma_bits = 40;
1974
1975         /* disable SB600 64bit support for safety */
1976         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1977                 struct pci_dev *p_smbus;
1978                 dma_bits = 40;
1979                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1980                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1981                                          NULL);
1982                 if (p_smbus) {
1983                         if (p_smbus->revision < 0x30)
1984                                 gcap &= ~AZX_GCAP_64OK;
1985                         pci_dev_put(p_smbus);
1986                 }
1987         }
1988
1989         /* NVidia hardware normally only supports up to 40 bits of DMA */
1990         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1991                 dma_bits = 40;
1992
1993         /* disable 64bit DMA address on some devices */
1994         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1995                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1996                 gcap &= ~AZX_GCAP_64OK;
1997         }
1998
1999         /* disable buffer size rounding to 128-byte multiples if supported */
2000         if (align_buffer_size >= 0)
2001                 chip->align_buffer_size = !!align_buffer_size;
2002         else {
2003                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
2004                         chip->align_buffer_size = 0;
2005                 else
2006                         chip->align_buffer_size = 1;
2007         }
2008
2009         /* allow 64bit DMA address if supported by H/W */
2010         if (!(gcap & AZX_GCAP_64OK))
2011                 dma_bits = 32;
2012         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
2013                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
2014         } else {
2015                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
2016                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
2017         }
2018
2019         /* read number of streams from GCAP register instead of using
2020          * hardcoded value
2021          */
2022         chip->capture_streams = (gcap >> 8) & 0x0f;
2023         chip->playback_streams = (gcap >> 12) & 0x0f;
2024         if (!chip->playback_streams && !chip->capture_streams) {
2025                 /* gcap didn't give any info, switching to old method */
2026
2027                 switch (chip->driver_type) {
2028                 case AZX_DRIVER_ULI:
2029                         chip->playback_streams = ULI_NUM_PLAYBACK;
2030                         chip->capture_streams = ULI_NUM_CAPTURE;
2031                         break;
2032                 case AZX_DRIVER_ATIHDMI:
2033                 case AZX_DRIVER_ATIHDMI_NS:
2034                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2035                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2036                         break;
2037                 case AZX_DRIVER_GENERIC:
2038                 default:
2039                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2040                         chip->capture_streams = ICH6_NUM_CAPTURE;
2041                         break;
2042                 }
2043         }
2044         chip->capture_index_offset = 0;
2045         chip->playback_index_offset = chip->capture_streams;
2046         chip->num_streams = chip->playback_streams + chip->capture_streams;
2047
2048         /* sanity check for the SDxCTL.STRM field overflow */
2049         if (chip->num_streams > 15 &&
2050             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2051                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2052                          "forcing separate stream tags", chip->num_streams);
2053                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2054         }
2055
2056         /* initialize streams */
2057         err = azx_init_streams(chip);
2058         if (err < 0)
2059                 return err;
2060
2061         err = azx_alloc_stream_pages(chip);
2062         if (err < 0)
2063                 return err;
2064
2065         /* initialize chip */
2066         azx_init_pci(chip);
2067
2068         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2069                 snd_hdac_i915_set_bclk(bus);
2070
2071         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2072
2073         /* codec detection */
2074         if (!azx_bus(chip)->codec_mask) {
2075                 dev_err(card->dev, "no codecs found!\n");
2076                 /* keep running the rest for the runtime PM */
2077         }
2078
2079         if (azx_acquire_irq(chip, 0) < 0)
2080                 return -EBUSY;
2081
2082         strcpy(card->driver, "HDA-Intel");
2083         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2084                 sizeof(card->shortname));
2085         snprintf(card->longname, sizeof(card->longname),
2086                  "%s at 0x%lx irq %i",
2087                  card->shortname, bus->addr, bus->irq);
2088
2089         return 0;
2090 }
2091
2092 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2093 /* callback from request_firmware_nowait() */
2094 static void azx_firmware_cb(const struct firmware *fw, void *context)
2095 {
2096         struct snd_card *card = context;
2097         struct azx *chip = card->private_data;
2098
2099         if (fw)
2100                 chip->fw = fw;
2101         else
2102                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2103         if (!chip->disabled) {
2104                 /* continue probing */
2105                 azx_probe_continue(chip);
2106         }
2107 }
2108 #endif
2109
2110 /*
2111  * HDA controller ops.
2112  */
2113
2114 /* PCI register access. */
2115 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2116 {
2117         writel(value, addr);
2118 }
2119
2120 static u32 pci_azx_readl(u32 __iomem *addr)
2121 {
2122         return readl(addr);
2123 }
2124
2125 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2126 {
2127         writew(value, addr);
2128 }
2129
2130 static u16 pci_azx_readw(u16 __iomem *addr)
2131 {
2132         return readw(addr);
2133 }
2134
2135 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2136 {
2137         writeb(value, addr);
2138 }
2139
2140 static u8 pci_azx_readb(u8 __iomem *addr)
2141 {
2142         return readb(addr);
2143 }
2144
2145 static int disable_msi_reset_irq(struct azx *chip)
2146 {
2147         struct hdac_bus *bus = azx_bus(chip);
2148         int err;
2149
2150         free_irq(bus->irq, chip);
2151         bus->irq = -1;
2152         pci_disable_msi(chip->pci);
2153         chip->msi = 0;
2154         err = azx_acquire_irq(chip, 1);
2155         if (err < 0)
2156                 return err;
2157
2158         return 0;
2159 }
2160
2161 /* DMA page allocation helpers.  */
2162 static int dma_alloc_pages(struct hdac_bus *bus,
2163                            int type,
2164                            size_t size,
2165                            struct snd_dma_buffer *buf)
2166 {
2167         struct azx *chip = bus_to_azx(bus);
2168         int err;
2169
2170         err = snd_dma_alloc_pages(type,
2171                                   bus->dev,
2172                                   size, buf);
2173         if (err < 0)
2174                 return err;
2175         mark_pages_wc(chip, buf, true);
2176         return 0;
2177 }
2178
2179 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2180 {
2181         struct azx *chip = bus_to_azx(bus);
2182
2183         mark_pages_wc(chip, buf, false);
2184         snd_dma_free_pages(buf);
2185 }
2186
2187 static int substream_alloc_pages(struct azx *chip,
2188                                  struct snd_pcm_substream *substream,
2189                                  size_t size)
2190 {
2191         struct azx_dev *azx_dev = get_azx_dev(substream);
2192         int ret;
2193
2194         mark_runtime_wc(chip, azx_dev, substream, false);
2195         ret = snd_pcm_lib_malloc_pages(substream, size);
2196         if (ret < 0)
2197                 return ret;
2198         mark_runtime_wc(chip, azx_dev, substream, true);
2199         return 0;
2200 }
2201
2202 static int substream_free_pages(struct azx *chip,
2203                                 struct snd_pcm_substream *substream)
2204 {
2205         struct azx_dev *azx_dev = get_azx_dev(substream);
2206         mark_runtime_wc(chip, azx_dev, substream, false);
2207         return snd_pcm_lib_free_pages(substream);
2208 }
2209
2210 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2211                              struct vm_area_struct *area)
2212 {
2213 #ifdef CONFIG_X86
2214         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2215         struct azx *chip = apcm->chip;
2216         if (chip->uc_buffer)
2217                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2218 #endif
2219 }
2220
2221 static const struct hdac_io_ops pci_hda_io_ops = {
2222         .reg_writel = pci_azx_writel,
2223         .reg_readl = pci_azx_readl,
2224         .reg_writew = pci_azx_writew,
2225         .reg_readw = pci_azx_readw,
2226         .reg_writeb = pci_azx_writeb,
2227         .reg_readb = pci_azx_readb,
2228         .dma_alloc_pages = dma_alloc_pages,
2229         .dma_free_pages = dma_free_pages,
2230 };
2231
2232 /* Blacklist for skipping the whole probe:
2233  * some HD-audio PCI entries are exposed without any codecs, and such devices
2234  * should be ignored from the beginning.
2235  */
2236 static const struct pci_device_id driver_blacklist[] = {
2237         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2238         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2239         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2240         {}
2241 };
2242
2243 static const struct hda_controller_ops pci_hda_ops = {
2244         .disable_msi_reset_irq = disable_msi_reset_irq,
2245         .substream_alloc_pages = substream_alloc_pages,
2246         .substream_free_pages = substream_free_pages,
2247         .pcm_mmap_prepare = pcm_mmap_prepare,
2248         .position_check = azx_position_check,
2249         .link_power = azx_intel_link_power,
2250 };
2251
2252 static int azx_probe(struct pci_dev *pci,
2253                      const struct pci_device_id *pci_id)
2254 {
2255         static int dev;
2256         struct snd_card *card;
2257         struct hda_intel *hda;
2258         struct azx *chip;
2259         bool schedule_probe;
2260         int err;
2261
2262         if (pci_match_id(driver_blacklist, pci)) {
2263                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2264                 return -ENODEV;
2265         }
2266
2267         if (dev >= SNDRV_CARDS)
2268                 return -ENODEV;
2269         if (!enable[dev]) {
2270                 dev++;
2271                 return -ENOENT;
2272         }
2273
2274         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2275                            0, &card);
2276         if (err < 0) {
2277                 dev_err(&pci->dev, "Error creating card!\n");
2278                 return err;
2279         }
2280
2281         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2282         if (err < 0)
2283                 goto out_free;
2284         card->private_data = chip;
2285         hda = container_of(chip, struct hda_intel, chip);
2286
2287         pci_set_drvdata(pci, card);
2288
2289         err = register_vga_switcheroo(chip);
2290         if (err < 0) {
2291                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2292                 goto out_free;
2293         }
2294
2295         if (check_hdmi_disabled(pci)) {
2296                 dev_info(card->dev, "VGA controller is disabled\n");
2297                 dev_info(card->dev, "Delaying initialization\n");
2298                 chip->disabled = true;
2299         }
2300
2301         schedule_probe = !chip->disabled;
2302
2303 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2304         if (patch[dev] && *patch[dev]) {
2305                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2306                          patch[dev]);
2307                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2308                                               &pci->dev, GFP_KERNEL, card,
2309                                               azx_firmware_cb);
2310                 if (err < 0)
2311                         goto out_free;
2312                 schedule_probe = false; /* continued in azx_firmware_cb() */
2313         }
2314 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2315
2316 #ifndef CONFIG_SND_HDA_I915
2317         if (CONTROLLER_IN_GPU(pci))
2318                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2319 #endif
2320
2321         if (schedule_probe)
2322                 schedule_work(&hda->probe_work);
2323
2324         dev++;
2325         if (chip->disabled)
2326                 complete_all(&hda->probe_wait);
2327         return 0;
2328
2329 out_free:
2330         snd_card_free(card);
2331         return err;
2332 }
2333
2334 #ifdef CONFIG_PM
2335 /* On some boards setting power_save to a non 0 value leads to clicking /
2336  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2337  * figure out how to avoid these sounds, but that is not always feasible.
2338  * So we keep a list of devices where we disable powersaving as its known
2339  * to causes problems on these devices.
2340  */
2341 static struct snd_pci_quirk power_save_blacklist[] = {
2342         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2343         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2344         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2345         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2346         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2347         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2348         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2349         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2350         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2351         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2352         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2353         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2354         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2355         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2356         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2357         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2358         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2359         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2360         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2361         /* https://bugs.launchpad.net/bugs/1821663 */
2362         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2363         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2364         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2365         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2366         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2367         SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2368         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2369         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2370         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2371         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2372         /* https://bugs.launchpad.net/bugs/1821663 */
2373         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2374         /* KONTRON SinglePC may cause a stall at runtime resume */
2375         SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2376         {}
2377 };
2378 #endif /* CONFIG_PM */
2379
2380 static void set_default_power_save(struct azx *chip)
2381 {
2382         int val = power_save;
2383
2384 #ifdef CONFIG_PM
2385         if (pm_blacklist) {
2386                 const struct snd_pci_quirk *q;
2387
2388                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2389                 if (q && val) {
2390                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2391                                  q->subvendor, q->subdevice);
2392                         val = 0;
2393                 }
2394         }
2395 #endif /* CONFIG_PM */
2396         snd_hda_set_power_save(&chip->bus, val * 1000);
2397 }
2398
2399 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2400 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2401         [AZX_DRIVER_NVIDIA] = 8,
2402         [AZX_DRIVER_TERA] = 1,
2403 };
2404
2405 static int azx_probe_continue(struct azx *chip)
2406 {
2407         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2408         struct hdac_bus *bus = azx_bus(chip);
2409         struct pci_dev *pci = chip->pci;
2410         int dev = chip->dev_index;
2411         int err;
2412
2413         to_hda_bus(bus)->bus_probing = 1;
2414         hda->probe_continued = 1;
2415
2416         /* bind with i915 if needed */
2417         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2418                 err = snd_hdac_i915_init(bus);
2419                 if (err < 0) {
2420                         /* if the controller is bound only with HDMI/DP
2421                          * (for HSW and BDW), we need to abort the probe;
2422                          * for other chips, still continue probing as other
2423                          * codecs can be on the same link.
2424                          */
2425                         if (CONTROLLER_IN_GPU(pci)) {
2426                                 dev_err(chip->card->dev,
2427                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2428                                 goto out_free;
2429                         } else {
2430                                 /* don't bother any longer */
2431                                 chip->driver_caps &=
2432                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2433                         }
2434                 }
2435         }
2436
2437         /* Request display power well for the HDA controller or codec. For
2438          * Haswell/Broadwell, both the display HDA controller and codec need
2439          * this power. For other platforms, like Baytrail/Braswell, only the
2440          * display codec needs the power and it can be released after probe.
2441          */
2442         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2443                 /* HSW/BDW controllers need this power */
2444                 if (CONTROLLER_IN_GPU(pci))
2445                         hda->need_i915_power = 1;
2446
2447                 err = snd_hdac_display_power(bus, true);
2448                 if (err < 0) {
2449                         dev_err(chip->card->dev,
2450                                 "Cannot turn on display power on i915\n");
2451                         goto i915_power_fail;
2452                 }
2453         }
2454
2455         err = azx_first_init(chip);
2456         if (err < 0)
2457                 goto out_free;
2458
2459 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2460         chip->beep_mode = beep_mode[dev];
2461 #endif
2462
2463         /* create codec instances */
2464         if (bus->codec_mask) {
2465                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2466                 if (err < 0)
2467                         goto out_free;
2468         }
2469
2470 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2471         if (chip->fw) {
2472                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2473                                          chip->fw->data);
2474                 if (err < 0)
2475                         goto out_free;
2476 #ifndef CONFIG_PM
2477                 release_firmware(chip->fw); /* no longer needed */
2478                 chip->fw = NULL;
2479 #endif
2480         }
2481 #endif
2482         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2483                 err = azx_codec_configure(chip);
2484                 if (err < 0)
2485                         goto out_free;
2486         }
2487
2488         err = snd_card_register(chip->card);
2489         if (err < 0)
2490                 goto out_free;
2491
2492         setup_vga_switcheroo_runtime_pm(chip);
2493
2494         chip->running = 1;
2495         azx_add_card_list(chip);
2496
2497         set_default_power_save(chip);
2498
2499         if (azx_has_pm_runtime(chip)) {
2500                 pm_runtime_use_autosuspend(&pci->dev);
2501                 pm_runtime_put_autosuspend(&pci->dev);
2502         }
2503
2504 out_free:
2505         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2506                 && !hda->need_i915_power)
2507                 snd_hdac_display_power(bus, false);
2508
2509 i915_power_fail:
2510         if (err < 0)
2511                 hda->init_failed = 1;
2512         complete_all(&hda->probe_wait);
2513         to_hda_bus(bus)->bus_probing = 0;
2514         return err;
2515 }
2516
2517 static void azx_remove(struct pci_dev *pci)
2518 {
2519         struct snd_card *card = pci_get_drvdata(pci);
2520         struct azx *chip;
2521         struct hda_intel *hda;
2522
2523         if (card) {
2524                 /* cancel the pending probing work */
2525                 chip = card->private_data;
2526                 hda = container_of(chip, struct hda_intel, chip);
2527                 /* FIXME: below is an ugly workaround.
2528                  * Both device_release_driver() and driver_probe_device()
2529                  * take *both* the device's and its parent's lock before
2530                  * calling the remove() and probe() callbacks.  The codec
2531                  * probe takes the locks of both the codec itself and its
2532                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2533                  * the PCI controller is unbound, it takes its lock, too
2534                  * ==> ouch, a deadlock!
2535                  * As a workaround, we unlock temporarily here the controller
2536                  * device during cancel_work_sync() call.
2537                  */
2538                 device_unlock(&pci->dev);
2539                 cancel_work_sync(&hda->probe_work);
2540                 device_lock(&pci->dev);
2541
2542                 snd_card_free(card);
2543         }
2544 }
2545
2546 static void azx_shutdown(struct pci_dev *pci)
2547 {
2548         struct snd_card *card = pci_get_drvdata(pci);
2549         struct azx *chip;
2550
2551         if (!card)
2552                 return;
2553         chip = card->private_data;
2554         if (chip && chip->running)
2555                 azx_stop_chip(chip);
2556 }
2557
2558 /* PCI IDs */
2559 static const struct pci_device_id azx_ids[] = {
2560         /* CPT */
2561         { PCI_DEVICE(0x8086, 0x1c20),
2562           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2563         /* PBG */
2564         { PCI_DEVICE(0x8086, 0x1d20),
2565           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2566         /* Panther Point */
2567         { PCI_DEVICE(0x8086, 0x1e20),
2568           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2569         /* Lynx Point */
2570         { PCI_DEVICE(0x8086, 0x8c20),
2571           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2572         /* 9 Series */
2573         { PCI_DEVICE(0x8086, 0x8ca0),
2574           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2575         /* Wellsburg */
2576         { PCI_DEVICE(0x8086, 0x8d20),
2577           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2578         { PCI_DEVICE(0x8086, 0x8d21),
2579           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2580         /* Lewisburg */
2581         { PCI_DEVICE(0x8086, 0xa1f0),
2582           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2583         { PCI_DEVICE(0x8086, 0xa270),
2584           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2585         /* Lynx Point-LP */
2586         { PCI_DEVICE(0x8086, 0x9c20),
2587           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2588         /* Lynx Point-LP */
2589         { PCI_DEVICE(0x8086, 0x9c21),
2590           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2591         /* Wildcat Point-LP */
2592         { PCI_DEVICE(0x8086, 0x9ca0),
2593           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2594         /* Sunrise Point */
2595         { PCI_DEVICE(0x8086, 0xa170),
2596           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2597         /* Sunrise Point-LP */
2598         { PCI_DEVICE(0x8086, 0x9d70),
2599           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2600         /* Kabylake */
2601         { PCI_DEVICE(0x8086, 0xa171),
2602           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2603         /* Kabylake-LP */
2604         { PCI_DEVICE(0x8086, 0x9d71),
2605           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2606         /* Kabylake-H */
2607         { PCI_DEVICE(0x8086, 0xa2f0),
2608           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2609         /* Coffelake */
2610         { PCI_DEVICE(0x8086, 0xa348),
2611           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2612         /* Cannonlake */
2613         { PCI_DEVICE(0x8086, 0x9dc8),
2614           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2615         /* Icelake */
2616         { PCI_DEVICE(0x8086, 0x34c8),
2617           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2618         /* Broxton-P(Apollolake) */
2619         { PCI_DEVICE(0x8086, 0x5a98),
2620           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2621         /* Broxton-T */
2622         { PCI_DEVICE(0x8086, 0x1a98),
2623           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2624         /* Gemini-Lake */
2625         { PCI_DEVICE(0x8086, 0x3198),
2626           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2627         /* Haswell */
2628         { PCI_DEVICE(0x8086, 0x0a0c),
2629           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2630         { PCI_DEVICE(0x8086, 0x0c0c),
2631           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2632         { PCI_DEVICE(0x8086, 0x0d0c),
2633           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2634         /* Broadwell */
2635         { PCI_DEVICE(0x8086, 0x160c),
2636           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2637         /* 5 Series/3400 */
2638         { PCI_DEVICE(0x8086, 0x3b56),
2639           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2640         { PCI_DEVICE(0x8086, 0x3b57),
2641           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2642         /* Poulsbo */
2643         { PCI_DEVICE(0x8086, 0x811b),
2644           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2645           AZX_DCAPS_POSFIX_LPIB },
2646         /* Oaktrail */
2647         { PCI_DEVICE(0x8086, 0x080a),
2648           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2649         /* BayTrail */
2650         { PCI_DEVICE(0x8086, 0x0f04),
2651           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2652         /* Braswell */
2653         { PCI_DEVICE(0x8086, 0x2284),
2654           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2655         /* ICH6 */
2656         { PCI_DEVICE(0x8086, 0x2668),
2657           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2658         /* ICH7 */
2659         { PCI_DEVICE(0x8086, 0x27d8),
2660           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2661         /* ESB2 */
2662         { PCI_DEVICE(0x8086, 0x269a),
2663           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2664         /* ICH8 */
2665         { PCI_DEVICE(0x8086, 0x284b),
2666           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2667         /* ICH9 */
2668         { PCI_DEVICE(0x8086, 0x293e),
2669           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2670         /* ICH9 */
2671         { PCI_DEVICE(0x8086, 0x293f),
2672           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2673         /* ICH10 */
2674         { PCI_DEVICE(0x8086, 0x3a3e),
2675           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2676         /* ICH10 */
2677         { PCI_DEVICE(0x8086, 0x3a6e),
2678           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2679         /* Generic Intel */
2680         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2681           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2682           .class_mask = 0xffffff,
2683           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2684         /* ATI SB 450/600/700/800/900 */
2685         { PCI_DEVICE(0x1002, 0x437b),
2686           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2687         { PCI_DEVICE(0x1002, 0x4383),
2688           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2689         /* AMD Hudson */
2690         { PCI_DEVICE(0x1022, 0x780d),
2691           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2692         /* AMD, X370 & co */
2693         { PCI_DEVICE(0x1022, 0x1457),
2694           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2695         /* AMD, X570 & co */
2696         { PCI_DEVICE(0x1022, 0x1487),
2697           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2698         /* AMD Stoney */
2699         { PCI_DEVICE(0x1022, 0x157a),
2700           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2701                          AZX_DCAPS_PM_RUNTIME },
2702         /* AMD Raven */
2703         { PCI_DEVICE(0x1022, 0x15e3),
2704           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2705         /* ATI HDMI */
2706         { PCI_DEVICE(0x1002, 0x0002),
2707           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2708         { PCI_DEVICE(0x1002, 0x1308),
2709           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2710         { PCI_DEVICE(0x1002, 0x157a),
2711           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2712         { PCI_DEVICE(0x1002, 0x15b3),
2713           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2714         { PCI_DEVICE(0x1002, 0x793b),
2715           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2716         { PCI_DEVICE(0x1002, 0x7919),
2717           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2718         { PCI_DEVICE(0x1002, 0x960f),
2719           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2720         { PCI_DEVICE(0x1002, 0x970f),
2721           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2722         { PCI_DEVICE(0x1002, 0x9840),
2723           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2724         { PCI_DEVICE(0x1002, 0xaa00),
2725           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2726         { PCI_DEVICE(0x1002, 0xaa08),
2727           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2728         { PCI_DEVICE(0x1002, 0xaa10),
2729           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2730         { PCI_DEVICE(0x1002, 0xaa18),
2731           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2732         { PCI_DEVICE(0x1002, 0xaa20),
2733           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2734         { PCI_DEVICE(0x1002, 0xaa28),
2735           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2736         { PCI_DEVICE(0x1002, 0xaa30),
2737           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2738         { PCI_DEVICE(0x1002, 0xaa38),
2739           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2740         { PCI_DEVICE(0x1002, 0xaa40),
2741           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2742         { PCI_DEVICE(0x1002, 0xaa48),
2743           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2744         { PCI_DEVICE(0x1002, 0xaa50),
2745           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2746         { PCI_DEVICE(0x1002, 0xaa58),
2747           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2748         { PCI_DEVICE(0x1002, 0xaa60),
2749           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2750         { PCI_DEVICE(0x1002, 0xaa68),
2751           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2752         { PCI_DEVICE(0x1002, 0xaa80),
2753           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2754         { PCI_DEVICE(0x1002, 0xaa88),
2755           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2756         { PCI_DEVICE(0x1002, 0xaa90),
2757           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2758         { PCI_DEVICE(0x1002, 0xaa98),
2759           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2760         { PCI_DEVICE(0x1002, 0x9902),
2761           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2762         { PCI_DEVICE(0x1002, 0xaaa0),
2763           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2764         { PCI_DEVICE(0x1002, 0xaaa8),
2765           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2766         { PCI_DEVICE(0x1002, 0xaab0),
2767           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2768         { PCI_DEVICE(0x1002, 0xaac0),
2769           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2770         { PCI_DEVICE(0x1002, 0xaac8),
2771           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2772         { PCI_DEVICE(0x1002, 0xaad8),
2773           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2774         { PCI_DEVICE(0x1002, 0xaae8),
2775           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2776         { PCI_DEVICE(0x1002, 0xaae0),
2777           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2778         { PCI_DEVICE(0x1002, 0xaaf0),
2779           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2780         /* VIA VT8251/VT8237A */
2781         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2782         /* VIA GFX VT7122/VX900 */
2783         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2784         /* VIA GFX VT6122/VX11 */
2785         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2786         /* SIS966 */
2787         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2788         /* ULI M5461 */
2789         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2790         /* NVIDIA MCP */
2791         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2792           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2793           .class_mask = 0xffffff,
2794           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2795         /* Teradici */
2796         { PCI_DEVICE(0x6549, 0x1200),
2797           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2798         { PCI_DEVICE(0x6549, 0x2200),
2799           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2800         /* Creative X-Fi (CA0110-IBG) */
2801         /* CTHDA chips */
2802         { PCI_DEVICE(0x1102, 0x0010),
2803           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2804         { PCI_DEVICE(0x1102, 0x0012),
2805           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2806 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2807         /* the following entry conflicts with snd-ctxfi driver,
2808          * as ctxfi driver mutates from HD-audio to native mode with
2809          * a special command sequence.
2810          */
2811         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2812           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2813           .class_mask = 0xffffff,
2814           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2815           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2816 #else
2817         /* this entry seems still valid -- i.e. without emu20kx chip */
2818         { PCI_DEVICE(0x1102, 0x0009),
2819           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2820           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2821 #endif
2822         /* CM8888 */
2823         { PCI_DEVICE(0x13f6, 0x5011),
2824           .driver_data = AZX_DRIVER_CMEDIA |
2825           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2826         /* Vortex86MX */
2827         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2828         /* VMware HDAudio */
2829         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2830         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2831         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2832           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2833           .class_mask = 0xffffff,
2834           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2835         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2836           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2837           .class_mask = 0xffffff,
2838           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2839         { 0, }
2840 };
2841 MODULE_DEVICE_TABLE(pci, azx_ids);
2842
2843 /* pci_driver definition */
2844 static struct pci_driver azx_driver = {
2845         .name = KBUILD_MODNAME,
2846         .id_table = azx_ids,
2847         .probe = azx_probe,
2848         .remove = azx_remove,
2849         .shutdown = azx_shutdown,
2850         .driver = {
2851                 .pm = AZX_PM_OPS,
2852         },
2853 };
2854
2855 module_pci_driver(azx_driver);