sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81         POS_FIX_FIFO,
  82 };
  83
  84 /* Defines for ATI HD Audio support in SB450 south bridge */
  85 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  86 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  87
  88 /* Defines for Nvidia HDA support */
  89 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  90 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  91 #define NVIDIA_HDA_ISTRM_COH          0x4d
  92 #define NVIDIA_HDA_OSTRM_COH          0x4c
  93 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  94
  95 /* Defines for Intel SCH HDA snoop control */
  96 #define INTEL_HDA_CGCTL  0x48
  97 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  98 #define INTEL_SCH_HDA_DEVC      0x78
  99 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 100
 101 /* Define IN stream 0 FIFO size offset in VIA controller */
 102 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 103 /* Define VIA HD Audio Device ID*/
 104 #define VIA_HDAC_DEVICE_ID              0x3288
 105
 106 /* max number of SDs */
 107 /* ICH, ATI and VIA have 4 playback and 4 capture */
 108 #define ICH6_NUM_CAPTURE        4
 109 #define ICH6_NUM_PLAYBACK       4
 110
 111 /* ULI has 6 playback and 5 capture */
 112 #define ULI_NUM_CAPTURE         5
 113 #define ULI_NUM_PLAYBACK        6
 114
 115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 116 #define ATIHDMI_NUM_CAPTURE     0
 117 #define ATIHDMI_NUM_PLAYBACK    8
 118
 119 /* TERA has 4 playback and 3 capture */
 120 #define TERA_NUM_CAPTURE        3
 121 #define TERA_NUM_PLAYBACK       4
 122
 123
 124 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 125 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 126 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 127 static char *model[SNDRV_CARDS];
 128 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 131 static int probe_only[SNDRV_CARDS];
 132 static int jackpoll_ms[SNDRV_CARDS];
 133 static int single_cmd = -1;
 134 static int enable_msi = -1;
 135 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 136 static char *patch[SNDRV_CARDS];
 137 #endif
 138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 139 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 140                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 141 #endif
 142
 143 module_param_array(index, int, NULL, 0444);
 144 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 145 module_param_array(id, charp, NULL, 0444);
 146 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 147 module_param_array(enable, bool, NULL, 0444);
 148 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 149 module_param_array(model, charp, NULL, 0444);
 150 MODULE_PARM_DESC(model, "Use the given board model.");
 151 module_param_array(position_fix, int, NULL, 0444);
 152 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 153                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 154 module_param_array(bdl_pos_adj, int, NULL, 0644);
 155 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 156 module_param_array(probe_mask, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 158 module_param_array(probe_only, int, NULL, 0444);
 159 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 160 module_param_array(jackpoll_ms, int, NULL, 0444);
 161 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 162 module_param(single_cmd, bint, 0444);
 163 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 164                  "(for debugging only).");
 165 module_param(enable_msi, bint, 0444);
 166 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 167 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 168 module_param_array(patch, charp, NULL, 0444);
 169 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 170 #endif
 171 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 172 module_param_array(beep_mode, bool, NULL, 0444);
 173 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 174                             "(0=off, 1=on) (default=1).");
 175 #endif
 176
 177 #ifdef CONFIG_PM
 178 static int param_set_xint(const char *val, const struct kernel_param *kp);
 179 static const struct kernel_param_ops param_ops_xint = {
 180         .set = param_set_xint,
 181         .get = param_get_int,
 182 };
 183 #define param_check_xint param_check_int
 184
 185 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 186 module_param(power_save, xint, 0644);
 187 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 188                  "(in second, 0 = disable).");
 189
 190 static bool pm_blacklist = true;
 191 module_param(pm_blacklist, bool, 0644);
 192 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 193
 194 /* reset the HD-audio controller in power save mode.
 195  * this may give more power-saving, but will take longer time to
 196  * wake up.
 197  */
 198 static bool power_save_controller = 1;
 199 module_param(power_save_controller, bool, 0644);
 200 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 201 #else
 202 #define power_save      0
 203 #endif /* CONFIG_PM */
 204
 205 static int align_buffer_size = -1;
 206 module_param(align_buffer_size, bint, 0644);
 207 MODULE_PARM_DESC(align_buffer_size,
 208                 "Force buffer and period sizes to be multiple of 128 bytes.");
 209
 210 #ifdef CONFIG_X86
 211 static int hda_snoop = -1;
 212 module_param_named(snoop, hda_snoop, bint, 0444);
 213 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 214 #else
 215 #define hda_snoop               true
 216 #endif
 217
 218
 219 MODULE_LICENSE("GPL");
 220 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 221                          "{Intel, ICH6M},"
 222                          "{Intel, ICH7},"
 223                          "{Intel, ESB2},"
 224                          "{Intel, ICH8},"
 225                          "{Intel, ICH9},"
 226                          "{Intel, ICH10},"
 227                          "{Intel, PCH},"
 228                          "{Intel, CPT},"
 229                          "{Intel, PPT},"
 230                          "{Intel, LPT},"
 231                          "{Intel, LPT_LP},"
 232                          "{Intel, WPT_LP},"
 233                          "{Intel, SPT},"
 234                          "{Intel, SPT_LP},"
 235                          "{Intel, HPT},"
 236                          "{Intel, PBG},"
 237                          "{Intel, SCH},"
 238                          "{ATI, SB450},"
 239                          "{ATI, SB600},"
 240                          "{ATI, RS600},"
 241                          "{ATI, RS690},"
 242                          "{ATI, RS780},"
 243                          "{ATI, R600},"
 244                          "{ATI, RV630},"
 245                          "{ATI, RV610},"
 246                          "{ATI, RV670},"
 247                          "{ATI, RV635},"
 248                          "{ATI, RV620},"
 249                          "{ATI, RV770},"
 250                          "{VIA, VT8251},"
 251                          "{VIA, VT8237A},"
 252                          "{SiS, SIS966},"
 253                          "{ULI, M5461}}");
 254 MODULE_DESCRIPTION("Intel HDA driver");
 255
 256 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 257 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 258 #define SUPPORT_VGA_SWITCHEROO
 259 #endif
 260 #endif
 261
 262
 263 /*
 264  */
 265
 266 /* driver types */
 267 enum {
 268         AZX_DRIVER_ICH,
 269         AZX_DRIVER_PCH,
 270         AZX_DRIVER_SCH,
 271         AZX_DRIVER_SKL,
 272         AZX_DRIVER_HDMI,
 273         AZX_DRIVER_ATI,
 274         AZX_DRIVER_ATIHDMI,
 275         AZX_DRIVER_ATIHDMI_NS,
 276         AZX_DRIVER_VIA,
 277         AZX_DRIVER_SIS,
 278         AZX_DRIVER_ULI,
 279         AZX_DRIVER_NVIDIA,
 280         AZX_DRIVER_TERA,
 281         AZX_DRIVER_CTX,
 282         AZX_DRIVER_CTHDA,
 283         AZX_DRIVER_CMEDIA,
 284         AZX_DRIVER_GENERIC,
 285         AZX_NUM_DRIVERS, /* keep this as last entry */
 286 };
 287
 288 #define azx_get_snoop_type(chip) \
 289         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 290 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 291
 292 /* quirks for old Intel chipsets */
 293 #define AZX_DCAPS_INTEL_ICH \
 294         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 295
 296 /* quirks for Intel PCH */
 297 #define AZX_DCAPS_INTEL_PCH_BASE \
 298         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 302 #define AZX_DCAPS_INTEL_PCH_NOPM \
 303         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 304
 305 /* PCH for HSW/BDW; with runtime PM */
 306 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 307 #define AZX_DCAPS_INTEL_PCH \
 308         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 309
 310 /* HSW HDMI */
 311 #define AZX_DCAPS_INTEL_HASWELL \
 312         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 313          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 314          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 315
 316 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 317 #define AZX_DCAPS_INTEL_BROADWELL \
 318         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 320          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 321
 322 #define AZX_DCAPS_INTEL_BAYTRAIL \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 324          AZX_DCAPS_I915_POWERWELL)
 325
 326 #define AZX_DCAPS_INTEL_BRASWELL \
 327         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 328          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 329
 330 #define AZX_DCAPS_INTEL_SKYLAKE \
 331         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 332          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 333          AZX_DCAPS_I915_POWERWELL)
 334
 335 #define AZX_DCAPS_INTEL_BROXTON \
 336         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 337          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 338          AZX_DCAPS_I915_POWERWELL)
 339
 340 /* quirks for ATI SB / AMD Hudson */
 341 #define AZX_DCAPS_PRESET_ATI_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI))
 344
 345 /* quirks for ATI/AMD HDMI */
 346 #define AZX_DCAPS_PRESET_ATI_HDMI \
 347         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 348          AZX_DCAPS_NO_MSI64)
 349
 350 /* quirks for ATI HDMI with snoop off */
 351 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 352         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 353
 354 /* quirks for AMD SB */
 355 #define AZX_DCAPS_PRESET_AMD_SB \
 356         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 357          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 358
 359 /* quirks for Nvidia */
 360 #define AZX_DCAPS_PRESET_NVIDIA \
 361         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 362          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 363
 364 #define AZX_DCAPS_PRESET_CTHDA \
 365         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 366          AZX_DCAPS_NO_64BIT |\
 367          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 368
 369 /*
 370  * vga_switcheroo support
 371  */
 372 #ifdef SUPPORT_VGA_SWITCHEROO
 373 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 374 #else
 375 #define use_vga_switcheroo(chip)        0
 376 #endif
 377
 378 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 379                                         ((pci)->device == 0x0c0c) || \
 380                                         ((pci)->device == 0x0d0c) || \
 381                                         ((pci)->device == 0x160c))
 382
 383 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 384 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 385 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 386
 387 static char *driver_short_names[] = {
 388         [AZX_DRIVER_ICH] = "HDA Intel",
 389         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 390         [AZX_DRIVER_SCH] = "HDA Intel MID",
 391         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 392         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 393         [AZX_DRIVER_ATI] = "HDA ATI SB",
 394         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 395         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 396         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 397         [AZX_DRIVER_SIS] = "HDA SIS966",
 398         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 399         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 400         [AZX_DRIVER_TERA] = "HDA Teradici",
 401         [AZX_DRIVER_CTX] = "HDA Creative",
 402         [AZX_DRIVER_CTHDA] = "HDA Creative",
 403         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 404         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 405 };
 406
 407 #ifdef CONFIG_X86
 408 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 409 {
 410         int pages;
 411
 412         if (azx_snoop(chip))
 413                 return;
 414         if (!dmab || !dmab->area || !dmab->bytes)
 415                 return;
 416
 417 #ifdef CONFIG_SND_DMA_SGBUF
 418         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 419                 struct snd_sg_buf *sgbuf = dmab->private_data;
 420                 if (!chip->uc_buffer)
 421                         return; /* deal with only CORB/RIRB buffers */
 422                 if (on)
 423                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 424                 else
 425                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 426                 return;
 427         }
 428 #endif
 429
 430         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 431         if (on)
 432                 set_memory_wc((unsigned long)dmab->area, pages);
 433         else
 434                 set_memory_wb((unsigned long)dmab->area, pages);
 435 }
 436
 437 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 438                                  bool on)
 439 {
 440         __mark_pages_wc(chip, buf, on);
 441 }
 442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 443                                    struct snd_pcm_substream *substream, bool on)
 444 {
 445         if (azx_dev->wc_marked != on) {
 446                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 447                 azx_dev->wc_marked = on;
 448         }
 449 }
 450 #else
 451 /* NOP for other archs */
 452 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 453                                  bool on)
 454 {
 455 }
 456 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 457                                    struct snd_pcm_substream *substream, bool on)
 458 {
 459 }
 460 #endif
 461
 462 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 463
 464 /*
 465  * initialize the PCI registers
 466  */
 467 /* update bits in a PCI register byte */
 468 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 469                             unsigned char mask, unsigned char val)
 470 {
 471         unsigned char data;
 472
 473         pci_read_config_byte(pci, reg, &data);
 474         data &= ~mask;
 475         data |= (val & mask);
 476         pci_write_config_byte(pci, reg, data);
 477 }
 478
 479 static void azx_init_pci(struct azx *chip)
 480 {
 481         int snoop_type = azx_get_snoop_type(chip);
 482
 483         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 484          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 485          * Ensuring these bits are 0 clears playback static on some HD Audio
 486          * codecs.
 487          * The PCI register TCSEL is defined in the Intel manuals.
 488          */
 489         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 490                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 491                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 492         }
 493
 494         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 495          * we need to enable snoop.
 496          */
 497         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 498                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 499                         azx_snoop(chip));
 500                 update_pci_byte(chip->pci,
 501                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 502                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 503         }
 504
 505         /* For NVIDIA HDA, enable snoop */
 506         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 507                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 508                         azx_snoop(chip));
 509                 update_pci_byte(chip->pci,
 510                                 NVIDIA_HDA_TRANSREG_ADDR,
 511                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 512                 update_pci_byte(chip->pci,
 513                                 NVIDIA_HDA_ISTRM_COH,
 514                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 515                 update_pci_byte(chip->pci,
 516                                 NVIDIA_HDA_OSTRM_COH,
 517                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 518         }
 519
 520         /* Enable SCH/PCH snoop if needed */
 521         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 522                 unsigned short snoop;
 523                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 524                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 525                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 526                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 527                         if (!azx_snoop(chip))
 528                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 529                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 530                         pci_read_config_word(chip->pci,
 531                                 INTEL_SCH_HDA_DEVC, &snoop);
 532                 }
 533                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 534                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 535                         "Disabled" : "Enabled");
 536         }
 537 }
 538
 539 /*
 540  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 541  * and makes an audio stream sensitive to system latencies when
 542  * 24/32 bits are playing.
 543  * Adjusting threshold of DMA fifo to force the DMA request
 544  * sooner to improve latency tolerance at the expense of power.
 545  */
 546 static void bxt_reduce_dma_latency(struct azx *chip)
 547 {
 548         u32 val;
 549
 550         val = azx_readl(chip, VS_EM4L);
 551         val &= (0x3 << 20);
 552         azx_writel(chip, VS_EM4L, val);
 553 }
 554
 555 /*
 556  * ML_LCAP bits:
 557  *  bit 0: 6 MHz Supported
 558  *  bit 1: 12 MHz Supported
 559  *  bit 2: 24 MHz Supported
 560  *  bit 3: 48 MHz Supported
 561  *  bit 4: 96 MHz Supported
 562  *  bit 5: 192 MHz Supported
 563  */
 564 static int intel_get_lctl_scf(struct azx *chip)
 565 {
 566         struct hdac_bus *bus = azx_bus(chip);
 567         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 568         u32 val, t;
 569         int i;
 570
 571         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 572
 573         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 574                 t = preferred_bits[i];
 575                 if (val & (1 << t))
 576                         return t;
 577         }
 578
 579         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 580         return 0;
 581 }
 582
 583 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 584 {
 585         struct hdac_bus *bus = azx_bus(chip);
 586         u32 val;
 587         int timeout;
 588
 589         /*
 590          * the codecs are sharing the first link setting by default
 591          * If other links are enabled for stream, they need similar fix
 592          */
 593         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 594         val &= ~AZX_MLCTL_SPA;
 595         val |= state << AZX_MLCTL_SPA_SHIFT;
 596         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 597         /* wait for CPA */
 598         timeout = 50;
 599         while (timeout) {
 600                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 601                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 602                         return 0;
 603                 timeout--;
 604                 udelay(10);
 605         }
 606
 607         return -1;
 608 }
 609
 610 static void intel_init_lctl(struct azx *chip)
 611 {
 612         struct hdac_bus *bus = azx_bus(chip);
 613         u32 val;
 614         int ret;
 615
 616         /* 0. check lctl register value is correct or not */
 617         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 618         /* if SCF is already set, let's use it */
 619         if ((val & ML_LCTL_SCF_MASK) != 0)
 620                 return;
 621
 622         /*
 623          * Before operating on SPA, CPA must match SPA.
 624          * Any deviation may result in undefined behavior.
 625          */
 626         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 627                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 628                 return;
 629
 630         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 631         ret = intel_ml_lctl_set_power(chip, 0);
 632         udelay(100);
 633         if (ret)
 634                 goto set_spa;
 635
 636         /* 2. update SCF to select a properly audio clock*/
 637         val &= ~ML_LCTL_SCF_MASK;
 638         val |= intel_get_lctl_scf(chip);
 639         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 640
 641 set_spa:
 642         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 643         intel_ml_lctl_set_power(chip, 1);
 644         udelay(100);
 645 }
 646
 647 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 648 {
 649         struct hdac_bus *bus = azx_bus(chip);
 650         struct pci_dev *pci = chip->pci;
 651         u32 val;
 652
 653         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 654                 snd_hdac_set_codec_wakeup(bus, true);
 655         if (chip->driver_type == AZX_DRIVER_SKL) {
 656                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 657                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 658                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 659         }
 660         azx_init_chip(chip, full_reset);
 661         if (chip->driver_type == AZX_DRIVER_SKL) {
 662                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 663                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 664                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 665         }
 666         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 667                 snd_hdac_set_codec_wakeup(bus, false);
 668
 669         /* reduce dma latency to avoid noise */
 670         if (IS_BXT(pci))
 671                 bxt_reduce_dma_latency(chip);
 672
 673         if (bus->mlcap != NULL)
 674                 intel_init_lctl(chip);
 675 }
 676
 677 /* calculate runtime delay from LPIB */
 678 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 679                                    unsigned int pos)
 680 {
 681         struct snd_pcm_substream *substream = azx_dev->core.substream;
 682         int stream = substream->stream;
 683         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 684         int delay;
 685
 686         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 687                 delay = pos - lpib_pos;
 688         else
 689                 delay = lpib_pos - pos;
 690         if (delay < 0) {
 691                 if (delay >= azx_dev->core.delay_negative_threshold)
 692                         delay = 0;
 693                 else
 694                         delay += azx_dev->core.bufsize;
 695         }
 696
 697         if (delay >= azx_dev->core.period_bytes) {
 698                 dev_info(chip->card->dev,
 699                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 700                          delay, azx_dev->core.period_bytes);
 701                 delay = 0;
 702                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 703                 chip->get_delay[stream] = NULL;
 704         }
 705
 706         return bytes_to_frames(substream->runtime, delay);
 707 }
 708
 709 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 710
 711 /* called from IRQ */
 712 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 713 {
 714         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 715         int ok;
 716
 717         ok = azx_position_ok(chip, azx_dev);
 718         if (ok == 1) {
 719                 azx_dev->irq_pending = 0;
 720                 return ok;
 721         } else if (ok == 0) {
 722                 /* bogus IRQ, process it later */
 723                 azx_dev->irq_pending = 1;
 724                 schedule_work(&hda->irq_pending_work);
 725         }
 726         return 0;
 727 }
 728
 729 /* Enable/disable i915 display power for the link */
 730 static int azx_intel_link_power(struct azx *chip, bool enable)
 731 {
 732         struct hdac_bus *bus = azx_bus(chip);
 733
 734         return snd_hdac_display_power(bus, enable);
 735 }
 736
 737 /*
 738  * Check whether the current DMA position is acceptable for updating
 739  * periods.  Returns non-zero if it's OK.
 740  *
 741  * Many HD-audio controllers appear pretty inaccurate about
 742  * the update-IRQ timing.  The IRQ is issued before actually the
 743  * data is processed.  So, we need to process it afterwords in a
 744  * workqueue.
 745  */
 746 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 747 {
 748         struct snd_pcm_substream *substream = azx_dev->core.substream;
 749         int stream = substream->stream;
 750         u32 wallclk;
 751         unsigned int pos;
 752
 753         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 754         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 755                 return -1;      /* bogus (too early) interrupt */
 756
 757         if (chip->get_position[stream])
 758                 pos = chip->get_position[stream](chip, azx_dev);
 759         else { /* use the position buffer as default */
 760                 pos = azx_get_pos_posbuf(chip, azx_dev);
 761                 if (!pos || pos == (u32)-1) {
 762                         dev_info(chip->card->dev,
 763                                  "Invalid position buffer, using LPIB read method instead.\n");
 764                         chip->get_position[stream] = azx_get_pos_lpib;
 765                         if (chip->get_position[0] == azx_get_pos_lpib &&
 766                             chip->get_position[1] == azx_get_pos_lpib)
 767                                 azx_bus(chip)->use_posbuf = false;
 768                         pos = azx_get_pos_lpib(chip, azx_dev);
 769                         chip->get_delay[stream] = NULL;
 770                 } else {
 771                         chip->get_position[stream] = azx_get_pos_posbuf;
 772                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 773                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 774                 }
 775         }
 776
 777         if (pos >= azx_dev->core.bufsize)
 778                 pos = 0;
 779
 780         if (WARN_ONCE(!azx_dev->core.period_bytes,
 781                       "hda-intel: zero azx_dev->period_bytes"))
 782                 return -1; /* this shouldn't happen! */
 783         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 784             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 785                 /* NG - it's below the first next period boundary */
 786                 return chip->bdl_pos_adj ? 0 : -1;
 787         azx_dev->core.start_wallclk += wallclk;
 788         return 1; /* OK, it's fine */
 789 }
 790
 791 /*
 792  * The work for pending PCM period updates.
 793  */
 794 static void azx_irq_pending_work(struct work_struct *work)
 795 {
 796         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 797         struct azx *chip = &hda->chip;
 798         struct hdac_bus *bus = azx_bus(chip);
 799         struct hdac_stream *s;
 800         int pending, ok;
 801
 802         if (!hda->irq_pending_warned) {
 803                 dev_info(chip->card->dev,
 804                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 805                          chip->card->number);
 806                 hda->irq_pending_warned = 1;
 807         }
 808
 809         for (;;) {
 810                 pending = 0;
 811                 spin_lock_irq(&bus->reg_lock);
 812                 list_for_each_entry(s, &bus->stream_list, list) {
 813                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 814                         if (!azx_dev->irq_pending ||
 815                             !s->substream ||
 816                             !s->running)
 817                                 continue;
 818                         ok = azx_position_ok(chip, azx_dev);
 819                         if (ok > 0) {
 820                                 azx_dev->irq_pending = 0;
 821                                 spin_unlock(&bus->reg_lock);
 822                                 snd_pcm_period_elapsed(s->substream);
 823                                 spin_lock(&bus->reg_lock);
 824                         } else if (ok < 0) {
 825                                 pending = 0;    /* too early */
 826                         } else
 827                                 pending++;
 828                 }
 829                 spin_unlock_irq(&bus->reg_lock);
 830                 if (!pending)
 831                         return;
 832                 msleep(1);
 833         }
 834 }
 835
 836 /* clear irq_pending flags and assure no on-going workq */
 837 static void azx_clear_irq_pending(struct azx *chip)
 838 {
 839         struct hdac_bus *bus = azx_bus(chip);
 840         struct hdac_stream *s;
 841
 842         spin_lock_irq(&bus->reg_lock);
 843         list_for_each_entry(s, &bus->stream_list, list) {
 844                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 845                 azx_dev->irq_pending = 0;
 846         }
 847         spin_unlock_irq(&bus->reg_lock);
 848 }
 849
 850 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 851 {
 852         struct hdac_bus *bus = azx_bus(chip);
 853
 854         if (request_irq(chip->pci->irq, azx_interrupt,
 855                         chip->msi ? 0 : IRQF_SHARED,
 856                         chip->card->irq_descr, chip)) {
 857                 dev_err(chip->card->dev,
 858                         "unable to grab IRQ %d, disabling device\n",
 859                         chip->pci->irq);
 860                 if (do_disconnect)
 861                         snd_card_disconnect(chip->card);
 862                 return -1;
 863         }
 864         bus->irq = chip->pci->irq;
 865         pci_intx(chip->pci, !chip->msi);
 866         return 0;
 867 }
 868
 869 /* get the current DMA position with correction on VIA chips */
 870 static unsigned int azx_via_get_position(struct azx *chip,
 871                                          struct azx_dev *azx_dev)
 872 {
 873         unsigned int link_pos, mini_pos, bound_pos;
 874         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 875         unsigned int fifo_size;
 876
 877         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 878         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 879                 /* Playback, no problem using link position */
 880                 return link_pos;
 881         }
 882
 883         /* Capture */
 884         /* For new chipset,
 885          * use mod to get the DMA position just like old chipset
 886          */
 887         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 888         mod_dma_pos %= azx_dev->core.period_bytes;
 889
 890         /* azx_dev->fifo_size can't get FIFO size of in stream.
 891          * Get from base address + offset.
 892          */
 893         fifo_size = readw(azx_bus(chip)->remap_addr +
 894                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 895
 896         if (azx_dev->insufficient) {
 897                 /* Link position never gather than FIFO size */
 898                 if (link_pos <= fifo_size)
 899                         return 0;
 900
 901                 azx_dev->insufficient = 0;
 902         }
 903
 904         if (link_pos <= fifo_size)
 905                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 906         else
 907                 mini_pos = link_pos - fifo_size;
 908
 909         /* Find nearest previous boudary */
 910         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 911         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 912         if (mod_link_pos >= fifo_size)
 913                 bound_pos = link_pos - mod_link_pos;
 914         else if (mod_dma_pos >= mod_mini_pos)
 915                 bound_pos = mini_pos - mod_mini_pos;
 916         else {
 917                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 918                 if (bound_pos >= azx_dev->core.bufsize)
 919                         bound_pos = 0;
 920         }
 921
 922         /* Calculate real DMA position we want */
 923         return bound_pos + mod_dma_pos;
 924 }
 925
 926 #define AMD_FIFO_SIZE   32
 927
 928 /* get the current DMA position with FIFO size correction */
 929 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 930 {
 931         struct snd_pcm_substream *substream = azx_dev->core.substream;
 932         struct snd_pcm_runtime *runtime = substream->runtime;
 933         unsigned int pos, delay;
 934
 935         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 936         if (!runtime)
 937                 return pos;
 938
 939         runtime->delay = AMD_FIFO_SIZE;
 940         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 941         if (azx_dev->insufficient) {
 942                 if (pos < delay) {
 943                         delay = pos;
 944                         runtime->delay = bytes_to_frames(runtime, pos);
 945                 } else {
 946                         azx_dev->insufficient = 0;
 947                 }
 948         }
 949
 950         /* correct the DMA position for capture stream */
 951         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 952                 if (pos < delay)
 953                         pos += azx_dev->core.bufsize;
 954                 pos -= delay;
 955         }
 956
 957         return pos;
 958 }
 959
 960 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 961                                    unsigned int pos)
 962 {
 963         struct snd_pcm_substream *substream = azx_dev->core.substream;
 964
 965         /* just read back the calculated value in the above */
 966         return substream->runtime->delay;
 967 }
 968
 969 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 970                                          struct azx_dev *azx_dev)
 971 {
 972         return _snd_hdac_chip_readl(azx_bus(chip),
 973                                     AZX_REG_VS_SDXDPIB_XBASE +
 974                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 975                                      azx_dev->core.index));
 976 }
 977
 978 /* get the current DMA position with correction on SKL+ chips */
 979 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 980 {
 981         /* DPIB register gives a more accurate position for playback */
 982         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 983                 return azx_skl_get_dpib_pos(chip, azx_dev);
 984
 985         /* For capture, we need to read posbuf, but it requires a delay
 986          * for the possible boundary overlap; the read of DPIB fetches the
 987          * actual posbuf
 988          */
 989         udelay(20);
 990         azx_skl_get_dpib_pos(chip, azx_dev);
 991         return azx_get_pos_posbuf(chip, azx_dev);
 992 }
 993
 994 #ifdef CONFIG_PM
 995 static DEFINE_MUTEX(card_list_lock);
 996 static LIST_HEAD(card_list);
 997
 998 static void azx_add_card_list(struct azx *chip)
 999 {
1000         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1001         mutex_lock(&card_list_lock);
1002         list_add(&hda->list, &card_list);
1003         mutex_unlock(&card_list_lock);
1004 }
1005
1006 static void azx_del_card_list(struct azx *chip)
1007 {
1008         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1009         mutex_lock(&card_list_lock);
1010         list_del_init(&hda->list);
1011         mutex_unlock(&card_list_lock);
1012 }
1013
1014 /* trigger power-save check at writing parameter */
1015 static int param_set_xint(const char *val, const struct kernel_param *kp)
1016 {
1017         struct hda_intel *hda;
1018         struct azx *chip;
1019         int prev = power_save;
1020         int ret = param_set_int(val, kp);
1021
1022         if (ret || prev == power_save)
1023                 return ret;
1024
1025         mutex_lock(&card_list_lock);
1026         list_for_each_entry(hda, &card_list, list) {
1027                 chip = &hda->chip;
1028                 if (!hda->probe_continued || chip->disabled)
1029                         continue;
1030                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1031         }
1032         mutex_unlock(&card_list_lock);
1033         return 0;
1034 }
1035 #else
1036 #define azx_add_card_list(chip) /* NOP */
1037 #define azx_del_card_list(chip) /* NOP */
1038 #endif /* CONFIG_PM */
1039
1040 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
1041 /*
1042  * power management
1043  */
1044 static int azx_suspend(struct device *dev)
1045 {
1046         struct snd_card *card = dev_get_drvdata(dev);
1047         struct azx *chip;
1048         struct hda_intel *hda;
1049         struct hdac_bus *bus;
1050
1051         if (!card)
1052                 return 0;
1053
1054         chip = card->private_data;
1055         hda = container_of(chip, struct hda_intel, chip);
1056         if (chip->disabled || hda->init_failed || !chip->running)
1057                 return 0;
1058
1059         bus = azx_bus(chip);
1060         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1061         azx_clear_irq_pending(chip);
1062         azx_stop_chip(chip);
1063         azx_enter_link_reset(chip);
1064         if (bus->irq >= 0) {
1065                 free_irq(bus->irq, chip);
1066                 bus->irq = -1;
1067         }
1068
1069         if (chip->msi)
1070                 pci_disable_msi(chip->pci);
1071         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1072                 && hda->need_i915_power)
1073                 snd_hdac_display_power(bus, false);
1074
1075         trace_azx_suspend(chip);
1076         return 0;
1077 }
1078
1079 static int azx_resume(struct device *dev)
1080 {
1081         struct pci_dev *pci = to_pci_dev(dev);
1082         struct snd_card *card = dev_get_drvdata(dev);
1083         struct azx *chip;
1084         struct hda_intel *hda;
1085         struct hdac_bus *bus;
1086
1087         if (!card)
1088                 return 0;
1089
1090         chip = card->private_data;
1091         hda = container_of(chip, struct hda_intel, chip);
1092         bus = azx_bus(chip);
1093         if (chip->disabled || hda->init_failed || !chip->running)
1094                 return 0;
1095
1096         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1097                 snd_hdac_display_power(bus, true);
1098                 if (hda->need_i915_power)
1099                         snd_hdac_i915_set_bclk(bus);
1100         }
1101
1102         if (chip->msi)
1103                 if (pci_enable_msi(pci) < 0)
1104                         chip->msi = 0;
1105         if (azx_acquire_irq(chip, 1) < 0)
1106                 return -EIO;
1107         azx_init_pci(chip);
1108
1109         hda_intel_init_chip(chip, true);
1110
1111         /* power down again for link-controlled chips */
1112         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1113             !hda->need_i915_power)
1114                 snd_hdac_display_power(bus, false);
1115
1116         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1117
1118         trace_azx_resume(chip);
1119         return 0;
1120 }
1121 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1122
1123 #ifdef CONFIG_PM_SLEEP
1124 /* put codec down to D3 at hibernation for Intel SKL+;
1125  * otherwise BIOS may still access the codec and screw up the driver
1126  */
1127 static int azx_freeze_noirq(struct device *dev)
1128 {
1129         struct snd_card *card = dev_get_drvdata(dev);
1130         struct azx *chip = card->private_data;
1131         struct pci_dev *pci = to_pci_dev(dev);
1132
1133         if (chip->driver_type == AZX_DRIVER_SKL)
1134                 pci_set_power_state(pci, PCI_D3hot);
1135
1136         return 0;
1137 }
1138
1139 static int azx_thaw_noirq(struct device *dev)
1140 {
1141         struct snd_card *card = dev_get_drvdata(dev);
1142         struct azx *chip = card->private_data;
1143         struct pci_dev *pci = to_pci_dev(dev);
1144
1145         if (chip->driver_type == AZX_DRIVER_SKL)
1146                 pci_set_power_state(pci, PCI_D0);
1147
1148         return 0;
1149 }
1150 #endif /* CONFIG_PM_SLEEP */
1151
1152 #ifdef CONFIG_PM
1153 static int azx_runtime_suspend(struct device *dev)
1154 {
1155         struct snd_card *card = dev_get_drvdata(dev);
1156         struct azx *chip;
1157         struct hda_intel *hda;
1158
1159         if (!card)
1160                 return 0;
1161
1162         chip = card->private_data;
1163         hda = container_of(chip, struct hda_intel, chip);
1164         if (chip->disabled || hda->init_failed)
1165                 return 0;
1166
1167         if (!azx_has_pm_runtime(chip))
1168                 return 0;
1169
1170         /* enable controller wake up event */
1171         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1172                   STATESTS_INT_MASK);
1173
1174         azx_stop_chip(chip);
1175         azx_enter_link_reset(chip);
1176         azx_clear_irq_pending(chip);
1177         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1178                 && hda->need_i915_power)
1179                 snd_hdac_display_power(azx_bus(chip), false);
1180
1181         trace_azx_runtime_suspend(chip);
1182         return 0;
1183 }
1184
1185 static int azx_runtime_resume(struct device *dev)
1186 {
1187         struct snd_card *card = dev_get_drvdata(dev);
1188         struct azx *chip;
1189         struct hda_intel *hda;
1190         struct hdac_bus *bus;
1191         struct hda_codec *codec;
1192         int status;
1193
1194         if (!card)
1195                 return 0;
1196
1197         chip = card->private_data;
1198         hda = container_of(chip, struct hda_intel, chip);
1199         bus = azx_bus(chip);
1200         if (chip->disabled || hda->init_failed)
1201                 return 0;
1202
1203         if (!azx_has_pm_runtime(chip))
1204                 return 0;
1205
1206         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1207                 snd_hdac_display_power(bus, true);
1208                 if (hda->need_i915_power)
1209                         snd_hdac_i915_set_bclk(bus);
1210         }
1211
1212         /* Read STATESTS before controller reset */
1213         status = azx_readw(chip, STATESTS);
1214
1215         azx_init_pci(chip);
1216         hda_intel_init_chip(chip, true);
1217
1218         if (status) {
1219                 list_for_each_codec(codec, &chip->bus)
1220                         if (status & (1 << codec->addr))
1221                                 schedule_delayed_work(&codec->jackpoll_work,
1222                                                       codec->jackpoll_interval);
1223         }
1224
1225         /* disable controller Wake Up event*/
1226         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1227                         ~STATESTS_INT_MASK);
1228
1229         /* power down again for link-controlled chips */
1230         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1231             !hda->need_i915_power)
1232                 snd_hdac_display_power(bus, false);
1233
1234         trace_azx_runtime_resume(chip);
1235         return 0;
1236 }
1237
1238 static int azx_runtime_idle(struct device *dev)
1239 {
1240         struct snd_card *card = dev_get_drvdata(dev);
1241         struct azx *chip;
1242         struct hda_intel *hda;
1243
1244         if (!card)
1245                 return 0;
1246
1247         chip = card->private_data;
1248         hda = container_of(chip, struct hda_intel, chip);
1249         if (chip->disabled || hda->init_failed)
1250                 return 0;
1251
1252         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1253             azx_bus(chip)->codec_powered || !chip->running)
1254                 return -EBUSY;
1255
1256         return 0;
1257 }
1258
1259 static const struct dev_pm_ops azx_pm = {
1260         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1261 #ifdef CONFIG_PM_SLEEP
1262         .freeze_noirq = azx_freeze_noirq,
1263         .thaw_noirq = azx_thaw_noirq,
1264 #endif
1265         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1266 };
1267
1268 #define AZX_PM_OPS      &azx_pm
1269 #else
1270 #define AZX_PM_OPS      NULL
1271 #endif /* CONFIG_PM */
1272
1273
1274 static int azx_probe_continue(struct azx *chip);
1275
1276 #ifdef SUPPORT_VGA_SWITCHEROO
1277 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1278
1279 static void azx_vs_set_state(struct pci_dev *pci,
1280                              enum vga_switcheroo_state state)
1281 {
1282         struct snd_card *card = pci_get_drvdata(pci);
1283         struct azx *chip = card->private_data;
1284         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285         struct hda_codec *codec;
1286         bool disabled;
1287
1288         wait_for_completion(&hda->probe_wait);
1289         if (hda->init_failed)
1290                 return;
1291
1292         disabled = (state == VGA_SWITCHEROO_OFF);
1293         if (chip->disabled == disabled)
1294                 return;
1295
1296         if (!hda->probe_continued) {
1297                 chip->disabled = disabled;
1298                 if (!disabled) {
1299                         dev_info(chip->card->dev,
1300                                  "Start delayed initialization\n");
1301                         if (azx_probe_continue(chip) < 0) {
1302                                 dev_err(chip->card->dev, "initialization error\n");
1303                                 hda->init_failed = true;
1304                         }
1305                 }
1306         } else {
1307                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1308                          disabled ? "Disabling" : "Enabling");
1309                 if (disabled) {
1310                         list_for_each_codec(codec, &chip->bus) {
1311                                 pm_runtime_suspend(hda_codec_dev(codec));
1312                                 pm_runtime_disable(hda_codec_dev(codec));
1313                         }
1314                         pm_runtime_suspend(card->dev);
1315                         pm_runtime_disable(card->dev);
1316                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1317                          * however we have no ACPI handle, so pci/acpi can't put us there,
1318                          * put ourselves there */
1319                         pci->current_state = PCI_D3cold;
1320                         chip->disabled = true;
1321                         if (snd_hda_lock_devices(&chip->bus))
1322                                 dev_warn(chip->card->dev,
1323                                          "Cannot lock devices!\n");
1324                 } else {
1325                         snd_hda_unlock_devices(&chip->bus);
1326                         chip->disabled = false;
1327                         pm_runtime_enable(card->dev);
1328                         list_for_each_codec(codec, &chip->bus) {
1329                                 pm_runtime_enable(hda_codec_dev(codec));
1330                                 pm_runtime_resume(hda_codec_dev(codec));
1331                         }
1332                 }
1333         }
1334 }
1335
1336 static bool azx_vs_can_switch(struct pci_dev *pci)
1337 {
1338         struct snd_card *card = pci_get_drvdata(pci);
1339         struct azx *chip = card->private_data;
1340         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1341
1342         wait_for_completion(&hda->probe_wait);
1343         if (hda->init_failed)
1344                 return false;
1345         if (chip->disabled || !hda->probe_continued)
1346                 return true;
1347         if (snd_hda_lock_devices(&chip->bus))
1348                 return false;
1349         snd_hda_unlock_devices(&chip->bus);
1350         return true;
1351 }
1352
1353 static void init_vga_switcheroo(struct azx *chip)
1354 {
1355         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1356         struct pci_dev *p = get_bound_vga(chip->pci);
1357         if (p) {
1358                 dev_info(chip->card->dev,
1359                          "Handle vga_switcheroo audio client\n");
1360                 hda->use_vga_switcheroo = 1;
1361                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1362                 pci_dev_put(p);
1363         }
1364 }
1365
1366 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1367         .set_gpu_state = azx_vs_set_state,
1368         .can_switch = azx_vs_can_switch,
1369 };
1370
1371 static int register_vga_switcheroo(struct azx *chip)
1372 {
1373         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1374         int err;
1375
1376         if (!hda->use_vga_switcheroo)
1377                 return 0;
1378         /* FIXME: currently only handling DIS controller
1379          * is there any machine with two switchable HDMI audio controllers?
1380          */
1381         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1382                                                    VGA_SWITCHEROO_DIS);
1383         if (err < 0)
1384                 return err;
1385         hda->vga_switcheroo_registered = 1;
1386
1387         return 0;
1388 }
1389 #else
1390 #define init_vga_switcheroo(chip)               /* NOP */
1391 #define register_vga_switcheroo(chip)           0
1392 #define check_hdmi_disabled(pci)        false
1393 #endif /* SUPPORT_VGA_SWITCHER */
1394
1395 /*
1396  * destructor
1397  */
1398 static int azx_free(struct azx *chip)
1399 {
1400         struct pci_dev *pci = chip->pci;
1401         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1402         struct hdac_bus *bus = azx_bus(chip);
1403
1404         if (azx_has_pm_runtime(chip) && chip->running)
1405                 pm_runtime_get_noresume(&pci->dev);
1406
1407         azx_del_card_list(chip);
1408
1409         hda->init_failed = 1; /* to be sure */
1410         complete_all(&hda->probe_wait);
1411
1412         if (use_vga_switcheroo(hda)) {
1413                 if (chip->disabled && hda->probe_continued)
1414                         snd_hda_unlock_devices(&chip->bus);
1415                 if (hda->vga_switcheroo_registered)
1416                         vga_switcheroo_unregister_client(chip->pci);
1417         }
1418
1419         if (bus->chip_init) {
1420                 azx_clear_irq_pending(chip);
1421                 azx_stop_all_streams(chip);
1422                 azx_stop_chip(chip);
1423         }
1424
1425         if (bus->irq >= 0)
1426                 free_irq(bus->irq, (void*)chip);
1427         if (chip->msi)
1428                 pci_disable_msi(chip->pci);
1429         iounmap(bus->remap_addr);
1430
1431         azx_free_stream_pages(chip);
1432         azx_free_streams(chip);
1433         snd_hdac_bus_exit(bus);
1434
1435         if (chip->region_requested)
1436                 pci_release_regions(chip->pci);
1437
1438         pci_disable_device(chip->pci);
1439 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1440         release_firmware(chip->fw);
1441 #endif
1442
1443         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1444                 if (hda->need_i915_power)
1445                         snd_hdac_display_power(bus, false);
1446         }
1447         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1448                 snd_hdac_i915_exit(bus);
1449         kfree(hda);
1450
1451         return 0;
1452 }
1453
1454 static int azx_dev_disconnect(struct snd_device *device)
1455 {
1456         struct azx *chip = device->device_data;
1457         struct hdac_bus *bus = azx_bus(chip);
1458
1459         chip->bus.shutdown = 1;
1460         cancel_work_sync(&bus->unsol_work);
1461
1462         return 0;
1463 }
1464
1465 static int azx_dev_free(struct snd_device *device)
1466 {
1467         return azx_free(device->device_data);
1468 }
1469
1470 #ifdef SUPPORT_VGA_SWITCHEROO
1471 /*
1472  * Check of disabled HDMI controller by vga_switcheroo
1473  */
1474 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1475 {
1476         struct pci_dev *p;
1477
1478         /* check only discrete GPU */
1479         switch (pci->vendor) {
1480         case PCI_VENDOR_ID_ATI:
1481         case PCI_VENDOR_ID_AMD:
1482         case PCI_VENDOR_ID_NVIDIA:
1483                 if (pci->devfn == 1) {
1484                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1485                                                         pci->bus->number, 0);
1486                         if (p) {
1487                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1488                                         return p;
1489                                 pci_dev_put(p);
1490                         }
1491                 }
1492                 break;
1493         }
1494         return NULL;
1495 }
1496
1497 static bool check_hdmi_disabled(struct pci_dev *pci)
1498 {
1499         bool vga_inactive = false;
1500         struct pci_dev *p = get_bound_vga(pci);
1501
1502         if (p) {
1503                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1504                         vga_inactive = true;
1505                 pci_dev_put(p);
1506         }
1507         return vga_inactive;
1508 }
1509 #endif /* SUPPORT_VGA_SWITCHEROO */
1510
1511 /*
1512  * white/black-listing for position_fix
1513  */
1514 static struct snd_pci_quirk position_fix_list[] = {
1515         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1522         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1523         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1524         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1525         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1526         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1527         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1528         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1529         {}
1530 };
1531
1532 static int check_position_fix(struct azx *chip, int fix)
1533 {
1534         const struct snd_pci_quirk *q;
1535
1536         switch (fix) {
1537         case POS_FIX_AUTO:
1538         case POS_FIX_LPIB:
1539         case POS_FIX_POSBUF:
1540         case POS_FIX_VIACOMBO:
1541         case POS_FIX_COMBO:
1542         case POS_FIX_SKL:
1543         case POS_FIX_FIFO:
1544                 return fix;
1545         }
1546
1547         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1548         if (q) {
1549                 dev_info(chip->card->dev,
1550                          "position_fix set to %d for device %04x:%04x\n",
1551                          q->value, q->subvendor, q->subdevice);
1552                 return q->value;
1553         }
1554
1555         /* Check VIA/ATI HD Audio Controller exist */
1556         if (chip->driver_type == AZX_DRIVER_VIA) {
1557                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1558                 return POS_FIX_VIACOMBO;
1559         }
1560         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1561                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1562                 return POS_FIX_FIFO;
1563         }
1564         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1565                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1566                 return POS_FIX_LPIB;
1567         }
1568         if (chip->driver_type == AZX_DRIVER_SKL) {
1569                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1570                 return POS_FIX_SKL;
1571         }
1572         return POS_FIX_AUTO;
1573 }
1574
1575 static void assign_position_fix(struct azx *chip, int fix)
1576 {
1577         static azx_get_pos_callback_t callbacks[] = {
1578                 [POS_FIX_AUTO] = NULL,
1579                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1580                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1581                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1582                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1583                 [POS_FIX_SKL] = azx_get_pos_skl,
1584                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1585         };
1586
1587         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1588
1589         /* combo mode uses LPIB only for playback */
1590         if (fix == POS_FIX_COMBO)
1591                 chip->get_position[1] = NULL;
1592
1593         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1594             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1595                 chip->get_delay[0] = chip->get_delay[1] =
1596                         azx_get_delay_from_lpib;
1597         }
1598
1599         if (fix == POS_FIX_FIFO)
1600                 chip->get_delay[0] = chip->get_delay[1] =
1601                         azx_get_delay_from_fifo;
1602 }
1603
1604 /*
1605  * black-lists for probe_mask
1606  */
1607 static struct snd_pci_quirk probe_mask_list[] = {
1608         /* Thinkpad often breaks the controller communication when accessing
1609          * to the non-working (or non-existing) modem codec slot.
1610          */
1611         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1612         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1613         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1614         /* broken BIOS */
1615         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1616         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1617         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1618         /* forced codec slots */
1619         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1620         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1621         /* WinFast VP200 H (Teradici) user reported broken communication */
1622         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1623         {}
1624 };
1625
1626 #define AZX_FORCE_CODEC_MASK    0x100
1627
1628 static void check_probe_mask(struct azx *chip, int dev)
1629 {
1630         const struct snd_pci_quirk *q;
1631
1632         chip->codec_probe_mask = probe_mask[dev];
1633         if (chip->codec_probe_mask == -1) {
1634                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1635                 if (q) {
1636                         dev_info(chip->card->dev,
1637                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1638                                  q->value, q->subvendor, q->subdevice);
1639                         chip->codec_probe_mask = q->value;
1640                 }
1641         }
1642
1643         /* check forced option */
1644         if (chip->codec_probe_mask != -1 &&
1645             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1646                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1647                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1648                          (int)azx_bus(chip)->codec_mask);
1649         }
1650 }
1651
1652 /*
1653  * white/black-list for enable_msi
1654  */
1655 static struct snd_pci_quirk msi_black_list[] = {
1656         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1657         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1658         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1659         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1660         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1661         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1662         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1663         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1664         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1665         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1666         {}
1667 };
1668
1669 static void check_msi(struct azx *chip)
1670 {
1671         const struct snd_pci_quirk *q;
1672
1673         if (enable_msi >= 0) {
1674                 chip->msi = !!enable_msi;
1675                 return;
1676         }
1677         chip->msi = 1;  /* enable MSI as default */
1678         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1679         if (q) {
1680                 dev_info(chip->card->dev,
1681                          "msi for device %04x:%04x set to %d\n",
1682                          q->subvendor, q->subdevice, q->value);
1683                 chip->msi = q->value;
1684                 return;
1685         }
1686
1687         /* NVidia chipsets seem to cause troubles with MSI */
1688         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1689                 dev_info(chip->card->dev, "Disabling MSI\n");
1690                 chip->msi = 0;
1691         }
1692 }
1693
1694 /* check the snoop mode availability */
1695 static void azx_check_snoop_available(struct azx *chip)
1696 {
1697         int snoop = hda_snoop;
1698
1699         if (snoop >= 0) {
1700                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1701                          snoop ? "snoop" : "non-snoop");
1702                 chip->snoop = snoop;
1703                 chip->uc_buffer = !snoop;
1704                 return;
1705         }
1706
1707         snoop = true;
1708         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1709             chip->driver_type == AZX_DRIVER_VIA) {
1710                 /* force to non-snoop mode for a new VIA controller
1711                  * when BIOS is set
1712                  */
1713                 u8 val;
1714                 pci_read_config_byte(chip->pci, 0x42, &val);
1715                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1716                                       chip->pci->revision == 0x20))
1717                         snoop = false;
1718         }
1719
1720         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1721                 snoop = false;
1722
1723         chip->snoop = snoop;
1724         if (!snoop) {
1725                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1726                 /* C-Media requires non-cached pages only for CORB/RIRB */
1727                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1728                         chip->uc_buffer = true;
1729         }
1730 }
1731
1732 static void azx_probe_work(struct work_struct *work)
1733 {
1734         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1735         azx_probe_continue(&hda->chip);
1736 }
1737
1738 static int default_bdl_pos_adj(struct azx *chip)
1739 {
1740         /* some exceptions: Atoms seem problematic with value 1 */
1741         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1742                 switch (chip->pci->device) {
1743                 case 0x0f04: /* Baytrail */
1744                 case 0x2284: /* Braswell */
1745                         return 32;
1746                 }
1747         }
1748
1749         switch (chip->driver_type) {
1750         case AZX_DRIVER_ICH:
1751         case AZX_DRIVER_PCH:
1752                 return 1;
1753         default:
1754                 return 32;
1755         }
1756 }
1757
1758 /*
1759  * constructor
1760  */
1761 static const struct hdac_io_ops pci_hda_io_ops;
1762 static const struct hda_controller_ops pci_hda_ops;
1763
1764 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1765                       int dev, unsigned int driver_caps,
1766                       struct azx **rchip)
1767 {
1768         static struct snd_device_ops ops = {
1769                 .dev_disconnect = azx_dev_disconnect,
1770                 .dev_free = azx_dev_free,
1771         };
1772         struct hda_intel *hda;
1773         struct azx *chip;
1774         int err;
1775
1776         *rchip = NULL;
1777
1778         err = pci_enable_device(pci);
1779         if (err < 0)
1780                 return err;
1781
1782         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1783         if (!hda) {
1784                 pci_disable_device(pci);
1785                 return -ENOMEM;
1786         }
1787
1788         chip = &hda->chip;
1789         mutex_init(&chip->open_mutex);
1790         chip->card = card;
1791         chip->pci = pci;
1792         chip->ops = &pci_hda_ops;
1793         chip->driver_caps = driver_caps;
1794         chip->driver_type = driver_caps & 0xff;
1795         check_msi(chip);
1796         chip->dev_index = dev;
1797         chip->jackpoll_ms = jackpoll_ms;
1798         INIT_LIST_HEAD(&chip->pcm_list);
1799         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1800         INIT_LIST_HEAD(&hda->list);
1801         init_vga_switcheroo(chip);
1802         init_completion(&hda->probe_wait);
1803
1804         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1805
1806         check_probe_mask(chip, dev);
1807
1808         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1809                 chip->fallback_to_single_cmd = 1;
1810         else /* explicitly set to single_cmd or not */
1811                 chip->single_cmd = single_cmd;
1812
1813         azx_check_snoop_available(chip);
1814
1815         if (bdl_pos_adj[dev] < 0)
1816                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1817         else
1818                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1819
1820         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1821         if (IS_CFL(pci) || IS_CNL(pci))
1822                 chip->polling_mode = 1;
1823
1824         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1825         if (err < 0) {
1826                 kfree(hda);
1827                 pci_disable_device(pci);
1828                 return err;
1829         }
1830
1831         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1832                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1833                 chip->bus.needs_damn_long_delay = 1;
1834         }
1835
1836         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1837         if (err < 0) {
1838                 dev_err(card->dev, "Error creating device [card]!\n");
1839                 azx_free(chip);
1840                 return err;
1841         }
1842
1843         /* continue probing in work context as may trigger request module */
1844         INIT_WORK(&hda->probe_work, azx_probe_work);
1845
1846         *rchip = chip;
1847
1848         return 0;
1849 }
1850
1851 static int azx_first_init(struct azx *chip)
1852 {
1853         int dev = chip->dev_index;
1854         struct pci_dev *pci = chip->pci;
1855         struct snd_card *card = chip->card;
1856         struct hdac_bus *bus = azx_bus(chip);
1857         int err;
1858         unsigned short gcap;
1859         unsigned int dma_bits = 64;
1860
1861 #if BITS_PER_LONG != 64
1862         /* Fix up base address on ULI M5461 */
1863         if (chip->driver_type == AZX_DRIVER_ULI) {
1864                 u16 tmp3;
1865                 pci_read_config_word(pci, 0x40, &tmp3);
1866                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1867                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1868         }
1869 #endif
1870
1871         err = pci_request_regions(pci, "ICH HD audio");
1872         if (err < 0)
1873                 return err;
1874         chip->region_requested = 1;
1875
1876         bus->addr = pci_resource_start(pci, 0);
1877         bus->remap_addr = pci_ioremap_bar(pci, 0);
1878         if (bus->remap_addr == NULL) {
1879                 dev_err(card->dev, "ioremap error\n");
1880                 return -ENXIO;
1881         }
1882
1883         if (chip->driver_type == AZX_DRIVER_SKL)
1884                 snd_hdac_bus_parse_capabilities(bus);
1885
1886         /*
1887          * Some Intel CPUs has always running timer (ART) feature and
1888          * controller may have Global time sync reporting capability, so
1889          * check both of these before declaring synchronized time reporting
1890          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1891          */
1892         chip->gts_present = false;
1893
1894 #ifdef CONFIG_X86
1895         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1896                 chip->gts_present = true;
1897 #endif
1898
1899         if (chip->msi) {
1900                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1901                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1902                         pci->no_64bit_msi = true;
1903                 }
1904                 if (pci_enable_msi(pci) < 0)
1905                         chip->msi = 0;
1906         }
1907
1908         pci_set_master(pci);
1909         synchronize_irq(bus->irq);
1910
1911         gcap = azx_readw(chip, GCAP);
1912         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1913
1914         /* AMD devices support 40 or 48bit DMA, take the safe one */
1915         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1916                 dma_bits = 40;
1917
1918         /* disable SB600 64bit support for safety */
1919         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1920                 struct pci_dev *p_smbus;
1921                 dma_bits = 40;
1922                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1923                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1924                                          NULL);
1925                 if (p_smbus) {
1926                         if (p_smbus->revision < 0x30)
1927                                 gcap &= ~AZX_GCAP_64OK;
1928                         pci_dev_put(p_smbus);
1929                 }
1930         }
1931
1932         /* NVidia hardware normally only supports up to 40 bits of DMA */
1933         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1934                 dma_bits = 40;
1935
1936         /* disable 64bit DMA address on some devices */
1937         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1938                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1939                 gcap &= ~AZX_GCAP_64OK;
1940         }
1941
1942         /* disable buffer size rounding to 128-byte multiples if supported */
1943         if (align_buffer_size >= 0)
1944                 chip->align_buffer_size = !!align_buffer_size;
1945         else {
1946                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1947                         chip->align_buffer_size = 0;
1948                 else
1949                         chip->align_buffer_size = 1;
1950         }
1951
1952         /* allow 64bit DMA address if supported by H/W */
1953         if (!(gcap & AZX_GCAP_64OK))
1954                 dma_bits = 32;
1955         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1956                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1957         } else {
1958                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1959                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1960         }
1961
1962         /* read number of streams from GCAP register instead of using
1963          * hardcoded value
1964          */
1965         chip->capture_streams = (gcap >> 8) & 0x0f;
1966         chip->playback_streams = (gcap >> 12) & 0x0f;
1967         if (!chip->playback_streams && !chip->capture_streams) {
1968                 /* gcap didn't give any info, switching to old method */
1969
1970                 switch (chip->driver_type) {
1971                 case AZX_DRIVER_ULI:
1972                         chip->playback_streams = ULI_NUM_PLAYBACK;
1973                         chip->capture_streams = ULI_NUM_CAPTURE;
1974                         break;
1975                 case AZX_DRIVER_ATIHDMI:
1976                 case AZX_DRIVER_ATIHDMI_NS:
1977                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1978                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1979                         break;
1980                 case AZX_DRIVER_GENERIC:
1981                 default:
1982                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1983                         chip->capture_streams = ICH6_NUM_CAPTURE;
1984                         break;
1985                 }
1986         }
1987         chip->capture_index_offset = 0;
1988         chip->playback_index_offset = chip->capture_streams;
1989         chip->num_streams = chip->playback_streams + chip->capture_streams;
1990
1991         /* sanity check for the SDxCTL.STRM field overflow */
1992         if (chip->num_streams > 15 &&
1993             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1994                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1995                          "forcing separate stream tags", chip->num_streams);
1996                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1997         }
1998
1999         /* initialize streams */
2000         err = azx_init_streams(chip);
2001         if (err < 0)
2002                 return err;
2003
2004         err = azx_alloc_stream_pages(chip);
2005         if (err < 0)
2006                 return err;
2007
2008         /* initialize chip */
2009         azx_init_pci(chip);
2010
2011         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2012                 snd_hdac_i915_set_bclk(bus);
2013
2014         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2015
2016         /* codec detection */
2017         if (!azx_bus(chip)->codec_mask) {
2018                 dev_err(card->dev, "no codecs found!\n");
2019                 return -ENODEV;
2020         }
2021
2022         if (azx_acquire_irq(chip, 0) < 0)
2023                 return -EBUSY;
2024
2025         strcpy(card->driver, "HDA-Intel");
2026         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2027                 sizeof(card->shortname));
2028         snprintf(card->longname, sizeof(card->longname),
2029                  "%s at 0x%lx irq %i",
2030                  card->shortname, bus->addr, bus->irq);
2031
2032         return 0;
2033 }
2034
2035 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2036 /* callback from request_firmware_nowait() */
2037 static void azx_firmware_cb(const struct firmware *fw, void *context)
2038 {
2039         struct snd_card *card = context;
2040         struct azx *chip = card->private_data;
2041
2042         if (fw)
2043                 chip->fw = fw;
2044         else
2045                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2046         if (!chip->disabled) {
2047                 /* continue probing */
2048                 azx_probe_continue(chip);
2049         }
2050 }
2051 #endif
2052
2053 /*
2054  * HDA controller ops.
2055  */
2056
2057 /* PCI register access. */
2058 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2059 {
2060         writel(value, addr);
2061 }
2062
2063 static u32 pci_azx_readl(u32 __iomem *addr)
2064 {
2065         return readl(addr);
2066 }
2067
2068 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2069 {
2070         writew(value, addr);
2071 }
2072
2073 static u16 pci_azx_readw(u16 __iomem *addr)
2074 {
2075         return readw(addr);
2076 }
2077
2078 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2079 {
2080         writeb(value, addr);
2081 }
2082
2083 static u8 pci_azx_readb(u8 __iomem *addr)
2084 {
2085         return readb(addr);
2086 }
2087
2088 static int disable_msi_reset_irq(struct azx *chip)
2089 {
2090         struct hdac_bus *bus = azx_bus(chip);
2091         int err;
2092
2093         free_irq(bus->irq, chip);
2094         bus->irq = -1;
2095         pci_disable_msi(chip->pci);
2096         chip->msi = 0;
2097         err = azx_acquire_irq(chip, 1);
2098         if (err < 0)
2099                 return err;
2100
2101         return 0;
2102 }
2103
2104 /* DMA page allocation helpers.  */
2105 static int dma_alloc_pages(struct hdac_bus *bus,
2106                            int type,
2107                            size_t size,
2108                            struct snd_dma_buffer *buf)
2109 {
2110         struct azx *chip = bus_to_azx(bus);
2111         int err;
2112
2113         err = snd_dma_alloc_pages(type,
2114                                   bus->dev,
2115                                   size, buf);
2116         if (err < 0)
2117                 return err;
2118         mark_pages_wc(chip, buf, true);
2119         return 0;
2120 }
2121
2122 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2123 {
2124         struct azx *chip = bus_to_azx(bus);
2125
2126         mark_pages_wc(chip, buf, false);
2127         snd_dma_free_pages(buf);
2128 }
2129
2130 static int substream_alloc_pages(struct azx *chip,
2131                                  struct snd_pcm_substream *substream,
2132                                  size_t size)
2133 {
2134         struct azx_dev *azx_dev = get_azx_dev(substream);
2135         int ret;
2136
2137         mark_runtime_wc(chip, azx_dev, substream, false);
2138         ret = snd_pcm_lib_malloc_pages(substream, size);
2139         if (ret < 0)
2140                 return ret;
2141         mark_runtime_wc(chip, azx_dev, substream, true);
2142         return 0;
2143 }
2144
2145 static int substream_free_pages(struct azx *chip,
2146                                 struct snd_pcm_substream *substream)
2147 {
2148         struct azx_dev *azx_dev = get_azx_dev(substream);
2149         mark_runtime_wc(chip, azx_dev, substream, false);
2150         return snd_pcm_lib_free_pages(substream);
2151 }
2152
2153 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2154                              struct vm_area_struct *area)
2155 {
2156 #ifdef CONFIG_X86
2157         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2158         struct azx *chip = apcm->chip;
2159         if (chip->uc_buffer)
2160                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2161 #endif
2162 }
2163
2164 static const struct hdac_io_ops pci_hda_io_ops = {
2165         .reg_writel = pci_azx_writel,
2166         .reg_readl = pci_azx_readl,
2167         .reg_writew = pci_azx_writew,
2168         .reg_readw = pci_azx_readw,
2169         .reg_writeb = pci_azx_writeb,
2170         .reg_readb = pci_azx_readb,
2171         .dma_alloc_pages = dma_alloc_pages,
2172         .dma_free_pages = dma_free_pages,
2173 };
2174
2175 /* Blacklist for skipping the whole probe:
2176  * some HD-audio PCI entries are exposed without any codecs, and such devices
2177  * should be ignored from the beginning.
2178  */
2179 static const struct pci_device_id driver_blacklist[] = {
2180         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2181         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2182         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2183         {}
2184 };
2185
2186 static const struct hda_controller_ops pci_hda_ops = {
2187         .disable_msi_reset_irq = disable_msi_reset_irq,
2188         .substream_alloc_pages = substream_alloc_pages,
2189         .substream_free_pages = substream_free_pages,
2190         .pcm_mmap_prepare = pcm_mmap_prepare,
2191         .position_check = azx_position_check,
2192         .link_power = azx_intel_link_power,
2193 };
2194
2195 static int azx_probe(struct pci_dev *pci,
2196                      const struct pci_device_id *pci_id)
2197 {
2198         static int dev;
2199         struct snd_card *card;
2200         struct hda_intel *hda;
2201         struct azx *chip;
2202         bool schedule_probe;
2203         int err;
2204
2205         if (pci_match_id(driver_blacklist, pci)) {
2206                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2207                 return -ENODEV;
2208         }
2209
2210         if (dev >= SNDRV_CARDS)
2211                 return -ENODEV;
2212         if (!enable[dev]) {
2213                 dev++;
2214                 return -ENOENT;
2215         }
2216
2217         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2218                            0, &card);
2219         if (err < 0) {
2220                 dev_err(&pci->dev, "Error creating card!\n");
2221                 return err;
2222         }
2223
2224         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2225         if (err < 0)
2226                 goto out_free;
2227         card->private_data = chip;
2228         hda = container_of(chip, struct hda_intel, chip);
2229
2230         pci_set_drvdata(pci, card);
2231
2232         err = register_vga_switcheroo(chip);
2233         if (err < 0) {
2234                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2235                 goto out_free;
2236         }
2237
2238         if (check_hdmi_disabled(pci)) {
2239                 dev_info(card->dev, "VGA controller is disabled\n");
2240                 dev_info(card->dev, "Delaying initialization\n");
2241                 chip->disabled = true;
2242         }
2243
2244         schedule_probe = !chip->disabled;
2245
2246 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2247         if (patch[dev] && *patch[dev]) {
2248                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2249                          patch[dev]);
2250                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2251                                               &pci->dev, GFP_KERNEL, card,
2252                                               azx_firmware_cb);
2253                 if (err < 0)
2254                         goto out_free;
2255                 schedule_probe = false; /* continued in azx_firmware_cb() */
2256         }
2257 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2258
2259 #ifndef CONFIG_SND_HDA_I915
2260         if (CONTROLLER_IN_GPU(pci))
2261                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2262 #endif
2263
2264         if (schedule_probe)
2265                 schedule_work(&hda->probe_work);
2266
2267         dev++;
2268         if (chip->disabled)
2269                 complete_all(&hda->probe_wait);
2270         return 0;
2271
2272 out_free:
2273         snd_card_free(card);
2274         return err;
2275 }
2276
2277 #ifdef CONFIG_PM
2278 /* On some boards setting power_save to a non 0 value leads to clicking /
2279  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2280  * figure out how to avoid these sounds, but that is not always feasible.
2281  * So we keep a list of devices where we disable powersaving as its known
2282  * to causes problems on these devices.
2283  */
2284 static struct snd_pci_quirk power_save_blacklist[] = {
2285         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2286         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2287         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2288         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2289         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2290         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2291         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2292         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2293         {}
2294 };
2295 #endif /* CONFIG_PM */
2296
2297 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2298 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2299         [AZX_DRIVER_NVIDIA] = 8,
2300         [AZX_DRIVER_TERA] = 1,
2301 };
2302
2303 static int azx_probe_continue(struct azx *chip)
2304 {
2305         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2306         struct hdac_bus *bus = azx_bus(chip);
2307         struct pci_dev *pci = chip->pci;
2308         struct hda_codec *codec;
2309         int dev = chip->dev_index;
2310         int val;
2311         int err;
2312
2313         to_hda_bus(bus)->bus_probing = 1;
2314         hda->probe_continued = 1;
2315
2316         /* bind with i915 if needed */
2317         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2318                 err = snd_hdac_i915_init(bus);
2319                 if (err < 0) {
2320                         /* if the controller is bound only with HDMI/DP
2321                          * (for HSW and BDW), we need to abort the probe;
2322                          * for other chips, still continue probing as other
2323                          * codecs can be on the same link.
2324                          */
2325                         if (CONTROLLER_IN_GPU(pci)) {
2326                                 dev_err(chip->card->dev,
2327                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2328                                 goto out_free;
2329                         } else {
2330                                 /* don't bother any longer */
2331                                 chip->driver_caps &=
2332                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2333                         }
2334                 }
2335         }
2336
2337         /* Request display power well for the HDA controller or codec. For
2338          * Haswell/Broadwell, both the display HDA controller and codec need
2339          * this power. For other platforms, like Baytrail/Braswell, only the
2340          * display codec needs the power and it can be released after probe.
2341          */
2342         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2343                 /* HSW/BDW controllers need this power */
2344                 if (CONTROLLER_IN_GPU(pci))
2345                         hda->need_i915_power = 1;
2346
2347                 err = snd_hdac_display_power(bus, true);
2348                 if (err < 0) {
2349                         dev_err(chip->card->dev,
2350                                 "Cannot turn on display power on i915\n");
2351                         goto i915_power_fail;
2352                 }
2353         }
2354
2355         err = azx_first_init(chip);
2356         if (err < 0)
2357                 goto out_free;
2358
2359 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2360         chip->beep_mode = beep_mode[dev];
2361 #endif
2362
2363         /* create codec instances */
2364         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2365         if (err < 0)
2366                 goto out_free;
2367
2368 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2369         if (chip->fw) {
2370                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2371                                          chip->fw->data);
2372                 if (err < 0)
2373                         goto out_free;
2374 #ifndef CONFIG_PM
2375                 release_firmware(chip->fw); /* no longer needed */
2376                 chip->fw = NULL;
2377 #endif
2378         }
2379 #endif
2380         if ((probe_only[dev] & 1) == 0) {
2381                 err = azx_codec_configure(chip);
2382                 if (err < 0)
2383                         goto out_free;
2384         }
2385
2386         err = snd_card_register(chip->card);
2387         if (err < 0)
2388                 goto out_free;
2389
2390         chip->running = 1;
2391         azx_add_card_list(chip);
2392
2393         /*
2394          * The discrete GPU cannot power down unless the HDA controller runtime
2395          * suspends, so activate runtime PM on codecs even if power_save == 0.
2396          */
2397         if (use_vga_switcheroo(hda))
2398                 list_for_each_codec(codec, &chip->bus)
2399                         codec->auto_runtime_pm = 1;
2400
2401         val = power_save;
2402 #ifdef CONFIG_PM
2403         if (pm_blacklist) {
2404                 const struct snd_pci_quirk *q;
2405
2406                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2407                 if (q && val) {
2408                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2409                                  q->subvendor, q->subdevice);
2410                         val = 0;
2411                 }
2412         }
2413 #endif /* CONFIG_PM */
2414         snd_hda_set_power_save(&chip->bus, val * 1000);
2415         if (azx_has_pm_runtime(chip))
2416                 pm_runtime_put_autosuspend(&pci->dev);
2417
2418 out_free:
2419         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2420                 && !hda->need_i915_power)
2421                 snd_hdac_display_power(bus, false);
2422
2423 i915_power_fail:
2424         if (err < 0)
2425                 hda->init_failed = 1;
2426         complete_all(&hda->probe_wait);
2427         to_hda_bus(bus)->bus_probing = 0;
2428         return err;
2429 }
2430
2431 static void azx_remove(struct pci_dev *pci)
2432 {
2433         struct snd_card *card = pci_get_drvdata(pci);
2434         struct azx *chip;
2435         struct hda_intel *hda;
2436
2437         if (card) {
2438                 /* cancel the pending probing work */
2439                 chip = card->private_data;
2440                 hda = container_of(chip, struct hda_intel, chip);
2441                 /* FIXME: below is an ugly workaround.
2442                  * Both device_release_driver() and driver_probe_device()
2443                  * take *both* the device's and its parent's lock before
2444                  * calling the remove() and probe() callbacks.  The codec
2445                  * probe takes the locks of both the codec itself and its
2446                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2447                  * the PCI controller is unbound, it takes its lock, too
2448                  * ==> ouch, a deadlock!
2449                  * As a workaround, we unlock temporarily here the controller
2450                  * device during cancel_work_sync() call.
2451                  */
2452                 device_unlock(&pci->dev);
2453                 cancel_work_sync(&hda->probe_work);
2454                 device_lock(&pci->dev);
2455
2456                 snd_card_free(card);
2457         }
2458 }
2459
2460 static void azx_shutdown(struct pci_dev *pci)
2461 {
2462         struct snd_card *card = pci_get_drvdata(pci);
2463         struct azx *chip;
2464
2465         if (!card)
2466                 return;
2467         chip = card->private_data;
2468         if (chip && chip->running)
2469                 azx_stop_chip(chip);
2470 }
2471
2472 /* PCI IDs */
2473 static const struct pci_device_id azx_ids[] = {
2474         /* CPT */
2475         { PCI_DEVICE(0x8086, 0x1c20),
2476           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2477         /* PBG */
2478         { PCI_DEVICE(0x8086, 0x1d20),
2479           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2480         /* Panther Point */
2481         { PCI_DEVICE(0x8086, 0x1e20),
2482           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2483         /* Lynx Point */
2484         { PCI_DEVICE(0x8086, 0x8c20),
2485           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2486         /* 9 Series */
2487         { PCI_DEVICE(0x8086, 0x8ca0),
2488           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2489         /* Wellsburg */
2490         { PCI_DEVICE(0x8086, 0x8d20),
2491           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2492         { PCI_DEVICE(0x8086, 0x8d21),
2493           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2494         /* Lewisburg */
2495         { PCI_DEVICE(0x8086, 0xa1f0),
2496           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2497         { PCI_DEVICE(0x8086, 0xa270),
2498           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2499         /* Lynx Point-LP */
2500         { PCI_DEVICE(0x8086, 0x9c20),
2501           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2502         /* Lynx Point-LP */
2503         { PCI_DEVICE(0x8086, 0x9c21),
2504           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2505         /* Wildcat Point-LP */
2506         { PCI_DEVICE(0x8086, 0x9ca0),
2507           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2508         /* Sunrise Point */
2509         { PCI_DEVICE(0x8086, 0xa170),
2510           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2511         /* Sunrise Point-LP */
2512         { PCI_DEVICE(0x8086, 0x9d70),
2513           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2514         /* Kabylake */
2515         { PCI_DEVICE(0x8086, 0xa171),
2516           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2517         /* Kabylake-LP */
2518         { PCI_DEVICE(0x8086, 0x9d71),
2519           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2520         /* Kabylake-H */
2521         { PCI_DEVICE(0x8086, 0xa2f0),
2522           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2523         /* Coffelake */
2524         { PCI_DEVICE(0x8086, 0xa348),
2525           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2526         /* Cannonlake */
2527         { PCI_DEVICE(0x8086, 0x9dc8),
2528           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2529         /* Broxton-P(Apollolake) */
2530         { PCI_DEVICE(0x8086, 0x5a98),
2531           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2532         /* Broxton-T */
2533         { PCI_DEVICE(0x8086, 0x1a98),
2534           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2535         /* Gemini-Lake */
2536         { PCI_DEVICE(0x8086, 0x3198),
2537           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2538         /* Haswell */
2539         { PCI_DEVICE(0x8086, 0x0a0c),
2540           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2541         { PCI_DEVICE(0x8086, 0x0c0c),
2542           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2543         { PCI_DEVICE(0x8086, 0x0d0c),
2544           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2545         /* Broadwell */
2546         { PCI_DEVICE(0x8086, 0x160c),
2547           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2548         /* 5 Series/3400 */
2549         { PCI_DEVICE(0x8086, 0x3b56),
2550           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2551         /* Poulsbo */
2552         { PCI_DEVICE(0x8086, 0x811b),
2553           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2554         /* Oaktrail */
2555         { PCI_DEVICE(0x8086, 0x080a),
2556           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2557         /* BayTrail */
2558         { PCI_DEVICE(0x8086, 0x0f04),
2559           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2560         /* Braswell */
2561         { PCI_DEVICE(0x8086, 0x2284),
2562           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2563         /* ICH6 */
2564         { PCI_DEVICE(0x8086, 0x2668),
2565           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2566         /* ICH7 */
2567         { PCI_DEVICE(0x8086, 0x27d8),
2568           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2569         /* ESB2 */
2570         { PCI_DEVICE(0x8086, 0x269a),
2571           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2572         /* ICH8 */
2573         { PCI_DEVICE(0x8086, 0x284b),
2574           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2575         /* ICH9 */
2576         { PCI_DEVICE(0x8086, 0x293e),
2577           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2578         /* ICH9 */
2579         { PCI_DEVICE(0x8086, 0x293f),
2580           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2581         /* ICH10 */
2582         { PCI_DEVICE(0x8086, 0x3a3e),
2583           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2584         /* ICH10 */
2585         { PCI_DEVICE(0x8086, 0x3a6e),
2586           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2587         /* Generic Intel */
2588         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2589           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2590           .class_mask = 0xffffff,
2591           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2592         /* ATI SB 450/600/700/800/900 */
2593         { PCI_DEVICE(0x1002, 0x437b),
2594           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2595         { PCI_DEVICE(0x1002, 0x4383),
2596           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2597         /* AMD Hudson */
2598         { PCI_DEVICE(0x1022, 0x780d),
2599           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2600         /* AMD, X370 & co */
2601         { PCI_DEVICE(0x1022, 0x1457),
2602           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2603         /* AMD, X570 & co */
2604         { PCI_DEVICE(0x1022, 0x1487),
2605           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2606         /* AMD Stoney */
2607         { PCI_DEVICE(0x1022, 0x157a),
2608           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2609                          AZX_DCAPS_PM_RUNTIME },
2610         /* AMD Raven */
2611         { PCI_DEVICE(0x1022, 0x15e3),
2612           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2613         /* ATI HDMI */
2614         { PCI_DEVICE(0x1002, 0x0002),
2615           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2616         { PCI_DEVICE(0x1002, 0x1308),
2617           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2618         { PCI_DEVICE(0x1002, 0x157a),
2619           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2620         { PCI_DEVICE(0x1002, 0x15b3),
2621           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2622         { PCI_DEVICE(0x1002, 0x793b),
2623           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2624         { PCI_DEVICE(0x1002, 0x7919),
2625           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2626         { PCI_DEVICE(0x1002, 0x960f),
2627           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2628         { PCI_DEVICE(0x1002, 0x970f),
2629           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630         { PCI_DEVICE(0x1002, 0x9840),
2631           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2632         { PCI_DEVICE(0x1002, 0xaa00),
2633           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634         { PCI_DEVICE(0x1002, 0xaa08),
2635           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636         { PCI_DEVICE(0x1002, 0xaa10),
2637           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638         { PCI_DEVICE(0x1002, 0xaa18),
2639           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2640         { PCI_DEVICE(0x1002, 0xaa20),
2641           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642         { PCI_DEVICE(0x1002, 0xaa28),
2643           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644         { PCI_DEVICE(0x1002, 0xaa30),
2645           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646         { PCI_DEVICE(0x1002, 0xaa38),
2647           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648         { PCI_DEVICE(0x1002, 0xaa40),
2649           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2650         { PCI_DEVICE(0x1002, 0xaa48),
2651           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652         { PCI_DEVICE(0x1002, 0xaa50),
2653           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2654         { PCI_DEVICE(0x1002, 0xaa58),
2655           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656         { PCI_DEVICE(0x1002, 0xaa60),
2657           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658         { PCI_DEVICE(0x1002, 0xaa68),
2659           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660         { PCI_DEVICE(0x1002, 0xaa80),
2661           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662         { PCI_DEVICE(0x1002, 0xaa88),
2663           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664         { PCI_DEVICE(0x1002, 0xaa90),
2665           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2666         { PCI_DEVICE(0x1002, 0xaa98),
2667           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2668         { PCI_DEVICE(0x1002, 0x9902),
2669           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2670         { PCI_DEVICE(0x1002, 0xaaa0),
2671           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2672         { PCI_DEVICE(0x1002, 0xaaa8),
2673           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2674         { PCI_DEVICE(0x1002, 0xaab0),
2675           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2676         { PCI_DEVICE(0x1002, 0xaac0),
2677           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2678         { PCI_DEVICE(0x1002, 0xaac8),
2679           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2680         { PCI_DEVICE(0x1002, 0xaad8),
2681           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2682         { PCI_DEVICE(0x1002, 0xaae8),
2683           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2684         { PCI_DEVICE(0x1002, 0xaae0),
2685           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2686         { PCI_DEVICE(0x1002, 0xaaf0),
2687           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2688         /* VIA VT8251/VT8237A */
2689         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2690         /* VIA GFX VT7122/VX900 */
2691         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2692         /* VIA GFX VT6122/VX11 */
2693         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2694         /* SIS966 */
2695         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2696         /* ULI M5461 */
2697         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2698         /* NVIDIA MCP */
2699         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2700           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2701           .class_mask = 0xffffff,
2702           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2703         /* Teradici */
2704         { PCI_DEVICE(0x6549, 0x1200),
2705           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2706         { PCI_DEVICE(0x6549, 0x2200),
2707           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2708         /* Creative X-Fi (CA0110-IBG) */
2709         /* CTHDA chips */
2710         { PCI_DEVICE(0x1102, 0x0010),
2711           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2712         { PCI_DEVICE(0x1102, 0x0012),
2713           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2714 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2715         /* the following entry conflicts with snd-ctxfi driver,
2716          * as ctxfi driver mutates from HD-audio to native mode with
2717          * a special command sequence.
2718          */
2719         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2720           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2721           .class_mask = 0xffffff,
2722           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2723           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2724 #else
2725         /* this entry seems still valid -- i.e. without emu20kx chip */
2726         { PCI_DEVICE(0x1102, 0x0009),
2727           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2728           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2729 #endif
2730         /* CM8888 */
2731         { PCI_DEVICE(0x13f6, 0x5011),
2732           .driver_data = AZX_DRIVER_CMEDIA |
2733           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2734         /* Vortex86MX */
2735         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2736         /* VMware HDAudio */
2737         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2738         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2739         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2740           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2741           .class_mask = 0xffffff,
2742           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2743         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2744           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2745           .class_mask = 0xffffff,
2746           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2747         { 0, }
2748 };
2749 MODULE_DEVICE_TABLE(pci, azx_ids);
2750
2751 /* pci_driver definition */
2752 static struct pci_driver azx_driver = {
2753         .name = KBUILD_MODNAME,
2754         .id_table = azx_ids,
2755         .probe = azx_probe,
2756         .remove = azx_remove,
2757         .shutdown = azx_shutdown,
2758         .driver = {
2759                 .pm = AZX_PM_OPS,
2760         },
2761 };
2762
2763 module_pci_driver(azx_driver);