sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81         POS_FIX_FIFO,
  82 };
  83
  84 /* Defines for ATI HD Audio support in SB450 south bridge */
  85 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  86 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  87
  88 /* Defines for Nvidia HDA support */
  89 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  90 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  91 #define NVIDIA_HDA_ISTRM_COH          0x4d
  92 #define NVIDIA_HDA_OSTRM_COH          0x4c
  93 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  94
  95 /* Defines for Intel SCH HDA snoop control */
  96 #define INTEL_HDA_CGCTL  0x48
  97 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  98 #define INTEL_SCH_HDA_DEVC      0x78
  99 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 100
 101 /* Define IN stream 0 FIFO size offset in VIA controller */
 102 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 103 /* Define VIA HD Audio Device ID*/
 104 #define VIA_HDAC_DEVICE_ID              0x3288
 105
 106 /* max number of SDs */
 107 /* ICH, ATI and VIA have 4 playback and 4 capture */
 108 #define ICH6_NUM_CAPTURE        4
 109 #define ICH6_NUM_PLAYBACK       4
 110
 111 /* ULI has 6 playback and 5 capture */
 112 #define ULI_NUM_CAPTURE         5
 113 #define ULI_NUM_PLAYBACK        6
 114
 115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 116 #define ATIHDMI_NUM_CAPTURE     0
 117 #define ATIHDMI_NUM_PLAYBACK    8
 118
 119 /* TERA has 4 playback and 3 capture */
 120 #define TERA_NUM_CAPTURE        3
 121 #define TERA_NUM_PLAYBACK       4
 122
 123
 124 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 125 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 126 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 127 static char *model[SNDRV_CARDS];
 128 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 131 static int probe_only[SNDRV_CARDS];
 132 static int jackpoll_ms[SNDRV_CARDS];
 133 static int single_cmd = -1;
 134 static int enable_msi = -1;
 135 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 136 static char *patch[SNDRV_CARDS];
 137 #endif
 138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 139 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 140                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 141 #endif
 142
 143 module_param_array(index, int, NULL, 0444);
 144 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 145 module_param_array(id, charp, NULL, 0444);
 146 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 147 module_param_array(enable, bool, NULL, 0444);
 148 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 149 module_param_array(model, charp, NULL, 0444);
 150 MODULE_PARM_DESC(model, "Use the given board model.");
 151 module_param_array(position_fix, int, NULL, 0444);
 152 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 153                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 154 module_param_array(bdl_pos_adj, int, NULL, 0644);
 155 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 156 module_param_array(probe_mask, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 158 module_param_array(probe_only, int, NULL, 0444);
 159 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 160 module_param_array(jackpoll_ms, int, NULL, 0444);
 161 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 162 module_param(single_cmd, bint, 0444);
 163 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 164                  "(for debugging only).");
 165 module_param(enable_msi, bint, 0444);
 166 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 167 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 168 module_param_array(patch, charp, NULL, 0444);
 169 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 170 #endif
 171 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 172 module_param_array(beep_mode, bool, NULL, 0444);
 173 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 174                             "(0=off, 1=on) (default=1).");
 175 #endif
 176
 177 #ifdef CONFIG_PM
 178 static int param_set_xint(const char *val, const struct kernel_param *kp);
 179 static const struct kernel_param_ops param_ops_xint = {
 180         .set = param_set_xint,
 181         .get = param_get_int,
 182 };
 183 #define param_check_xint param_check_int
 184
 185 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 186 module_param(power_save, xint, 0644);
 187 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 188                  "(in second, 0 = disable).");
 189
 190 static bool pm_blacklist = true;
 191 module_param(pm_blacklist, bool, 0644);
 192 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 193
 194 /* reset the HD-audio controller in power save mode.
 195  * this may give more power-saving, but will take longer time to
 196  * wake up.
 197  */
 198 static bool power_save_controller = 1;
 199 module_param(power_save_controller, bool, 0644);
 200 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 201 #else
 202 #define power_save      0
 203 #endif /* CONFIG_PM */
 204
 205 static int align_buffer_size = -1;
 206 module_param(align_buffer_size, bint, 0644);
 207 MODULE_PARM_DESC(align_buffer_size,
 208                 "Force buffer and period sizes to be multiple of 128 bytes.");
 209
 210 #ifdef CONFIG_X86
 211 static int hda_snoop = -1;
 212 module_param_named(snoop, hda_snoop, bint, 0444);
 213 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 214 #else
 215 #define hda_snoop               true
 216 #endif
 217
 218
 219 MODULE_LICENSE("GPL");
 220 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 221                          "{Intel, ICH6M},"
 222                          "{Intel, ICH7},"
 223                          "{Intel, ESB2},"
 224                          "{Intel, ICH8},"
 225                          "{Intel, ICH9},"
 226                          "{Intel, ICH10},"
 227                          "{Intel, PCH},"
 228                          "{Intel, CPT},"
 229                          "{Intel, PPT},"
 230                          "{Intel, LPT},"
 231                          "{Intel, LPT_LP},"
 232                          "{Intel, WPT_LP},"
 233                          "{Intel, SPT},"
 234                          "{Intel, SPT_LP},"
 235                          "{Intel, HPT},"
 236                          "{Intel, PBG},"
 237                          "{Intel, SCH},"
 238                          "{ATI, SB450},"
 239                          "{ATI, SB600},"
 240                          "{ATI, RS600},"
 241                          "{ATI, RS690},"
 242                          "{ATI, RS780},"
 243                          "{ATI, R600},"
 244                          "{ATI, RV630},"
 245                          "{ATI, RV610},"
 246                          "{ATI, RV670},"
 247                          "{ATI, RV635},"
 248                          "{ATI, RV620},"
 249                          "{ATI, RV770},"
 250                          "{VIA, VT8251},"
 251                          "{VIA, VT8237A},"
 252                          "{SiS, SIS966},"
 253                          "{ULI, M5461}}");
 254 MODULE_DESCRIPTION("Intel HDA driver");
 255
 256 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 257 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 258 #define SUPPORT_VGA_SWITCHEROO
 259 #endif
 260 #endif
 261
 262
 263 /*
 264  */
 265
 266 /* driver types */
 267 enum {
 268         AZX_DRIVER_ICH,
 269         AZX_DRIVER_PCH,
 270         AZX_DRIVER_SCH,
 271         AZX_DRIVER_SKL,
 272         AZX_DRIVER_HDMI,
 273         AZX_DRIVER_ATI,
 274         AZX_DRIVER_ATIHDMI,
 275         AZX_DRIVER_ATIHDMI_NS,
 276         AZX_DRIVER_VIA,
 277         AZX_DRIVER_SIS,
 278         AZX_DRIVER_ULI,
 279         AZX_DRIVER_NVIDIA,
 280         AZX_DRIVER_TERA,
 281         AZX_DRIVER_CTX,
 282         AZX_DRIVER_CTHDA,
 283         AZX_DRIVER_CMEDIA,
 284         AZX_DRIVER_GENERIC,
 285         AZX_NUM_DRIVERS, /* keep this as last entry */
 286 };
 287
 288 #define azx_get_snoop_type(chip) \
 289         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 290 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 291
 292 /* quirks for old Intel chipsets */
 293 #define AZX_DCAPS_INTEL_ICH \
 294         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 295
 296 /* quirks for Intel PCH */
 297 #define AZX_DCAPS_INTEL_PCH_BASE \
 298         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 302 #define AZX_DCAPS_INTEL_PCH_NOPM \
 303         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 304
 305 /* PCH for HSW/BDW; with runtime PM */
 306 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 307 #define AZX_DCAPS_INTEL_PCH \
 308         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 309
 310 /* HSW HDMI */
 311 #define AZX_DCAPS_INTEL_HASWELL \
 312         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 313          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 314          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 315
 316 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 317 #define AZX_DCAPS_INTEL_BROADWELL \
 318         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 320          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 321
 322 #define AZX_DCAPS_INTEL_BAYTRAIL \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 324          AZX_DCAPS_I915_POWERWELL)
 325
 326 #define AZX_DCAPS_INTEL_BRASWELL \
 327         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 328          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 329
 330 #define AZX_DCAPS_INTEL_SKYLAKE \
 331         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 332          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 333          AZX_DCAPS_I915_POWERWELL)
 334
 335 #define AZX_DCAPS_INTEL_BROXTON \
 336         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 337          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 338          AZX_DCAPS_I915_POWERWELL)
 339
 340 /* quirks for ATI SB / AMD Hudson */
 341 #define AZX_DCAPS_PRESET_ATI_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI))
 344
 345 /* quirks for ATI/AMD HDMI */
 346 #define AZX_DCAPS_PRESET_ATI_HDMI \
 347         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 348          AZX_DCAPS_NO_MSI64)
 349
 350 /* quirks for ATI HDMI with snoop off */
 351 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 352         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 353
 354 /* quirks for AMD SB */
 355 #define AZX_DCAPS_PRESET_AMD_SB \
 356         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 357          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 358
 359 /* quirks for Nvidia */
 360 #define AZX_DCAPS_PRESET_NVIDIA \
 361         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 362          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 363
 364 #define AZX_DCAPS_PRESET_CTHDA \
 365         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 366          AZX_DCAPS_NO_64BIT |\
 367          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 368
 369 /*
 370  * vga_switcheroo support
 371  */
 372 #ifdef SUPPORT_VGA_SWITCHEROO
 373 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 374 #else
 375 #define use_vga_switcheroo(chip)        0
 376 #endif
 377
 378 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 379                                         ((pci)->device == 0x0c0c) || \
 380                                         ((pci)->device == 0x0d0c) || \
 381                                         ((pci)->device == 0x160c))
 382
 383 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 384 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 385 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 386
 387 static char *driver_short_names[] = {
 388         [AZX_DRIVER_ICH] = "HDA Intel",
 389         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 390         [AZX_DRIVER_SCH] = "HDA Intel MID",
 391         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 392         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 393         [AZX_DRIVER_ATI] = "HDA ATI SB",
 394         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 395         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 396         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 397         [AZX_DRIVER_SIS] = "HDA SIS966",
 398         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 399         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 400         [AZX_DRIVER_TERA] = "HDA Teradici",
 401         [AZX_DRIVER_CTX] = "HDA Creative",
 402         [AZX_DRIVER_CTHDA] = "HDA Creative",
 403         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 404         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 405 };
 406
 407 #ifdef CONFIG_X86
 408 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 409 {
 410         int pages;
 411
 412         if (azx_snoop(chip))
 413                 return;
 414         if (!dmab || !dmab->area || !dmab->bytes)
 415                 return;
 416
 417 #ifdef CONFIG_SND_DMA_SGBUF
 418         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 419                 struct snd_sg_buf *sgbuf = dmab->private_data;
 420                 if (!chip->uc_buffer)
 421                         return; /* deal with only CORB/RIRB buffers */
 422                 if (on)
 423                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 424                 else
 425                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 426                 return;
 427         }
 428 #endif
 429
 430         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 431         if (on)
 432                 set_memory_wc((unsigned long)dmab->area, pages);
 433         else
 434                 set_memory_wb((unsigned long)dmab->area, pages);
 435 }
 436
 437 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 438                                  bool on)
 439 {
 440         __mark_pages_wc(chip, buf, on);
 441 }
 442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 443                                    struct snd_pcm_substream *substream, bool on)
 444 {
 445         if (azx_dev->wc_marked != on) {
 446                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 447                 azx_dev->wc_marked = on;
 448         }
 449 }
 450 #else
 451 /* NOP for other archs */
 452 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 453                                  bool on)
 454 {
 455 }
 456 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 457                                    struct snd_pcm_substream *substream, bool on)
 458 {
 459 }
 460 #endif
 461
 462 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 463
 464 /*
 465  * initialize the PCI registers
 466  */
 467 /* update bits in a PCI register byte */
 468 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 469                             unsigned char mask, unsigned char val)
 470 {
 471         unsigned char data;
 472
 473         pci_read_config_byte(pci, reg, &data);
 474         data &= ~mask;
 475         data |= (val & mask);
 476         pci_write_config_byte(pci, reg, data);
 477 }
 478
 479 static void azx_init_pci(struct azx *chip)
 480 {
 481         int snoop_type = azx_get_snoop_type(chip);
 482
 483         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 484          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 485          * Ensuring these bits are 0 clears playback static on some HD Audio
 486          * codecs.
 487          * The PCI register TCSEL is defined in the Intel manuals.
 488          */
 489         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 490                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 491                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 492         }
 493
 494         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 495          * we need to enable snoop.
 496          */
 497         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 498                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 499                         azx_snoop(chip));
 500                 update_pci_byte(chip->pci,
 501                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 502                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 503         }
 504
 505         /* For NVIDIA HDA, enable snoop */
 506         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 507                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 508                         azx_snoop(chip));
 509                 update_pci_byte(chip->pci,
 510                                 NVIDIA_HDA_TRANSREG_ADDR,
 511                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 512                 update_pci_byte(chip->pci,
 513                                 NVIDIA_HDA_ISTRM_COH,
 514                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 515                 update_pci_byte(chip->pci,
 516                                 NVIDIA_HDA_OSTRM_COH,
 517                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 518         }
 519
 520         /* Enable SCH/PCH snoop if needed */
 521         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 522                 unsigned short snoop;
 523                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 524                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 525                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 526                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 527                         if (!azx_snoop(chip))
 528                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 529                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 530                         pci_read_config_word(chip->pci,
 531                                 INTEL_SCH_HDA_DEVC, &snoop);
 532                 }
 533                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 534                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 535                         "Disabled" : "Enabled");
 536         }
 537 }
 538
 539 /*
 540  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 541  * and makes an audio stream sensitive to system latencies when
 542  * 24/32 bits are playing.
 543  * Adjusting threshold of DMA fifo to force the DMA request
 544  * sooner to improve latency tolerance at the expense of power.
 545  */
 546 static void bxt_reduce_dma_latency(struct azx *chip)
 547 {
 548         u32 val;
 549
 550         val = azx_readl(chip, VS_EM4L);
 551         val &= (0x3 << 20);
 552         azx_writel(chip, VS_EM4L, val);
 553 }
 554
 555 /*
 556  * ML_LCAP bits:
 557  *  bit 0: 6 MHz Supported
 558  *  bit 1: 12 MHz Supported
 559  *  bit 2: 24 MHz Supported
 560  *  bit 3: 48 MHz Supported
 561  *  bit 4: 96 MHz Supported
 562  *  bit 5: 192 MHz Supported
 563  */
 564 static int intel_get_lctl_scf(struct azx *chip)
 565 {
 566         struct hdac_bus *bus = azx_bus(chip);
 567         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 568         u32 val, t;
 569         int i;
 570
 571         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 572
 573         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 574                 t = preferred_bits[i];
 575                 if (val & (1 << t))
 576                         return t;
 577         }
 578
 579         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 580         return 0;
 581 }
 582
 583 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 584 {
 585         struct hdac_bus *bus = azx_bus(chip);
 586         u32 val;
 587         int timeout;
 588
 589         /*
 590          * the codecs are sharing the first link setting by default
 591          * If other links are enabled for stream, they need similar fix
 592          */
 593         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 594         val &= ~AZX_MLCTL_SPA;
 595         val |= state << AZX_MLCTL_SPA_SHIFT;
 596         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 597         /* wait for CPA */
 598         timeout = 50;
 599         while (timeout) {
 600                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 601                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 602                         return 0;
 603                 timeout--;
 604                 udelay(10);
 605         }
 606
 607         return -1;
 608 }
 609
 610 static void intel_init_lctl(struct azx *chip)
 611 {
 612         struct hdac_bus *bus = azx_bus(chip);
 613         u32 val;
 614         int ret;
 615
 616         /* 0. check lctl register value is correct or not */
 617         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 618         /* if SCF is already set, let's use it */
 619         if ((val & ML_LCTL_SCF_MASK) != 0)
 620                 return;
 621
 622         /*
 623          * Before operating on SPA, CPA must match SPA.
 624          * Any deviation may result in undefined behavior.
 625          */
 626         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 627                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 628                 return;
 629
 630         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 631         ret = intel_ml_lctl_set_power(chip, 0);
 632         udelay(100);
 633         if (ret)
 634                 goto set_spa;
 635
 636         /* 2. update SCF to select a properly audio clock*/
 637         val &= ~ML_LCTL_SCF_MASK;
 638         val |= intel_get_lctl_scf(chip);
 639         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 640
 641 set_spa:
 642         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 643         intel_ml_lctl_set_power(chip, 1);
 644         udelay(100);
 645 }
 646
 647 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 648 {
 649         struct hdac_bus *bus = azx_bus(chip);
 650         struct pci_dev *pci = chip->pci;
 651         u32 val;
 652
 653         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 654                 snd_hdac_set_codec_wakeup(bus, true);
 655         if (chip->driver_type == AZX_DRIVER_SKL) {
 656                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 657                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 658                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 659         }
 660         azx_init_chip(chip, full_reset);
 661         if (chip->driver_type == AZX_DRIVER_SKL) {
 662                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 663                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 664                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 665         }
 666         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 667                 snd_hdac_set_codec_wakeup(bus, false);
 668
 669         /* reduce dma latency to avoid noise */
 670         if (IS_BXT(pci))
 671                 bxt_reduce_dma_latency(chip);
 672
 673         if (bus->mlcap != NULL)
 674                 intel_init_lctl(chip);
 675 }
 676
 677 /* calculate runtime delay from LPIB */
 678 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 679                                    unsigned int pos)
 680 {
 681         struct snd_pcm_substream *substream = azx_dev->core.substream;
 682         int stream = substream->stream;
 683         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 684         int delay;
 685
 686         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 687                 delay = pos - lpib_pos;
 688         else
 689                 delay = lpib_pos - pos;
 690         if (delay < 0) {
 691                 if (delay >= azx_dev->core.delay_negative_threshold)
 692                         delay = 0;
 693                 else
 694                         delay += azx_dev->core.bufsize;
 695         }
 696
 697         if (delay >= azx_dev->core.period_bytes) {
 698                 dev_info(chip->card->dev,
 699                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 700                          delay, azx_dev->core.period_bytes);
 701                 delay = 0;
 702                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 703                 chip->get_delay[stream] = NULL;
 704         }
 705
 706         return bytes_to_frames(substream->runtime, delay);
 707 }
 708
 709 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 710
 711 /* called from IRQ */
 712 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 713 {
 714         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 715         int ok;
 716
 717         ok = azx_position_ok(chip, azx_dev);
 718         if (ok == 1) {
 719                 azx_dev->irq_pending = 0;
 720                 return ok;
 721         } else if (ok == 0) {
 722                 /* bogus IRQ, process it later */
 723                 azx_dev->irq_pending = 1;
 724                 schedule_work(&hda->irq_pending_work);
 725         }
 726         return 0;
 727 }
 728
 729 /* Enable/disable i915 display power for the link */
 730 static int azx_intel_link_power(struct azx *chip, bool enable)
 731 {
 732         struct hdac_bus *bus = azx_bus(chip);
 733
 734         return snd_hdac_display_power(bus, enable);
 735 }
 736
 737 /*
 738  * Check whether the current DMA position is acceptable for updating
 739  * periods.  Returns non-zero if it's OK.
 740  *
 741  * Many HD-audio controllers appear pretty inaccurate about
 742  * the update-IRQ timing.  The IRQ is issued before actually the
 743  * data is processed.  So, we need to process it afterwords in a
 744  * workqueue.
 745  *
 746  * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
 747  */
 748 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 749 {
 750         struct snd_pcm_substream *substream = azx_dev->core.substream;
 751         struct snd_pcm_runtime *runtime = substream->runtime;
 752         int stream = substream->stream;
 753         u32 wallclk;
 754         unsigned int pos;
 755         snd_pcm_uframes_t hwptr, target;
 756
 757         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 758         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 759                 return -1;      /* bogus (too early) interrupt */
 760
 761         if (chip->get_position[stream])
 762                 pos = chip->get_position[stream](chip, azx_dev);
 763         else { /* use the position buffer as default */
 764                 pos = azx_get_pos_posbuf(chip, azx_dev);
 765                 if (!pos || pos == (u32)-1) {
 766                         dev_info(chip->card->dev,
 767                                  "Invalid position buffer, using LPIB read method instead.\n");
 768                         chip->get_position[stream] = azx_get_pos_lpib;
 769                         if (chip->get_position[0] == azx_get_pos_lpib &&
 770                             chip->get_position[1] == azx_get_pos_lpib)
 771                                 azx_bus(chip)->use_posbuf = false;
 772                         pos = azx_get_pos_lpib(chip, azx_dev);
 773                         chip->get_delay[stream] = NULL;
 774                 } else {
 775                         chip->get_position[stream] = azx_get_pos_posbuf;
 776                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 777                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 778                 }
 779         }
 780
 781         if (pos >= azx_dev->core.bufsize)
 782                 pos = 0;
 783
 784         if (WARN_ONCE(!azx_dev->core.period_bytes,
 785                       "hda-intel: zero azx_dev->period_bytes"))
 786                 return -1; /* this shouldn't happen! */
 787         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 788             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 789                 /* NG - it's below the first next period boundary */
 790                 return chip->bdl_pos_adj ? 0 : -1;
 791         azx_dev->core.start_wallclk += wallclk;
 792
 793         if (azx_dev->core.no_period_wakeup)
 794                 return 1; /* OK, no need to check period boundary */
 795
 796         if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
 797                 return 1; /* OK, already in hwptr updating process */
 798
 799         /* check whether the period gets really elapsed */
 800         pos = bytes_to_frames(runtime, pos);
 801         hwptr = runtime->hw_ptr_base + pos;
 802         if (hwptr < runtime->status->hw_ptr)
 803                 hwptr += runtime->buffer_size;
 804         target = runtime->hw_ptr_interrupt + runtime->period_size;
 805         if (hwptr < target) {
 806                 /* too early wakeup, process it later */
 807                 return chip->bdl_pos_adj ? 0 : -1;
 808         }
 809
 810         return 1; /* OK, it's fine */
 811 }
 812
 813 /*
 814  * The work for pending PCM period updates.
 815  */
 816 static void azx_irq_pending_work(struct work_struct *work)
 817 {
 818         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 819         struct azx *chip = &hda->chip;
 820         struct hdac_bus *bus = azx_bus(chip);
 821         struct hdac_stream *s;
 822         int pending, ok;
 823
 824         if (!hda->irq_pending_warned) {
 825                 dev_info(chip->card->dev,
 826                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 827                          chip->card->number);
 828                 hda->irq_pending_warned = 1;
 829         }
 830
 831         for (;;) {
 832                 pending = 0;
 833                 spin_lock_irq(&bus->reg_lock);
 834                 list_for_each_entry(s, &bus->stream_list, list) {
 835                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 836                         if (!azx_dev->irq_pending ||
 837                             !s->substream ||
 838                             !s->running)
 839                                 continue;
 840                         ok = azx_position_ok(chip, azx_dev);
 841                         if (ok > 0) {
 842                                 azx_dev->irq_pending = 0;
 843                                 spin_unlock(&bus->reg_lock);
 844                                 snd_pcm_period_elapsed(s->substream);
 845                                 spin_lock(&bus->reg_lock);
 846                         } else if (ok < 0) {
 847                                 pending = 0;    /* too early */
 848                         } else
 849                                 pending++;
 850                 }
 851                 spin_unlock_irq(&bus->reg_lock);
 852                 if (!pending)
 853                         return;
 854                 msleep(1);
 855         }
 856 }
 857
 858 /* clear irq_pending flags and assure no on-going workq */
 859 static void azx_clear_irq_pending(struct azx *chip)
 860 {
 861         struct hdac_bus *bus = azx_bus(chip);
 862         struct hdac_stream *s;
 863
 864         spin_lock_irq(&bus->reg_lock);
 865         list_for_each_entry(s, &bus->stream_list, list) {
 866                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 867                 azx_dev->irq_pending = 0;
 868         }
 869         spin_unlock_irq(&bus->reg_lock);
 870 }
 871
 872 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 873 {
 874         struct hdac_bus *bus = azx_bus(chip);
 875
 876         if (request_irq(chip->pci->irq, azx_interrupt,
 877                         chip->msi ? 0 : IRQF_SHARED,
 878                         chip->card->irq_descr, chip)) {
 879                 dev_err(chip->card->dev,
 880                         "unable to grab IRQ %d, disabling device\n",
 881                         chip->pci->irq);
 882                 if (do_disconnect)
 883                         snd_card_disconnect(chip->card);
 884                 return -1;
 885         }
 886         bus->irq = chip->pci->irq;
 887         pci_intx(chip->pci, !chip->msi);
 888         return 0;
 889 }
 890
 891 /* get the current DMA position with correction on VIA chips */
 892 static unsigned int azx_via_get_position(struct azx *chip,
 893                                          struct azx_dev *azx_dev)
 894 {
 895         unsigned int link_pos, mini_pos, bound_pos;
 896         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 897         unsigned int fifo_size;
 898
 899         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 900         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 901                 /* Playback, no problem using link position */
 902                 return link_pos;
 903         }
 904
 905         /* Capture */
 906         /* For new chipset,
 907          * use mod to get the DMA position just like old chipset
 908          */
 909         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 910         mod_dma_pos %= azx_dev->core.period_bytes;
 911
 912         /* azx_dev->fifo_size can't get FIFO size of in stream.
 913          * Get from base address + offset.
 914          */
 915         fifo_size = readw(azx_bus(chip)->remap_addr +
 916                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 917
 918         if (azx_dev->insufficient) {
 919                 /* Link position never gather than FIFO size */
 920                 if (link_pos <= fifo_size)
 921                         return 0;
 922
 923                 azx_dev->insufficient = 0;
 924         }
 925
 926         if (link_pos <= fifo_size)
 927                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 928         else
 929                 mini_pos = link_pos - fifo_size;
 930
 931         /* Find nearest previous boudary */
 932         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 933         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 934         if (mod_link_pos >= fifo_size)
 935                 bound_pos = link_pos - mod_link_pos;
 936         else if (mod_dma_pos >= mod_mini_pos)
 937                 bound_pos = mini_pos - mod_mini_pos;
 938         else {
 939                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 940                 if (bound_pos >= azx_dev->core.bufsize)
 941                         bound_pos = 0;
 942         }
 943
 944         /* Calculate real DMA position we want */
 945         return bound_pos + mod_dma_pos;
 946 }
 947
 948 #define AMD_FIFO_SIZE   32
 949
 950 /* get the current DMA position with FIFO size correction */
 951 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 952 {
 953         struct snd_pcm_substream *substream = azx_dev->core.substream;
 954         struct snd_pcm_runtime *runtime = substream->runtime;
 955         unsigned int pos, delay;
 956
 957         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 958         if (!runtime)
 959                 return pos;
 960
 961         runtime->delay = AMD_FIFO_SIZE;
 962         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 963         if (azx_dev->insufficient) {
 964                 if (pos < delay) {
 965                         delay = pos;
 966                         runtime->delay = bytes_to_frames(runtime, pos);
 967                 } else {
 968                         azx_dev->insufficient = 0;
 969                 }
 970         }
 971
 972         /* correct the DMA position for capture stream */
 973         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 974                 if (pos < delay)
 975                         pos += azx_dev->core.bufsize;
 976                 pos -= delay;
 977         }
 978
 979         return pos;
 980 }
 981
 982 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 983                                    unsigned int pos)
 984 {
 985         struct snd_pcm_substream *substream = azx_dev->core.substream;
 986
 987         /* just read back the calculated value in the above */
 988         return substream->runtime->delay;
 989 }
 990
 991 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 992                                          struct azx_dev *azx_dev)
 993 {
 994         return _snd_hdac_chip_readl(azx_bus(chip),
 995                                     AZX_REG_VS_SDXDPIB_XBASE +
 996                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 997                                      azx_dev->core.index));
 998 }
 999
1000 /* get the current DMA position with correction on SKL+ chips */
1001 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
1002 {
1003         /* DPIB register gives a more accurate position for playback */
1004         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1005                 return azx_skl_get_dpib_pos(chip, azx_dev);
1006
1007         /* read of DPIB fetches the actual posbuf */
1008         azx_skl_get_dpib_pos(chip, azx_dev);
1009         return azx_get_pos_posbuf(chip, azx_dev);
1010 }
1011
1012 #ifdef CONFIG_PM
1013 static DEFINE_MUTEX(card_list_lock);
1014 static LIST_HEAD(card_list);
1015
1016 static void azx_add_card_list(struct azx *chip)
1017 {
1018         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1019         mutex_lock(&card_list_lock);
1020         list_add(&hda->list, &card_list);
1021         mutex_unlock(&card_list_lock);
1022 }
1023
1024 static void azx_del_card_list(struct azx *chip)
1025 {
1026         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1027         mutex_lock(&card_list_lock);
1028         list_del_init(&hda->list);
1029         mutex_unlock(&card_list_lock);
1030 }
1031
1032 /* trigger power-save check at writing parameter */
1033 static int param_set_xint(const char *val, const struct kernel_param *kp)
1034 {
1035         struct hda_intel *hda;
1036         struct azx *chip;
1037         int prev = power_save;
1038         int ret = param_set_int(val, kp);
1039
1040         if (ret || prev == power_save)
1041                 return ret;
1042
1043         mutex_lock(&card_list_lock);
1044         list_for_each_entry(hda, &card_list, list) {
1045                 chip = &hda->chip;
1046                 if (!hda->probe_continued || chip->disabled)
1047                         continue;
1048                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1049         }
1050         mutex_unlock(&card_list_lock);
1051         return 0;
1052 }
1053 #else
1054 #define azx_add_card_list(chip) /* NOP */
1055 #define azx_del_card_list(chip) /* NOP */
1056 #endif /* CONFIG_PM */
1057
1058 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
1059 /*
1060  * power management
1061  */
1062 static int azx_suspend(struct device *dev)
1063 {
1064         struct snd_card *card = dev_get_drvdata(dev);
1065         struct azx *chip;
1066         struct hda_intel *hda;
1067         struct hdac_bus *bus;
1068
1069         if (!card)
1070                 return 0;
1071
1072         chip = card->private_data;
1073         hda = container_of(chip, struct hda_intel, chip);
1074         if (chip->disabled || hda->init_failed || !chip->running)
1075                 return 0;
1076
1077         bus = azx_bus(chip);
1078         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1079         azx_clear_irq_pending(chip);
1080         azx_stop_chip(chip);
1081         azx_enter_link_reset(chip);
1082         if (bus->irq >= 0) {
1083                 free_irq(bus->irq, chip);
1084                 bus->irq = -1;
1085         }
1086
1087         if (chip->msi)
1088                 pci_disable_msi(chip->pci);
1089         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1090                 && hda->need_i915_power)
1091                 snd_hdac_display_power(bus, false);
1092
1093         trace_azx_suspend(chip);
1094         return 0;
1095 }
1096
1097 static int azx_resume(struct device *dev)
1098 {
1099         struct pci_dev *pci = to_pci_dev(dev);
1100         struct snd_card *card = dev_get_drvdata(dev);
1101         struct azx *chip;
1102         struct hda_intel *hda;
1103         struct hdac_bus *bus;
1104
1105         if (!card)
1106                 return 0;
1107
1108         chip = card->private_data;
1109         hda = container_of(chip, struct hda_intel, chip);
1110         bus = azx_bus(chip);
1111         if (chip->disabled || hda->init_failed || !chip->running)
1112                 return 0;
1113
1114         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1115                 snd_hdac_display_power(bus, true);
1116                 if (hda->need_i915_power)
1117                         snd_hdac_i915_set_bclk(bus);
1118         }
1119
1120         if (chip->msi)
1121                 if (pci_enable_msi(pci) < 0)
1122                         chip->msi = 0;
1123         if (azx_acquire_irq(chip, 1) < 0)
1124                 return -EIO;
1125         azx_init_pci(chip);
1126
1127         hda_intel_init_chip(chip, true);
1128
1129         /* power down again for link-controlled chips */
1130         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1131             !hda->need_i915_power)
1132                 snd_hdac_display_power(bus, false);
1133
1134         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1135
1136         trace_azx_resume(chip);
1137         return 0;
1138 }
1139 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1140
1141 #ifdef CONFIG_PM_SLEEP
1142 /* put codec down to D3 at hibernation for Intel SKL+;
1143  * otherwise BIOS may still access the codec and screw up the driver
1144  */
1145 static int azx_freeze_noirq(struct device *dev)
1146 {
1147         struct snd_card *card = dev_get_drvdata(dev);
1148         struct azx *chip = card->private_data;
1149         struct pci_dev *pci = to_pci_dev(dev);
1150
1151         if (chip->driver_type == AZX_DRIVER_SKL)
1152                 pci_set_power_state(pci, PCI_D3hot);
1153
1154         return 0;
1155 }
1156
1157 static int azx_thaw_noirq(struct device *dev)
1158 {
1159         struct snd_card *card = dev_get_drvdata(dev);
1160         struct azx *chip = card->private_data;
1161         struct pci_dev *pci = to_pci_dev(dev);
1162
1163         if (chip->driver_type == AZX_DRIVER_SKL)
1164                 pci_set_power_state(pci, PCI_D0);
1165
1166         return 0;
1167 }
1168 #endif /* CONFIG_PM_SLEEP */
1169
1170 #ifdef CONFIG_PM
1171 static int azx_runtime_suspend(struct device *dev)
1172 {
1173         struct snd_card *card = dev_get_drvdata(dev);
1174         struct azx *chip;
1175         struct hda_intel *hda;
1176
1177         if (!card)
1178                 return 0;
1179
1180         chip = card->private_data;
1181         hda = container_of(chip, struct hda_intel, chip);
1182         if (chip->disabled || hda->init_failed)
1183                 return 0;
1184
1185         if (!azx_has_pm_runtime(chip))
1186                 return 0;
1187
1188         /* enable controller wake up event */
1189         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1190                   STATESTS_INT_MASK);
1191
1192         azx_stop_chip(chip);
1193         azx_enter_link_reset(chip);
1194         azx_clear_irq_pending(chip);
1195         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1196                 && hda->need_i915_power)
1197                 snd_hdac_display_power(azx_bus(chip), false);
1198
1199         trace_azx_runtime_suspend(chip);
1200         return 0;
1201 }
1202
1203 static int azx_runtime_resume(struct device *dev)
1204 {
1205         struct snd_card *card = dev_get_drvdata(dev);
1206         struct azx *chip;
1207         struct hda_intel *hda;
1208         struct hdac_bus *bus;
1209         struct hda_codec *codec;
1210         int status;
1211
1212         if (!card)
1213                 return 0;
1214
1215         chip = card->private_data;
1216         hda = container_of(chip, struct hda_intel, chip);
1217         bus = azx_bus(chip);
1218         if (chip->disabled || hda->init_failed)
1219                 return 0;
1220
1221         if (!azx_has_pm_runtime(chip))
1222                 return 0;
1223
1224         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1225                 snd_hdac_display_power(bus, true);
1226                 if (hda->need_i915_power)
1227                         snd_hdac_i915_set_bclk(bus);
1228         }
1229
1230         /* Read STATESTS before controller reset */
1231         status = azx_readw(chip, STATESTS);
1232
1233         azx_init_pci(chip);
1234         hda_intel_init_chip(chip, true);
1235
1236         if (status) {
1237                 list_for_each_codec(codec, &chip->bus)
1238                         if (status & (1 << codec->addr))
1239                                 schedule_delayed_work(&codec->jackpoll_work,
1240                                                       codec->jackpoll_interval);
1241         }
1242
1243         /* disable controller Wake Up event*/
1244         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1245                         ~STATESTS_INT_MASK);
1246
1247         /* power down again for link-controlled chips */
1248         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1249             !hda->need_i915_power)
1250                 snd_hdac_display_power(bus, false);
1251
1252         trace_azx_runtime_resume(chip);
1253         return 0;
1254 }
1255
1256 static int azx_runtime_idle(struct device *dev)
1257 {
1258         struct snd_card *card = dev_get_drvdata(dev);
1259         struct azx *chip;
1260         struct hda_intel *hda;
1261
1262         if (!card)
1263                 return 0;
1264
1265         chip = card->private_data;
1266         hda = container_of(chip, struct hda_intel, chip);
1267         if (chip->disabled || hda->init_failed)
1268                 return 0;
1269
1270         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1271             azx_bus(chip)->codec_powered || !chip->running)
1272                 return -EBUSY;
1273
1274         return 0;
1275 }
1276
1277 static const struct dev_pm_ops azx_pm = {
1278         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1279 #ifdef CONFIG_PM_SLEEP
1280         .freeze_noirq = azx_freeze_noirq,
1281         .thaw_noirq = azx_thaw_noirq,
1282 #endif
1283         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1284 };
1285
1286 #define AZX_PM_OPS      &azx_pm
1287 #else
1288 #define AZX_PM_OPS      NULL
1289 #endif /* CONFIG_PM */
1290
1291
1292 static int azx_probe_continue(struct azx *chip);
1293
1294 #ifdef SUPPORT_VGA_SWITCHEROO
1295 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1296
1297 static void azx_vs_set_state(struct pci_dev *pci,
1298                              enum vga_switcheroo_state state)
1299 {
1300         struct snd_card *card = pci_get_drvdata(pci);
1301         struct azx *chip = card->private_data;
1302         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1303         struct hda_codec *codec;
1304         bool disabled;
1305
1306         wait_for_completion(&hda->probe_wait);
1307         if (hda->init_failed)
1308                 return;
1309
1310         disabled = (state == VGA_SWITCHEROO_OFF);
1311         if (chip->disabled == disabled)
1312                 return;
1313
1314         if (!hda->probe_continued) {
1315                 chip->disabled = disabled;
1316                 if (!disabled) {
1317                         dev_info(chip->card->dev,
1318                                  "Start delayed initialization\n");
1319                         if (azx_probe_continue(chip) < 0) {
1320                                 dev_err(chip->card->dev, "initialization error\n");
1321                                 hda->init_failed = true;
1322                         }
1323                 }
1324         } else {
1325                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1326                          disabled ? "Disabling" : "Enabling");
1327                 if (disabled) {
1328                         list_for_each_codec(codec, &chip->bus) {
1329                                 pm_runtime_suspend(hda_codec_dev(codec));
1330                                 pm_runtime_disable(hda_codec_dev(codec));
1331                         }
1332                         pm_runtime_suspend(card->dev);
1333                         pm_runtime_disable(card->dev);
1334                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1335                          * however we have no ACPI handle, so pci/acpi can't put us there,
1336                          * put ourselves there */
1337                         pci->current_state = PCI_D3cold;
1338                         chip->disabled = true;
1339                         if (snd_hda_lock_devices(&chip->bus))
1340                                 dev_warn(chip->card->dev,
1341                                          "Cannot lock devices!\n");
1342                 } else {
1343                         snd_hda_unlock_devices(&chip->bus);
1344                         chip->disabled = false;
1345                         pm_runtime_enable(card->dev);
1346                         list_for_each_codec(codec, &chip->bus) {
1347                                 pm_runtime_enable(hda_codec_dev(codec));
1348                                 pm_runtime_resume(hda_codec_dev(codec));
1349                         }
1350                 }
1351         }
1352 }
1353
1354 static bool azx_vs_can_switch(struct pci_dev *pci)
1355 {
1356         struct snd_card *card = pci_get_drvdata(pci);
1357         struct azx *chip = card->private_data;
1358         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1359
1360         wait_for_completion(&hda->probe_wait);
1361         if (hda->init_failed)
1362                 return false;
1363         if (chip->disabled || !hda->probe_continued)
1364                 return true;
1365         if (snd_hda_lock_devices(&chip->bus))
1366                 return false;
1367         snd_hda_unlock_devices(&chip->bus);
1368         return true;
1369 }
1370
1371 static void init_vga_switcheroo(struct azx *chip)
1372 {
1373         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1374         struct pci_dev *p = get_bound_vga(chip->pci);
1375         if (p) {
1376                 dev_info(chip->card->dev,
1377                          "Handle vga_switcheroo audio client\n");
1378                 hda->use_vga_switcheroo = 1;
1379                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1380                 pci_dev_put(p);
1381         }
1382 }
1383
1384 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1385         .set_gpu_state = azx_vs_set_state,
1386         .can_switch = azx_vs_can_switch,
1387 };
1388
1389 static int register_vga_switcheroo(struct azx *chip)
1390 {
1391         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1392         int err;
1393
1394         if (!hda->use_vga_switcheroo)
1395                 return 0;
1396         /* FIXME: currently only handling DIS controller
1397          * is there any machine with two switchable HDMI audio controllers?
1398          */
1399         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1400                                                    VGA_SWITCHEROO_DIS);
1401         if (err < 0)
1402                 return err;
1403         hda->vga_switcheroo_registered = 1;
1404
1405         return 0;
1406 }
1407 #else
1408 #define init_vga_switcheroo(chip)               /* NOP */
1409 #define register_vga_switcheroo(chip)           0
1410 #define check_hdmi_disabled(pci)        false
1411 #endif /* SUPPORT_VGA_SWITCHER */
1412
1413 /*
1414  * destructor
1415  */
1416 static int azx_free(struct azx *chip)
1417 {
1418         struct pci_dev *pci = chip->pci;
1419         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1420         struct hdac_bus *bus = azx_bus(chip);
1421
1422         if (azx_has_pm_runtime(chip) && chip->running)
1423                 pm_runtime_get_noresume(&pci->dev);
1424
1425         azx_del_card_list(chip);
1426
1427         hda->init_failed = 1; /* to be sure */
1428         complete_all(&hda->probe_wait);
1429
1430         if (use_vga_switcheroo(hda)) {
1431                 if (chip->disabled && hda->probe_continued)
1432                         snd_hda_unlock_devices(&chip->bus);
1433                 if (hda->vga_switcheroo_registered)
1434                         vga_switcheroo_unregister_client(chip->pci);
1435         }
1436
1437         if (bus->chip_init) {
1438                 azx_clear_irq_pending(chip);
1439                 azx_stop_all_streams(chip);
1440                 azx_stop_chip(chip);
1441         }
1442
1443         if (bus->irq >= 0)
1444                 free_irq(bus->irq, (void*)chip);
1445         if (chip->msi)
1446                 pci_disable_msi(chip->pci);
1447         iounmap(bus->remap_addr);
1448
1449         azx_free_stream_pages(chip);
1450         azx_free_streams(chip);
1451         snd_hdac_bus_exit(bus);
1452
1453         if (chip->region_requested)
1454                 pci_release_regions(chip->pci);
1455
1456         pci_disable_device(chip->pci);
1457 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1458         release_firmware(chip->fw);
1459 #endif
1460
1461         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1462                 if (hda->need_i915_power)
1463                         snd_hdac_display_power(bus, false);
1464         }
1465         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1466                 snd_hdac_i915_exit(bus);
1467         kfree(hda);
1468
1469         return 0;
1470 }
1471
1472 static int azx_dev_disconnect(struct snd_device *device)
1473 {
1474         struct azx *chip = device->device_data;
1475         struct hdac_bus *bus = azx_bus(chip);
1476
1477         chip->bus.shutdown = 1;
1478         cancel_work_sync(&bus->unsol_work);
1479
1480         return 0;
1481 }
1482
1483 static int azx_dev_free(struct snd_device *device)
1484 {
1485         return azx_free(device->device_data);
1486 }
1487
1488 #ifdef SUPPORT_VGA_SWITCHEROO
1489 /*
1490  * Check of disabled HDMI controller by vga_switcheroo
1491  */
1492 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1493 {
1494         struct pci_dev *p;
1495
1496         /* check only discrete GPU */
1497         switch (pci->vendor) {
1498         case PCI_VENDOR_ID_ATI:
1499         case PCI_VENDOR_ID_AMD:
1500         case PCI_VENDOR_ID_NVIDIA:
1501                 if (pci->devfn == 1) {
1502                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1503                                                         pci->bus->number, 0);
1504                         if (p) {
1505                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1506                                         return p;
1507                                 pci_dev_put(p);
1508                         }
1509                 }
1510                 break;
1511         }
1512         return NULL;
1513 }
1514
1515 static bool check_hdmi_disabled(struct pci_dev *pci)
1516 {
1517         bool vga_inactive = false;
1518         struct pci_dev *p = get_bound_vga(pci);
1519
1520         if (p) {
1521                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1522                         vga_inactive = true;
1523                 pci_dev_put(p);
1524         }
1525         return vga_inactive;
1526 }
1527 #endif /* SUPPORT_VGA_SWITCHEROO */
1528
1529 /*
1530  * white/black-listing for position_fix
1531  */
1532 static struct snd_pci_quirk position_fix_list[] = {
1533         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1534         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1535         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1536         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1537         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1538         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1539         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1540         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1541         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1542         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1543         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1544         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1545         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1546         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1547         {}
1548 };
1549
1550 static int check_position_fix(struct azx *chip, int fix)
1551 {
1552         const struct snd_pci_quirk *q;
1553
1554         switch (fix) {
1555         case POS_FIX_AUTO:
1556         case POS_FIX_LPIB:
1557         case POS_FIX_POSBUF:
1558         case POS_FIX_VIACOMBO:
1559         case POS_FIX_COMBO:
1560         case POS_FIX_SKL:
1561         case POS_FIX_FIFO:
1562                 return fix;
1563         }
1564
1565         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1566         if (q) {
1567                 dev_info(chip->card->dev,
1568                          "position_fix set to %d for device %04x:%04x\n",
1569                          q->value, q->subvendor, q->subdevice);
1570                 return q->value;
1571         }
1572
1573         /* Check VIA/ATI HD Audio Controller exist */
1574         if (chip->driver_type == AZX_DRIVER_VIA) {
1575                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1576                 return POS_FIX_VIACOMBO;
1577         }
1578         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1579                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1580                 return POS_FIX_FIFO;
1581         }
1582         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1583                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1584                 return POS_FIX_LPIB;
1585         }
1586         if (chip->driver_type == AZX_DRIVER_SKL) {
1587                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1588                 return POS_FIX_SKL;
1589         }
1590         return POS_FIX_AUTO;
1591 }
1592
1593 static void assign_position_fix(struct azx *chip, int fix)
1594 {
1595         static azx_get_pos_callback_t callbacks[] = {
1596                 [POS_FIX_AUTO] = NULL,
1597                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1598                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1599                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1600                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1601                 [POS_FIX_SKL] = azx_get_pos_skl,
1602                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1603         };
1604
1605         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1606
1607         /* combo mode uses LPIB only for playback */
1608         if (fix == POS_FIX_COMBO)
1609                 chip->get_position[1] = NULL;
1610
1611         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1612             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1613                 chip->get_delay[0] = chip->get_delay[1] =
1614                         azx_get_delay_from_lpib;
1615         }
1616
1617         if (fix == POS_FIX_FIFO)
1618                 chip->get_delay[0] = chip->get_delay[1] =
1619                         azx_get_delay_from_fifo;
1620 }
1621
1622 /*
1623  * black-lists for probe_mask
1624  */
1625 static struct snd_pci_quirk probe_mask_list[] = {
1626         /* Thinkpad often breaks the controller communication when accessing
1627          * to the non-working (or non-existing) modem codec slot.
1628          */
1629         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1630         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1631         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1632         /* broken BIOS */
1633         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1634         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1635         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1636         /* forced codec slots */
1637         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1638         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1639         /* WinFast VP200 H (Teradici) user reported broken communication */
1640         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1641         {}
1642 };
1643
1644 #define AZX_FORCE_CODEC_MASK    0x100
1645
1646 static void check_probe_mask(struct azx *chip, int dev)
1647 {
1648         const struct snd_pci_quirk *q;
1649
1650         chip->codec_probe_mask = probe_mask[dev];
1651         if (chip->codec_probe_mask == -1) {
1652                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1653                 if (q) {
1654                         dev_info(chip->card->dev,
1655                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1656                                  q->value, q->subvendor, q->subdevice);
1657                         chip->codec_probe_mask = q->value;
1658                 }
1659         }
1660
1661         /* check forced option */
1662         if (chip->codec_probe_mask != -1 &&
1663             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1664                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1665                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1666                          (int)azx_bus(chip)->codec_mask);
1667         }
1668 }
1669
1670 /*
1671  * white/black-list for enable_msi
1672  */
1673 static struct snd_pci_quirk msi_black_list[] = {
1674         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1675         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1676         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1677         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1678         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1679         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1680         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1681         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1682         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1683         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1684         {}
1685 };
1686
1687 static void check_msi(struct azx *chip)
1688 {
1689         const struct snd_pci_quirk *q;
1690
1691         if (enable_msi >= 0) {
1692                 chip->msi = !!enable_msi;
1693                 return;
1694         }
1695         chip->msi = 1;  /* enable MSI as default */
1696         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1697         if (q) {
1698                 dev_info(chip->card->dev,
1699                          "msi for device %04x:%04x set to %d\n",
1700                          q->subvendor, q->subdevice, q->value);
1701                 chip->msi = q->value;
1702                 return;
1703         }
1704
1705         /* NVidia chipsets seem to cause troubles with MSI */
1706         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1707                 dev_info(chip->card->dev, "Disabling MSI\n");
1708                 chip->msi = 0;
1709         }
1710 }
1711
1712 /* check the snoop mode availability */
1713 static void azx_check_snoop_available(struct azx *chip)
1714 {
1715         int snoop = hda_snoop;
1716
1717         if (snoop >= 0) {
1718                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1719                          snoop ? "snoop" : "non-snoop");
1720                 chip->snoop = snoop;
1721                 chip->uc_buffer = !snoop;
1722                 return;
1723         }
1724
1725         snoop = true;
1726         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1727             chip->driver_type == AZX_DRIVER_VIA) {
1728                 /* force to non-snoop mode for a new VIA controller
1729                  * when BIOS is set
1730                  */
1731                 u8 val;
1732                 pci_read_config_byte(chip->pci, 0x42, &val);
1733                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1734                                       chip->pci->revision == 0x20))
1735                         snoop = false;
1736         }
1737
1738         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1739                 snoop = false;
1740
1741         chip->snoop = snoop;
1742         if (!snoop) {
1743                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1744                 /* C-Media requires non-cached pages only for CORB/RIRB */
1745                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1746                         chip->uc_buffer = true;
1747         }
1748 }
1749
1750 static void azx_probe_work(struct work_struct *work)
1751 {
1752         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1753         azx_probe_continue(&hda->chip);
1754 }
1755
1756 static int default_bdl_pos_adj(struct azx *chip)
1757 {
1758         /* some exceptions: Atoms seem problematic with value 1 */
1759         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1760                 switch (chip->pci->device) {
1761                 case 0x0f04: /* Baytrail */
1762                 case 0x2284: /* Braswell */
1763                         return 32;
1764                 }
1765         }
1766
1767         switch (chip->driver_type) {
1768         case AZX_DRIVER_ICH:
1769         case AZX_DRIVER_PCH:
1770                 return 1;
1771         default:
1772                 return 32;
1773         }
1774 }
1775
1776 /*
1777  * constructor
1778  */
1779 static const struct hdac_io_ops pci_hda_io_ops;
1780 static const struct hda_controller_ops pci_hda_ops;
1781
1782 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1783                       int dev, unsigned int driver_caps,
1784                       struct azx **rchip)
1785 {
1786         static struct snd_device_ops ops = {
1787                 .dev_disconnect = azx_dev_disconnect,
1788                 .dev_free = azx_dev_free,
1789         };
1790         struct hda_intel *hda;
1791         struct azx *chip;
1792         int err;
1793
1794         *rchip = NULL;
1795
1796         err = pci_enable_device(pci);
1797         if (err < 0)
1798                 return err;
1799
1800         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1801         if (!hda) {
1802                 pci_disable_device(pci);
1803                 return -ENOMEM;
1804         }
1805
1806         chip = &hda->chip;
1807         mutex_init(&chip->open_mutex);
1808         chip->card = card;
1809         chip->pci = pci;
1810         chip->ops = &pci_hda_ops;
1811         chip->driver_caps = driver_caps;
1812         chip->driver_type = driver_caps & 0xff;
1813         check_msi(chip);
1814         chip->dev_index = dev;
1815         chip->jackpoll_ms = jackpoll_ms;
1816         INIT_LIST_HEAD(&chip->pcm_list);
1817         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1818         INIT_LIST_HEAD(&hda->list);
1819         init_vga_switcheroo(chip);
1820         init_completion(&hda->probe_wait);
1821
1822         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1823
1824         check_probe_mask(chip, dev);
1825
1826         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1827                 chip->fallback_to_single_cmd = 1;
1828         else /* explicitly set to single_cmd or not */
1829                 chip->single_cmd = single_cmd;
1830
1831         azx_check_snoop_available(chip);
1832
1833         if (bdl_pos_adj[dev] < 0)
1834                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1835         else
1836                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1837
1838         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1839         if (IS_CFL(pci) || IS_CNL(pci))
1840                 chip->polling_mode = 1;
1841
1842         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1843         if (err < 0) {
1844                 kfree(hda);
1845                 pci_disable_device(pci);
1846                 return err;
1847         }
1848
1849         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1850                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1851                 chip->bus.needs_damn_long_delay = 1;
1852         }
1853
1854         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1855         if (err < 0) {
1856                 dev_err(card->dev, "Error creating device [card]!\n");
1857                 azx_free(chip);
1858                 return err;
1859         }
1860
1861         /* continue probing in work context as may trigger request module */
1862         INIT_WORK(&hda->probe_work, azx_probe_work);
1863
1864         *rchip = chip;
1865
1866         return 0;
1867 }
1868
1869 static int azx_first_init(struct azx *chip)
1870 {
1871         int dev = chip->dev_index;
1872         struct pci_dev *pci = chip->pci;
1873         struct snd_card *card = chip->card;
1874         struct hdac_bus *bus = azx_bus(chip);
1875         int err;
1876         unsigned short gcap;
1877         unsigned int dma_bits = 64;
1878
1879 #if BITS_PER_LONG != 64
1880         /* Fix up base address on ULI M5461 */
1881         if (chip->driver_type == AZX_DRIVER_ULI) {
1882                 u16 tmp3;
1883                 pci_read_config_word(pci, 0x40, &tmp3);
1884                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1885                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1886         }
1887 #endif
1888
1889         err = pci_request_regions(pci, "ICH HD audio");
1890         if (err < 0)
1891                 return err;
1892         chip->region_requested = 1;
1893
1894         bus->addr = pci_resource_start(pci, 0);
1895         bus->remap_addr = pci_ioremap_bar(pci, 0);
1896         if (bus->remap_addr == NULL) {
1897                 dev_err(card->dev, "ioremap error\n");
1898                 return -ENXIO;
1899         }
1900
1901         if (chip->driver_type == AZX_DRIVER_SKL)
1902                 snd_hdac_bus_parse_capabilities(bus);
1903
1904         /*
1905          * Some Intel CPUs has always running timer (ART) feature and
1906          * controller may have Global time sync reporting capability, so
1907          * check both of these before declaring synchronized time reporting
1908          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1909          */
1910         chip->gts_present = false;
1911
1912 #ifdef CONFIG_X86
1913         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1914                 chip->gts_present = true;
1915 #endif
1916
1917         if (chip->msi) {
1918                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1919                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1920                         pci->no_64bit_msi = true;
1921                 }
1922                 if (pci_enable_msi(pci) < 0)
1923                         chip->msi = 0;
1924         }
1925
1926         pci_set_master(pci);
1927         synchronize_irq(bus->irq);
1928
1929         gcap = azx_readw(chip, GCAP);
1930         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1931
1932         /* AMD devices support 40 or 48bit DMA, take the safe one */
1933         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1934                 dma_bits = 40;
1935
1936         /* disable SB600 64bit support for safety */
1937         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1938                 struct pci_dev *p_smbus;
1939                 dma_bits = 40;
1940                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1941                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1942                                          NULL);
1943                 if (p_smbus) {
1944                         if (p_smbus->revision < 0x30)
1945                                 gcap &= ~AZX_GCAP_64OK;
1946                         pci_dev_put(p_smbus);
1947                 }
1948         }
1949
1950         /* NVidia hardware normally only supports up to 40 bits of DMA */
1951         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1952                 dma_bits = 40;
1953
1954         /* disable 64bit DMA address on some devices */
1955         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1956                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1957                 gcap &= ~AZX_GCAP_64OK;
1958         }
1959
1960         /* disable buffer size rounding to 128-byte multiples if supported */
1961         if (align_buffer_size >= 0)
1962                 chip->align_buffer_size = !!align_buffer_size;
1963         else {
1964                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1965                         chip->align_buffer_size = 0;
1966                 else
1967                         chip->align_buffer_size = 1;
1968         }
1969
1970         /* allow 64bit DMA address if supported by H/W */
1971         if (!(gcap & AZX_GCAP_64OK))
1972                 dma_bits = 32;
1973         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1974                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1975         } else {
1976                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1977                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1978         }
1979
1980         /* read number of streams from GCAP register instead of using
1981          * hardcoded value
1982          */
1983         chip->capture_streams = (gcap >> 8) & 0x0f;
1984         chip->playback_streams = (gcap >> 12) & 0x0f;
1985         if (!chip->playback_streams && !chip->capture_streams) {
1986                 /* gcap didn't give any info, switching to old method */
1987
1988                 switch (chip->driver_type) {
1989                 case AZX_DRIVER_ULI:
1990                         chip->playback_streams = ULI_NUM_PLAYBACK;
1991                         chip->capture_streams = ULI_NUM_CAPTURE;
1992                         break;
1993                 case AZX_DRIVER_ATIHDMI:
1994                 case AZX_DRIVER_ATIHDMI_NS:
1995                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1996                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1997                         break;
1998                 case AZX_DRIVER_GENERIC:
1999                 default:
2000                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2001                         chip->capture_streams = ICH6_NUM_CAPTURE;
2002                         break;
2003                 }
2004         }
2005         chip->capture_index_offset = 0;
2006         chip->playback_index_offset = chip->capture_streams;
2007         chip->num_streams = chip->playback_streams + chip->capture_streams;
2008
2009         /* sanity check for the SDxCTL.STRM field overflow */
2010         if (chip->num_streams > 15 &&
2011             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2012                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2013                          "forcing separate stream tags", chip->num_streams);
2014                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2015         }
2016
2017         /* initialize streams */
2018         err = azx_init_streams(chip);
2019         if (err < 0)
2020                 return err;
2021
2022         err = azx_alloc_stream_pages(chip);
2023         if (err < 0)
2024                 return err;
2025
2026         /* initialize chip */
2027         azx_init_pci(chip);
2028
2029         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2030                 snd_hdac_i915_set_bclk(bus);
2031
2032         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2033
2034         /* codec detection */
2035         if (!azx_bus(chip)->codec_mask) {
2036                 dev_err(card->dev, "no codecs found!\n");
2037                 return -ENODEV;
2038         }
2039
2040         if (azx_acquire_irq(chip, 0) < 0)
2041                 return -EBUSY;
2042
2043         strcpy(card->driver, "HDA-Intel");
2044         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2045                 sizeof(card->shortname));
2046         snprintf(card->longname, sizeof(card->longname),
2047                  "%s at 0x%lx irq %i",
2048                  card->shortname, bus->addr, bus->irq);
2049
2050         return 0;
2051 }
2052
2053 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2054 /* callback from request_firmware_nowait() */
2055 static void azx_firmware_cb(const struct firmware *fw, void *context)
2056 {
2057         struct snd_card *card = context;
2058         struct azx *chip = card->private_data;
2059
2060         if (fw)
2061                 chip->fw = fw;
2062         else
2063                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2064         if (!chip->disabled) {
2065                 /* continue probing */
2066                 azx_probe_continue(chip);
2067         }
2068 }
2069 #endif
2070
2071 /*
2072  * HDA controller ops.
2073  */
2074
2075 /* PCI register access. */
2076 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2077 {
2078         writel(value, addr);
2079 }
2080
2081 static u32 pci_azx_readl(u32 __iomem *addr)
2082 {
2083         return readl(addr);
2084 }
2085
2086 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2087 {
2088         writew(value, addr);
2089 }
2090
2091 static u16 pci_azx_readw(u16 __iomem *addr)
2092 {
2093         return readw(addr);
2094 }
2095
2096 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2097 {
2098         writeb(value, addr);
2099 }
2100
2101 static u8 pci_azx_readb(u8 __iomem *addr)
2102 {
2103         return readb(addr);
2104 }
2105
2106 static int disable_msi_reset_irq(struct azx *chip)
2107 {
2108         struct hdac_bus *bus = azx_bus(chip);
2109         int err;
2110
2111         free_irq(bus->irq, chip);
2112         bus->irq = -1;
2113         pci_disable_msi(chip->pci);
2114         chip->msi = 0;
2115         err = azx_acquire_irq(chip, 1);
2116         if (err < 0)
2117                 return err;
2118
2119         return 0;
2120 }
2121
2122 /* DMA page allocation helpers.  */
2123 static int dma_alloc_pages(struct hdac_bus *bus,
2124                            int type,
2125                            size_t size,
2126                            struct snd_dma_buffer *buf)
2127 {
2128         struct azx *chip = bus_to_azx(bus);
2129         int err;
2130
2131         err = snd_dma_alloc_pages(type,
2132                                   bus->dev,
2133                                   size, buf);
2134         if (err < 0)
2135                 return err;
2136         mark_pages_wc(chip, buf, true);
2137         return 0;
2138 }
2139
2140 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2141 {
2142         struct azx *chip = bus_to_azx(bus);
2143
2144         mark_pages_wc(chip, buf, false);
2145         snd_dma_free_pages(buf);
2146 }
2147
2148 static int substream_alloc_pages(struct azx *chip,
2149                                  struct snd_pcm_substream *substream,
2150                                  size_t size)
2151 {
2152         struct azx_dev *azx_dev = get_azx_dev(substream);
2153         int ret;
2154
2155         mark_runtime_wc(chip, azx_dev, substream, false);
2156         ret = snd_pcm_lib_malloc_pages(substream, size);
2157         if (ret < 0)
2158                 return ret;
2159         mark_runtime_wc(chip, azx_dev, substream, true);
2160         return 0;
2161 }
2162
2163 static int substream_free_pages(struct azx *chip,
2164                                 struct snd_pcm_substream *substream)
2165 {
2166         struct azx_dev *azx_dev = get_azx_dev(substream);
2167         mark_runtime_wc(chip, azx_dev, substream, false);
2168         return snd_pcm_lib_free_pages(substream);
2169 }
2170
2171 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2172                              struct vm_area_struct *area)
2173 {
2174 #ifdef CONFIG_X86
2175         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2176         struct azx *chip = apcm->chip;
2177         if (chip->uc_buffer)
2178                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2179 #endif
2180 }
2181
2182 static const struct hdac_io_ops pci_hda_io_ops = {
2183         .reg_writel = pci_azx_writel,
2184         .reg_readl = pci_azx_readl,
2185         .reg_writew = pci_azx_writew,
2186         .reg_readw = pci_azx_readw,
2187         .reg_writeb = pci_azx_writeb,
2188         .reg_readb = pci_azx_readb,
2189         .dma_alloc_pages = dma_alloc_pages,
2190         .dma_free_pages = dma_free_pages,
2191 };
2192
2193 /* Blacklist for skipping the whole probe:
2194  * some HD-audio PCI entries are exposed without any codecs, and such devices
2195  * should be ignored from the beginning.
2196  */
2197 static const struct pci_device_id driver_blacklist[] = {
2198         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2199         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2200         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2201         {}
2202 };
2203
2204 static const struct hda_controller_ops pci_hda_ops = {
2205         .disable_msi_reset_irq = disable_msi_reset_irq,
2206         .substream_alloc_pages = substream_alloc_pages,
2207         .substream_free_pages = substream_free_pages,
2208         .pcm_mmap_prepare = pcm_mmap_prepare,
2209         .position_check = azx_position_check,
2210         .link_power = azx_intel_link_power,
2211 };
2212
2213 static int azx_probe(struct pci_dev *pci,
2214                      const struct pci_device_id *pci_id)
2215 {
2216         static int dev;
2217         struct snd_card *card;
2218         struct hda_intel *hda;
2219         struct azx *chip;
2220         bool schedule_probe;
2221         int err;
2222
2223         if (pci_match_id(driver_blacklist, pci)) {
2224                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2225                 return -ENODEV;
2226         }
2227
2228         if (dev >= SNDRV_CARDS)
2229                 return -ENODEV;
2230         if (!enable[dev]) {
2231                 dev++;
2232                 return -ENOENT;
2233         }
2234
2235         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2236                            0, &card);
2237         if (err < 0) {
2238                 dev_err(&pci->dev, "Error creating card!\n");
2239                 return err;
2240         }
2241
2242         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2243         if (err < 0)
2244                 goto out_free;
2245         card->private_data = chip;
2246         hda = container_of(chip, struct hda_intel, chip);
2247
2248         pci_set_drvdata(pci, card);
2249
2250         err = register_vga_switcheroo(chip);
2251         if (err < 0) {
2252                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2253                 goto out_free;
2254         }
2255
2256         if (check_hdmi_disabled(pci)) {
2257                 dev_info(card->dev, "VGA controller is disabled\n");
2258                 dev_info(card->dev, "Delaying initialization\n");
2259                 chip->disabled = true;
2260         }
2261
2262         schedule_probe = !chip->disabled;
2263
2264 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2265         if (patch[dev] && *patch[dev]) {
2266                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2267                          patch[dev]);
2268                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2269                                               &pci->dev, GFP_KERNEL, card,
2270                                               azx_firmware_cb);
2271                 if (err < 0)
2272                         goto out_free;
2273                 schedule_probe = false; /* continued in azx_firmware_cb() */
2274         }
2275 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2276
2277 #ifndef CONFIG_SND_HDA_I915
2278         if (CONTROLLER_IN_GPU(pci))
2279                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2280 #endif
2281
2282         if (schedule_probe)
2283                 schedule_work(&hda->probe_work);
2284
2285         dev++;
2286         if (chip->disabled)
2287                 complete_all(&hda->probe_wait);
2288         return 0;
2289
2290 out_free:
2291         snd_card_free(card);
2292         return err;
2293 }
2294
2295 #ifdef CONFIG_PM
2296 /* On some boards setting power_save to a non 0 value leads to clicking /
2297  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2298  * figure out how to avoid these sounds, but that is not always feasible.
2299  * So we keep a list of devices where we disable powersaving as its known
2300  * to causes problems on these devices.
2301  */
2302 static struct snd_pci_quirk power_save_blacklist[] = {
2303         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2304         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2305         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2306         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2307         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2308         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2309         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2310         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2311         {}
2312 };
2313 #endif /* CONFIG_PM */
2314
2315 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2316 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2317         [AZX_DRIVER_NVIDIA] = 8,
2318         [AZX_DRIVER_TERA] = 1,
2319 };
2320
2321 static int azx_probe_continue(struct azx *chip)
2322 {
2323         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2324         struct hdac_bus *bus = azx_bus(chip);
2325         struct pci_dev *pci = chip->pci;
2326         struct hda_codec *codec;
2327         int dev = chip->dev_index;
2328         int val;
2329         int err;
2330
2331         to_hda_bus(bus)->bus_probing = 1;
2332         hda->probe_continued = 1;
2333
2334         /* bind with i915 if needed */
2335         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2336                 err = snd_hdac_i915_init(bus);
2337                 if (err < 0) {
2338                         /* if the controller is bound only with HDMI/DP
2339                          * (for HSW and BDW), we need to abort the probe;
2340                          * for other chips, still continue probing as other
2341                          * codecs can be on the same link.
2342                          */
2343                         if (CONTROLLER_IN_GPU(pci)) {
2344                                 dev_err(chip->card->dev,
2345                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2346                                 goto out_free;
2347                         } else {
2348                                 /* don't bother any longer */
2349                                 chip->driver_caps &=
2350                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2351                         }
2352                 }
2353         }
2354
2355         /* Request display power well for the HDA controller or codec. For
2356          * Haswell/Broadwell, both the display HDA controller and codec need
2357          * this power. For other platforms, like Baytrail/Braswell, only the
2358          * display codec needs the power and it can be released after probe.
2359          */
2360         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2361                 /* HSW/BDW controllers need this power */
2362                 if (CONTROLLER_IN_GPU(pci))
2363                         hda->need_i915_power = 1;
2364
2365                 err = snd_hdac_display_power(bus, true);
2366                 if (err < 0) {
2367                         dev_err(chip->card->dev,
2368                                 "Cannot turn on display power on i915\n");
2369                         goto i915_power_fail;
2370                 }
2371         }
2372
2373         err = azx_first_init(chip);
2374         if (err < 0)
2375                 goto out_free;
2376
2377 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2378         chip->beep_mode = beep_mode[dev];
2379 #endif
2380
2381         /* create codec instances */
2382         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2383         if (err < 0)
2384                 goto out_free;
2385
2386 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2387         if (chip->fw) {
2388                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2389                                          chip->fw->data);
2390                 if (err < 0)
2391                         goto out_free;
2392 #ifndef CONFIG_PM
2393                 release_firmware(chip->fw); /* no longer needed */
2394                 chip->fw = NULL;
2395 #endif
2396         }
2397 #endif
2398         if ((probe_only[dev] & 1) == 0) {
2399                 err = azx_codec_configure(chip);
2400                 if (err < 0)
2401                         goto out_free;
2402         }
2403
2404         err = snd_card_register(chip->card);
2405         if (err < 0)
2406                 goto out_free;
2407
2408         chip->running = 1;
2409         azx_add_card_list(chip);
2410
2411         /*
2412          * The discrete GPU cannot power down unless the HDA controller runtime
2413          * suspends, so activate runtime PM on codecs even if power_save == 0.
2414          */
2415         if (use_vga_switcheroo(hda))
2416                 list_for_each_codec(codec, &chip->bus)
2417                         codec->auto_runtime_pm = 1;
2418
2419         val = power_save;
2420 #ifdef CONFIG_PM
2421         if (pm_blacklist) {
2422                 const struct snd_pci_quirk *q;
2423
2424                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2425                 if (q && val) {
2426                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2427                                  q->subvendor, q->subdevice);
2428                         val = 0;
2429                 }
2430         }
2431 #endif /* CONFIG_PM */
2432         snd_hda_set_power_save(&chip->bus, val * 1000);
2433         if (azx_has_pm_runtime(chip))
2434                 pm_runtime_put_autosuspend(&pci->dev);
2435
2436 out_free:
2437         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2438                 && !hda->need_i915_power)
2439                 snd_hdac_display_power(bus, false);
2440
2441 i915_power_fail:
2442         if (err < 0)
2443                 hda->init_failed = 1;
2444         complete_all(&hda->probe_wait);
2445         to_hda_bus(bus)->bus_probing = 0;
2446         return err;
2447 }
2448
2449 static void azx_remove(struct pci_dev *pci)
2450 {
2451         struct snd_card *card = pci_get_drvdata(pci);
2452         struct azx *chip;
2453         struct hda_intel *hda;
2454
2455         if (card) {
2456                 /* cancel the pending probing work */
2457                 chip = card->private_data;
2458                 hda = container_of(chip, struct hda_intel, chip);
2459                 /* FIXME: below is an ugly workaround.
2460                  * Both device_release_driver() and driver_probe_device()
2461                  * take *both* the device's and its parent's lock before
2462                  * calling the remove() and probe() callbacks.  The codec
2463                  * probe takes the locks of both the codec itself and its
2464                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2465                  * the PCI controller is unbound, it takes its lock, too
2466                  * ==> ouch, a deadlock!
2467                  * As a workaround, we unlock temporarily here the controller
2468                  * device during cancel_work_sync() call.
2469                  */
2470                 device_unlock(&pci->dev);
2471                 cancel_work_sync(&hda->probe_work);
2472                 device_lock(&pci->dev);
2473
2474                 snd_card_free(card);
2475         }
2476 }
2477
2478 static void azx_shutdown(struct pci_dev *pci)
2479 {
2480         struct snd_card *card = pci_get_drvdata(pci);
2481         struct azx *chip;
2482
2483         if (!card)
2484                 return;
2485         chip = card->private_data;
2486         if (chip && chip->running)
2487                 azx_stop_chip(chip);
2488 }
2489
2490 /* PCI IDs */
2491 static const struct pci_device_id azx_ids[] = {
2492         /* CPT */
2493         { PCI_DEVICE(0x8086, 0x1c20),
2494           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2495         /* PBG */
2496         { PCI_DEVICE(0x8086, 0x1d20),
2497           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2498         /* Panther Point */
2499         { PCI_DEVICE(0x8086, 0x1e20),
2500           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2501         /* Lynx Point */
2502         { PCI_DEVICE(0x8086, 0x8c20),
2503           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2504         /* 9 Series */
2505         { PCI_DEVICE(0x8086, 0x8ca0),
2506           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2507         /* Wellsburg */
2508         { PCI_DEVICE(0x8086, 0x8d20),
2509           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2510         { PCI_DEVICE(0x8086, 0x8d21),
2511           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2512         /* Lewisburg */
2513         { PCI_DEVICE(0x8086, 0xa1f0),
2514           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2515         { PCI_DEVICE(0x8086, 0xa270),
2516           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2517         /* Lynx Point-LP */
2518         { PCI_DEVICE(0x8086, 0x9c20),
2519           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2520         /* Lynx Point-LP */
2521         { PCI_DEVICE(0x8086, 0x9c21),
2522           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2523         /* Wildcat Point-LP */
2524         { PCI_DEVICE(0x8086, 0x9ca0),
2525           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2526         /* Sunrise Point */
2527         { PCI_DEVICE(0x8086, 0xa170),
2528           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2529         /* Sunrise Point-LP */
2530         { PCI_DEVICE(0x8086, 0x9d70),
2531           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2532         /* Kabylake */
2533         { PCI_DEVICE(0x8086, 0xa171),
2534           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2535         /* Kabylake-LP */
2536         { PCI_DEVICE(0x8086, 0x9d71),
2537           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2538         /* Kabylake-H */
2539         { PCI_DEVICE(0x8086, 0xa2f0),
2540           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2541         /* Coffelake */
2542         { PCI_DEVICE(0x8086, 0xa348),
2543           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2544         /* Cannonlake */
2545         { PCI_DEVICE(0x8086, 0x9dc8),
2546           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2547         /* Broxton-P(Apollolake) */
2548         { PCI_DEVICE(0x8086, 0x5a98),
2549           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2550         /* Broxton-T */
2551         { PCI_DEVICE(0x8086, 0x1a98),
2552           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2553         /* Gemini-Lake */
2554         { PCI_DEVICE(0x8086, 0x3198),
2555           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2556         /* Haswell */
2557         { PCI_DEVICE(0x8086, 0x0a0c),
2558           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2559         { PCI_DEVICE(0x8086, 0x0c0c),
2560           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2561         { PCI_DEVICE(0x8086, 0x0d0c),
2562           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2563         /* Broadwell */
2564         { PCI_DEVICE(0x8086, 0x160c),
2565           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2566         /* 5 Series/3400 */
2567         { PCI_DEVICE(0x8086, 0x3b56),
2568           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2569         /* Poulsbo */
2570         { PCI_DEVICE(0x8086, 0x811b),
2571           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2572         /* Oaktrail */
2573         { PCI_DEVICE(0x8086, 0x080a),
2574           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2575         /* BayTrail */
2576         { PCI_DEVICE(0x8086, 0x0f04),
2577           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2578         /* Braswell */
2579         { PCI_DEVICE(0x8086, 0x2284),
2580           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2581         /* ICH6 */
2582         { PCI_DEVICE(0x8086, 0x2668),
2583           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2584         /* ICH7 */
2585         { PCI_DEVICE(0x8086, 0x27d8),
2586           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2587         /* ESB2 */
2588         { PCI_DEVICE(0x8086, 0x269a),
2589           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2590         /* ICH8 */
2591         { PCI_DEVICE(0x8086, 0x284b),
2592           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2593         /* ICH9 */
2594         { PCI_DEVICE(0x8086, 0x293e),
2595           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2596         /* ICH9 */
2597         { PCI_DEVICE(0x8086, 0x293f),
2598           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2599         /* ICH10 */
2600         { PCI_DEVICE(0x8086, 0x3a3e),
2601           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2602         /* ICH10 */
2603         { PCI_DEVICE(0x8086, 0x3a6e),
2604           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2605         /* Generic Intel */
2606         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2607           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2608           .class_mask = 0xffffff,
2609           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2610         /* ATI SB 450/600/700/800/900 */
2611         { PCI_DEVICE(0x1002, 0x437b),
2612           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2613         { PCI_DEVICE(0x1002, 0x4383),
2614           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2615         /* AMD Hudson */
2616         { PCI_DEVICE(0x1022, 0x780d),
2617           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2618         /* AMD, X370 & co */
2619         { PCI_DEVICE(0x1022, 0x1457),
2620           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2621         /* AMD, X570 & co */
2622         { PCI_DEVICE(0x1022, 0x1487),
2623           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2624         /* AMD Stoney */
2625         { PCI_DEVICE(0x1022, 0x157a),
2626           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2627                          AZX_DCAPS_PM_RUNTIME },
2628         /* AMD Raven */
2629         { PCI_DEVICE(0x1022, 0x15e3),
2630           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2631         /* ATI HDMI */
2632         { PCI_DEVICE(0x1002, 0x0002),
2633           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2634         { PCI_DEVICE(0x1002, 0x1308),
2635           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2636         { PCI_DEVICE(0x1002, 0x157a),
2637           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2638         { PCI_DEVICE(0x1002, 0x15b3),
2639           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2640         { PCI_DEVICE(0x1002, 0x793b),
2641           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642         { PCI_DEVICE(0x1002, 0x7919),
2643           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644         { PCI_DEVICE(0x1002, 0x960f),
2645           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646         { PCI_DEVICE(0x1002, 0x970f),
2647           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648         { PCI_DEVICE(0x1002, 0x9840),
2649           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2650         { PCI_DEVICE(0x1002, 0xaa00),
2651           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652         { PCI_DEVICE(0x1002, 0xaa08),
2653           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2654         { PCI_DEVICE(0x1002, 0xaa10),
2655           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656         { PCI_DEVICE(0x1002, 0xaa18),
2657           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658         { PCI_DEVICE(0x1002, 0xaa20),
2659           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660         { PCI_DEVICE(0x1002, 0xaa28),
2661           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662         { PCI_DEVICE(0x1002, 0xaa30),
2663           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664         { PCI_DEVICE(0x1002, 0xaa38),
2665           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2666         { PCI_DEVICE(0x1002, 0xaa40),
2667           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2668         { PCI_DEVICE(0x1002, 0xaa48),
2669           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2670         { PCI_DEVICE(0x1002, 0xaa50),
2671           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2672         { PCI_DEVICE(0x1002, 0xaa58),
2673           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2674         { PCI_DEVICE(0x1002, 0xaa60),
2675           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2676         { PCI_DEVICE(0x1002, 0xaa68),
2677           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2678         { PCI_DEVICE(0x1002, 0xaa80),
2679           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2680         { PCI_DEVICE(0x1002, 0xaa88),
2681           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2682         { PCI_DEVICE(0x1002, 0xaa90),
2683           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2684         { PCI_DEVICE(0x1002, 0xaa98),
2685           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2686         { PCI_DEVICE(0x1002, 0x9902),
2687           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2688         { PCI_DEVICE(0x1002, 0xaaa0),
2689           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2690         { PCI_DEVICE(0x1002, 0xaaa8),
2691           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2692         { PCI_DEVICE(0x1002, 0xaab0),
2693           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2694         { PCI_DEVICE(0x1002, 0xaac0),
2695           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2696         { PCI_DEVICE(0x1002, 0xaac8),
2697           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2698         { PCI_DEVICE(0x1002, 0xaad8),
2699           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2700         { PCI_DEVICE(0x1002, 0xaae8),
2701           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2702         { PCI_DEVICE(0x1002, 0xaae0),
2703           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2704         { PCI_DEVICE(0x1002, 0xaaf0),
2705           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2706         /* VIA VT8251/VT8237A */
2707         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2708         /* VIA GFX VT7122/VX900 */
2709         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2710         /* VIA GFX VT6122/VX11 */
2711         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2712         /* SIS966 */
2713         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2714         /* ULI M5461 */
2715         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2716         /* NVIDIA MCP */
2717         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2718           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2719           .class_mask = 0xffffff,
2720           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2721         /* Teradici */
2722         { PCI_DEVICE(0x6549, 0x1200),
2723           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2724         { PCI_DEVICE(0x6549, 0x2200),
2725           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2726         /* Creative X-Fi (CA0110-IBG) */
2727         /* CTHDA chips */
2728         { PCI_DEVICE(0x1102, 0x0010),
2729           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2730         { PCI_DEVICE(0x1102, 0x0012),
2731           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2732 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2733         /* the following entry conflicts with snd-ctxfi driver,
2734          * as ctxfi driver mutates from HD-audio to native mode with
2735          * a special command sequence.
2736          */
2737         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2738           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2739           .class_mask = 0xffffff,
2740           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2741           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2742 #else
2743         /* this entry seems still valid -- i.e. without emu20kx chip */
2744         { PCI_DEVICE(0x1102, 0x0009),
2745           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2746           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2747 #endif
2748         /* CM8888 */
2749         { PCI_DEVICE(0x13f6, 0x5011),
2750           .driver_data = AZX_DRIVER_CMEDIA |
2751           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2752         /* Vortex86MX */
2753         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2754         /* VMware HDAudio */
2755         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2756         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2757         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2758           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2759           .class_mask = 0xffffff,
2760           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2761         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2762           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2763           .class_mask = 0xffffff,
2764           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2765         { 0, }
2766 };
2767 MODULE_DEVICE_TABLE(pci, azx_ids);
2768
2769 /* pci_driver definition */
2770 static struct pci_driver azx_driver = {
2771         .name = KBUILD_MODNAME,
2772         .id_table = azx_ids,
2773         .probe = azx_probe,
2774         .remove = azx_remove,
2775         .shutdown = azx_shutdown,
2776         .driver = {
2777                 .pm = AZX_PM_OPS,
2778         },
2779 };
2780
2781 module_pci_driver(azx_driver);