sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68         POS_FIX_FIFO,
  69 };
  70
  71 /* Defines for ATI HD Audio support in SB450 south bridge */
  72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  74
  75 /* Defines for Nvidia HDA support */
  76 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  77 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  78 #define NVIDIA_HDA_ISTRM_COH          0x4d
  79 #define NVIDIA_HDA_OSTRM_COH          0x4c
  80 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  81
  82 /* Defines for Intel SCH HDA snoop control */
  83 #define INTEL_HDA_CGCTL  0x48
  84 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  85 #define INTEL_SCH_HDA_DEVC      0x78
  86 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  87
  88 /* Define VIA HD Audio Device ID*/
  89 #define VIA_HDAC_DEVICE_ID              0x3288
  90
  91 /* max number of SDs */
  92 /* ICH, ATI and VIA have 4 playback and 4 capture */
  93 #define ICH6_NUM_CAPTURE        4
  94 #define ICH6_NUM_PLAYBACK       4
  95
  96 /* ULI has 6 playback and 5 capture */
  97 #define ULI_NUM_CAPTURE         5
  98 #define ULI_NUM_PLAYBACK        6
  99
 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 101 #define ATIHDMI_NUM_CAPTURE     0
 102 #define ATIHDMI_NUM_PLAYBACK    8
 103
 104 /* TERA has 4 playback and 3 capture */
 105 #define TERA_NUM_CAPTURE        3
 106 #define TERA_NUM_PLAYBACK       4
 107
 108
 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 112 static char *model[SNDRV_CARDS];
 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_only[SNDRV_CARDS];
 117 static int jackpoll_ms[SNDRV_CARDS];
 118 static int single_cmd = -1;
 119 static int enable_msi = -1;
 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 121 static char *patch[SNDRV_CARDS];
 122 #endif
 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 125                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 126 #endif
 127 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 128
 129 module_param_array(index, int, NULL, 0444);
 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 131 module_param_array(id, charp, NULL, 0444);
 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 133 module_param_array(enable, bool, NULL, 0444);
 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 135 module_param_array(model, charp, NULL, 0444);
 136 MODULE_PARM_DESC(model, "Use the given board model.");
 137 module_param_array(position_fix, int, NULL, 0444);
 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 139                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 140 module_param_array(bdl_pos_adj, int, NULL, 0644);
 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 142 module_param_array(probe_mask, int, NULL, 0444);
 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 144 module_param_array(probe_only, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 146 module_param_array(jackpoll_ms, int, NULL, 0444);
 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 148 module_param(single_cmd, bint, 0444);
 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 150                  "(for debugging only).");
 151 module_param(enable_msi, bint, 0444);
 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 154 module_param_array(patch, charp, NULL, 0444);
 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 156 #endif
 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 158 module_param_array(beep_mode, bool, NULL, 0444);
 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 160                             "(0=off, 1=on) (default=1).");
 161 #endif
 162 module_param(dmic_detect, bool, 0444);
 163 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 164
 165 #ifdef CONFIG_PM
 166 static int param_set_xint(const char *val, const struct kernel_param *kp);
 167 static const struct kernel_param_ops param_ops_xint = {
 168         .set = param_set_xint,
 169         .get = param_get_int,
 170 };
 171 #define param_check_xint param_check_int
 172
 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 174 module_param(power_save, xint, 0644);
 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 176                  "(in second, 0 = disable).");
 177
 178 static bool pm_blacklist = true;
 179 module_param(pm_blacklist, bool, 0644);
 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 181
 182 /* reset the HD-audio controller in power save mode.
 183  * this may give more power-saving, but will take longer time to
 184  * wake up.
 185  */
 186 static bool power_save_controller = 1;
 187 module_param(power_save_controller, bool, 0644);
 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 189 #else
 190 #define power_save      0
 191 #endif /* CONFIG_PM */
 192
 193 static int align_buffer_size = -1;
 194 module_param(align_buffer_size, bint, 0644);
 195 MODULE_PARM_DESC(align_buffer_size,
 196                 "Force buffer and period sizes to be multiple of 128 bytes.");
 197
 198 #ifdef CONFIG_X86
 199 static int hda_snoop = -1;
 200 module_param_named(snoop, hda_snoop, bint, 0444);
 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 202 #else
 203 #define hda_snoop               true
 204 #endif
 205
 206
 207 MODULE_LICENSE("GPL");
 208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 209                          "{Intel, ICH6M},"
 210                          "{Intel, ICH7},"
 211                          "{Intel, ESB2},"
 212                          "{Intel, ICH8},"
 213                          "{Intel, ICH9},"
 214                          "{Intel, ICH10},"
 215                          "{Intel, PCH},"
 216                          "{Intel, CPT},"
 217                          "{Intel, PPT},"
 218                          "{Intel, LPT},"
 219                          "{Intel, LPT_LP},"
 220                          "{Intel, WPT_LP},"
 221                          "{Intel, SPT},"
 222                          "{Intel, SPT_LP},"
 223                          "{Intel, HPT},"
 224                          "{Intel, PBG},"
 225                          "{Intel, SCH},"
 226                          "{ATI, SB450},"
 227                          "{ATI, SB600},"
 228                          "{ATI, RS600},"
 229                          "{ATI, RS690},"
 230                          "{ATI, RS780},"
 231                          "{ATI, R600},"
 232                          "{ATI, RV630},"
 233                          "{ATI, RV610},"
 234                          "{ATI, RV670},"
 235                          "{ATI, RV635},"
 236                          "{ATI, RV620},"
 237                          "{ATI, RV770},"
 238                          "{VIA, VT8251},"
 239                          "{VIA, VT8237A},"
 240                          "{SiS, SIS966},"
 241                          "{ULI, M5461}}");
 242 MODULE_DESCRIPTION("Intel HDA driver");
 243
 244 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 245 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 246 #define SUPPORT_VGA_SWITCHEROO
 247 #endif
 248 #endif
 249
 250
 251 /*
 252  */
 253
 254 /* driver types */
 255 enum {
 256         AZX_DRIVER_ICH,
 257         AZX_DRIVER_PCH,
 258         AZX_DRIVER_SCH,
 259         AZX_DRIVER_SKL,
 260         AZX_DRIVER_HDMI,
 261         AZX_DRIVER_ATI,
 262         AZX_DRIVER_ATIHDMI,
 263         AZX_DRIVER_ATIHDMI_NS,
 264         AZX_DRIVER_VIA,
 265         AZX_DRIVER_SIS,
 266         AZX_DRIVER_ULI,
 267         AZX_DRIVER_NVIDIA,
 268         AZX_DRIVER_TERA,
 269         AZX_DRIVER_CTX,
 270         AZX_DRIVER_CTHDA,
 271         AZX_DRIVER_CMEDIA,
 272         AZX_DRIVER_ZHAOXIN,
 273         AZX_DRIVER_GENERIC,
 274         AZX_NUM_DRIVERS, /* keep this as last entry */
 275 };
 276
 277 #define azx_get_snoop_type(chip) \
 278         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 279 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 280
 281 /* quirks for old Intel chipsets */
 282 #define AZX_DCAPS_INTEL_ICH \
 283         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
 284          AZX_DCAPS_SYNC_WRITE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 290
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 305
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 311
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SYNC_WRITE |\
 322          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 325
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339
 340 /* quirks for AMD SB */
 341 #define AZX_DCAPS_PRESET_AMD_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 344
 345 /* quirks for Nvidia */
 346 #define AZX_DCAPS_PRESET_NVIDIA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 348          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 349
 350 #define AZX_DCAPS_PRESET_CTHDA \
 351         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 352          AZX_DCAPS_NO_64BIT |\
 353          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 354
 355 /*
 356  * vga_switcheroo support
 357  */
 358 #ifdef SUPPORT_VGA_SWITCHEROO
 359 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 360 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 361 #else
 362 #define use_vga_switcheroo(chip)        0
 363 #define needs_eld_notify_link(chip)     false
 364 #endif
 365
 366 #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) &&         \
 367                                        (((pci)->device == 0x0a0c) || \
 368                                         ((pci)->device == 0x0c0c) || \
 369                                         ((pci)->device == 0x0d0c) || \
 370                                         ((pci)->device == 0x160c) || \
 371                                         ((pci)->device == 0x490d) || \
 372                                         ((pci)->device == 0x4f90) || \
 373                                         ((pci)->device == 0x4f91) || \
 374                                         ((pci)->device == 0x4f92)))
 375
 376 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 377 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 378 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 379
 380 static char *driver_short_names[] = {
 381         [AZX_DRIVER_ICH] = "HDA Intel",
 382         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 383         [AZX_DRIVER_SCH] = "HDA Intel MID",
 384         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 385         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 386         [AZX_DRIVER_ATI] = "HDA ATI SB",
 387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 388         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 389         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 390         [AZX_DRIVER_SIS] = "HDA SIS966",
 391         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 392         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 393         [AZX_DRIVER_TERA] = "HDA Teradici",
 394         [AZX_DRIVER_CTX] = "HDA Creative",
 395         [AZX_DRIVER_CTHDA] = "HDA Creative",
 396         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 397         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 398         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 399 };
 400
 401 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 402 static void set_default_power_save(struct azx *chip);
 403
 404 /*
 405  * initialize the PCI registers
 406  */
 407 /* update bits in a PCI register byte */
 408 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 409                             unsigned char mask, unsigned char val)
 410 {
 411         unsigned char data;
 412
 413         pci_read_config_byte(pci, reg, &data);
 414         data &= ~mask;
 415         data |= (val & mask);
 416         pci_write_config_byte(pci, reg, data);
 417 }
 418
 419 static void azx_init_pci(struct azx *chip)
 420 {
 421         int snoop_type = azx_get_snoop_type(chip);
 422
 423         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 424          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 425          * Ensuring these bits are 0 clears playback static on some HD Audio
 426          * codecs.
 427          * The PCI register TCSEL is defined in the Intel manuals.
 428          */
 429         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 430                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 431                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 432         }
 433
 434         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 435          * we need to enable snoop.
 436          */
 437         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 438                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 439                         azx_snoop(chip));
 440                 update_pci_byte(chip->pci,
 441                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 442                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 443         }
 444
 445         /* For NVIDIA HDA, enable snoop */
 446         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 447                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 448                         azx_snoop(chip));
 449                 update_pci_byte(chip->pci,
 450                                 NVIDIA_HDA_TRANSREG_ADDR,
 451                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 452                 update_pci_byte(chip->pci,
 453                                 NVIDIA_HDA_ISTRM_COH,
 454                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 455                 update_pci_byte(chip->pci,
 456                                 NVIDIA_HDA_OSTRM_COH,
 457                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 458         }
 459
 460         /* Enable SCH/PCH snoop if needed */
 461         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 462                 unsigned short snoop;
 463                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 464                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 465                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 466                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 467                         if (!azx_snoop(chip))
 468                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 469                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 470                         pci_read_config_word(chip->pci,
 471                                 INTEL_SCH_HDA_DEVC, &snoop);
 472                 }
 473                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 474                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 475                         "Disabled" : "Enabled");
 476         }
 477 }
 478
 479 /*
 480  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 481  * and makes an audio stream sensitive to system latencies when
 482  * 24/32 bits are playing.
 483  * Adjusting threshold of DMA fifo to force the DMA request
 484  * sooner to improve latency tolerance at the expense of power.
 485  */
 486 static void bxt_reduce_dma_latency(struct azx *chip)
 487 {
 488         u32 val;
 489
 490         val = azx_readl(chip, VS_EM4L);
 491         val &= (0x3 << 20);
 492         azx_writel(chip, VS_EM4L, val);
 493 }
 494
 495 /*
 496  * ML_LCAP bits:
 497  *  bit 0: 6 MHz Supported
 498  *  bit 1: 12 MHz Supported
 499  *  bit 2: 24 MHz Supported
 500  *  bit 3: 48 MHz Supported
 501  *  bit 4: 96 MHz Supported
 502  *  bit 5: 192 MHz Supported
 503  */
 504 static int intel_get_lctl_scf(struct azx *chip)
 505 {
 506         struct hdac_bus *bus = azx_bus(chip);
 507         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 508         u32 val, t;
 509         int i;
 510
 511         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 512
 513         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 514                 t = preferred_bits[i];
 515                 if (val & (1 << t))
 516                         return t;
 517         }
 518
 519         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 520         return 0;
 521 }
 522
 523 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 524 {
 525         struct hdac_bus *bus = azx_bus(chip);
 526         u32 val;
 527         int timeout;
 528
 529         /*
 530          * the codecs are sharing the first link setting by default
 531          * If other links are enabled for stream, they need similar fix
 532          */
 533         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 534         val &= ~AZX_MLCTL_SPA;
 535         val |= state << AZX_MLCTL_SPA_SHIFT;
 536         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 537         /* wait for CPA */
 538         timeout = 50;
 539         while (timeout) {
 540                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 541                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 542                         return 0;
 543                 timeout--;
 544                 udelay(10);
 545         }
 546
 547         return -1;
 548 }
 549
 550 static void intel_init_lctl(struct azx *chip)
 551 {
 552         struct hdac_bus *bus = azx_bus(chip);
 553         u32 val;
 554         int ret;
 555
 556         /* 0. check lctl register value is correct or not */
 557         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 558         /* if SCF is already set, let's use it */
 559         if ((val & ML_LCTL_SCF_MASK) != 0)
 560                 return;
 561
 562         /*
 563          * Before operating on SPA, CPA must match SPA.
 564          * Any deviation may result in undefined behavior.
 565          */
 566         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 567                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 568                 return;
 569
 570         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 571         ret = intel_ml_lctl_set_power(chip, 0);
 572         udelay(100);
 573         if (ret)
 574                 goto set_spa;
 575
 576         /* 2. update SCF to select a properly audio clock*/
 577         val &= ~ML_LCTL_SCF_MASK;
 578         val |= intel_get_lctl_scf(chip);
 579         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 580
 581 set_spa:
 582         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 583         intel_ml_lctl_set_power(chip, 1);
 584         udelay(100);
 585 }
 586
 587 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 588 {
 589         struct hdac_bus *bus = azx_bus(chip);
 590         struct pci_dev *pci = chip->pci;
 591         u32 val;
 592
 593         snd_hdac_set_codec_wakeup(bus, true);
 594         if (chip->driver_type == AZX_DRIVER_SKL) {
 595                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 596                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 597                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 598         }
 599         azx_init_chip(chip, full_reset);
 600         if (chip->driver_type == AZX_DRIVER_SKL) {
 601                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 602                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 603                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 604         }
 605
 606         snd_hdac_set_codec_wakeup(bus, false);
 607
 608         /* reduce dma latency to avoid noise */
 609         if (IS_BXT(pci))
 610                 bxt_reduce_dma_latency(chip);
 611
 612         if (bus->mlcap != NULL)
 613                 intel_init_lctl(chip);
 614 }
 615
 616 /* calculate runtime delay from LPIB */
 617 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 618                                    unsigned int pos)
 619 {
 620         struct snd_pcm_substream *substream = azx_dev->core.substream;
 621         int stream = substream->stream;
 622         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 623         int delay;
 624
 625         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 626                 delay = pos - lpib_pos;
 627         else
 628                 delay = lpib_pos - pos;
 629         if (delay < 0) {
 630                 if (delay >= azx_dev->core.delay_negative_threshold)
 631                         delay = 0;
 632                 else
 633                         delay += azx_dev->core.bufsize;
 634         }
 635
 636         if (delay >= azx_dev->core.period_bytes) {
 637                 dev_info(chip->card->dev,
 638                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 639                          delay, azx_dev->core.period_bytes);
 640                 delay = 0;
 641                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 642                 chip->get_delay[stream] = NULL;
 643         }
 644
 645         return bytes_to_frames(substream->runtime, delay);
 646 }
 647
 648 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 649
 650 /* called from IRQ */
 651 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 652 {
 653         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 654         int ok;
 655
 656         ok = azx_position_ok(chip, azx_dev);
 657         if (ok == 1) {
 658                 azx_dev->irq_pending = 0;
 659                 return ok;
 660         } else if (ok == 0) {
 661                 /* bogus IRQ, process it later */
 662                 azx_dev->irq_pending = 1;
 663                 schedule_work(&hda->irq_pending_work);
 664         }
 665         return 0;
 666 }
 667
 668 #define display_power(chip, enable) \
 669         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 670
 671 /*
 672  * Check whether the current DMA position is acceptable for updating
 673  * periods.  Returns non-zero if it's OK.
 674  *
 675  * Many HD-audio controllers appear pretty inaccurate about
 676  * the update-IRQ timing.  The IRQ is issued before actually the
 677  * data is processed.  So, we need to process it afterwords in a
 678  * workqueue.
 679  *
 680  * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
 681  */
 682 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 683 {
 684         struct snd_pcm_substream *substream = azx_dev->core.substream;
 685         struct snd_pcm_runtime *runtime = substream->runtime;
 686         int stream = substream->stream;
 687         u32 wallclk;
 688         unsigned int pos;
 689         snd_pcm_uframes_t hwptr, target;
 690
 691         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 692         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 693                 return -1;      /* bogus (too early) interrupt */
 694
 695         if (chip->get_position[stream])
 696                 pos = chip->get_position[stream](chip, azx_dev);
 697         else { /* use the position buffer as default */
 698                 pos = azx_get_pos_posbuf(chip, azx_dev);
 699                 if (!pos || pos == (u32)-1) {
 700                         dev_info(chip->card->dev,
 701                                  "Invalid position buffer, using LPIB read method instead.\n");
 702                         chip->get_position[stream] = azx_get_pos_lpib;
 703                         if (chip->get_position[0] == azx_get_pos_lpib &&
 704                             chip->get_position[1] == azx_get_pos_lpib)
 705                                 azx_bus(chip)->use_posbuf = false;
 706                         pos = azx_get_pos_lpib(chip, azx_dev);
 707                         chip->get_delay[stream] = NULL;
 708                 } else {
 709                         chip->get_position[stream] = azx_get_pos_posbuf;
 710                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 711                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 712                 }
 713         }
 714
 715         if (pos >= azx_dev->core.bufsize)
 716                 pos = 0;
 717
 718         if (WARN_ONCE(!azx_dev->core.period_bytes,
 719                       "hda-intel: zero azx_dev->period_bytes"))
 720                 return -1; /* this shouldn't happen! */
 721         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 722             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 723                 /* NG - it's below the first next period boundary */
 724                 return chip->bdl_pos_adj ? 0 : -1;
 725         azx_dev->core.start_wallclk += wallclk;
 726
 727         if (azx_dev->core.no_period_wakeup)
 728                 return 1; /* OK, no need to check period boundary */
 729
 730         if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
 731                 return 1; /* OK, already in hwptr updating process */
 732
 733         /* check whether the period gets really elapsed */
 734         pos = bytes_to_frames(runtime, pos);
 735         hwptr = runtime->hw_ptr_base + pos;
 736         if (hwptr < runtime->status->hw_ptr)
 737                 hwptr += runtime->buffer_size;
 738         target = runtime->hw_ptr_interrupt + runtime->period_size;
 739         if (hwptr < target) {
 740                 /* too early wakeup, process it later */
 741                 return chip->bdl_pos_adj ? 0 : -1;
 742         }
 743
 744         return 1; /* OK, it's fine */
 745 }
 746
 747 /*
 748  * The work for pending PCM period updates.
 749  */
 750 static void azx_irq_pending_work(struct work_struct *work)
 751 {
 752         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 753         struct azx *chip = &hda->chip;
 754         struct hdac_bus *bus = azx_bus(chip);
 755         struct hdac_stream *s;
 756         int pending, ok;
 757
 758         if (!hda->irq_pending_warned) {
 759                 dev_info(chip->card->dev,
 760                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 761                          chip->card->number);
 762                 hda->irq_pending_warned = 1;
 763         }
 764
 765         for (;;) {
 766                 pending = 0;
 767                 spin_lock_irq(&bus->reg_lock);
 768                 list_for_each_entry(s, &bus->stream_list, list) {
 769                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 770                         if (!azx_dev->irq_pending ||
 771                             !s->substream ||
 772                             !s->running)
 773                                 continue;
 774                         ok = azx_position_ok(chip, azx_dev);
 775                         if (ok > 0) {
 776                                 azx_dev->irq_pending = 0;
 777                                 spin_unlock(&bus->reg_lock);
 778                                 snd_pcm_period_elapsed(s->substream);
 779                                 spin_lock(&bus->reg_lock);
 780                         } else if (ok < 0) {
 781                                 pending = 0;    /* too early */
 782                         } else
 783                                 pending++;
 784                 }
 785                 spin_unlock_irq(&bus->reg_lock);
 786                 if (!pending)
 787                         return;
 788                 msleep(1);
 789         }
 790 }
 791
 792 /* clear irq_pending flags and assure no on-going workq */
 793 static void azx_clear_irq_pending(struct azx *chip)
 794 {
 795         struct hdac_bus *bus = azx_bus(chip);
 796         struct hdac_stream *s;
 797
 798         spin_lock_irq(&bus->reg_lock);
 799         list_for_each_entry(s, &bus->stream_list, list) {
 800                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 801                 azx_dev->irq_pending = 0;
 802         }
 803         spin_unlock_irq(&bus->reg_lock);
 804 }
 805
 806 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 807 {
 808         struct hdac_bus *bus = azx_bus(chip);
 809
 810         if (request_irq(chip->pci->irq, azx_interrupt,
 811                         chip->msi ? 0 : IRQF_SHARED,
 812                         chip->card->irq_descr, chip)) {
 813                 dev_err(chip->card->dev,
 814                         "unable to grab IRQ %d, disabling device\n",
 815                         chip->pci->irq);
 816                 if (do_disconnect)
 817                         snd_card_disconnect(chip->card);
 818                 return -1;
 819         }
 820         bus->irq = chip->pci->irq;
 821         pci_intx(chip->pci, !chip->msi);
 822         return 0;
 823 }
 824
 825 /* get the current DMA position with correction on VIA chips */
 826 static unsigned int azx_via_get_position(struct azx *chip,
 827                                          struct azx_dev *azx_dev)
 828 {
 829         unsigned int link_pos, mini_pos, bound_pos;
 830         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 831         unsigned int fifo_size;
 832
 833         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 834         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 835                 /* Playback, no problem using link position */
 836                 return link_pos;
 837         }
 838
 839         /* Capture */
 840         /* For new chipset,
 841          * use mod to get the DMA position just like old chipset
 842          */
 843         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 844         mod_dma_pos %= azx_dev->core.period_bytes;
 845
 846         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 847
 848         if (azx_dev->insufficient) {
 849                 /* Link position never gather than FIFO size */
 850                 if (link_pos <= fifo_size)
 851                         return 0;
 852
 853                 azx_dev->insufficient = 0;
 854         }
 855
 856         if (link_pos <= fifo_size)
 857                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 858         else
 859                 mini_pos = link_pos - fifo_size;
 860
 861         /* Find nearest previous boudary */
 862         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 863         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 864         if (mod_link_pos >= fifo_size)
 865                 bound_pos = link_pos - mod_link_pos;
 866         else if (mod_dma_pos >= mod_mini_pos)
 867                 bound_pos = mini_pos - mod_mini_pos;
 868         else {
 869                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 870                 if (bound_pos >= azx_dev->core.bufsize)
 871                         bound_pos = 0;
 872         }
 873
 874         /* Calculate real DMA position we want */
 875         return bound_pos + mod_dma_pos;
 876 }
 877
 878 #define AMD_FIFO_SIZE   32
 879
 880 /* get the current DMA position with FIFO size correction */
 881 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 882 {
 883         struct snd_pcm_substream *substream = azx_dev->core.substream;
 884         struct snd_pcm_runtime *runtime = substream->runtime;
 885         unsigned int pos, delay;
 886
 887         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 888         if (!runtime)
 889                 return pos;
 890
 891         runtime->delay = AMD_FIFO_SIZE;
 892         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 893         if (azx_dev->insufficient) {
 894                 if (pos < delay) {
 895                         delay = pos;
 896                         runtime->delay = bytes_to_frames(runtime, pos);
 897                 } else {
 898                         azx_dev->insufficient = 0;
 899                 }
 900         }
 901
 902         /* correct the DMA position for capture stream */
 903         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 904                 if (pos < delay)
 905                         pos += azx_dev->core.bufsize;
 906                 pos -= delay;
 907         }
 908
 909         return pos;
 910 }
 911
 912 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 913                                    unsigned int pos)
 914 {
 915         struct snd_pcm_substream *substream = azx_dev->core.substream;
 916
 917         /* just read back the calculated value in the above */
 918         return substream->runtime->delay;
 919 }
 920
 921 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 922                                          struct azx_dev *azx_dev)
 923 {
 924         return _snd_hdac_chip_readl(azx_bus(chip),
 925                                     AZX_REG_VS_SDXDPIB_XBASE +
 926                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 927                                      azx_dev->core.index));
 928 }
 929
 930 /* get the current DMA position with correction on SKL+ chips */
 931 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 932 {
 933         /* DPIB register gives a more accurate position for playback */
 934         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 935                 return azx_skl_get_dpib_pos(chip, azx_dev);
 936
 937         /* read of DPIB fetches the actual posbuf */
 938         azx_skl_get_dpib_pos(chip, azx_dev);
 939         return azx_get_pos_posbuf(chip, azx_dev);
 940 }
 941
 942 #ifdef CONFIG_PM
 943 static DEFINE_MUTEX(card_list_lock);
 944 static LIST_HEAD(card_list);
 945
 946 static void azx_add_card_list(struct azx *chip)
 947 {
 948         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 949         mutex_lock(&card_list_lock);
 950         list_add(&hda->list, &card_list);
 951         mutex_unlock(&card_list_lock);
 952 }
 953
 954 static void azx_del_card_list(struct azx *chip)
 955 {
 956         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 957         mutex_lock(&card_list_lock);
 958         list_del_init(&hda->list);
 959         mutex_unlock(&card_list_lock);
 960 }
 961
 962 /* trigger power-save check at writing parameter */
 963 static int param_set_xint(const char *val, const struct kernel_param *kp)
 964 {
 965         struct hda_intel *hda;
 966         struct azx *chip;
 967         int prev = power_save;
 968         int ret = param_set_int(val, kp);
 969
 970         if (ret || prev == power_save)
 971                 return ret;
 972
 973         mutex_lock(&card_list_lock);
 974         list_for_each_entry(hda, &card_list, list) {
 975                 chip = &hda->chip;
 976                 if (!hda->probe_continued || chip->disabled)
 977                         continue;
 978                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 979         }
 980         mutex_unlock(&card_list_lock);
 981         return 0;
 982 }
 983
 984 /*
 985  * power management
 986  */
 987 static bool azx_is_pm_ready(struct snd_card *card)
 988 {
 989         struct azx *chip;
 990         struct hda_intel *hda;
 991
 992         if (!card)
 993                 return false;
 994         chip = card->private_data;
 995         hda = container_of(chip, struct hda_intel, chip);
 996         if (chip->disabled || hda->init_failed || !chip->running)
 997                 return false;
 998         return true;
 999 }
1000
1001 static void __azx_runtime_suspend(struct azx *chip)
1002 {
1003         azx_stop_chip(chip);
1004         azx_enter_link_reset(chip);
1005         azx_clear_irq_pending(chip);
1006         display_power(chip, false);
1007 }
1008
1009 static void __azx_runtime_resume(struct azx *chip)
1010 {
1011         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1012         struct hdac_bus *bus = azx_bus(chip);
1013         struct hda_codec *codec;
1014         int status;
1015
1016         display_power(chip, true);
1017         if (hda->need_i915_power)
1018                 snd_hdac_i915_set_bclk(bus);
1019
1020         /* Read STATESTS before controller reset */
1021         status = azx_readw(chip, STATESTS);
1022
1023         azx_init_pci(chip);
1024         hda_intel_init_chip(chip, true);
1025
1026         /* Avoid codec resume if runtime resume is for system suspend */
1027         if (!chip->pm_prepared) {
1028                 list_for_each_codec(codec, &chip->bus) {
1029                         if (codec->relaxed_resume)
1030                                 continue;
1031
1032                         if (codec->forced_resume || (status & (1 << codec->addr)))
1033                                 pm_request_resume(hda_codec_dev(codec));
1034                 }
1035         }
1036
1037         /* power down again for link-controlled chips */
1038         if (!hda->need_i915_power)
1039                 display_power(chip, false);
1040 }
1041
1042 #ifdef CONFIG_PM_SLEEP
1043 static int azx_prepare(struct device *dev)
1044 {
1045         struct snd_card *card = dev_get_drvdata(dev);
1046         struct azx *chip;
1047
1048         if (!azx_is_pm_ready(card))
1049                 return 0;
1050
1051         chip = card->private_data;
1052         chip->pm_prepared = 1;
1053         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1054
1055         flush_work(&azx_bus(chip)->unsol_work);
1056
1057         /* HDA controller always requires different WAKEEN for runtime suspend
1058          * and system suspend, so don't use direct-complete here.
1059          */
1060         return 0;
1061 }
1062
1063 static void azx_complete(struct device *dev)
1064 {
1065         struct snd_card *card = dev_get_drvdata(dev);
1066         struct azx *chip;
1067
1068         if (!azx_is_pm_ready(card))
1069                 return;
1070
1071         chip = card->private_data;
1072         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1073         chip->pm_prepared = 0;
1074 }
1075
1076 static int azx_suspend(struct device *dev)
1077 {
1078         struct snd_card *card = dev_get_drvdata(dev);
1079         struct azx *chip;
1080         struct hdac_bus *bus;
1081
1082         if (!azx_is_pm_ready(card))
1083                 return 0;
1084
1085         chip = card->private_data;
1086         bus = azx_bus(chip);
1087         __azx_runtime_suspend(chip);
1088         if (bus->irq >= 0) {
1089                 free_irq(bus->irq, chip);
1090                 bus->irq = -1;
1091         }
1092
1093         if (chip->msi)
1094                 pci_disable_msi(chip->pci);
1095
1096         trace_azx_suspend(chip);
1097         return 0;
1098 }
1099
1100 static int azx_resume(struct device *dev)
1101 {
1102         struct snd_card *card = dev_get_drvdata(dev);
1103         struct azx *chip;
1104
1105         if (!azx_is_pm_ready(card))
1106                 return 0;
1107
1108         chip = card->private_data;
1109         if (chip->msi)
1110                 if (pci_enable_msi(chip->pci) < 0)
1111                         chip->msi = 0;
1112         if (azx_acquire_irq(chip, 1) < 0)
1113                 return -EIO;
1114
1115         __azx_runtime_resume(chip);
1116
1117         trace_azx_resume(chip);
1118         return 0;
1119 }
1120
1121 /* put codec down to D3 at hibernation for Intel SKL+;
1122  * otherwise BIOS may still access the codec and screw up the driver
1123  */
1124 static int azx_freeze_noirq(struct device *dev)
1125 {
1126         struct snd_card *card = dev_get_drvdata(dev);
1127         struct azx *chip = card->private_data;
1128         struct pci_dev *pci = to_pci_dev(dev);
1129
1130         if (!azx_is_pm_ready(card))
1131                 return 0;
1132         if (chip->driver_type == AZX_DRIVER_SKL)
1133                 pci_set_power_state(pci, PCI_D3hot);
1134
1135         return 0;
1136 }
1137
1138 static int azx_thaw_noirq(struct device *dev)
1139 {
1140         struct snd_card *card = dev_get_drvdata(dev);
1141         struct azx *chip = card->private_data;
1142         struct pci_dev *pci = to_pci_dev(dev);
1143
1144         if (!azx_is_pm_ready(card))
1145                 return 0;
1146         if (chip->driver_type == AZX_DRIVER_SKL)
1147                 pci_set_power_state(pci, PCI_D0);
1148
1149         return 0;
1150 }
1151 #endif /* CONFIG_PM_SLEEP */
1152
1153 static int azx_runtime_suspend(struct device *dev)
1154 {
1155         struct snd_card *card = dev_get_drvdata(dev);
1156         struct azx *chip;
1157
1158         if (!azx_is_pm_ready(card))
1159                 return 0;
1160         chip = card->private_data;
1161
1162         /* enable controller wake up event */
1163         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1164
1165         __azx_runtime_suspend(chip);
1166         trace_azx_runtime_suspend(chip);
1167         return 0;
1168 }
1169
1170 static int azx_runtime_resume(struct device *dev)
1171 {
1172         struct snd_card *card = dev_get_drvdata(dev);
1173         struct azx *chip;
1174
1175         if (!azx_is_pm_ready(card))
1176                 return 0;
1177         chip = card->private_data;
1178         __azx_runtime_resume(chip);
1179
1180         /* disable controller Wake Up event*/
1181         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1182
1183         trace_azx_runtime_resume(chip);
1184         return 0;
1185 }
1186
1187 static int azx_runtime_idle(struct device *dev)
1188 {
1189         struct snd_card *card = dev_get_drvdata(dev);
1190         struct azx *chip;
1191         struct hda_intel *hda;
1192
1193         if (!card)
1194                 return 0;
1195
1196         chip = card->private_data;
1197         hda = container_of(chip, struct hda_intel, chip);
1198         if (chip->disabled || hda->init_failed)
1199                 return 0;
1200
1201         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1202             azx_bus(chip)->codec_powered || !chip->running)
1203                 return -EBUSY;
1204
1205         /* ELD notification gets broken when HD-audio bus is off */
1206         if (needs_eld_notify_link(chip))
1207                 return -EBUSY;
1208
1209         return 0;
1210 }
1211
1212 static const struct dev_pm_ops azx_pm = {
1213         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1214 #ifdef CONFIG_PM_SLEEP
1215         .prepare = azx_prepare,
1216         .complete = azx_complete,
1217         .freeze_noirq = azx_freeze_noirq,
1218         .thaw_noirq = azx_thaw_noirq,
1219 #endif
1220         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1221 };
1222
1223 #define AZX_PM_OPS      &azx_pm
1224 #else
1225 #define azx_add_card_list(chip) /* NOP */
1226 #define azx_del_card_list(chip) /* NOP */
1227 #define AZX_PM_OPS      NULL
1228 #endif /* CONFIG_PM */
1229
1230
1231 static int azx_probe_continue(struct azx *chip);
1232
1233 #ifdef SUPPORT_VGA_SWITCHEROO
1234 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1235
1236 static void azx_vs_set_state(struct pci_dev *pci,
1237                              enum vga_switcheroo_state state)
1238 {
1239         struct snd_card *card = pci_get_drvdata(pci);
1240         struct azx *chip = card->private_data;
1241         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242         struct hda_codec *codec;
1243         bool disabled;
1244
1245         wait_for_completion(&hda->probe_wait);
1246         if (hda->init_failed)
1247                 return;
1248
1249         disabled = (state == VGA_SWITCHEROO_OFF);
1250         if (chip->disabled == disabled)
1251                 return;
1252
1253         if (!hda->probe_continued) {
1254                 chip->disabled = disabled;
1255                 if (!disabled) {
1256                         dev_info(chip->card->dev,
1257                                  "Start delayed initialization\n");
1258                         if (azx_probe_continue(chip) < 0)
1259                                 dev_err(chip->card->dev, "initialization error\n");
1260                 }
1261         } else {
1262                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1263                          disabled ? "Disabling" : "Enabling");
1264                 if (disabled) {
1265                         list_for_each_codec(codec, &chip->bus) {
1266                                 pm_runtime_suspend(hda_codec_dev(codec));
1267                                 pm_runtime_disable(hda_codec_dev(codec));
1268                         }
1269                         pm_runtime_suspend(card->dev);
1270                         pm_runtime_disable(card->dev);
1271                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1272                          * however we have no ACPI handle, so pci/acpi can't put us there,
1273                          * put ourselves there */
1274                         pci->current_state = PCI_D3cold;
1275                         chip->disabled = true;
1276                         if (snd_hda_lock_devices(&chip->bus))
1277                                 dev_warn(chip->card->dev,
1278                                          "Cannot lock devices!\n");
1279                 } else {
1280                         snd_hda_unlock_devices(&chip->bus);
1281                         chip->disabled = false;
1282                         pm_runtime_enable(card->dev);
1283                         list_for_each_codec(codec, &chip->bus) {
1284                                 pm_runtime_enable(hda_codec_dev(codec));
1285                                 pm_runtime_resume(hda_codec_dev(codec));
1286                         }
1287                 }
1288         }
1289 }
1290
1291 static bool azx_vs_can_switch(struct pci_dev *pci)
1292 {
1293         struct snd_card *card = pci_get_drvdata(pci);
1294         struct azx *chip = card->private_data;
1295         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1296
1297         wait_for_completion(&hda->probe_wait);
1298         if (hda->init_failed)
1299                 return false;
1300         if (chip->disabled || !hda->probe_continued)
1301                 return true;
1302         if (snd_hda_lock_devices(&chip->bus))
1303                 return false;
1304         snd_hda_unlock_devices(&chip->bus);
1305         return true;
1306 }
1307
1308 /*
1309  * The discrete GPU cannot power down unless the HDA controller runtime
1310  * suspends, so activate runtime PM on codecs even if power_save == 0.
1311  */
1312 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1313 {
1314         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1315         struct hda_codec *codec;
1316
1317         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1318                 list_for_each_codec(codec, &chip->bus)
1319                         codec->auto_runtime_pm = 1;
1320                 /* reset the power save setup */
1321                 if (chip->running)
1322                         set_default_power_save(chip);
1323         }
1324 }
1325
1326 static void azx_vs_gpu_bound(struct pci_dev *pci,
1327                              enum vga_switcheroo_client_id client_id)
1328 {
1329         struct snd_card *card = pci_get_drvdata(pci);
1330         struct azx *chip = card->private_data;
1331
1332         if (client_id == VGA_SWITCHEROO_DIS)
1333                 chip->bus.keep_power = 0;
1334         setup_vga_switcheroo_runtime_pm(chip);
1335 }
1336
1337 static void init_vga_switcheroo(struct azx *chip)
1338 {
1339         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1340         struct pci_dev *p = get_bound_vga(chip->pci);
1341         struct pci_dev *parent;
1342         if (p) {
1343                 dev_info(chip->card->dev,
1344                          "Handle vga_switcheroo audio client\n");
1345                 hda->use_vga_switcheroo = 1;
1346
1347                 /* cleared in either gpu_bound op or codec probe, or when its
1348                  * upstream port has _PR3 (i.e. dGPU).
1349                  */
1350                 parent = pci_upstream_bridge(p);
1351                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1352                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1353                 pci_dev_put(p);
1354         }
1355 }
1356
1357 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1358         .set_gpu_state = azx_vs_set_state,
1359         .can_switch = azx_vs_can_switch,
1360         .gpu_bound = azx_vs_gpu_bound,
1361 };
1362
1363 static int register_vga_switcheroo(struct azx *chip)
1364 {
1365         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1366         struct pci_dev *p;
1367         int err;
1368
1369         if (!hda->use_vga_switcheroo)
1370                 return 0;
1371
1372         p = get_bound_vga(chip->pci);
1373         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1374         pci_dev_put(p);
1375
1376         if (err < 0)
1377                 return err;
1378         hda->vga_switcheroo_registered = 1;
1379
1380         return 0;
1381 }
1382 #else
1383 #define init_vga_switcheroo(chip)               /* NOP */
1384 #define register_vga_switcheroo(chip)           0
1385 #define check_hdmi_disabled(pci)        false
1386 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1387 #endif /* SUPPORT_VGA_SWITCHER */
1388
1389 /*
1390  * destructor
1391  */
1392 static void azx_free(struct azx *chip)
1393 {
1394         struct pci_dev *pci = chip->pci;
1395         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1396         struct hdac_bus *bus = azx_bus(chip);
1397
1398         if (hda->freed)
1399                 return;
1400
1401         if (azx_has_pm_runtime(chip) && chip->running)
1402                 pm_runtime_get_noresume(&pci->dev);
1403         chip->running = 0;
1404
1405         azx_del_card_list(chip);
1406
1407         hda->init_failed = 1; /* to be sure */
1408         complete_all(&hda->probe_wait);
1409
1410         if (use_vga_switcheroo(hda)) {
1411                 if (chip->disabled && hda->probe_continued)
1412                         snd_hda_unlock_devices(&chip->bus);
1413                 if (hda->vga_switcheroo_registered)
1414                         vga_switcheroo_unregister_client(chip->pci);
1415         }
1416
1417         if (bus->chip_init) {
1418                 azx_clear_irq_pending(chip);
1419                 azx_stop_all_streams(chip);
1420                 azx_stop_chip(chip);
1421         }
1422
1423         if (bus->irq >= 0)
1424                 free_irq(bus->irq, (void*)chip);
1425         if (chip->msi)
1426                 pci_disable_msi(chip->pci);
1427         iounmap(bus->remap_addr);
1428
1429         azx_free_stream_pages(chip);
1430         azx_free_streams(chip);
1431         snd_hdac_bus_exit(bus);
1432
1433         if (chip->region_requested)
1434                 pci_release_regions(chip->pci);
1435
1436         pci_disable_device(chip->pci);
1437 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1438         release_firmware(chip->fw);
1439 #endif
1440         display_power(chip, false);
1441
1442         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1443                 snd_hdac_i915_exit(bus);
1444
1445         hda->freed = 1;
1446 }
1447
1448 static int azx_dev_disconnect(struct snd_device *device)
1449 {
1450         struct azx *chip = device->device_data;
1451         struct hdac_bus *bus = azx_bus(chip);
1452
1453         chip->bus.shutdown = 1;
1454         cancel_work_sync(&bus->unsol_work);
1455
1456         return 0;
1457 }
1458
1459 static int azx_dev_free(struct snd_device *device)
1460 {
1461         azx_free(device->device_data);
1462         return 0;
1463 }
1464
1465 #ifdef SUPPORT_VGA_SWITCHEROO
1466 /*
1467  * Check of disabled HDMI controller by vga_switcheroo
1468  */
1469 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1470 {
1471         struct pci_dev *p;
1472
1473         /* check only discrete GPU */
1474         switch (pci->vendor) {
1475         case PCI_VENDOR_ID_ATI:
1476         case PCI_VENDOR_ID_AMD:
1477         case PCI_VENDOR_ID_NVIDIA:
1478                 if (pci->devfn == 1) {
1479                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1480                                                         pci->bus->number, 0);
1481                         if (p) {
1482                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1483                                         return p;
1484                                 pci_dev_put(p);
1485                         }
1486                 }
1487                 break;
1488         }
1489         return NULL;
1490 }
1491
1492 static bool check_hdmi_disabled(struct pci_dev *pci)
1493 {
1494         bool vga_inactive = false;
1495         struct pci_dev *p = get_bound_vga(pci);
1496
1497         if (p) {
1498                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1499                         vga_inactive = true;
1500                 pci_dev_put(p);
1501         }
1502         return vga_inactive;
1503 }
1504 #endif /* SUPPORT_VGA_SWITCHEROO */
1505
1506 /*
1507  * white/black-listing for position_fix
1508  */
1509 static struct snd_pci_quirk position_fix_list[] = {
1510         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1511         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1512         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1513         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1514         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1515         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1522         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1523         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1524         {}
1525 };
1526
1527 static int check_position_fix(struct azx *chip, int fix)
1528 {
1529         const struct snd_pci_quirk *q;
1530
1531         switch (fix) {
1532         case POS_FIX_AUTO:
1533         case POS_FIX_LPIB:
1534         case POS_FIX_POSBUF:
1535         case POS_FIX_VIACOMBO:
1536         case POS_FIX_COMBO:
1537         case POS_FIX_SKL:
1538         case POS_FIX_FIFO:
1539                 return fix;
1540         }
1541
1542         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1543         if (q) {
1544                 dev_info(chip->card->dev,
1545                          "position_fix set to %d for device %04x:%04x\n",
1546                          q->value, q->subvendor, q->subdevice);
1547                 return q->value;
1548         }
1549
1550         /* Check VIA/ATI HD Audio Controller exist */
1551         if (chip->driver_type == AZX_DRIVER_VIA) {
1552                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1553                 return POS_FIX_VIACOMBO;
1554         }
1555         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1556                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1557                 return POS_FIX_FIFO;
1558         }
1559         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1560                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1561                 return POS_FIX_LPIB;
1562         }
1563         if (chip->driver_type == AZX_DRIVER_SKL) {
1564                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1565                 return POS_FIX_SKL;
1566         }
1567         return POS_FIX_AUTO;
1568 }
1569
1570 static void assign_position_fix(struct azx *chip, int fix)
1571 {
1572         static azx_get_pos_callback_t callbacks[] = {
1573                 [POS_FIX_AUTO] = NULL,
1574                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1575                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1576                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1577                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1578                 [POS_FIX_SKL] = azx_get_pos_skl,
1579                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1580         };
1581
1582         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1583
1584         /* combo mode uses LPIB only for playback */
1585         if (fix == POS_FIX_COMBO)
1586                 chip->get_position[1] = NULL;
1587
1588         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1589             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1590                 chip->get_delay[0] = chip->get_delay[1] =
1591                         azx_get_delay_from_lpib;
1592         }
1593
1594         if (fix == POS_FIX_FIFO)
1595                 chip->get_delay[0] = chip->get_delay[1] =
1596                         azx_get_delay_from_fifo;
1597 }
1598
1599 /*
1600  * black-lists for probe_mask
1601  */
1602 static struct snd_pci_quirk probe_mask_list[] = {
1603         /* Thinkpad often breaks the controller communication when accessing
1604          * to the non-working (or non-existing) modem codec slot.
1605          */
1606         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1607         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1608         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1609         /* broken BIOS */
1610         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1611         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1612         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1613         /* forced codec slots */
1614         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1615         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1616         SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1617         /* WinFast VP200 H (Teradici) user reported broken communication */
1618         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1619         {}
1620 };
1621
1622 #define AZX_FORCE_CODEC_MASK    0x100
1623
1624 static void check_probe_mask(struct azx *chip, int dev)
1625 {
1626         const struct snd_pci_quirk *q;
1627
1628         chip->codec_probe_mask = probe_mask[dev];
1629         if (chip->codec_probe_mask == -1) {
1630                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1631                 if (q) {
1632                         dev_info(chip->card->dev,
1633                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1634                                  q->value, q->subvendor, q->subdevice);
1635                         chip->codec_probe_mask = q->value;
1636                 }
1637         }
1638
1639         /* check forced option */
1640         if (chip->codec_probe_mask != -1 &&
1641             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1642                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1643                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1644                          (int)azx_bus(chip)->codec_mask);
1645         }
1646 }
1647
1648 /*
1649  * white/black-list for enable_msi
1650  */
1651 static struct snd_pci_quirk msi_black_list[] = {
1652         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1653         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1654         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1655         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1656         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1657         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1658         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1659         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1660         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1661         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1662         {}
1663 };
1664
1665 static void check_msi(struct azx *chip)
1666 {
1667         const struct snd_pci_quirk *q;
1668
1669         if (enable_msi >= 0) {
1670                 chip->msi = !!enable_msi;
1671                 return;
1672         }
1673         chip->msi = 1;  /* enable MSI as default */
1674         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1675         if (q) {
1676                 dev_info(chip->card->dev,
1677                          "msi for device %04x:%04x set to %d\n",
1678                          q->subvendor, q->subdevice, q->value);
1679                 chip->msi = q->value;
1680                 return;
1681         }
1682
1683         /* NVidia chipsets seem to cause troubles with MSI */
1684         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1685                 dev_info(chip->card->dev, "Disabling MSI\n");
1686                 chip->msi = 0;
1687         }
1688 }
1689
1690 /* check the snoop mode availability */
1691 static void azx_check_snoop_available(struct azx *chip)
1692 {
1693         int snoop = hda_snoop;
1694
1695         if (snoop >= 0) {
1696                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1697                          snoop ? "snoop" : "non-snoop");
1698                 chip->snoop = snoop;
1699                 chip->uc_buffer = !snoop;
1700                 return;
1701         }
1702
1703         snoop = true;
1704         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1705             chip->driver_type == AZX_DRIVER_VIA) {
1706                 /* force to non-snoop mode for a new VIA controller
1707                  * when BIOS is set
1708                  */
1709                 u8 val;
1710                 pci_read_config_byte(chip->pci, 0x42, &val);
1711                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1712                                       chip->pci->revision == 0x20))
1713                         snoop = false;
1714         }
1715
1716         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1717                 snoop = false;
1718
1719         chip->snoop = snoop;
1720         if (!snoop) {
1721                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1722                 /* C-Media requires non-cached pages only for CORB/RIRB */
1723                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1724                         chip->uc_buffer = true;
1725         }
1726 }
1727
1728 static void azx_probe_work(struct work_struct *work)
1729 {
1730         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1731         azx_probe_continue(&hda->chip);
1732 }
1733
1734 static int default_bdl_pos_adj(struct azx *chip)
1735 {
1736         /* some exceptions: Atoms seem problematic with value 1 */
1737         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1738                 switch (chip->pci->device) {
1739                 case 0x0f04: /* Baytrail */
1740                 case 0x2284: /* Braswell */
1741                         return 32;
1742                 }
1743         }
1744
1745         switch (chip->driver_type) {
1746         case AZX_DRIVER_ICH:
1747         case AZX_DRIVER_PCH:
1748                 return 1;
1749         default:
1750                 return 32;
1751         }
1752 }
1753
1754 /*
1755  * constructor
1756  */
1757 static const struct hda_controller_ops pci_hda_ops;
1758
1759 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1760                       int dev, unsigned int driver_caps,
1761                       struct azx **rchip)
1762 {
1763         static struct snd_device_ops ops = {
1764                 .dev_disconnect = azx_dev_disconnect,
1765                 .dev_free = azx_dev_free,
1766         };
1767         struct hda_intel *hda;
1768         struct azx *chip;
1769         int err;
1770
1771         *rchip = NULL;
1772
1773         err = pci_enable_device(pci);
1774         if (err < 0)
1775                 return err;
1776
1777         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1778         if (!hda) {
1779                 pci_disable_device(pci);
1780                 return -ENOMEM;
1781         }
1782
1783         chip = &hda->chip;
1784         mutex_init(&chip->open_mutex);
1785         chip->card = card;
1786         chip->pci = pci;
1787         chip->ops = &pci_hda_ops;
1788         chip->driver_caps = driver_caps;
1789         chip->driver_type = driver_caps & 0xff;
1790         check_msi(chip);
1791         chip->dev_index = dev;
1792         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1793                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1794         INIT_LIST_HEAD(&chip->pcm_list);
1795         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1796         INIT_LIST_HEAD(&hda->list);
1797         init_vga_switcheroo(chip);
1798         init_completion(&hda->probe_wait);
1799
1800         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1801
1802         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1803                 chip->fallback_to_single_cmd = 1;
1804         else /* explicitly set to single_cmd or not */
1805                 chip->single_cmd = single_cmd;
1806
1807         azx_check_snoop_available(chip);
1808
1809         if (bdl_pos_adj[dev] < 0)
1810                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1811         else
1812                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1813
1814         err = azx_bus_init(chip, model[dev]);
1815         if (err < 0) {
1816                 pci_disable_device(pci);
1817                 return err;
1818         }
1819
1820         /* use the non-cached pages in non-snoop mode */
1821         if (!azx_snoop(chip))
1822                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1823
1824         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1825         if (IS_CFL(pci) || IS_CNL(pci))
1826                 azx_bus(chip)->polling_mode = 1;
1827
1828         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1829                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1830                 chip->bus.needs_damn_long_delay = 1;
1831         }
1832
1833         check_probe_mask(chip, dev);
1834
1835         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1836         if (err < 0) {
1837                 dev_err(card->dev, "Error creating device [card]!\n");
1838                 azx_free(chip);
1839                 return err;
1840         }
1841
1842         /* continue probing in work context as may trigger request module */
1843         INIT_WORK(&hda->probe_work, azx_probe_work);
1844
1845         *rchip = chip;
1846
1847         return 0;
1848 }
1849
1850 static int azx_first_init(struct azx *chip)
1851 {
1852         int dev = chip->dev_index;
1853         struct pci_dev *pci = chip->pci;
1854         struct snd_card *card = chip->card;
1855         struct hdac_bus *bus = azx_bus(chip);
1856         int err;
1857         unsigned short gcap;
1858         unsigned int dma_bits = 64;
1859
1860 #if BITS_PER_LONG != 64
1861         /* Fix up base address on ULI M5461 */
1862         if (chip->driver_type == AZX_DRIVER_ULI) {
1863                 u16 tmp3;
1864                 pci_read_config_word(pci, 0x40, &tmp3);
1865                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1866                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1867         }
1868 #endif
1869
1870         err = pci_request_regions(pci, "ICH HD audio");
1871         if (err < 0)
1872                 return err;
1873         chip->region_requested = 1;
1874
1875         bus->addr = pci_resource_start(pci, 0);
1876         bus->remap_addr = pci_ioremap_bar(pci, 0);
1877         if (bus->remap_addr == NULL) {
1878                 dev_err(card->dev, "ioremap error\n");
1879                 return -ENXIO;
1880         }
1881
1882         if (chip->driver_type == AZX_DRIVER_SKL)
1883                 snd_hdac_bus_parse_capabilities(bus);
1884
1885         /*
1886          * Some Intel CPUs has always running timer (ART) feature and
1887          * controller may have Global time sync reporting capability, so
1888          * check both of these before declaring synchronized time reporting
1889          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1890          */
1891         chip->gts_present = false;
1892
1893 #ifdef CONFIG_X86
1894         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1895                 chip->gts_present = true;
1896 #endif
1897
1898         if (chip->msi) {
1899                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1900                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1901                         pci->no_64bit_msi = true;
1902                 }
1903                 if (pci_enable_msi(pci) < 0)
1904                         chip->msi = 0;
1905         }
1906
1907         pci_set_master(pci);
1908         synchronize_irq(bus->irq);
1909
1910         gcap = azx_readw(chip, GCAP);
1911         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1912
1913         /* AMD devices support 40 or 48bit DMA, take the safe one */
1914         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1915                 dma_bits = 40;
1916
1917         /* disable SB600 64bit support for safety */
1918         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1919                 struct pci_dev *p_smbus;
1920                 dma_bits = 40;
1921                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1922                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1923                                          NULL);
1924                 if (p_smbus) {
1925                         if (p_smbus->revision < 0x30)
1926                                 gcap &= ~AZX_GCAP_64OK;
1927                         pci_dev_put(p_smbus);
1928                 }
1929         }
1930
1931         /* NVidia hardware normally only supports up to 40 bits of DMA */
1932         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1933                 dma_bits = 40;
1934
1935         /* disable 64bit DMA address on some devices */
1936         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1937                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1938                 gcap &= ~AZX_GCAP_64OK;
1939         }
1940
1941         /* disable buffer size rounding to 128-byte multiples if supported */
1942         if (align_buffer_size >= 0)
1943                 chip->align_buffer_size = !!align_buffer_size;
1944         else {
1945                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1946                         chip->align_buffer_size = 0;
1947                 else
1948                         chip->align_buffer_size = 1;
1949         }
1950
1951         /* allow 64bit DMA address if supported by H/W */
1952         if (!(gcap & AZX_GCAP_64OK))
1953                 dma_bits = 32;
1954         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1955                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1956         } else {
1957                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1958                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1959         }
1960
1961         /* read number of streams from GCAP register instead of using
1962          * hardcoded value
1963          */
1964         chip->capture_streams = (gcap >> 8) & 0x0f;
1965         chip->playback_streams = (gcap >> 12) & 0x0f;
1966         if (!chip->playback_streams && !chip->capture_streams) {
1967                 /* gcap didn't give any info, switching to old method */
1968
1969                 switch (chip->driver_type) {
1970                 case AZX_DRIVER_ULI:
1971                         chip->playback_streams = ULI_NUM_PLAYBACK;
1972                         chip->capture_streams = ULI_NUM_CAPTURE;
1973                         break;
1974                 case AZX_DRIVER_ATIHDMI:
1975                 case AZX_DRIVER_ATIHDMI_NS:
1976                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1977                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1978                         break;
1979                 case AZX_DRIVER_GENERIC:
1980                 default:
1981                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1982                         chip->capture_streams = ICH6_NUM_CAPTURE;
1983                         break;
1984                 }
1985         }
1986         chip->capture_index_offset = 0;
1987         chip->playback_index_offset = chip->capture_streams;
1988         chip->num_streams = chip->playback_streams + chip->capture_streams;
1989
1990         /* sanity check for the SDxCTL.STRM field overflow */
1991         if (chip->num_streams > 15 &&
1992             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1993                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1994                          "forcing separate stream tags", chip->num_streams);
1995                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1996         }
1997
1998         /* initialize streams */
1999         err = azx_init_streams(chip);
2000         if (err < 0)
2001                 return err;
2002
2003         err = azx_alloc_stream_pages(chip);
2004         if (err < 0)
2005                 return err;
2006
2007         /* initialize chip */
2008         azx_init_pci(chip);
2009
2010         snd_hdac_i915_set_bclk(bus);
2011
2012         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2013
2014         /* codec detection */
2015         if (!azx_bus(chip)->codec_mask) {
2016                 dev_err(card->dev, "no codecs found!\n");
2017                 /* keep running the rest for the runtime PM */
2018         }
2019
2020         if (azx_acquire_irq(chip, 0) < 0)
2021                 return -EBUSY;
2022
2023         strcpy(card->driver, "HDA-Intel");
2024         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2025                 sizeof(card->shortname));
2026         snprintf(card->longname, sizeof(card->longname),
2027                  "%s at 0x%lx irq %i",
2028                  card->shortname, bus->addr, bus->irq);
2029
2030         return 0;
2031 }
2032
2033 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2034 /* callback from request_firmware_nowait() */
2035 static void azx_firmware_cb(const struct firmware *fw, void *context)
2036 {
2037         struct snd_card *card = context;
2038         struct azx *chip = card->private_data;
2039
2040         if (fw)
2041                 chip->fw = fw;
2042         else
2043                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2044         if (!chip->disabled) {
2045                 /* continue probing */
2046                 azx_probe_continue(chip);
2047         }
2048 }
2049 #endif
2050
2051 static int disable_msi_reset_irq(struct azx *chip)
2052 {
2053         struct hdac_bus *bus = azx_bus(chip);
2054         int err;
2055
2056         free_irq(bus->irq, chip);
2057         bus->irq = -1;
2058         pci_disable_msi(chip->pci);
2059         chip->msi = 0;
2060         err = azx_acquire_irq(chip, 1);
2061         if (err < 0)
2062                 return err;
2063
2064         return 0;
2065 }
2066
2067 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2068                              struct vm_area_struct *area)
2069 {
2070 #ifdef CONFIG_X86
2071         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2072         struct azx *chip = apcm->chip;
2073         if (chip->uc_buffer)
2074                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2075 #endif
2076 }
2077
2078 /* Blacklist for skipping the whole probe:
2079  * some HD-audio PCI entries are exposed without any codecs, and such devices
2080  * should be ignored from the beginning.
2081  */
2082 static const struct pci_device_id driver_blacklist[] = {
2083         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2084         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2085         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2086         {}
2087 };
2088
2089 static const struct hda_controller_ops pci_hda_ops = {
2090         .disable_msi_reset_irq = disable_msi_reset_irq,
2091         .pcm_mmap_prepare = pcm_mmap_prepare,
2092         .position_check = azx_position_check,
2093 };
2094
2095 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2096 {
2097         struct nhlt_acpi_table *nhlt;
2098         int ret = 0;
2099
2100         if (chip->driver_type == AZX_DRIVER_SKL &&
2101             pci->class != 0x040300) {
2102                 nhlt = intel_nhlt_init(&pci->dev);
2103                 if (nhlt) {
2104                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2105                                 ret = -ENODEV;
2106                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2107                         }
2108                         intel_nhlt_free(nhlt);
2109                 }
2110         }
2111         return ret;
2112 }
2113
2114 static int azx_probe(struct pci_dev *pci,
2115                      const struct pci_device_id *pci_id)
2116 {
2117         static int dev;
2118         struct snd_card *card;
2119         struct hda_intel *hda;
2120         struct azx *chip;
2121         bool schedule_probe;
2122         int err;
2123
2124         if (pci_match_id(driver_blacklist, pci)) {
2125                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2126                 return -ENODEV;
2127         }
2128
2129         if (dev >= SNDRV_CARDS)
2130                 return -ENODEV;
2131         if (!enable[dev]) {
2132                 dev++;
2133                 return -ENOENT;
2134         }
2135
2136         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2137                            0, &card);
2138         if (err < 0) {
2139                 dev_err(&pci->dev, "Error creating card!\n");
2140                 return err;
2141         }
2142
2143         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2144         if (err < 0)
2145                 goto out_free;
2146         card->private_data = chip;
2147         hda = container_of(chip, struct hda_intel, chip);
2148
2149         /*
2150          * stop probe if digital microphones detected on Skylake+ platform
2151          * with the DSP enabled. This is an opt-in behavior defined at build
2152          * time or at run-time with a module parameter
2153          */
2154         if (dmic_detect) {
2155                 err = azx_check_dmic(pci, chip);
2156                 if (err < 0)
2157                         goto out_free;
2158         }
2159
2160         pci_set_drvdata(pci, card);
2161
2162         err = register_vga_switcheroo(chip);
2163         if (err < 0) {
2164                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2165                 goto out_free;
2166         }
2167
2168         if (check_hdmi_disabled(pci)) {
2169                 dev_info(card->dev, "VGA controller is disabled\n");
2170                 dev_info(card->dev, "Delaying initialization\n");
2171                 chip->disabled = true;
2172         }
2173
2174         schedule_probe = !chip->disabled;
2175
2176 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2177         if (patch[dev] && *patch[dev]) {
2178                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2179                          patch[dev]);
2180                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2181                                               &pci->dev, GFP_KERNEL, card,
2182                                               azx_firmware_cb);
2183                 if (err < 0)
2184                         goto out_free;
2185                 schedule_probe = false; /* continued in azx_firmware_cb() */
2186         }
2187 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2188
2189 #ifndef CONFIG_SND_HDA_I915
2190         if (CONTROLLER_IN_GPU(pci))
2191                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2192 #endif
2193
2194         if (schedule_probe)
2195                 schedule_work(&hda->probe_work);
2196
2197         dev++;
2198         if (chip->disabled)
2199                 complete_all(&hda->probe_wait);
2200         return 0;
2201
2202 out_free:
2203         snd_card_free(card);
2204         return err;
2205 }
2206
2207 #ifdef CONFIG_PM
2208 /* On some boards setting power_save to a non 0 value leads to clicking /
2209  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2210  * figure out how to avoid these sounds, but that is not always feasible.
2211  * So we keep a list of devices where we disable powersaving as its known
2212  * to causes problems on these devices.
2213  */
2214 static struct snd_pci_quirk power_save_blacklist[] = {
2215         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2216         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2217         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2218         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2219         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2220         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2221         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2222         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2223         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2224         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2225         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2226         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2227         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2228         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2229         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2230         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2231         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2232         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2233         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2234         /* https://bugs.launchpad.net/bugs/1821663 */
2235         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2236         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2237         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2238         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2239         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2240         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2241         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2242         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2243         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2244         /* https://bugs.launchpad.net/bugs/1821663 */
2245         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2246         {}
2247 };
2248 #endif /* CONFIG_PM */
2249
2250 static void set_default_power_save(struct azx *chip)
2251 {
2252         int val = power_save;
2253
2254 #ifdef CONFIG_PM
2255         if (pm_blacklist) {
2256                 const struct snd_pci_quirk *q;
2257
2258                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2259                 if (q && val) {
2260                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2261                                  q->subvendor, q->subdevice);
2262                         val = 0;
2263                 }
2264         }
2265 #endif /* CONFIG_PM */
2266         snd_hda_set_power_save(&chip->bus, val * 1000);
2267 }
2268
2269 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2270 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2271         [AZX_DRIVER_NVIDIA] = 8,
2272         [AZX_DRIVER_TERA] = 1,
2273 };
2274
2275 static int azx_probe_continue(struct azx *chip)
2276 {
2277         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2278         struct hdac_bus *bus = azx_bus(chip);
2279         struct pci_dev *pci = chip->pci;
2280         int dev = chip->dev_index;
2281         int err;
2282
2283         to_hda_bus(bus)->bus_probing = 1;
2284         hda->probe_continued = 1;
2285
2286         /* bind with i915 if needed */
2287         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2288                 err = snd_hdac_i915_init(bus);
2289                 if (err < 0) {
2290                         /* if the controller is bound only with HDMI/DP
2291                          * (for HSW and BDW), we need to abort the probe;
2292                          * for other chips, still continue probing as other
2293                          * codecs can be on the same link.
2294                          */
2295                         if (CONTROLLER_IN_GPU(pci)) {
2296                                 dev_err(chip->card->dev,
2297                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2298                                 goto out_free;
2299                         } else {
2300                                 /* don't bother any longer */
2301                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2302                         }
2303                 }
2304
2305                 /* HSW/BDW controllers need this power */
2306                 if (CONTROLLER_IN_GPU(pci))
2307                         hda->need_i915_power = 1;
2308         }
2309
2310         /* Request display power well for the HDA controller or codec. For
2311          * Haswell/Broadwell, both the display HDA controller and codec need
2312          * this power. For other platforms, like Baytrail/Braswell, only the
2313          * display codec needs the power and it can be released after probe.
2314          */
2315         display_power(chip, true);
2316
2317         err = azx_first_init(chip);
2318         if (err < 0)
2319                 goto out_free;
2320
2321 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2322         chip->beep_mode = beep_mode[dev];
2323 #endif
2324
2325         /* create codec instances */
2326         if (bus->codec_mask) {
2327                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2328                 if (err < 0)
2329                         goto out_free;
2330         }
2331
2332 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2333         if (chip->fw) {
2334                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2335                                          chip->fw->data);
2336                 if (err < 0)
2337                         goto out_free;
2338 #ifndef CONFIG_PM
2339                 release_firmware(chip->fw); /* no longer needed */
2340                 chip->fw = NULL;
2341 #endif
2342         }
2343 #endif
2344         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2345                 err = azx_codec_configure(chip);
2346                 if (err < 0)
2347                         goto out_free;
2348         }
2349
2350         err = snd_card_register(chip->card);
2351         if (err < 0)
2352                 goto out_free;
2353
2354         setup_vga_switcheroo_runtime_pm(chip);
2355
2356         chip->running = 1;
2357         azx_add_card_list(chip);
2358
2359         set_default_power_save(chip);
2360
2361         if (azx_has_pm_runtime(chip)) {
2362                 pm_runtime_use_autosuspend(&pci->dev);
2363                 pm_runtime_allow(&pci->dev);
2364                 pm_runtime_put_autosuspend(&pci->dev);
2365         }
2366
2367 out_free:
2368         if (err < 0) {
2369                 azx_free(chip);
2370                 return err;
2371         }
2372
2373         if (!hda->need_i915_power)
2374                 display_power(chip, false);
2375         complete_all(&hda->probe_wait);
2376         to_hda_bus(bus)->bus_probing = 0;
2377         return 0;
2378 }
2379
2380 static void azx_remove(struct pci_dev *pci)
2381 {
2382         struct snd_card *card = pci_get_drvdata(pci);
2383         struct azx *chip;
2384         struct hda_intel *hda;
2385
2386         if (card) {
2387                 /* cancel the pending probing work */
2388                 chip = card->private_data;
2389                 hda = container_of(chip, struct hda_intel, chip);
2390                 /* FIXME: below is an ugly workaround.
2391                  * Both device_release_driver() and driver_probe_device()
2392                  * take *both* the device's and its parent's lock before
2393                  * calling the remove() and probe() callbacks.  The codec
2394                  * probe takes the locks of both the codec itself and its
2395                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2396                  * the PCI controller is unbound, it takes its lock, too
2397                  * ==> ouch, a deadlock!
2398                  * As a workaround, we unlock temporarily here the controller
2399                  * device during cancel_work_sync() call.
2400                  */
2401                 device_unlock(&pci->dev);
2402                 cancel_work_sync(&hda->probe_work);
2403                 device_lock(&pci->dev);
2404
2405                 snd_card_free(card);
2406         }
2407 }
2408
2409 static void azx_shutdown(struct pci_dev *pci)
2410 {
2411         struct snd_card *card = pci_get_drvdata(pci);
2412         struct azx *chip;
2413
2414         if (!card)
2415                 return;
2416         chip = card->private_data;
2417         if (chip && chip->running)
2418                 azx_stop_chip(chip);
2419 }
2420
2421 /* PCI IDs */
2422 static const struct pci_device_id azx_ids[] = {
2423         /* CPT */
2424         { PCI_DEVICE(0x8086, 0x1c20),
2425           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2426         /* PBG */
2427         { PCI_DEVICE(0x8086, 0x1d20),
2428           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2429         /* Panther Point */
2430         { PCI_DEVICE(0x8086, 0x1e20),
2431           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2432         /* Lynx Point */
2433         { PCI_DEVICE(0x8086, 0x8c20),
2434           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2435         /* 9 Series */
2436         { PCI_DEVICE(0x8086, 0x8ca0),
2437           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2438         /* Wellsburg */
2439         { PCI_DEVICE(0x8086, 0x8d20),
2440           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2441         { PCI_DEVICE(0x8086, 0x8d21),
2442           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2443         /* Lewisburg */
2444         { PCI_DEVICE(0x8086, 0xa1f0),
2445           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2446         { PCI_DEVICE(0x8086, 0xa270),
2447           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2448         /* Lynx Point-LP */
2449         { PCI_DEVICE(0x8086, 0x9c20),
2450           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2451         /* Lynx Point-LP */
2452         { PCI_DEVICE(0x8086, 0x9c21),
2453           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2454         /* Wildcat Point-LP */
2455         { PCI_DEVICE(0x8086, 0x9ca0),
2456           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2457         /* Sunrise Point */
2458         { PCI_DEVICE(0x8086, 0xa170),
2459           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2460         /* Sunrise Point-LP */
2461         { PCI_DEVICE(0x8086, 0x9d70),
2462           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2463         /* Kabylake */
2464         { PCI_DEVICE(0x8086, 0xa171),
2465           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2466         /* Kabylake-LP */
2467         { PCI_DEVICE(0x8086, 0x9d71),
2468           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2469         /* Kabylake-H */
2470         { PCI_DEVICE(0x8086, 0xa2f0),
2471           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2472         /* Coffelake */
2473         { PCI_DEVICE(0x8086, 0xa348),
2474           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2475         /* Cannonlake */
2476         { PCI_DEVICE(0x8086, 0x9dc8),
2477           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478         /* CometLake-LP */
2479         { PCI_DEVICE(0x8086, 0x02C8),
2480           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2481         /* CometLake-H */
2482         { PCI_DEVICE(0x8086, 0x06C8),
2483           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2484         { PCI_DEVICE(0x8086, 0xf1c8),
2485           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2486         /* CometLake-S */
2487         { PCI_DEVICE(0x8086, 0xa3f0),
2488           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2489         /* CometLake-R */
2490         { PCI_DEVICE(0x8086, 0xf0c8),
2491           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2492         /* Icelake */
2493         { PCI_DEVICE(0x8086, 0x34c8),
2494           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2495         /* Icelake-H */
2496         { PCI_DEVICE(0x8086, 0x3dc8),
2497           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2498         /* Jasperlake */
2499         { PCI_DEVICE(0x8086, 0x38c8),
2500           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2501         { PCI_DEVICE(0x8086, 0x4dc8),
2502           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2503         /* Tigerlake */
2504         { PCI_DEVICE(0x8086, 0xa0c8),
2505           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2506         /* Tigerlake-H */
2507         { PCI_DEVICE(0x8086, 0x43c8),
2508           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2509         /* DG1 */
2510         { PCI_DEVICE(0x8086, 0x490d),
2511           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2512         /* DG2 */
2513         { PCI_DEVICE(0x8086, 0x4f90),
2514           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2515         { PCI_DEVICE(0x8086, 0x4f91),
2516           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2517         { PCI_DEVICE(0x8086, 0x4f92),
2518           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2519         /* Alderlake-S */
2520         { PCI_DEVICE(0x8086, 0x7ad0),
2521           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2522         /* Elkhart Lake */
2523         { PCI_DEVICE(0x8086, 0x4b55),
2524           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2525         { PCI_DEVICE(0x8086, 0x4b58),
2526           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2527         /* Broxton-P(Apollolake) */
2528         { PCI_DEVICE(0x8086, 0x5a98),
2529           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2530         /* Broxton-T */
2531         { PCI_DEVICE(0x8086, 0x1a98),
2532           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2533         /* Gemini-Lake */
2534         { PCI_DEVICE(0x8086, 0x3198),
2535           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2536         /* Haswell */
2537         { PCI_DEVICE(0x8086, 0x0a0c),
2538           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2539         { PCI_DEVICE(0x8086, 0x0c0c),
2540           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2541         { PCI_DEVICE(0x8086, 0x0d0c),
2542           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2543         /* Broadwell */
2544         { PCI_DEVICE(0x8086, 0x160c),
2545           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2546         /* 5 Series/3400 */
2547         { PCI_DEVICE(0x8086, 0x3b56),
2548           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2549         { PCI_DEVICE(0x8086, 0x3b57),
2550           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2551         /* Poulsbo */
2552         { PCI_DEVICE(0x8086, 0x811b),
2553           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2554           AZX_DCAPS_POSFIX_LPIB },
2555         /* Oaktrail */
2556         { PCI_DEVICE(0x8086, 0x080a),
2557           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2558         /* BayTrail */
2559         { PCI_DEVICE(0x8086, 0x0f04),
2560           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2561         /* Braswell */
2562         { PCI_DEVICE(0x8086, 0x2284),
2563           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2564         /* ICH6 */
2565         { PCI_DEVICE(0x8086, 0x2668),
2566           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2567         /* ICH7 */
2568         { PCI_DEVICE(0x8086, 0x27d8),
2569           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2570         /* ESB2 */
2571         { PCI_DEVICE(0x8086, 0x269a),
2572           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2573         /* ICH8 */
2574         { PCI_DEVICE(0x8086, 0x284b),
2575           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2576         /* ICH9 */
2577         { PCI_DEVICE(0x8086, 0x293e),
2578           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2579         /* ICH9 */
2580         { PCI_DEVICE(0x8086, 0x293f),
2581           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2582         /* ICH10 */
2583         { PCI_DEVICE(0x8086, 0x3a3e),
2584           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2585         /* ICH10 */
2586         { PCI_DEVICE(0x8086, 0x3a6e),
2587           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2588         /* Generic Intel */
2589         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2590           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2591           .class_mask = 0xffffff,
2592           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2593         /* ATI SB 450/600/700/800/900 */
2594         { PCI_DEVICE(0x1002, 0x437b),
2595           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2596         { PCI_DEVICE(0x1002, 0x4383),
2597           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2598         /* AMD Hudson */
2599         { PCI_DEVICE(0x1022, 0x780d),
2600           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2601         /* AMD, X370 & co */
2602         { PCI_DEVICE(0x1022, 0x1457),
2603           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2604         /* AMD, X570 & co */
2605         { PCI_DEVICE(0x1022, 0x1487),
2606           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2607         /* AMD Stoney */
2608         { PCI_DEVICE(0x1022, 0x157a),
2609           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2610                          AZX_DCAPS_PM_RUNTIME },
2611         /* AMD Raven */
2612         { PCI_DEVICE(0x1022, 0x15e3),
2613           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2614         /* ATI HDMI */
2615         { PCI_DEVICE(0x1002, 0x0002),
2616           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2617         { PCI_DEVICE(0x1002, 0x1308),
2618           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2619         { PCI_DEVICE(0x1002, 0x157a),
2620           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2621         { PCI_DEVICE(0x1002, 0x15b3),
2622           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2623         { PCI_DEVICE(0x1002, 0x793b),
2624           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(0x1002, 0x7919),
2626           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627         { PCI_DEVICE(0x1002, 0x960f),
2628           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629         { PCI_DEVICE(0x1002, 0x970f),
2630           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631         { PCI_DEVICE(0x1002, 0x9840),
2632           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2633         { PCI_DEVICE(0x1002, 0xaa00),
2634           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635         { PCI_DEVICE(0x1002, 0xaa08),
2636           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637         { PCI_DEVICE(0x1002, 0xaa10),
2638           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639         { PCI_DEVICE(0x1002, 0xaa18),
2640           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641         { PCI_DEVICE(0x1002, 0xaa20),
2642           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643         { PCI_DEVICE(0x1002, 0xaa28),
2644           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645         { PCI_DEVICE(0x1002, 0xaa30),
2646           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647         { PCI_DEVICE(0x1002, 0xaa38),
2648           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649         { PCI_DEVICE(0x1002, 0xaa40),
2650           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651         { PCI_DEVICE(0x1002, 0xaa48),
2652           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653         { PCI_DEVICE(0x1002, 0xaa50),
2654           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655         { PCI_DEVICE(0x1002, 0xaa58),
2656           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657         { PCI_DEVICE(0x1002, 0xaa60),
2658           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659         { PCI_DEVICE(0x1002, 0xaa68),
2660           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661         { PCI_DEVICE(0x1002, 0xaa80),
2662           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663         { PCI_DEVICE(0x1002, 0xaa88),
2664           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665         { PCI_DEVICE(0x1002, 0xaa90),
2666           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667         { PCI_DEVICE(0x1002, 0xaa98),
2668           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669         { PCI_DEVICE(0x1002, 0x9902),
2670           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2671         { PCI_DEVICE(0x1002, 0xaaa0),
2672           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2673         { PCI_DEVICE(0x1002, 0xaaa8),
2674           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2675         { PCI_DEVICE(0x1002, 0xaab0),
2676           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2677         { PCI_DEVICE(0x1002, 0xaac0),
2678           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2679         { PCI_DEVICE(0x1002, 0xaac8),
2680           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2681         { PCI_DEVICE(0x1002, 0xaad8),
2682           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2683         { PCI_DEVICE(0x1002, 0xaae8),
2684           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2685         { PCI_DEVICE(0x1002, 0xaae0),
2686           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2687         { PCI_DEVICE(0x1002, 0xaaf0),
2688           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2689         /* VIA VT8251/VT8237A */
2690         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2691         /* VIA GFX VT7122/VX900 */
2692         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2693         /* VIA GFX VT6122/VX11 */
2694         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2695         /* SIS966 */
2696         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2697         /* ULI M5461 */
2698         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2699         /* NVIDIA MCP */
2700         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2701           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2702           .class_mask = 0xffffff,
2703           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2704         /* Teradici */
2705         { PCI_DEVICE(0x6549, 0x1200),
2706           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2707         { PCI_DEVICE(0x6549, 0x2200),
2708           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2709         /* Creative X-Fi (CA0110-IBG) */
2710         /* CTHDA chips */
2711         { PCI_DEVICE(0x1102, 0x0010),
2712           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2713         { PCI_DEVICE(0x1102, 0x0012),
2714           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2715 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2716         /* the following entry conflicts with snd-ctxfi driver,
2717          * as ctxfi driver mutates from HD-audio to native mode with
2718          * a special command sequence.
2719          */
2720         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2721           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2722           .class_mask = 0xffffff,
2723           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2724           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2725 #else
2726         /* this entry seems still valid -- i.e. without emu20kx chip */
2727         { PCI_DEVICE(0x1102, 0x0009),
2728           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2729           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2730 #endif
2731         /* CM8888 */
2732         { PCI_DEVICE(0x13f6, 0x5011),
2733           .driver_data = AZX_DRIVER_CMEDIA |
2734           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2735         /* Vortex86MX */
2736         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2737         /* VMware HDAudio */
2738         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2739         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2740         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2741           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2742           .class_mask = 0xffffff,
2743           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2744         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2745           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2746           .class_mask = 0xffffff,
2747           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2748         /* Zhaoxin */
2749         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2750         { 0, }
2751 };
2752 MODULE_DEVICE_TABLE(pci, azx_ids);
2753
2754 /* pci_driver definition */
2755 static struct pci_driver azx_driver = {
2756         .name = KBUILD_MODNAME,
2757         .id_table = azx_ids,
2758         .probe = azx_probe,
2759         .remove = azx_remove,
2760         .shutdown = azx_shutdown,
2761         .driver = {
2762                 .pm = AZX_PM_OPS,
2763         },
2764 };
2765
2766 module_pci_driver(azx_driver);