3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/set_memory.h>
57 #include <asm/cpufeature.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
73 /* position fix mode */
84 /* Defines for ATI HD Audio support in SB450 south bridge */
85 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
86 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
88 /* Defines for Nvidia HDA support */
89 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
90 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
91 #define NVIDIA_HDA_ISTRM_COH 0x4d
92 #define NVIDIA_HDA_OSTRM_COH 0x4c
93 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
95 /* Defines for Intel SCH HDA snoop control */
96 #define INTEL_HDA_CGCTL 0x48
97 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
98 #define INTEL_SCH_HDA_DEVC 0x78
99 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
101 /* Define IN stream 0 FIFO size offset in VIA controller */
102 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
103 /* Define VIA HD Audio Device ID*/
104 #define VIA_HDAC_DEVICE_ID 0x3288
106 /* max number of SDs */
107 /* ICH, ATI and VIA have 4 playback and 4 capture */
108 #define ICH6_NUM_CAPTURE 4
109 #define ICH6_NUM_PLAYBACK 4
111 /* ULI has 6 playback and 5 capture */
112 #define ULI_NUM_CAPTURE 5
113 #define ULI_NUM_PLAYBACK 6
115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
116 #define ATIHDMI_NUM_CAPTURE 0
117 #define ATIHDMI_NUM_PLAYBACK 8
119 /* TERA has 4 playback and 3 capture */
120 #define TERA_NUM_CAPTURE 3
121 #define TERA_NUM_PLAYBACK 4
124 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
125 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
126 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
127 static char *model[SNDRV_CARDS];
128 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
130 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
131 static int probe_only[SNDRV_CARDS];
132 static int jackpoll_ms[SNDRV_CARDS];
133 static int single_cmd = -1;
134 static int enable_msi = -1;
135 #ifdef CONFIG_SND_HDA_PATCH_LOADER
136 static char *patch[SNDRV_CARDS];
138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
139 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
140 CONFIG_SND_HDA_INPUT_BEEP_MODE};
143 module_param_array(index, int, NULL, 0444);
144 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
145 module_param_array(id, charp, NULL, 0444);
146 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
147 module_param_array(enable, bool, NULL, 0444);
148 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
149 module_param_array(model, charp, NULL, 0444);
150 MODULE_PARM_DESC(model, "Use the given board model.");
151 module_param_array(position_fix, int, NULL, 0444);
152 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
153 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
154 module_param_array(bdl_pos_adj, int, NULL, 0644);
155 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
156 module_param_array(probe_mask, int, NULL, 0444);
157 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
158 module_param_array(probe_only, int, NULL, 0444);
159 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
160 module_param_array(jackpoll_ms, int, NULL, 0444);
161 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
162 module_param(single_cmd, bint, 0444);
163 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
164 "(for debugging only).");
165 module_param(enable_msi, bint, 0444);
166 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
167 #ifdef CONFIG_SND_HDA_PATCH_LOADER
168 module_param_array(patch, charp, NULL, 0444);
169 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
171 #ifdef CONFIG_SND_HDA_INPUT_BEEP
172 module_param_array(beep_mode, bool, NULL, 0444);
173 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
174 "(0=off, 1=on) (default=1).");
178 static int param_set_xint(const char *val, const struct kernel_param *kp);
179 static const struct kernel_param_ops param_ops_xint = {
180 .set = param_set_xint,
181 .get = param_get_int,
183 #define param_check_xint param_check_int
185 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
186 module_param(power_save, xint, 0644);
187 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
188 "(in second, 0 = disable).");
190 static bool pm_blacklist = true;
191 module_param(pm_blacklist, bool, 0644);
192 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
194 /* reset the HD-audio controller in power save mode.
195 * this may give more power-saving, but will take longer time to
198 static bool power_save_controller = 1;
199 module_param(power_save_controller, bool, 0644);
200 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
203 #endif /* CONFIG_PM */
205 static int align_buffer_size = -1;
206 module_param(align_buffer_size, bint, 0644);
207 MODULE_PARM_DESC(align_buffer_size,
208 "Force buffer and period sizes to be multiple of 128 bytes.");
211 static int hda_snoop = -1;
212 module_param_named(snoop, hda_snoop, bint, 0444);
213 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
215 #define hda_snoop true
219 MODULE_LICENSE("GPL");
220 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
254 MODULE_DESCRIPTION("Intel HDA driver");
256 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
257 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
258 #define SUPPORT_VGA_SWITCHEROO
275 AZX_DRIVER_ATIHDMI_NS,
285 AZX_NUM_DRIVERS, /* keep this as last entry */
288 #define azx_get_snoop_type(chip) \
289 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
290 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
292 /* quirks for old Intel chipsets */
293 #define AZX_DCAPS_INTEL_ICH \
294 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
296 /* quirks for Intel PCH */
297 #define AZX_DCAPS_INTEL_PCH_BASE \
298 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
299 AZX_DCAPS_SNOOP_TYPE(SCH))
301 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
302 #define AZX_DCAPS_INTEL_PCH_NOPM \
303 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
305 /* PCH for HSW/BDW; with runtime PM */
306 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
307 #define AZX_DCAPS_INTEL_PCH \
308 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
311 #define AZX_DCAPS_INTEL_HASWELL \
312 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
313 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
314 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
316 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
317 #define AZX_DCAPS_INTEL_BROADWELL \
318 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
319 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
320 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
322 #define AZX_DCAPS_INTEL_BAYTRAIL \
323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
324 AZX_DCAPS_I915_POWERWELL)
326 #define AZX_DCAPS_INTEL_BRASWELL \
327 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
328 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
330 #define AZX_DCAPS_INTEL_SKYLAKE \
331 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
332 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
333 AZX_DCAPS_I915_POWERWELL)
335 #define AZX_DCAPS_INTEL_BROXTON \
336 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
337 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
338 AZX_DCAPS_I915_POWERWELL)
340 /* quirks for ATI SB / AMD Hudson */
341 #define AZX_DCAPS_PRESET_ATI_SB \
342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
343 AZX_DCAPS_SNOOP_TYPE(ATI))
345 /* quirks for ATI/AMD HDMI */
346 #define AZX_DCAPS_PRESET_ATI_HDMI \
347 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
350 /* quirks for ATI HDMI with snoop off */
351 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
352 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
354 /* quirks for AMD SB */
355 #define AZX_DCAPS_PRESET_AMD_SB \
356 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
357 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
359 /* quirks for Nvidia */
360 #define AZX_DCAPS_PRESET_NVIDIA \
361 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
362 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
364 #define AZX_DCAPS_PRESET_CTHDA \
365 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
366 AZX_DCAPS_NO_64BIT |\
367 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
370 * vga_switcheroo support
372 #ifdef SUPPORT_VGA_SWITCHEROO
373 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
375 #define use_vga_switcheroo(chip) 0
378 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
379 ((pci)->device == 0x0c0c) || \
380 ((pci)->device == 0x0d0c) || \
381 ((pci)->device == 0x160c))
383 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
384 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
385 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
387 static char *driver_short_names[] = {
388 [AZX_DRIVER_ICH] = "HDA Intel",
389 [AZX_DRIVER_PCH] = "HDA Intel PCH",
390 [AZX_DRIVER_SCH] = "HDA Intel MID",
391 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
392 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
393 [AZX_DRIVER_ATI] = "HDA ATI SB",
394 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
395 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
396 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
397 [AZX_DRIVER_SIS] = "HDA SIS966",
398 [AZX_DRIVER_ULI] = "HDA ULI M5461",
399 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
400 [AZX_DRIVER_TERA] = "HDA Teradici",
401 [AZX_DRIVER_CTX] = "HDA Creative",
402 [AZX_DRIVER_CTHDA] = "HDA Creative",
403 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
404 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
408 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
414 if (!dmab || !dmab->area || !dmab->bytes)
417 #ifdef CONFIG_SND_DMA_SGBUF
418 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
419 struct snd_sg_buf *sgbuf = dmab->private_data;
420 if (!chip->uc_buffer)
421 return; /* deal with only CORB/RIRB buffers */
423 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
425 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
430 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
432 set_memory_wc((unsigned long)dmab->area, pages);
434 set_memory_wb((unsigned long)dmab->area, pages);
437 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
440 __mark_pages_wc(chip, buf, on);
442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
443 struct snd_pcm_substream *substream, bool on)
445 if (azx_dev->wc_marked != on) {
446 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
447 azx_dev->wc_marked = on;
451 /* NOP for other archs */
452 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
456 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
457 struct snd_pcm_substream *substream, bool on)
462 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
465 * initialize the PCI registers
467 /* update bits in a PCI register byte */
468 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
469 unsigned char mask, unsigned char val)
473 pci_read_config_byte(pci, reg, &data);
475 data |= (val & mask);
476 pci_write_config_byte(pci, reg, data);
479 static void azx_init_pci(struct azx *chip)
481 int snoop_type = azx_get_snoop_type(chip);
483 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
484 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
485 * Ensuring these bits are 0 clears playback static on some HD Audio
487 * The PCI register TCSEL is defined in the Intel manuals.
489 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
490 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
491 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
494 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
495 * we need to enable snoop.
497 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
498 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
500 update_pci_byte(chip->pci,
501 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
502 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
505 /* For NVIDIA HDA, enable snoop */
506 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
507 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
509 update_pci_byte(chip->pci,
510 NVIDIA_HDA_TRANSREG_ADDR,
511 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
512 update_pci_byte(chip->pci,
513 NVIDIA_HDA_ISTRM_COH,
514 0x01, NVIDIA_HDA_ENABLE_COHBIT);
515 update_pci_byte(chip->pci,
516 NVIDIA_HDA_OSTRM_COH,
517 0x01, NVIDIA_HDA_ENABLE_COHBIT);
520 /* Enable SCH/PCH snoop if needed */
521 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
522 unsigned short snoop;
523 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
524 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
525 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
526 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
527 if (!azx_snoop(chip))
528 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
529 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
530 pci_read_config_word(chip->pci,
531 INTEL_SCH_HDA_DEVC, &snoop);
533 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
534 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
535 "Disabled" : "Enabled");
540 * In BXT-P A0, HD-Audio DMA requests is later than expected,
541 * and makes an audio stream sensitive to system latencies when
542 * 24/32 bits are playing.
543 * Adjusting threshold of DMA fifo to force the DMA request
544 * sooner to improve latency tolerance at the expense of power.
546 static void bxt_reduce_dma_latency(struct azx *chip)
550 val = azx_readl(chip, VS_EM4L);
552 azx_writel(chip, VS_EM4L, val);
557 * bit 0: 6 MHz Supported
558 * bit 1: 12 MHz Supported
559 * bit 2: 24 MHz Supported
560 * bit 3: 48 MHz Supported
561 * bit 4: 96 MHz Supported
562 * bit 5: 192 MHz Supported
564 static int intel_get_lctl_scf(struct azx *chip)
566 struct hdac_bus *bus = azx_bus(chip);
567 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
571 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
573 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
574 t = preferred_bits[i];
579 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
583 static int intel_ml_lctl_set_power(struct azx *chip, int state)
585 struct hdac_bus *bus = azx_bus(chip);
590 * the codecs are sharing the first link setting by default
591 * If other links are enabled for stream, they need similar fix
593 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
594 val &= ~AZX_MLCTL_SPA;
595 val |= state << AZX_MLCTL_SPA_SHIFT;
596 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
600 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
601 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
610 static void intel_init_lctl(struct azx *chip)
612 struct hdac_bus *bus = azx_bus(chip);
616 /* 0. check lctl register value is correct or not */
617 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
618 /* if SCF is already set, let's use it */
619 if ((val & ML_LCTL_SCF_MASK) != 0)
623 * Before operating on SPA, CPA must match SPA.
624 * Any deviation may result in undefined behavior.
626 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
627 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
630 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
631 ret = intel_ml_lctl_set_power(chip, 0);
636 /* 2. update SCF to select a properly audio clock*/
637 val &= ~ML_LCTL_SCF_MASK;
638 val |= intel_get_lctl_scf(chip);
639 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
642 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
643 intel_ml_lctl_set_power(chip, 1);
647 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
649 struct hdac_bus *bus = azx_bus(chip);
650 struct pci_dev *pci = chip->pci;
653 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
654 snd_hdac_set_codec_wakeup(bus, true);
655 if (chip->driver_type == AZX_DRIVER_SKL) {
656 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
657 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
658 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
660 azx_init_chip(chip, full_reset);
661 if (chip->driver_type == AZX_DRIVER_SKL) {
662 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
663 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
664 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
666 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
667 snd_hdac_set_codec_wakeup(bus, false);
669 /* reduce dma latency to avoid noise */
671 bxt_reduce_dma_latency(chip);
673 if (bus->mlcap != NULL)
674 intel_init_lctl(chip);
677 /* calculate runtime delay from LPIB */
678 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
681 struct snd_pcm_substream *substream = azx_dev->core.substream;
682 int stream = substream->stream;
683 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
686 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
687 delay = pos - lpib_pos;
689 delay = lpib_pos - pos;
691 if (delay >= azx_dev->core.delay_negative_threshold)
694 delay += azx_dev->core.bufsize;
697 if (delay >= azx_dev->core.period_bytes) {
698 dev_info(chip->card->dev,
699 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
700 delay, azx_dev->core.period_bytes);
702 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
703 chip->get_delay[stream] = NULL;
706 return bytes_to_frames(substream->runtime, delay);
709 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
711 /* called from IRQ */
712 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
714 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
717 ok = azx_position_ok(chip, azx_dev);
719 azx_dev->irq_pending = 0;
721 } else if (ok == 0) {
722 /* bogus IRQ, process it later */
723 azx_dev->irq_pending = 1;
724 schedule_work(&hda->irq_pending_work);
729 /* Enable/disable i915 display power for the link */
730 static int azx_intel_link_power(struct azx *chip, bool enable)
732 struct hdac_bus *bus = azx_bus(chip);
734 return snd_hdac_display_power(bus, enable);
738 * Check whether the current DMA position is acceptable for updating
739 * periods. Returns non-zero if it's OK.
741 * Many HD-audio controllers appear pretty inaccurate about
742 * the update-IRQ timing. The IRQ is issued before actually the
743 * data is processed. So, we need to process it afterwords in a
746 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
748 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
750 struct snd_pcm_substream *substream = azx_dev->core.substream;
751 struct snd_pcm_runtime *runtime = substream->runtime;
752 int stream = substream->stream;
755 snd_pcm_uframes_t hwptr, target;
757 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
758 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
759 return -1; /* bogus (too early) interrupt */
761 if (chip->get_position[stream])
762 pos = chip->get_position[stream](chip, azx_dev);
763 else { /* use the position buffer as default */
764 pos = azx_get_pos_posbuf(chip, azx_dev);
765 if (!pos || pos == (u32)-1) {
766 dev_info(chip->card->dev,
767 "Invalid position buffer, using LPIB read method instead.\n");
768 chip->get_position[stream] = azx_get_pos_lpib;
769 if (chip->get_position[0] == azx_get_pos_lpib &&
770 chip->get_position[1] == azx_get_pos_lpib)
771 azx_bus(chip)->use_posbuf = false;
772 pos = azx_get_pos_lpib(chip, azx_dev);
773 chip->get_delay[stream] = NULL;
775 chip->get_position[stream] = azx_get_pos_posbuf;
776 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
777 chip->get_delay[stream] = azx_get_delay_from_lpib;
781 if (pos >= azx_dev->core.bufsize)
784 if (WARN_ONCE(!azx_dev->core.period_bytes,
785 "hda-intel: zero azx_dev->period_bytes"))
786 return -1; /* this shouldn't happen! */
787 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
788 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
789 /* NG - it's below the first next period boundary */
790 return chip->bdl_pos_adj ? 0 : -1;
791 azx_dev->core.start_wallclk += wallclk;
793 if (azx_dev->core.no_period_wakeup)
794 return 1; /* OK, no need to check period boundary */
796 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
797 return 1; /* OK, already in hwptr updating process */
799 /* check whether the period gets really elapsed */
800 pos = bytes_to_frames(runtime, pos);
801 hwptr = runtime->hw_ptr_base + pos;
802 if (hwptr < runtime->status->hw_ptr)
803 hwptr += runtime->buffer_size;
804 target = runtime->hw_ptr_interrupt + runtime->period_size;
805 if (hwptr < target) {
806 /* too early wakeup, process it later */
807 return chip->bdl_pos_adj ? 0 : -1;
810 return 1; /* OK, it's fine */
814 * The work for pending PCM period updates.
816 static void azx_irq_pending_work(struct work_struct *work)
818 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
819 struct azx *chip = &hda->chip;
820 struct hdac_bus *bus = azx_bus(chip);
821 struct hdac_stream *s;
824 if (!hda->irq_pending_warned) {
825 dev_info(chip->card->dev,
826 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
828 hda->irq_pending_warned = 1;
833 spin_lock_irq(&bus->reg_lock);
834 list_for_each_entry(s, &bus->stream_list, list) {
835 struct azx_dev *azx_dev = stream_to_azx_dev(s);
836 if (!azx_dev->irq_pending ||
840 ok = azx_position_ok(chip, azx_dev);
842 azx_dev->irq_pending = 0;
843 spin_unlock(&bus->reg_lock);
844 snd_pcm_period_elapsed(s->substream);
845 spin_lock(&bus->reg_lock);
847 pending = 0; /* too early */
851 spin_unlock_irq(&bus->reg_lock);
858 /* clear irq_pending flags and assure no on-going workq */
859 static void azx_clear_irq_pending(struct azx *chip)
861 struct hdac_bus *bus = azx_bus(chip);
862 struct hdac_stream *s;
864 spin_lock_irq(&bus->reg_lock);
865 list_for_each_entry(s, &bus->stream_list, list) {
866 struct azx_dev *azx_dev = stream_to_azx_dev(s);
867 azx_dev->irq_pending = 0;
869 spin_unlock_irq(&bus->reg_lock);
872 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
874 struct hdac_bus *bus = azx_bus(chip);
876 if (request_irq(chip->pci->irq, azx_interrupt,
877 chip->msi ? 0 : IRQF_SHARED,
878 chip->card->irq_descr, chip)) {
879 dev_err(chip->card->dev,
880 "unable to grab IRQ %d, disabling device\n",
883 snd_card_disconnect(chip->card);
886 bus->irq = chip->pci->irq;
887 pci_intx(chip->pci, !chip->msi);
891 /* get the current DMA position with correction on VIA chips */
892 static unsigned int azx_via_get_position(struct azx *chip,
893 struct azx_dev *azx_dev)
895 unsigned int link_pos, mini_pos, bound_pos;
896 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
897 unsigned int fifo_size;
899 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
900 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
901 /* Playback, no problem using link position */
907 * use mod to get the DMA position just like old chipset
909 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
910 mod_dma_pos %= azx_dev->core.period_bytes;
912 /* azx_dev->fifo_size can't get FIFO size of in stream.
913 * Get from base address + offset.
915 fifo_size = readw(azx_bus(chip)->remap_addr +
916 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
918 if (azx_dev->insufficient) {
919 /* Link position never gather than FIFO size */
920 if (link_pos <= fifo_size)
923 azx_dev->insufficient = 0;
926 if (link_pos <= fifo_size)
927 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
929 mini_pos = link_pos - fifo_size;
931 /* Find nearest previous boudary */
932 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
933 mod_link_pos = link_pos % azx_dev->core.period_bytes;
934 if (mod_link_pos >= fifo_size)
935 bound_pos = link_pos - mod_link_pos;
936 else if (mod_dma_pos >= mod_mini_pos)
937 bound_pos = mini_pos - mod_mini_pos;
939 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
940 if (bound_pos >= azx_dev->core.bufsize)
944 /* Calculate real DMA position we want */
945 return bound_pos + mod_dma_pos;
948 #define AMD_FIFO_SIZE 32
950 /* get the current DMA position with FIFO size correction */
951 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
953 struct snd_pcm_substream *substream = azx_dev->core.substream;
954 struct snd_pcm_runtime *runtime = substream->runtime;
955 unsigned int pos, delay;
957 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
961 runtime->delay = AMD_FIFO_SIZE;
962 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
963 if (azx_dev->insufficient) {
966 runtime->delay = bytes_to_frames(runtime, pos);
968 azx_dev->insufficient = 0;
972 /* correct the DMA position for capture stream */
973 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
975 pos += azx_dev->core.bufsize;
982 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
985 struct snd_pcm_substream *substream = azx_dev->core.substream;
987 /* just read back the calculated value in the above */
988 return substream->runtime->delay;
991 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
992 struct azx_dev *azx_dev)
994 return _snd_hdac_chip_readl(azx_bus(chip),
995 AZX_REG_VS_SDXDPIB_XBASE +
996 (AZX_REG_VS_SDXDPIB_XINTERVAL *
997 azx_dev->core.index));
1000 /* get the current DMA position with correction on SKL+ chips */
1001 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
1003 /* DPIB register gives a more accurate position for playback */
1004 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1005 return azx_skl_get_dpib_pos(chip, azx_dev);
1007 /* read of DPIB fetches the actual posbuf */
1008 azx_skl_get_dpib_pos(chip, azx_dev);
1009 return azx_get_pos_posbuf(chip, azx_dev);
1013 static DEFINE_MUTEX(card_list_lock);
1014 static LIST_HEAD(card_list);
1016 static void azx_add_card_list(struct azx *chip)
1018 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1019 mutex_lock(&card_list_lock);
1020 list_add(&hda->list, &card_list);
1021 mutex_unlock(&card_list_lock);
1024 static void azx_del_card_list(struct azx *chip)
1026 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1027 mutex_lock(&card_list_lock);
1028 list_del_init(&hda->list);
1029 mutex_unlock(&card_list_lock);
1032 /* trigger power-save check at writing parameter */
1033 static int param_set_xint(const char *val, const struct kernel_param *kp)
1035 struct hda_intel *hda;
1037 int prev = power_save;
1038 int ret = param_set_int(val, kp);
1040 if (ret || prev == power_save)
1043 mutex_lock(&card_list_lock);
1044 list_for_each_entry(hda, &card_list, list) {
1046 if (!hda->probe_continued || chip->disabled)
1048 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1050 mutex_unlock(&card_list_lock);
1054 #define azx_add_card_list(chip) /* NOP */
1055 #define azx_del_card_list(chip) /* NOP */
1056 #endif /* CONFIG_PM */
1058 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
1062 static int azx_suspend(struct device *dev)
1064 struct snd_card *card = dev_get_drvdata(dev);
1066 struct hda_intel *hda;
1067 struct hdac_bus *bus;
1072 chip = card->private_data;
1073 hda = container_of(chip, struct hda_intel, chip);
1074 if (chip->disabled || hda->init_failed || !chip->running)
1077 bus = azx_bus(chip);
1078 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1079 azx_clear_irq_pending(chip);
1080 azx_stop_chip(chip);
1081 azx_enter_link_reset(chip);
1082 if (bus->irq >= 0) {
1083 free_irq(bus->irq, chip);
1088 pci_disable_msi(chip->pci);
1089 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1090 && hda->need_i915_power)
1091 snd_hdac_display_power(bus, false);
1093 trace_azx_suspend(chip);
1097 static int azx_resume(struct device *dev)
1099 struct pci_dev *pci = to_pci_dev(dev);
1100 struct snd_card *card = dev_get_drvdata(dev);
1102 struct hda_intel *hda;
1103 struct hdac_bus *bus;
1108 chip = card->private_data;
1109 hda = container_of(chip, struct hda_intel, chip);
1110 bus = azx_bus(chip);
1111 if (chip->disabled || hda->init_failed || !chip->running)
1114 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1115 snd_hdac_display_power(bus, true);
1116 if (hda->need_i915_power)
1117 snd_hdac_i915_set_bclk(bus);
1121 if (pci_enable_msi(pci) < 0)
1123 if (azx_acquire_irq(chip, 1) < 0)
1127 hda_intel_init_chip(chip, true);
1129 /* power down again for link-controlled chips */
1130 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1131 !hda->need_i915_power)
1132 snd_hdac_display_power(bus, false);
1134 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1136 trace_azx_resume(chip);
1139 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1141 #ifdef CONFIG_PM_SLEEP
1142 /* put codec down to D3 at hibernation for Intel SKL+;
1143 * otherwise BIOS may still access the codec and screw up the driver
1145 static int azx_freeze_noirq(struct device *dev)
1147 struct snd_card *card = dev_get_drvdata(dev);
1148 struct azx *chip = card->private_data;
1149 struct pci_dev *pci = to_pci_dev(dev);
1151 if (chip->driver_type == AZX_DRIVER_SKL)
1152 pci_set_power_state(pci, PCI_D3hot);
1157 static int azx_thaw_noirq(struct device *dev)
1159 struct snd_card *card = dev_get_drvdata(dev);
1160 struct azx *chip = card->private_data;
1161 struct pci_dev *pci = to_pci_dev(dev);
1163 if (chip->driver_type == AZX_DRIVER_SKL)
1164 pci_set_power_state(pci, PCI_D0);
1168 #endif /* CONFIG_PM_SLEEP */
1171 static int azx_runtime_suspend(struct device *dev)
1173 struct snd_card *card = dev_get_drvdata(dev);
1175 struct hda_intel *hda;
1180 chip = card->private_data;
1181 hda = container_of(chip, struct hda_intel, chip);
1182 if (chip->disabled || hda->init_failed)
1185 if (!azx_has_pm_runtime(chip))
1188 /* enable controller wake up event */
1189 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1192 azx_stop_chip(chip);
1193 azx_enter_link_reset(chip);
1194 azx_clear_irq_pending(chip);
1195 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1196 && hda->need_i915_power)
1197 snd_hdac_display_power(azx_bus(chip), false);
1199 trace_azx_runtime_suspend(chip);
1203 static int azx_runtime_resume(struct device *dev)
1205 struct snd_card *card = dev_get_drvdata(dev);
1207 struct hda_intel *hda;
1208 struct hdac_bus *bus;
1209 struct hda_codec *codec;
1215 chip = card->private_data;
1216 hda = container_of(chip, struct hda_intel, chip);
1217 bus = azx_bus(chip);
1218 if (chip->disabled || hda->init_failed)
1221 if (!azx_has_pm_runtime(chip))
1224 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1225 snd_hdac_display_power(bus, true);
1226 if (hda->need_i915_power)
1227 snd_hdac_i915_set_bclk(bus);
1230 /* Read STATESTS before controller reset */
1231 status = azx_readw(chip, STATESTS);
1234 hda_intel_init_chip(chip, true);
1237 list_for_each_codec(codec, &chip->bus)
1238 if (status & (1 << codec->addr))
1239 schedule_delayed_work(&codec->jackpoll_work,
1240 codec->jackpoll_interval);
1243 /* disable controller Wake Up event*/
1244 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1245 ~STATESTS_INT_MASK);
1247 /* power down again for link-controlled chips */
1248 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1249 !hda->need_i915_power)
1250 snd_hdac_display_power(bus, false);
1252 trace_azx_runtime_resume(chip);
1256 static int azx_runtime_idle(struct device *dev)
1258 struct snd_card *card = dev_get_drvdata(dev);
1260 struct hda_intel *hda;
1265 chip = card->private_data;
1266 hda = container_of(chip, struct hda_intel, chip);
1267 if (chip->disabled || hda->init_failed)
1270 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1271 azx_bus(chip)->codec_powered || !chip->running)
1277 static const struct dev_pm_ops azx_pm = {
1278 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1279 #ifdef CONFIG_PM_SLEEP
1280 .freeze_noirq = azx_freeze_noirq,
1281 .thaw_noirq = azx_thaw_noirq,
1283 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1286 #define AZX_PM_OPS &azx_pm
1288 #define AZX_PM_OPS NULL
1289 #endif /* CONFIG_PM */
1292 static int azx_probe_continue(struct azx *chip);
1294 #ifdef SUPPORT_VGA_SWITCHEROO
1295 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1297 static void azx_vs_set_state(struct pci_dev *pci,
1298 enum vga_switcheroo_state state)
1300 struct snd_card *card = pci_get_drvdata(pci);
1301 struct azx *chip = card->private_data;
1302 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1303 struct hda_codec *codec;
1306 wait_for_completion(&hda->probe_wait);
1307 if (hda->init_failed)
1310 disabled = (state == VGA_SWITCHEROO_OFF);
1311 if (chip->disabled == disabled)
1314 if (!hda->probe_continued) {
1315 chip->disabled = disabled;
1317 dev_info(chip->card->dev,
1318 "Start delayed initialization\n");
1319 if (azx_probe_continue(chip) < 0) {
1320 dev_err(chip->card->dev, "initialization error\n");
1321 hda->init_failed = true;
1325 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1326 disabled ? "Disabling" : "Enabling");
1328 list_for_each_codec(codec, &chip->bus) {
1329 pm_runtime_suspend(hda_codec_dev(codec));
1330 pm_runtime_disable(hda_codec_dev(codec));
1332 pm_runtime_suspend(card->dev);
1333 pm_runtime_disable(card->dev);
1334 /* when we get suspended by vga_switcheroo we end up in D3cold,
1335 * however we have no ACPI handle, so pci/acpi can't put us there,
1336 * put ourselves there */
1337 pci->current_state = PCI_D3cold;
1338 chip->disabled = true;
1339 if (snd_hda_lock_devices(&chip->bus))
1340 dev_warn(chip->card->dev,
1341 "Cannot lock devices!\n");
1343 snd_hda_unlock_devices(&chip->bus);
1344 chip->disabled = false;
1345 pm_runtime_enable(card->dev);
1346 list_for_each_codec(codec, &chip->bus) {
1347 pm_runtime_enable(hda_codec_dev(codec));
1348 pm_runtime_resume(hda_codec_dev(codec));
1354 static bool azx_vs_can_switch(struct pci_dev *pci)
1356 struct snd_card *card = pci_get_drvdata(pci);
1357 struct azx *chip = card->private_data;
1358 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1360 wait_for_completion(&hda->probe_wait);
1361 if (hda->init_failed)
1363 if (chip->disabled || !hda->probe_continued)
1365 if (snd_hda_lock_devices(&chip->bus))
1367 snd_hda_unlock_devices(&chip->bus);
1371 static void init_vga_switcheroo(struct azx *chip)
1373 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1374 struct pci_dev *p = get_bound_vga(chip->pci);
1376 dev_info(chip->card->dev,
1377 "Handle vga_switcheroo audio client\n");
1378 hda->use_vga_switcheroo = 1;
1379 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1384 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1385 .set_gpu_state = azx_vs_set_state,
1386 .can_switch = azx_vs_can_switch,
1389 static int register_vga_switcheroo(struct azx *chip)
1391 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1394 if (!hda->use_vga_switcheroo)
1396 /* FIXME: currently only handling DIS controller
1397 * is there any machine with two switchable HDMI audio controllers?
1399 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1400 VGA_SWITCHEROO_DIS);
1403 hda->vga_switcheroo_registered = 1;
1408 #define init_vga_switcheroo(chip) /* NOP */
1409 #define register_vga_switcheroo(chip) 0
1410 #define check_hdmi_disabled(pci) false
1411 #endif /* SUPPORT_VGA_SWITCHER */
1416 static int azx_free(struct azx *chip)
1418 struct pci_dev *pci = chip->pci;
1419 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1420 struct hdac_bus *bus = azx_bus(chip);
1422 if (azx_has_pm_runtime(chip) && chip->running)
1423 pm_runtime_get_noresume(&pci->dev);
1425 azx_del_card_list(chip);
1427 hda->init_failed = 1; /* to be sure */
1428 complete_all(&hda->probe_wait);
1430 if (use_vga_switcheroo(hda)) {
1431 if (chip->disabled && hda->probe_continued)
1432 snd_hda_unlock_devices(&chip->bus);
1433 if (hda->vga_switcheroo_registered)
1434 vga_switcheroo_unregister_client(chip->pci);
1437 if (bus->chip_init) {
1438 azx_clear_irq_pending(chip);
1439 azx_stop_all_streams(chip);
1440 azx_stop_chip(chip);
1444 free_irq(bus->irq, (void*)chip);
1446 pci_disable_msi(chip->pci);
1447 iounmap(bus->remap_addr);
1449 azx_free_stream_pages(chip);
1450 azx_free_streams(chip);
1451 snd_hdac_bus_exit(bus);
1453 if (chip->region_requested)
1454 pci_release_regions(chip->pci);
1456 pci_disable_device(chip->pci);
1457 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1458 release_firmware(chip->fw);
1461 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1462 if (hda->need_i915_power)
1463 snd_hdac_display_power(bus, false);
1465 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1466 snd_hdac_i915_exit(bus);
1472 static int azx_dev_disconnect(struct snd_device *device)
1474 struct azx *chip = device->device_data;
1475 struct hdac_bus *bus = azx_bus(chip);
1477 chip->bus.shutdown = 1;
1478 cancel_work_sync(&bus->unsol_work);
1483 static int azx_dev_free(struct snd_device *device)
1485 return azx_free(device->device_data);
1488 #ifdef SUPPORT_VGA_SWITCHEROO
1490 * Check of disabled HDMI controller by vga_switcheroo
1492 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1496 /* check only discrete GPU */
1497 switch (pci->vendor) {
1498 case PCI_VENDOR_ID_ATI:
1499 case PCI_VENDOR_ID_AMD:
1500 case PCI_VENDOR_ID_NVIDIA:
1501 if (pci->devfn == 1) {
1502 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1503 pci->bus->number, 0);
1505 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1515 static bool check_hdmi_disabled(struct pci_dev *pci)
1517 bool vga_inactive = false;
1518 struct pci_dev *p = get_bound_vga(pci);
1521 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1522 vga_inactive = true;
1525 return vga_inactive;
1527 #endif /* SUPPORT_VGA_SWITCHEROO */
1530 * white/black-listing for position_fix
1532 static struct snd_pci_quirk position_fix_list[] = {
1533 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1534 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1535 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1536 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1537 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1538 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1539 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1540 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1541 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1542 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1543 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1544 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1545 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1546 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1550 static int check_position_fix(struct azx *chip, int fix)
1552 const struct snd_pci_quirk *q;
1557 case POS_FIX_POSBUF:
1558 case POS_FIX_VIACOMBO:
1565 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1567 dev_info(chip->card->dev,
1568 "position_fix set to %d for device %04x:%04x\n",
1569 q->value, q->subvendor, q->subdevice);
1573 /* Check VIA/ATI HD Audio Controller exist */
1574 if (chip->driver_type == AZX_DRIVER_VIA) {
1575 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1576 return POS_FIX_VIACOMBO;
1578 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1579 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1580 return POS_FIX_FIFO;
1582 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1583 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1584 return POS_FIX_LPIB;
1586 if (chip->driver_type == AZX_DRIVER_SKL) {
1587 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1590 return POS_FIX_AUTO;
1593 static void assign_position_fix(struct azx *chip, int fix)
1595 static azx_get_pos_callback_t callbacks[] = {
1596 [POS_FIX_AUTO] = NULL,
1597 [POS_FIX_LPIB] = azx_get_pos_lpib,
1598 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1599 [POS_FIX_VIACOMBO] = azx_via_get_position,
1600 [POS_FIX_COMBO] = azx_get_pos_lpib,
1601 [POS_FIX_SKL] = azx_get_pos_skl,
1602 [POS_FIX_FIFO] = azx_get_pos_fifo,
1605 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1607 /* combo mode uses LPIB only for playback */
1608 if (fix == POS_FIX_COMBO)
1609 chip->get_position[1] = NULL;
1611 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1612 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1613 chip->get_delay[0] = chip->get_delay[1] =
1614 azx_get_delay_from_lpib;
1617 if (fix == POS_FIX_FIFO)
1618 chip->get_delay[0] = chip->get_delay[1] =
1619 azx_get_delay_from_fifo;
1623 * black-lists for probe_mask
1625 static struct snd_pci_quirk probe_mask_list[] = {
1626 /* Thinkpad often breaks the controller communication when accessing
1627 * to the non-working (or non-existing) modem codec slot.
1629 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1630 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1631 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1633 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1634 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1635 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1636 /* forced codec slots */
1637 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1638 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1639 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1640 /* WinFast VP200 H (Teradici) user reported broken communication */
1641 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1645 #define AZX_FORCE_CODEC_MASK 0x100
1647 static void check_probe_mask(struct azx *chip, int dev)
1649 const struct snd_pci_quirk *q;
1651 chip->codec_probe_mask = probe_mask[dev];
1652 if (chip->codec_probe_mask == -1) {
1653 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1655 dev_info(chip->card->dev,
1656 "probe_mask set to 0x%x for device %04x:%04x\n",
1657 q->value, q->subvendor, q->subdevice);
1658 chip->codec_probe_mask = q->value;
1662 /* check forced option */
1663 if (chip->codec_probe_mask != -1 &&
1664 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1665 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1666 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1667 (int)azx_bus(chip)->codec_mask);
1672 * white/black-list for enable_msi
1674 static struct snd_pci_quirk msi_black_list[] = {
1675 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1676 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1677 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1678 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1679 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1680 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1681 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1682 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1683 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1684 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1688 static void check_msi(struct azx *chip)
1690 const struct snd_pci_quirk *q;
1692 if (enable_msi >= 0) {
1693 chip->msi = !!enable_msi;
1696 chip->msi = 1; /* enable MSI as default */
1697 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1699 dev_info(chip->card->dev,
1700 "msi for device %04x:%04x set to %d\n",
1701 q->subvendor, q->subdevice, q->value);
1702 chip->msi = q->value;
1706 /* NVidia chipsets seem to cause troubles with MSI */
1707 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1708 dev_info(chip->card->dev, "Disabling MSI\n");
1713 /* check the snoop mode availability */
1714 static void azx_check_snoop_available(struct azx *chip)
1716 int snoop = hda_snoop;
1719 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1720 snoop ? "snoop" : "non-snoop");
1721 chip->snoop = snoop;
1722 chip->uc_buffer = !snoop;
1727 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1728 chip->driver_type == AZX_DRIVER_VIA) {
1729 /* force to non-snoop mode for a new VIA controller
1733 pci_read_config_byte(chip->pci, 0x42, &val);
1734 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1735 chip->pci->revision == 0x20))
1739 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1742 chip->snoop = snoop;
1744 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1745 /* C-Media requires non-cached pages only for CORB/RIRB */
1746 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1747 chip->uc_buffer = true;
1751 static void azx_probe_work(struct work_struct *work)
1753 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1754 azx_probe_continue(&hda->chip);
1757 static int default_bdl_pos_adj(struct azx *chip)
1759 /* some exceptions: Atoms seem problematic with value 1 */
1760 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1761 switch (chip->pci->device) {
1762 case 0x0f04: /* Baytrail */
1763 case 0x2284: /* Braswell */
1768 switch (chip->driver_type) {
1769 case AZX_DRIVER_ICH:
1770 case AZX_DRIVER_PCH:
1780 static const struct hdac_io_ops pci_hda_io_ops;
1781 static const struct hda_controller_ops pci_hda_ops;
1783 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1784 int dev, unsigned int driver_caps,
1787 static struct snd_device_ops ops = {
1788 .dev_disconnect = azx_dev_disconnect,
1789 .dev_free = azx_dev_free,
1791 struct hda_intel *hda;
1797 err = pci_enable_device(pci);
1801 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1803 pci_disable_device(pci);
1808 mutex_init(&chip->open_mutex);
1811 chip->ops = &pci_hda_ops;
1812 chip->driver_caps = driver_caps;
1813 chip->driver_type = driver_caps & 0xff;
1815 chip->dev_index = dev;
1816 chip->jackpoll_ms = jackpoll_ms;
1817 INIT_LIST_HEAD(&chip->pcm_list);
1818 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1819 INIT_LIST_HEAD(&hda->list);
1820 init_vga_switcheroo(chip);
1821 init_completion(&hda->probe_wait);
1823 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1825 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1826 chip->fallback_to_single_cmd = 1;
1827 else /* explicitly set to single_cmd or not */
1828 chip->single_cmd = single_cmd;
1830 azx_check_snoop_available(chip);
1832 if (bdl_pos_adj[dev] < 0)
1833 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1835 chip->bdl_pos_adj = bdl_pos_adj[dev];
1837 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1838 if (IS_CFL(pci) || IS_CNL(pci))
1839 chip->polling_mode = 1;
1841 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1844 pci_disable_device(pci);
1848 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1849 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1850 chip->bus.needs_damn_long_delay = 1;
1853 check_probe_mask(chip, dev);
1855 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1857 dev_err(card->dev, "Error creating device [card]!\n");
1862 /* continue probing in work context as may trigger request module */
1863 INIT_WORK(&hda->probe_work, azx_probe_work);
1870 static int azx_first_init(struct azx *chip)
1872 int dev = chip->dev_index;
1873 struct pci_dev *pci = chip->pci;
1874 struct snd_card *card = chip->card;
1875 struct hdac_bus *bus = azx_bus(chip);
1877 unsigned short gcap;
1878 unsigned int dma_bits = 64;
1880 #if BITS_PER_LONG != 64
1881 /* Fix up base address on ULI M5461 */
1882 if (chip->driver_type == AZX_DRIVER_ULI) {
1884 pci_read_config_word(pci, 0x40, &tmp3);
1885 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1886 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1890 err = pci_request_regions(pci, "ICH HD audio");
1893 chip->region_requested = 1;
1895 bus->addr = pci_resource_start(pci, 0);
1896 bus->remap_addr = pci_ioremap_bar(pci, 0);
1897 if (bus->remap_addr == NULL) {
1898 dev_err(card->dev, "ioremap error\n");
1902 if (chip->driver_type == AZX_DRIVER_SKL)
1903 snd_hdac_bus_parse_capabilities(bus);
1906 * Some Intel CPUs has always running timer (ART) feature and
1907 * controller may have Global time sync reporting capability, so
1908 * check both of these before declaring synchronized time reporting
1909 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1911 chip->gts_present = false;
1914 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1915 chip->gts_present = true;
1919 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1920 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1921 pci->no_64bit_msi = true;
1923 if (pci_enable_msi(pci) < 0)
1927 pci_set_master(pci);
1928 synchronize_irq(bus->irq);
1930 gcap = azx_readw(chip, GCAP);
1931 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1933 /* AMD devices support 40 or 48bit DMA, take the safe one */
1934 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1937 /* disable SB600 64bit support for safety */
1938 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1939 struct pci_dev *p_smbus;
1941 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1942 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1945 if (p_smbus->revision < 0x30)
1946 gcap &= ~AZX_GCAP_64OK;
1947 pci_dev_put(p_smbus);
1951 /* NVidia hardware normally only supports up to 40 bits of DMA */
1952 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1955 /* disable 64bit DMA address on some devices */
1956 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1957 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1958 gcap &= ~AZX_GCAP_64OK;
1961 /* disable buffer size rounding to 128-byte multiples if supported */
1962 if (align_buffer_size >= 0)
1963 chip->align_buffer_size = !!align_buffer_size;
1965 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1966 chip->align_buffer_size = 0;
1968 chip->align_buffer_size = 1;
1971 /* allow 64bit DMA address if supported by H/W */
1972 if (!(gcap & AZX_GCAP_64OK))
1974 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1975 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1977 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1978 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1981 /* read number of streams from GCAP register instead of using
1984 chip->capture_streams = (gcap >> 8) & 0x0f;
1985 chip->playback_streams = (gcap >> 12) & 0x0f;
1986 if (!chip->playback_streams && !chip->capture_streams) {
1987 /* gcap didn't give any info, switching to old method */
1989 switch (chip->driver_type) {
1990 case AZX_DRIVER_ULI:
1991 chip->playback_streams = ULI_NUM_PLAYBACK;
1992 chip->capture_streams = ULI_NUM_CAPTURE;
1994 case AZX_DRIVER_ATIHDMI:
1995 case AZX_DRIVER_ATIHDMI_NS:
1996 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1997 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1999 case AZX_DRIVER_GENERIC:
2001 chip->playback_streams = ICH6_NUM_PLAYBACK;
2002 chip->capture_streams = ICH6_NUM_CAPTURE;
2006 chip->capture_index_offset = 0;
2007 chip->playback_index_offset = chip->capture_streams;
2008 chip->num_streams = chip->playback_streams + chip->capture_streams;
2010 /* sanity check for the SDxCTL.STRM field overflow */
2011 if (chip->num_streams > 15 &&
2012 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2013 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2014 "forcing separate stream tags", chip->num_streams);
2015 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2018 /* initialize streams */
2019 err = azx_init_streams(chip);
2023 err = azx_alloc_stream_pages(chip);
2027 /* initialize chip */
2030 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2031 snd_hdac_i915_set_bclk(bus);
2033 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2035 /* codec detection */
2036 if (!azx_bus(chip)->codec_mask) {
2037 dev_err(card->dev, "no codecs found!\n");
2041 if (azx_acquire_irq(chip, 0) < 0)
2044 strcpy(card->driver, "HDA-Intel");
2045 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2046 sizeof(card->shortname));
2047 snprintf(card->longname, sizeof(card->longname),
2048 "%s at 0x%lx irq %i",
2049 card->shortname, bus->addr, bus->irq);
2054 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2055 /* callback from request_firmware_nowait() */
2056 static void azx_firmware_cb(const struct firmware *fw, void *context)
2058 struct snd_card *card = context;
2059 struct azx *chip = card->private_data;
2064 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2065 if (!chip->disabled) {
2066 /* continue probing */
2067 azx_probe_continue(chip);
2073 * HDA controller ops.
2076 /* PCI register access. */
2077 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2079 writel(value, addr);
2082 static u32 pci_azx_readl(u32 __iomem *addr)
2087 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2089 writew(value, addr);
2092 static u16 pci_azx_readw(u16 __iomem *addr)
2097 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2099 writeb(value, addr);
2102 static u8 pci_azx_readb(u8 __iomem *addr)
2107 static int disable_msi_reset_irq(struct azx *chip)
2109 struct hdac_bus *bus = azx_bus(chip);
2112 free_irq(bus->irq, chip);
2114 pci_disable_msi(chip->pci);
2116 err = azx_acquire_irq(chip, 1);
2123 /* DMA page allocation helpers. */
2124 static int dma_alloc_pages(struct hdac_bus *bus,
2127 struct snd_dma_buffer *buf)
2129 struct azx *chip = bus_to_azx(bus);
2132 err = snd_dma_alloc_pages(type,
2137 mark_pages_wc(chip, buf, true);
2141 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2143 struct azx *chip = bus_to_azx(bus);
2145 mark_pages_wc(chip, buf, false);
2146 snd_dma_free_pages(buf);
2149 static int substream_alloc_pages(struct azx *chip,
2150 struct snd_pcm_substream *substream,
2153 struct azx_dev *azx_dev = get_azx_dev(substream);
2156 mark_runtime_wc(chip, azx_dev, substream, false);
2157 ret = snd_pcm_lib_malloc_pages(substream, size);
2160 mark_runtime_wc(chip, azx_dev, substream, true);
2164 static int substream_free_pages(struct azx *chip,
2165 struct snd_pcm_substream *substream)
2167 struct azx_dev *azx_dev = get_azx_dev(substream);
2168 mark_runtime_wc(chip, azx_dev, substream, false);
2169 return snd_pcm_lib_free_pages(substream);
2172 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2173 struct vm_area_struct *area)
2176 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2177 struct azx *chip = apcm->chip;
2178 if (chip->uc_buffer)
2179 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2183 static const struct hdac_io_ops pci_hda_io_ops = {
2184 .reg_writel = pci_azx_writel,
2185 .reg_readl = pci_azx_readl,
2186 .reg_writew = pci_azx_writew,
2187 .reg_readw = pci_azx_readw,
2188 .reg_writeb = pci_azx_writeb,
2189 .reg_readb = pci_azx_readb,
2190 .dma_alloc_pages = dma_alloc_pages,
2191 .dma_free_pages = dma_free_pages,
2194 /* Blacklist for skipping the whole probe:
2195 * some HD-audio PCI entries are exposed without any codecs, and such devices
2196 * should be ignored from the beginning.
2198 static const struct pci_device_id driver_blacklist[] = {
2199 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2200 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2201 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2205 static const struct hda_controller_ops pci_hda_ops = {
2206 .disable_msi_reset_irq = disable_msi_reset_irq,
2207 .substream_alloc_pages = substream_alloc_pages,
2208 .substream_free_pages = substream_free_pages,
2209 .pcm_mmap_prepare = pcm_mmap_prepare,
2210 .position_check = azx_position_check,
2211 .link_power = azx_intel_link_power,
2214 static int azx_probe(struct pci_dev *pci,
2215 const struct pci_device_id *pci_id)
2218 struct snd_card *card;
2219 struct hda_intel *hda;
2221 bool schedule_probe;
2224 if (pci_match_id(driver_blacklist, pci)) {
2225 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2229 if (dev >= SNDRV_CARDS)
2236 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2239 dev_err(&pci->dev, "Error creating card!\n");
2243 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2246 card->private_data = chip;
2247 hda = container_of(chip, struct hda_intel, chip);
2249 pci_set_drvdata(pci, card);
2251 err = register_vga_switcheroo(chip);
2253 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2257 if (check_hdmi_disabled(pci)) {
2258 dev_info(card->dev, "VGA controller is disabled\n");
2259 dev_info(card->dev, "Delaying initialization\n");
2260 chip->disabled = true;
2263 schedule_probe = !chip->disabled;
2265 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2266 if (patch[dev] && *patch[dev]) {
2267 dev_info(card->dev, "Applying patch firmware '%s'\n",
2269 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2270 &pci->dev, GFP_KERNEL, card,
2274 schedule_probe = false; /* continued in azx_firmware_cb() */
2276 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2278 #ifndef CONFIG_SND_HDA_I915
2279 if (CONTROLLER_IN_GPU(pci))
2280 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2284 schedule_work(&hda->probe_work);
2288 complete_all(&hda->probe_wait);
2292 snd_card_free(card);
2297 /* On some boards setting power_save to a non 0 value leads to clicking /
2298 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2299 * figure out how to avoid these sounds, but that is not always feasible.
2300 * So we keep a list of devices where we disable powersaving as its known
2301 * to causes problems on these devices.
2303 static struct snd_pci_quirk power_save_blacklist[] = {
2304 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2305 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2306 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2307 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2308 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2309 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2310 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2311 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2314 #endif /* CONFIG_PM */
2316 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2317 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2318 [AZX_DRIVER_NVIDIA] = 8,
2319 [AZX_DRIVER_TERA] = 1,
2322 static int azx_probe_continue(struct azx *chip)
2324 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2325 struct hdac_bus *bus = azx_bus(chip);
2326 struct pci_dev *pci = chip->pci;
2327 struct hda_codec *codec;
2328 int dev = chip->dev_index;
2332 to_hda_bus(bus)->bus_probing = 1;
2333 hda->probe_continued = 1;
2335 /* bind with i915 if needed */
2336 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2337 err = snd_hdac_i915_init(bus);
2339 /* if the controller is bound only with HDMI/DP
2340 * (for HSW and BDW), we need to abort the probe;
2341 * for other chips, still continue probing as other
2342 * codecs can be on the same link.
2344 if (CONTROLLER_IN_GPU(pci)) {
2345 dev_err(chip->card->dev,
2346 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2349 /* don't bother any longer */
2350 chip->driver_caps &=
2351 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2356 /* Request display power well for the HDA controller or codec. For
2357 * Haswell/Broadwell, both the display HDA controller and codec need
2358 * this power. For other platforms, like Baytrail/Braswell, only the
2359 * display codec needs the power and it can be released after probe.
2361 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2362 /* HSW/BDW controllers need this power */
2363 if (CONTROLLER_IN_GPU(pci))
2364 hda->need_i915_power = 1;
2366 err = snd_hdac_display_power(bus, true);
2368 dev_err(chip->card->dev,
2369 "Cannot turn on display power on i915\n");
2370 goto i915_power_fail;
2374 err = azx_first_init(chip);
2378 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2379 chip->beep_mode = beep_mode[dev];
2382 /* create codec instances */
2383 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2387 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2389 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2394 release_firmware(chip->fw); /* no longer needed */
2399 if ((probe_only[dev] & 1) == 0) {
2400 err = azx_codec_configure(chip);
2405 err = snd_card_register(chip->card);
2410 azx_add_card_list(chip);
2413 * The discrete GPU cannot power down unless the HDA controller runtime
2414 * suspends, so activate runtime PM on codecs even if power_save == 0.
2416 if (use_vga_switcheroo(hda))
2417 list_for_each_codec(codec, &chip->bus)
2418 codec->auto_runtime_pm = 1;
2423 const struct snd_pci_quirk *q;
2425 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2427 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2428 q->subvendor, q->subdevice);
2432 #endif /* CONFIG_PM */
2433 snd_hda_set_power_save(&chip->bus, val * 1000);
2434 if (azx_has_pm_runtime(chip))
2435 pm_runtime_put_autosuspend(&pci->dev);
2438 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2439 && !hda->need_i915_power)
2440 snd_hdac_display_power(bus, false);
2444 hda->init_failed = 1;
2445 complete_all(&hda->probe_wait);
2446 to_hda_bus(bus)->bus_probing = 0;
2450 static void azx_remove(struct pci_dev *pci)
2452 struct snd_card *card = pci_get_drvdata(pci);
2454 struct hda_intel *hda;
2457 /* cancel the pending probing work */
2458 chip = card->private_data;
2459 hda = container_of(chip, struct hda_intel, chip);
2460 /* FIXME: below is an ugly workaround.
2461 * Both device_release_driver() and driver_probe_device()
2462 * take *both* the device's and its parent's lock before
2463 * calling the remove() and probe() callbacks. The codec
2464 * probe takes the locks of both the codec itself and its
2465 * parent, i.e. the PCI controller dev. Meanwhile, when
2466 * the PCI controller is unbound, it takes its lock, too
2467 * ==> ouch, a deadlock!
2468 * As a workaround, we unlock temporarily here the controller
2469 * device during cancel_work_sync() call.
2471 device_unlock(&pci->dev);
2472 cancel_work_sync(&hda->probe_work);
2473 device_lock(&pci->dev);
2475 snd_card_free(card);
2479 static void azx_shutdown(struct pci_dev *pci)
2481 struct snd_card *card = pci_get_drvdata(pci);
2486 chip = card->private_data;
2487 if (chip && chip->running)
2488 azx_stop_chip(chip);
2492 static const struct pci_device_id azx_ids[] = {
2494 { PCI_DEVICE(0x8086, 0x1c20),
2495 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2497 { PCI_DEVICE(0x8086, 0x1d20),
2498 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2500 { PCI_DEVICE(0x8086, 0x1e20),
2501 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2503 { PCI_DEVICE(0x8086, 0x8c20),
2504 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2506 { PCI_DEVICE(0x8086, 0x8ca0),
2507 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2509 { PCI_DEVICE(0x8086, 0x8d20),
2510 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2511 { PCI_DEVICE(0x8086, 0x8d21),
2512 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2514 { PCI_DEVICE(0x8086, 0xa1f0),
2515 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2516 { PCI_DEVICE(0x8086, 0xa270),
2517 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2519 { PCI_DEVICE(0x8086, 0x9c20),
2520 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2522 { PCI_DEVICE(0x8086, 0x9c21),
2523 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2524 /* Wildcat Point-LP */
2525 { PCI_DEVICE(0x8086, 0x9ca0),
2526 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2528 { PCI_DEVICE(0x8086, 0xa170),
2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2530 /* Sunrise Point-LP */
2531 { PCI_DEVICE(0x8086, 0x9d70),
2532 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2534 { PCI_DEVICE(0x8086, 0xa171),
2535 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2537 { PCI_DEVICE(0x8086, 0x9d71),
2538 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2540 { PCI_DEVICE(0x8086, 0xa2f0),
2541 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2543 { PCI_DEVICE(0x8086, 0xa348),
2544 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2546 { PCI_DEVICE(0x8086, 0x9dc8),
2547 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2548 /* Broxton-P(Apollolake) */
2549 { PCI_DEVICE(0x8086, 0x5a98),
2550 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2552 { PCI_DEVICE(0x8086, 0x1a98),
2553 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2555 { PCI_DEVICE(0x8086, 0x3198),
2556 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2558 { PCI_DEVICE(0x8086, 0x0a0c),
2559 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2560 { PCI_DEVICE(0x8086, 0x0c0c),
2561 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2562 { PCI_DEVICE(0x8086, 0x0d0c),
2563 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2565 { PCI_DEVICE(0x8086, 0x160c),
2566 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2568 { PCI_DEVICE(0x8086, 0x3b56),
2569 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2570 { PCI_DEVICE(0x8086, 0x3b57),
2571 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2573 { PCI_DEVICE(0x8086, 0x811b),
2574 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2575 AZX_DCAPS_POSFIX_LPIB },
2577 { PCI_DEVICE(0x8086, 0x080a),
2578 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2580 { PCI_DEVICE(0x8086, 0x0f04),
2581 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2583 { PCI_DEVICE(0x8086, 0x2284),
2584 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2586 { PCI_DEVICE(0x8086, 0x2668),
2587 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2589 { PCI_DEVICE(0x8086, 0x27d8),
2590 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2592 { PCI_DEVICE(0x8086, 0x269a),
2593 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2595 { PCI_DEVICE(0x8086, 0x284b),
2596 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2598 { PCI_DEVICE(0x8086, 0x293e),
2599 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2601 { PCI_DEVICE(0x8086, 0x293f),
2602 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2604 { PCI_DEVICE(0x8086, 0x3a3e),
2605 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2607 { PCI_DEVICE(0x8086, 0x3a6e),
2608 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2610 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2611 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2612 .class_mask = 0xffffff,
2613 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2614 /* ATI SB 450/600/700/800/900 */
2615 { PCI_DEVICE(0x1002, 0x437b),
2616 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2617 { PCI_DEVICE(0x1002, 0x4383),
2618 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2620 { PCI_DEVICE(0x1022, 0x780d),
2621 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2622 /* AMD, X370 & co */
2623 { PCI_DEVICE(0x1022, 0x1457),
2624 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2625 /* AMD, X570 & co */
2626 { PCI_DEVICE(0x1022, 0x1487),
2627 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2629 { PCI_DEVICE(0x1022, 0x157a),
2630 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2631 AZX_DCAPS_PM_RUNTIME },
2633 { PCI_DEVICE(0x1022, 0x15e3),
2634 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2636 { PCI_DEVICE(0x1002, 0x0002),
2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2638 { PCI_DEVICE(0x1002, 0x1308),
2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2640 { PCI_DEVICE(0x1002, 0x157a),
2641 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2642 { PCI_DEVICE(0x1002, 0x15b3),
2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2644 { PCI_DEVICE(0x1002, 0x793b),
2645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646 { PCI_DEVICE(0x1002, 0x7919),
2647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648 { PCI_DEVICE(0x1002, 0x960f),
2649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2650 { PCI_DEVICE(0x1002, 0x970f),
2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652 { PCI_DEVICE(0x1002, 0x9840),
2653 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2654 { PCI_DEVICE(0x1002, 0xaa00),
2655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656 { PCI_DEVICE(0x1002, 0xaa08),
2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658 { PCI_DEVICE(0x1002, 0xaa10),
2659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660 { PCI_DEVICE(0x1002, 0xaa18),
2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662 { PCI_DEVICE(0x1002, 0xaa20),
2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664 { PCI_DEVICE(0x1002, 0xaa28),
2665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2666 { PCI_DEVICE(0x1002, 0xaa30),
2667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2668 { PCI_DEVICE(0x1002, 0xaa38),
2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2670 { PCI_DEVICE(0x1002, 0xaa40),
2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2672 { PCI_DEVICE(0x1002, 0xaa48),
2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2674 { PCI_DEVICE(0x1002, 0xaa50),
2675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2676 { PCI_DEVICE(0x1002, 0xaa58),
2677 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2678 { PCI_DEVICE(0x1002, 0xaa60),
2679 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2680 { PCI_DEVICE(0x1002, 0xaa68),
2681 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2682 { PCI_DEVICE(0x1002, 0xaa80),
2683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2684 { PCI_DEVICE(0x1002, 0xaa88),
2685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2686 { PCI_DEVICE(0x1002, 0xaa90),
2687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2688 { PCI_DEVICE(0x1002, 0xaa98),
2689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2690 { PCI_DEVICE(0x1002, 0x9902),
2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2692 { PCI_DEVICE(0x1002, 0xaaa0),
2693 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2694 { PCI_DEVICE(0x1002, 0xaaa8),
2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2696 { PCI_DEVICE(0x1002, 0xaab0),
2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2698 { PCI_DEVICE(0x1002, 0xaac0),
2699 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2700 { PCI_DEVICE(0x1002, 0xaac8),
2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2702 { PCI_DEVICE(0x1002, 0xaad8),
2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2704 { PCI_DEVICE(0x1002, 0xaae8),
2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2706 { PCI_DEVICE(0x1002, 0xaae0),
2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2708 { PCI_DEVICE(0x1002, 0xaaf0),
2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2710 /* VIA VT8251/VT8237A */
2711 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2712 /* VIA GFX VT7122/VX900 */
2713 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2714 /* VIA GFX VT6122/VX11 */
2715 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2717 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2719 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2721 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2722 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2723 .class_mask = 0xffffff,
2724 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2726 { PCI_DEVICE(0x6549, 0x1200),
2727 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2728 { PCI_DEVICE(0x6549, 0x2200),
2729 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2730 /* Creative X-Fi (CA0110-IBG) */
2732 { PCI_DEVICE(0x1102, 0x0010),
2733 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2734 { PCI_DEVICE(0x1102, 0x0012),
2735 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2736 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2737 /* the following entry conflicts with snd-ctxfi driver,
2738 * as ctxfi driver mutates from HD-audio to native mode with
2739 * a special command sequence.
2741 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2742 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2743 .class_mask = 0xffffff,
2744 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2745 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2747 /* this entry seems still valid -- i.e. without emu20kx chip */
2748 { PCI_DEVICE(0x1102, 0x0009),
2749 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2750 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2753 { PCI_DEVICE(0x13f6, 0x5011),
2754 .driver_data = AZX_DRIVER_CMEDIA |
2755 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2757 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2758 /* VMware HDAudio */
2759 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2760 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2761 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2762 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2763 .class_mask = 0xffffff,
2764 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2765 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2766 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2767 .class_mask = 0xffffff,
2768 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2771 MODULE_DEVICE_TABLE(pci, azx_ids);
2773 /* pci_driver definition */
2774 static struct pci_driver azx_driver = {
2775 .name = KBUILD_MODNAME,
2776 .id_table = azx_ids,
2778 .remove = azx_remove,
2779 .shutdown = azx_shutdown,
2785 module_pci_driver(azx_driver);