sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81         POS_FIX_FIFO,
  82 };
  83
  84 /* Defines for ATI HD Audio support in SB450 south bridge */
  85 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  86 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  87
  88 /* Defines for Nvidia HDA support */
  89 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  90 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  91 #define NVIDIA_HDA_ISTRM_COH          0x4d
  92 #define NVIDIA_HDA_OSTRM_COH          0x4c
  93 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  94
  95 /* Defines for Intel SCH HDA snoop control */
  96 #define INTEL_HDA_CGCTL  0x48
  97 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  98 #define INTEL_SCH_HDA_DEVC      0x78
  99 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 100
 101 /* Define IN stream 0 FIFO size offset in VIA controller */
 102 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 103 /* Define VIA HD Audio Device ID*/
 104 #define VIA_HDAC_DEVICE_ID              0x3288
 105
 106 /* max number of SDs */
 107 /* ICH, ATI and VIA have 4 playback and 4 capture */
 108 #define ICH6_NUM_CAPTURE        4
 109 #define ICH6_NUM_PLAYBACK       4
 110
 111 /* ULI has 6 playback and 5 capture */
 112 #define ULI_NUM_CAPTURE         5
 113 #define ULI_NUM_PLAYBACK        6
 114
 115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 116 #define ATIHDMI_NUM_CAPTURE     0
 117 #define ATIHDMI_NUM_PLAYBACK    8
 118
 119 /* TERA has 4 playback and 3 capture */
 120 #define TERA_NUM_CAPTURE        3
 121 #define TERA_NUM_PLAYBACK       4
 122
 123
 124 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 125 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 126 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 127 static char *model[SNDRV_CARDS];
 128 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 131 static int probe_only[SNDRV_CARDS];
 132 static int jackpoll_ms[SNDRV_CARDS];
 133 static int single_cmd = -1;
 134 static int enable_msi = -1;
 135 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 136 static char *patch[SNDRV_CARDS];
 137 #endif
 138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 139 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 140                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 141 #endif
 142
 143 module_param_array(index, int, NULL, 0444);
 144 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 145 module_param_array(id, charp, NULL, 0444);
 146 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 147 module_param_array(enable, bool, NULL, 0444);
 148 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 149 module_param_array(model, charp, NULL, 0444);
 150 MODULE_PARM_DESC(model, "Use the given board model.");
 151 module_param_array(position_fix, int, NULL, 0444);
 152 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 153                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 154 module_param_array(bdl_pos_adj, int, NULL, 0644);
 155 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 156 module_param_array(probe_mask, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 158 module_param_array(probe_only, int, NULL, 0444);
 159 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 160 module_param_array(jackpoll_ms, int, NULL, 0444);
 161 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 162 module_param(single_cmd, bint, 0444);
 163 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 164                  "(for debugging only).");
 165 module_param(enable_msi, bint, 0444);
 166 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 167 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 168 module_param_array(patch, charp, NULL, 0444);
 169 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 170 #endif
 171 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 172 module_param_array(beep_mode, bool, NULL, 0444);
 173 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 174                             "(0=off, 1=on) (default=1).");
 175 #endif
 176
 177 #ifdef CONFIG_PM
 178 static int param_set_xint(const char *val, const struct kernel_param *kp);
 179 static const struct kernel_param_ops param_ops_xint = {
 180         .set = param_set_xint,
 181         .get = param_get_int,
 182 };
 183 #define param_check_xint param_check_int
 184
 185 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 186 module_param(power_save, xint, 0644);
 187 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 188                  "(in second, 0 = disable).");
 189
 190 static bool pm_blacklist = true;
 191 module_param(pm_blacklist, bool, 0644);
 192 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 193
 194 /* reset the HD-audio controller in power save mode.
 195  * this may give more power-saving, but will take longer time to
 196  * wake up.
 197  */
 198 static bool power_save_controller = 1;
 199 module_param(power_save_controller, bool, 0644);
 200 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 201 #else
 202 #define power_save      0
 203 #endif /* CONFIG_PM */
 204
 205 static int align_buffer_size = -1;
 206 module_param(align_buffer_size, bint, 0644);
 207 MODULE_PARM_DESC(align_buffer_size,
 208                 "Force buffer and period sizes to be multiple of 128 bytes.");
 209
 210 #ifdef CONFIG_X86
 211 static int hda_snoop = -1;
 212 module_param_named(snoop, hda_snoop, bint, 0444);
 213 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 214 #else
 215 #define hda_snoop               true
 216 #endif
 217
 218
 219 MODULE_LICENSE("GPL");
 220 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 221                          "{Intel, ICH6M},"
 222                          "{Intel, ICH7},"
 223                          "{Intel, ESB2},"
 224                          "{Intel, ICH8},"
 225                          "{Intel, ICH9},"
 226                          "{Intel, ICH10},"
 227                          "{Intel, PCH},"
 228                          "{Intel, CPT},"
 229                          "{Intel, PPT},"
 230                          "{Intel, LPT},"
 231                          "{Intel, LPT_LP},"
 232                          "{Intel, WPT_LP},"
 233                          "{Intel, SPT},"
 234                          "{Intel, SPT_LP},"
 235                          "{Intel, HPT},"
 236                          "{Intel, PBG},"
 237                          "{Intel, SCH},"
 238                          "{ATI, SB450},"
 239                          "{ATI, SB600},"
 240                          "{ATI, RS600},"
 241                          "{ATI, RS690},"
 242                          "{ATI, RS780},"
 243                          "{ATI, R600},"
 244                          "{ATI, RV630},"
 245                          "{ATI, RV610},"
 246                          "{ATI, RV670},"
 247                          "{ATI, RV635},"
 248                          "{ATI, RV620},"
 249                          "{ATI, RV770},"
 250                          "{VIA, VT8251},"
 251                          "{VIA, VT8237A},"
 252                          "{SiS, SIS966},"
 253                          "{ULI, M5461}}");
 254 MODULE_DESCRIPTION("Intel HDA driver");
 255
 256 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 257 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 258 #define SUPPORT_VGA_SWITCHEROO
 259 #endif
 260 #endif
 261
 262
 263 /*
 264  */
 265
 266 /* driver types */
 267 enum {
 268         AZX_DRIVER_ICH,
 269         AZX_DRIVER_PCH,
 270         AZX_DRIVER_SCH,
 271         AZX_DRIVER_SKL,
 272         AZX_DRIVER_HDMI,
 273         AZX_DRIVER_ATI,
 274         AZX_DRIVER_ATIHDMI,
 275         AZX_DRIVER_ATIHDMI_NS,
 276         AZX_DRIVER_VIA,
 277         AZX_DRIVER_SIS,
 278         AZX_DRIVER_ULI,
 279         AZX_DRIVER_NVIDIA,
 280         AZX_DRIVER_TERA,
 281         AZX_DRIVER_CTX,
 282         AZX_DRIVER_CTHDA,
 283         AZX_DRIVER_CMEDIA,
 284         AZX_DRIVER_GENERIC,
 285         AZX_NUM_DRIVERS, /* keep this as last entry */
 286 };
 287
 288 #define azx_get_snoop_type(chip) \
 289         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 290 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 291
 292 /* quirks for old Intel chipsets */
 293 #define AZX_DCAPS_INTEL_ICH \
 294         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 295
 296 /* quirks for Intel PCH */
 297 #define AZX_DCAPS_INTEL_PCH_BASE \
 298         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 302 #define AZX_DCAPS_INTEL_PCH_NOPM \
 303         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 304
 305 /* PCH for HSW/BDW; with runtime PM */
 306 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 307 #define AZX_DCAPS_INTEL_PCH \
 308         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 309
 310 /* HSW HDMI */
 311 #define AZX_DCAPS_INTEL_HASWELL \
 312         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 313          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 314          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 315
 316 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 317 #define AZX_DCAPS_INTEL_BROADWELL \
 318         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 320          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 321
 322 #define AZX_DCAPS_INTEL_BAYTRAIL \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 324          AZX_DCAPS_I915_POWERWELL)
 325
 326 #define AZX_DCAPS_INTEL_BRASWELL \
 327         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 328          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 329
 330 #define AZX_DCAPS_INTEL_SKYLAKE \
 331         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 332          AZX_DCAPS_SYNC_WRITE |\
 333          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 334          AZX_DCAPS_I915_POWERWELL)
 335
 336 #define AZX_DCAPS_INTEL_BROXTON                 AZX_DCAPS_INTEL_SKYLAKE
 337
 338 /* quirks for ATI SB / AMD Hudson */
 339 #define AZX_DCAPS_PRESET_ATI_SB \
 340         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 341          AZX_DCAPS_SNOOP_TYPE(ATI))
 342
 343 /* quirks for ATI/AMD HDMI */
 344 #define AZX_DCAPS_PRESET_ATI_HDMI \
 345         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 346          AZX_DCAPS_NO_MSI64)
 347
 348 /* quirks for ATI HDMI with snoop off */
 349 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 350         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 351
 352 /* quirks for AMD SB */
 353 #define AZX_DCAPS_PRESET_AMD_SB \
 354         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 355          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 356
 357 /* quirks for Nvidia */
 358 #define AZX_DCAPS_PRESET_NVIDIA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 360          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 361
 362 #define AZX_DCAPS_PRESET_CTHDA \
 363         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 364          AZX_DCAPS_NO_64BIT |\
 365          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 366
 367 /*
 368  * vga_switcheroo support
 369  */
 370 #ifdef SUPPORT_VGA_SWITCHEROO
 371 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 372 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 373 #else
 374 #define use_vga_switcheroo(chip)        0
 375 #define needs_eld_notify_link(chip)     false
 376 #endif
 377
 378 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 379                                         ((pci)->device == 0x0c0c) || \
 380                                         ((pci)->device == 0x0d0c) || \
 381                                         ((pci)->device == 0x160c))
 382
 383 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 384 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 385 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 386
 387 static char *driver_short_names[] = {
 388         [AZX_DRIVER_ICH] = "HDA Intel",
 389         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 390         [AZX_DRIVER_SCH] = "HDA Intel MID",
 391         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 392         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 393         [AZX_DRIVER_ATI] = "HDA ATI SB",
 394         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 395         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 396         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 397         [AZX_DRIVER_SIS] = "HDA SIS966",
 398         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 399         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 400         [AZX_DRIVER_TERA] = "HDA Teradici",
 401         [AZX_DRIVER_CTX] = "HDA Creative",
 402         [AZX_DRIVER_CTHDA] = "HDA Creative",
 403         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 404         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 405 };
 406
 407 #ifdef CONFIG_X86
 408 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 409 {
 410         int pages;
 411
 412         if (azx_snoop(chip))
 413                 return;
 414         if (!dmab || !dmab->area || !dmab->bytes)
 415                 return;
 416
 417 #ifdef CONFIG_SND_DMA_SGBUF
 418         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 419                 struct snd_sg_buf *sgbuf = dmab->private_data;
 420                 if (!chip->uc_buffer)
 421                         return; /* deal with only CORB/RIRB buffers */
 422                 if (on)
 423                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 424                 else
 425                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 426                 return;
 427         }
 428 #endif
 429
 430         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 431         if (on)
 432                 set_memory_wc((unsigned long)dmab->area, pages);
 433         else
 434                 set_memory_wb((unsigned long)dmab->area, pages);
 435 }
 436
 437 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 438                                  bool on)
 439 {
 440         __mark_pages_wc(chip, buf, on);
 441 }
 442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 443                                    struct snd_pcm_substream *substream, bool on)
 444 {
 445         if (azx_dev->wc_marked != on) {
 446                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 447                 azx_dev->wc_marked = on;
 448         }
 449 }
 450 #else
 451 /* NOP for other archs */
 452 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 453                                  bool on)
 454 {
 455 }
 456 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 457                                    struct snd_pcm_substream *substream, bool on)
 458 {
 459 }
 460 #endif
 461
 462 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 463 static void set_default_power_save(struct azx *chip);
 464
 465 /*
 466  * initialize the PCI registers
 467  */
 468 /* update bits in a PCI register byte */
 469 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 470                             unsigned char mask, unsigned char val)
 471 {
 472         unsigned char data;
 473
 474         pci_read_config_byte(pci, reg, &data);
 475         data &= ~mask;
 476         data |= (val & mask);
 477         pci_write_config_byte(pci, reg, data);
 478 }
 479
 480 static void azx_init_pci(struct azx *chip)
 481 {
 482         int snoop_type = azx_get_snoop_type(chip);
 483
 484         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 485          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 486          * Ensuring these bits are 0 clears playback static on some HD Audio
 487          * codecs.
 488          * The PCI register TCSEL is defined in the Intel manuals.
 489          */
 490         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 491                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 492                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 493         }
 494
 495         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 496          * we need to enable snoop.
 497          */
 498         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 499                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 500                         azx_snoop(chip));
 501                 update_pci_byte(chip->pci,
 502                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 503                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 504         }
 505
 506         /* For NVIDIA HDA, enable snoop */
 507         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 508                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 509                         azx_snoop(chip));
 510                 update_pci_byte(chip->pci,
 511                                 NVIDIA_HDA_TRANSREG_ADDR,
 512                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 513                 update_pci_byte(chip->pci,
 514                                 NVIDIA_HDA_ISTRM_COH,
 515                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 516                 update_pci_byte(chip->pci,
 517                                 NVIDIA_HDA_OSTRM_COH,
 518                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 519         }
 520
 521         /* Enable SCH/PCH snoop if needed */
 522         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 523                 unsigned short snoop;
 524                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 525                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 526                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 527                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 528                         if (!azx_snoop(chip))
 529                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 530                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 531                         pci_read_config_word(chip->pci,
 532                                 INTEL_SCH_HDA_DEVC, &snoop);
 533                 }
 534                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 535                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 536                         "Disabled" : "Enabled");
 537         }
 538 }
 539
 540 /*
 541  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 542  * and makes an audio stream sensitive to system latencies when
 543  * 24/32 bits are playing.
 544  * Adjusting threshold of DMA fifo to force the DMA request
 545  * sooner to improve latency tolerance at the expense of power.
 546  */
 547 static void bxt_reduce_dma_latency(struct azx *chip)
 548 {
 549         u32 val;
 550
 551         val = azx_readl(chip, VS_EM4L);
 552         val &= (0x3 << 20);
 553         azx_writel(chip, VS_EM4L, val);
 554 }
 555
 556 /*
 557  * ML_LCAP bits:
 558  *  bit 0: 6 MHz Supported
 559  *  bit 1: 12 MHz Supported
 560  *  bit 2: 24 MHz Supported
 561  *  bit 3: 48 MHz Supported
 562  *  bit 4: 96 MHz Supported
 563  *  bit 5: 192 MHz Supported
 564  */
 565 static int intel_get_lctl_scf(struct azx *chip)
 566 {
 567         struct hdac_bus *bus = azx_bus(chip);
 568         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 569         u32 val, t;
 570         int i;
 571
 572         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 573
 574         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 575                 t = preferred_bits[i];
 576                 if (val & (1 << t))
 577                         return t;
 578         }
 579
 580         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 581         return 0;
 582 }
 583
 584 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 585 {
 586         struct hdac_bus *bus = azx_bus(chip);
 587         u32 val;
 588         int timeout;
 589
 590         /*
 591          * the codecs are sharing the first link setting by default
 592          * If other links are enabled for stream, they need similar fix
 593          */
 594         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 595         val &= ~AZX_MLCTL_SPA;
 596         val |= state << AZX_MLCTL_SPA_SHIFT;
 597         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 598         /* wait for CPA */
 599         timeout = 50;
 600         while (timeout) {
 601                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 602                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 603                         return 0;
 604                 timeout--;
 605                 udelay(10);
 606         }
 607
 608         return -1;
 609 }
 610
 611 static void intel_init_lctl(struct azx *chip)
 612 {
 613         struct hdac_bus *bus = azx_bus(chip);
 614         u32 val;
 615         int ret;
 616
 617         /* 0. check lctl register value is correct or not */
 618         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 619         /* if SCF is already set, let's use it */
 620         if ((val & ML_LCTL_SCF_MASK) != 0)
 621                 return;
 622
 623         /*
 624          * Before operating on SPA, CPA must match SPA.
 625          * Any deviation may result in undefined behavior.
 626          */
 627         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 628                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 629                 return;
 630
 631         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 632         ret = intel_ml_lctl_set_power(chip, 0);
 633         udelay(100);
 634         if (ret)
 635                 goto set_spa;
 636
 637         /* 2. update SCF to select a properly audio clock*/
 638         val &= ~ML_LCTL_SCF_MASK;
 639         val |= intel_get_lctl_scf(chip);
 640         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 641
 642 set_spa:
 643         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 644         intel_ml_lctl_set_power(chip, 1);
 645         udelay(100);
 646 }
 647
 648 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 649 {
 650         struct hdac_bus *bus = azx_bus(chip);
 651         struct pci_dev *pci = chip->pci;
 652         u32 val;
 653
 654         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 655                 snd_hdac_set_codec_wakeup(bus, true);
 656         if (chip->driver_type == AZX_DRIVER_SKL) {
 657                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 658                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 659                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 660         }
 661         azx_init_chip(chip, full_reset);
 662         if (chip->driver_type == AZX_DRIVER_SKL) {
 663                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 664                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 665                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 666         }
 667         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 668                 snd_hdac_set_codec_wakeup(bus, false);
 669
 670         /* reduce dma latency to avoid noise */
 671         if (IS_BXT(pci))
 672                 bxt_reduce_dma_latency(chip);
 673
 674         if (bus->mlcap != NULL)
 675                 intel_init_lctl(chip);
 676 }
 677
 678 /* calculate runtime delay from LPIB */
 679 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 680                                    unsigned int pos)
 681 {
 682         struct snd_pcm_substream *substream = azx_dev->core.substream;
 683         int stream = substream->stream;
 684         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 685         int delay;
 686
 687         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 688                 delay = pos - lpib_pos;
 689         else
 690                 delay = lpib_pos - pos;
 691         if (delay < 0) {
 692                 if (delay >= azx_dev->core.delay_negative_threshold)
 693                         delay = 0;
 694                 else
 695                         delay += azx_dev->core.bufsize;
 696         }
 697
 698         if (delay >= azx_dev->core.period_bytes) {
 699                 dev_info(chip->card->dev,
 700                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 701                          delay, azx_dev->core.period_bytes);
 702                 delay = 0;
 703                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 704                 chip->get_delay[stream] = NULL;
 705         }
 706
 707         return bytes_to_frames(substream->runtime, delay);
 708 }
 709
 710 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 711
 712 /* called from IRQ */
 713 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 714 {
 715         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 716         int ok;
 717
 718         ok = azx_position_ok(chip, azx_dev);
 719         if (ok == 1) {
 720                 azx_dev->irq_pending = 0;
 721                 return ok;
 722         } else if (ok == 0) {
 723                 /* bogus IRQ, process it later */
 724                 azx_dev->irq_pending = 1;
 725                 schedule_work(&hda->irq_pending_work);
 726         }
 727         return 0;
 728 }
 729
 730 /* Enable/disable i915 display power for the link */
 731 static int azx_intel_link_power(struct azx *chip, bool enable)
 732 {
 733         struct hdac_bus *bus = azx_bus(chip);
 734
 735         return snd_hdac_display_power(bus, enable);
 736 }
 737
 738 /*
 739  * Check whether the current DMA position is acceptable for updating
 740  * periods.  Returns non-zero if it's OK.
 741  *
 742  * Many HD-audio controllers appear pretty inaccurate about
 743  * the update-IRQ timing.  The IRQ is issued before actually the
 744  * data is processed.  So, we need to process it afterwords in a
 745  * workqueue.
 746  */
 747 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 748 {
 749         struct snd_pcm_substream *substream = azx_dev->core.substream;
 750         int stream = substream->stream;
 751         u32 wallclk;
 752         unsigned int pos;
 753
 754         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 755         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 756                 return -1;      /* bogus (too early) interrupt */
 757
 758         if (chip->get_position[stream])
 759                 pos = chip->get_position[stream](chip, azx_dev);
 760         else { /* use the position buffer as default */
 761                 pos = azx_get_pos_posbuf(chip, azx_dev);
 762                 if (!pos || pos == (u32)-1) {
 763                         dev_info(chip->card->dev,
 764                                  "Invalid position buffer, using LPIB read method instead.\n");
 765                         chip->get_position[stream] = azx_get_pos_lpib;
 766                         if (chip->get_position[0] == azx_get_pos_lpib &&
 767                             chip->get_position[1] == azx_get_pos_lpib)
 768                                 azx_bus(chip)->use_posbuf = false;
 769                         pos = azx_get_pos_lpib(chip, azx_dev);
 770                         chip->get_delay[stream] = NULL;
 771                 } else {
 772                         chip->get_position[stream] = azx_get_pos_posbuf;
 773                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 774                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 775                 }
 776         }
 777
 778         if (pos >= azx_dev->core.bufsize)
 779                 pos = 0;
 780
 781         if (WARN_ONCE(!azx_dev->core.period_bytes,
 782                       "hda-intel: zero azx_dev->period_bytes"))
 783                 return -1; /* this shouldn't happen! */
 784         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 785             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 786                 /* NG - it's below the first next period boundary */
 787                 return chip->bdl_pos_adj ? 0 : -1;
 788         azx_dev->core.start_wallclk += wallclk;
 789         return 1; /* OK, it's fine */
 790 }
 791
 792 /*
 793  * The work for pending PCM period updates.
 794  */
 795 static void azx_irq_pending_work(struct work_struct *work)
 796 {
 797         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 798         struct azx *chip = &hda->chip;
 799         struct hdac_bus *bus = azx_bus(chip);
 800         struct hdac_stream *s;
 801         int pending, ok;
 802
 803         if (!hda->irq_pending_warned) {
 804                 dev_info(chip->card->dev,
 805                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 806                          chip->card->number);
 807                 hda->irq_pending_warned = 1;
 808         }
 809
 810         for (;;) {
 811                 pending = 0;
 812                 spin_lock_irq(&bus->reg_lock);
 813                 list_for_each_entry(s, &bus->stream_list, list) {
 814                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 815                         if (!azx_dev->irq_pending ||
 816                             !s->substream ||
 817                             !s->running)
 818                                 continue;
 819                         ok = azx_position_ok(chip, azx_dev);
 820                         if (ok > 0) {
 821                                 azx_dev->irq_pending = 0;
 822                                 spin_unlock(&bus->reg_lock);
 823                                 snd_pcm_period_elapsed(s->substream);
 824                                 spin_lock(&bus->reg_lock);
 825                         } else if (ok < 0) {
 826                                 pending = 0;    /* too early */
 827                         } else
 828                                 pending++;
 829                 }
 830                 spin_unlock_irq(&bus->reg_lock);
 831                 if (!pending)
 832                         return;
 833                 msleep(1);
 834         }
 835 }
 836
 837 /* clear irq_pending flags and assure no on-going workq */
 838 static void azx_clear_irq_pending(struct azx *chip)
 839 {
 840         struct hdac_bus *bus = azx_bus(chip);
 841         struct hdac_stream *s;
 842
 843         spin_lock_irq(&bus->reg_lock);
 844         list_for_each_entry(s, &bus->stream_list, list) {
 845                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 846                 azx_dev->irq_pending = 0;
 847         }
 848         spin_unlock_irq(&bus->reg_lock);
 849 }
 850
 851 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 852 {
 853         struct hdac_bus *bus = azx_bus(chip);
 854
 855         if (request_irq(chip->pci->irq, azx_interrupt,
 856                         chip->msi ? 0 : IRQF_SHARED,
 857                         chip->card->irq_descr, chip)) {
 858                 dev_err(chip->card->dev,
 859                         "unable to grab IRQ %d, disabling device\n",
 860                         chip->pci->irq);
 861                 if (do_disconnect)
 862                         snd_card_disconnect(chip->card);
 863                 return -1;
 864         }
 865         bus->irq = chip->pci->irq;
 866         pci_intx(chip->pci, !chip->msi);
 867         return 0;
 868 }
 869
 870 /* get the current DMA position with correction on VIA chips */
 871 static unsigned int azx_via_get_position(struct azx *chip,
 872                                          struct azx_dev *azx_dev)
 873 {
 874         unsigned int link_pos, mini_pos, bound_pos;
 875         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 876         unsigned int fifo_size;
 877
 878         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 879         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 880                 /* Playback, no problem using link position */
 881                 return link_pos;
 882         }
 883
 884         /* Capture */
 885         /* For new chipset,
 886          * use mod to get the DMA position just like old chipset
 887          */
 888         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 889         mod_dma_pos %= azx_dev->core.period_bytes;
 890
 891         /* azx_dev->fifo_size can't get FIFO size of in stream.
 892          * Get from base address + offset.
 893          */
 894         fifo_size = readw(azx_bus(chip)->remap_addr +
 895                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 896
 897         if (azx_dev->insufficient) {
 898                 /* Link position never gather than FIFO size */
 899                 if (link_pos <= fifo_size)
 900                         return 0;
 901
 902                 azx_dev->insufficient = 0;
 903         }
 904
 905         if (link_pos <= fifo_size)
 906                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 907         else
 908                 mini_pos = link_pos - fifo_size;
 909
 910         /* Find nearest previous boudary */
 911         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 912         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 913         if (mod_link_pos >= fifo_size)
 914                 bound_pos = link_pos - mod_link_pos;
 915         else if (mod_dma_pos >= mod_mini_pos)
 916                 bound_pos = mini_pos - mod_mini_pos;
 917         else {
 918                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 919                 if (bound_pos >= azx_dev->core.bufsize)
 920                         bound_pos = 0;
 921         }
 922
 923         /* Calculate real DMA position we want */
 924         return bound_pos + mod_dma_pos;
 925 }
 926
 927 #define AMD_FIFO_SIZE   32
 928
 929 /* get the current DMA position with FIFO size correction */
 930 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 931 {
 932         struct snd_pcm_substream *substream = azx_dev->core.substream;
 933         struct snd_pcm_runtime *runtime = substream->runtime;
 934         unsigned int pos, delay;
 935
 936         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 937         if (!runtime)
 938                 return pos;
 939
 940         runtime->delay = AMD_FIFO_SIZE;
 941         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 942         if (azx_dev->insufficient) {
 943                 if (pos < delay) {
 944                         delay = pos;
 945                         runtime->delay = bytes_to_frames(runtime, pos);
 946                 } else {
 947                         azx_dev->insufficient = 0;
 948                 }
 949         }
 950
 951         /* correct the DMA position for capture stream */
 952         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 953                 if (pos < delay)
 954                         pos += azx_dev->core.bufsize;
 955                 pos -= delay;
 956         }
 957
 958         return pos;
 959 }
 960
 961 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 962                                    unsigned int pos)
 963 {
 964         struct snd_pcm_substream *substream = azx_dev->core.substream;
 965
 966         /* just read back the calculated value in the above */
 967         return substream->runtime->delay;
 968 }
 969
 970 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 971                                          struct azx_dev *azx_dev)
 972 {
 973         return _snd_hdac_chip_readl(azx_bus(chip),
 974                                     AZX_REG_VS_SDXDPIB_XBASE +
 975                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 976                                      azx_dev->core.index));
 977 }
 978
 979 /* get the current DMA position with correction on SKL+ chips */
 980 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 981 {
 982         /* DPIB register gives a more accurate position for playback */
 983         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 984                 return azx_skl_get_dpib_pos(chip, azx_dev);
 985
 986         /* For capture, we need to read posbuf, but it requires a delay
 987          * for the possible boundary overlap; the read of DPIB fetches the
 988          * actual posbuf
 989          */
 990         udelay(20);
 991         azx_skl_get_dpib_pos(chip, azx_dev);
 992         return azx_get_pos_posbuf(chip, azx_dev);
 993 }
 994
 995 #ifdef CONFIG_PM
 996 static DEFINE_MUTEX(card_list_lock);
 997 static LIST_HEAD(card_list);
 998
 999 static void azx_add_card_list(struct azx *chip)
1000 {
1001         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1002         mutex_lock(&card_list_lock);
1003         list_add(&hda->list, &card_list);
1004         mutex_unlock(&card_list_lock);
1005 }
1006
1007 static void azx_del_card_list(struct azx *chip)
1008 {
1009         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1010         mutex_lock(&card_list_lock);
1011         list_del_init(&hda->list);
1012         mutex_unlock(&card_list_lock);
1013 }
1014
1015 /* trigger power-save check at writing parameter */
1016 static int param_set_xint(const char *val, const struct kernel_param *kp)
1017 {
1018         struct hda_intel *hda;
1019         struct azx *chip;
1020         int prev = power_save;
1021         int ret = param_set_int(val, kp);
1022
1023         if (ret || prev == power_save)
1024                 return ret;
1025
1026         mutex_lock(&card_list_lock);
1027         list_for_each_entry(hda, &card_list, list) {
1028                 chip = &hda->chip;
1029                 if (!hda->probe_continued || chip->disabled)
1030                         continue;
1031                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1032         }
1033         mutex_unlock(&card_list_lock);
1034         return 0;
1035 }
1036 #else
1037 #define azx_add_card_list(chip) /* NOP */
1038 #define azx_del_card_list(chip) /* NOP */
1039 #endif /* CONFIG_PM */
1040
1041 #ifdef CONFIG_PM_SLEEP
1042 /*
1043  * power management
1044  */
1045 static int azx_suspend(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip;
1049         struct hda_intel *hda;
1050         struct hdac_bus *bus;
1051
1052         if (!card)
1053                 return 0;
1054
1055         chip = card->private_data;
1056         hda = container_of(chip, struct hda_intel, chip);
1057         if (chip->disabled || hda->init_failed || !chip->running)
1058                 return 0;
1059
1060         bus = azx_bus(chip);
1061         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1062         azx_clear_irq_pending(chip);
1063         azx_stop_chip(chip);
1064         azx_enter_link_reset(chip);
1065         if (bus->irq >= 0) {
1066                 free_irq(bus->irq, chip);
1067                 bus->irq = -1;
1068         }
1069
1070         if (chip->msi)
1071                 pci_disable_msi(chip->pci);
1072         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1073                 && hda->need_i915_power)
1074                 snd_hdac_display_power(bus, false);
1075
1076         trace_azx_suspend(chip);
1077         return 0;
1078 }
1079
1080 static int azx_resume(struct device *dev)
1081 {
1082         struct pci_dev *pci = to_pci_dev(dev);
1083         struct snd_card *card = dev_get_drvdata(dev);
1084         struct azx *chip;
1085         struct hda_intel *hda;
1086         struct hdac_bus *bus;
1087
1088         if (!card)
1089                 return 0;
1090
1091         chip = card->private_data;
1092         hda = container_of(chip, struct hda_intel, chip);
1093         bus = azx_bus(chip);
1094         if (chip->disabled || hda->init_failed || !chip->running)
1095                 return 0;
1096
1097         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1098                 snd_hdac_display_power(bus, true);
1099                 if (hda->need_i915_power)
1100                         snd_hdac_i915_set_bclk(bus);
1101         }
1102
1103         if (chip->msi)
1104                 if (pci_enable_msi(pci) < 0)
1105                         chip->msi = 0;
1106         if (azx_acquire_irq(chip, 1) < 0)
1107                 return -EIO;
1108         azx_init_pci(chip);
1109
1110         hda_intel_init_chip(chip, true);
1111
1112         /* power down again for link-controlled chips */
1113         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1114             !hda->need_i915_power)
1115                 snd_hdac_display_power(bus, false);
1116
1117         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1118
1119         trace_azx_resume(chip);
1120         return 0;
1121 }
1122
1123 /* put codec down to D3 at hibernation for Intel SKL+;
1124  * otherwise BIOS may still access the codec and screw up the driver
1125  */
1126 static int azx_freeze_noirq(struct device *dev)
1127 {
1128         struct snd_card *card = dev_get_drvdata(dev);
1129         struct azx *chip = card->private_data;
1130         struct pci_dev *pci = to_pci_dev(dev);
1131
1132         if (chip->driver_type == AZX_DRIVER_SKL)
1133                 pci_set_power_state(pci, PCI_D3hot);
1134
1135         return 0;
1136 }
1137
1138 static int azx_thaw_noirq(struct device *dev)
1139 {
1140         struct snd_card *card = dev_get_drvdata(dev);
1141         struct azx *chip = card->private_data;
1142         struct pci_dev *pci = to_pci_dev(dev);
1143
1144         if (chip->driver_type == AZX_DRIVER_SKL)
1145                 pci_set_power_state(pci, PCI_D0);
1146
1147         return 0;
1148 }
1149 #endif /* CONFIG_PM_SLEEP */
1150
1151 #ifdef CONFIG_PM
1152 static int azx_runtime_suspend(struct device *dev)
1153 {
1154         struct snd_card *card = dev_get_drvdata(dev);
1155         struct azx *chip;
1156         struct hda_intel *hda;
1157
1158         if (!card)
1159                 return 0;
1160
1161         chip = card->private_data;
1162         hda = container_of(chip, struct hda_intel, chip);
1163         if (chip->disabled || hda->init_failed)
1164                 return 0;
1165
1166         if (!azx_has_pm_runtime(chip))
1167                 return 0;
1168
1169         /* enable controller wake up event */
1170         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1171                   STATESTS_INT_MASK);
1172
1173         azx_stop_chip(chip);
1174         azx_enter_link_reset(chip);
1175         azx_clear_irq_pending(chip);
1176         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1177                 && hda->need_i915_power)
1178                 snd_hdac_display_power(azx_bus(chip), false);
1179
1180         trace_azx_runtime_suspend(chip);
1181         return 0;
1182 }
1183
1184 static int azx_runtime_resume(struct device *dev)
1185 {
1186         struct snd_card *card = dev_get_drvdata(dev);
1187         struct azx *chip;
1188         struct hda_intel *hda;
1189         struct hdac_bus *bus;
1190         struct hda_codec *codec;
1191         int status;
1192
1193         if (!card)
1194                 return 0;
1195
1196         chip = card->private_data;
1197         hda = container_of(chip, struct hda_intel, chip);
1198         bus = azx_bus(chip);
1199         if (chip->disabled || hda->init_failed)
1200                 return 0;
1201
1202         if (!azx_has_pm_runtime(chip))
1203                 return 0;
1204
1205         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1206                 snd_hdac_display_power(bus, true);
1207                 if (hda->need_i915_power)
1208                         snd_hdac_i915_set_bclk(bus);
1209         }
1210
1211         /* Read STATESTS before controller reset */
1212         status = azx_readw(chip, STATESTS);
1213
1214         azx_init_pci(chip);
1215         hda_intel_init_chip(chip, true);
1216
1217         if (status) {
1218                 list_for_each_codec(codec, &chip->bus)
1219                         if (status & (1 << codec->addr))
1220                                 schedule_delayed_work(&codec->jackpoll_work,
1221                                                       codec->jackpoll_interval);
1222         }
1223
1224         /* disable controller Wake Up event*/
1225         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1226                         ~STATESTS_INT_MASK);
1227
1228         /* power down again for link-controlled chips */
1229         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1230             !hda->need_i915_power)
1231                 snd_hdac_display_power(bus, false);
1232
1233         trace_azx_runtime_resume(chip);
1234         return 0;
1235 }
1236
1237 static int azx_runtime_idle(struct device *dev)
1238 {
1239         struct snd_card *card = dev_get_drvdata(dev);
1240         struct azx *chip;
1241         struct hda_intel *hda;
1242
1243         if (!card)
1244                 return 0;
1245
1246         chip = card->private_data;
1247         hda = container_of(chip, struct hda_intel, chip);
1248         if (chip->disabled || hda->init_failed)
1249                 return 0;
1250
1251         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1252             azx_bus(chip)->codec_powered || !chip->running)
1253                 return -EBUSY;
1254
1255         /* ELD notification gets broken when HD-audio bus is off */
1256         if (needs_eld_notify_link(hda))
1257                 return -EBUSY;
1258
1259         return 0;
1260 }
1261
1262 static const struct dev_pm_ops azx_pm = {
1263         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1264 #ifdef CONFIG_PM_SLEEP
1265         .freeze_noirq = azx_freeze_noirq,
1266         .thaw_noirq = azx_thaw_noirq,
1267 #endif
1268         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1269 };
1270
1271 #define AZX_PM_OPS      &azx_pm
1272 #else
1273 #define AZX_PM_OPS      NULL
1274 #endif /* CONFIG_PM */
1275
1276
1277 static int azx_probe_continue(struct azx *chip);
1278
1279 #ifdef SUPPORT_VGA_SWITCHEROO
1280 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1281
1282 static void azx_vs_set_state(struct pci_dev *pci,
1283                              enum vga_switcheroo_state state)
1284 {
1285         struct snd_card *card = pci_get_drvdata(pci);
1286         struct azx *chip = card->private_data;
1287         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1288         struct hda_codec *codec;
1289         bool disabled;
1290
1291         wait_for_completion(&hda->probe_wait);
1292         if (hda->init_failed)
1293                 return;
1294
1295         disabled = (state == VGA_SWITCHEROO_OFF);
1296         if (chip->disabled == disabled)
1297                 return;
1298
1299         if (!hda->probe_continued) {
1300                 chip->disabled = disabled;
1301                 if (!disabled) {
1302                         dev_info(chip->card->dev,
1303                                  "Start delayed initialization\n");
1304                         if (azx_probe_continue(chip) < 0) {
1305                                 dev_err(chip->card->dev, "initialization error\n");
1306                                 hda->init_failed = true;
1307                         }
1308                 }
1309         } else {
1310                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1311                          disabled ? "Disabling" : "Enabling");
1312                 if (disabled) {
1313                         list_for_each_codec(codec, &chip->bus) {
1314                                 pm_runtime_suspend(hda_codec_dev(codec));
1315                                 pm_runtime_disable(hda_codec_dev(codec));
1316                         }
1317                         pm_runtime_suspend(card->dev);
1318                         pm_runtime_disable(card->dev);
1319                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1320                          * however we have no ACPI handle, so pci/acpi can't put us there,
1321                          * put ourselves there */
1322                         pci->current_state = PCI_D3cold;
1323                         chip->disabled = true;
1324                         if (snd_hda_lock_devices(&chip->bus))
1325                                 dev_warn(chip->card->dev,
1326                                          "Cannot lock devices!\n");
1327                 } else {
1328                         snd_hda_unlock_devices(&chip->bus);
1329                         chip->disabled = false;
1330                         pm_runtime_enable(card->dev);
1331                         list_for_each_codec(codec, &chip->bus) {
1332                                 pm_runtime_enable(hda_codec_dev(codec));
1333                                 pm_runtime_resume(hda_codec_dev(codec));
1334                         }
1335                 }
1336         }
1337 }
1338
1339 static bool azx_vs_can_switch(struct pci_dev *pci)
1340 {
1341         struct snd_card *card = pci_get_drvdata(pci);
1342         struct azx *chip = card->private_data;
1343         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1344
1345         wait_for_completion(&hda->probe_wait);
1346         if (hda->init_failed)
1347                 return false;
1348         if (chip->disabled || !hda->probe_continued)
1349                 return true;
1350         if (snd_hda_lock_devices(&chip->bus))
1351                 return false;
1352         snd_hda_unlock_devices(&chip->bus);
1353         return true;
1354 }
1355
1356 /*
1357  * The discrete GPU cannot power down unless the HDA controller runtime
1358  * suspends, so activate runtime PM on codecs even if power_save == 0.
1359  */
1360 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1361 {
1362         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1363         struct hda_codec *codec;
1364
1365         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1366                 list_for_each_codec(codec, &chip->bus)
1367                         codec->auto_runtime_pm = 1;
1368                 /* reset the power save setup */
1369                 if (chip->running)
1370                         set_default_power_save(chip);
1371         }
1372 }
1373
1374 static void azx_vs_gpu_bound(struct pci_dev *pci,
1375                              enum vga_switcheroo_client_id client_id)
1376 {
1377         struct snd_card *card = pci_get_drvdata(pci);
1378         struct azx *chip = card->private_data;
1379         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1380
1381         if (client_id == VGA_SWITCHEROO_DIS)
1382                 hda->need_eld_notify_link = 0;
1383         setup_vga_switcheroo_runtime_pm(chip);
1384 }
1385
1386 static void init_vga_switcheroo(struct azx *chip)
1387 {
1388         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1389         struct pci_dev *p = get_bound_vga(chip->pci);
1390         if (p) {
1391                 dev_info(chip->card->dev,
1392                          "Handle vga_switcheroo audio client\n");
1393                 hda->use_vga_switcheroo = 1;
1394                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1395                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1396                 pci_dev_put(p);
1397         }
1398 }
1399
1400 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1401         .set_gpu_state = azx_vs_set_state,
1402         .can_switch = azx_vs_can_switch,
1403         .gpu_bound = azx_vs_gpu_bound,
1404 };
1405
1406 static int register_vga_switcheroo(struct azx *chip)
1407 {
1408         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1409         struct pci_dev *p;
1410         int err;
1411
1412         if (!hda->use_vga_switcheroo)
1413                 return 0;
1414
1415         p = get_bound_vga(chip->pci);
1416         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1417         pci_dev_put(p);
1418
1419         if (err < 0)
1420                 return err;
1421         hda->vga_switcheroo_registered = 1;
1422
1423         return 0;
1424 }
1425 #else
1426 #define init_vga_switcheroo(chip)               /* NOP */
1427 #define register_vga_switcheroo(chip)           0
1428 #define check_hdmi_disabled(pci)        false
1429 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1430 #endif /* SUPPORT_VGA_SWITCHER */
1431
1432 /*
1433  * destructor
1434  */
1435 static int azx_free(struct azx *chip)
1436 {
1437         struct pci_dev *pci = chip->pci;
1438         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1439         struct hdac_bus *bus = azx_bus(chip);
1440
1441         if (azx_has_pm_runtime(chip) && chip->running)
1442                 pm_runtime_get_noresume(&pci->dev);
1443         chip->running = 0;
1444
1445         azx_del_card_list(chip);
1446
1447         hda->init_failed = 1; /* to be sure */
1448         complete_all(&hda->probe_wait);
1449
1450         if (use_vga_switcheroo(hda)) {
1451                 if (chip->disabled && hda->probe_continued)
1452                         snd_hda_unlock_devices(&chip->bus);
1453                 if (hda->vga_switcheroo_registered)
1454                         vga_switcheroo_unregister_client(chip->pci);
1455         }
1456
1457         if (bus->chip_init) {
1458                 azx_clear_irq_pending(chip);
1459                 azx_stop_all_streams(chip);
1460                 azx_stop_chip(chip);
1461         }
1462
1463         if (bus->irq >= 0)
1464                 free_irq(bus->irq, (void*)chip);
1465         if (chip->msi)
1466                 pci_disable_msi(chip->pci);
1467         iounmap(bus->remap_addr);
1468
1469         azx_free_stream_pages(chip);
1470         azx_free_streams(chip);
1471         snd_hdac_bus_exit(bus);
1472
1473         if (chip->region_requested)
1474                 pci_release_regions(chip->pci);
1475
1476         pci_disable_device(chip->pci);
1477 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1478         release_firmware(chip->fw);
1479 #endif
1480
1481         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1482                 if (hda->need_i915_power)
1483                         snd_hdac_display_power(bus, false);
1484         }
1485         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1486                 snd_hdac_i915_exit(bus);
1487         kfree(hda);
1488
1489         return 0;
1490 }
1491
1492 static int azx_dev_disconnect(struct snd_device *device)
1493 {
1494         struct azx *chip = device->device_data;
1495         struct hdac_bus *bus = azx_bus(chip);
1496
1497         chip->bus.shutdown = 1;
1498         cancel_work_sync(&bus->unsol_work);
1499
1500         return 0;
1501 }
1502
1503 static int azx_dev_free(struct snd_device *device)
1504 {
1505         return azx_free(device->device_data);
1506 }
1507
1508 #ifdef SUPPORT_VGA_SWITCHEROO
1509 /*
1510  * Check of disabled HDMI controller by vga_switcheroo
1511  */
1512 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1513 {
1514         struct pci_dev *p;
1515
1516         /* check only discrete GPU */
1517         switch (pci->vendor) {
1518         case PCI_VENDOR_ID_ATI:
1519         case PCI_VENDOR_ID_AMD:
1520         case PCI_VENDOR_ID_NVIDIA:
1521                 if (pci->devfn == 1) {
1522                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1523                                                         pci->bus->number, 0);
1524                         if (p) {
1525                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1526                                         return p;
1527                                 pci_dev_put(p);
1528                         }
1529                 }
1530                 break;
1531         }
1532         return NULL;
1533 }
1534
1535 static bool check_hdmi_disabled(struct pci_dev *pci)
1536 {
1537         bool vga_inactive = false;
1538         struct pci_dev *p = get_bound_vga(pci);
1539
1540         if (p) {
1541                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1542                         vga_inactive = true;
1543                 pci_dev_put(p);
1544         }
1545         return vga_inactive;
1546 }
1547 #endif /* SUPPORT_VGA_SWITCHEROO */
1548
1549 /*
1550  * white/black-listing for position_fix
1551  */
1552 static struct snd_pci_quirk position_fix_list[] = {
1553         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1554         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1555         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1556         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1557         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1558         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1559         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1560         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1561         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1562         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1563         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1564         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1565         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1566         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1567         {}
1568 };
1569
1570 static int check_position_fix(struct azx *chip, int fix)
1571 {
1572         const struct snd_pci_quirk *q;
1573
1574         switch (fix) {
1575         case POS_FIX_AUTO:
1576         case POS_FIX_LPIB:
1577         case POS_FIX_POSBUF:
1578         case POS_FIX_VIACOMBO:
1579         case POS_FIX_COMBO:
1580         case POS_FIX_SKL:
1581         case POS_FIX_FIFO:
1582                 return fix;
1583         }
1584
1585         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1586         if (q) {
1587                 dev_info(chip->card->dev,
1588                          "position_fix set to %d for device %04x:%04x\n",
1589                          q->value, q->subvendor, q->subdevice);
1590                 return q->value;
1591         }
1592
1593         /* Check VIA/ATI HD Audio Controller exist */
1594         if (chip->driver_type == AZX_DRIVER_VIA) {
1595                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1596                 return POS_FIX_VIACOMBO;
1597         }
1598         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1599                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1600                 return POS_FIX_FIFO;
1601         }
1602         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1603                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1604                 return POS_FIX_LPIB;
1605         }
1606         if (chip->driver_type == AZX_DRIVER_SKL) {
1607                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1608                 return POS_FIX_SKL;
1609         }
1610         return POS_FIX_AUTO;
1611 }
1612
1613 static void assign_position_fix(struct azx *chip, int fix)
1614 {
1615         static azx_get_pos_callback_t callbacks[] = {
1616                 [POS_FIX_AUTO] = NULL,
1617                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1618                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1619                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1620                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1621                 [POS_FIX_SKL] = azx_get_pos_skl,
1622                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1623         };
1624
1625         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1626
1627         /* combo mode uses LPIB only for playback */
1628         if (fix == POS_FIX_COMBO)
1629                 chip->get_position[1] = NULL;
1630
1631         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1632             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1633                 chip->get_delay[0] = chip->get_delay[1] =
1634                         azx_get_delay_from_lpib;
1635         }
1636
1637         if (fix == POS_FIX_FIFO)
1638                 chip->get_delay[0] = chip->get_delay[1] =
1639                         azx_get_delay_from_fifo;
1640 }
1641
1642 /*
1643  * black-lists for probe_mask
1644  */
1645 static struct snd_pci_quirk probe_mask_list[] = {
1646         /* Thinkpad often breaks the controller communication when accessing
1647          * to the non-working (or non-existing) modem codec slot.
1648          */
1649         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1650         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1651         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1652         /* broken BIOS */
1653         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1654         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1655         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1656         /* forced codec slots */
1657         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1658         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1659         /* WinFast VP200 H (Teradici) user reported broken communication */
1660         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1661         {}
1662 };
1663
1664 #define AZX_FORCE_CODEC_MASK    0x100
1665
1666 static void check_probe_mask(struct azx *chip, int dev)
1667 {
1668         const struct snd_pci_quirk *q;
1669
1670         chip->codec_probe_mask = probe_mask[dev];
1671         if (chip->codec_probe_mask == -1) {
1672                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1673                 if (q) {
1674                         dev_info(chip->card->dev,
1675                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1676                                  q->value, q->subvendor, q->subdevice);
1677                         chip->codec_probe_mask = q->value;
1678                 }
1679         }
1680
1681         /* check forced option */
1682         if (chip->codec_probe_mask != -1 &&
1683             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1684                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1685                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1686                          (int)azx_bus(chip)->codec_mask);
1687         }
1688 }
1689
1690 /*
1691  * white/black-list for enable_msi
1692  */
1693 static struct snd_pci_quirk msi_black_list[] = {
1694         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1695         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1696         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1697         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1698         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1699         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1700         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1701         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1702         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1703         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1704         {}
1705 };
1706
1707 static void check_msi(struct azx *chip)
1708 {
1709         const struct snd_pci_quirk *q;
1710
1711         if (enable_msi >= 0) {
1712                 chip->msi = !!enable_msi;
1713                 return;
1714         }
1715         chip->msi = 1;  /* enable MSI as default */
1716         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1717         if (q) {
1718                 dev_info(chip->card->dev,
1719                          "msi for device %04x:%04x set to %d\n",
1720                          q->subvendor, q->subdevice, q->value);
1721                 chip->msi = q->value;
1722                 return;
1723         }
1724
1725         /* NVidia chipsets seem to cause troubles with MSI */
1726         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1727                 dev_info(chip->card->dev, "Disabling MSI\n");
1728                 chip->msi = 0;
1729         }
1730 }
1731
1732 /* check the snoop mode availability */
1733 static void azx_check_snoop_available(struct azx *chip)
1734 {
1735         int snoop = hda_snoop;
1736
1737         if (snoop >= 0) {
1738                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1739                          snoop ? "snoop" : "non-snoop");
1740                 chip->snoop = snoop;
1741                 chip->uc_buffer = !snoop;
1742                 return;
1743         }
1744
1745         snoop = true;
1746         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1747             chip->driver_type == AZX_DRIVER_VIA) {
1748                 /* force to non-snoop mode for a new VIA controller
1749                  * when BIOS is set
1750                  */
1751                 u8 val;
1752                 pci_read_config_byte(chip->pci, 0x42, &val);
1753                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1754                                       chip->pci->revision == 0x20))
1755                         snoop = false;
1756         }
1757
1758         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1759                 snoop = false;
1760
1761         chip->snoop = snoop;
1762         if (!snoop) {
1763                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1764                 /* C-Media requires non-cached pages only for CORB/RIRB */
1765                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1766                         chip->uc_buffer = true;
1767         }
1768 }
1769
1770 static void azx_probe_work(struct work_struct *work)
1771 {
1772         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1773         azx_probe_continue(&hda->chip);
1774 }
1775
1776 static int default_bdl_pos_adj(struct azx *chip)
1777 {
1778         /* some exceptions: Atoms seem problematic with value 1 */
1779         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1780                 switch (chip->pci->device) {
1781                 case 0x0f04: /* Baytrail */
1782                 case 0x2284: /* Braswell */
1783                         return 32;
1784                 }
1785         }
1786
1787         switch (chip->driver_type) {
1788         case AZX_DRIVER_ICH:
1789         case AZX_DRIVER_PCH:
1790                 return 1;
1791         default:
1792                 return 32;
1793         }
1794 }
1795
1796 /*
1797  * constructor
1798  */
1799 static const struct hdac_io_ops pci_hda_io_ops;
1800 static const struct hda_controller_ops pci_hda_ops;
1801
1802 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1803                       int dev, unsigned int driver_caps,
1804                       struct azx **rchip)
1805 {
1806         static struct snd_device_ops ops = {
1807                 .dev_disconnect = azx_dev_disconnect,
1808                 .dev_free = azx_dev_free,
1809         };
1810         struct hda_intel *hda;
1811         struct azx *chip;
1812         int err;
1813
1814         *rchip = NULL;
1815
1816         err = pci_enable_device(pci);
1817         if (err < 0)
1818                 return err;
1819
1820         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1821         if (!hda) {
1822                 pci_disable_device(pci);
1823                 return -ENOMEM;
1824         }
1825
1826         chip = &hda->chip;
1827         mutex_init(&chip->open_mutex);
1828         chip->card = card;
1829         chip->pci = pci;
1830         chip->ops = &pci_hda_ops;
1831         chip->driver_caps = driver_caps;
1832         chip->driver_type = driver_caps & 0xff;
1833         check_msi(chip);
1834         chip->dev_index = dev;
1835         chip->jackpoll_ms = jackpoll_ms;
1836         INIT_LIST_HEAD(&chip->pcm_list);
1837         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1838         INIT_LIST_HEAD(&hda->list);
1839         init_vga_switcheroo(chip);
1840         init_completion(&hda->probe_wait);
1841
1842         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1843
1844         check_probe_mask(chip, dev);
1845
1846         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1847                 chip->fallback_to_single_cmd = 1;
1848         else /* explicitly set to single_cmd or not */
1849                 chip->single_cmd = single_cmd;
1850
1851         azx_check_snoop_available(chip);
1852
1853         if (bdl_pos_adj[dev] < 0)
1854                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1855         else
1856                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1857
1858         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1859         if (IS_CFL(pci) || IS_CNL(pci))
1860                 chip->polling_mode = 1;
1861
1862         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1863         if (err < 0) {
1864                 kfree(hda);
1865                 pci_disable_device(pci);
1866                 return err;
1867         }
1868
1869         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1870                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1871                 chip->bus.needs_damn_long_delay = 1;
1872         }
1873
1874         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1875         if (err < 0) {
1876                 dev_err(card->dev, "Error creating device [card]!\n");
1877                 azx_free(chip);
1878                 return err;
1879         }
1880
1881         /* continue probing in work context as may trigger request module */
1882         INIT_WORK(&hda->probe_work, azx_probe_work);
1883
1884         *rchip = chip;
1885
1886         return 0;
1887 }
1888
1889 static int azx_first_init(struct azx *chip)
1890 {
1891         int dev = chip->dev_index;
1892         struct pci_dev *pci = chip->pci;
1893         struct snd_card *card = chip->card;
1894         struct hdac_bus *bus = azx_bus(chip);
1895         int err;
1896         unsigned short gcap;
1897         unsigned int dma_bits = 64;
1898
1899 #if BITS_PER_LONG != 64
1900         /* Fix up base address on ULI M5461 */
1901         if (chip->driver_type == AZX_DRIVER_ULI) {
1902                 u16 tmp3;
1903                 pci_read_config_word(pci, 0x40, &tmp3);
1904                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1905                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1906         }
1907 #endif
1908
1909         err = pci_request_regions(pci, "ICH HD audio");
1910         if (err < 0)
1911                 return err;
1912         chip->region_requested = 1;
1913
1914         bus->addr = pci_resource_start(pci, 0);
1915         bus->remap_addr = pci_ioremap_bar(pci, 0);
1916         if (bus->remap_addr == NULL) {
1917                 dev_err(card->dev, "ioremap error\n");
1918                 return -ENXIO;
1919         }
1920
1921         if (chip->driver_type == AZX_DRIVER_SKL)
1922                 snd_hdac_bus_parse_capabilities(bus);
1923
1924         /*
1925          * Some Intel CPUs has always running timer (ART) feature and
1926          * controller may have Global time sync reporting capability, so
1927          * check both of these before declaring synchronized time reporting
1928          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1929          */
1930         chip->gts_present = false;
1931
1932 #ifdef CONFIG_X86
1933         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1934                 chip->gts_present = true;
1935 #endif
1936
1937         if (chip->msi) {
1938                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1939                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1940                         pci->no_64bit_msi = true;
1941                 }
1942                 if (pci_enable_msi(pci) < 0)
1943                         chip->msi = 0;
1944         }
1945
1946         pci_set_master(pci);
1947         synchronize_irq(bus->irq);
1948
1949         gcap = azx_readw(chip, GCAP);
1950         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1951
1952         /* AMD devices support 40 or 48bit DMA, take the safe one */
1953         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1954                 dma_bits = 40;
1955
1956         /* disable SB600 64bit support for safety */
1957         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1958                 struct pci_dev *p_smbus;
1959                 dma_bits = 40;
1960                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1961                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1962                                          NULL);
1963                 if (p_smbus) {
1964                         if (p_smbus->revision < 0x30)
1965                                 gcap &= ~AZX_GCAP_64OK;
1966                         pci_dev_put(p_smbus);
1967                 }
1968         }
1969
1970         /* NVidia hardware normally only supports up to 40 bits of DMA */
1971         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1972                 dma_bits = 40;
1973
1974         /* disable 64bit DMA address on some devices */
1975         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1976                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1977                 gcap &= ~AZX_GCAP_64OK;
1978         }
1979
1980         /* disable buffer size rounding to 128-byte multiples if supported */
1981         if (align_buffer_size >= 0)
1982                 chip->align_buffer_size = !!align_buffer_size;
1983         else {
1984                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1985                         chip->align_buffer_size = 0;
1986                 else
1987                         chip->align_buffer_size = 1;
1988         }
1989
1990         /* allow 64bit DMA address if supported by H/W */
1991         if (!(gcap & AZX_GCAP_64OK))
1992                 dma_bits = 32;
1993         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1994                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1995         } else {
1996                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1997                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1998         }
1999
2000         /* read number of streams from GCAP register instead of using
2001          * hardcoded value
2002          */
2003         chip->capture_streams = (gcap >> 8) & 0x0f;
2004         chip->playback_streams = (gcap >> 12) & 0x0f;
2005         if (!chip->playback_streams && !chip->capture_streams) {
2006                 /* gcap didn't give any info, switching to old method */
2007
2008                 switch (chip->driver_type) {
2009                 case AZX_DRIVER_ULI:
2010                         chip->playback_streams = ULI_NUM_PLAYBACK;
2011                         chip->capture_streams = ULI_NUM_CAPTURE;
2012                         break;
2013                 case AZX_DRIVER_ATIHDMI:
2014                 case AZX_DRIVER_ATIHDMI_NS:
2015                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2016                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2017                         break;
2018                 case AZX_DRIVER_GENERIC:
2019                 default:
2020                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2021                         chip->capture_streams = ICH6_NUM_CAPTURE;
2022                         break;
2023                 }
2024         }
2025         chip->capture_index_offset = 0;
2026         chip->playback_index_offset = chip->capture_streams;
2027         chip->num_streams = chip->playback_streams + chip->capture_streams;
2028
2029         /* sanity check for the SDxCTL.STRM field overflow */
2030         if (chip->num_streams > 15 &&
2031             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2032                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2033                          "forcing separate stream tags", chip->num_streams);
2034                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2035         }
2036
2037         /* initialize streams */
2038         err = azx_init_streams(chip);
2039         if (err < 0)
2040                 return err;
2041
2042         err = azx_alloc_stream_pages(chip);
2043         if (err < 0)
2044                 return err;
2045
2046         /* initialize chip */
2047         azx_init_pci(chip);
2048
2049         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2050                 snd_hdac_i915_set_bclk(bus);
2051
2052         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2053
2054         /* codec detection */
2055         if (!azx_bus(chip)->codec_mask) {
2056                 dev_err(card->dev, "no codecs found!\n");
2057                 /* keep running the rest for the runtime PM */
2058         }
2059
2060         if (azx_acquire_irq(chip, 0) < 0)
2061                 return -EBUSY;
2062
2063         strcpy(card->driver, "HDA-Intel");
2064         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2065                 sizeof(card->shortname));
2066         snprintf(card->longname, sizeof(card->longname),
2067                  "%s at 0x%lx irq %i",
2068                  card->shortname, bus->addr, bus->irq);
2069
2070         return 0;
2071 }
2072
2073 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2074 /* callback from request_firmware_nowait() */
2075 static void azx_firmware_cb(const struct firmware *fw, void *context)
2076 {
2077         struct snd_card *card = context;
2078         struct azx *chip = card->private_data;
2079
2080         if (fw)
2081                 chip->fw = fw;
2082         else
2083                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2084         if (!chip->disabled) {
2085                 /* continue probing */
2086                 azx_probe_continue(chip);
2087         }
2088 }
2089 #endif
2090
2091 /*
2092  * HDA controller ops.
2093  */
2094
2095 /* PCI register access. */
2096 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2097 {
2098         writel(value, addr);
2099 }
2100
2101 static u32 pci_azx_readl(u32 __iomem *addr)
2102 {
2103         return readl(addr);
2104 }
2105
2106 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2107 {
2108         writew(value, addr);
2109 }
2110
2111 static u16 pci_azx_readw(u16 __iomem *addr)
2112 {
2113         return readw(addr);
2114 }
2115
2116 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2117 {
2118         writeb(value, addr);
2119 }
2120
2121 static u8 pci_azx_readb(u8 __iomem *addr)
2122 {
2123         return readb(addr);
2124 }
2125
2126 static int disable_msi_reset_irq(struct azx *chip)
2127 {
2128         struct hdac_bus *bus = azx_bus(chip);
2129         int err;
2130
2131         free_irq(bus->irq, chip);
2132         bus->irq = -1;
2133         pci_disable_msi(chip->pci);
2134         chip->msi = 0;
2135         err = azx_acquire_irq(chip, 1);
2136         if (err < 0)
2137                 return err;
2138
2139         return 0;
2140 }
2141
2142 /* DMA page allocation helpers.  */
2143 static int dma_alloc_pages(struct hdac_bus *bus,
2144                            int type,
2145                            size_t size,
2146                            struct snd_dma_buffer *buf)
2147 {
2148         struct azx *chip = bus_to_azx(bus);
2149         int err;
2150
2151         err = snd_dma_alloc_pages(type,
2152                                   bus->dev,
2153                                   size, buf);
2154         if (err < 0)
2155                 return err;
2156         mark_pages_wc(chip, buf, true);
2157         return 0;
2158 }
2159
2160 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2161 {
2162         struct azx *chip = bus_to_azx(bus);
2163
2164         mark_pages_wc(chip, buf, false);
2165         snd_dma_free_pages(buf);
2166 }
2167
2168 static int substream_alloc_pages(struct azx *chip,
2169                                  struct snd_pcm_substream *substream,
2170                                  size_t size)
2171 {
2172         struct azx_dev *azx_dev = get_azx_dev(substream);
2173         int ret;
2174
2175         mark_runtime_wc(chip, azx_dev, substream, false);
2176         ret = snd_pcm_lib_malloc_pages(substream, size);
2177         if (ret < 0)
2178                 return ret;
2179         mark_runtime_wc(chip, azx_dev, substream, true);
2180         return 0;
2181 }
2182
2183 static int substream_free_pages(struct azx *chip,
2184                                 struct snd_pcm_substream *substream)
2185 {
2186         struct azx_dev *azx_dev = get_azx_dev(substream);
2187         mark_runtime_wc(chip, azx_dev, substream, false);
2188         return snd_pcm_lib_free_pages(substream);
2189 }
2190
2191 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2192                              struct vm_area_struct *area)
2193 {
2194 #ifdef CONFIG_X86
2195         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2196         struct azx *chip = apcm->chip;
2197         if (chip->uc_buffer)
2198                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2199 #endif
2200 }
2201
2202 static const struct hdac_io_ops pci_hda_io_ops = {
2203         .reg_writel = pci_azx_writel,
2204         .reg_readl = pci_azx_readl,
2205         .reg_writew = pci_azx_writew,
2206         .reg_readw = pci_azx_readw,
2207         .reg_writeb = pci_azx_writeb,
2208         .reg_readb = pci_azx_readb,
2209         .dma_alloc_pages = dma_alloc_pages,
2210         .dma_free_pages = dma_free_pages,
2211 };
2212
2213 /* Blacklist for skipping the whole probe:
2214  * some HD-audio PCI entries are exposed without any codecs, and such devices
2215  * should be ignored from the beginning.
2216  */
2217 static const struct pci_device_id driver_blacklist[] = {
2218         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2219         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2220         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2221         {}
2222 };
2223
2224 static const struct hda_controller_ops pci_hda_ops = {
2225         .disable_msi_reset_irq = disable_msi_reset_irq,
2226         .substream_alloc_pages = substream_alloc_pages,
2227         .substream_free_pages = substream_free_pages,
2228         .pcm_mmap_prepare = pcm_mmap_prepare,
2229         .position_check = azx_position_check,
2230         .link_power = azx_intel_link_power,
2231 };
2232
2233 static int azx_probe(struct pci_dev *pci,
2234                      const struct pci_device_id *pci_id)
2235 {
2236         static int dev;
2237         struct snd_card *card;
2238         struct hda_intel *hda;
2239         struct azx *chip;
2240         bool schedule_probe;
2241         int err;
2242
2243         if (pci_match_id(driver_blacklist, pci)) {
2244                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2245                 return -ENODEV;
2246         }
2247
2248         if (dev >= SNDRV_CARDS)
2249                 return -ENODEV;
2250         if (!enable[dev]) {
2251                 dev++;
2252                 return -ENOENT;
2253         }
2254
2255         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2256                            0, &card);
2257         if (err < 0) {
2258                 dev_err(&pci->dev, "Error creating card!\n");
2259                 return err;
2260         }
2261
2262         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2263         if (err < 0)
2264                 goto out_free;
2265         card->private_data = chip;
2266         hda = container_of(chip, struct hda_intel, chip);
2267
2268         pci_set_drvdata(pci, card);
2269
2270         err = register_vga_switcheroo(chip);
2271         if (err < 0) {
2272                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2273                 goto out_free;
2274         }
2275
2276         if (check_hdmi_disabled(pci)) {
2277                 dev_info(card->dev, "VGA controller is disabled\n");
2278                 dev_info(card->dev, "Delaying initialization\n");
2279                 chip->disabled = true;
2280         }
2281
2282         schedule_probe = !chip->disabled;
2283
2284 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2285         if (patch[dev] && *patch[dev]) {
2286                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2287                          patch[dev]);
2288                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2289                                               &pci->dev, GFP_KERNEL, card,
2290                                               azx_firmware_cb);
2291                 if (err < 0)
2292                         goto out_free;
2293                 schedule_probe = false; /* continued in azx_firmware_cb() */
2294         }
2295 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2296
2297 #ifndef CONFIG_SND_HDA_I915
2298         if (CONTROLLER_IN_GPU(pci))
2299                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2300 #endif
2301
2302         if (schedule_probe)
2303                 schedule_work(&hda->probe_work);
2304
2305         dev++;
2306         if (chip->disabled)
2307                 complete_all(&hda->probe_wait);
2308         return 0;
2309
2310 out_free:
2311         snd_card_free(card);
2312         return err;
2313 }
2314
2315 #ifdef CONFIG_PM
2316 /* On some boards setting power_save to a non 0 value leads to clicking /
2317  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2318  * figure out how to avoid these sounds, but that is not always feasible.
2319  * So we keep a list of devices where we disable powersaving as its known
2320  * to causes problems on these devices.
2321  */
2322 static struct snd_pci_quirk power_save_blacklist[] = {
2323         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2324         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2325         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2326         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2327         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2328         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2329         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2330         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2331         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2332         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2333         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2334         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2335         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2336         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2337         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2338         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2339         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2340         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2341         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2342         /* https://bugs.launchpad.net/bugs/1821663 */
2343         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2344         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2345         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2346         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2347         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2348         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2349         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2350         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2351         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2352         /* https://bugs.launchpad.net/bugs/1821663 */
2353         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2354         {}
2355 };
2356 #endif /* CONFIG_PM */
2357
2358 static void set_default_power_save(struct azx *chip)
2359 {
2360         int val = power_save;
2361
2362 #ifdef CONFIG_PM
2363         if (pm_blacklist) {
2364                 const struct snd_pci_quirk *q;
2365
2366                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2367                 if (q && val) {
2368                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2369                                  q->subvendor, q->subdevice);
2370                         val = 0;
2371                 }
2372         }
2373 #endif /* CONFIG_PM */
2374         snd_hda_set_power_save(&chip->bus, val * 1000);
2375 }
2376
2377 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2378 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2379         [AZX_DRIVER_NVIDIA] = 8,
2380         [AZX_DRIVER_TERA] = 1,
2381 };
2382
2383 static int azx_probe_continue(struct azx *chip)
2384 {
2385         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2386         struct hdac_bus *bus = azx_bus(chip);
2387         struct pci_dev *pci = chip->pci;
2388         int dev = chip->dev_index;
2389         int err;
2390
2391         to_hda_bus(bus)->bus_probing = 1;
2392         hda->probe_continued = 1;
2393
2394         /* bind with i915 if needed */
2395         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2396                 err = snd_hdac_i915_init(bus);
2397                 if (err < 0) {
2398                         /* if the controller is bound only with HDMI/DP
2399                          * (for HSW and BDW), we need to abort the probe;
2400                          * for other chips, still continue probing as other
2401                          * codecs can be on the same link.
2402                          */
2403                         if (CONTROLLER_IN_GPU(pci)) {
2404                                 dev_err(chip->card->dev,
2405                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2406                                 goto out_free;
2407                         } else {
2408                                 /* don't bother any longer */
2409                                 chip->driver_caps &=
2410                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2411                         }
2412                 }
2413         }
2414
2415         /* Request display power well for the HDA controller or codec. For
2416          * Haswell/Broadwell, both the display HDA controller and codec need
2417          * this power. For other platforms, like Baytrail/Braswell, only the
2418          * display codec needs the power and it can be released after probe.
2419          */
2420         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2421                 /* HSW/BDW controllers need this power */
2422                 if (CONTROLLER_IN_GPU(pci))
2423                         hda->need_i915_power = 1;
2424
2425                 err = snd_hdac_display_power(bus, true);
2426                 if (err < 0) {
2427                         dev_err(chip->card->dev,
2428                                 "Cannot turn on display power on i915\n");
2429                         goto i915_power_fail;
2430                 }
2431         }
2432
2433         err = azx_first_init(chip);
2434         if (err < 0)
2435                 goto out_free;
2436
2437 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2438         chip->beep_mode = beep_mode[dev];
2439 #endif
2440
2441         /* create codec instances */
2442         if (bus->codec_mask) {
2443                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2444                 if (err < 0)
2445                         goto out_free;
2446         }
2447
2448 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2449         if (chip->fw) {
2450                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2451                                          chip->fw->data);
2452                 if (err < 0)
2453                         goto out_free;
2454 #ifndef CONFIG_PM
2455                 release_firmware(chip->fw); /* no longer needed */
2456                 chip->fw = NULL;
2457 #endif
2458         }
2459 #endif
2460         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2461                 err = azx_codec_configure(chip);
2462                 if (err < 0)
2463                         goto out_free;
2464         }
2465
2466         err = snd_card_register(chip->card);
2467         if (err < 0)
2468                 goto out_free;
2469
2470         setup_vga_switcheroo_runtime_pm(chip);
2471
2472         chip->running = 1;
2473         azx_add_card_list(chip);
2474
2475         set_default_power_save(chip);
2476
2477         if (azx_has_pm_runtime(chip)) {
2478                 pm_runtime_use_autosuspend(&pci->dev);
2479                 pm_runtime_put_autosuspend(&pci->dev);
2480         }
2481
2482 out_free:
2483         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2484                 && !hda->need_i915_power)
2485                 snd_hdac_display_power(bus, false);
2486
2487 i915_power_fail:
2488         if (err < 0)
2489                 hda->init_failed = 1;
2490         complete_all(&hda->probe_wait);
2491         to_hda_bus(bus)->bus_probing = 0;
2492         return err;
2493 }
2494
2495 static void azx_remove(struct pci_dev *pci)
2496 {
2497         struct snd_card *card = pci_get_drvdata(pci);
2498         struct azx *chip;
2499         struct hda_intel *hda;
2500
2501         if (card) {
2502                 /* cancel the pending probing work */
2503                 chip = card->private_data;
2504                 hda = container_of(chip, struct hda_intel, chip);
2505                 /* FIXME: below is an ugly workaround.
2506                  * Both device_release_driver() and driver_probe_device()
2507                  * take *both* the device's and its parent's lock before
2508                  * calling the remove() and probe() callbacks.  The codec
2509                  * probe takes the locks of both the codec itself and its
2510                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2511                  * the PCI controller is unbound, it takes its lock, too
2512                  * ==> ouch, a deadlock!
2513                  * As a workaround, we unlock temporarily here the controller
2514                  * device during cancel_work_sync() call.
2515                  */
2516                 device_unlock(&pci->dev);
2517                 cancel_work_sync(&hda->probe_work);
2518                 device_lock(&pci->dev);
2519
2520                 snd_card_free(card);
2521         }
2522 }
2523
2524 static void azx_shutdown(struct pci_dev *pci)
2525 {
2526         struct snd_card *card = pci_get_drvdata(pci);
2527         struct azx *chip;
2528
2529         if (!card)
2530                 return;
2531         chip = card->private_data;
2532         if (chip && chip->running)
2533                 azx_stop_chip(chip);
2534 }
2535
2536 /* PCI IDs */
2537 static const struct pci_device_id azx_ids[] = {
2538         /* CPT */
2539         { PCI_DEVICE(0x8086, 0x1c20),
2540           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2541         /* PBG */
2542         { PCI_DEVICE(0x8086, 0x1d20),
2543           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2544         /* Panther Point */
2545         { PCI_DEVICE(0x8086, 0x1e20),
2546           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2547         /* Lynx Point */
2548         { PCI_DEVICE(0x8086, 0x8c20),
2549           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2550         /* 9 Series */
2551         { PCI_DEVICE(0x8086, 0x8ca0),
2552           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2553         /* Wellsburg */
2554         { PCI_DEVICE(0x8086, 0x8d20),
2555           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2556         { PCI_DEVICE(0x8086, 0x8d21),
2557           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2558         /* Lewisburg */
2559         { PCI_DEVICE(0x8086, 0xa1f0),
2560           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2561         { PCI_DEVICE(0x8086, 0xa270),
2562           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2563         /* Lynx Point-LP */
2564         { PCI_DEVICE(0x8086, 0x9c20),
2565           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2566         /* Lynx Point-LP */
2567         { PCI_DEVICE(0x8086, 0x9c21),
2568           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2569         /* Wildcat Point-LP */
2570         { PCI_DEVICE(0x8086, 0x9ca0),
2571           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2572         /* Sunrise Point */
2573         { PCI_DEVICE(0x8086, 0xa170),
2574           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2575         /* Sunrise Point-LP */
2576         { PCI_DEVICE(0x8086, 0x9d70),
2577           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2578         /* Kabylake */
2579         { PCI_DEVICE(0x8086, 0xa171),
2580           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2581         /* Kabylake-LP */
2582         { PCI_DEVICE(0x8086, 0x9d71),
2583           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2584         /* Kabylake-H */
2585         { PCI_DEVICE(0x8086, 0xa2f0),
2586           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2587         /* Coffelake */
2588         { PCI_DEVICE(0x8086, 0xa348),
2589           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2590         /* Cannonlake */
2591         { PCI_DEVICE(0x8086, 0x9dc8),
2592           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2593         /* Icelake */
2594         { PCI_DEVICE(0x8086, 0x34c8),
2595           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2596         /* Broxton-P(Apollolake) */
2597         { PCI_DEVICE(0x8086, 0x5a98),
2598           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2599         /* Broxton-T */
2600         { PCI_DEVICE(0x8086, 0x1a98),
2601           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2602         /* Gemini-Lake */
2603         { PCI_DEVICE(0x8086, 0x3198),
2604           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2605         /* Haswell */
2606         { PCI_DEVICE(0x8086, 0x0a0c),
2607           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2608         { PCI_DEVICE(0x8086, 0x0c0c),
2609           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2610         { PCI_DEVICE(0x8086, 0x0d0c),
2611           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2612         /* Broadwell */
2613         { PCI_DEVICE(0x8086, 0x160c),
2614           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2615         /* 5 Series/3400 */
2616         { PCI_DEVICE(0x8086, 0x3b56),
2617           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2618         /* Poulsbo */
2619         { PCI_DEVICE(0x8086, 0x811b),
2620           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2621         /* Oaktrail */
2622         { PCI_DEVICE(0x8086, 0x080a),
2623           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2624         /* BayTrail */
2625         { PCI_DEVICE(0x8086, 0x0f04),
2626           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2627         /* Braswell */
2628         { PCI_DEVICE(0x8086, 0x2284),
2629           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2630         /* ICH6 */
2631         { PCI_DEVICE(0x8086, 0x2668),
2632           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2633         /* ICH7 */
2634         { PCI_DEVICE(0x8086, 0x27d8),
2635           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2636         /* ESB2 */
2637         { PCI_DEVICE(0x8086, 0x269a),
2638           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2639         /* ICH8 */
2640         { PCI_DEVICE(0x8086, 0x284b),
2641           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2642         /* ICH9 */
2643         { PCI_DEVICE(0x8086, 0x293e),
2644           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2645         /* ICH9 */
2646         { PCI_DEVICE(0x8086, 0x293f),
2647           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2648         /* ICH10 */
2649         { PCI_DEVICE(0x8086, 0x3a3e),
2650           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2651         /* ICH10 */
2652         { PCI_DEVICE(0x8086, 0x3a6e),
2653           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2654         /* Generic Intel */
2655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2656           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2657           .class_mask = 0xffffff,
2658           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2659         /* ATI SB 450/600/700/800/900 */
2660         { PCI_DEVICE(0x1002, 0x437b),
2661           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2662         { PCI_DEVICE(0x1002, 0x4383),
2663           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2664         /* AMD Hudson */
2665         { PCI_DEVICE(0x1022, 0x780d),
2666           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2667         /* AMD, X370 & co */
2668         { PCI_DEVICE(0x1022, 0x1457),
2669           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2670         /* AMD, X570 & co */
2671         { PCI_DEVICE(0x1022, 0x1487),
2672           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2673         /* AMD Stoney */
2674         { PCI_DEVICE(0x1022, 0x157a),
2675           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2676                          AZX_DCAPS_PM_RUNTIME },
2677         /* AMD Raven */
2678         { PCI_DEVICE(0x1022, 0x15e3),
2679           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2680         /* ATI HDMI */
2681         { PCI_DEVICE(0x1002, 0x0002),
2682           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2683         { PCI_DEVICE(0x1002, 0x1308),
2684           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2685         { PCI_DEVICE(0x1002, 0x157a),
2686           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2687         { PCI_DEVICE(0x1002, 0x15b3),
2688           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2689         { PCI_DEVICE(0x1002, 0x793b),
2690           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2691         { PCI_DEVICE(0x1002, 0x7919),
2692           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2693         { PCI_DEVICE(0x1002, 0x960f),
2694           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2695         { PCI_DEVICE(0x1002, 0x970f),
2696           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2697         { PCI_DEVICE(0x1002, 0x9840),
2698           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2699         { PCI_DEVICE(0x1002, 0xaa00),
2700           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2701         { PCI_DEVICE(0x1002, 0xaa08),
2702           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2703         { PCI_DEVICE(0x1002, 0xaa10),
2704           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2705         { PCI_DEVICE(0x1002, 0xaa18),
2706           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2707         { PCI_DEVICE(0x1002, 0xaa20),
2708           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2709         { PCI_DEVICE(0x1002, 0xaa28),
2710           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2711         { PCI_DEVICE(0x1002, 0xaa30),
2712           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2713         { PCI_DEVICE(0x1002, 0xaa38),
2714           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2715         { PCI_DEVICE(0x1002, 0xaa40),
2716           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2717         { PCI_DEVICE(0x1002, 0xaa48),
2718           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2719         { PCI_DEVICE(0x1002, 0xaa50),
2720           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2721         { PCI_DEVICE(0x1002, 0xaa58),
2722           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2723         { PCI_DEVICE(0x1002, 0xaa60),
2724           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2725         { PCI_DEVICE(0x1002, 0xaa68),
2726           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2727         { PCI_DEVICE(0x1002, 0xaa80),
2728           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2729         { PCI_DEVICE(0x1002, 0xaa88),
2730           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2731         { PCI_DEVICE(0x1002, 0xaa90),
2732           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2733         { PCI_DEVICE(0x1002, 0xaa98),
2734           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2735         { PCI_DEVICE(0x1002, 0x9902),
2736           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2737         { PCI_DEVICE(0x1002, 0xaaa0),
2738           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2739         { PCI_DEVICE(0x1002, 0xaaa8),
2740           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2741         { PCI_DEVICE(0x1002, 0xaab0),
2742           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2743         { PCI_DEVICE(0x1002, 0xaac0),
2744           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2745         { PCI_DEVICE(0x1002, 0xaac8),
2746           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2747         { PCI_DEVICE(0x1002, 0xaad8),
2748           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2749         { PCI_DEVICE(0x1002, 0xaae8),
2750           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2751         { PCI_DEVICE(0x1002, 0xaae0),
2752           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2753         { PCI_DEVICE(0x1002, 0xaaf0),
2754           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2755         /* VIA VT8251/VT8237A */
2756         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2757         /* VIA GFX VT7122/VX900 */
2758         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2759         /* VIA GFX VT6122/VX11 */
2760         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2761         /* SIS966 */
2762         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2763         /* ULI M5461 */
2764         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2765         /* NVIDIA MCP */
2766         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2767           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2768           .class_mask = 0xffffff,
2769           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2770         /* Teradici */
2771         { PCI_DEVICE(0x6549, 0x1200),
2772           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2773         { PCI_DEVICE(0x6549, 0x2200),
2774           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2775         /* Creative X-Fi (CA0110-IBG) */
2776         /* CTHDA chips */
2777         { PCI_DEVICE(0x1102, 0x0010),
2778           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2779         { PCI_DEVICE(0x1102, 0x0012),
2780           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2781 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2782         /* the following entry conflicts with snd-ctxfi driver,
2783          * as ctxfi driver mutates from HD-audio to native mode with
2784          * a special command sequence.
2785          */
2786         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2787           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2788           .class_mask = 0xffffff,
2789           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2790           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2791 #else
2792         /* this entry seems still valid -- i.e. without emu20kx chip */
2793         { PCI_DEVICE(0x1102, 0x0009),
2794           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2795           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2796 #endif
2797         /* CM8888 */
2798         { PCI_DEVICE(0x13f6, 0x5011),
2799           .driver_data = AZX_DRIVER_CMEDIA |
2800           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2801         /* Vortex86MX */
2802         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2803         /* VMware HDAudio */
2804         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2805         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2806         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2807           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2808           .class_mask = 0xffffff,
2809           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2810         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2811           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2812           .class_mask = 0xffffff,
2813           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2814         { 0, }
2815 };
2816 MODULE_DEVICE_TABLE(pci, azx_ids);
2817
2818 /* pci_driver definition */
2819 static struct pci_driver azx_driver = {
2820         .name = KBUILD_MODNAME,
2821         .id_table = azx_ids,
2822         .probe = azx_probe,
2823         .remove = azx_remove,
2824         .shutdown = azx_shutdown,
2825         .driver = {
2826                 .pm = AZX_PM_OPS,
2827         },
2828 };
2829
2830 module_pci_driver(azx_driver);