sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80 };
  81
  82 /* Defines for ATI HD Audio support in SB450 south bridge */
  83 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  84 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  85
  86 /* Defines for Nvidia HDA support */
  87 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  88 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  89 #define NVIDIA_HDA_ISTRM_COH          0x4d
  90 #define NVIDIA_HDA_OSTRM_COH          0x4c
  91 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  92
  93 /* Defines for Intel SCH HDA snoop control */
  94 #define INTEL_HDA_CGCTL  0x48
  95 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  96 #define INTEL_SCH_HDA_DEVC      0x78
  97 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  98
  99 /* Define IN stream 0 FIFO size offset in VIA controller */
 100 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 101 /* Define VIA HD Audio Device ID*/
 102 #define VIA_HDAC_DEVICE_ID              0x3288
 103
 104 /* max number of SDs */
 105 /* ICH, ATI and VIA have 4 playback and 4 capture */
 106 #define ICH6_NUM_CAPTURE        4
 107 #define ICH6_NUM_PLAYBACK       4
 108
 109 /* ULI has 6 playback and 5 capture */
 110 #define ULI_NUM_CAPTURE         5
 111 #define ULI_NUM_PLAYBACK        6
 112
 113 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 114 #define ATIHDMI_NUM_CAPTURE     0
 115 #define ATIHDMI_NUM_PLAYBACK    8
 116
 117 /* TERA has 4 playback and 3 capture */
 118 #define TERA_NUM_CAPTURE        3
 119 #define TERA_NUM_PLAYBACK       4
 120
 121
 122 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 123 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 124 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 125 static char *model[SNDRV_CARDS];
 126 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_only[SNDRV_CARDS];
 130 static int jackpoll_ms[SNDRV_CARDS];
 131 static bool single_cmd;
 132 static int enable_msi = -1;
 133 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 134 static char *patch[SNDRV_CARDS];
 135 #endif
 136 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 137 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 138                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 139 #endif
 140
 141 module_param_array(index, int, NULL, 0444);
 142 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 143 module_param_array(id, charp, NULL, 0444);
 144 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 145 module_param_array(enable, bool, NULL, 0444);
 146 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 147 module_param_array(model, charp, NULL, 0444);
 148 MODULE_PARM_DESC(model, "Use the given board model.");
 149 module_param_array(position_fix, int, NULL, 0444);
 150 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 151                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 152 module_param_array(bdl_pos_adj, int, NULL, 0644);
 153 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 154 module_param_array(probe_mask, int, NULL, 0444);
 155 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 156 module_param_array(probe_only, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 158 module_param_array(jackpoll_ms, int, NULL, 0444);
 159 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 160 module_param(single_cmd, bool, 0444);
 161 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 162                  "(for debugging only).");
 163 module_param(enable_msi, bint, 0444);
 164 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 165 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 166 module_param_array(patch, charp, NULL, 0444);
 167 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 168 #endif
 169 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 170 module_param_array(beep_mode, bool, NULL, 0444);
 171 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 172                             "(0=off, 1=on) (default=1).");
 173 #endif
 174
 175 #ifdef CONFIG_PM
 176 static int param_set_xint(const char *val, const struct kernel_param *kp);
 177 static const struct kernel_param_ops param_ops_xint = {
 178         .set = param_set_xint,
 179         .get = param_get_int,
 180 };
 181 #define param_check_xint param_check_int
 182
 183 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 184 module_param(power_save, xint, 0644);
 185 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 186                  "(in second, 0 = disable).");
 187
 188 static bool pm_blacklist = true;
 189 module_param(pm_blacklist, bool, 0644);
 190 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 191
 192 /* reset the HD-audio controller in power save mode.
 193  * this may give more power-saving, but will take longer time to
 194  * wake up.
 195  */
 196 static bool power_save_controller = 1;
 197 module_param(power_save_controller, bool, 0644);
 198 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 199 #else
 200 #define power_save      0
 201 #endif /* CONFIG_PM */
 202
 203 static int align_buffer_size = -1;
 204 module_param(align_buffer_size, bint, 0644);
 205 MODULE_PARM_DESC(align_buffer_size,
 206                 "Force buffer and period sizes to be multiple of 128 bytes.");
 207
 208 #ifdef CONFIG_X86
 209 static int hda_snoop = -1;
 210 module_param_named(snoop, hda_snoop, bint, 0444);
 211 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 212 #else
 213 #define hda_snoop               true
 214 #endif
 215
 216
 217 MODULE_LICENSE("GPL");
 218 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 219                          "{Intel, ICH6M},"
 220                          "{Intel, ICH7},"
 221                          "{Intel, ESB2},"
 222                          "{Intel, ICH8},"
 223                          "{Intel, ICH9},"
 224                          "{Intel, ICH10},"
 225                          "{Intel, PCH},"
 226                          "{Intel, CPT},"
 227                          "{Intel, PPT},"
 228                          "{Intel, LPT},"
 229                          "{Intel, LPT_LP},"
 230                          "{Intel, WPT_LP},"
 231                          "{Intel, SPT},"
 232                          "{Intel, SPT_LP},"
 233                          "{Intel, HPT},"
 234                          "{Intel, PBG},"
 235                          "{Intel, SCH},"
 236                          "{ATI, SB450},"
 237                          "{ATI, SB600},"
 238                          "{ATI, RS600},"
 239                          "{ATI, RS690},"
 240                          "{ATI, RS780},"
 241                          "{ATI, R600},"
 242                          "{ATI, RV630},"
 243                          "{ATI, RV610},"
 244                          "{ATI, RV670},"
 245                          "{ATI, RV635},"
 246                          "{ATI, RV620},"
 247                          "{ATI, RV770},"
 248                          "{VIA, VT8251},"
 249                          "{VIA, VT8237A},"
 250                          "{SiS, SIS966},"
 251                          "{ULI, M5461}}");
 252 MODULE_DESCRIPTION("Intel HDA driver");
 253
 254 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 255 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 256 #define SUPPORT_VGA_SWITCHEROO
 257 #endif
 258 #endif
 259
 260
 261 /*
 262  */
 263
 264 /* driver types */
 265 enum {
 266         AZX_DRIVER_ICH,
 267         AZX_DRIVER_PCH,
 268         AZX_DRIVER_SCH,
 269         AZX_DRIVER_HDMI,
 270         AZX_DRIVER_ATI,
 271         AZX_DRIVER_ATIHDMI,
 272         AZX_DRIVER_ATIHDMI_NS,
 273         AZX_DRIVER_VIA,
 274         AZX_DRIVER_SIS,
 275         AZX_DRIVER_ULI,
 276         AZX_DRIVER_NVIDIA,
 277         AZX_DRIVER_TERA,
 278         AZX_DRIVER_CTX,
 279         AZX_DRIVER_CTHDA,
 280         AZX_DRIVER_CMEDIA,
 281         AZX_DRIVER_GENERIC,
 282         AZX_NUM_DRIVERS, /* keep this as last entry */
 283 };
 284
 285 #define azx_get_snoop_type(chip) \
 286         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 287 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 288
 289 /* quirks for old Intel chipsets */
 290 #define AZX_DCAPS_INTEL_ICH \
 291         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 292
 293 /* quirks for Intel PCH */
 294 #define AZX_DCAPS_INTEL_PCH_BASE \
 295         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 296          AZX_DCAPS_SNOOP_TYPE(SCH))
 297
 298 /* PCH up to IVB; no runtime PM */
 299 #define AZX_DCAPS_INTEL_PCH_NOPM \
 300         (AZX_DCAPS_INTEL_PCH_BASE)
 301
 302 /* PCH for HSW/BDW; with runtime PM */
 303 #define AZX_DCAPS_INTEL_PCH \
 304         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 305
 306 /* HSW HDMI */
 307 #define AZX_DCAPS_INTEL_HASWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH))
 311
 312 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 313 #define AZX_DCAPS_INTEL_BROADWELL \
 314         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 315          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 316          AZX_DCAPS_SNOOP_TYPE(SCH))
 317
 318 #define AZX_DCAPS_INTEL_BAYTRAIL \
 319         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 320
 321 #define AZX_DCAPS_INTEL_BRASWELL \
 322         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 323
 324 #define AZX_DCAPS_INTEL_SKYLAKE \
 325         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 326          AZX_DCAPS_I915_POWERWELL)
 327
 328 #define AZX_DCAPS_INTEL_BROXTON \
 329         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 330          AZX_DCAPS_I915_POWERWELL)
 331
 332 /* quirks for ATI SB / AMD Hudson */
 333 #define AZX_DCAPS_PRESET_ATI_SB \
 334         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 335          AZX_DCAPS_SNOOP_TYPE(ATI))
 336
 337 /* quirks for ATI/AMD HDMI */
 338 #define AZX_DCAPS_PRESET_ATI_HDMI \
 339         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 340          AZX_DCAPS_NO_MSI64)
 341
 342 /* quirks for ATI HDMI with snoop off */
 343 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 344         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 345
 346 /* quirks for Nvidia */
 347 #define AZX_DCAPS_PRESET_NVIDIA \
 348         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 349          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 350
 351 #define AZX_DCAPS_PRESET_CTHDA \
 352         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 353          AZX_DCAPS_NO_64BIT |\
 354          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 355
 356 /*
 357  * vga_switcheroo support
 358  */
 359 #ifdef SUPPORT_VGA_SWITCHEROO
 360 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 361 #else
 362 #define use_vga_switcheroo(chip)        0
 363 #endif
 364
 365 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 366                                         ((pci)->device == 0x0c0c) || \
 367                                         ((pci)->device == 0x0d0c) || \
 368                                         ((pci)->device == 0x160c))
 369
 370 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 371 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 372 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 373 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
 374 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 375 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 376 #define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
 377 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
 378                         IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)  || \
 379                         IS_GLK(pci)
 380
 381 static char *driver_short_names[] = {
 382         [AZX_DRIVER_ICH] = "HDA Intel",
 383         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 384         [AZX_DRIVER_SCH] = "HDA Intel MID",
 385         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 386         [AZX_DRIVER_ATI] = "HDA ATI SB",
 387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 388         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 389         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 390         [AZX_DRIVER_SIS] = "HDA SIS966",
 391         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 392         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 393         [AZX_DRIVER_TERA] = "HDA Teradici",
 394         [AZX_DRIVER_CTX] = "HDA Creative",
 395         [AZX_DRIVER_CTHDA] = "HDA Creative",
 396         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 397         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 398 };
 399
 400 #ifdef CONFIG_X86
 401 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 402 {
 403         int pages;
 404
 405         if (azx_snoop(chip))
 406                 return;
 407         if (!dmab || !dmab->area || !dmab->bytes)
 408                 return;
 409
 410 #ifdef CONFIG_SND_DMA_SGBUF
 411         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 412                 struct snd_sg_buf *sgbuf = dmab->private_data;
 413                 if (!chip->uc_buffer)
 414                         return; /* deal with only CORB/RIRB buffers */
 415                 if (on)
 416                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 417                 else
 418                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 419                 return;
 420         }
 421 #endif
 422
 423         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 424         if (on)
 425                 set_memory_wc((unsigned long)dmab->area, pages);
 426         else
 427                 set_memory_wb((unsigned long)dmab->area, pages);
 428 }
 429
 430 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 431                                  bool on)
 432 {
 433         __mark_pages_wc(chip, buf, on);
 434 }
 435 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 436                                    struct snd_pcm_substream *substream, bool on)
 437 {
 438         if (azx_dev->wc_marked != on) {
 439                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 440                 azx_dev->wc_marked = on;
 441         }
 442 }
 443 #else
 444 /* NOP for other archs */
 445 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 446                                  bool on)
 447 {
 448 }
 449 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 450                                    struct snd_pcm_substream *substream, bool on)
 451 {
 452 }
 453 #endif
 454
 455 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 456
 457 /*
 458  * initialize the PCI registers
 459  */
 460 /* update bits in a PCI register byte */
 461 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 462                             unsigned char mask, unsigned char val)
 463 {
 464         unsigned char data;
 465
 466         pci_read_config_byte(pci, reg, &data);
 467         data &= ~mask;
 468         data |= (val & mask);
 469         pci_write_config_byte(pci, reg, data);
 470 }
 471
 472 static void azx_init_pci(struct azx *chip)
 473 {
 474         int snoop_type = azx_get_snoop_type(chip);
 475
 476         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 477          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 478          * Ensuring these bits are 0 clears playback static on some HD Audio
 479          * codecs.
 480          * The PCI register TCSEL is defined in the Intel manuals.
 481          */
 482         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 483                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 484                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 485         }
 486
 487         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 488          * we need to enable snoop.
 489          */
 490         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 491                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 492                         azx_snoop(chip));
 493                 update_pci_byte(chip->pci,
 494                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 495                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 496         }
 497
 498         /* For NVIDIA HDA, enable snoop */
 499         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 500                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 501                         azx_snoop(chip));
 502                 update_pci_byte(chip->pci,
 503                                 NVIDIA_HDA_TRANSREG_ADDR,
 504                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 505                 update_pci_byte(chip->pci,
 506                                 NVIDIA_HDA_ISTRM_COH,
 507                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 508                 update_pci_byte(chip->pci,
 509                                 NVIDIA_HDA_OSTRM_COH,
 510                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 511         }
 512
 513         /* Enable SCH/PCH snoop if needed */
 514         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 515                 unsigned short snoop;
 516                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 517                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 518                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 519                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 520                         if (!azx_snoop(chip))
 521                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 522                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 523                         pci_read_config_word(chip->pci,
 524                                 INTEL_SCH_HDA_DEVC, &snoop);
 525                 }
 526                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 527                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 528                         "Disabled" : "Enabled");
 529         }
 530 }
 531
 532 /*
 533  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 534  * and makes an audio stream sensitive to system latencies when
 535  * 24/32 bits are playing.
 536  * Adjusting threshold of DMA fifo to force the DMA request
 537  * sooner to improve latency tolerance at the expense of power.
 538  */
 539 static void bxt_reduce_dma_latency(struct azx *chip)
 540 {
 541         u32 val;
 542
 543         val = azx_readl(chip, SKL_EM4L);
 544         val &= (0x3 << 20);
 545         azx_writel(chip, SKL_EM4L, val);
 546 }
 547
 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         struct pci_dev *pci = chip->pci;
 552         u32 val;
 553
 554         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 555                 snd_hdac_set_codec_wakeup(bus, true);
 556         if (IS_SKL_PLUS(pci)) {
 557                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 558                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 559                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 560         }
 561         azx_init_chip(chip, full_reset);
 562         if (IS_SKL_PLUS(pci)) {
 563                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 564                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 565                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 566         }
 567         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 568                 snd_hdac_set_codec_wakeup(bus, false);
 569
 570         /* reduce dma latency to avoid noise */
 571         if (IS_BXT(pci))
 572                 bxt_reduce_dma_latency(chip);
 573 }
 574
 575 /* calculate runtime delay from LPIB */
 576 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 577                                    unsigned int pos)
 578 {
 579         struct snd_pcm_substream *substream = azx_dev->core.substream;
 580         int stream = substream->stream;
 581         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 582         int delay;
 583
 584         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 585                 delay = pos - lpib_pos;
 586         else
 587                 delay = lpib_pos - pos;
 588         if (delay < 0) {
 589                 if (delay >= azx_dev->core.delay_negative_threshold)
 590                         delay = 0;
 591                 else
 592                         delay += azx_dev->core.bufsize;
 593         }
 594
 595         if (delay >= azx_dev->core.period_bytes) {
 596                 dev_info(chip->card->dev,
 597                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 598                          delay, azx_dev->core.period_bytes);
 599                 delay = 0;
 600                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 601                 chip->get_delay[stream] = NULL;
 602         }
 603
 604         return bytes_to_frames(substream->runtime, delay);
 605 }
 606
 607 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 608
 609 /* called from IRQ */
 610 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 611 {
 612         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 613         int ok;
 614
 615         ok = azx_position_ok(chip, azx_dev);
 616         if (ok == 1) {
 617                 azx_dev->irq_pending = 0;
 618                 return ok;
 619         } else if (ok == 0) {
 620                 /* bogus IRQ, process it later */
 621                 azx_dev->irq_pending = 1;
 622                 schedule_work(&hda->irq_pending_work);
 623         }
 624         return 0;
 625 }
 626
 627 /* Enable/disable i915 display power for the link */
 628 static int azx_intel_link_power(struct azx *chip, bool enable)
 629 {
 630         struct hdac_bus *bus = azx_bus(chip);
 631
 632         return snd_hdac_display_power(bus, enable);
 633 }
 634
 635 /*
 636  * Check whether the current DMA position is acceptable for updating
 637  * periods.  Returns non-zero if it's OK.
 638  *
 639  * Many HD-audio controllers appear pretty inaccurate about
 640  * the update-IRQ timing.  The IRQ is issued before actually the
 641  * data is processed.  So, we need to process it afterwords in a
 642  * workqueue.
 643  */
 644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 645 {
 646         struct snd_pcm_substream *substream = azx_dev->core.substream;
 647         int stream = substream->stream;
 648         u32 wallclk;
 649         unsigned int pos;
 650
 651         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 652         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 653                 return -1;      /* bogus (too early) interrupt */
 654
 655         if (chip->get_position[stream])
 656                 pos = chip->get_position[stream](chip, azx_dev);
 657         else { /* use the position buffer as default */
 658                 pos = azx_get_pos_posbuf(chip, azx_dev);
 659                 if (!pos || pos == (u32)-1) {
 660                         dev_info(chip->card->dev,
 661                                  "Invalid position buffer, using LPIB read method instead.\n");
 662                         chip->get_position[stream] = azx_get_pos_lpib;
 663                         if (chip->get_position[0] == azx_get_pos_lpib &&
 664                             chip->get_position[1] == azx_get_pos_lpib)
 665                                 azx_bus(chip)->use_posbuf = false;
 666                         pos = azx_get_pos_lpib(chip, azx_dev);
 667                         chip->get_delay[stream] = NULL;
 668                 } else {
 669                         chip->get_position[stream] = azx_get_pos_posbuf;
 670                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 671                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 672                 }
 673         }
 674
 675         if (pos >= azx_dev->core.bufsize)
 676                 pos = 0;
 677
 678         if (WARN_ONCE(!azx_dev->core.period_bytes,
 679                       "hda-intel: zero azx_dev->period_bytes"))
 680                 return -1; /* this shouldn't happen! */
 681         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 682             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 683                 /* NG - it's below the first next period boundary */
 684                 return chip->bdl_pos_adj ? 0 : -1;
 685         azx_dev->core.start_wallclk += wallclk;
 686         return 1; /* OK, it's fine */
 687 }
 688
 689 /*
 690  * The work for pending PCM period updates.
 691  */
 692 static void azx_irq_pending_work(struct work_struct *work)
 693 {
 694         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 695         struct azx *chip = &hda->chip;
 696         struct hdac_bus *bus = azx_bus(chip);
 697         struct hdac_stream *s;
 698         int pending, ok;
 699
 700         if (!hda->irq_pending_warned) {
 701                 dev_info(chip->card->dev,
 702                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 703                          chip->card->number);
 704                 hda->irq_pending_warned = 1;
 705         }
 706
 707         for (;;) {
 708                 pending = 0;
 709                 spin_lock_irq(&bus->reg_lock);
 710                 list_for_each_entry(s, &bus->stream_list, list) {
 711                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 712                         if (!azx_dev->irq_pending ||
 713                             !s->substream ||
 714                             !s->running)
 715                                 continue;
 716                         ok = azx_position_ok(chip, azx_dev);
 717                         if (ok > 0) {
 718                                 azx_dev->irq_pending = 0;
 719                                 spin_unlock(&bus->reg_lock);
 720                                 snd_pcm_period_elapsed(s->substream);
 721                                 spin_lock(&bus->reg_lock);
 722                         } else if (ok < 0) {
 723                                 pending = 0;    /* too early */
 724                         } else
 725                                 pending++;
 726                 }
 727                 spin_unlock_irq(&bus->reg_lock);
 728                 if (!pending)
 729                         return;
 730                 msleep(1);
 731         }
 732 }
 733
 734 /* clear irq_pending flags and assure no on-going workq */
 735 static void azx_clear_irq_pending(struct azx *chip)
 736 {
 737         struct hdac_bus *bus = azx_bus(chip);
 738         struct hdac_stream *s;
 739
 740         spin_lock_irq(&bus->reg_lock);
 741         list_for_each_entry(s, &bus->stream_list, list) {
 742                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 743                 azx_dev->irq_pending = 0;
 744         }
 745         spin_unlock_irq(&bus->reg_lock);
 746 }
 747
 748 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 749 {
 750         struct hdac_bus *bus = azx_bus(chip);
 751
 752         if (request_irq(chip->pci->irq, azx_interrupt,
 753                         chip->msi ? 0 : IRQF_SHARED,
 754                         chip->card->irq_descr, chip)) {
 755                 dev_err(chip->card->dev,
 756                         "unable to grab IRQ %d, disabling device\n",
 757                         chip->pci->irq);
 758                 if (do_disconnect)
 759                         snd_card_disconnect(chip->card);
 760                 return -1;
 761         }
 762         bus->irq = chip->pci->irq;
 763         pci_intx(chip->pci, !chip->msi);
 764         return 0;
 765 }
 766
 767 /* get the current DMA position with correction on VIA chips */
 768 static unsigned int azx_via_get_position(struct azx *chip,
 769                                          struct azx_dev *azx_dev)
 770 {
 771         unsigned int link_pos, mini_pos, bound_pos;
 772         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 773         unsigned int fifo_size;
 774
 775         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 776         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 777                 /* Playback, no problem using link position */
 778                 return link_pos;
 779         }
 780
 781         /* Capture */
 782         /* For new chipset,
 783          * use mod to get the DMA position just like old chipset
 784          */
 785         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 786         mod_dma_pos %= azx_dev->core.period_bytes;
 787
 788         /* azx_dev->fifo_size can't get FIFO size of in stream.
 789          * Get from base address + offset.
 790          */
 791         fifo_size = readw(azx_bus(chip)->remap_addr +
 792                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 793
 794         if (azx_dev->insufficient) {
 795                 /* Link position never gather than FIFO size */
 796                 if (link_pos <= fifo_size)
 797                         return 0;
 798
 799                 azx_dev->insufficient = 0;
 800         }
 801
 802         if (link_pos <= fifo_size)
 803                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 804         else
 805                 mini_pos = link_pos - fifo_size;
 806
 807         /* Find nearest previous boudary */
 808         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 809         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 810         if (mod_link_pos >= fifo_size)
 811                 bound_pos = link_pos - mod_link_pos;
 812         else if (mod_dma_pos >= mod_mini_pos)
 813                 bound_pos = mini_pos - mod_mini_pos;
 814         else {
 815                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 816                 if (bound_pos >= azx_dev->core.bufsize)
 817                         bound_pos = 0;
 818         }
 819
 820         /* Calculate real DMA position we want */
 821         return bound_pos + mod_dma_pos;
 822 }
 823
 824 #ifdef CONFIG_PM
 825 static DEFINE_MUTEX(card_list_lock);
 826 static LIST_HEAD(card_list);
 827
 828 static void azx_add_card_list(struct azx *chip)
 829 {
 830         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 831         mutex_lock(&card_list_lock);
 832         list_add(&hda->list, &card_list);
 833         mutex_unlock(&card_list_lock);
 834 }
 835
 836 static void azx_del_card_list(struct azx *chip)
 837 {
 838         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 839         mutex_lock(&card_list_lock);
 840         list_del_init(&hda->list);
 841         mutex_unlock(&card_list_lock);
 842 }
 843
 844 /* trigger power-save check at writing parameter */
 845 static int param_set_xint(const char *val, const struct kernel_param *kp)
 846 {
 847         struct hda_intel *hda;
 848         struct azx *chip;
 849         int prev = power_save;
 850         int ret = param_set_int(val, kp);
 851
 852         if (ret || prev == power_save)
 853                 return ret;
 854
 855         mutex_lock(&card_list_lock);
 856         list_for_each_entry(hda, &card_list, list) {
 857                 chip = &hda->chip;
 858                 if (!hda->probe_continued || chip->disabled)
 859                         continue;
 860                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 861         }
 862         mutex_unlock(&card_list_lock);
 863         return 0;
 864 }
 865 #else
 866 #define azx_add_card_list(chip) /* NOP */
 867 #define azx_del_card_list(chip) /* NOP */
 868 #endif /* CONFIG_PM */
 869
 870 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 871 /*
 872  * power management
 873  */
 874 static int azx_suspend(struct device *dev)
 875 {
 876         struct snd_card *card = dev_get_drvdata(dev);
 877         struct azx *chip;
 878         struct hda_intel *hda;
 879         struct hdac_bus *bus;
 880
 881         if (!card)
 882                 return 0;
 883
 884         chip = card->private_data;
 885         hda = container_of(chip, struct hda_intel, chip);
 886         if (chip->disabled || hda->init_failed || !chip->running)
 887                 return 0;
 888
 889         bus = azx_bus(chip);
 890         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 891         azx_clear_irq_pending(chip);
 892         azx_stop_chip(chip);
 893         azx_enter_link_reset(chip);
 894         if (bus->irq >= 0) {
 895                 free_irq(bus->irq, chip);
 896                 bus->irq = -1;
 897         }
 898
 899         if (chip->msi)
 900                 pci_disable_msi(chip->pci);
 901         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 902                 && hda->need_i915_power)
 903                 snd_hdac_display_power(bus, false);
 904
 905         trace_azx_suspend(chip);
 906         return 0;
 907 }
 908
 909 static int azx_resume(struct device *dev)
 910 {
 911         struct pci_dev *pci = to_pci_dev(dev);
 912         struct snd_card *card = dev_get_drvdata(dev);
 913         struct azx *chip;
 914         struct hda_intel *hda;
 915         struct hdac_bus *bus;
 916
 917         if (!card)
 918                 return 0;
 919
 920         chip = card->private_data;
 921         hda = container_of(chip, struct hda_intel, chip);
 922         bus = azx_bus(chip);
 923         if (chip->disabled || hda->init_failed || !chip->running)
 924                 return 0;
 925
 926         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 927                 snd_hdac_display_power(bus, true);
 928                 if (hda->need_i915_power)
 929                         snd_hdac_i915_set_bclk(bus);
 930         }
 931
 932         if (chip->msi)
 933                 if (pci_enable_msi(pci) < 0)
 934                         chip->msi = 0;
 935         if (azx_acquire_irq(chip, 1) < 0)
 936                 return -EIO;
 937         azx_init_pci(chip);
 938
 939         hda_intel_init_chip(chip, true);
 940
 941         /* power down again for link-controlled chips */
 942         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 943             !hda->need_i915_power)
 944                 snd_hdac_display_power(bus, false);
 945
 946         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 947
 948         trace_azx_resume(chip);
 949         return 0;
 950 }
 951 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 952
 953 #ifdef CONFIG_PM_SLEEP
 954 /* put codec down to D3 at hibernation for Intel SKL+;
 955  * otherwise BIOS may still access the codec and screw up the driver
 956  */
 957 static int azx_freeze_noirq(struct device *dev)
 958 {
 959         struct pci_dev *pci = to_pci_dev(dev);
 960
 961         if (IS_SKL_PLUS(pci))
 962                 pci_set_power_state(pci, PCI_D3hot);
 963
 964         return 0;
 965 }
 966
 967 static int azx_thaw_noirq(struct device *dev)
 968 {
 969         struct pci_dev *pci = to_pci_dev(dev);
 970
 971         if (IS_SKL_PLUS(pci))
 972                 pci_set_power_state(pci, PCI_D0);
 973
 974         return 0;
 975 }
 976 #endif /* CONFIG_PM_SLEEP */
 977
 978 #ifdef CONFIG_PM
 979 static int azx_runtime_suspend(struct device *dev)
 980 {
 981         struct snd_card *card = dev_get_drvdata(dev);
 982         struct azx *chip;
 983         struct hda_intel *hda;
 984
 985         if (!card)
 986                 return 0;
 987
 988         chip = card->private_data;
 989         hda = container_of(chip, struct hda_intel, chip);
 990         if (chip->disabled || hda->init_failed)
 991                 return 0;
 992
 993         if (!azx_has_pm_runtime(chip))
 994                 return 0;
 995
 996         /* enable controller wake up event */
 997         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 998                   STATESTS_INT_MASK);
 999
1000         azx_stop_chip(chip);
1001         azx_enter_link_reset(chip);
1002         azx_clear_irq_pending(chip);
1003         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1004                 && hda->need_i915_power)
1005                 snd_hdac_display_power(azx_bus(chip), false);
1006
1007         trace_azx_runtime_suspend(chip);
1008         return 0;
1009 }
1010
1011 static int azx_runtime_resume(struct device *dev)
1012 {
1013         struct snd_card *card = dev_get_drvdata(dev);
1014         struct azx *chip;
1015         struct hda_intel *hda;
1016         struct hdac_bus *bus;
1017         struct hda_codec *codec;
1018         int status;
1019
1020         if (!card)
1021                 return 0;
1022
1023         chip = card->private_data;
1024         hda = container_of(chip, struct hda_intel, chip);
1025         bus = azx_bus(chip);
1026         if (chip->disabled || hda->init_failed)
1027                 return 0;
1028
1029         if (!azx_has_pm_runtime(chip))
1030                 return 0;
1031
1032         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1033                 snd_hdac_display_power(bus, true);
1034                 if (hda->need_i915_power)
1035                         snd_hdac_i915_set_bclk(bus);
1036         }
1037
1038         /* Read STATESTS before controller reset */
1039         status = azx_readw(chip, STATESTS);
1040
1041         azx_init_pci(chip);
1042         hda_intel_init_chip(chip, true);
1043
1044         if (status) {
1045                 list_for_each_codec(codec, &chip->bus)
1046                         if (status & (1 << codec->addr))
1047                                 schedule_delayed_work(&codec->jackpoll_work,
1048                                                       codec->jackpoll_interval);
1049         }
1050
1051         /* disable controller Wake Up event*/
1052         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1053                         ~STATESTS_INT_MASK);
1054
1055         /* power down again for link-controlled chips */
1056         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1057             !hda->need_i915_power)
1058                 snd_hdac_display_power(bus, false);
1059
1060         trace_azx_runtime_resume(chip);
1061         return 0;
1062 }
1063
1064 static int azx_runtime_idle(struct device *dev)
1065 {
1066         struct snd_card *card = dev_get_drvdata(dev);
1067         struct azx *chip;
1068         struct hda_intel *hda;
1069
1070         if (!card)
1071                 return 0;
1072
1073         chip = card->private_data;
1074         hda = container_of(chip, struct hda_intel, chip);
1075         if (chip->disabled || hda->init_failed)
1076                 return 0;
1077
1078         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1079             azx_bus(chip)->codec_powered || !chip->running)
1080                 return -EBUSY;
1081
1082         return 0;
1083 }
1084
1085 static const struct dev_pm_ops azx_pm = {
1086         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1087 #ifdef CONFIG_PM_SLEEP
1088         .freeze_noirq = azx_freeze_noirq,
1089         .thaw_noirq = azx_thaw_noirq,
1090 #endif
1091         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1092 };
1093
1094 #define AZX_PM_OPS      &azx_pm
1095 #else
1096 #define AZX_PM_OPS      NULL
1097 #endif /* CONFIG_PM */
1098
1099
1100 static int azx_probe_continue(struct azx *chip);
1101
1102 #ifdef SUPPORT_VGA_SWITCHEROO
1103 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1104
1105 static void azx_vs_set_state(struct pci_dev *pci,
1106                              enum vga_switcheroo_state state)
1107 {
1108         struct snd_card *card = pci_get_drvdata(pci);
1109         struct azx *chip = card->private_data;
1110         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1111         bool disabled;
1112
1113         wait_for_completion(&hda->probe_wait);
1114         if (hda->init_failed)
1115                 return;
1116
1117         disabled = (state == VGA_SWITCHEROO_OFF);
1118         if (chip->disabled == disabled)
1119                 return;
1120
1121         if (!hda->probe_continued) {
1122                 chip->disabled = disabled;
1123                 if (!disabled) {
1124                         dev_info(chip->card->dev,
1125                                  "Start delayed initialization\n");
1126                         if (azx_probe_continue(chip) < 0) {
1127                                 dev_err(chip->card->dev, "initialization error\n");
1128                                 hda->init_failed = true;
1129                         }
1130                 }
1131         } else {
1132                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1133                          disabled ? "Disabling" : "Enabling");
1134                 if (disabled) {
1135                         pm_runtime_put_sync_suspend(card->dev);
1136                         azx_suspend(card->dev);
1137                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1138                          * however we have no ACPI handle, so pci/acpi can't put us there,
1139                          * put ourselves there */
1140                         pci->current_state = PCI_D3cold;
1141                         chip->disabled = true;
1142                         if (snd_hda_lock_devices(&chip->bus))
1143                                 dev_warn(chip->card->dev,
1144                                          "Cannot lock devices!\n");
1145                 } else {
1146                         snd_hda_unlock_devices(&chip->bus);
1147                         pm_runtime_get_noresume(card->dev);
1148                         chip->disabled = false;
1149                         azx_resume(card->dev);
1150                 }
1151         }
1152 }
1153
1154 static bool azx_vs_can_switch(struct pci_dev *pci)
1155 {
1156         struct snd_card *card = pci_get_drvdata(pci);
1157         struct azx *chip = card->private_data;
1158         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1159
1160         wait_for_completion(&hda->probe_wait);
1161         if (hda->init_failed)
1162                 return false;
1163         if (chip->disabled || !hda->probe_continued)
1164                 return true;
1165         if (snd_hda_lock_devices(&chip->bus))
1166                 return false;
1167         snd_hda_unlock_devices(&chip->bus);
1168         return true;
1169 }
1170
1171 static void init_vga_switcheroo(struct azx *chip)
1172 {
1173         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1174         struct pci_dev *p = get_bound_vga(chip->pci);
1175         if (p) {
1176                 dev_info(chip->card->dev,
1177                          "Handle vga_switcheroo audio client\n");
1178                 hda->use_vga_switcheroo = 1;
1179                 pci_dev_put(p);
1180         }
1181 }
1182
1183 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1184         .set_gpu_state = azx_vs_set_state,
1185         .can_switch = azx_vs_can_switch,
1186 };
1187
1188 static int register_vga_switcheroo(struct azx *chip)
1189 {
1190         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191         int err;
1192
1193         if (!hda->use_vga_switcheroo)
1194                 return 0;
1195         /* FIXME: currently only handling DIS controller
1196          * is there any machine with two switchable HDMI audio controllers?
1197          */
1198         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1199                                                    VGA_SWITCHEROO_DIS);
1200         if (err < 0)
1201                 return err;
1202         hda->vga_switcheroo_registered = 1;
1203
1204         /* register as an optimus hdmi audio power domain */
1205         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1206                                                          &hda->hdmi_pm_domain);
1207         return 0;
1208 }
1209 #else
1210 #define init_vga_switcheroo(chip)               /* NOP */
1211 #define register_vga_switcheroo(chip)           0
1212 #define check_hdmi_disabled(pci)        false
1213 #endif /* SUPPORT_VGA_SWITCHER */
1214
1215 /*
1216  * destructor
1217  */
1218 static int azx_free(struct azx *chip)
1219 {
1220         struct pci_dev *pci = chip->pci;
1221         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222         struct hdac_bus *bus = azx_bus(chip);
1223
1224         if (azx_has_pm_runtime(chip) && chip->running)
1225                 pm_runtime_get_noresume(&pci->dev);
1226
1227         azx_del_card_list(chip);
1228
1229         hda->init_failed = 1; /* to be sure */
1230         complete_all(&hda->probe_wait);
1231
1232         if (use_vga_switcheroo(hda)) {
1233                 if (chip->disabled && hda->probe_continued)
1234                         snd_hda_unlock_devices(&chip->bus);
1235                 if (hda->vga_switcheroo_registered) {
1236                         vga_switcheroo_unregister_client(chip->pci);
1237                         vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1238                 }
1239         }
1240
1241         if (bus->chip_init) {
1242                 azx_clear_irq_pending(chip);
1243                 azx_stop_all_streams(chip);
1244                 azx_stop_chip(chip);
1245         }
1246
1247         if (bus->irq >= 0)
1248                 free_irq(bus->irq, (void*)chip);
1249         if (chip->msi)
1250                 pci_disable_msi(chip->pci);
1251         iounmap(bus->remap_addr);
1252
1253         azx_free_stream_pages(chip);
1254         azx_free_streams(chip);
1255         snd_hdac_bus_exit(bus);
1256
1257         if (chip->region_requested)
1258                 pci_release_regions(chip->pci);
1259
1260         pci_disable_device(chip->pci);
1261 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1262         release_firmware(chip->fw);
1263 #endif
1264
1265         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1266                 if (hda->need_i915_power)
1267                         snd_hdac_display_power(bus, false);
1268                 snd_hdac_i915_exit(bus);
1269         }
1270         kfree(hda);
1271
1272         return 0;
1273 }
1274
1275 static int azx_dev_disconnect(struct snd_device *device)
1276 {
1277         struct azx *chip = device->device_data;
1278         struct hdac_bus *bus = azx_bus(chip);
1279
1280         chip->bus.shutdown = 1;
1281         cancel_work_sync(&bus->unsol_work);
1282
1283         return 0;
1284 }
1285
1286 static int azx_dev_free(struct snd_device *device)
1287 {
1288         return azx_free(device->device_data);
1289 }
1290
1291 #ifdef SUPPORT_VGA_SWITCHEROO
1292 /*
1293  * Check of disabled HDMI controller by vga_switcheroo
1294  */
1295 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1296 {
1297         struct pci_dev *p;
1298
1299         /* check only discrete GPU */
1300         switch (pci->vendor) {
1301         case PCI_VENDOR_ID_ATI:
1302         case PCI_VENDOR_ID_AMD:
1303         case PCI_VENDOR_ID_NVIDIA:
1304                 if (pci->devfn == 1) {
1305                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1306                                                         pci->bus->number, 0);
1307                         if (p) {
1308                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1309                                         return p;
1310                                 pci_dev_put(p);
1311                         }
1312                 }
1313                 break;
1314         }
1315         return NULL;
1316 }
1317
1318 static bool check_hdmi_disabled(struct pci_dev *pci)
1319 {
1320         bool vga_inactive = false;
1321         struct pci_dev *p = get_bound_vga(pci);
1322
1323         if (p) {
1324                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1325                         vga_inactive = true;
1326                 pci_dev_put(p);
1327         }
1328         return vga_inactive;
1329 }
1330 #endif /* SUPPORT_VGA_SWITCHEROO */
1331
1332 /*
1333  * white/black-listing for position_fix
1334  */
1335 static struct snd_pci_quirk position_fix_list[] = {
1336         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1337         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1338         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1339         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1340         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1341         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1342         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1343         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1344         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1345         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1346         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1347         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1348         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1349         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1350         {}
1351 };
1352
1353 static int check_position_fix(struct azx *chip, int fix)
1354 {
1355         const struct snd_pci_quirk *q;
1356
1357         switch (fix) {
1358         case POS_FIX_AUTO:
1359         case POS_FIX_LPIB:
1360         case POS_FIX_POSBUF:
1361         case POS_FIX_VIACOMBO:
1362         case POS_FIX_COMBO:
1363                 return fix;
1364         }
1365
1366         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1367         if (q) {
1368                 dev_info(chip->card->dev,
1369                          "position_fix set to %d for device %04x:%04x\n",
1370                          q->value, q->subvendor, q->subdevice);
1371                 return q->value;
1372         }
1373
1374         /* Check VIA/ATI HD Audio Controller exist */
1375         if (chip->driver_type == AZX_DRIVER_VIA) {
1376                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1377                 return POS_FIX_VIACOMBO;
1378         }
1379         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1380                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1381                 return POS_FIX_LPIB;
1382         }
1383         return POS_FIX_AUTO;
1384 }
1385
1386 static void assign_position_fix(struct azx *chip, int fix)
1387 {
1388         static azx_get_pos_callback_t callbacks[] = {
1389                 [POS_FIX_AUTO] = NULL,
1390                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1391                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1392                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1393                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1394         };
1395
1396         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1397
1398         /* combo mode uses LPIB only for playback */
1399         if (fix == POS_FIX_COMBO)
1400                 chip->get_position[1] = NULL;
1401
1402         if (fix == POS_FIX_POSBUF &&
1403             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1404                 chip->get_delay[0] = chip->get_delay[1] =
1405                         azx_get_delay_from_lpib;
1406         }
1407
1408 }
1409
1410 /*
1411  * black-lists for probe_mask
1412  */
1413 static struct snd_pci_quirk probe_mask_list[] = {
1414         /* Thinkpad often breaks the controller communication when accessing
1415          * to the non-working (or non-existing) modem codec slot.
1416          */
1417         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1418         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1419         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1420         /* broken BIOS */
1421         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1422         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1423         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1424         /* forced codec slots */
1425         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1426         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1427         /* WinFast VP200 H (Teradici) user reported broken communication */
1428         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1429         {}
1430 };
1431
1432 #define AZX_FORCE_CODEC_MASK    0x100
1433
1434 static void check_probe_mask(struct azx *chip, int dev)
1435 {
1436         const struct snd_pci_quirk *q;
1437
1438         chip->codec_probe_mask = probe_mask[dev];
1439         if (chip->codec_probe_mask == -1) {
1440                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1441                 if (q) {
1442                         dev_info(chip->card->dev,
1443                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1444                                  q->value, q->subvendor, q->subdevice);
1445                         chip->codec_probe_mask = q->value;
1446                 }
1447         }
1448
1449         /* check forced option */
1450         if (chip->codec_probe_mask != -1 &&
1451             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1452                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1453                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1454                          (int)azx_bus(chip)->codec_mask);
1455         }
1456 }
1457
1458 /*
1459  * white/black-list for enable_msi
1460  */
1461 static struct snd_pci_quirk msi_black_list[] = {
1462         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1463         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1464         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1465         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1466         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1467         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1468         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1469         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1470         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1471         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1472         {}
1473 };
1474
1475 static void check_msi(struct azx *chip)
1476 {
1477         const struct snd_pci_quirk *q;
1478
1479         if (enable_msi >= 0) {
1480                 chip->msi = !!enable_msi;
1481                 return;
1482         }
1483         chip->msi = 1;  /* enable MSI as default */
1484         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1485         if (q) {
1486                 dev_info(chip->card->dev,
1487                          "msi for device %04x:%04x set to %d\n",
1488                          q->subvendor, q->subdevice, q->value);
1489                 chip->msi = q->value;
1490                 return;
1491         }
1492
1493         /* NVidia chipsets seem to cause troubles with MSI */
1494         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1495                 dev_info(chip->card->dev, "Disabling MSI\n");
1496                 chip->msi = 0;
1497         }
1498 }
1499
1500 /* check the snoop mode availability */
1501 static void azx_check_snoop_available(struct azx *chip)
1502 {
1503         int snoop = hda_snoop;
1504
1505         if (snoop >= 0) {
1506                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1507                          snoop ? "snoop" : "non-snoop");
1508                 chip->snoop = snoop;
1509                 chip->uc_buffer = !snoop;
1510                 return;
1511         }
1512
1513         snoop = true;
1514         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1515             chip->driver_type == AZX_DRIVER_VIA) {
1516                 /* force to non-snoop mode for a new VIA controller
1517                  * when BIOS is set
1518                  */
1519                 u8 val;
1520                 pci_read_config_byte(chip->pci, 0x42, &val);
1521                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1522                                       chip->pci->revision == 0x20))
1523                         snoop = false;
1524         }
1525
1526         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1527                 snoop = false;
1528
1529         chip->snoop = snoop;
1530         if (!snoop) {
1531                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1532                 /* C-Media requires non-cached pages only for CORB/RIRB */
1533                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1534                         chip->uc_buffer = true;
1535         }
1536 }
1537
1538 static void azx_probe_work(struct work_struct *work)
1539 {
1540         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1541         azx_probe_continue(&hda->chip);
1542 }
1543
1544 static int default_bdl_pos_adj(struct azx *chip)
1545 {
1546         /* some exceptions: Atoms seem problematic with value 1 */
1547         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1548                 switch (chip->pci->device) {
1549                 case 0x0f04: /* Baytrail */
1550                 case 0x2284: /* Braswell */
1551                         return 32;
1552                 }
1553         }
1554
1555         switch (chip->driver_type) {
1556         case AZX_DRIVER_ICH:
1557         case AZX_DRIVER_PCH:
1558                 return 1;
1559         default:
1560                 return 32;
1561         }
1562 }
1563
1564 /*
1565  * constructor
1566  */
1567 static const struct hdac_io_ops pci_hda_io_ops;
1568 static const struct hda_controller_ops pci_hda_ops;
1569
1570 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1571                       int dev, unsigned int driver_caps,
1572                       struct azx **rchip)
1573 {
1574         static struct snd_device_ops ops = {
1575                 .dev_disconnect = azx_dev_disconnect,
1576                 .dev_free = azx_dev_free,
1577         };
1578         struct hda_intel *hda;
1579         struct azx *chip;
1580         int err;
1581
1582         *rchip = NULL;
1583
1584         err = pci_enable_device(pci);
1585         if (err < 0)
1586                 return err;
1587
1588         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1589         if (!hda) {
1590                 pci_disable_device(pci);
1591                 return -ENOMEM;
1592         }
1593
1594         chip = &hda->chip;
1595         mutex_init(&chip->open_mutex);
1596         chip->card = card;
1597         chip->pci = pci;
1598         chip->ops = &pci_hda_ops;
1599         chip->driver_caps = driver_caps;
1600         chip->driver_type = driver_caps & 0xff;
1601         check_msi(chip);
1602         chip->dev_index = dev;
1603         chip->jackpoll_ms = jackpoll_ms;
1604         INIT_LIST_HEAD(&chip->pcm_list);
1605         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1606         INIT_LIST_HEAD(&hda->list);
1607         init_vga_switcheroo(chip);
1608         init_completion(&hda->probe_wait);
1609
1610         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1611
1612         check_probe_mask(chip, dev);
1613
1614         chip->single_cmd = single_cmd;
1615         azx_check_snoop_available(chip);
1616
1617         if (bdl_pos_adj[dev] < 0)
1618                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1619         else
1620                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1621
1622         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1623         if (err < 0) {
1624                 kfree(hda);
1625                 pci_disable_device(pci);
1626                 return err;
1627         }
1628
1629         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1630                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1631                 chip->bus.needs_damn_long_delay = 1;
1632         }
1633
1634         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1635         if (err < 0) {
1636                 dev_err(card->dev, "Error creating device [card]!\n");
1637                 azx_free(chip);
1638                 return err;
1639         }
1640
1641         /* continue probing in work context as may trigger request module */
1642         INIT_WORK(&hda->probe_work, azx_probe_work);
1643
1644         *rchip = chip;
1645
1646         return 0;
1647 }
1648
1649 static int azx_first_init(struct azx *chip)
1650 {
1651         int dev = chip->dev_index;
1652         struct pci_dev *pci = chip->pci;
1653         struct snd_card *card = chip->card;
1654         struct hdac_bus *bus = azx_bus(chip);
1655         int err;
1656         unsigned short gcap;
1657         unsigned int dma_bits = 64;
1658
1659 #if BITS_PER_LONG != 64
1660         /* Fix up base address on ULI M5461 */
1661         if (chip->driver_type == AZX_DRIVER_ULI) {
1662                 u16 tmp3;
1663                 pci_read_config_word(pci, 0x40, &tmp3);
1664                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1665                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1666         }
1667 #endif
1668
1669         err = pci_request_regions(pci, "ICH HD audio");
1670         if (err < 0)
1671                 return err;
1672         chip->region_requested = 1;
1673
1674         bus->addr = pci_resource_start(pci, 0);
1675         bus->remap_addr = pci_ioremap_bar(pci, 0);
1676         if (bus->remap_addr == NULL) {
1677                 dev_err(card->dev, "ioremap error\n");
1678                 return -ENXIO;
1679         }
1680
1681         if (IS_SKL_PLUS(pci))
1682                 snd_hdac_bus_parse_capabilities(bus);
1683
1684         /*
1685          * Some Intel CPUs has always running timer (ART) feature and
1686          * controller may have Global time sync reporting capability, so
1687          * check both of these before declaring synchronized time reporting
1688          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1689          */
1690         chip->gts_present = false;
1691
1692 #ifdef CONFIG_X86
1693         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1694                 chip->gts_present = true;
1695 #endif
1696
1697         if (chip->msi) {
1698                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1699                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1700                         pci->no_64bit_msi = true;
1701                 }
1702                 if (pci_enable_msi(pci) < 0)
1703                         chip->msi = 0;
1704         }
1705
1706         pci_set_master(pci);
1707         synchronize_irq(bus->irq);
1708
1709         gcap = azx_readw(chip, GCAP);
1710         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1711
1712         /* AMD devices support 40 or 48bit DMA, take the safe one */
1713         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1714                 dma_bits = 40;
1715
1716         /* disable SB600 64bit support for safety */
1717         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1718                 struct pci_dev *p_smbus;
1719                 dma_bits = 40;
1720                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1721                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1722                                          NULL);
1723                 if (p_smbus) {
1724                         if (p_smbus->revision < 0x30)
1725                                 gcap &= ~AZX_GCAP_64OK;
1726                         pci_dev_put(p_smbus);
1727                 }
1728         }
1729
1730         /* NVidia hardware normally only supports up to 40 bits of DMA */
1731         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1732                 dma_bits = 40;
1733
1734         /* disable 64bit DMA address on some devices */
1735         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1736                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1737                 gcap &= ~AZX_GCAP_64OK;
1738         }
1739
1740         /* disable buffer size rounding to 128-byte multiples if supported */
1741         if (align_buffer_size >= 0)
1742                 chip->align_buffer_size = !!align_buffer_size;
1743         else {
1744                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1745                         chip->align_buffer_size = 0;
1746                 else
1747                         chip->align_buffer_size = 1;
1748         }
1749
1750         /* allow 64bit DMA address if supported by H/W */
1751         if (!(gcap & AZX_GCAP_64OK))
1752                 dma_bits = 32;
1753         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1754                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1755         } else {
1756                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1757                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1758         }
1759
1760         /* read number of streams from GCAP register instead of using
1761          * hardcoded value
1762          */
1763         chip->capture_streams = (gcap >> 8) & 0x0f;
1764         chip->playback_streams = (gcap >> 12) & 0x0f;
1765         if (!chip->playback_streams && !chip->capture_streams) {
1766                 /* gcap didn't give any info, switching to old method */
1767
1768                 switch (chip->driver_type) {
1769                 case AZX_DRIVER_ULI:
1770                         chip->playback_streams = ULI_NUM_PLAYBACK;
1771                         chip->capture_streams = ULI_NUM_CAPTURE;
1772                         break;
1773                 case AZX_DRIVER_ATIHDMI:
1774                 case AZX_DRIVER_ATIHDMI_NS:
1775                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1776                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1777                         break;
1778                 case AZX_DRIVER_GENERIC:
1779                 default:
1780                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1781                         chip->capture_streams = ICH6_NUM_CAPTURE;
1782                         break;
1783                 }
1784         }
1785         chip->capture_index_offset = 0;
1786         chip->playback_index_offset = chip->capture_streams;
1787         chip->num_streams = chip->playback_streams + chip->capture_streams;
1788
1789         /* initialize streams */
1790         err = azx_init_streams(chip);
1791         if (err < 0)
1792                 return err;
1793
1794         err = azx_alloc_stream_pages(chip);
1795         if (err < 0)
1796                 return err;
1797
1798         /* initialize chip */
1799         azx_init_pci(chip);
1800
1801         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1802                 snd_hdac_i915_set_bclk(bus);
1803
1804         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1805
1806         /* codec detection */
1807         if (!azx_bus(chip)->codec_mask) {
1808                 dev_err(card->dev, "no codecs found!\n");
1809                 return -ENODEV;
1810         }
1811
1812         if (azx_acquire_irq(chip, 0) < 0)
1813                 return -EBUSY;
1814
1815         strcpy(card->driver, "HDA-Intel");
1816         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1817                 sizeof(card->shortname));
1818         snprintf(card->longname, sizeof(card->longname),
1819                  "%s at 0x%lx irq %i",
1820                  card->shortname, bus->addr, bus->irq);
1821
1822         return 0;
1823 }
1824
1825 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1826 /* callback from request_firmware_nowait() */
1827 static void azx_firmware_cb(const struct firmware *fw, void *context)
1828 {
1829         struct snd_card *card = context;
1830         struct azx *chip = card->private_data;
1831
1832         if (fw)
1833                 chip->fw = fw;
1834         else
1835                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
1836         if (!chip->disabled) {
1837                 /* continue probing */
1838                 azx_probe_continue(chip);
1839         }
1840 }
1841 #endif
1842
1843 /*
1844  * HDA controller ops.
1845  */
1846
1847 /* PCI register access. */
1848 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1849 {
1850         writel(value, addr);
1851 }
1852
1853 static u32 pci_azx_readl(u32 __iomem *addr)
1854 {
1855         return readl(addr);
1856 }
1857
1858 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1859 {
1860         writew(value, addr);
1861 }
1862
1863 static u16 pci_azx_readw(u16 __iomem *addr)
1864 {
1865         return readw(addr);
1866 }
1867
1868 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1869 {
1870         writeb(value, addr);
1871 }
1872
1873 static u8 pci_azx_readb(u8 __iomem *addr)
1874 {
1875         return readb(addr);
1876 }
1877
1878 static int disable_msi_reset_irq(struct azx *chip)
1879 {
1880         struct hdac_bus *bus = azx_bus(chip);
1881         int err;
1882
1883         free_irq(bus->irq, chip);
1884         bus->irq = -1;
1885         pci_disable_msi(chip->pci);
1886         chip->msi = 0;
1887         err = azx_acquire_irq(chip, 1);
1888         if (err < 0)
1889                 return err;
1890
1891         return 0;
1892 }
1893
1894 /* DMA page allocation helpers.  */
1895 static int dma_alloc_pages(struct hdac_bus *bus,
1896                            int type,
1897                            size_t size,
1898                            struct snd_dma_buffer *buf)
1899 {
1900         struct azx *chip = bus_to_azx(bus);
1901         int err;
1902
1903         err = snd_dma_alloc_pages(type,
1904                                   bus->dev,
1905                                   size, buf);
1906         if (err < 0)
1907                 return err;
1908         mark_pages_wc(chip, buf, true);
1909         return 0;
1910 }
1911
1912 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1913 {
1914         struct azx *chip = bus_to_azx(bus);
1915
1916         mark_pages_wc(chip, buf, false);
1917         snd_dma_free_pages(buf);
1918 }
1919
1920 static int substream_alloc_pages(struct azx *chip,
1921                                  struct snd_pcm_substream *substream,
1922                                  size_t size)
1923 {
1924         struct azx_dev *azx_dev = get_azx_dev(substream);
1925         int ret;
1926
1927         mark_runtime_wc(chip, azx_dev, substream, false);
1928         ret = snd_pcm_lib_malloc_pages(substream, size);
1929         if (ret < 0)
1930                 return ret;
1931         mark_runtime_wc(chip, azx_dev, substream, true);
1932         return 0;
1933 }
1934
1935 static int substream_free_pages(struct azx *chip,
1936                                 struct snd_pcm_substream *substream)
1937 {
1938         struct azx_dev *azx_dev = get_azx_dev(substream);
1939         mark_runtime_wc(chip, azx_dev, substream, false);
1940         return snd_pcm_lib_free_pages(substream);
1941 }
1942
1943 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1944                              struct vm_area_struct *area)
1945 {
1946 #ifdef CONFIG_X86
1947         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1948         struct azx *chip = apcm->chip;
1949         if (chip->uc_buffer)
1950                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1951 #endif
1952 }
1953
1954 static const struct hdac_io_ops pci_hda_io_ops = {
1955         .reg_writel = pci_azx_writel,
1956         .reg_readl = pci_azx_readl,
1957         .reg_writew = pci_azx_writew,
1958         .reg_readw = pci_azx_readw,
1959         .reg_writeb = pci_azx_writeb,
1960         .reg_readb = pci_azx_readb,
1961         .dma_alloc_pages = dma_alloc_pages,
1962         .dma_free_pages = dma_free_pages,
1963 };
1964
1965 /* Blacklist for skipping the whole probe:
1966  * some HD-audio PCI entries are exposed without any codecs, and such devices
1967  * should be ignored from the beginning.
1968  */
1969 static const struct pci_device_id driver_blacklist[] = {
1970         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
1971         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
1972         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
1973         {}
1974 };
1975
1976 static const struct hda_controller_ops pci_hda_ops = {
1977         .disable_msi_reset_irq = disable_msi_reset_irq,
1978         .substream_alloc_pages = substream_alloc_pages,
1979         .substream_free_pages = substream_free_pages,
1980         .pcm_mmap_prepare = pcm_mmap_prepare,
1981         .position_check = azx_position_check,
1982         .link_power = azx_intel_link_power,
1983 };
1984
1985 static int azx_probe(struct pci_dev *pci,
1986                      const struct pci_device_id *pci_id)
1987 {
1988         static int dev;
1989         struct snd_card *card;
1990         struct hda_intel *hda;
1991         struct azx *chip;
1992         bool schedule_probe;
1993         int err;
1994
1995         if (pci_match_id(driver_blacklist, pci)) {
1996                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
1997                 return -ENODEV;
1998         }
1999
2000         if (dev >= SNDRV_CARDS)
2001                 return -ENODEV;
2002         if (!enable[dev]) {
2003                 dev++;
2004                 return -ENOENT;
2005         }
2006
2007         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2008                            0, &card);
2009         if (err < 0) {
2010                 dev_err(&pci->dev, "Error creating card!\n");
2011                 return err;
2012         }
2013
2014         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2015         if (err < 0)
2016                 goto out_free;
2017         card->private_data = chip;
2018         hda = container_of(chip, struct hda_intel, chip);
2019
2020         pci_set_drvdata(pci, card);
2021
2022         err = register_vga_switcheroo(chip);
2023         if (err < 0) {
2024                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2025                 goto out_free;
2026         }
2027
2028         if (check_hdmi_disabled(pci)) {
2029                 dev_info(card->dev, "VGA controller is disabled\n");
2030                 dev_info(card->dev, "Delaying initialization\n");
2031                 chip->disabled = true;
2032         }
2033
2034         schedule_probe = !chip->disabled;
2035
2036 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2037         if (patch[dev] && *patch[dev]) {
2038                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2039                          patch[dev]);
2040                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2041                                               &pci->dev, GFP_KERNEL, card,
2042                                               azx_firmware_cb);
2043                 if (err < 0)
2044                         goto out_free;
2045                 schedule_probe = false; /* continued in azx_firmware_cb() */
2046         }
2047 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2048
2049 #ifndef CONFIG_SND_HDA_I915
2050         if (CONTROLLER_IN_GPU(pci))
2051                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2052 #endif
2053
2054         if (schedule_probe)
2055                 schedule_work(&hda->probe_work);
2056
2057         dev++;
2058         if (chip->disabled)
2059                 complete_all(&hda->probe_wait);
2060         return 0;
2061
2062 out_free:
2063         snd_card_free(card);
2064         return err;
2065 }
2066
2067 #ifdef CONFIG_PM
2068 /* On some boards setting power_save to a non 0 value leads to clicking /
2069  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2070  * figure out how to avoid these sounds, but that is not always feasible.
2071  * So we keep a list of devices where we disable powersaving as its known
2072  * to causes problems on these devices.
2073  */
2074 static struct snd_pci_quirk power_save_blacklist[] = {
2075         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2076         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2077         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2078         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2079         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2080         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2081         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2082         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2083         {}
2084 };
2085 #endif /* CONFIG_PM */
2086
2087 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2088 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2089         [AZX_DRIVER_NVIDIA] = 8,
2090         [AZX_DRIVER_TERA] = 1,
2091 };
2092
2093 static int azx_probe_continue(struct azx *chip)
2094 {
2095         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2096         struct hdac_bus *bus = azx_bus(chip);
2097         struct pci_dev *pci = chip->pci;
2098         int dev = chip->dev_index;
2099         int val;
2100         int err;
2101
2102         to_hda_bus(bus)->bus_probing = 1;
2103         hda->probe_continued = 1;
2104
2105         /* Request display power well for the HDA controller or codec. For
2106          * Haswell/Broadwell, both the display HDA controller and codec need
2107          * this power. For other platforms, like Baytrail/Braswell, only the
2108          * display codec needs the power and it can be released after probe.
2109          */
2110         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2111                 /* HSW/BDW controllers need this power */
2112                 if (CONTROLLER_IN_GPU(pci))
2113                         hda->need_i915_power = 1;
2114
2115                 err = snd_hdac_i915_init(bus);
2116                 if (err < 0) {
2117                         /* if the controller is bound only with HDMI/DP
2118                          * (for HSW and BDW), we need to abort the probe;
2119                          * for other chips, still continue probing as other
2120                          * codecs can be on the same link.
2121                          */
2122                         if (CONTROLLER_IN_GPU(pci)) {
2123                                 dev_err(chip->card->dev,
2124                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2125                                 goto out_free;
2126                         } else
2127                                 goto skip_i915;
2128                 }
2129
2130                 err = snd_hdac_display_power(bus, true);
2131                 if (err < 0) {
2132                         dev_err(chip->card->dev,
2133                                 "Cannot turn on display power on i915\n");
2134                         goto i915_power_fail;
2135                 }
2136         }
2137
2138  skip_i915:
2139         err = azx_first_init(chip);
2140         if (err < 0)
2141                 goto out_free;
2142
2143 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2144         chip->beep_mode = beep_mode[dev];
2145 #endif
2146
2147         /* create codec instances */
2148         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2149         if (err < 0)
2150                 goto out_free;
2151
2152 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2153         if (chip->fw) {
2154                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2155                                          chip->fw->data);
2156                 if (err < 0)
2157                         goto out_free;
2158 #ifndef CONFIG_PM
2159                 release_firmware(chip->fw); /* no longer needed */
2160                 chip->fw = NULL;
2161 #endif
2162         }
2163 #endif
2164         if ((probe_only[dev] & 1) == 0) {
2165                 err = azx_codec_configure(chip);
2166                 if (err < 0)
2167                         goto out_free;
2168         }
2169
2170         err = snd_card_register(chip->card);
2171         if (err < 0)
2172                 goto out_free;
2173
2174         chip->running = 1;
2175         azx_add_card_list(chip);
2176
2177         val = power_save;
2178 #ifdef CONFIG_PM
2179         if (pm_blacklist) {
2180                 const struct snd_pci_quirk *q;
2181
2182                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2183                 if (q && val) {
2184                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2185                                  q->subvendor, q->subdevice);
2186                         val = 0;
2187                 }
2188         }
2189 #endif /* CONFIG_PM */
2190         snd_hda_set_power_save(&chip->bus, val * 1000);
2191         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2192                 pm_runtime_put_autosuspend(&pci->dev);
2193
2194 out_free:
2195         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2196                 && !hda->need_i915_power)
2197                 snd_hdac_display_power(bus, false);
2198
2199 i915_power_fail:
2200         if (err < 0)
2201                 hda->init_failed = 1;
2202         complete_all(&hda->probe_wait);
2203         to_hda_bus(bus)->bus_probing = 0;
2204         return err;
2205 }
2206
2207 static void azx_remove(struct pci_dev *pci)
2208 {
2209         struct snd_card *card = pci_get_drvdata(pci);
2210         struct azx *chip;
2211         struct hda_intel *hda;
2212
2213         if (card) {
2214                 /* cancel the pending probing work */
2215                 chip = card->private_data;
2216                 hda = container_of(chip, struct hda_intel, chip);
2217                 /* FIXME: below is an ugly workaround.
2218                  * Both device_release_driver() and driver_probe_device()
2219                  * take *both* the device's and its parent's lock before
2220                  * calling the remove() and probe() callbacks.  The codec
2221                  * probe takes the locks of both the codec itself and its
2222                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2223                  * the PCI controller is unbound, it takes its lock, too
2224                  * ==> ouch, a deadlock!
2225                  * As a workaround, we unlock temporarily here the controller
2226                  * device during cancel_work_sync() call.
2227                  */
2228                 device_unlock(&pci->dev);
2229                 cancel_work_sync(&hda->probe_work);
2230                 device_lock(&pci->dev);
2231
2232                 snd_card_free(card);
2233         }
2234 }
2235
2236 static void azx_shutdown(struct pci_dev *pci)
2237 {
2238         struct snd_card *card = pci_get_drvdata(pci);
2239         struct azx *chip;
2240
2241         if (!card)
2242                 return;
2243         chip = card->private_data;
2244         if (chip && chip->running)
2245                 azx_stop_chip(chip);
2246 }
2247
2248 /* PCI IDs */
2249 static const struct pci_device_id azx_ids[] = {
2250         /* CPT */
2251         { PCI_DEVICE(0x8086, 0x1c20),
2252           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2253         /* PBG */
2254         { PCI_DEVICE(0x8086, 0x1d20),
2255           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2256         /* Panther Point */
2257         { PCI_DEVICE(0x8086, 0x1e20),
2258           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2259         /* Lynx Point */
2260         { PCI_DEVICE(0x8086, 0x8c20),
2261           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2262         /* 9 Series */
2263         { PCI_DEVICE(0x8086, 0x8ca0),
2264           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2265         /* Wellsburg */
2266         { PCI_DEVICE(0x8086, 0x8d20),
2267           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2268         { PCI_DEVICE(0x8086, 0x8d21),
2269           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2270         /* Lewisburg */
2271         { PCI_DEVICE(0x8086, 0xa1f0),
2272           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2273         { PCI_DEVICE(0x8086, 0xa270),
2274           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2275         /* Lynx Point-LP */
2276         { PCI_DEVICE(0x8086, 0x9c20),
2277           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2278         /* Lynx Point-LP */
2279         { PCI_DEVICE(0x8086, 0x9c21),
2280           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2281         /* Wildcat Point-LP */
2282         { PCI_DEVICE(0x8086, 0x9ca0),
2283           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2284         /* Sunrise Point */
2285         { PCI_DEVICE(0x8086, 0xa170),
2286           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2287         /* Sunrise Point-LP */
2288         { PCI_DEVICE(0x8086, 0x9d70),
2289           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2290         /* Kabylake */
2291         { PCI_DEVICE(0x8086, 0xa171),
2292           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2293         /* Kabylake-LP */
2294         { PCI_DEVICE(0x8086, 0x9d71),
2295           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2296         /* Kabylake-H */
2297         { PCI_DEVICE(0x8086, 0xa2f0),
2298           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2299         /* Broxton-P(Apollolake) */
2300         { PCI_DEVICE(0x8086, 0x5a98),
2301           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2302         /* Broxton-T */
2303         { PCI_DEVICE(0x8086, 0x1a98),
2304           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2305         /* Haswell */
2306         { PCI_DEVICE(0x8086, 0x0a0c),
2307           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2308         { PCI_DEVICE(0x8086, 0x0c0c),
2309           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2310         { PCI_DEVICE(0x8086, 0x0d0c),
2311           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2312         /* Broadwell */
2313         { PCI_DEVICE(0x8086, 0x160c),
2314           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2315         /* 5 Series/3400 */
2316         { PCI_DEVICE(0x8086, 0x3b56),
2317           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2318         /* Poulsbo */
2319         { PCI_DEVICE(0x8086, 0x811b),
2320           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2321         /* Oaktrail */
2322         { PCI_DEVICE(0x8086, 0x080a),
2323           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2324         /* BayTrail */
2325         { PCI_DEVICE(0x8086, 0x0f04),
2326           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2327         /* Braswell */
2328         { PCI_DEVICE(0x8086, 0x2284),
2329           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2330         /* ICH6 */
2331         { PCI_DEVICE(0x8086, 0x2668),
2332           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2333         /* ICH7 */
2334         { PCI_DEVICE(0x8086, 0x27d8),
2335           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2336         /* ESB2 */
2337         { PCI_DEVICE(0x8086, 0x269a),
2338           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2339         /* ICH8 */
2340         { PCI_DEVICE(0x8086, 0x284b),
2341           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2342         /* ICH9 */
2343         { PCI_DEVICE(0x8086, 0x293e),
2344           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2345         /* ICH9 */
2346         { PCI_DEVICE(0x8086, 0x293f),
2347           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2348         /* ICH10 */
2349         { PCI_DEVICE(0x8086, 0x3a3e),
2350           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2351         /* ICH10 */
2352         { PCI_DEVICE(0x8086, 0x3a6e),
2353           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2354         /* Generic Intel */
2355         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2356           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2357           .class_mask = 0xffffff,
2358           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2359         /* ATI SB 450/600/700/800/900 */
2360         { PCI_DEVICE(0x1002, 0x437b),
2361           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2362         { PCI_DEVICE(0x1002, 0x4383),
2363           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2364         /* AMD Hudson */
2365         { PCI_DEVICE(0x1022, 0x780d),
2366           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2367         /* AMD Stoney */
2368         { PCI_DEVICE(0x1022, 0x157a),
2369           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2370                          AZX_DCAPS_PM_RUNTIME },
2371         /* AMD Raven */
2372         { PCI_DEVICE(0x1022, 0x15e3),
2373           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2374                          AZX_DCAPS_PM_RUNTIME },
2375         /* ATI HDMI */
2376         { PCI_DEVICE(0x1002, 0x0002),
2377           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2378         { PCI_DEVICE(0x1002, 0x1308),
2379           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2380         { PCI_DEVICE(0x1002, 0x157a),
2381           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2382         { PCI_DEVICE(0x1002, 0x15b3),
2383           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2384         { PCI_DEVICE(0x1002, 0x793b),
2385           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2386         { PCI_DEVICE(0x1002, 0x7919),
2387           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2388         { PCI_DEVICE(0x1002, 0x960f),
2389           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2390         { PCI_DEVICE(0x1002, 0x970f),
2391           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2392         { PCI_DEVICE(0x1002, 0x9840),
2393           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2394         { PCI_DEVICE(0x1002, 0xaa00),
2395           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2396         { PCI_DEVICE(0x1002, 0xaa08),
2397           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2398         { PCI_DEVICE(0x1002, 0xaa10),
2399           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2400         { PCI_DEVICE(0x1002, 0xaa18),
2401           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2402         { PCI_DEVICE(0x1002, 0xaa20),
2403           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2404         { PCI_DEVICE(0x1002, 0xaa28),
2405           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2406         { PCI_DEVICE(0x1002, 0xaa30),
2407           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2408         { PCI_DEVICE(0x1002, 0xaa38),
2409           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2410         { PCI_DEVICE(0x1002, 0xaa40),
2411           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2412         { PCI_DEVICE(0x1002, 0xaa48),
2413           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2414         { PCI_DEVICE(0x1002, 0xaa50),
2415           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2416         { PCI_DEVICE(0x1002, 0xaa58),
2417           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2418         { PCI_DEVICE(0x1002, 0xaa60),
2419           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2420         { PCI_DEVICE(0x1002, 0xaa68),
2421           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2422         { PCI_DEVICE(0x1002, 0xaa80),
2423           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2424         { PCI_DEVICE(0x1002, 0xaa88),
2425           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2426         { PCI_DEVICE(0x1002, 0xaa90),
2427           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2428         { PCI_DEVICE(0x1002, 0xaa98),
2429           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2430         { PCI_DEVICE(0x1002, 0x9902),
2431           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2432         { PCI_DEVICE(0x1002, 0xaaa0),
2433           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2434         { PCI_DEVICE(0x1002, 0xaaa8),
2435           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2436         { PCI_DEVICE(0x1002, 0xaab0),
2437           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2438         { PCI_DEVICE(0x1002, 0xaac0),
2439           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2440         { PCI_DEVICE(0x1002, 0xaac8),
2441           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2442         { PCI_DEVICE(0x1002, 0xaad8),
2443           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2444         { PCI_DEVICE(0x1002, 0xaae8),
2445           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2446         { PCI_DEVICE(0x1002, 0xaae0),
2447           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2448         { PCI_DEVICE(0x1002, 0xaaf0),
2449           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2450         /* VIA VT8251/VT8237A */
2451         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2452         /* VIA GFX VT7122/VX900 */
2453         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2454         /* VIA GFX VT6122/VX11 */
2455         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2456         /* SIS966 */
2457         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2458         /* ULI M5461 */
2459         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2460         /* NVIDIA MCP */
2461         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2462           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2463           .class_mask = 0xffffff,
2464           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2465         /* Teradici */
2466         { PCI_DEVICE(0x6549, 0x1200),
2467           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2468         { PCI_DEVICE(0x6549, 0x2200),
2469           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2470         /* Creative X-Fi (CA0110-IBG) */
2471         /* CTHDA chips */
2472         { PCI_DEVICE(0x1102, 0x0010),
2473           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2474         { PCI_DEVICE(0x1102, 0x0012),
2475           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2476 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2477         /* the following entry conflicts with snd-ctxfi driver,
2478          * as ctxfi driver mutates from HD-audio to native mode with
2479          * a special command sequence.
2480          */
2481         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2482           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2483           .class_mask = 0xffffff,
2484           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2485           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2486 #else
2487         /* this entry seems still valid -- i.e. without emu20kx chip */
2488         { PCI_DEVICE(0x1102, 0x0009),
2489           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2490           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2491 #endif
2492         /* CM8888 */
2493         { PCI_DEVICE(0x13f6, 0x5011),
2494           .driver_data = AZX_DRIVER_CMEDIA |
2495           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2496         /* Vortex86MX */
2497         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2498         /* VMware HDAudio */
2499         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2500         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2501         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2502           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2503           .class_mask = 0xffffff,
2504           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2505         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2506           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2507           .class_mask = 0xffffff,
2508           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2509         { 0, }
2510 };
2511 MODULE_DEVICE_TABLE(pci, azx_ids);
2512
2513 /* pci_driver definition */
2514 static struct pci_driver azx_driver = {
2515         .name = KBUILD_MODNAME,
2516         .id_table = azx_ids,
2517         .probe = azx_probe,
2518         .remove = azx_remove,
2519         .shutdown = azx_shutdown,
2520         .driver = {
2521                 .pm = AZX_PM_OPS,
2522         },
2523 };
2524
2525 module_pci_driver(azx_driver);