1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Implementation of primary alsa driver code base for Intel HD Audio.
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
12 #include <linux/clocksource.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
21 /* for art-tsc conversion */
25 #include <sound/core.h>
26 #include <sound/initval.h>
27 #include "hda_controller.h"
29 #define CREATE_TRACE_POINTS
30 #include "hda_controller_trace.h"
32 /* DSP lock helpers */
33 #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
34 #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
35 #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
37 /* assign a stream for the PCM */
38 static inline struct azx_dev *
39 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
41 struct hdac_stream *s;
43 s = snd_hdac_stream_assign(azx_bus(chip), substream);
46 return stream_to_azx_dev(s);
49 /* release the assigned stream */
50 static inline void azx_release_device(struct azx_dev *azx_dev)
52 snd_hdac_stream_release(azx_stream(azx_dev));
55 static inline struct hda_pcm_stream *
56 to_hda_pcm_stream(struct snd_pcm_substream *substream)
58 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
59 return &apcm->info->stream[substream->stream];
62 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
65 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
66 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
67 u64 codec_frames, codec_nsecs;
69 if (!hinfo->ops.get_delay)
72 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
73 codec_nsecs = div_u64(codec_frames * 1000000000LL,
74 substream->runtime->rate);
76 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
77 return nsec + codec_nsecs;
79 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
86 static int azx_pcm_close(struct snd_pcm_substream *substream)
88 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
89 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
90 struct azx *chip = apcm->chip;
91 struct azx_dev *azx_dev = get_azx_dev(substream);
93 trace_azx_pcm_close(chip, azx_dev);
94 mutex_lock(&chip->open_mutex);
95 azx_release_device(azx_dev);
97 hinfo->ops.close(hinfo, apcm->codec, substream);
98 snd_hda_power_down(apcm->codec);
99 mutex_unlock(&chip->open_mutex);
100 snd_hda_codec_pcm_put(apcm->info);
104 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
105 struct snd_pcm_hw_params *hw_params)
107 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
108 struct azx *chip = apcm->chip;
109 struct azx_dev *azx_dev = get_azx_dev(substream);
112 trace_azx_pcm_hw_params(chip, azx_dev);
114 if (dsp_is_locked(azx_dev)) {
119 azx_dev->core.bufsize = 0;
120 azx_dev->core.period_bytes = 0;
121 azx_dev->core.format_val = 0;
122 ret = snd_pcm_lib_malloc_pages(substream,
123 params_buffer_bytes(hw_params));
130 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
132 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
133 struct azx_dev *azx_dev = get_azx_dev(substream);
134 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
137 /* reset BDL address */
139 if (!dsp_is_locked(azx_dev))
140 snd_hdac_stream_cleanup(azx_stream(azx_dev));
142 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
144 err = snd_pcm_lib_free_pages(substream);
145 azx_stream(azx_dev)->prepared = 0;
150 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
152 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
153 struct azx *chip = apcm->chip;
154 struct azx_dev *azx_dev = get_azx_dev(substream);
155 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
156 struct snd_pcm_runtime *runtime = substream->runtime;
157 unsigned int format_val, stream_tag;
159 struct hda_spdif_out *spdif =
160 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
161 unsigned short ctls = spdif ? spdif->ctls : 0;
163 trace_azx_pcm_prepare(chip, azx_dev);
165 if (dsp_is_locked(azx_dev)) {
170 snd_hdac_stream_reset(azx_stream(azx_dev));
171 format_val = snd_hdac_calc_stream_format(runtime->rate,
177 dev_err(chip->card->dev,
178 "invalid format_val, rate=%d, ch=%d, format=%d\n",
179 runtime->rate, runtime->channels, runtime->format);
184 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
188 snd_hdac_stream_setup(azx_stream(azx_dev));
190 stream_tag = azx_dev->core.stream_tag;
191 /* CA-IBG chips need the playback stream starting from 1 */
192 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
193 stream_tag > chip->capture_streams)
194 stream_tag -= chip->capture_streams;
195 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
196 azx_dev->core.format_val, substream);
200 azx_stream(azx_dev)->prepared = 1;
205 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
207 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
208 struct azx *chip = apcm->chip;
209 struct hdac_bus *bus = azx_bus(chip);
210 struct azx_dev *azx_dev;
211 struct snd_pcm_substream *s;
212 struct hdac_stream *hstr;
217 azx_dev = get_azx_dev(substream);
218 trace_azx_pcm_trigger(chip, azx_dev, cmd);
220 hstr = azx_stream(azx_dev);
221 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
222 sync_reg = AZX_REG_OLD_SSYNC;
224 sync_reg = AZX_REG_SSYNC;
226 if (dsp_is_locked(azx_dev) || !hstr->prepared)
230 case SNDRV_PCM_TRIGGER_START:
231 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
232 case SNDRV_PCM_TRIGGER_RESUME:
235 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
236 case SNDRV_PCM_TRIGGER_SUSPEND:
237 case SNDRV_PCM_TRIGGER_STOP:
244 snd_pcm_group_for_each_entry(s, substream) {
245 if (s->pcm->card != substream->pcm->card)
247 azx_dev = get_azx_dev(s);
248 sbits |= 1 << azx_dev->core.index;
249 snd_pcm_trigger_done(s, substream);
252 spin_lock(&bus->reg_lock);
254 /* first, set SYNC bits of corresponding streams */
255 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
257 snd_pcm_group_for_each_entry(s, substream) {
258 if (s->pcm->card != substream->pcm->card)
260 azx_dev = get_azx_dev(s);
262 azx_dev->insufficient = 1;
263 snd_hdac_stream_start(azx_stream(azx_dev), true);
265 snd_hdac_stream_stop(azx_stream(azx_dev));
268 spin_unlock(&bus->reg_lock);
270 snd_hdac_stream_sync(hstr, start, sbits);
272 spin_lock(&bus->reg_lock);
273 /* reset SYNC bits */
274 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
276 snd_hdac_stream_timecounter_init(hstr, sbits);
277 spin_unlock(&bus->reg_lock);
281 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
283 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
285 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
287 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
289 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
291 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
293 unsigned int azx_get_position(struct azx *chip,
294 struct azx_dev *azx_dev)
296 struct snd_pcm_substream *substream = azx_dev->core.substream;
298 int stream = substream->stream;
301 if (chip->get_position[stream])
302 pos = chip->get_position[stream](chip, azx_dev);
303 else /* use the position buffer as default */
304 pos = azx_get_pos_posbuf(chip, azx_dev);
306 if (pos >= azx_dev->core.bufsize)
309 if (substream->runtime) {
310 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
311 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
313 if (chip->get_delay[stream])
314 delay += chip->get_delay[stream](chip, azx_dev, pos);
315 if (hinfo->ops.get_delay)
316 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
318 substream->runtime->delay = delay;
321 trace_azx_get_position(chip, azx_dev, pos, delay);
324 EXPORT_SYMBOL_GPL(azx_get_position);
326 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
328 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
329 struct azx *chip = apcm->chip;
330 struct azx_dev *azx_dev = get_azx_dev(substream);
331 return bytes_to_frames(substream->runtime,
332 azx_get_position(chip, azx_dev));
336 * azx_scale64: Scale base by mult/div while not overflowing sanely
338 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
340 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
341 * is about 384307 ie ~4.5 days.
343 * This scales the calculation so that overflow will happen but after 2^64 /
344 * 48000 secs, which is pretty large!
347 * base may overflow, but since there isn’t any additional division
348 * performed on base it’s OK
349 * rem can’t overflow because both are 32-bit values
353 static u64 azx_scale64(u64 base, u32 num, u32 den)
357 rem = do_div(base, den);
367 static int azx_get_sync_time(ktime_t *device,
368 struct system_counterval_t *system, void *ctx)
370 struct snd_pcm_substream *substream = ctx;
371 struct azx_dev *azx_dev = get_azx_dev(substream);
372 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
373 struct azx *chip = apcm->chip;
374 struct snd_pcm_runtime *runtime;
375 u64 ll_counter, ll_counter_l, ll_counter_h;
376 u64 tsc_counter, tsc_counter_l, tsc_counter_h;
377 u32 wallclk_ctr, wallclk_cycles;
383 runtime = substream->runtime;
385 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
390 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
393 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
394 (azx_dev->core.stream_tag - 1);
395 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
397 /* Enable the capture */
398 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
401 if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
409 dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
413 /* Read wall clock counter */
414 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
416 /* Read TSC counter */
417 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
418 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
420 /* Read Link counter */
421 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
422 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
424 /* Ack: registers read done */
425 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
427 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
430 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
431 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
434 * An error occurs near frame "rollover". The clocks in
435 * frame value indicates whether this error may have
436 * occurred. Here we use the value of 10 i.e.,
437 * HDA_MAX_CYCLE_OFFSET
439 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
440 && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
444 * Sleep before we read again, else we may again get
445 * value near to MAX_CYCLE. Try to sleep for different
446 * amount of time so we dont hit the same number again
448 udelay(retry_count++);
450 } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
452 if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
453 dev_err_ratelimited(chip->card->dev,
454 "Error in WALFCC cycle count\n");
458 *device = ns_to_ktime(azx_scale64(ll_counter,
459 NSEC_PER_SEC, runtime->rate));
460 *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
461 ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
463 *system = convert_art_to_tsc(tsc_counter);
469 static int azx_get_sync_time(ktime_t *device,
470 struct system_counterval_t *system, void *ctx)
476 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
477 struct system_device_crosststamp *xtstamp)
479 return get_device_system_crosststamp(azx_get_sync_time,
480 substream, NULL, xtstamp);
483 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
484 struct snd_pcm_audio_tstamp_config *ts)
486 if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
487 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
493 static int azx_get_time_info(struct snd_pcm_substream *substream,
494 struct timespec *system_ts, struct timespec *audio_ts,
495 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
496 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
498 struct azx_dev *azx_dev = get_azx_dev(substream);
499 struct snd_pcm_runtime *runtime = substream->runtime;
500 struct system_device_crosststamp xtstamp;
504 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
505 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
507 snd_pcm_gettime(substream->runtime, system_ts);
509 nsec = timecounter_read(&azx_dev->core.tc);
510 nsec = div_u64(nsec, 3); /* can be optimized */
511 if (audio_tstamp_config->report_delay)
512 nsec = azx_adjust_codec_delay(substream, nsec);
514 *audio_ts = ns_to_timespec(nsec);
516 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
517 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
518 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
520 } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
522 ret = azx_get_crosststamp(substream, &xtstamp);
526 switch (runtime->tstamp_type) {
527 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
530 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
531 *system_ts = ktime_to_timespec(xtstamp.sys_monoraw);
535 *system_ts = ktime_to_timespec(xtstamp.sys_realtime);
540 *audio_ts = ktime_to_timespec(xtstamp.device);
542 audio_tstamp_report->actual_type =
543 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
544 audio_tstamp_report->accuracy_report = 1;
545 /* 24 MHz WallClock == 42ns resolution */
546 audio_tstamp_report->accuracy = 42;
549 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
555 static struct snd_pcm_hardware azx_pcm_hw = {
556 .info = (SNDRV_PCM_INFO_MMAP |
557 SNDRV_PCM_INFO_INTERLEAVED |
558 SNDRV_PCM_INFO_BLOCK_TRANSFER |
559 SNDRV_PCM_INFO_MMAP_VALID |
560 /* No full-resume yet implemented */
561 /* SNDRV_PCM_INFO_RESUME |*/
562 SNDRV_PCM_INFO_PAUSE |
563 SNDRV_PCM_INFO_SYNC_START |
564 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
565 SNDRV_PCM_INFO_HAS_LINK_ATIME |
566 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
567 .formats = SNDRV_PCM_FMTBIT_S16_LE,
568 .rates = SNDRV_PCM_RATE_48000,
573 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
574 .period_bytes_min = 128,
575 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
577 .periods_max = AZX_MAX_FRAG,
581 static int azx_pcm_open(struct snd_pcm_substream *substream)
583 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
584 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
585 struct azx *chip = apcm->chip;
586 struct azx_dev *azx_dev;
587 struct snd_pcm_runtime *runtime = substream->runtime;
591 snd_hda_codec_pcm_get(apcm->info);
592 mutex_lock(&chip->open_mutex);
593 azx_dev = azx_assign_device(chip, substream);
594 trace_azx_pcm_open(chip, azx_dev);
595 if (azx_dev == NULL) {
599 runtime->private_data = azx_dev;
601 runtime->hw = azx_pcm_hw;
602 if (chip->gts_present)
603 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
604 runtime->hw.channels_min = hinfo->channels_min;
605 runtime->hw.channels_max = hinfo->channels_max;
606 runtime->hw.formats = hinfo->formats;
607 runtime->hw.rates = hinfo->rates;
608 snd_pcm_limit_hw_rates(runtime);
609 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
611 /* avoid wrap-around with wall-clock */
612 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
616 if (chip->align_buffer_size)
617 /* constrain buffer sizes to be multiple of 128
618 bytes. This is more efficient in terms of memory
619 access but isn't required by the HDA spec and
620 prevents users from specifying exact period/buffer
621 sizes. For example for 44.1kHz, a period size set
622 to 20ms will be rounded to 19.59ms. */
625 /* Don't enforce steps on buffer sizes, still need to
626 be multiple of 4 bytes (HDA spec). Tested on Intel
627 HDA controllers, may not work on all devices where
628 option needs to be disabled */
631 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
633 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
635 snd_hda_power_up(apcm->codec);
637 err = hinfo->ops.open(hinfo, apcm->codec, substream);
641 azx_release_device(azx_dev);
644 snd_pcm_limit_hw_rates(runtime);
646 if (snd_BUG_ON(!runtime->hw.channels_min) ||
647 snd_BUG_ON(!runtime->hw.channels_max) ||
648 snd_BUG_ON(!runtime->hw.formats) ||
649 snd_BUG_ON(!runtime->hw.rates)) {
650 azx_release_device(azx_dev);
651 if (hinfo->ops.close)
652 hinfo->ops.close(hinfo, apcm->codec, substream);
657 /* disable LINK_ATIME timestamps for capture streams
658 until we figure out how to handle digital inputs */
659 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
660 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
661 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
664 snd_pcm_set_sync(substream);
665 mutex_unlock(&chip->open_mutex);
669 snd_hda_power_down(apcm->codec);
671 mutex_unlock(&chip->open_mutex);
672 snd_hda_codec_pcm_put(apcm->info);
676 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
677 struct vm_area_struct *area)
679 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
680 struct azx *chip = apcm->chip;
681 if (chip->ops->pcm_mmap_prepare)
682 chip->ops->pcm_mmap_prepare(substream, area);
683 return snd_pcm_lib_default_mmap(substream, area);
686 static const struct snd_pcm_ops azx_pcm_ops = {
687 .open = azx_pcm_open,
688 .close = azx_pcm_close,
689 .ioctl = snd_pcm_lib_ioctl,
690 .hw_params = azx_pcm_hw_params,
691 .hw_free = azx_pcm_hw_free,
692 .prepare = azx_pcm_prepare,
693 .trigger = azx_pcm_trigger,
694 .pointer = azx_pcm_pointer,
695 .get_time_info = azx_get_time_info,
696 .mmap = azx_pcm_mmap,
697 .page = snd_pcm_sgbuf_ops_page,
700 static void azx_pcm_free(struct snd_pcm *pcm)
702 struct azx_pcm *apcm = pcm->private_data;
704 list_del(&apcm->list);
705 apcm->info->pcm = NULL;
710 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
712 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
713 struct hda_pcm *cpcm)
715 struct hdac_bus *bus = &_bus->core;
716 struct azx *chip = bus_to_azx(bus);
718 struct azx_pcm *apcm;
719 int pcm_dev = cpcm->device;
722 int type = SNDRV_DMA_TYPE_DEV_SG;
724 list_for_each_entry(apcm, &chip->pcm_list, list) {
725 if (apcm->pcm->device == pcm_dev) {
726 dev_err(chip->card->dev, "PCM %d already exists\n",
731 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
732 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
733 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
737 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
738 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
740 snd_device_free(chip->card, pcm);
747 pcm->private_data = apcm;
748 pcm->private_free = azx_pcm_free;
749 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
750 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
751 list_add_tail(&apcm->list, &chip->pcm_list);
753 for (s = 0; s < 2; s++) {
754 if (cpcm->stream[s].substreams)
755 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
757 /* buffer pre-allocation */
758 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
759 if (size > MAX_PREALLOC_SIZE)
760 size = MAX_PREALLOC_SIZE;
762 type = SNDRV_DMA_TYPE_DEV_UC_SG;
763 snd_pcm_lib_preallocate_pages_for_all(pcm, type,
765 size, MAX_PREALLOC_SIZE);
769 static unsigned int azx_command_addr(u32 cmd)
771 unsigned int addr = cmd >> 28;
773 if (addr >= AZX_MAX_CODECS) {
781 /* receive a response */
782 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
785 struct azx *chip = bus_to_azx(bus);
786 struct hda_bus *hbus = &chip->bus;
787 unsigned long timeout;
788 unsigned long loopcounter;
793 timeout = jiffies + msecs_to_jiffies(1000);
795 for (loopcounter = 0;; loopcounter++) {
796 spin_lock_irq(&bus->reg_lock);
797 if (bus->polling_mode || do_poll)
798 snd_hdac_bus_update_rirb(bus);
799 if (!bus->rirb.cmds[addr]) {
803 *res = bus->rirb.res[addr]; /* the last value */
804 spin_unlock_irq(&bus->reg_lock);
807 spin_unlock_irq(&bus->reg_lock);
808 if (time_after(jiffies, timeout))
810 #define LOOP_COUNT_MAX 3000
811 if (hbus->needs_damn_long_delay ||
812 loopcounter > LOOP_COUNT_MAX) {
813 if (loopcounter > LOOP_COUNT_MAX && !warned) {
814 dev_dbg_ratelimited(chip->card->dev,
815 "too slow response, last cmd=%#08x\n",
816 bus->last_cmd[addr]);
819 msleep(2); /* temporary workaround */
826 if (hbus->no_response_fallback)
829 if (!bus->polling_mode && bus->poll_count < 2) {
830 dev_dbg(chip->card->dev,
831 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
832 bus->last_cmd[addr]);
839 if (!bus->polling_mode) {
840 dev_warn(chip->card->dev,
841 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
842 bus->last_cmd[addr]);
843 bus->polling_mode = 1;
848 dev_warn(chip->card->dev,
849 "No response from codec, disabling MSI: last cmd=0x%08x\n",
850 bus->last_cmd[addr]);
851 if (chip->ops->disable_msi_reset_irq &&
852 chip->ops->disable_msi_reset_irq(chip) < 0)
858 /* If this critical timeout happens during the codec probing
859 * phase, this is likely an access to a non-existing codec
860 * slot. Better to return an error and reset the system.
865 /* no fallback mechanism? */
866 if (!chip->fallback_to_single_cmd)
869 /* a fatal communication error; need either to reset or to fallback
870 * to the single_cmd mode
872 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
873 hbus->response_reset = 1;
874 dev_err(chip->card->dev,
875 "No response from codec, resetting bus: last cmd=0x%08x\n",
876 bus->last_cmd[addr]);
877 return -EAGAIN; /* give a chance to retry */
880 dev_err(chip->card->dev,
881 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
882 bus->last_cmd[addr]);
883 chip->single_cmd = 1;
884 hbus->response_reset = 0;
885 snd_hdac_bus_stop_cmd_io(bus);
890 * Use the single immediate command instead of CORB/RIRB for simplicity
892 * Note: according to Intel, this is not preferred use. The command was
893 * intended for the BIOS only, and may get confused with unsolicited
894 * responses. So, we shouldn't use it for normal operation from the
896 * I left the codes, however, for debugging/testing purposes.
899 /* receive a response */
900 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
905 /* check IRV busy bit */
906 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
907 /* reuse rirb.res as the response return value */
908 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
913 if (printk_ratelimit())
914 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
915 azx_readw(chip, IRS));
916 azx_bus(chip)->rirb.res[addr] = -1;
921 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
923 struct azx *chip = bus_to_azx(bus);
924 unsigned int addr = azx_command_addr(val);
927 bus->last_cmd[azx_command_addr(val)] = val;
929 /* check ICB busy bit */
930 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
931 /* Clear IRV valid bit */
932 azx_writew(chip, IRS, azx_readw(chip, IRS) |
934 azx_writel(chip, IC, val);
935 azx_writew(chip, IRS, azx_readw(chip, IRS) |
937 return azx_single_wait_for_response(chip, addr);
941 if (printk_ratelimit())
942 dev_dbg(chip->card->dev,
943 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
944 azx_readw(chip, IRS), val);
948 /* receive a response */
949 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
953 *res = bus->rirb.res[addr];
958 * The below are the main callbacks from hda_codec.
960 * They are just the skeleton to call sub-callbacks according to the
961 * current setting of chip->single_cmd.
965 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
967 struct azx *chip = bus_to_azx(bus);
971 if (chip->single_cmd)
972 return azx_single_send_cmd(bus, val);
974 return snd_hdac_bus_send_cmd(bus, val);
978 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
981 struct azx *chip = bus_to_azx(bus);
985 if (chip->single_cmd)
986 return azx_single_get_response(bus, addr, res);
988 return azx_rirb_get_response(bus, addr, res);
991 static const struct hdac_bus_ops bus_core_ops = {
992 .command = azx_send_cmd,
993 .get_response = azx_get_response,
996 #ifdef CONFIG_SND_HDA_DSP_LOADER
998 * DSP loading code (e.g. for CA0132)
1001 /* use the first stream for loading DSP */
1002 static struct azx_dev *
1003 azx_get_dsp_loader_dev(struct azx *chip)
1005 struct hdac_bus *bus = azx_bus(chip);
1006 struct hdac_stream *s;
1008 list_for_each_entry(s, &bus->stream_list, list)
1009 if (s->index == chip->playback_index_offset)
1010 return stream_to_azx_dev(s);
1015 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1016 unsigned int byte_size,
1017 struct snd_dma_buffer *bufp)
1019 struct hdac_bus *bus = &codec->bus->core;
1020 struct azx *chip = bus_to_azx(bus);
1021 struct azx_dev *azx_dev;
1022 struct hdac_stream *hstr;
1026 azx_dev = azx_get_dsp_loader_dev(chip);
1027 hstr = azx_stream(azx_dev);
1028 spin_lock_irq(&bus->reg_lock);
1030 chip->saved_azx_dev = *azx_dev;
1033 spin_unlock_irq(&bus->reg_lock);
1035 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
1037 spin_lock_irq(&bus->reg_lock);
1039 *azx_dev = chip->saved_azx_dev;
1040 spin_unlock_irq(&bus->reg_lock);
1047 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
1049 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1051 struct hdac_bus *bus = &codec->bus->core;
1052 struct azx *chip = bus_to_azx(bus);
1053 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1055 snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
1057 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
1059 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1060 struct snd_dma_buffer *dmab)
1062 struct hdac_bus *bus = &codec->bus->core;
1063 struct azx *chip = bus_to_azx(bus);
1064 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1065 struct hdac_stream *hstr = azx_stream(azx_dev);
1067 if (!dmab->area || !hstr->locked)
1070 snd_hdac_dsp_cleanup(hstr, dmab);
1071 spin_lock_irq(&bus->reg_lock);
1073 *azx_dev = chip->saved_azx_dev;
1074 hstr->locked = false;
1075 spin_unlock_irq(&bus->reg_lock);
1077 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1078 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1081 * reset and start the controller registers
1083 void azx_init_chip(struct azx *chip, bool full_reset)
1085 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1086 /* correct RINTCNT for CXT */
1087 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1088 azx_writew(chip, RINTCNT, 0xc0);
1091 EXPORT_SYMBOL_GPL(azx_init_chip);
1093 void azx_stop_all_streams(struct azx *chip)
1095 struct hdac_bus *bus = azx_bus(chip);
1097 snd_hdac_stop_streams(bus);
1099 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1101 void azx_stop_chip(struct azx *chip)
1103 snd_hdac_bus_stop_chip(azx_bus(chip));
1105 EXPORT_SYMBOL_GPL(azx_stop_chip);
1110 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1112 struct azx *chip = bus_to_azx(bus);
1113 struct azx_dev *azx_dev = stream_to_azx_dev(s);
1115 /* check whether this IRQ is really acceptable */
1116 if (!chip->ops->position_check ||
1117 chip->ops->position_check(chip, azx_dev)) {
1118 spin_unlock(&bus->reg_lock);
1119 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1120 spin_lock(&bus->reg_lock);
1124 irqreturn_t azx_interrupt(int irq, void *dev_id)
1126 struct azx *chip = dev_id;
1127 struct hdac_bus *bus = azx_bus(chip);
1129 bool active, handled = false;
1130 int repeat = 0; /* count for avoiding endless loop */
1133 if (azx_has_pm_runtime(chip))
1134 if (!pm_runtime_active(chip->card->dev))
1138 spin_lock(&bus->reg_lock);
1144 status = azx_readl(chip, INTSTS);
1145 if (status == 0 || status == 0xffffffff)
1150 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1153 status = azx_readb(chip, RIRBSTS);
1154 if (status & RIRB_INT_MASK) {
1156 * Clearing the interrupt status here ensures that no
1157 * interrupt gets masked after the RIRB wp is read in
1158 * snd_hdac_bus_update_rirb. This avoids a possible
1159 * race condition where codec response in RIRB may
1160 * remain unserviced by IRQ, eventually falling back
1161 * to polling mode in azx_rirb_get_response.
1163 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1165 if (status & RIRB_INT_RESPONSE) {
1166 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1168 snd_hdac_bus_update_rirb(bus);
1171 } while (active && ++repeat < 10);
1174 spin_unlock(&bus->reg_lock);
1176 return IRQ_RETVAL(handled);
1178 EXPORT_SYMBOL_GPL(azx_interrupt);
1185 * Probe the given codec address
1187 static int probe_codec(struct azx *chip, int addr)
1189 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1190 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1191 struct hdac_bus *bus = azx_bus(chip);
1193 unsigned int res = -1;
1195 mutex_lock(&bus->cmd_mutex);
1197 azx_send_cmd(bus, cmd);
1198 err = azx_get_response(bus, addr, &res);
1200 mutex_unlock(&bus->cmd_mutex);
1201 if (err < 0 || res == -1)
1203 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1207 void snd_hda_bus_reset(struct hda_bus *bus)
1209 struct azx *chip = bus_to_azx(&bus->core);
1212 azx_stop_chip(chip);
1213 azx_init_chip(chip, true);
1214 if (bus->core.chip_init)
1215 snd_hda_bus_reset_codecs(bus);
1219 /* HD-audio bus initialization */
1220 int azx_bus_init(struct azx *chip, const char *model)
1222 struct hda_bus *bus = &chip->bus;
1225 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1229 bus->card = chip->card;
1230 mutex_init(&bus->prepare_mutex);
1231 bus->pci = chip->pci;
1232 bus->modelname = model;
1233 bus->mixer_assigned = -1;
1234 bus->core.snoop = azx_snoop(chip);
1235 if (chip->get_position[0] != azx_get_pos_lpib ||
1236 chip->get_position[1] != azx_get_pos_lpib)
1237 bus->core.use_posbuf = true;
1238 bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1239 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1240 bus->core.corbrp_self_clear = true;
1242 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1243 bus->core.align_bdle_4k = true;
1245 /* AMD chipsets often cause the communication stalls upon certain
1246 * sequence like the pin-detection. It seems that forcing the synced
1247 * access works around the stall. Grrr...
1249 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1250 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1251 bus->core.sync_write = 1;
1252 bus->allow_bus_reset = 1;
1257 EXPORT_SYMBOL_GPL(azx_bus_init);
1260 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1262 struct hdac_bus *bus = azx_bus(chip);
1267 max_slots = AZX_DEFAULT_CODECS;
1269 /* First try to probe all given codec slots */
1270 for (c = 0; c < max_slots; c++) {
1271 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1272 if (probe_codec(chip, c) < 0) {
1273 /* Some BIOSen give you wrong codec addresses
1276 dev_warn(chip->card->dev,
1277 "Codec #%d probe error; disabling it...\n", c);
1278 bus->codec_mask &= ~(1 << c);
1279 /* More badly, accessing to a non-existing
1280 * codec often screws up the controller chip,
1281 * and disturbs the further communications.
1282 * Thus if an error occurs during probing,
1283 * better to reset the controller chip to
1284 * get back to the sanity state.
1286 azx_stop_chip(chip);
1287 azx_init_chip(chip, true);
1292 /* Then create codec instances */
1293 for (c = 0; c < max_slots; c++) {
1294 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1295 struct hda_codec *codec;
1296 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1299 codec->jackpoll_interval = chip->jackpoll_interval;
1300 codec->beep_mode = chip->beep_mode;
1305 dev_err(chip->card->dev, "no codecs initialized\n");
1310 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1312 /* configure each codec instance */
1313 int azx_codec_configure(struct azx *chip)
1315 struct hda_codec *codec, *next;
1317 /* use _safe version here since snd_hda_codec_configure() deregisters
1318 * the device upon error and deletes itself from the bus list.
1320 list_for_each_codec_safe(codec, next, &chip->bus) {
1321 snd_hda_codec_configure(codec);
1324 if (!azx_bus(chip)->num_codecs)
1328 EXPORT_SYMBOL_GPL(azx_codec_configure);
1330 static int stream_direction(struct azx *chip, unsigned char index)
1332 if (index >= chip->capture_index_offset &&
1333 index < chip->capture_index_offset + chip->capture_streams)
1334 return SNDRV_PCM_STREAM_CAPTURE;
1335 return SNDRV_PCM_STREAM_PLAYBACK;
1338 /* initialize SD streams */
1339 int azx_init_streams(struct azx *chip)
1342 int stream_tags[2] = { 0, 0 };
1344 /* initialize each stream (aka device)
1345 * assign the starting bdl address to each stream (device)
1348 for (i = 0; i < chip->num_streams; i++) {
1349 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1355 dir = stream_direction(chip, i);
1356 /* stream tag must be unique throughout
1357 * the stream direction group,
1358 * valid values 1...15
1359 * use separate stream tag if the flag
1360 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1362 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1363 tag = ++stream_tags[dir];
1366 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1372 EXPORT_SYMBOL_GPL(azx_init_streams);
1374 void azx_free_streams(struct azx *chip)
1376 struct hdac_bus *bus = azx_bus(chip);
1377 struct hdac_stream *s;
1379 while (!list_empty(&bus->stream_list)) {
1380 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1382 kfree(stream_to_azx_dev(s));
1385 EXPORT_SYMBOL_GPL(azx_free_streams);