3 * Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 #include <linux/clocksource.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
32 /* for art-tsc conversion */
36 #include <sound/core.h>
37 #include <sound/initval.h>
38 #include "hda_controller.h"
40 #define CREATE_TRACE_POINTS
41 #include "hda_controller_trace.h"
43 /* DSP lock helpers */
44 #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
45 #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
46 #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
48 /* assign a stream for the PCM */
49 static inline struct azx_dev *
50 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
52 struct hdac_stream *s;
54 s = snd_hdac_stream_assign(azx_bus(chip), substream);
57 return stream_to_azx_dev(s);
60 /* release the assigned stream */
61 static inline void azx_release_device(struct azx_dev *azx_dev)
63 snd_hdac_stream_release(azx_stream(azx_dev));
66 static inline struct hda_pcm_stream *
67 to_hda_pcm_stream(struct snd_pcm_substream *substream)
69 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
70 return &apcm->info->stream[substream->stream];
73 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
76 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
77 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
78 u64 codec_frames, codec_nsecs;
80 if (!hinfo->ops.get_delay)
83 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
84 codec_nsecs = div_u64(codec_frames * 1000000000LL,
85 substream->runtime->rate);
87 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
88 return nsec + codec_nsecs;
90 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
97 static int azx_pcm_close(struct snd_pcm_substream *substream)
99 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
100 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
101 struct azx *chip = apcm->chip;
102 struct azx_dev *azx_dev = get_azx_dev(substream);
104 trace_azx_pcm_close(chip, azx_dev);
105 mutex_lock(&chip->open_mutex);
106 azx_release_device(azx_dev);
107 if (hinfo->ops.close)
108 hinfo->ops.close(hinfo, apcm->codec, substream);
109 snd_hda_power_down(apcm->codec);
110 mutex_unlock(&chip->open_mutex);
111 snd_hda_codec_pcm_put(apcm->info);
115 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
116 struct snd_pcm_hw_params *hw_params)
118 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
119 struct azx *chip = apcm->chip;
120 struct azx_dev *azx_dev = get_azx_dev(substream);
123 trace_azx_pcm_hw_params(chip, azx_dev);
125 if (dsp_is_locked(azx_dev)) {
130 azx_dev->core.bufsize = 0;
131 azx_dev->core.period_bytes = 0;
132 azx_dev->core.format_val = 0;
133 ret = chip->ops->substream_alloc_pages(chip, substream,
134 params_buffer_bytes(hw_params));
140 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
142 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
143 struct azx_dev *azx_dev = get_azx_dev(substream);
144 struct azx *chip = apcm->chip;
145 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
148 /* reset BDL address */
150 if (!dsp_is_locked(azx_dev))
151 snd_hdac_stream_cleanup(azx_stream(azx_dev));
153 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
155 err = chip->ops->substream_free_pages(chip, substream);
156 azx_stream(azx_dev)->prepared = 0;
161 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
163 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
164 struct azx *chip = apcm->chip;
165 struct azx_dev *azx_dev = get_azx_dev(substream);
166 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
167 struct snd_pcm_runtime *runtime = substream->runtime;
168 unsigned int format_val, stream_tag;
170 struct hda_spdif_out *spdif =
171 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
172 unsigned short ctls = spdif ? spdif->ctls : 0;
174 trace_azx_pcm_prepare(chip, azx_dev);
176 if (dsp_is_locked(azx_dev)) {
181 snd_hdac_stream_reset(azx_stream(azx_dev));
182 format_val = snd_hdac_calc_stream_format(runtime->rate,
188 dev_err(chip->card->dev,
189 "invalid format_val, rate=%d, ch=%d, format=%d\n",
190 runtime->rate, runtime->channels, runtime->format);
195 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
199 snd_hdac_stream_setup(azx_stream(azx_dev));
201 stream_tag = azx_dev->core.stream_tag;
202 /* CA-IBG chips need the playback stream starting from 1 */
203 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
204 stream_tag > chip->capture_streams)
205 stream_tag -= chip->capture_streams;
206 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
207 azx_dev->core.format_val, substream);
211 azx_stream(azx_dev)->prepared = 1;
216 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
218 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
219 struct azx *chip = apcm->chip;
220 struct hdac_bus *bus = azx_bus(chip);
221 struct azx_dev *azx_dev;
222 struct snd_pcm_substream *s;
223 struct hdac_stream *hstr;
228 azx_dev = get_azx_dev(substream);
229 trace_azx_pcm_trigger(chip, azx_dev, cmd);
231 hstr = azx_stream(azx_dev);
232 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
233 sync_reg = AZX_REG_OLD_SSYNC;
235 sync_reg = AZX_REG_SSYNC;
237 if (dsp_is_locked(azx_dev) || !hstr->prepared)
241 case SNDRV_PCM_TRIGGER_START:
242 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
243 case SNDRV_PCM_TRIGGER_RESUME:
246 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 case SNDRV_PCM_TRIGGER_STOP:
255 snd_pcm_group_for_each_entry(s, substream) {
256 if (s->pcm->card != substream->pcm->card)
258 azx_dev = get_azx_dev(s);
259 sbits |= 1 << azx_dev->core.index;
260 snd_pcm_trigger_done(s, substream);
263 spin_lock(&bus->reg_lock);
265 /* first, set SYNC bits of corresponding streams */
266 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
268 snd_pcm_group_for_each_entry(s, substream) {
269 if (s->pcm->card != substream->pcm->card)
271 azx_dev = get_azx_dev(s);
273 azx_dev->insufficient = 1;
274 snd_hdac_stream_start(azx_stream(azx_dev), true);
276 snd_hdac_stream_stop(azx_stream(azx_dev));
279 spin_unlock(&bus->reg_lock);
281 snd_hdac_stream_sync(hstr, start, sbits);
283 spin_lock(&bus->reg_lock);
284 /* reset SYNC bits */
285 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
287 snd_hdac_stream_timecounter_init(hstr, sbits);
288 spin_unlock(&bus->reg_lock);
292 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
294 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
296 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
298 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
300 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
302 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
304 unsigned int azx_get_position(struct azx *chip,
305 struct azx_dev *azx_dev)
307 struct snd_pcm_substream *substream = azx_dev->core.substream;
309 int stream = substream->stream;
312 if (chip->get_position[stream])
313 pos = chip->get_position[stream](chip, azx_dev);
314 else /* use the position buffer as default */
315 pos = azx_get_pos_posbuf(chip, azx_dev);
317 if (pos >= azx_dev->core.bufsize)
320 if (substream->runtime) {
321 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
322 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
324 if (chip->get_delay[stream])
325 delay += chip->get_delay[stream](chip, azx_dev, pos);
326 if (hinfo->ops.get_delay)
327 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
329 substream->runtime->delay = delay;
332 trace_azx_get_position(chip, azx_dev, pos, delay);
335 EXPORT_SYMBOL_GPL(azx_get_position);
337 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
339 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
340 struct azx *chip = apcm->chip;
341 struct azx_dev *azx_dev = get_azx_dev(substream);
342 return bytes_to_frames(substream->runtime,
343 azx_get_position(chip, azx_dev));
347 * azx_scale64: Scale base by mult/div while not overflowing sanely
349 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
351 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
352 * is about 384307 ie ~4.5 days.
354 * This scales the calculation so that overflow will happen but after 2^64 /
355 * 48000 secs, which is pretty large!
358 * base may overflow, but since there isn’t any additional division
359 * performed on base it’s OK
360 * rem can’t overflow because both are 32-bit values
364 static u64 azx_scale64(u64 base, u32 num, u32 den)
368 rem = do_div(base, den);
378 static int azx_get_sync_time(ktime_t *device,
379 struct system_counterval_t *system, void *ctx)
381 struct snd_pcm_substream *substream = ctx;
382 struct azx_dev *azx_dev = get_azx_dev(substream);
383 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
384 struct azx *chip = apcm->chip;
385 struct snd_pcm_runtime *runtime;
386 u64 ll_counter, ll_counter_l, ll_counter_h;
387 u64 tsc_counter, tsc_counter_l, tsc_counter_h;
388 u32 wallclk_ctr, wallclk_cycles;
394 runtime = substream->runtime;
396 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
401 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
404 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
405 (azx_dev->core.stream_tag - 1);
406 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
408 /* Enable the capture */
409 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
412 if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
420 dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
424 /* Read wall clock counter */
425 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
427 /* Read TSC counter */
428 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
429 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
431 /* Read Link counter */
432 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
433 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
435 /* Ack: registers read done */
436 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
438 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
441 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
442 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
445 * An error occurs near frame "rollover". The clocks in
446 * frame value indicates whether this error may have
447 * occurred. Here we use the value of 10 i.e.,
448 * HDA_MAX_CYCLE_OFFSET
450 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
451 && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
455 * Sleep before we read again, else we may again get
456 * value near to MAX_CYCLE. Try to sleep for different
457 * amount of time so we dont hit the same number again
459 udelay(retry_count++);
461 } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
463 if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
464 dev_err_ratelimited(chip->card->dev,
465 "Error in WALFCC cycle count\n");
469 *device = ns_to_ktime(azx_scale64(ll_counter,
470 NSEC_PER_SEC, runtime->rate));
471 *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
472 ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
474 *system = convert_art_to_tsc(tsc_counter);
480 static int azx_get_sync_time(ktime_t *device,
481 struct system_counterval_t *system, void *ctx)
487 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
488 struct system_device_crosststamp *xtstamp)
490 return get_device_system_crosststamp(azx_get_sync_time,
491 substream, NULL, xtstamp);
494 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
495 struct snd_pcm_audio_tstamp_config *ts)
497 if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
498 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
504 static int azx_get_time_info(struct snd_pcm_substream *substream,
505 struct timespec *system_ts, struct timespec *audio_ts,
506 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
507 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
509 struct azx_dev *azx_dev = get_azx_dev(substream);
510 struct snd_pcm_runtime *runtime = substream->runtime;
511 struct system_device_crosststamp xtstamp;
515 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
516 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
518 snd_pcm_gettime(substream->runtime, system_ts);
520 nsec = timecounter_read(&azx_dev->core.tc);
521 nsec = div_u64(nsec, 3); /* can be optimized */
522 if (audio_tstamp_config->report_delay)
523 nsec = azx_adjust_codec_delay(substream, nsec);
525 *audio_ts = ns_to_timespec(nsec);
527 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
528 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
529 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
531 } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
533 ret = azx_get_crosststamp(substream, &xtstamp);
537 switch (runtime->tstamp_type) {
538 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
541 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
542 *system_ts = ktime_to_timespec(xtstamp.sys_monoraw);
546 *system_ts = ktime_to_timespec(xtstamp.sys_realtime);
551 *audio_ts = ktime_to_timespec(xtstamp.device);
553 audio_tstamp_report->actual_type =
554 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
555 audio_tstamp_report->accuracy_report = 1;
556 /* 24 MHz WallClock == 42ns resolution */
557 audio_tstamp_report->accuracy = 42;
560 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
566 static struct snd_pcm_hardware azx_pcm_hw = {
567 .info = (SNDRV_PCM_INFO_MMAP |
568 SNDRV_PCM_INFO_INTERLEAVED |
569 SNDRV_PCM_INFO_BLOCK_TRANSFER |
570 SNDRV_PCM_INFO_MMAP_VALID |
571 /* No full-resume yet implemented */
572 /* SNDRV_PCM_INFO_RESUME |*/
573 SNDRV_PCM_INFO_PAUSE |
574 SNDRV_PCM_INFO_SYNC_START |
575 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
576 SNDRV_PCM_INFO_HAS_LINK_ATIME |
577 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
578 .formats = SNDRV_PCM_FMTBIT_S16_LE,
579 .rates = SNDRV_PCM_RATE_48000,
584 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
585 .period_bytes_min = 128,
586 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
588 .periods_max = AZX_MAX_FRAG,
592 static int azx_pcm_open(struct snd_pcm_substream *substream)
594 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
595 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
596 struct azx *chip = apcm->chip;
597 struct azx_dev *azx_dev;
598 struct snd_pcm_runtime *runtime = substream->runtime;
602 snd_hda_codec_pcm_get(apcm->info);
603 mutex_lock(&chip->open_mutex);
604 azx_dev = azx_assign_device(chip, substream);
605 trace_azx_pcm_open(chip, azx_dev);
606 if (azx_dev == NULL) {
610 runtime->private_data = azx_dev;
612 runtime->hw = azx_pcm_hw;
613 if (chip->gts_present)
614 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
615 runtime->hw.channels_min = hinfo->channels_min;
616 runtime->hw.channels_max = hinfo->channels_max;
617 runtime->hw.formats = hinfo->formats;
618 runtime->hw.rates = hinfo->rates;
619 snd_pcm_limit_hw_rates(runtime);
620 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
622 /* avoid wrap-around with wall-clock */
623 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
627 if (chip->align_buffer_size)
628 /* constrain buffer sizes to be multiple of 128
629 bytes. This is more efficient in terms of memory
630 access but isn't required by the HDA spec and
631 prevents users from specifying exact period/buffer
632 sizes. For example for 44.1kHz, a period size set
633 to 20ms will be rounded to 19.59ms. */
636 /* Don't enforce steps on buffer sizes, still need to
637 be multiple of 4 bytes (HDA spec). Tested on Intel
638 HDA controllers, may not work on all devices where
639 option needs to be disabled */
642 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
644 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
646 snd_hda_power_up(apcm->codec);
648 err = hinfo->ops.open(hinfo, apcm->codec, substream);
652 azx_release_device(azx_dev);
655 snd_pcm_limit_hw_rates(runtime);
657 if (snd_BUG_ON(!runtime->hw.channels_min) ||
658 snd_BUG_ON(!runtime->hw.channels_max) ||
659 snd_BUG_ON(!runtime->hw.formats) ||
660 snd_BUG_ON(!runtime->hw.rates)) {
661 azx_release_device(azx_dev);
662 if (hinfo->ops.close)
663 hinfo->ops.close(hinfo, apcm->codec, substream);
668 /* disable LINK_ATIME timestamps for capture streams
669 until we figure out how to handle digital inputs */
670 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
671 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
672 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
675 snd_pcm_set_sync(substream);
676 mutex_unlock(&chip->open_mutex);
680 snd_hda_power_down(apcm->codec);
682 mutex_unlock(&chip->open_mutex);
683 snd_hda_codec_pcm_put(apcm->info);
687 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
688 struct vm_area_struct *area)
690 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
691 struct azx *chip = apcm->chip;
692 if (chip->ops->pcm_mmap_prepare)
693 chip->ops->pcm_mmap_prepare(substream, area);
694 return snd_pcm_lib_default_mmap(substream, area);
697 static const struct snd_pcm_ops azx_pcm_ops = {
698 .open = azx_pcm_open,
699 .close = azx_pcm_close,
700 .ioctl = snd_pcm_lib_ioctl,
701 .hw_params = azx_pcm_hw_params,
702 .hw_free = azx_pcm_hw_free,
703 .prepare = azx_pcm_prepare,
704 .trigger = azx_pcm_trigger,
705 .pointer = azx_pcm_pointer,
706 .get_time_info = azx_get_time_info,
707 .mmap = azx_pcm_mmap,
708 .page = snd_pcm_sgbuf_ops_page,
711 static void azx_pcm_free(struct snd_pcm *pcm)
713 struct azx_pcm *apcm = pcm->private_data;
715 list_del(&apcm->list);
716 apcm->info->pcm = NULL;
721 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
723 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
724 struct hda_pcm *cpcm)
726 struct hdac_bus *bus = &_bus->core;
727 struct azx *chip = bus_to_azx(bus);
729 struct azx_pcm *apcm;
730 int pcm_dev = cpcm->device;
734 list_for_each_entry(apcm, &chip->pcm_list, list) {
735 if (apcm->pcm->device == pcm_dev) {
736 dev_err(chip->card->dev, "PCM %d already exists\n",
741 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
742 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
743 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
747 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
748 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
750 snd_device_free(chip->card, pcm);
757 pcm->private_data = apcm;
758 pcm->private_free = azx_pcm_free;
759 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
760 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
761 list_add_tail(&apcm->list, &chip->pcm_list);
763 for (s = 0; s < 2; s++) {
764 if (cpcm->stream[s].substreams)
765 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
767 /* buffer pre-allocation */
768 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
769 if (size > MAX_PREALLOC_SIZE)
770 size = MAX_PREALLOC_SIZE;
771 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
773 size, MAX_PREALLOC_SIZE);
777 static unsigned int azx_command_addr(u32 cmd)
779 unsigned int addr = cmd >> 28;
781 if (addr >= AZX_MAX_CODECS) {
789 /* receive a response */
790 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
793 struct azx *chip = bus_to_azx(bus);
794 struct hda_bus *hbus = &chip->bus;
795 unsigned long timeout;
796 unsigned long loopcounter;
800 timeout = jiffies + msecs_to_jiffies(1000);
802 for (loopcounter = 0;; loopcounter++) {
803 spin_lock_irq(&bus->reg_lock);
804 if (chip->polling_mode || do_poll)
805 snd_hdac_bus_update_rirb(bus);
806 if (!bus->rirb.cmds[addr]) {
808 chip->poll_count = 0;
810 *res = bus->rirb.res[addr]; /* the last value */
811 spin_unlock_irq(&bus->reg_lock);
814 spin_unlock_irq(&bus->reg_lock);
815 if (time_after(jiffies, timeout))
817 if (hbus->needs_damn_long_delay || loopcounter > 3000)
818 msleep(2); /* temporary workaround */
825 if (hbus->no_response_fallback)
828 if (!chip->polling_mode && chip->poll_count < 2) {
829 dev_dbg(chip->card->dev,
830 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
831 bus->last_cmd[addr]);
838 if (!chip->polling_mode) {
839 dev_warn(chip->card->dev,
840 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
841 bus->last_cmd[addr]);
842 chip->polling_mode = 1;
847 dev_warn(chip->card->dev,
848 "No response from codec, disabling MSI: last cmd=0x%08x\n",
849 bus->last_cmd[addr]);
850 if (chip->ops->disable_msi_reset_irq &&
851 chip->ops->disable_msi_reset_irq(chip) < 0)
857 /* If this critical timeout happens during the codec probing
858 * phase, this is likely an access to a non-existing codec
859 * slot. Better to return an error and reset the system.
864 /* no fallback mechanism? */
865 if (!chip->fallback_to_single_cmd)
868 /* a fatal communication error; need either to reset or to fallback
869 * to the single_cmd mode
871 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
872 hbus->response_reset = 1;
873 dev_err(chip->card->dev,
874 "No response from codec, resetting bus: last cmd=0x%08x\n",
875 bus->last_cmd[addr]);
876 return -EAGAIN; /* give a chance to retry */
879 dev_err(chip->card->dev,
880 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
881 bus->last_cmd[addr]);
882 chip->single_cmd = 1;
883 hbus->response_reset = 0;
884 snd_hdac_bus_stop_cmd_io(bus);
889 * Use the single immediate command instead of CORB/RIRB for simplicity
891 * Note: according to Intel, this is not preferred use. The command was
892 * intended for the BIOS only, and may get confused with unsolicited
893 * responses. So, we shouldn't use it for normal operation from the
895 * I left the codes, however, for debugging/testing purposes.
898 /* receive a response */
899 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
904 /* check IRV busy bit */
905 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
906 /* reuse rirb.res as the response return value */
907 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
912 if (printk_ratelimit())
913 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
914 azx_readw(chip, IRS));
915 azx_bus(chip)->rirb.res[addr] = -1;
920 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
922 struct azx *chip = bus_to_azx(bus);
923 unsigned int addr = azx_command_addr(val);
926 bus->last_cmd[azx_command_addr(val)] = val;
928 /* check ICB busy bit */
929 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
930 /* Clear IRV valid bit */
931 azx_writew(chip, IRS, azx_readw(chip, IRS) |
933 azx_writel(chip, IC, val);
934 azx_writew(chip, IRS, azx_readw(chip, IRS) |
936 return azx_single_wait_for_response(chip, addr);
940 if (printk_ratelimit())
941 dev_dbg(chip->card->dev,
942 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
943 azx_readw(chip, IRS), val);
947 /* receive a response */
948 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
952 *res = bus->rirb.res[addr];
957 * The below are the main callbacks from hda_codec.
959 * They are just the skeleton to call sub-callbacks according to the
960 * current setting of chip->single_cmd.
964 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
966 struct azx *chip = bus_to_azx(bus);
970 if (chip->single_cmd)
971 return azx_single_send_cmd(bus, val);
973 return snd_hdac_bus_send_cmd(bus, val);
977 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
980 struct azx *chip = bus_to_azx(bus);
984 if (chip->single_cmd)
985 return azx_single_get_response(bus, addr, res);
987 return azx_rirb_get_response(bus, addr, res);
990 static int azx_link_power(struct hdac_bus *bus, bool enable)
992 struct azx *chip = bus_to_azx(bus);
994 if (chip->ops->link_power)
995 return chip->ops->link_power(chip, enable);
1000 static const struct hdac_bus_ops bus_core_ops = {
1001 .command = azx_send_cmd,
1002 .get_response = azx_get_response,
1003 .link_power = azx_link_power,
1006 #ifdef CONFIG_SND_HDA_DSP_LOADER
1008 * DSP loading code (e.g. for CA0132)
1011 /* use the first stream for loading DSP */
1012 static struct azx_dev *
1013 azx_get_dsp_loader_dev(struct azx *chip)
1015 struct hdac_bus *bus = azx_bus(chip);
1016 struct hdac_stream *s;
1018 list_for_each_entry(s, &bus->stream_list, list)
1019 if (s->index == chip->playback_index_offset)
1020 return stream_to_azx_dev(s);
1025 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1026 unsigned int byte_size,
1027 struct snd_dma_buffer *bufp)
1029 struct hdac_bus *bus = &codec->bus->core;
1030 struct azx *chip = bus_to_azx(bus);
1031 struct azx_dev *azx_dev;
1032 struct hdac_stream *hstr;
1036 azx_dev = azx_get_dsp_loader_dev(chip);
1037 hstr = azx_stream(azx_dev);
1038 spin_lock_irq(&bus->reg_lock);
1040 chip->saved_azx_dev = *azx_dev;
1043 spin_unlock_irq(&bus->reg_lock);
1045 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
1047 spin_lock_irq(&bus->reg_lock);
1049 *azx_dev = chip->saved_azx_dev;
1050 spin_unlock_irq(&bus->reg_lock);
1057 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
1059 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1061 struct hdac_bus *bus = &codec->bus->core;
1062 struct azx *chip = bus_to_azx(bus);
1063 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1065 snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
1067 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
1069 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1070 struct snd_dma_buffer *dmab)
1072 struct hdac_bus *bus = &codec->bus->core;
1073 struct azx *chip = bus_to_azx(bus);
1074 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1075 struct hdac_stream *hstr = azx_stream(azx_dev);
1077 if (!dmab->area || !hstr->locked)
1080 snd_hdac_dsp_cleanup(hstr, dmab);
1081 spin_lock_irq(&bus->reg_lock);
1083 *azx_dev = chip->saved_azx_dev;
1084 hstr->locked = false;
1085 spin_unlock_irq(&bus->reg_lock);
1087 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1088 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1091 * reset and start the controller registers
1093 void azx_init_chip(struct azx *chip, bool full_reset)
1095 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1096 /* correct RINTCNT for CXT */
1097 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1098 azx_writew(chip, RINTCNT, 0xc0);
1101 EXPORT_SYMBOL_GPL(azx_init_chip);
1103 void azx_stop_all_streams(struct azx *chip)
1105 struct hdac_bus *bus = azx_bus(chip);
1106 struct hdac_stream *s;
1108 list_for_each_entry(s, &bus->stream_list, list)
1109 snd_hdac_stream_stop(s);
1111 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1113 void azx_stop_chip(struct azx *chip)
1115 snd_hdac_bus_stop_chip(azx_bus(chip));
1117 EXPORT_SYMBOL_GPL(azx_stop_chip);
1122 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1124 struct azx *chip = bus_to_azx(bus);
1125 struct azx_dev *azx_dev = stream_to_azx_dev(s);
1127 /* check whether this IRQ is really acceptable */
1128 if (!chip->ops->position_check ||
1129 chip->ops->position_check(chip, azx_dev)) {
1130 spin_unlock(&bus->reg_lock);
1131 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1132 spin_lock(&bus->reg_lock);
1136 irqreturn_t azx_interrupt(int irq, void *dev_id)
1138 struct azx *chip = dev_id;
1139 struct hdac_bus *bus = azx_bus(chip);
1141 bool active, handled = false;
1142 int repeat = 0; /* count for avoiding endless loop */
1145 if (azx_has_pm_runtime(chip))
1146 if (!pm_runtime_active(chip->card->dev))
1150 spin_lock(&bus->reg_lock);
1156 status = azx_readl(chip, INTSTS);
1157 if (status == 0 || status == 0xffffffff)
1162 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1165 status = azx_readb(chip, RIRBSTS);
1166 if (status & RIRB_INT_MASK) {
1168 * Clearing the interrupt status here ensures that no
1169 * interrupt gets masked after the RIRB wp is read in
1170 * snd_hdac_bus_update_rirb. This avoids a possible
1171 * race condition where codec response in RIRB may
1172 * remain unserviced by IRQ, eventually falling back
1173 * to polling mode in azx_rirb_get_response.
1175 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1177 if (status & RIRB_INT_RESPONSE) {
1178 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1180 snd_hdac_bus_update_rirb(bus);
1183 } while (active && ++repeat < 10);
1186 spin_unlock(&bus->reg_lock);
1188 return IRQ_RETVAL(handled);
1190 EXPORT_SYMBOL_GPL(azx_interrupt);
1197 * Probe the given codec address
1199 static int probe_codec(struct azx *chip, int addr)
1201 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1202 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1203 struct hdac_bus *bus = azx_bus(chip);
1205 unsigned int res = -1;
1207 mutex_lock(&bus->cmd_mutex);
1209 azx_send_cmd(bus, cmd);
1210 err = azx_get_response(bus, addr, &res);
1212 mutex_unlock(&bus->cmd_mutex);
1213 if (err < 0 || res == -1)
1215 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1219 void snd_hda_bus_reset(struct hda_bus *bus)
1221 struct azx *chip = bus_to_azx(&bus->core);
1224 azx_stop_chip(chip);
1225 azx_init_chip(chip, true);
1226 if (bus->core.chip_init)
1227 snd_hda_bus_reset_codecs(bus);
1231 static int get_jackpoll_interval(struct azx *chip)
1236 if (!chip->jackpoll_ms)
1239 i = chip->jackpoll_ms[chip->dev_index];
1242 if (i < 50 || i > 60000)
1245 j = msecs_to_jiffies(i);
1247 dev_warn(chip->card->dev,
1248 "jackpoll_ms value out of range: %d\n", i);
1252 /* HD-audio bus initialization */
1253 int azx_bus_init(struct azx *chip, const char *model,
1254 const struct hdac_io_ops *io_ops)
1256 struct hda_bus *bus = &chip->bus;
1259 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
1264 bus->card = chip->card;
1265 mutex_init(&bus->prepare_mutex);
1266 bus->pci = chip->pci;
1267 bus->modelname = model;
1268 bus->mixer_assigned = -1;
1269 bus->core.snoop = azx_snoop(chip);
1270 if (chip->get_position[0] != azx_get_pos_lpib ||
1271 chip->get_position[1] != azx_get_pos_lpib)
1272 bus->core.use_posbuf = true;
1273 bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1274 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1275 bus->core.corbrp_self_clear = true;
1277 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1278 bus->core.align_bdle_4k = true;
1280 /* AMD chipsets often cause the communication stalls upon certain
1281 * sequence like the pin-detection. It seems that forcing the synced
1282 * access works around the stall. Grrr...
1284 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1285 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1286 bus->core.sync_write = 1;
1287 bus->allow_bus_reset = 1;
1292 EXPORT_SYMBOL_GPL(azx_bus_init);
1295 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1297 struct hdac_bus *bus = azx_bus(chip);
1302 max_slots = AZX_DEFAULT_CODECS;
1304 /* First try to probe all given codec slots */
1305 for (c = 0; c < max_slots; c++) {
1306 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1307 if (probe_codec(chip, c) < 0) {
1308 /* Some BIOSen give you wrong codec addresses
1311 dev_warn(chip->card->dev,
1312 "Codec #%d probe error; disabling it...\n", c);
1313 bus->codec_mask &= ~(1 << c);
1314 /* More badly, accessing to a non-existing
1315 * codec often screws up the controller chip,
1316 * and disturbs the further communications.
1317 * Thus if an error occurs during probing,
1318 * better to reset the controller chip to
1319 * get back to the sanity state.
1321 azx_stop_chip(chip);
1322 azx_init_chip(chip, true);
1327 /* Then create codec instances */
1328 for (c = 0; c < max_slots; c++) {
1329 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1330 struct hda_codec *codec;
1331 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1334 codec->jackpoll_interval = get_jackpoll_interval(chip);
1335 codec->beep_mode = chip->beep_mode;
1340 dev_err(chip->card->dev, "no codecs initialized\n");
1345 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1347 /* configure each codec instance */
1348 int azx_codec_configure(struct azx *chip)
1350 struct hda_codec *codec, *next;
1352 /* use _safe version here since snd_hda_codec_configure() deregisters
1353 * the device upon error and deletes itself from the bus list.
1355 list_for_each_codec_safe(codec, next, &chip->bus) {
1356 snd_hda_codec_configure(codec);
1359 if (!azx_bus(chip)->num_codecs)
1363 EXPORT_SYMBOL_GPL(azx_codec_configure);
1365 static int stream_direction(struct azx *chip, unsigned char index)
1367 if (index >= chip->capture_index_offset &&
1368 index < chip->capture_index_offset + chip->capture_streams)
1369 return SNDRV_PCM_STREAM_CAPTURE;
1370 return SNDRV_PCM_STREAM_PLAYBACK;
1373 /* initialize SD streams */
1374 int azx_init_streams(struct azx *chip)
1377 int stream_tags[2] = { 0, 0 };
1379 /* initialize each stream (aka device)
1380 * assign the starting bdl address to each stream (device)
1383 for (i = 0; i < chip->num_streams; i++) {
1384 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1390 dir = stream_direction(chip, i);
1391 /* stream tag must be unique throughout
1392 * the stream direction group,
1393 * valid values 1...15
1394 * use separate stream tag if the flag
1395 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1397 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1398 tag = ++stream_tags[dir];
1401 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1407 EXPORT_SYMBOL_GPL(azx_init_streams);
1409 void azx_free_streams(struct azx *chip)
1411 struct hdac_bus *bus = azx_bus(chip);
1412 struct hdac_stream *s;
1414 while (!list_empty(&bus->stream_list)) {
1415 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1417 kfree(stream_to_azx_dev(s));
1420 EXPORT_SYMBOL_GPL(azx_free_streams);