3 * Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 #include <linux/clocksource.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <sound/core.h>
31 #include <sound/initval.h>
32 #include "hda_controller.h"
34 #define CREATE_TRACE_POINTS
35 #include "hda_controller_trace.h"
37 /* DSP lock helpers */
38 #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
39 #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
40 #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
42 /* assign a stream for the PCM */
43 static inline struct azx_dev *
44 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
46 struct hdac_stream *s;
48 s = snd_hdac_stream_assign(azx_bus(chip), substream);
51 return stream_to_azx_dev(s);
54 /* release the assigned stream */
55 static inline void azx_release_device(struct azx_dev *azx_dev)
57 snd_hdac_stream_release(azx_stream(azx_dev));
60 static inline struct hda_pcm_stream *
61 to_hda_pcm_stream(struct snd_pcm_substream *substream)
63 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
64 return &apcm->info->stream[substream->stream];
67 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
70 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
71 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
72 u64 codec_frames, codec_nsecs;
74 if (!hinfo->ops.get_delay)
77 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
78 codec_nsecs = div_u64(codec_frames * 1000000000LL,
79 substream->runtime->rate);
81 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
82 return nsec + codec_nsecs;
84 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
91 static int azx_pcm_close(struct snd_pcm_substream *substream)
93 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
94 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
95 struct azx *chip = apcm->chip;
96 struct azx_dev *azx_dev = get_azx_dev(substream);
98 trace_azx_pcm_close(chip, azx_dev);
99 mutex_lock(&chip->open_mutex);
100 azx_release_device(azx_dev);
101 if (hinfo->ops.close)
102 hinfo->ops.close(hinfo, apcm->codec, substream);
103 snd_hda_power_down(apcm->codec);
104 mutex_unlock(&chip->open_mutex);
105 snd_hda_codec_pcm_put(apcm->info);
109 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
110 struct snd_pcm_hw_params *hw_params)
112 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
113 struct azx *chip = apcm->chip;
114 struct azx_dev *azx_dev = get_azx_dev(substream);
117 trace_azx_pcm_hw_params(chip, azx_dev);
119 if (dsp_is_locked(azx_dev)) {
124 azx_dev->core.bufsize = 0;
125 azx_dev->core.period_bytes = 0;
126 azx_dev->core.format_val = 0;
127 ret = chip->ops->substream_alloc_pages(chip, substream,
128 params_buffer_bytes(hw_params));
134 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
136 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
137 struct azx_dev *azx_dev = get_azx_dev(substream);
138 struct azx *chip = apcm->chip;
139 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
142 /* reset BDL address */
144 if (!dsp_is_locked(azx_dev))
145 snd_hdac_stream_cleanup(azx_stream(azx_dev));
147 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
149 err = chip->ops->substream_free_pages(chip, substream);
150 azx_stream(azx_dev)->prepared = 0;
155 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
157 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
158 struct azx *chip = apcm->chip;
159 struct azx_dev *azx_dev = get_azx_dev(substream);
160 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
161 struct snd_pcm_runtime *runtime = substream->runtime;
162 unsigned int format_val, stream_tag;
164 struct hda_spdif_out *spdif =
165 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
166 unsigned short ctls = spdif ? spdif->ctls : 0;
168 trace_azx_pcm_prepare(chip, azx_dev);
170 if (dsp_is_locked(azx_dev)) {
175 snd_hdac_stream_reset(azx_stream(azx_dev));
176 format_val = snd_hdac_calc_stream_format(runtime->rate,
182 dev_err(chip->card->dev,
183 "invalid format_val, rate=%d, ch=%d, format=%d\n",
184 runtime->rate, runtime->channels, runtime->format);
189 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
193 snd_hdac_stream_setup(azx_stream(azx_dev));
195 stream_tag = azx_dev->core.stream_tag;
196 /* CA-IBG chips need the playback stream starting from 1 */
197 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
198 stream_tag > chip->capture_streams)
199 stream_tag -= chip->capture_streams;
200 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
201 azx_dev->core.format_val, substream);
205 azx_stream(azx_dev)->prepared = 1;
210 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
212 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
213 struct azx *chip = apcm->chip;
214 struct hdac_bus *bus = azx_bus(chip);
215 struct azx_dev *azx_dev;
216 struct snd_pcm_substream *s;
217 struct hdac_stream *hstr;
222 azx_dev = get_azx_dev(substream);
223 trace_azx_pcm_trigger(chip, azx_dev, cmd);
225 hstr = azx_stream(azx_dev);
226 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
227 sync_reg = AZX_REG_OLD_SSYNC;
229 sync_reg = AZX_REG_SSYNC;
231 if (dsp_is_locked(azx_dev) || !hstr->prepared)
235 case SNDRV_PCM_TRIGGER_START:
236 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
237 case SNDRV_PCM_TRIGGER_RESUME:
240 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
241 case SNDRV_PCM_TRIGGER_SUSPEND:
242 case SNDRV_PCM_TRIGGER_STOP:
249 snd_pcm_group_for_each_entry(s, substream) {
250 if (s->pcm->card != substream->pcm->card)
252 azx_dev = get_azx_dev(s);
253 sbits |= 1 << azx_dev->core.index;
254 snd_pcm_trigger_done(s, substream);
257 spin_lock(&bus->reg_lock);
259 /* first, set SYNC bits of corresponding streams */
260 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
262 snd_pcm_group_for_each_entry(s, substream) {
263 if (s->pcm->card != substream->pcm->card)
265 azx_dev = get_azx_dev(s);
267 azx_dev->insufficient = 1;
268 snd_hdac_stream_start(azx_stream(azx_dev), true);
270 snd_hdac_stream_stop(azx_stream(azx_dev));
273 spin_unlock(&bus->reg_lock);
275 snd_hdac_stream_sync(hstr, start, sbits);
277 spin_lock(&bus->reg_lock);
278 /* reset SYNC bits */
279 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
281 snd_hdac_stream_timecounter_init(hstr, sbits);
282 spin_unlock(&bus->reg_lock);
286 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
288 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
290 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
292 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
294 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
296 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
298 unsigned int azx_get_position(struct azx *chip,
299 struct azx_dev *azx_dev)
301 struct snd_pcm_substream *substream = azx_dev->core.substream;
303 int stream = substream->stream;
306 if (chip->get_position[stream])
307 pos = chip->get_position[stream](chip, azx_dev);
308 else /* use the position buffer as default */
309 pos = azx_get_pos_posbuf(chip, azx_dev);
311 if (pos >= azx_dev->core.bufsize)
314 if (substream->runtime) {
315 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
316 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
318 if (chip->get_delay[stream])
319 delay += chip->get_delay[stream](chip, azx_dev, pos);
320 if (hinfo->ops.get_delay)
321 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
323 substream->runtime->delay = delay;
326 trace_azx_get_position(chip, azx_dev, pos, delay);
329 EXPORT_SYMBOL_GPL(azx_get_position);
331 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
333 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
334 struct azx *chip = apcm->chip;
335 struct azx_dev *azx_dev = get_azx_dev(substream);
336 return bytes_to_frames(substream->runtime,
337 azx_get_position(chip, azx_dev));
340 static int azx_get_time_info(struct snd_pcm_substream *substream,
341 struct timespec *system_ts, struct timespec *audio_ts,
342 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
343 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
345 struct azx_dev *azx_dev = get_azx_dev(substream);
348 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
349 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
351 snd_pcm_gettime(substream->runtime, system_ts);
353 nsec = timecounter_read(&azx_dev->core.tc);
354 nsec = div_u64(nsec, 3); /* can be optimized */
355 if (audio_tstamp_config->report_delay)
356 nsec = azx_adjust_codec_delay(substream, nsec);
358 *audio_ts = ns_to_timespec(nsec);
360 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
361 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
362 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
365 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
370 static struct snd_pcm_hardware azx_pcm_hw = {
371 .info = (SNDRV_PCM_INFO_MMAP |
372 SNDRV_PCM_INFO_INTERLEAVED |
373 SNDRV_PCM_INFO_BLOCK_TRANSFER |
374 SNDRV_PCM_INFO_MMAP_VALID |
375 /* No full-resume yet implemented */
376 /* SNDRV_PCM_INFO_RESUME |*/
377 SNDRV_PCM_INFO_PAUSE |
378 SNDRV_PCM_INFO_SYNC_START |
379 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
380 SNDRV_PCM_INFO_HAS_LINK_ATIME |
381 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
382 .formats = SNDRV_PCM_FMTBIT_S16_LE,
383 .rates = SNDRV_PCM_RATE_48000,
388 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
389 .period_bytes_min = 128,
390 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
392 .periods_max = AZX_MAX_FRAG,
396 static int azx_pcm_open(struct snd_pcm_substream *substream)
398 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
399 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
400 struct azx *chip = apcm->chip;
401 struct azx_dev *azx_dev;
402 struct snd_pcm_runtime *runtime = substream->runtime;
406 snd_hda_codec_pcm_get(apcm->info);
407 mutex_lock(&chip->open_mutex);
408 azx_dev = azx_assign_device(chip, substream);
409 trace_azx_pcm_open(chip, azx_dev);
410 if (azx_dev == NULL) {
414 runtime->private_data = azx_dev;
415 runtime->hw = azx_pcm_hw;
416 runtime->hw.channels_min = hinfo->channels_min;
417 runtime->hw.channels_max = hinfo->channels_max;
418 runtime->hw.formats = hinfo->formats;
419 runtime->hw.rates = hinfo->rates;
420 snd_pcm_limit_hw_rates(runtime);
421 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
423 /* avoid wrap-around with wall-clock */
424 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
428 if (chip->align_buffer_size)
429 /* constrain buffer sizes to be multiple of 128
430 bytes. This is more efficient in terms of memory
431 access but isn't required by the HDA spec and
432 prevents users from specifying exact period/buffer
433 sizes. For example for 44.1kHz, a period size set
434 to 20ms will be rounded to 19.59ms. */
437 /* Don't enforce steps on buffer sizes, still need to
438 be multiple of 4 bytes (HDA spec). Tested on Intel
439 HDA controllers, may not work on all devices where
440 option needs to be disabled */
443 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
445 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
447 snd_hda_power_up(apcm->codec);
449 err = hinfo->ops.open(hinfo, apcm->codec, substream);
453 azx_release_device(azx_dev);
456 snd_pcm_limit_hw_rates(runtime);
458 if (snd_BUG_ON(!runtime->hw.channels_min) ||
459 snd_BUG_ON(!runtime->hw.channels_max) ||
460 snd_BUG_ON(!runtime->hw.formats) ||
461 snd_BUG_ON(!runtime->hw.rates)) {
462 azx_release_device(azx_dev);
463 if (hinfo->ops.close)
464 hinfo->ops.close(hinfo, apcm->codec, substream);
469 /* disable LINK_ATIME timestamps for capture streams
470 until we figure out how to handle digital inputs */
471 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
472 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
473 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
476 snd_pcm_set_sync(substream);
477 mutex_unlock(&chip->open_mutex);
481 snd_hda_power_down(apcm->codec);
483 mutex_unlock(&chip->open_mutex);
484 snd_hda_codec_pcm_put(apcm->info);
488 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
489 struct vm_area_struct *area)
491 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
492 struct azx *chip = apcm->chip;
493 if (chip->ops->pcm_mmap_prepare)
494 chip->ops->pcm_mmap_prepare(substream, area);
495 return snd_pcm_lib_default_mmap(substream, area);
498 static struct snd_pcm_ops azx_pcm_ops = {
499 .open = azx_pcm_open,
500 .close = azx_pcm_close,
501 .ioctl = snd_pcm_lib_ioctl,
502 .hw_params = azx_pcm_hw_params,
503 .hw_free = azx_pcm_hw_free,
504 .prepare = azx_pcm_prepare,
505 .trigger = azx_pcm_trigger,
506 .pointer = azx_pcm_pointer,
507 .get_time_info = azx_get_time_info,
508 .mmap = azx_pcm_mmap,
509 .page = snd_pcm_sgbuf_ops_page,
512 static void azx_pcm_free(struct snd_pcm *pcm)
514 struct azx_pcm *apcm = pcm->private_data;
516 list_del(&apcm->list);
517 apcm->info->pcm = NULL;
522 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
524 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
525 struct hda_pcm *cpcm)
527 struct hdac_bus *bus = &_bus->core;
528 struct azx *chip = bus_to_azx(bus);
530 struct azx_pcm *apcm;
531 int pcm_dev = cpcm->device;
535 list_for_each_entry(apcm, &chip->pcm_list, list) {
536 if (apcm->pcm->device == pcm_dev) {
537 dev_err(chip->card->dev, "PCM %d already exists\n",
542 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
543 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
544 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
548 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
549 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
551 snd_device_free(chip->card, pcm);
558 pcm->private_data = apcm;
559 pcm->private_free = azx_pcm_free;
560 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
561 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
562 list_add_tail(&apcm->list, &chip->pcm_list);
564 for (s = 0; s < 2; s++) {
565 if (cpcm->stream[s].substreams)
566 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
568 /* buffer pre-allocation */
569 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
570 if (size > MAX_PREALLOC_SIZE)
571 size = MAX_PREALLOC_SIZE;
572 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
574 size, MAX_PREALLOC_SIZE);
578 static unsigned int azx_command_addr(u32 cmd)
580 unsigned int addr = cmd >> 28;
582 if (addr >= AZX_MAX_CODECS) {
590 /* receive a response */
591 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
594 struct azx *chip = bus_to_azx(bus);
595 struct hda_bus *hbus = &chip->bus;
596 unsigned long timeout;
597 unsigned long loopcounter;
601 timeout = jiffies + msecs_to_jiffies(1000);
603 for (loopcounter = 0;; loopcounter++) {
604 spin_lock_irq(&bus->reg_lock);
605 if (chip->polling_mode || do_poll)
606 snd_hdac_bus_update_rirb(bus);
607 if (!bus->rirb.cmds[addr]) {
609 chip->poll_count = 0;
611 *res = bus->rirb.res[addr]; /* the last value */
612 spin_unlock_irq(&bus->reg_lock);
615 spin_unlock_irq(&bus->reg_lock);
616 if (time_after(jiffies, timeout))
618 if (hbus->needs_damn_long_delay || loopcounter > 3000)
619 msleep(2); /* temporary workaround */
626 if (hbus->no_response_fallback)
629 if (!chip->polling_mode && chip->poll_count < 2) {
630 dev_dbg(chip->card->dev,
631 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
632 bus->last_cmd[addr]);
639 if (!chip->polling_mode) {
640 dev_warn(chip->card->dev,
641 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
642 bus->last_cmd[addr]);
643 chip->polling_mode = 1;
648 dev_warn(chip->card->dev,
649 "No response from codec, disabling MSI: last cmd=0x%08x\n",
650 bus->last_cmd[addr]);
651 if (chip->ops->disable_msi_reset_irq &&
652 chip->ops->disable_msi_reset_irq(chip) < 0)
658 /* If this critical timeout happens during the codec probing
659 * phase, this is likely an access to a non-existing codec
660 * slot. Better to return an error and reset the system.
665 /* a fatal communication error; need either to reset or to fallback
666 * to the single_cmd mode
668 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
669 hbus->response_reset = 1;
670 dev_err(chip->card->dev,
671 "No response from codec, resetting bus: last cmd=0x%08x\n",
672 bus->last_cmd[addr]);
673 return -EAGAIN; /* give a chance to retry */
676 dev_err(chip->card->dev,
677 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
678 bus->last_cmd[addr]);
679 chip->single_cmd = 1;
680 hbus->response_reset = 0;
681 snd_hdac_bus_stop_cmd_io(bus);
686 * Use the single immediate command instead of CORB/RIRB for simplicity
688 * Note: according to Intel, this is not preferred use. The command was
689 * intended for the BIOS only, and may get confused with unsolicited
690 * responses. So, we shouldn't use it for normal operation from the
692 * I left the codes, however, for debugging/testing purposes.
695 /* receive a response */
696 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
701 /* check IRV busy bit */
702 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
703 /* reuse rirb.res as the response return value */
704 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
709 if (printk_ratelimit())
710 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
711 azx_readw(chip, IRS));
712 azx_bus(chip)->rirb.res[addr] = -1;
717 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
719 struct azx *chip = bus_to_azx(bus);
720 unsigned int addr = azx_command_addr(val);
723 bus->last_cmd[azx_command_addr(val)] = val;
725 /* check ICB busy bit */
726 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
727 /* Clear IRV valid bit */
728 azx_writew(chip, IRS, azx_readw(chip, IRS) |
730 azx_writel(chip, IC, val);
731 azx_writew(chip, IRS, azx_readw(chip, IRS) |
733 return azx_single_wait_for_response(chip, addr);
737 if (printk_ratelimit())
738 dev_dbg(chip->card->dev,
739 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
740 azx_readw(chip, IRS), val);
744 /* receive a response */
745 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
749 *res = bus->rirb.res[addr];
754 * The below are the main callbacks from hda_codec.
756 * They are just the skeleton to call sub-callbacks according to the
757 * current setting of chip->single_cmd.
761 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
763 struct azx *chip = bus_to_azx(bus);
767 if (chip->single_cmd)
768 return azx_single_send_cmd(bus, val);
770 return snd_hdac_bus_send_cmd(bus, val);
774 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
777 struct azx *chip = bus_to_azx(bus);
781 if (chip->single_cmd)
782 return azx_single_get_response(bus, addr, res);
784 return azx_rirb_get_response(bus, addr, res);
787 static int azx_link_power(struct hdac_bus *bus, bool enable)
789 struct azx *chip = bus_to_azx(bus);
791 if (chip->ops->link_power)
792 return chip->ops->link_power(chip, enable);
797 static const struct hdac_bus_ops bus_core_ops = {
798 .command = azx_send_cmd,
799 .get_response = azx_get_response,
800 .link_power = azx_link_power,
803 #ifdef CONFIG_SND_HDA_DSP_LOADER
805 * DSP loading code (e.g. for CA0132)
808 /* use the first stream for loading DSP */
809 static struct azx_dev *
810 azx_get_dsp_loader_dev(struct azx *chip)
812 struct hdac_bus *bus = azx_bus(chip);
813 struct hdac_stream *s;
815 list_for_each_entry(s, &bus->stream_list, list)
816 if (s->index == chip->playback_index_offset)
817 return stream_to_azx_dev(s);
822 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
823 unsigned int byte_size,
824 struct snd_dma_buffer *bufp)
826 struct hdac_bus *bus = &codec->bus->core;
827 struct azx *chip = bus_to_azx(bus);
828 struct azx_dev *azx_dev;
829 struct hdac_stream *hstr;
833 azx_dev = azx_get_dsp_loader_dev(chip);
834 hstr = azx_stream(azx_dev);
835 spin_lock_irq(&bus->reg_lock);
837 chip->saved_azx_dev = *azx_dev;
840 spin_unlock_irq(&bus->reg_lock);
842 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
844 spin_lock_irq(&bus->reg_lock);
846 *azx_dev = chip->saved_azx_dev;
847 spin_unlock_irq(&bus->reg_lock);
854 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
856 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
858 struct hdac_bus *bus = &codec->bus->core;
859 struct azx *chip = bus_to_azx(bus);
860 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
862 snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
864 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
866 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
867 struct snd_dma_buffer *dmab)
869 struct hdac_bus *bus = &codec->bus->core;
870 struct azx *chip = bus_to_azx(bus);
871 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
872 struct hdac_stream *hstr = azx_stream(azx_dev);
874 if (!dmab->area || !hstr->locked)
877 snd_hdac_dsp_cleanup(hstr, dmab);
878 spin_lock_irq(&bus->reg_lock);
880 *azx_dev = chip->saved_azx_dev;
881 hstr->locked = false;
882 spin_unlock_irq(&bus->reg_lock);
884 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
885 #endif /* CONFIG_SND_HDA_DSP_LOADER */
888 * reset and start the controller registers
890 void azx_init_chip(struct azx *chip, bool full_reset)
892 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
893 /* correct RINTCNT for CXT */
894 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
895 azx_writew(chip, RINTCNT, 0xc0);
898 EXPORT_SYMBOL_GPL(azx_init_chip);
900 void azx_stop_all_streams(struct azx *chip)
902 struct hdac_bus *bus = azx_bus(chip);
903 struct hdac_stream *s;
905 list_for_each_entry(s, &bus->stream_list, list)
906 snd_hdac_stream_stop(s);
908 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
910 void azx_stop_chip(struct azx *chip)
912 snd_hdac_bus_stop_chip(azx_bus(chip));
914 EXPORT_SYMBOL_GPL(azx_stop_chip);
919 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
921 struct azx *chip = bus_to_azx(bus);
922 struct azx_dev *azx_dev = stream_to_azx_dev(s);
924 /* check whether this IRQ is really acceptable */
925 if (!chip->ops->position_check ||
926 chip->ops->position_check(chip, azx_dev)) {
927 spin_unlock(&bus->reg_lock);
928 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
929 spin_lock(&bus->reg_lock);
933 irqreturn_t azx_interrupt(int irq, void *dev_id)
935 struct azx *chip = dev_id;
936 struct hdac_bus *bus = azx_bus(chip);
940 if (azx_has_pm_runtime(chip))
941 if (!pm_runtime_active(chip->card->dev))
945 spin_lock(&bus->reg_lock);
947 if (chip->disabled) {
948 spin_unlock(&bus->reg_lock);
952 status = azx_readl(chip, INTSTS);
953 if (status == 0 || status == 0xffffffff) {
954 spin_unlock(&bus->reg_lock);
958 snd_hdac_bus_handle_stream_irq(bus, status, stream_update);
961 status = azx_readb(chip, RIRBSTS);
962 if (status & RIRB_INT_MASK) {
963 if (status & RIRB_INT_RESPONSE) {
964 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
966 snd_hdac_bus_update_rirb(bus);
968 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
971 spin_unlock(&bus->reg_lock);
975 EXPORT_SYMBOL_GPL(azx_interrupt);
982 * Probe the given codec address
984 static int probe_codec(struct azx *chip, int addr)
986 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
987 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
988 struct hdac_bus *bus = azx_bus(chip);
990 unsigned int res = -1;
992 mutex_lock(&bus->cmd_mutex);
994 azx_send_cmd(bus, cmd);
995 err = azx_get_response(bus, addr, &res);
997 mutex_unlock(&bus->cmd_mutex);
998 if (err < 0 || res == -1)
1000 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1004 void snd_hda_bus_reset(struct hda_bus *bus)
1006 struct azx *chip = bus_to_azx(&bus->core);
1009 azx_stop_chip(chip);
1010 azx_init_chip(chip, true);
1011 if (bus->core.chip_init)
1012 snd_hda_bus_reset_codecs(bus);
1016 static int get_jackpoll_interval(struct azx *chip)
1021 if (!chip->jackpoll_ms)
1024 i = chip->jackpoll_ms[chip->dev_index];
1027 if (i < 50 || i > 60000)
1030 j = msecs_to_jiffies(i);
1032 dev_warn(chip->card->dev,
1033 "jackpoll_ms value out of range: %d\n", i);
1037 /* HD-audio bus initialization */
1038 int azx_bus_init(struct azx *chip, const char *model,
1039 const struct hdac_io_ops *io_ops)
1041 struct hda_bus *bus = &chip->bus;
1044 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
1049 bus->card = chip->card;
1050 mutex_init(&bus->prepare_mutex);
1051 bus->pci = chip->pci;
1052 bus->modelname = model;
1053 bus->mixer_assigned = -1;
1054 bus->core.snoop = azx_snoop(chip);
1055 if (chip->get_position[0] != azx_get_pos_lpib ||
1056 chip->get_position[1] != azx_get_pos_lpib)
1057 bus->core.use_posbuf = true;
1058 if (chip->bdl_pos_adj)
1059 bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index];
1060 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1061 bus->core.corbrp_self_clear = true;
1063 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1064 bus->core.align_bdle_4k = true;
1066 /* AMD chipsets often cause the communication stalls upon certain
1067 * sequence like the pin-detection. It seems that forcing the synced
1068 * access works around the stall. Grrr...
1070 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1071 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1072 bus->core.sync_write = 1;
1073 bus->allow_bus_reset = 1;
1078 EXPORT_SYMBOL_GPL(azx_bus_init);
1081 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1083 struct hdac_bus *bus = azx_bus(chip);
1088 max_slots = AZX_DEFAULT_CODECS;
1090 /* First try to probe all given codec slots */
1091 for (c = 0; c < max_slots; c++) {
1092 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1093 if (probe_codec(chip, c) < 0) {
1094 /* Some BIOSen give you wrong codec addresses
1097 dev_warn(chip->card->dev,
1098 "Codec #%d probe error; disabling it...\n", c);
1099 bus->codec_mask &= ~(1 << c);
1100 /* More badly, accessing to a non-existing
1101 * codec often screws up the controller chip,
1102 * and disturbs the further communications.
1103 * Thus if an error occurs during probing,
1104 * better to reset the controller chip to
1105 * get back to the sanity state.
1107 azx_stop_chip(chip);
1108 azx_init_chip(chip, true);
1113 /* Then create codec instances */
1114 for (c = 0; c < max_slots; c++) {
1115 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1116 struct hda_codec *codec;
1117 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1120 codec->jackpoll_interval = get_jackpoll_interval(chip);
1121 codec->beep_mode = chip->beep_mode;
1126 dev_err(chip->card->dev, "no codecs initialized\n");
1131 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1133 /* configure each codec instance */
1134 int azx_codec_configure(struct azx *chip)
1136 struct hda_codec *codec, *next;
1138 /* use _safe version here since snd_hda_codec_configure() deregisters
1139 * the device upon error and deletes itself from the bus list.
1141 list_for_each_codec_safe(codec, next, &chip->bus) {
1142 snd_hda_codec_configure(codec);
1146 EXPORT_SYMBOL_GPL(azx_codec_configure);
1148 static int stream_direction(struct azx *chip, unsigned char index)
1150 if (index >= chip->capture_index_offset &&
1151 index < chip->capture_index_offset + chip->capture_streams)
1152 return SNDRV_PCM_STREAM_CAPTURE;
1153 return SNDRV_PCM_STREAM_PLAYBACK;
1156 /* initialize SD streams */
1157 int azx_init_streams(struct azx *chip)
1160 int stream_tags[2] = { 0, 0 };
1162 /* initialize each stream (aka device)
1163 * assign the starting bdl address to each stream (device)
1166 for (i = 0; i < chip->num_streams; i++) {
1167 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1173 dir = stream_direction(chip, i);
1174 /* stream tag must be unique throughout
1175 * the stream direction group,
1176 * valid values 1...15
1177 * use separate stream tag if the flag
1178 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1180 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1181 tag = ++stream_tags[dir];
1184 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1190 EXPORT_SYMBOL_GPL(azx_init_streams);
1192 void azx_free_streams(struct azx *chip)
1194 struct hdac_bus *bus = azx_bus(chip);
1195 struct hdac_stream *s;
1197 while (!list_empty(&bus->stream_list)) {
1198 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1200 kfree(stream_to_azx_dev(s));
1203 EXPORT_SYMBOL_GPL(azx_free_streams);