1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Lee Revell <rlrevell@joe-job.com>
5 * James Courtier-Dutton <James@superbug.co.uk>
6 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
9 * Routines for control of EMU10K1 chips
12 #include <linux/time.h>
13 #include <sound/core.h>
14 #include <sound/emu10k1.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
19 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg)
23 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK)
24 : (0xffff0000 & ~PTR_ADDRESS_MASK))))
26 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK))
31 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn)
34 unsigned int regptr, val;
37 regptr = (reg << 16) | chn;
38 if (!check_ptr_reg(emu, regptr))
41 spin_lock_irqsave(&emu->emu_lock, flags);
42 outl(regptr, emu->port + PTR);
43 val = inl(emu->port + DATA);
44 spin_unlock_irqrestore(&emu->emu_lock, flags);
46 if (reg & 0xff000000) {
47 unsigned char size, offset;
49 size = (reg >> 24) & 0x3f;
50 offset = (reg >> 16) & 0x1f;
51 mask = (1 << size) - 1;
53 return (val >> offset) & mask;
59 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
61 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data)
67 regptr = (reg << 16) | chn;
68 if (!check_ptr_reg(emu, regptr))
71 if (reg & 0xff000000) {
72 unsigned char size, offset;
74 size = (reg >> 24) & 0x3f;
75 offset = (reg >> 16) & 0x1f;
76 mask = (1 << size) - 1;
77 if (snd_BUG_ON(data & ~mask))
82 spin_lock_irqsave(&emu->emu_lock, flags);
83 outl(regptr, emu->port + PTR);
84 data |= inl(emu->port + DATA) & ~mask;
86 spin_lock_irqsave(&emu->emu_lock, flags);
87 outl(regptr, emu->port + PTR);
89 outl(data, emu->port + DATA);
90 spin_unlock_irqrestore(&emu->emu_lock, flags);
93 EXPORT_SYMBOL(snd_emu10k1_ptr_write);
95 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...)
101 if (snd_BUG_ON(!emu))
103 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK))
105 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16);
108 spin_lock_irqsave(&emu->emu_lock, flags);
111 u32 reg = va_arg(va, u32);
112 if (reg == REGLIST_END)
114 data = va_arg(va, u32);
115 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here
117 outl((reg << 16) | chn, emu->port + PTR);
118 outl(data, emu->port + DATA);
120 spin_unlock_irqrestore(&emu->emu_lock, flags);
124 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple);
126 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu,
131 unsigned int regptr, val;
133 regptr = (reg << 16) | chn;
135 spin_lock_irqsave(&emu->emu_lock, flags);
136 outl(regptr, emu->port + PTR2);
137 val = inl(emu->port + DATA2);
138 spin_unlock_irqrestore(&emu->emu_lock, flags);
142 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu,
150 regptr = (reg << 16) | chn;
152 spin_lock_irqsave(&emu->emu_lock, flags);
153 outl(regptr, emu->port + PTR2);
154 outl(data, emu->port + DATA2);
155 spin_unlock_irqrestore(&emu->emu_lock, flags);
158 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu,
161 unsigned int reset, set;
162 unsigned int reg, tmp;
166 /* This function is not re-entrant, so protect against it. */
167 spin_lock(&emu->spi_lock);
168 if (emu->card_capabilities->ca0108_chip)
171 /* For other chip types the SPI register
172 * is currently unknown. */
177 /* Only 16bit values allowed */
182 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
183 reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
184 set = reset | 0x10000; /* Set xxx1xxxx */
185 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
186 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
187 snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
189 /* Wait for status bit to return to 0 */
190 for (n = 0; n < 100; n++) {
192 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
193 if (!(tmp & 0x10000)) {
203 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
204 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
207 spin_unlock(&emu->spi_lock);
211 /* The ADC does not support i2c read, so only write is implemented */
212 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu,
222 if ((reg > 0x7f) || (value > 0x1ff)) {
223 dev_err(emu->card->dev, "i2c_write: invalid values.\n");
227 /* This function is not re-entrant, so protect against it. */
228 spin_lock(&emu->i2c_lock);
230 tmp = reg << 25 | value << 16;
232 /* This controls the I2C connected to the WM8775 ADC Codec */
233 snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp);
234 tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */
236 for (retry = 0; retry < 10; retry++) {
237 /* Send the data to i2c */
239 tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
240 snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp);
242 /* Wait till the transaction ends */
245 status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0);
247 if ((status & I2C_A_ADC_START) == 0)
250 if (timeout > 1000) {
251 dev_warn(emu->card->dev,
252 "emu10k1:I2C:timeout status=0x%x\n",
257 //Read back and see if the transaction is successful
258 if ((status & I2C_A_ADC_ABORT) == 0)
263 dev_err(emu->card->dev, "Writing to ADC failed!\n");
264 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n",
270 spin_unlock(&emu->i2c_lock);
274 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value)
276 if (snd_BUG_ON(reg > 0x3f))
278 reg += 0x40; /* 0x40 upwards are registers. */
279 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */
281 outw(reg, emu->port + A_GPIO);
283 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
285 outw(value, emu->port + A_GPIO);
287 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
290 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
294 spin_lock_irqsave(&emu->emu_lock, flags);
295 snd_emu1010_fpga_write_locked(emu, reg, value);
296 spin_unlock_irqrestore(&emu->emu_lock, flags);
299 static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value)
301 // The higest input pin is used as the designated interrupt trigger,
302 // so it needs to be masked out.
303 // But note that any other input pin change will also cause an IRQ,
304 // so using this function often causes an IRQ as a side effect.
305 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
306 if (snd_BUG_ON(reg > 0x3f))
308 reg += 0x40; /* 0x40 upwards are registers. */
309 outw(reg, emu->port + A_GPIO);
311 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
313 *value = ((inw(emu->port + A_GPIO) >> 8) & mask);
316 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
320 spin_lock_irqsave(&emu->emu_lock, flags);
321 snd_emu1010_fpga_read_locked(emu, reg, value);
322 spin_unlock_irqrestore(&emu->emu_lock, flags);
325 /* Each Destination has one and only one Source,
326 * but one Source can feed any number of Destinations simultaneously.
328 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src)
332 if (snd_BUG_ON(dst & ~0x71f))
334 if (snd_BUG_ON(src & ~0x71f))
336 spin_lock_irqsave(&emu->emu_lock, flags);
337 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
338 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8);
340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f);
341 spin_unlock_irqrestore(&emu->emu_lock, flags);
344 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst)
349 if (snd_BUG_ON(dst & ~0x71f))
351 spin_lock_irqsave(&emu->emu_lock, flags);
352 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
353 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
354 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi);
355 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo);
356 spin_unlock_irqrestore(&emu->emu_lock, flags);
357 return (hi << 8) | lo;
360 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src)
362 u32 reg_lo, reg_hi, value, value2;
365 case EMU_HANA_WCLOCK_HANA_SPDIF_IN:
366 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value);
367 if (value & EMU_HANA_SPDIF_MODE_RX_INVALID)
369 reg_lo = EMU_HANA_WC_SPDIF_LO;
370 reg_hi = EMU_HANA_WC_SPDIF_HI;
372 case EMU_HANA_WCLOCK_HANA_ADAT_IN:
373 reg_lo = EMU_HANA_WC_ADAT_LO;
374 reg_hi = EMU_HANA_WC_ADAT_HI;
376 case EMU_HANA_WCLOCK_SYNC_BNC:
377 reg_lo = EMU_HANA_WC_BNC_LO;
378 reg_hi = EMU_HANA_WC_BNC_HI;
380 case EMU_HANA_WCLOCK_2ND_HANA:
381 reg_lo = EMU_HANA2_WC_SPDIF_LO;
382 reg_hi = EMU_HANA2_WC_SPDIF_HI;
387 snd_emu1010_fpga_read(emu, reg_hi, &value);
388 snd_emu1010_fpga_read(emu, reg_lo, &value2);
389 // FIXME: The /4 is valid for 0404b, but contradicts all other info.
390 return 0x1770000 / 4 / (((value << 5) | value2) + 1);
393 void snd_emu1010_update_clock(struct snd_emu10k1 *emu)
398 switch (emu->emu1010.wclock) {
399 case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X:
401 leds = EMU_HANA_DOCK_LEDS_2_44K;
403 case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X:
405 leds = EMU_HANA_DOCK_LEDS_2_48K;
408 clock = snd_emu1010_get_raw_rate(
409 emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK);
410 // The raw rate reading is rather coarse (it cannot accurately
411 // represent 44.1 kHz) and fluctuates slightly. Luckily, the
412 // clock comes from digital inputs, which use standardized rates.
413 // So we round to the closest standard rate and ignore discrepancies.
416 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K;
419 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K;
423 emu->emu1010.word_clock = clock;
425 // FIXME: this should probably represent the AND of all currently
426 // used sources' lock status. But we don't know how to get that ...
427 leds |= EMU_HANA_DOCK_LEDS_2_LOCK;
429 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds);
432 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)
437 spin_lock_irqsave(&emu->emu_lock, flags);
438 enable = inl(emu->port + INTE) | intrenb;
439 outl(enable, emu->port + INTE);
440 spin_unlock_irqrestore(&emu->emu_lock, flags);
443 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb)
448 spin_lock_irqsave(&emu->emu_lock, flags);
449 enable = inl(emu->port + INTE) & ~intrenb;
450 outl(enable, emu->port + INTE);
451 spin_unlock_irqrestore(&emu->emu_lock, flags);
454 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
459 spin_lock_irqsave(&emu->emu_lock, flags);
460 if (voicenum >= 32) {
461 outl(CLIEH << 16, emu->port + PTR);
462 val = inl(emu->port + DATA);
463 val |= 1 << (voicenum - 32);
465 outl(CLIEL << 16, emu->port + PTR);
466 val = inl(emu->port + DATA);
467 val |= 1 << voicenum;
469 outl(val, emu->port + DATA);
470 spin_unlock_irqrestore(&emu->emu_lock, flags);
473 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
478 spin_lock_irqsave(&emu->emu_lock, flags);
479 if (voicenum >= 32) {
480 outl(CLIEH << 16, emu->port + PTR);
481 val = inl(emu->port + DATA);
482 val &= ~(1 << (voicenum - 32));
484 outl(CLIEL << 16, emu->port + PTR);
485 val = inl(emu->port + DATA);
486 val &= ~(1 << voicenum);
488 outl(val, emu->port + DATA);
489 spin_unlock_irqrestore(&emu->emu_lock, flags);
492 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
496 spin_lock_irqsave(&emu->emu_lock, flags);
497 if (voicenum >= 32) {
498 outl(CLIPH << 16, emu->port + PTR);
499 voicenum = 1 << (voicenum - 32);
501 outl(CLIPL << 16, emu->port + PTR);
502 voicenum = 1 << voicenum;
504 outl(voicenum, emu->port + DATA);
505 spin_unlock_irqrestore(&emu->emu_lock, flags);
508 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
513 spin_lock_irqsave(&emu->emu_lock, flags);
514 if (voicenum >= 32) {
515 outl(HLIEH << 16, emu->port + PTR);
516 val = inl(emu->port + DATA);
517 val |= 1 << (voicenum - 32);
519 outl(HLIEL << 16, emu->port + PTR);
520 val = inl(emu->port + DATA);
521 val |= 1 << voicenum;
523 outl(val, emu->port + DATA);
524 spin_unlock_irqrestore(&emu->emu_lock, flags);
527 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
532 spin_lock_irqsave(&emu->emu_lock, flags);
533 if (voicenum >= 32) {
534 outl(HLIEH << 16, emu->port + PTR);
535 val = inl(emu->port + DATA);
536 val &= ~(1 << (voicenum - 32));
538 outl(HLIEL << 16, emu->port + PTR);
539 val = inl(emu->port + DATA);
540 val &= ~(1 << voicenum);
542 outl(val, emu->port + DATA);
543 spin_unlock_irqrestore(&emu->emu_lock, flags);
546 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
550 spin_lock_irqsave(&emu->emu_lock, flags);
551 if (voicenum >= 32) {
552 outl(HLIPH << 16, emu->port + PTR);
553 voicenum = 1 << (voicenum - 32);
555 outl(HLIPL << 16, emu->port + PTR);
556 voicenum = 1 << voicenum;
558 outl(voicenum, emu->port + DATA);
559 spin_unlock_irqrestore(&emu->emu_lock, flags);
563 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
568 spin_lock_irqsave(&emu->emu_lock, flags);
569 if (voicenum >= 32) {
570 outl(SOLEH << 16, emu->port + PTR);
571 sol = inl(emu->port + DATA);
572 sol |= 1 << (voicenum - 32);
574 outl(SOLEL << 16, emu->port + PTR);
575 sol = inl(emu->port + DATA);
576 sol |= 1 << voicenum;
578 outl(sol, emu->port + DATA);
579 spin_unlock_irqrestore(&emu->emu_lock, flags);
582 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
587 spin_lock_irqsave(&emu->emu_lock, flags);
588 if (voicenum >= 32) {
589 outl(SOLEH << 16, emu->port + PTR);
590 sol = inl(emu->port + DATA);
591 sol &= ~(1 << (voicenum - 32));
593 outl(SOLEL << 16, emu->port + PTR);
594 sol = inl(emu->port + DATA);
595 sol &= ~(1 << voicenum);
597 outl(sol, emu->port + DATA);
598 spin_unlock_irqrestore(&emu->emu_lock, flags);
602 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
606 spin_lock_irqsave(&emu->emu_lock, flags);
607 outl(SOLEL << 16, emu->port + PTR);
608 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA);
609 outl(SOLEH << 16, emu->port + PTR);
610 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA);
611 spin_unlock_irqrestore(&emu->emu_lock, flags);
614 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
618 spin_lock_irqsave(&emu->emu_lock, flags);
619 outl(SOLEL << 16, emu->port + PTR);
620 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA);
621 outl(SOLEH << 16, emu->port + PTR);
622 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA);
623 spin_unlock_irqrestore(&emu->emu_lock, flags);
626 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices)
632 spin_lock_irqsave(&emu->emu_lock, flags);
634 outl(SOLEL << 16, emu->port + PTR);
635 soll = inl(emu->port + DATA);
636 outl(SOLEH << 16, emu->port + PTR);
637 solh = inl(emu->port + DATA);
639 soll &= (u32)~voices;
640 solh &= (u32)(~voices >> 32);
642 for (int tries = 0; tries < 1000; tries++) {
643 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2);
644 // First we wait for the third quarter of the sample cycle ...
645 u32 wc = inl(emu->port + WC);
646 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc);
647 if (cc >= quart * 2 && cc < quart * 3) {
648 // ... and release the low voices, while the high ones are serviced.
649 outl(SOLEL << 16, emu->port + PTR);
650 outl(soll, emu->port + DATA);
651 // Then we wait for the first quarter of the next sample cycle ...
652 for (; tries < 1000; tries++) {
653 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC));
656 // We will block for 10+ us with interrupts disabled. This is
657 // not nice at all, but necessary for reasonable reliability.
662 // ... and release the high voices, while the low ones are serviced.
663 outl(SOLEH << 16, emu->port + PTR);
664 outl(solh, emu->port + DATA);
665 // Finally we verify that nothing interfered in fact.
666 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) ==
667 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) {
674 // Don't block for too long
675 spin_unlock_irqrestore(&emu->emu_lock, flags);
677 spin_lock_irqsave(&emu->emu_lock, flags);
680 spin_unlock_irqrestore(&emu->emu_lock, flags);
684 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait)
686 volatile unsigned count;
687 unsigned int newtime = 0, curtime;
689 curtime = inl(emu->port + WC) >> 6;
692 while (count++ < 16384) {
693 newtime = inl(emu->port + WC) >> 6;
694 if (newtime != curtime)
703 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
705 struct snd_emu10k1 *emu = ac97->private_data;
709 spin_lock_irqsave(&emu->emu_lock, flags);
710 outb(reg, emu->port + AC97ADDRESS);
711 val = inw(emu->port + AC97DATA);
712 spin_unlock_irqrestore(&emu->emu_lock, flags);
716 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data)
718 struct snd_emu10k1 *emu = ac97->private_data;
721 spin_lock_irqsave(&emu->emu_lock, flags);
722 outb(reg, emu->port + AC97ADDRESS);
723 outw(data, emu->port + AC97DATA);
724 spin_unlock_irqrestore(&emu->emu_lock, flags);