2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Routines for effect processor FX8010
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added EMU 1010 support.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/pci.h>
32 #include <linux/capability.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/init.h>
37 #include <linux/mutex.h>
38 #include <linux/moduleparam.h>
39 #include <linux/nospec.h>
41 #include <sound/core.h>
42 #include <sound/tlv.h>
43 #include <sound/emu10k1.h>
45 #if 0 /* for testing purposes - digital out -> capture */
46 #define EMU10K1_CAPTURE_DIGITAL_OUT
48 #if 0 /* for testing purposes - set S/PDIF to AC3 output */
49 #define EMU10K1_SET_AC3_IEC958
51 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
52 #define EMU10K1_CENTER_LFE_FROM_FRONT
55 static bool high_res_gpr_volume;
56 module_param(high_res_gpr_volume, bool, 0444);
57 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
63 static char *fxbuses[16] = {
64 /* 0x00 */ "PCM Left",
65 /* 0x01 */ "PCM Right",
66 /* 0x02 */ "PCM Surround Left",
67 /* 0x03 */ "PCM Surround Right",
68 /* 0x04 */ "MIDI Left",
69 /* 0x05 */ "MIDI Right",
76 /* 0x0c */ "MIDI Reverb",
77 /* 0x0d */ "MIDI Chorus",
82 static char *creative_ins[16] = {
83 /* 0x00 */ "AC97 Left",
84 /* 0x01 */ "AC97 Right",
85 /* 0x02 */ "TTL IEC958 Left",
86 /* 0x03 */ "TTL IEC958 Right",
87 /* 0x04 */ "Zoom Video Left",
88 /* 0x05 */ "Zoom Video Right",
89 /* 0x06 */ "Optical IEC958 Left",
90 /* 0x07 */ "Optical IEC958 Right",
91 /* 0x08 */ "Line/Mic 1 Left",
92 /* 0x09 */ "Line/Mic 1 Right",
93 /* 0x0a */ "Coaxial IEC958 Left",
94 /* 0x0b */ "Coaxial IEC958 Right",
95 /* 0x0c */ "Line/Mic 2 Left",
96 /* 0x0d */ "Line/Mic 2 Right",
101 static char *audigy_ins[16] = {
102 /* 0x00 */ "AC97 Left",
103 /* 0x01 */ "AC97 Right",
104 /* 0x02 */ "Audigy CD Left",
105 /* 0x03 */ "Audigy CD Right",
106 /* 0x04 */ "Optical IEC958 Left",
107 /* 0x05 */ "Optical IEC958 Right",
110 /* 0x08 */ "Line/Mic 2 Left",
111 /* 0x09 */ "Line/Mic 2 Right",
112 /* 0x0a */ "SPDIF Left",
113 /* 0x0b */ "SPDIF Right",
114 /* 0x0c */ "Aux2 Left",
115 /* 0x0d */ "Aux2 Right",
120 static char *creative_outs[32] = {
121 /* 0x00 */ "AC97 Left",
122 /* 0x01 */ "AC97 Right",
123 /* 0x02 */ "Optical IEC958 Left",
124 /* 0x03 */ "Optical IEC958 Right",
127 /* 0x06 */ "Headphone Left",
128 /* 0x07 */ "Headphone Right",
129 /* 0x08 */ "Surround Left",
130 /* 0x09 */ "Surround Right",
131 /* 0x0a */ "PCM Capture Left",
132 /* 0x0b */ "PCM Capture Right",
133 /* 0x0c */ "MIC Capture",
134 /* 0x0d */ "AC97 Surround Left",
135 /* 0x0e */ "AC97 Surround Right",
138 /* 0x11 */ "Analog Center",
139 /* 0x12 */ "Analog LFE",
155 static char *audigy_outs[32] = {
156 /* 0x00 */ "Digital Front Left",
157 /* 0x01 */ "Digital Front Right",
158 /* 0x02 */ "Digital Center",
159 /* 0x03 */ "Digital LEF",
160 /* 0x04 */ "Headphone Left",
161 /* 0x05 */ "Headphone Right",
162 /* 0x06 */ "Digital Rear Left",
163 /* 0x07 */ "Digital Rear Right",
164 /* 0x08 */ "Front Left",
165 /* 0x09 */ "Front Right",
170 /* 0x0e */ "Rear Left",
171 /* 0x0f */ "Rear Right",
172 /* 0x10 */ "AC97 Front Left",
173 /* 0x11 */ "AC97 Front Right",
174 /* 0x12 */ "ADC Capture Left",
175 /* 0x13 */ "ADC Capture Right",
190 static const u32 bass_table[41][5] = {
191 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
192 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
193 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
194 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
195 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
196 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
197 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
198 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
199 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
200 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
201 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
202 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
203 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
204 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
205 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
206 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
207 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
208 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
209 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
210 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
211 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
212 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
213 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
214 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
215 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
216 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
217 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
218 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
219 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
220 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
221 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
222 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
223 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
224 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
225 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
226 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
227 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
228 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
229 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
230 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
231 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
234 static const u32 treble_table[41][5] = {
235 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
236 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
237 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
238 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
239 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
240 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
241 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
242 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
243 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
244 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
245 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
246 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
247 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
248 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
249 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
250 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
251 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
252 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
253 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
254 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
255 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
256 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
257 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
258 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
259 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
260 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
261 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
262 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
263 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
264 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
265 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
266 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
267 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
268 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
269 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
270 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
271 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
272 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
273 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
274 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
275 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
278 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
279 static const u32 db_table[101] = {
280 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
281 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
282 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
283 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
284 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
285 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
286 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
287 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
288 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
289 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
290 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
291 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
292 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
293 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
294 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
295 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
296 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
297 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
298 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
299 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
303 /* EMU10k1/EMU10k2 DSP control db gain */
304 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
305 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
307 /* EMU10K1 bass/treble db gain */
308 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
310 static const u32 onoff_table[2] = {
311 0x00000000, 0x00000001
318 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
320 struct snd_emu10k1_fx8010_ctl *ctl =
321 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
323 if (ctl->min == 0 && ctl->max == 1)
324 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
326 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
327 uinfo->count = ctl->vcount;
328 uinfo->value.integer.min = ctl->min;
329 uinfo->value.integer.max = ctl->max;
333 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
335 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
336 struct snd_emu10k1_fx8010_ctl *ctl =
337 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
341 spin_lock_irqsave(&emu->reg_lock, flags);
342 for (i = 0; i < ctl->vcount; i++)
343 ucontrol->value.integer.value[i] = ctl->value[i];
344 spin_unlock_irqrestore(&emu->reg_lock, flags);
348 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
350 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
351 struct snd_emu10k1_fx8010_ctl *ctl =
352 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
354 unsigned int nval, val;
358 spin_lock_irqsave(&emu->reg_lock, flags);
359 for (i = 0; i < ctl->vcount; i++) {
360 nval = ucontrol->value.integer.value[i];
365 if (nval != ctl->value[i])
367 val = ctl->value[i] = nval;
368 switch (ctl->translation) {
369 case EMU10K1_GPR_TRANSLATION_NONE:
370 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
372 case EMU10K1_GPR_TRANSLATION_TABLE100:
373 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
375 case EMU10K1_GPR_TRANSLATION_BASS:
376 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
380 for (j = 0; j < 5; j++)
381 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
383 case EMU10K1_GPR_TRANSLATION_TREBLE:
384 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
388 for (j = 0; j < 5; j++)
389 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
391 case EMU10K1_GPR_TRANSLATION_ONOFF:
392 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
397 spin_unlock_irqrestore(&emu->reg_lock, flags);
405 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
407 struct snd_emu10k1_fx8010_irq *irq, *nirq;
409 irq = emu->fx8010.irq_handlers;
411 nirq = irq->next; /* irq ptr can be removed from list */
412 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
414 irq->handler(emu, irq->private_data);
415 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
421 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
422 snd_fx8010_irq_handler_t *handler,
423 unsigned char gpr_running,
425 struct snd_emu10k1_fx8010_irq *irq)
429 irq->handler = handler;
430 irq->gpr_running = gpr_running;
431 irq->private_data = private_data;
433 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
434 if (emu->fx8010.irq_handlers == NULL) {
435 emu->fx8010.irq_handlers = irq;
436 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
437 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
439 irq->next = emu->fx8010.irq_handlers;
440 emu->fx8010.irq_handlers = irq;
442 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
446 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
447 struct snd_emu10k1_fx8010_irq *irq)
449 struct snd_emu10k1_fx8010_irq *tmp;
452 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
453 if ((tmp = emu->fx8010.irq_handlers) == irq) {
454 emu->fx8010.irq_handlers = tmp->next;
455 if (emu->fx8010.irq_handlers == NULL) {
456 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
457 emu->dsp_interrupt = NULL;
460 while (tmp && tmp->next != irq)
463 tmp->next = tmp->next->next;
465 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
469 /*************************************************************************
470 * EMU10K1 effect manager
471 *************************************************************************/
473 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
475 u32 op, u32 r, u32 a, u32 x, u32 y)
478 if (snd_BUG_ON(*ptr >= 512))
480 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
481 set_bit(*ptr, icode->code_valid);
482 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
483 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
487 #define OP(icode, ptr, op, r, a, x, y) \
488 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
490 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
492 u32 op, u32 r, u32 a, u32 x, u32 y)
495 if (snd_BUG_ON(*ptr >= 1024))
497 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
498 set_bit(*ptr, icode->code_valid);
499 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
500 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
504 #define A_OP(icode, ptr, op, r, a, x, y) \
505 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
507 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
509 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
510 snd_emu10k1_ptr_write(emu, pc, 0, data);
513 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
515 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
516 return snd_emu10k1_ptr_read(emu, pc, 0);
519 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
520 struct snd_emu10k1_fx8010_code *icode,
526 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
527 if (!test_bit(gpr, icode->gpr_valid))
530 val = *(__force u32 *)&icode->gpr_map[gpr];
531 else if (get_user(val, &icode->gpr_map[gpr]))
533 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
538 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
539 struct snd_emu10k1_fx8010_code *icode)
544 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
545 set_bit(gpr, icode->gpr_valid);
546 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
547 if (put_user(val, &icode->gpr_map[gpr]))
553 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
554 struct snd_emu10k1_fx8010_code *icode,
560 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
561 if (!test_bit(tram, icode->tram_valid))
564 val = *(__force u32 *)&icode->tram_data_map[tram];
565 addr = *(__force u32 *)&icode->tram_addr_map[tram];
567 if (get_user(val, &icode->tram_data_map[tram]) ||
568 get_user(addr, &icode->tram_addr_map[tram]))
571 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
573 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
575 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
576 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
582 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
583 struct snd_emu10k1_fx8010_code *icode)
588 memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
589 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
590 set_bit(tram, icode->tram_valid);
591 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
593 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
595 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
596 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
598 if (put_user(val, &icode->tram_data_map[tram]) ||
599 put_user(addr, &icode->tram_addr_map[tram]))
605 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
606 struct snd_emu10k1_fx8010_code *icode,
611 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
612 if (!test_bit(pc / 2, icode->code_valid))
615 lo = *(__force u32 *)&icode->code[pc + 0];
616 hi = *(__force u32 *)&icode->code[pc + 1];
618 if (get_user(lo, &icode->code[pc + 0]) ||
619 get_user(hi, &icode->code[pc + 1]))
622 snd_emu10k1_efx_write(emu, pc + 0, lo);
623 snd_emu10k1_efx_write(emu, pc + 1, hi);
628 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
629 struct snd_emu10k1_fx8010_code *icode)
633 memset(icode->code_valid, 0, sizeof(icode->code_valid));
634 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
635 set_bit(pc / 2, icode->code_valid);
636 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
638 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
644 static struct snd_emu10k1_fx8010_ctl *
645 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
647 struct snd_emu10k1_fx8010_ctl *ctl;
648 struct snd_kcontrol *kcontrol;
650 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
651 kcontrol = ctl->kcontrol;
652 if (kcontrol->id.iface == id->iface &&
653 !strcmp(kcontrol->id.name, id->name) &&
654 kcontrol->id.index == id->index)
660 #define MAX_TLV_SIZE 256
662 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
664 unsigned int data[2];
670 memcpy(data, (__force void *)_tlv, sizeof(data));
671 else if (copy_from_user(data, _tlv, sizeof(data)))
673 if (data[1] >= MAX_TLV_SIZE)
675 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
678 memcpy(tlv, data, sizeof(data));
680 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
681 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
688 static int copy_gctl(struct snd_emu10k1 *emu,
689 struct snd_emu10k1_fx8010_control_gpr *gctl,
690 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
691 int idx, bool in_kernel)
693 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
695 if (emu->support_tlv) {
697 memcpy(gctl, (__force void *)&_gctl[idx], sizeof(*gctl));
698 else if (copy_from_user(gctl, &_gctl[idx], sizeof(*gctl)))
703 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
705 memcpy(gctl, (__force void *)&octl[idx], sizeof(*octl));
706 else if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
712 static int copy_gctl_to_user(struct snd_emu10k1 *emu,
713 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
714 struct snd_emu10k1_fx8010_control_gpr *gctl,
717 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
719 if (emu->support_tlv)
720 return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
722 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
723 return copy_to_user(&octl[idx], gctl, sizeof(*octl));
726 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
727 struct snd_emu10k1_fx8010_code *icode,
731 struct snd_ctl_elem_id __user *_id;
732 struct snd_ctl_elem_id id;
733 struct snd_emu10k1_fx8010_control_gpr *gctl;
736 for (i = 0, _id = icode->gpr_del_controls;
737 i < icode->gpr_del_control_count; i++, _id++) {
739 id = *(__force struct snd_ctl_elem_id *)_id;
740 else if (copy_from_user(&id, _id, sizeof(id)))
742 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
745 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
749 for (i = 0; i < icode->gpr_add_control_count; i++) {
750 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
755 if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
757 down_read(&emu->card->controls_rwsem);
758 if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
759 up_read(&emu->card->controls_rwsem);
763 up_read(&emu->card->controls_rwsem);
764 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
765 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
770 for (i = 0; i < icode->gpr_list_control_count; i++) {
771 /* FIXME: we need to check the WRITE access */
772 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
783 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
785 struct snd_emu10k1_fx8010_ctl *ctl;
787 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
788 kctl->private_value = 0;
789 list_del(&ctl->list);
794 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
795 struct snd_emu10k1_fx8010_code *icode,
799 struct snd_emu10k1_fx8010_control_gpr *gctl;
800 struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
801 struct snd_kcontrol_new knew;
802 struct snd_kcontrol *kctl;
803 struct snd_ctl_elem_value *val;
806 val = kmalloc(sizeof(*val), GFP_KERNEL);
807 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
808 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
809 if (!val || !gctl || !nctl) {
814 for (i = 0; i < icode->gpr_add_control_count; i++) {
815 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
820 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
821 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
825 if (! gctl->id.name[0]) {
829 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
830 memset(&knew, 0, sizeof(knew));
831 knew.iface = gctl->id.iface;
832 knew.name = gctl->id.name;
833 knew.index = gctl->id.index;
834 knew.device = gctl->id.device;
835 knew.subdevice = gctl->id.subdevice;
836 knew.info = snd_emu10k1_gpr_ctl_info;
837 knew.tlv.p = copy_tlv((__force const unsigned int __user *)gctl->tlv, in_kernel);
839 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
840 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
841 knew.get = snd_emu10k1_gpr_ctl_get;
842 knew.put = snd_emu10k1_gpr_ctl_put;
843 memset(nctl, 0, sizeof(*nctl));
844 nctl->vcount = gctl->vcount;
845 nctl->count = gctl->count;
846 for (j = 0; j < 32; j++) {
847 nctl->gpr[j] = gctl->gpr[j];
848 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
849 val->value.integer.value[j] = gctl->value[j];
851 nctl->min = gctl->min;
852 nctl->max = gctl->max;
853 nctl->translation = gctl->translation;
855 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
861 knew.private_value = (unsigned long)ctl;
863 if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
868 kctl->private_free = snd_emu10k1_ctl_private_free;
869 ctl->kcontrol = kctl;
870 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
873 nctl->list = ctl->list;
874 nctl->kcontrol = ctl->kcontrol;
876 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
877 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
879 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
888 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
889 struct snd_emu10k1_fx8010_code *icode,
893 struct snd_ctl_elem_id id;
894 struct snd_ctl_elem_id __user *_id;
895 struct snd_emu10k1_fx8010_ctl *ctl;
896 struct snd_card *card = emu->card;
898 for (i = 0, _id = icode->gpr_del_controls;
899 i < icode->gpr_del_control_count; i++, _id++) {
901 id = *(__force struct snd_ctl_elem_id *)_id;
902 else if (copy_from_user(&id, _id, sizeof(id)))
904 down_write(&card->controls_rwsem);
905 ctl = snd_emu10k1_look_for_ctl(emu, &id);
907 snd_ctl_remove(card, ctl->kcontrol);
908 up_write(&card->controls_rwsem);
913 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
914 struct snd_emu10k1_fx8010_code *icode)
916 unsigned int i = 0, j;
917 unsigned int total = 0;
918 struct snd_emu10k1_fx8010_control_gpr *gctl;
919 struct snd_emu10k1_fx8010_ctl *ctl;
920 struct snd_ctl_elem_id *id;
922 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
926 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
928 if (icode->gpr_list_controls &&
929 i < icode->gpr_list_control_count) {
930 memset(gctl, 0, sizeof(*gctl));
931 id = &ctl->kcontrol->id;
932 gctl->id.iface = id->iface;
933 strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
934 gctl->id.index = id->index;
935 gctl->id.device = id->device;
936 gctl->id.subdevice = id->subdevice;
937 gctl->vcount = ctl->vcount;
938 gctl->count = ctl->count;
939 for (j = 0; j < 32; j++) {
940 gctl->gpr[j] = ctl->gpr[j];
941 gctl->value[j] = ctl->value[j];
943 gctl->min = ctl->min;
944 gctl->max = ctl->max;
945 gctl->translation = ctl->translation;
946 if (copy_gctl_to_user(emu, icode->gpr_list_controls,
954 icode->gpr_list_control_total = total;
959 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
960 struct snd_emu10k1_fx8010_code *icode,
965 mutex_lock(&emu->fx8010.lock);
966 err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
969 strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
970 /* stop FX processor - this may be dangerous, but it's better to miss
971 some samples than generate wrong ones - [jk] */
973 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
975 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
976 /* ok, do the main job */
977 err = snd_emu10k1_del_controls(emu, icode, in_kernel);
980 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
983 err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
986 err = snd_emu10k1_code_poke(emu, icode, in_kernel);
989 err = snd_emu10k1_add_controls(emu, icode, in_kernel);
992 /* start FX processor when the DSP code is updated */
994 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
996 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
998 mutex_unlock(&emu->fx8010.lock);
1002 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
1003 struct snd_emu10k1_fx8010_code *icode)
1007 mutex_lock(&emu->fx8010.lock);
1008 strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
1009 /* ok, do the main job */
1010 err = snd_emu10k1_gpr_peek(emu, icode);
1012 err = snd_emu10k1_tram_peek(emu, icode);
1014 err = snd_emu10k1_code_peek(emu, icode);
1016 err = snd_emu10k1_list_controls(emu, icode);
1017 mutex_unlock(&emu->fx8010.lock);
1021 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
1022 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1026 struct snd_emu10k1_fx8010_pcm *pcm;
1028 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1030 ipcm->substream = array_index_nospec(ipcm->substream,
1031 EMU10K1_FX8010_PCM_COUNT);
1032 if (ipcm->channels > 32)
1034 pcm = &emu->fx8010.pcm[ipcm->substream];
1035 mutex_lock(&emu->fx8010.lock);
1036 spin_lock_irq(&emu->reg_lock);
1041 if (ipcm->channels == 0) { /* remove */
1044 /* FIXME: we need to add universal code to the PCM transfer routine */
1045 if (ipcm->channels != 2) {
1051 pcm->channels = ipcm->channels;
1052 pcm->tram_start = ipcm->tram_start;
1053 pcm->buffer_size = ipcm->buffer_size;
1054 pcm->gpr_size = ipcm->gpr_size;
1055 pcm->gpr_count = ipcm->gpr_count;
1056 pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1057 pcm->gpr_ptr = ipcm->gpr_ptr;
1058 pcm->gpr_trigger = ipcm->gpr_trigger;
1059 pcm->gpr_running = ipcm->gpr_running;
1060 for (i = 0; i < pcm->channels; i++)
1061 pcm->etram[i] = ipcm->etram[i];
1064 spin_unlock_irq(&emu->reg_lock);
1065 mutex_unlock(&emu->fx8010.lock);
1069 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1070 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1074 struct snd_emu10k1_fx8010_pcm *pcm;
1076 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1078 ipcm->substream = array_index_nospec(ipcm->substream,
1079 EMU10K1_FX8010_PCM_COUNT);
1080 pcm = &emu->fx8010.pcm[ipcm->substream];
1081 mutex_lock(&emu->fx8010.lock);
1082 spin_lock_irq(&emu->reg_lock);
1083 ipcm->channels = pcm->channels;
1084 ipcm->tram_start = pcm->tram_start;
1085 ipcm->buffer_size = pcm->buffer_size;
1086 ipcm->gpr_size = pcm->gpr_size;
1087 ipcm->gpr_ptr = pcm->gpr_ptr;
1088 ipcm->gpr_count = pcm->gpr_count;
1089 ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1090 ipcm->gpr_trigger = pcm->gpr_trigger;
1091 ipcm->gpr_running = pcm->gpr_running;
1092 for (i = 0; i < pcm->channels; i++)
1093 ipcm->etram[i] = pcm->etram[i];
1094 ipcm->res1 = ipcm->res2 = 0;
1096 spin_unlock_irq(&emu->reg_lock);
1097 mutex_unlock(&emu->fx8010.lock);
1101 #define SND_EMU10K1_GPR_CONTROLS 44
1102 #define SND_EMU10K1_INPUTS 12
1103 #define SND_EMU10K1_PLAYBACK_CHANNELS 8
1104 #define SND_EMU10K1_CAPTURE_CHANNELS 4
1107 snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1108 const char *name, int gpr, int defval)
1110 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1111 strcpy(ctl->id.name, name);
1112 ctl->vcount = ctl->count = 1;
1113 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1114 if (high_res_gpr_volume) {
1116 ctl->max = 0x7fffffff;
1117 ctl->tlv = snd_emu10k1_db_linear;
1118 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1122 ctl->tlv = snd_emu10k1_db_scale1;
1123 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1128 snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1129 const char *name, int gpr, int defval)
1131 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1132 strcpy(ctl->id.name, name);
1133 ctl->vcount = ctl->count = 2;
1134 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1135 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1136 if (high_res_gpr_volume) {
1138 ctl->max = 0x7fffffff;
1139 ctl->tlv = snd_emu10k1_db_linear;
1140 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1144 ctl->tlv = snd_emu10k1_db_scale1;
1145 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1150 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1151 const char *name, int gpr, int defval)
1153 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1154 strcpy(ctl->id.name, name);
1155 ctl->vcount = ctl->count = 1;
1156 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1159 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1163 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1164 const char *name, int gpr, int defval)
1166 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1167 strcpy(ctl->id.name, name);
1168 ctl->vcount = ctl->count = 2;
1169 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1170 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1173 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1177 * Used for emu1010 - conversion from 32-bit capture inputs from HANA
1178 * to 2 x 16-bit registers in audigy - their values are read via DMA.
1179 * Conversion is performed by Audigy DSP instructions of FX8010.
1181 static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1182 struct snd_emu10k1_fx8010_code *icode,
1183 u32 *ptr, int tmp, int bit_shifter16,
1184 int reg_in, int reg_out)
1186 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
1187 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
1188 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
1189 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
1190 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
1191 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
1192 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
1193 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
1198 * initial DSP configuration for Audigy
1201 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1203 int err, i, z, gpr, nctl;
1205 const int playback = 10;
1206 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
1207 const int stereo_mix = capture + 2;
1208 const int tmp = 0x88;
1210 struct snd_emu10k1_fx8010_code *icode = NULL;
1211 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1215 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1219 icode->gpr_map = (u_int32_t __user *) kcalloc(512 + 256 + 256 + 2 * 1024,
1220 sizeof(u_int32_t), GFP_KERNEL);
1221 if (!icode->gpr_map)
1223 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1224 sizeof(*controls), GFP_KERNEL);
1228 gpr_map = (u32 __force *)icode->gpr_map;
1230 icode->tram_data_map = icode->gpr_map + 512;
1231 icode->tram_addr_map = icode->tram_data_map + 256;
1232 icode->code = icode->tram_addr_map + 256;
1234 /* clear free GPRs */
1235 for (i = 0; i < 512; i++)
1236 set_bit(i, icode->gpr_valid);
1238 /* clear TRAM data & address lines */
1239 for (i = 0; i < 256; i++)
1240 set_bit(i, icode->tram_valid);
1242 strcpy(icode->name, "Audigy DSP code for ALSA");
1245 gpr = stereo_mix + 10;
1246 gpr_map[gpr++] = 0x00007fff;
1247 gpr_map[gpr++] = 0x00008000;
1248 gpr_map[gpr++] = 0x0000ffff;
1249 bit_shifter16 = gpr;
1251 /* stop FX processor */
1252 snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
1255 /* PCM front Playback Volume (independent from stereo mix)
1256 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
1257 * where gpr contains attenuation from corresponding mixer control
1258 * (snd_emu10k1_init_stereo_control)
1260 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1261 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1262 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1265 /* PCM Surround Playback (independent from stereo mix) */
1266 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1267 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1268 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1271 /* PCM Side Playback (independent from stereo mix) */
1272 if (emu->card_capabilities->spk71) {
1273 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1274 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1275 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1279 /* PCM Center Playback (independent from stereo mix) */
1280 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1281 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1284 /* PCM LFE Playback (independent from stereo mix) */
1285 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1286 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1292 /* Wave (PCM) Playback Volume (will be renamed later) */
1293 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1294 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1295 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1298 /* Synth Playback */
1299 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1300 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1301 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1304 /* Wave (PCM) Capture */
1305 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1306 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1307 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1311 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1312 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1313 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1319 #define A_ADD_VOLUME_IN(var,vol,input) \
1320 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1322 /* emu1212 DSP 0 and DSP 1 Capture */
1323 if (emu->card_capabilities->emu_model) {
1324 if (emu->card_capabilities->ca0108_chip) {
1325 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
1326 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
1327 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
1328 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
1329 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
1331 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
1332 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
1334 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1337 /* AC'97 Playback Volume - used only for mic (renamed later) */
1338 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1339 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1340 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1342 /* AC'97 Capture Volume - used only for mic */
1343 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1344 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1345 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1348 /* mic capture buffer */
1349 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
1351 /* Audigy CD Playback Volume */
1352 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1353 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1354 snd_emu10k1_init_stereo_control(&controls[nctl++],
1355 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1358 /* Audigy CD Capture Volume */
1359 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1360 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1361 snd_emu10k1_init_stereo_control(&controls[nctl++],
1362 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1366 /* Optical SPDIF Playback Volume */
1367 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1368 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1369 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1371 /* Optical SPDIF Capture Volume */
1372 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1373 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1374 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1377 /* Line2 Playback Volume */
1378 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1379 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1380 snd_emu10k1_init_stereo_control(&controls[nctl++],
1381 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1384 /* Line2 Capture Volume */
1385 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1386 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1387 snd_emu10k1_init_stereo_control(&controls[nctl++],
1388 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1392 /* Philips ADC Playback Volume */
1393 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1394 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1395 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1397 /* Philips ADC Capture Volume */
1398 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1399 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1400 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1403 /* Aux2 Playback Volume */
1404 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1405 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1406 snd_emu10k1_init_stereo_control(&controls[nctl++],
1407 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1410 /* Aux2 Capture Volume */
1411 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1412 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1413 snd_emu10k1_init_stereo_control(&controls[nctl++],
1414 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1418 /* Stereo Mix Front Playback Volume */
1419 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1420 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1421 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1424 /* Stereo Mix Surround Playback */
1425 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1426 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1427 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1430 /* Stereo Mix Center Playback */
1431 /* Center = sub = Left/2 + Right/2 */
1432 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
1433 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1434 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1437 /* Stereo Mix LFE Playback */
1438 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1439 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1442 if (emu->card_capabilities->spk71) {
1443 /* Stereo Mix Side Playback */
1444 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1445 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1446 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1453 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1454 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1455 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1457 #define _A_SWITCH(icode, ptr, dst, src, sw) \
1458 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1459 #define A_SWITCH(icode, ptr, dst, src, sw) \
1460 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1461 #define _A_SWITCH_NEG(icode, ptr, dst, src) \
1462 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1463 #define A_SWITCH_NEG(icode, ptr, dst, src) \
1464 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1468 * Process tone control
1470 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
1471 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
1472 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
1473 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
1474 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
1475 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
1476 if (emu->card_capabilities->spk71) {
1477 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
1478 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
1482 ctl = &controls[nctl + 0];
1483 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1484 strcpy(ctl->id.name, "Tone Control - Bass");
1489 ctl->value[0] = ctl->value[1] = 20;
1490 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1491 ctl = &controls[nctl + 1];
1492 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1493 strcpy(ctl->id.name, "Tone Control - Treble");
1498 ctl->value[0] = ctl->value[1] = 20;
1499 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1501 #define BASS_GPR 0x8c
1502 #define TREBLE_GPR 0x96
1504 for (z = 0; z < 5; z++) {
1506 for (j = 0; j < 2; j++) {
1507 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
1508 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
1511 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
1513 for (j = 0; j < 2; j++) { /* left/right */
1514 k = 0xb0 + (z * 8) + (j * 4);
1515 l = 0xe0 + (z * 8) + (j * 4);
1516 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
1518 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
1519 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
1520 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
1521 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
1522 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
1523 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1525 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
1526 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
1527 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
1528 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
1529 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
1530 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1532 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1534 if (z == 2) /* center */
1543 for (z = 0; z < 8; z++) {
1544 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
1545 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
1546 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1547 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1549 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1552 /* Master volume (will be renamed later) */
1553 for (z = 0; z < 8; z++)
1554 A_OP(icode, &ptr, iMAC0, A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS));
1555 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1558 /* analog speakers */
1559 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1560 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1561 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1562 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1563 if (emu->card_capabilities->spk71)
1564 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
1567 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1569 /* digital outputs */
1570 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
1571 if (emu->card_capabilities->emu_model) {
1572 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1573 dev_info(emu->card->dev, "EMU outputs on\n");
1574 for (z = 0; z < 8; z++) {
1575 if (emu->card_capabilities->ca0108_chip) {
1576 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1578 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1583 /* IEC958 Optical Raw Playback Switch */
1585 gpr_map[gpr++] = 0x1008;
1586 gpr_map[gpr++] = 0xffff0000;
1587 for (z = 0; z < 2; z++) {
1588 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1589 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1590 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1591 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1592 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1593 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1594 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
1595 if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1596 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1597 dev_info(emu->card->dev,
1598 "Installing spdif_bug patch: %s\n",
1599 emu->card_capabilities->name);
1600 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1601 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1603 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1606 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1609 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1610 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1611 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1614 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1615 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1617 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1618 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1621 if (emu->card_capabilities->emu_model) {
1622 if (emu->card_capabilities->ca0108_chip) {
1623 dev_info(emu->card->dev, "EMU2 inputs on\n");
1624 for (z = 0; z < 0x10; z++) {
1625 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
1631 dev_info(emu->card->dev, "EMU inputs on\n");
1632 /* Capture 16 (originally 8) channels of S32_LE sound */
1635 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1638 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1639 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1640 * will need to also be delayed; we use an auxiliary register for that. */
1641 for (z = 1; z < 0x10; z++) {
1642 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
1643 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
1644 gpr_map[gpr++] = 0x00000000;
1649 for (z = 4; z < 8; z++) {
1650 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1652 for (z = 0xc; z < 0x10; z++) {
1653 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1657 /* EFX capture - capture the 16 EXTINs */
1658 /* Capture 16 channels of S16_LE sound */
1659 for (z = 0; z < 16; z++) {
1660 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1664 #endif /* JCD test */
1674 /* clear remaining instruction memory */
1676 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1678 icode->gpr_add_control_count = nctl;
1679 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
1680 emu->support_tlv = 1; /* support TLV */
1681 err = snd_emu10k1_icode_poke(emu, icode, true);
1682 emu->support_tlv = 0; /* clear again */
1687 kfree((void __force *)icode->gpr_map);
1695 * initial DSP configuration for Emu10k1
1698 /* when volume = max, then copy only to avoid volume modification */
1699 /* with iMAC0 (negative values) */
1700 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1702 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1703 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1704 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
1705 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1707 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1709 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1710 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1711 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
1712 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1713 OP(icode, ptr, iMAC0, dst, dst, src, vol);
1715 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1717 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1718 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1719 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1720 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1721 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1724 #define VOLUME(icode, ptr, dst, src, vol) \
1725 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1726 #define VOLUME_IN(icode, ptr, dst, src, vol) \
1727 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1728 #define VOLUME_ADD(icode, ptr, dst, src, vol) \
1729 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1730 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1731 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1732 #define VOLUME_OUT(icode, ptr, dst, src, vol) \
1733 _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1734 #define _SWITCH(icode, ptr, dst, src, sw) \
1735 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1736 #define SWITCH(icode, ptr, dst, src, sw) \
1737 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1738 #define SWITCH_IN(icode, ptr, dst, src, sw) \
1739 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1740 #define _SWITCH_NEG(icode, ptr, dst, src) \
1741 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1742 #define SWITCH_NEG(icode, ptr, dst, src) \
1743 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1746 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1748 int err, i, z, gpr, tmp, playback, capture;
1750 struct snd_emu10k1_fx8010_code *icode;
1751 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1752 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1756 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1760 icode->gpr_map = (u_int32_t __user *) kcalloc(256 + 160 + 160 + 2 * 512,
1761 sizeof(u_int32_t), GFP_KERNEL);
1762 if (!icode->gpr_map)
1765 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1766 sizeof(struct snd_emu10k1_fx8010_control_gpr),
1771 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
1775 gpr_map = (u32 __force *)icode->gpr_map;
1777 icode->tram_data_map = icode->gpr_map + 256;
1778 icode->tram_addr_map = icode->tram_data_map + 160;
1779 icode->code = icode->tram_addr_map + 160;
1781 /* clear free GPRs */
1782 for (i = 0; i < 256; i++)
1783 set_bit(i, icode->gpr_valid);
1785 /* clear TRAM data & address lines */
1786 for (i = 0; i < 160; i++)
1787 set_bit(i, icode->tram_valid);
1789 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1791 /* we have 12 inputs */
1792 playback = SND_EMU10K1_INPUTS;
1793 /* we have 6 playback channels and tone control doubles */
1794 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
1795 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1796 tmp = 0x88; /* we need 4 temporary GPR */
1797 /* from 0x8c to 0xff is the area for tone control */
1799 /* stop FX processor */
1800 snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
1805 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
1806 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
1807 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
1808 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
1809 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
1810 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
1811 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
1812 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
1813 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
1814 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
1815 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
1816 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
1818 /* Raw S/PDIF PCM */
1819 ipcm->substream = 0;
1821 ipcm->tram_start = 0;
1822 ipcm->buffer_size = (64 * 1024) / 2;
1823 ipcm->gpr_size = gpr++;
1824 ipcm->gpr_ptr = gpr++;
1825 ipcm->gpr_count = gpr++;
1826 ipcm->gpr_tmpcount = gpr++;
1827 ipcm->gpr_trigger = gpr++;
1828 ipcm->gpr_running = gpr++;
1832 gpr_map[gpr + 0] = 0xfffff000;
1833 gpr_map[gpr + 1] = 0xffff0000;
1834 gpr_map[gpr + 2] = 0x70000000;
1835 gpr_map[gpr + 3] = 0x00000007;
1836 gpr_map[gpr + 4] = 0x001f << 11;
1837 gpr_map[gpr + 5] = 0x001c << 11;
1838 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
1839 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
1840 gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1841 gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1842 gpr_map[gpr + 10] = 1<<11;
1843 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
1844 gpr_map[gpr + 12] = 0;
1846 /* if the trigger flag is not set, skip */
1847 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1848 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1849 /* if the running flag is set, we're running */
1850 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1851 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1852 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1853 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1854 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1855 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1856 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1858 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1859 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1860 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1861 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1863 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1864 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1865 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1866 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1867 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1869 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1870 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1871 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1872 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1873 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1875 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1876 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1877 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1878 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1879 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1881 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1882 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1883 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1884 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1885 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1887 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1888 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1890 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1891 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1896 /* Wave Playback Volume */
1897 for (z = 0; z < 2; z++)
1898 VOLUME(icode, &ptr, playback + z, z, gpr + z);
1899 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1902 /* Wave Surround Playback Volume */
1903 for (z = 0; z < 2; z++)
1904 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1905 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1908 /* Wave Center/LFE Playback Volume */
1909 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1910 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
1911 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
1912 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
1913 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
1914 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
1916 /* Wave Capture Volume + Switch */
1917 for (z = 0; z < 2; z++) {
1918 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
1919 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
1921 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
1922 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
1925 /* Synth Playback Volume */
1926 for (z = 0; z < 2; z++)
1927 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
1928 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
1931 /* Synth Capture Volume + Switch */
1932 for (z = 0; z < 2; z++) {
1933 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
1934 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1936 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
1937 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
1940 /* Surround Digital Playback Volume (renamed later without Digital) */
1941 for (z = 0; z < 2; z++)
1942 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
1943 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
1946 /* Surround Capture Volume + Switch */
1947 for (z = 0; z < 2; z++) {
1948 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
1949 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1951 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
1952 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
1955 /* Center Playback Volume (renamed later without Digital) */
1956 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
1957 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
1959 /* LFE Playback Volume + Switch (renamed later without Digital) */
1960 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
1961 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
1963 /* Front Playback Volume */
1964 for (z = 0; z < 2; z++)
1965 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
1966 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
1969 /* Front Capture Volume + Switch */
1970 for (z = 0; z < 2; z++) {
1971 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
1972 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1974 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
1975 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
1982 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
1983 /* AC'97 Playback Volume */
1984 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
1985 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
1986 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
1987 /* AC'97 Capture Volume */
1988 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
1989 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
1990 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
1993 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
1994 /* IEC958 TTL Playback Volume */
1995 for (z = 0; z < 2; z++)
1996 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
1997 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2000 /* IEC958 TTL Capture Volume + Switch */
2001 for (z = 0; z < 2; z++) {
2002 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2003 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2005 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2006 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2010 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2011 /* Zoom Video Playback Volume */
2012 for (z = 0; z < 2; z++)
2013 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2014 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2017 /* Zoom Video Capture Volume + Switch */
2018 for (z = 0; z < 2; z++) {
2019 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2020 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2022 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2023 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2027 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2028 /* IEC958 Optical Playback Volume */
2029 for (z = 0; z < 2; z++)
2030 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2031 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2034 /* IEC958 Optical Capture Volume */
2035 for (z = 0; z < 2; z++) {
2036 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2037 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2039 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2040 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2044 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2045 /* Line LiveDrive Playback Volume */
2046 for (z = 0; z < 2; z++)
2047 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2048 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2051 /* Line LiveDrive Capture Volume + Switch */
2052 for (z = 0; z < 2; z++) {
2053 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2054 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2056 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2057 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2061 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2062 /* IEC958 Coax Playback Volume */
2063 for (z = 0; z < 2; z++)
2064 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2065 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2068 /* IEC958 Coax Capture Volume + Switch */
2069 for (z = 0; z < 2; z++) {
2070 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2071 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2073 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2074 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2078 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2079 /* Line LiveDrive Playback Volume */
2080 for (z = 0; z < 2; z++)
2081 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2082 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2083 controls[i-1].id.index = 1;
2086 /* Line LiveDrive Capture Volume */
2087 for (z = 0; z < 2; z++) {
2088 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2089 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2091 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2092 controls[i-1].id.index = 1;
2093 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2094 controls[i-1].id.index = 1;
2099 * Process tone control
2101 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
2102 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
2103 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
2104 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
2105 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
2106 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
2108 ctl = &controls[i + 0];
2109 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2110 strcpy(ctl->id.name, "Tone Control - Bass");
2115 ctl->value[0] = ctl->value[1] = 20;
2116 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2117 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2118 ctl = &controls[i + 1];
2119 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2120 strcpy(ctl->id.name, "Tone Control - Treble");
2125 ctl->value[0] = ctl->value[1] = 20;
2126 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2127 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2129 #define BASS_GPR 0x8c
2130 #define TREBLE_GPR 0x96
2132 for (z = 0; z < 5; z++) {
2134 for (j = 0; j < 2; j++) {
2135 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2136 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2139 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
2141 for (j = 0; j < 2; j++) { /* left/right */
2142 k = 0xa0 + (z * 8) + (j * 4);
2143 l = 0xd0 + (z * 8) + (j * 4);
2144 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
2146 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2147 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2148 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2149 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2150 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2151 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2153 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2154 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2155 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2156 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2157 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2158 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2160 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2162 if (z == 2) /* center */
2171 for (z = 0; z < 6; z++) {
2172 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
2173 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
2174 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2175 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2177 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2183 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2184 /* AC'97 Playback Volume */
2186 for (z = 0; z < 2; z++)
2187 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
2190 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2191 /* IEC958 Optical Raw Playback Switch */
2193 for (z = 0; z < 2; z++) {
2194 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2195 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2196 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2197 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2198 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2199 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2203 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2207 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2208 /* Headphone Playback Volume */
2210 for (z = 0; z < 2; z++) {
2211 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
2212 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2213 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2214 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2215 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2218 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2219 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
2220 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2221 controls[i-1].id.index = 1;
2222 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2223 controls[i-1].id.index = 1;
2228 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2229 for (z = 0; z < 2; z++)
2230 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2232 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2233 for (z = 0; z < 2; z++)
2234 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2236 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2237 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2238 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2239 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2241 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2242 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2246 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2247 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2248 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2249 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2251 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2252 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2256 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2257 for (z = 0; z < 2; z++)
2258 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2261 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2262 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2264 /* EFX capture - capture the 16 EXTINS */
2265 if (emu->card_capabilities->sblive51) {
2266 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
2267 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
2269 * Since only 14 of the 16 EXTINs are used, this is not a big problem.
2270 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
2271 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
2272 * channel. Multitrack recorders will still see the center/lfe output signal
2273 * on the second and third channels.
2275 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
2276 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
2277 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
2278 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
2279 for (z = 4; z < 14; z++)
2280 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2282 for (z = 0; z < 16; z++)
2283 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2292 if (i > SND_EMU10K1_GPR_CONTROLS) {
2298 /* clear remaining instruction memory */
2300 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2302 if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
2304 icode->gpr_add_control_count = i;
2305 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
2306 emu->support_tlv = 1; /* support TLV */
2307 err = snd_emu10k1_icode_poke(emu, icode, true);
2308 emu->support_tlv = 0; /* clear again */
2310 err = snd_emu10k1_ipcm_poke(emu, ipcm);
2316 kfree((void __force *)icode->gpr_map);
2322 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2324 spin_lock_init(&emu->fx8010.irq_lock);
2325 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2327 return _snd_emu10k1_audigy_init_efx(emu);
2329 return _snd_emu10k1_init_efx(emu);
2332 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2334 /* stop processor */
2336 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2338 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2341 #if 0 /* FIXME: who use them? */
2342 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2344 if (output < 0 || output >= 6)
2346 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2350 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2352 if (output < 0 || output >= 6)
2354 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2359 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2363 /* size is in samples */
2365 size = (size - 1) >> 13;
2371 size = 0x2000 << size_reg;
2373 if ((emu->fx8010.etram_pages.bytes / 2) == size)
2375 spin_lock_irq(&emu->emu_lock);
2376 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2377 spin_unlock_irq(&emu->emu_lock);
2378 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2379 snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
2380 if (emu->fx8010.etram_pages.area != NULL) {
2381 snd_dma_free_pages(&emu->fx8010.etram_pages);
2382 emu->fx8010.etram_pages.area = NULL;
2383 emu->fx8010.etram_pages.bytes = 0;
2387 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
2388 size * 2, &emu->fx8010.etram_pages) < 0)
2390 memset(emu->fx8010.etram_pages.area, 0, size * 2);
2391 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2392 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2393 spin_lock_irq(&emu->emu_lock);
2394 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2395 spin_unlock_irq(&emu->emu_lock);
2401 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2406 static void copy_string(char *dst, char *src, char *null, int idx)
2409 sprintf(dst, "%s %02X", null, idx);
2414 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2415 struct snd_emu10k1_fx8010_info *info)
2417 char **fxbus, **extin, **extout;
2418 unsigned short fxbus_mask, extin_mask, extout_mask;
2421 info->internal_tram_size = emu->fx8010.itram_size;
2422 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2424 extin = emu->audigy ? audigy_ins : creative_ins;
2425 extout = emu->audigy ? audigy_outs : creative_outs;
2426 fxbus_mask = emu->fx8010.fxbus_mask;
2427 extin_mask = emu->fx8010.extin_mask;
2428 extout_mask = emu->fx8010.extout_mask;
2429 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2430 copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
2431 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2432 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2434 for (res = 16; res < 32; res++, extout++)
2435 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2436 info->gpr_controls = emu->fx8010.gpr_count;
2439 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2441 struct snd_emu10k1 *emu = hw->private_data;
2442 struct snd_emu10k1_fx8010_info *info;
2443 struct snd_emu10k1_fx8010_code *icode;
2444 struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2446 void __user *argp = (void __user *)arg;
2450 case SNDRV_EMU10K1_IOCTL_PVERSION:
2451 emu->support_tlv = 1;
2452 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2453 case SNDRV_EMU10K1_IOCTL_INFO:
2454 info = kzalloc(sizeof(*info), GFP_KERNEL);
2457 snd_emu10k1_fx8010_info(emu, info);
2458 if (copy_to_user(argp, info, sizeof(*info))) {
2464 case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2465 if (!capable(CAP_SYS_ADMIN))
2468 icode = memdup_user(argp, sizeof(*icode));
2470 return PTR_ERR(icode);
2471 res = snd_emu10k1_icode_poke(emu, icode, false);
2474 case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2475 icode = memdup_user(argp, sizeof(*icode));
2477 return PTR_ERR(icode);
2478 res = snd_emu10k1_icode_peek(emu, icode);
2479 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2485 case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2486 ipcm = memdup_user(argp, sizeof(*ipcm));
2488 return PTR_ERR(ipcm);
2489 res = snd_emu10k1_ipcm_poke(emu, ipcm);
2492 case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2493 ipcm = memdup_user(argp, sizeof(*ipcm));
2495 return PTR_ERR(ipcm);
2496 res = snd_emu10k1_ipcm_peek(emu, ipcm);
2497 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2503 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2504 if (!capable(CAP_SYS_ADMIN))
2506 if (get_user(addr, (unsigned int __user *)argp))
2508 mutex_lock(&emu->fx8010.lock);
2509 res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2510 mutex_unlock(&emu->fx8010.lock);
2512 case SNDRV_EMU10K1_IOCTL_STOP:
2513 if (!capable(CAP_SYS_ADMIN))
2516 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2518 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2520 case SNDRV_EMU10K1_IOCTL_CONTINUE:
2521 if (!capable(CAP_SYS_ADMIN))
2524 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2526 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2528 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2529 if (!capable(CAP_SYS_ADMIN))
2532 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2534 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2537 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2539 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2541 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2542 if (!capable(CAP_SYS_ADMIN))
2544 if (get_user(addr, (unsigned int __user *)argp))
2549 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
2551 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
2554 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
2556 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
2558 case SNDRV_EMU10K1_IOCTL_DBG_READ:
2560 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2562 addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2563 if (put_user(addr, (unsigned int __user *)argp))
2570 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2575 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2577 struct snd_hwdep *hw;
2580 if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
2582 strcpy(hw->name, "EMU10K1 (FX8010)");
2583 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2584 hw->ops.open = snd_emu10k1_fx8010_open;
2585 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2586 hw->ops.release = snd_emu10k1_fx8010_release;
2587 hw->private_data = emu;
2591 #ifdef CONFIG_PM_SLEEP
2592 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2596 len = emu->audigy ? 0x200 : 0x100;
2597 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
2598 if (! emu->saved_gpr)
2600 len = emu->audigy ? 0x100 : 0xa0;
2601 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
2602 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
2603 if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2605 len = emu->audigy ? 2 * 1024 : 2 * 512;
2606 emu->saved_icode = vmalloc(array_size(len, 4));
2607 if (! emu->saved_icode)
2612 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2614 kfree(emu->saved_gpr);
2615 kfree(emu->tram_val_saved);
2616 kfree(emu->tram_addr_saved);
2617 vfree(emu->saved_icode);
2621 * save/restore GPR, TRAM and codes
2623 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2627 len = emu->audigy ? 0x200 : 0x100;
2628 for (i = 0; i < len; i++)
2629 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2631 len = emu->audigy ? 0x100 : 0xa0;
2632 for (i = 0; i < len; i++) {
2633 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2634 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2636 emu->tram_addr_saved[i] >>= 12;
2637 emu->tram_addr_saved[i] |=
2638 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2642 len = emu->audigy ? 2 * 1024 : 2 * 512;
2643 for (i = 0; i < len; i++)
2644 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2647 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2652 if (emu->fx8010.etram_pages.bytes > 0) {
2653 unsigned size, size_reg = 0;
2654 size = emu->fx8010.etram_pages.bytes / 2;
2655 size = (size - 1) >> 13;
2660 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2661 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2662 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2663 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2667 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2669 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2671 len = emu->audigy ? 0x200 : 0x100;
2672 for (i = 0; i < len; i++)
2673 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2675 len = emu->audigy ? 0x100 : 0xa0;
2676 for (i = 0; i < len; i++) {
2677 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2678 emu->tram_val_saved[i]);
2680 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2681 emu->tram_addr_saved[i]);
2683 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2684 emu->tram_addr_saved[i] << 12);
2685 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2686 emu->tram_addr_saved[i] >> 20);
2690 len = emu->audigy ? 2 * 1024 : 2 * 512;
2691 for (i = 0; i < len; i++)
2692 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2694 /* start FX processor when the DSP code is updated */
2696 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2698 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);