2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Routines for effect processor FX8010
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added EMU 1010 support.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/pci.h>
32 #include <linux/capability.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/init.h>
37 #include <linux/mutex.h>
38 #include <linux/moduleparam.h>
39 #include <linux/nospec.h>
41 #include <sound/core.h>
42 #include <sound/tlv.h>
43 #include <sound/emu10k1.h>
45 #if 0 /* for testing purposes - digital out -> capture */
46 #define EMU10K1_CAPTURE_DIGITAL_OUT
48 #if 0 /* for testing purposes - set S/PDIF to AC3 output */
49 #define EMU10K1_SET_AC3_IEC958
51 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
52 #define EMU10K1_CENTER_LFE_FROM_FRONT
55 static bool high_res_gpr_volume;
56 module_param(high_res_gpr_volume, bool, 0444);
57 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
63 static char *fxbuses[16] = {
64 /* 0x00 */ "PCM Left",
65 /* 0x01 */ "PCM Right",
66 /* 0x02 */ "PCM Surround Left",
67 /* 0x03 */ "PCM Surround Right",
68 /* 0x04 */ "MIDI Left",
69 /* 0x05 */ "MIDI Right",
76 /* 0x0c */ "MIDI Reverb",
77 /* 0x0d */ "MIDI Chorus",
82 static char *creative_ins[16] = {
83 /* 0x00 */ "AC97 Left",
84 /* 0x01 */ "AC97 Right",
85 /* 0x02 */ "TTL IEC958 Left",
86 /* 0x03 */ "TTL IEC958 Right",
87 /* 0x04 */ "Zoom Video Left",
88 /* 0x05 */ "Zoom Video Right",
89 /* 0x06 */ "Optical IEC958 Left",
90 /* 0x07 */ "Optical IEC958 Right",
91 /* 0x08 */ "Line/Mic 1 Left",
92 /* 0x09 */ "Line/Mic 1 Right",
93 /* 0x0a */ "Coaxial IEC958 Left",
94 /* 0x0b */ "Coaxial IEC958 Right",
95 /* 0x0c */ "Line/Mic 2 Left",
96 /* 0x0d */ "Line/Mic 2 Right",
101 static char *audigy_ins[16] = {
102 /* 0x00 */ "AC97 Left",
103 /* 0x01 */ "AC97 Right",
104 /* 0x02 */ "Audigy CD Left",
105 /* 0x03 */ "Audigy CD Right",
106 /* 0x04 */ "Optical IEC958 Left",
107 /* 0x05 */ "Optical IEC958 Right",
110 /* 0x08 */ "Line/Mic 2 Left",
111 /* 0x09 */ "Line/Mic 2 Right",
112 /* 0x0a */ "SPDIF Left",
113 /* 0x0b */ "SPDIF Right",
114 /* 0x0c */ "Aux2 Left",
115 /* 0x0d */ "Aux2 Right",
120 static char *creative_outs[32] = {
121 /* 0x00 */ "AC97 Left",
122 /* 0x01 */ "AC97 Right",
123 /* 0x02 */ "Optical IEC958 Left",
124 /* 0x03 */ "Optical IEC958 Right",
127 /* 0x06 */ "Headphone Left",
128 /* 0x07 */ "Headphone Right",
129 /* 0x08 */ "Surround Left",
130 /* 0x09 */ "Surround Right",
131 /* 0x0a */ "PCM Capture Left",
132 /* 0x0b */ "PCM Capture Right",
133 /* 0x0c */ "MIC Capture",
134 /* 0x0d */ "AC97 Surround Left",
135 /* 0x0e */ "AC97 Surround Right",
138 /* 0x11 */ "Analog Center",
139 /* 0x12 */ "Analog LFE",
155 static char *audigy_outs[32] = {
156 /* 0x00 */ "Digital Front Left",
157 /* 0x01 */ "Digital Front Right",
158 /* 0x02 */ "Digital Center",
159 /* 0x03 */ "Digital LEF",
160 /* 0x04 */ "Headphone Left",
161 /* 0x05 */ "Headphone Right",
162 /* 0x06 */ "Digital Rear Left",
163 /* 0x07 */ "Digital Rear Right",
164 /* 0x08 */ "Front Left",
165 /* 0x09 */ "Front Right",
170 /* 0x0e */ "Rear Left",
171 /* 0x0f */ "Rear Right",
172 /* 0x10 */ "AC97 Front Left",
173 /* 0x11 */ "AC97 Front Right",
174 /* 0x12 */ "ADC Caputre Left",
175 /* 0x13 */ "ADC Capture Right",
190 static const u32 bass_table[41][5] = {
191 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
192 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
193 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
194 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
195 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
196 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
197 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
198 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
199 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
200 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
201 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
202 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
203 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
204 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
205 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
206 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
207 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
208 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
209 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
210 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
211 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
212 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
213 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
214 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
215 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
216 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
217 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
218 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
219 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
220 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
221 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
222 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
223 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
224 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
225 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
226 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
227 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
228 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
229 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
230 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
231 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
234 static const u32 treble_table[41][5] = {
235 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
236 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
237 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
238 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
239 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
240 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
241 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
242 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
243 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
244 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
245 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
246 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
247 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
248 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
249 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
250 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
251 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
252 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
253 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
254 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
255 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
256 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
257 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
258 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
259 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
260 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
261 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
262 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
263 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
264 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
265 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
266 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
267 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
268 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
269 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
270 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
271 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
272 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
273 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
274 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
275 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
278 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
279 static const u32 db_table[101] = {
280 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
281 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
282 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
283 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
284 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
285 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
286 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
287 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
288 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
289 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
290 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
291 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
292 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
293 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
294 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
295 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
296 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
297 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
298 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
299 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
303 /* EMU10k1/EMU10k2 DSP control db gain */
304 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
305 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
307 /* EMU10K1 bass/treble db gain */
308 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
310 static const u32 onoff_table[2] = {
311 0x00000000, 0x00000001
317 static inline mm_segment_t snd_enter_user(void)
319 mm_segment_t fs = get_fs();
324 static inline void snd_leave_user(mm_segment_t fs)
333 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
335 struct snd_emu10k1_fx8010_ctl *ctl =
336 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
338 if (ctl->min == 0 && ctl->max == 1)
339 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
341 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
342 uinfo->count = ctl->vcount;
343 uinfo->value.integer.min = ctl->min;
344 uinfo->value.integer.max = ctl->max;
348 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
350 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
351 struct snd_emu10k1_fx8010_ctl *ctl =
352 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
356 spin_lock_irqsave(&emu->reg_lock, flags);
357 for (i = 0; i < ctl->vcount; i++)
358 ucontrol->value.integer.value[i] = ctl->value[i];
359 spin_unlock_irqrestore(&emu->reg_lock, flags);
363 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
365 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
366 struct snd_emu10k1_fx8010_ctl *ctl =
367 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
369 unsigned int nval, val;
373 spin_lock_irqsave(&emu->reg_lock, flags);
374 for (i = 0; i < ctl->vcount; i++) {
375 nval = ucontrol->value.integer.value[i];
380 if (nval != ctl->value[i])
382 val = ctl->value[i] = nval;
383 switch (ctl->translation) {
384 case EMU10K1_GPR_TRANSLATION_NONE:
385 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
387 case EMU10K1_GPR_TRANSLATION_TABLE100:
388 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
390 case EMU10K1_GPR_TRANSLATION_BASS:
391 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
395 for (j = 0; j < 5; j++)
396 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
398 case EMU10K1_GPR_TRANSLATION_TREBLE:
399 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
403 for (j = 0; j < 5; j++)
404 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
406 case EMU10K1_GPR_TRANSLATION_ONOFF:
407 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
412 spin_unlock_irqrestore(&emu->reg_lock, flags);
420 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
422 struct snd_emu10k1_fx8010_irq *irq, *nirq;
424 irq = emu->fx8010.irq_handlers;
426 nirq = irq->next; /* irq ptr can be removed from list */
427 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
429 irq->handler(emu, irq->private_data);
430 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
436 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
437 snd_fx8010_irq_handler_t *handler,
438 unsigned char gpr_running,
440 struct snd_emu10k1_fx8010_irq **r_irq)
442 struct snd_emu10k1_fx8010_irq *irq;
445 irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
448 irq->handler = handler;
449 irq->gpr_running = gpr_running;
450 irq->private_data = private_data;
452 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
453 if (emu->fx8010.irq_handlers == NULL) {
454 emu->fx8010.irq_handlers = irq;
455 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
456 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
458 irq->next = emu->fx8010.irq_handlers;
459 emu->fx8010.irq_handlers = irq;
461 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
467 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
468 struct snd_emu10k1_fx8010_irq *irq)
470 struct snd_emu10k1_fx8010_irq *tmp;
473 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
474 if ((tmp = emu->fx8010.irq_handlers) == irq) {
475 emu->fx8010.irq_handlers = tmp->next;
476 if (emu->fx8010.irq_handlers == NULL) {
477 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
478 emu->dsp_interrupt = NULL;
481 while (tmp && tmp->next != irq)
484 tmp->next = tmp->next->next;
486 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
491 /*************************************************************************
492 * EMU10K1 effect manager
493 *************************************************************************/
495 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
497 u32 op, u32 r, u32 a, u32 x, u32 y)
500 if (snd_BUG_ON(*ptr >= 512))
502 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
503 set_bit(*ptr, icode->code_valid);
504 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
505 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
509 #define OP(icode, ptr, op, r, a, x, y) \
510 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
512 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
514 u32 op, u32 r, u32 a, u32 x, u32 y)
517 if (snd_BUG_ON(*ptr >= 1024))
519 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
520 set_bit(*ptr, icode->code_valid);
521 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
522 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
526 #define A_OP(icode, ptr, op, r, a, x, y) \
527 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
529 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
531 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
532 snd_emu10k1_ptr_write(emu, pc, 0, data);
535 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
537 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
538 return snd_emu10k1_ptr_read(emu, pc, 0);
541 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
542 struct snd_emu10k1_fx8010_code *icode)
547 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
548 if (!test_bit(gpr, icode->gpr_valid))
550 if (get_user(val, &icode->gpr_map[gpr]))
552 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
557 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
558 struct snd_emu10k1_fx8010_code *icode)
563 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
564 set_bit(gpr, icode->gpr_valid);
565 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
566 if (put_user(val, &icode->gpr_map[gpr]))
572 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
573 struct snd_emu10k1_fx8010_code *icode)
578 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
579 if (!test_bit(tram, icode->tram_valid))
581 if (get_user(val, &icode->tram_data_map[tram]) ||
582 get_user(addr, &icode->tram_addr_map[tram]))
584 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
586 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
588 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
589 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
595 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
596 struct snd_emu10k1_fx8010_code *icode)
601 memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
602 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
603 set_bit(tram, icode->tram_valid);
604 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
606 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
608 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
609 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
611 if (put_user(val, &icode->tram_data_map[tram]) ||
612 put_user(addr, &icode->tram_addr_map[tram]))
618 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
619 struct snd_emu10k1_fx8010_code *icode)
623 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
624 if (!test_bit(pc / 2, icode->code_valid))
626 if (get_user(lo, &icode->code[pc + 0]) ||
627 get_user(hi, &icode->code[pc + 1]))
629 snd_emu10k1_efx_write(emu, pc + 0, lo);
630 snd_emu10k1_efx_write(emu, pc + 1, hi);
635 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
636 struct snd_emu10k1_fx8010_code *icode)
640 memset(icode->code_valid, 0, sizeof(icode->code_valid));
641 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
642 set_bit(pc / 2, icode->code_valid);
643 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
645 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
651 static struct snd_emu10k1_fx8010_ctl *
652 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
654 struct snd_emu10k1_fx8010_ctl *ctl;
655 struct snd_kcontrol *kcontrol;
657 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
658 kcontrol = ctl->kcontrol;
659 if (kcontrol->id.iface == id->iface &&
660 !strcmp(kcontrol->id.name, id->name) &&
661 kcontrol->id.index == id->index)
667 #define MAX_TLV_SIZE 256
669 static unsigned int *copy_tlv(const unsigned int __user *_tlv)
671 unsigned int data[2];
676 if (copy_from_user(data, _tlv, sizeof(data)))
678 if (data[1] >= MAX_TLV_SIZE)
680 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
683 memcpy(tlv, data, sizeof(data));
684 if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
691 static int copy_gctl(struct snd_emu10k1 *emu,
692 struct snd_emu10k1_fx8010_control_gpr *gctl,
693 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
696 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
698 if (emu->support_tlv)
699 return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
700 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
701 if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
707 static int copy_gctl_to_user(struct snd_emu10k1 *emu,
708 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
709 struct snd_emu10k1_fx8010_control_gpr *gctl,
712 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
714 if (emu->support_tlv)
715 return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
717 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
718 return copy_to_user(&octl[idx], gctl, sizeof(*octl));
721 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
722 struct snd_emu10k1_fx8010_code *icode)
725 struct snd_ctl_elem_id __user *_id;
726 struct snd_ctl_elem_id id;
727 struct snd_emu10k1_fx8010_control_gpr *gctl;
730 for (i = 0, _id = icode->gpr_del_controls;
731 i < icode->gpr_del_control_count; i++, _id++) {
732 if (copy_from_user(&id, _id, sizeof(id)))
734 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
737 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
741 for (i = 0; i < icode->gpr_add_control_count; i++) {
742 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
746 if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
748 down_read(&emu->card->controls_rwsem);
749 if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
750 up_read(&emu->card->controls_rwsem);
754 up_read(&emu->card->controls_rwsem);
755 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
756 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
761 for (i = 0; i < icode->gpr_list_control_count; i++) {
762 /* FIXME: we need to check the WRITE access */
763 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i)) {
773 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
775 struct snd_emu10k1_fx8010_ctl *ctl;
777 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
778 kctl->private_value = 0;
779 list_del(&ctl->list);
784 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
785 struct snd_emu10k1_fx8010_code *icode)
788 struct snd_emu10k1_fx8010_control_gpr *gctl;
789 struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
790 struct snd_kcontrol_new knew;
791 struct snd_kcontrol *kctl;
792 struct snd_ctl_elem_value *val;
795 val = kmalloc(sizeof(*val), GFP_KERNEL);
796 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
797 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
798 if (!val || !gctl || !nctl) {
803 for (i = 0; i < icode->gpr_add_control_count; i++) {
804 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
808 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
809 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
813 if (! gctl->id.name[0]) {
817 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
818 memset(&knew, 0, sizeof(knew));
819 knew.iface = gctl->id.iface;
820 knew.name = gctl->id.name;
821 knew.index = gctl->id.index;
822 knew.device = gctl->id.device;
823 knew.subdevice = gctl->id.subdevice;
824 knew.info = snd_emu10k1_gpr_ctl_info;
825 knew.tlv.p = copy_tlv(gctl->tlv);
827 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
828 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
829 knew.get = snd_emu10k1_gpr_ctl_get;
830 knew.put = snd_emu10k1_gpr_ctl_put;
831 memset(nctl, 0, sizeof(*nctl));
832 nctl->vcount = gctl->vcount;
833 nctl->count = gctl->count;
834 for (j = 0; j < 32; j++) {
835 nctl->gpr[j] = gctl->gpr[j];
836 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
837 val->value.integer.value[j] = gctl->value[j];
839 nctl->min = gctl->min;
840 nctl->max = gctl->max;
841 nctl->translation = gctl->translation;
843 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
849 knew.private_value = (unsigned long)ctl;
851 if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
856 kctl->private_free = snd_emu10k1_ctl_private_free;
857 ctl->kcontrol = kctl;
858 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
861 nctl->list = ctl->list;
862 nctl->kcontrol = ctl->kcontrol;
864 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
865 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
867 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
876 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
877 struct snd_emu10k1_fx8010_code *icode)
880 struct snd_ctl_elem_id id;
881 struct snd_ctl_elem_id __user *_id;
882 struct snd_emu10k1_fx8010_ctl *ctl;
883 struct snd_card *card = emu->card;
885 for (i = 0, _id = icode->gpr_del_controls;
886 i < icode->gpr_del_control_count; i++, _id++) {
887 if (copy_from_user(&id, _id, sizeof(id)))
889 down_write(&card->controls_rwsem);
890 ctl = snd_emu10k1_look_for_ctl(emu, &id);
892 snd_ctl_remove(card, ctl->kcontrol);
893 up_write(&card->controls_rwsem);
898 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
899 struct snd_emu10k1_fx8010_code *icode)
901 unsigned int i = 0, j;
902 unsigned int total = 0;
903 struct snd_emu10k1_fx8010_control_gpr *gctl;
904 struct snd_emu10k1_fx8010_ctl *ctl;
905 struct snd_ctl_elem_id *id;
907 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
911 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
913 if (icode->gpr_list_controls &&
914 i < icode->gpr_list_control_count) {
915 memset(gctl, 0, sizeof(*gctl));
916 id = &ctl->kcontrol->id;
917 gctl->id.iface = id->iface;
918 strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
919 gctl->id.index = id->index;
920 gctl->id.device = id->device;
921 gctl->id.subdevice = id->subdevice;
922 gctl->vcount = ctl->vcount;
923 gctl->count = ctl->count;
924 for (j = 0; j < 32; j++) {
925 gctl->gpr[j] = ctl->gpr[j];
926 gctl->value[j] = ctl->value[j];
928 gctl->min = ctl->min;
929 gctl->max = ctl->max;
930 gctl->translation = ctl->translation;
931 if (copy_gctl_to_user(emu, icode->gpr_list_controls,
939 icode->gpr_list_control_total = total;
944 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
945 struct snd_emu10k1_fx8010_code *icode)
949 mutex_lock(&emu->fx8010.lock);
950 if ((err = snd_emu10k1_verify_controls(emu, icode)) < 0)
952 strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
953 /* stop FX processor - this may be dangerous, but it's better to miss
954 some samples than generate wrong ones - [jk] */
956 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
958 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
959 /* ok, do the main job */
960 if ((err = snd_emu10k1_del_controls(emu, icode)) < 0 ||
961 (err = snd_emu10k1_gpr_poke(emu, icode)) < 0 ||
962 (err = snd_emu10k1_tram_poke(emu, icode)) < 0 ||
963 (err = snd_emu10k1_code_poke(emu, icode)) < 0 ||
964 (err = snd_emu10k1_add_controls(emu, icode)) < 0)
966 /* start FX processor when the DSP code is updated */
968 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
970 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
972 mutex_unlock(&emu->fx8010.lock);
976 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
977 struct snd_emu10k1_fx8010_code *icode)
981 mutex_lock(&emu->fx8010.lock);
982 strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
983 /* ok, do the main job */
984 err = snd_emu10k1_gpr_peek(emu, icode);
986 err = snd_emu10k1_tram_peek(emu, icode);
988 err = snd_emu10k1_code_peek(emu, icode);
990 err = snd_emu10k1_list_controls(emu, icode);
991 mutex_unlock(&emu->fx8010.lock);
995 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
996 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1000 struct snd_emu10k1_fx8010_pcm *pcm;
1002 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1004 ipcm->substream = array_index_nospec(ipcm->substream,
1005 EMU10K1_FX8010_PCM_COUNT);
1006 if (ipcm->channels > 32)
1008 pcm = &emu->fx8010.pcm[ipcm->substream];
1009 mutex_lock(&emu->fx8010.lock);
1010 spin_lock_irq(&emu->reg_lock);
1015 if (ipcm->channels == 0) { /* remove */
1018 /* FIXME: we need to add universal code to the PCM transfer routine */
1019 if (ipcm->channels != 2) {
1025 pcm->channels = ipcm->channels;
1026 pcm->tram_start = ipcm->tram_start;
1027 pcm->buffer_size = ipcm->buffer_size;
1028 pcm->gpr_size = ipcm->gpr_size;
1029 pcm->gpr_count = ipcm->gpr_count;
1030 pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1031 pcm->gpr_ptr = ipcm->gpr_ptr;
1032 pcm->gpr_trigger = ipcm->gpr_trigger;
1033 pcm->gpr_running = ipcm->gpr_running;
1034 for (i = 0; i < pcm->channels; i++)
1035 pcm->etram[i] = ipcm->etram[i];
1038 spin_unlock_irq(&emu->reg_lock);
1039 mutex_unlock(&emu->fx8010.lock);
1043 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1044 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1048 struct snd_emu10k1_fx8010_pcm *pcm;
1050 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1052 ipcm->substream = array_index_nospec(ipcm->substream,
1053 EMU10K1_FX8010_PCM_COUNT);
1054 pcm = &emu->fx8010.pcm[ipcm->substream];
1055 mutex_lock(&emu->fx8010.lock);
1056 spin_lock_irq(&emu->reg_lock);
1057 ipcm->channels = pcm->channels;
1058 ipcm->tram_start = pcm->tram_start;
1059 ipcm->buffer_size = pcm->buffer_size;
1060 ipcm->gpr_size = pcm->gpr_size;
1061 ipcm->gpr_ptr = pcm->gpr_ptr;
1062 ipcm->gpr_count = pcm->gpr_count;
1063 ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1064 ipcm->gpr_trigger = pcm->gpr_trigger;
1065 ipcm->gpr_running = pcm->gpr_running;
1066 for (i = 0; i < pcm->channels; i++)
1067 ipcm->etram[i] = pcm->etram[i];
1068 ipcm->res1 = ipcm->res2 = 0;
1070 spin_unlock_irq(&emu->reg_lock);
1071 mutex_unlock(&emu->fx8010.lock);
1075 #define SND_EMU10K1_GPR_CONTROLS 44
1076 #define SND_EMU10K1_INPUTS 12
1077 #define SND_EMU10K1_PLAYBACK_CHANNELS 8
1078 #define SND_EMU10K1_CAPTURE_CHANNELS 4
1081 snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1082 const char *name, int gpr, int defval)
1084 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1085 strcpy(ctl->id.name, name);
1086 ctl->vcount = ctl->count = 1;
1087 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1088 if (high_res_gpr_volume) {
1090 ctl->max = 0x7fffffff;
1091 ctl->tlv = snd_emu10k1_db_linear;
1092 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1096 ctl->tlv = snd_emu10k1_db_scale1;
1097 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1102 snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1103 const char *name, int gpr, int defval)
1105 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1106 strcpy(ctl->id.name, name);
1107 ctl->vcount = ctl->count = 2;
1108 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1109 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1110 if (high_res_gpr_volume) {
1112 ctl->max = 0x7fffffff;
1113 ctl->tlv = snd_emu10k1_db_linear;
1114 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1118 ctl->tlv = snd_emu10k1_db_scale1;
1119 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1124 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1125 const char *name, int gpr, int defval)
1127 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1128 strcpy(ctl->id.name, name);
1129 ctl->vcount = ctl->count = 1;
1130 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1133 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1137 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1138 const char *name, int gpr, int defval)
1140 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1141 strcpy(ctl->id.name, name);
1142 ctl->vcount = ctl->count = 2;
1143 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1144 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1147 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1151 * Used for emu1010 - conversion from 32-bit capture inputs from HANA
1152 * to 2 x 16-bit registers in audigy - their values are read via DMA.
1153 * Conversion is performed by Audigy DSP instructions of FX8010.
1155 static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1156 struct snd_emu10k1_fx8010_code *icode,
1157 u32 *ptr, int tmp, int bit_shifter16,
1158 int reg_in, int reg_out)
1160 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
1161 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
1162 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
1163 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
1164 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
1165 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
1166 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
1167 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
1172 * initial DSP configuration for Audigy
1175 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1177 int err, i, z, gpr, nctl;
1179 const int playback = 10;
1180 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
1181 const int stereo_mix = capture + 2;
1182 const int tmp = 0x88;
1184 struct snd_emu10k1_fx8010_code *icode = NULL;
1185 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1190 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1194 icode->gpr_map = (u_int32_t __user *) kcalloc(512 + 256 + 256 + 2 * 1024,
1195 sizeof(u_int32_t), GFP_KERNEL);
1196 if (!icode->gpr_map)
1198 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1199 sizeof(*controls), GFP_KERNEL);
1203 gpr_map = (u32 __force *)icode->gpr_map;
1205 icode->tram_data_map = icode->gpr_map + 512;
1206 icode->tram_addr_map = icode->tram_data_map + 256;
1207 icode->code = icode->tram_addr_map + 256;
1209 /* clear free GPRs */
1210 for (i = 0; i < 512; i++)
1211 set_bit(i, icode->gpr_valid);
1213 /* clear TRAM data & address lines */
1214 for (i = 0; i < 256; i++)
1215 set_bit(i, icode->tram_valid);
1217 strcpy(icode->name, "Audigy DSP code for ALSA");
1220 gpr = stereo_mix + 10;
1221 gpr_map[gpr++] = 0x00007fff;
1222 gpr_map[gpr++] = 0x00008000;
1223 gpr_map[gpr++] = 0x0000ffff;
1224 bit_shifter16 = gpr;
1226 /* stop FX processor */
1227 snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
1230 /* PCM front Playback Volume (independent from stereo mix)
1231 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
1232 * where gpr contains attenuation from corresponding mixer control
1233 * (snd_emu10k1_init_stereo_control)
1235 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1236 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1237 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1240 /* PCM Surround Playback (independent from stereo mix) */
1241 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1242 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1243 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1246 /* PCM Side Playback (independent from stereo mix) */
1247 if (emu->card_capabilities->spk71) {
1248 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1249 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1250 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1254 /* PCM Center Playback (independent from stereo mix) */
1255 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1256 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1259 /* PCM LFE Playback (independent from stereo mix) */
1260 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1261 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1267 /* Wave (PCM) Playback Volume (will be renamed later) */
1268 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1269 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1270 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1273 /* Synth Playback */
1274 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1275 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1276 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1279 /* Wave (PCM) Capture */
1280 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1281 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1282 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1286 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1287 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1288 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1294 #define A_ADD_VOLUME_IN(var,vol,input) \
1295 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1297 /* emu1212 DSP 0 and DSP 1 Capture */
1298 if (emu->card_capabilities->emu_model) {
1299 if (emu->card_capabilities->ca0108_chip) {
1300 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
1301 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
1302 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
1303 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
1304 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
1306 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
1307 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
1309 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1312 /* AC'97 Playback Volume - used only for mic (renamed later) */
1313 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1314 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1315 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1317 /* AC'97 Capture Volume - used only for mic */
1318 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1319 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1320 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1323 /* mic capture buffer */
1324 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
1326 /* Audigy CD Playback Volume */
1327 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1328 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1329 snd_emu10k1_init_stereo_control(&controls[nctl++],
1330 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1333 /* Audigy CD Capture Volume */
1334 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1335 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1336 snd_emu10k1_init_stereo_control(&controls[nctl++],
1337 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1341 /* Optical SPDIF Playback Volume */
1342 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1343 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1344 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1346 /* Optical SPDIF Capture Volume */
1347 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1348 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1349 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1352 /* Line2 Playback Volume */
1353 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1354 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1355 snd_emu10k1_init_stereo_control(&controls[nctl++],
1356 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1359 /* Line2 Capture Volume */
1360 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1361 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1362 snd_emu10k1_init_stereo_control(&controls[nctl++],
1363 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1367 /* Philips ADC Playback Volume */
1368 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1369 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1370 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1372 /* Philips ADC Capture Volume */
1373 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1374 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1375 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1378 /* Aux2 Playback Volume */
1379 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1380 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1381 snd_emu10k1_init_stereo_control(&controls[nctl++],
1382 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1385 /* Aux2 Capture Volume */
1386 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1387 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1388 snd_emu10k1_init_stereo_control(&controls[nctl++],
1389 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1393 /* Stereo Mix Front Playback Volume */
1394 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1395 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1396 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1399 /* Stereo Mix Surround Playback */
1400 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1401 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1402 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1405 /* Stereo Mix Center Playback */
1406 /* Center = sub = Left/2 + Right/2 */
1407 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
1408 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1409 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1412 /* Stereo Mix LFE Playback */
1413 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1414 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1417 if (emu->card_capabilities->spk71) {
1418 /* Stereo Mix Side Playback */
1419 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1420 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1421 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1428 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1429 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1430 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1432 #define _A_SWITCH(icode, ptr, dst, src, sw) \
1433 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1434 #define A_SWITCH(icode, ptr, dst, src, sw) \
1435 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1436 #define _A_SWITCH_NEG(icode, ptr, dst, src) \
1437 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1438 #define A_SWITCH_NEG(icode, ptr, dst, src) \
1439 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1443 * Process tone control
1445 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
1446 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
1447 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
1448 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
1449 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
1450 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
1451 if (emu->card_capabilities->spk71) {
1452 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
1453 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
1457 ctl = &controls[nctl + 0];
1458 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1459 strcpy(ctl->id.name, "Tone Control - Bass");
1464 ctl->value[0] = ctl->value[1] = 20;
1465 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1466 ctl = &controls[nctl + 1];
1467 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1468 strcpy(ctl->id.name, "Tone Control - Treble");
1473 ctl->value[0] = ctl->value[1] = 20;
1474 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1476 #define BASS_GPR 0x8c
1477 #define TREBLE_GPR 0x96
1479 for (z = 0; z < 5; z++) {
1481 for (j = 0; j < 2; j++) {
1482 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
1483 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
1486 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
1488 for (j = 0; j < 2; j++) { /* left/right */
1489 k = 0xb0 + (z * 8) + (j * 4);
1490 l = 0xe0 + (z * 8) + (j * 4);
1491 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
1493 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
1494 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
1495 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
1496 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
1497 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
1498 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1500 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
1501 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
1502 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
1503 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
1504 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
1505 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1507 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1509 if (z == 2) /* center */
1518 for (z = 0; z < 8; z++) {
1519 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
1520 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
1521 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1522 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1524 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1527 /* Master volume (will be renamed later) */
1528 A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
1529 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
1530 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
1531 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
1532 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
1533 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
1534 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
1535 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
1536 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1539 /* analog speakers */
1540 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1541 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1542 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1543 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1544 if (emu->card_capabilities->spk71)
1545 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
1548 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1550 /* digital outputs */
1551 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
1552 if (emu->card_capabilities->emu_model) {
1553 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1554 dev_info(emu->card->dev, "EMU outputs on\n");
1555 for (z = 0; z < 8; z++) {
1556 if (emu->card_capabilities->ca0108_chip) {
1557 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1559 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1564 /* IEC958 Optical Raw Playback Switch */
1566 gpr_map[gpr++] = 0x1008;
1567 gpr_map[gpr++] = 0xffff0000;
1568 for (z = 0; z < 2; z++) {
1569 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1570 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1571 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1572 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1573 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1574 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1575 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
1576 if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1577 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1578 dev_info(emu->card->dev,
1579 "Installing spdif_bug patch: %s\n",
1580 emu->card_capabilities->name);
1581 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1582 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1584 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1587 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1590 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1591 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1592 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1595 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1596 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1598 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1599 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1602 if (emu->card_capabilities->emu_model) {
1603 if (emu->card_capabilities->ca0108_chip) {
1604 dev_info(emu->card->dev, "EMU2 inputs on\n");
1605 for (z = 0; z < 0x10; z++) {
1606 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
1612 dev_info(emu->card->dev, "EMU inputs on\n");
1613 /* Capture 16 (originally 8) channels of S32_LE sound */
1616 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1619 /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
1620 /* A_P16VIN(0) is delayed by one sample,
1621 * so all other A_P16VIN channels will need to also be delayed
1623 /* Left ADC in. 1 of 2 */
1624 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1625 /* Right ADC in 1 of 2 */
1626 gpr_map[gpr++] = 0x00000000;
1627 /* Delaying by one sample: instead of copying the input
1628 * value A_P16VIN to output A_FXBUS2 as in the first channel,
1629 * we use an auxiliary register, delaying the value by one
1632 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
1633 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
1634 gpr_map[gpr++] = 0x00000000;
1635 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
1636 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
1637 gpr_map[gpr++] = 0x00000000;
1638 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
1639 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
1640 /* For 96kHz mode */
1641 /* Left ADC in. 2 of 2 */
1642 gpr_map[gpr++] = 0x00000000;
1643 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
1644 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
1645 /* Right ADC in 2 of 2 */
1646 gpr_map[gpr++] = 0x00000000;
1647 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
1648 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
1649 gpr_map[gpr++] = 0x00000000;
1650 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
1651 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
1652 gpr_map[gpr++] = 0x00000000;
1653 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
1654 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
1655 /* Pavel Hofman - we still have voices, A_FXBUS2s, and
1656 * A_P16VINs available -
1657 * let's add 8 more capture channels - total of 16
1659 gpr_map[gpr++] = 0x00000000;
1660 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1664 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
1665 A_C_00000000, A_C_00000000);
1666 gpr_map[gpr++] = 0x00000000;
1667 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1671 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
1672 A_C_00000000, A_C_00000000);
1673 gpr_map[gpr++] = 0x00000000;
1674 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1678 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
1679 A_C_00000000, A_C_00000000);
1680 gpr_map[gpr++] = 0x00000000;
1681 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1685 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
1686 A_C_00000000, A_C_00000000);
1687 gpr_map[gpr++] = 0x00000000;
1688 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1692 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
1693 A_C_00000000, A_C_00000000);
1694 gpr_map[gpr++] = 0x00000000;
1695 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1699 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
1700 A_C_00000000, A_C_00000000);
1701 gpr_map[gpr++] = 0x00000000;
1702 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1706 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
1707 A_C_00000000, A_C_00000000);
1708 gpr_map[gpr++] = 0x00000000;
1709 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1713 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
1714 A_C_00000000, A_C_00000000);
1718 for (z = 4; z < 8; z++) {
1719 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1721 for (z = 0xc; z < 0x10; z++) {
1722 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1726 /* EFX capture - capture the 16 EXTINs */
1727 /* Capture 16 channels of S16_LE sound */
1728 for (z = 0; z < 16; z++) {
1729 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1733 #endif /* JCD test */
1743 /* clear remaining instruction memory */
1745 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1747 seg = snd_enter_user();
1748 icode->gpr_add_control_count = nctl;
1749 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
1750 emu->support_tlv = 1; /* support TLV */
1751 err = snd_emu10k1_icode_poke(emu, icode);
1752 emu->support_tlv = 0; /* clear again */
1753 snd_leave_user(seg);
1758 kfree((void __force *)icode->gpr_map);
1766 * initial DSP configuration for Emu10k1
1769 /* when volume = max, then copy only to avoid volume modification */
1770 /* with iMAC0 (negative values) */
1771 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1773 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1774 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1775 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
1776 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1778 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1780 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1781 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1782 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
1783 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1784 OP(icode, ptr, iMAC0, dst, dst, src, vol);
1786 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1788 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1789 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1790 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1791 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1792 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1795 #define VOLUME(icode, ptr, dst, src, vol) \
1796 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1797 #define VOLUME_IN(icode, ptr, dst, src, vol) \
1798 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1799 #define VOLUME_ADD(icode, ptr, dst, src, vol) \
1800 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1801 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1802 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1803 #define VOLUME_OUT(icode, ptr, dst, src, vol) \
1804 _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1805 #define _SWITCH(icode, ptr, dst, src, sw) \
1806 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1807 #define SWITCH(icode, ptr, dst, src, sw) \
1808 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1809 #define SWITCH_IN(icode, ptr, dst, src, sw) \
1810 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1811 #define _SWITCH_NEG(icode, ptr, dst, src) \
1812 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1813 #define SWITCH_NEG(icode, ptr, dst, src) \
1814 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1817 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1819 int err, i, z, gpr, tmp, playback, capture;
1821 struct snd_emu10k1_fx8010_code *icode;
1822 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1823 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1828 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1832 icode->gpr_map = (u_int32_t __user *) kcalloc(256 + 160 + 160 + 2 * 512,
1833 sizeof(u_int32_t), GFP_KERNEL);
1834 if (!icode->gpr_map)
1837 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1838 sizeof(struct snd_emu10k1_fx8010_control_gpr),
1843 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
1847 gpr_map = (u32 __force *)icode->gpr_map;
1849 icode->tram_data_map = icode->gpr_map + 256;
1850 icode->tram_addr_map = icode->tram_data_map + 160;
1851 icode->code = icode->tram_addr_map + 160;
1853 /* clear free GPRs */
1854 for (i = 0; i < 256; i++)
1855 set_bit(i, icode->gpr_valid);
1857 /* clear TRAM data & address lines */
1858 for (i = 0; i < 160; i++)
1859 set_bit(i, icode->tram_valid);
1861 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1863 /* we have 12 inputs */
1864 playback = SND_EMU10K1_INPUTS;
1865 /* we have 6 playback channels and tone control doubles */
1866 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
1867 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1868 tmp = 0x88; /* we need 4 temporary GPR */
1869 /* from 0x8c to 0xff is the area for tone control */
1871 /* stop FX processor */
1872 snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
1877 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
1878 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
1879 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
1880 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
1881 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
1882 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
1883 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
1884 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
1885 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
1886 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
1887 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
1888 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
1890 /* Raw S/PDIF PCM */
1891 ipcm->substream = 0;
1893 ipcm->tram_start = 0;
1894 ipcm->buffer_size = (64 * 1024) / 2;
1895 ipcm->gpr_size = gpr++;
1896 ipcm->gpr_ptr = gpr++;
1897 ipcm->gpr_count = gpr++;
1898 ipcm->gpr_tmpcount = gpr++;
1899 ipcm->gpr_trigger = gpr++;
1900 ipcm->gpr_running = gpr++;
1904 gpr_map[gpr + 0] = 0xfffff000;
1905 gpr_map[gpr + 1] = 0xffff0000;
1906 gpr_map[gpr + 2] = 0x70000000;
1907 gpr_map[gpr + 3] = 0x00000007;
1908 gpr_map[gpr + 4] = 0x001f << 11;
1909 gpr_map[gpr + 5] = 0x001c << 11;
1910 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
1911 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
1912 gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1913 gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1914 gpr_map[gpr + 10] = 1<<11;
1915 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
1916 gpr_map[gpr + 12] = 0;
1918 /* if the trigger flag is not set, skip */
1919 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1920 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1921 /* if the running flag is set, we're running */
1922 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1923 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1924 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1925 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1926 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1927 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1928 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1930 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1931 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1932 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1933 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1935 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1936 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1937 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1938 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1939 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1941 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1942 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1943 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1944 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1945 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1947 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1948 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1949 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1950 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1951 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1953 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1954 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1955 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1956 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1957 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1959 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1960 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1962 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1963 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1968 /* Wave Playback Volume */
1969 for (z = 0; z < 2; z++)
1970 VOLUME(icode, &ptr, playback + z, z, gpr + z);
1971 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1974 /* Wave Surround Playback Volume */
1975 for (z = 0; z < 2; z++)
1976 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1977 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1980 /* Wave Center/LFE Playback Volume */
1981 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1982 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
1983 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
1984 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
1985 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
1986 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
1988 /* Wave Capture Volume + Switch */
1989 for (z = 0; z < 2; z++) {
1990 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
1991 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
1993 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
1994 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
1997 /* Synth Playback Volume */
1998 for (z = 0; z < 2; z++)
1999 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
2000 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
2003 /* Synth Capture Volume + Switch */
2004 for (z = 0; z < 2; z++) {
2005 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
2006 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2008 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
2009 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
2012 /* Surround Digital Playback Volume (renamed later without Digital) */
2013 for (z = 0; z < 2; z++)
2014 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
2015 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
2018 /* Surround Capture Volume + Switch */
2019 for (z = 0; z < 2; z++) {
2020 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
2021 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2023 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
2024 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
2027 /* Center Playback Volume (renamed later without Digital) */
2028 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
2029 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
2031 /* LFE Playback Volume + Switch (renamed later without Digital) */
2032 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
2033 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
2035 /* Front Playback Volume */
2036 for (z = 0; z < 2; z++)
2037 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
2038 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
2041 /* Front Capture Volume + Switch */
2042 for (z = 0; z < 2; z++) {
2043 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
2044 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2046 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
2047 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
2054 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
2055 /* AC'97 Playback Volume */
2056 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
2057 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
2058 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
2059 /* AC'97 Capture Volume */
2060 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
2061 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
2062 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
2065 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
2066 /* IEC958 TTL Playback Volume */
2067 for (z = 0; z < 2; z++)
2068 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
2069 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2072 /* IEC958 TTL Capture Volume + Switch */
2073 for (z = 0; z < 2; z++) {
2074 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2075 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2077 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2078 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2082 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2083 /* Zoom Video Playback Volume */
2084 for (z = 0; z < 2; z++)
2085 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2086 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2089 /* Zoom Video Capture Volume + Switch */
2090 for (z = 0; z < 2; z++) {
2091 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2092 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2094 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2095 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2099 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2100 /* IEC958 Optical Playback Volume */
2101 for (z = 0; z < 2; z++)
2102 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2103 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2106 /* IEC958 Optical Capture Volume */
2107 for (z = 0; z < 2; z++) {
2108 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2109 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2111 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2112 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2116 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2117 /* Line LiveDrive Playback Volume */
2118 for (z = 0; z < 2; z++)
2119 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2120 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2123 /* Line LiveDrive Capture Volume + Switch */
2124 for (z = 0; z < 2; z++) {
2125 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2126 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2128 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2129 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2133 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2134 /* IEC958 Coax Playback Volume */
2135 for (z = 0; z < 2; z++)
2136 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2137 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2140 /* IEC958 Coax Capture Volume + Switch */
2141 for (z = 0; z < 2; z++) {
2142 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2143 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2145 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2146 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2150 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2151 /* Line LiveDrive Playback Volume */
2152 for (z = 0; z < 2; z++)
2153 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2154 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2155 controls[i-1].id.index = 1;
2158 /* Line LiveDrive Capture Volume */
2159 for (z = 0; z < 2; z++) {
2160 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2161 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2163 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2164 controls[i-1].id.index = 1;
2165 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2166 controls[i-1].id.index = 1;
2171 * Process tone control
2173 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
2174 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
2175 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
2176 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
2177 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
2178 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
2180 ctl = &controls[i + 0];
2181 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2182 strcpy(ctl->id.name, "Tone Control - Bass");
2187 ctl->value[0] = ctl->value[1] = 20;
2188 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2189 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2190 ctl = &controls[i + 1];
2191 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2192 strcpy(ctl->id.name, "Tone Control - Treble");
2197 ctl->value[0] = ctl->value[1] = 20;
2198 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2199 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2201 #define BASS_GPR 0x8c
2202 #define TREBLE_GPR 0x96
2204 for (z = 0; z < 5; z++) {
2206 for (j = 0; j < 2; j++) {
2207 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2208 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2211 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
2213 for (j = 0; j < 2; j++) { /* left/right */
2214 k = 0xa0 + (z * 8) + (j * 4);
2215 l = 0xd0 + (z * 8) + (j * 4);
2216 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
2218 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2219 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2220 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2221 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2222 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2223 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2225 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2226 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2227 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2228 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2229 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2230 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2232 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2234 if (z == 2) /* center */
2243 for (z = 0; z < 6; z++) {
2244 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
2245 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
2246 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2247 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2249 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2255 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2256 /* AC'97 Playback Volume */
2258 for (z = 0; z < 2; z++)
2259 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
2262 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2263 /* IEC958 Optical Raw Playback Switch */
2265 for (z = 0; z < 2; z++) {
2266 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2267 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2268 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2269 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2270 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2271 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2275 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2279 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2280 /* Headphone Playback Volume */
2282 for (z = 0; z < 2; z++) {
2283 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
2284 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2285 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2286 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2287 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2290 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2291 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
2292 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2293 controls[i-1].id.index = 1;
2294 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2295 controls[i-1].id.index = 1;
2300 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2301 for (z = 0; z < 2; z++)
2302 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2304 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2305 for (z = 0; z < 2; z++)
2306 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2308 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2309 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2310 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2311 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2313 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2314 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2318 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2319 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2320 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2321 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2323 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2324 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2328 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2329 for (z = 0; z < 2; z++)
2330 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2333 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2334 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2336 /* EFX capture - capture the 16 EXTINS */
2337 if (emu->card_capabilities->sblive51) {
2338 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
2339 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
2341 * Since only 14 of the 16 EXTINs are used, this is not a big problem.
2342 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
2343 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
2344 * channel. Multitrack recorders will still see the center/lfe output signal
2345 * on the second and third channels.
2347 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
2348 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
2349 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
2350 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
2351 for (z = 4; z < 14; z++)
2352 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2354 for (z = 0; z < 16; z++)
2355 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2364 if (i > SND_EMU10K1_GPR_CONTROLS) {
2370 /* clear remaining instruction memory */
2372 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2374 if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
2376 seg = snd_enter_user();
2377 icode->gpr_add_control_count = i;
2378 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
2379 emu->support_tlv = 1; /* support TLV */
2380 err = snd_emu10k1_icode_poke(emu, icode);
2381 emu->support_tlv = 0; /* clear again */
2382 snd_leave_user(seg);
2384 err = snd_emu10k1_ipcm_poke(emu, ipcm);
2390 kfree((void __force *)icode->gpr_map);
2396 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2398 spin_lock_init(&emu->fx8010.irq_lock);
2399 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2401 return _snd_emu10k1_audigy_init_efx(emu);
2403 return _snd_emu10k1_init_efx(emu);
2406 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2408 /* stop processor */
2410 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2412 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2415 #if 0 /* FIXME: who use them? */
2416 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2418 if (output < 0 || output >= 6)
2420 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2424 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2426 if (output < 0 || output >= 6)
2428 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2433 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2437 /* size is in samples */
2439 size = (size - 1) >> 13;
2445 size = 0x2000 << size_reg;
2447 if ((emu->fx8010.etram_pages.bytes / 2) == size)
2449 spin_lock_irq(&emu->emu_lock);
2450 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2451 spin_unlock_irq(&emu->emu_lock);
2452 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2453 snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
2454 if (emu->fx8010.etram_pages.area != NULL) {
2455 snd_dma_free_pages(&emu->fx8010.etram_pages);
2456 emu->fx8010.etram_pages.area = NULL;
2457 emu->fx8010.etram_pages.bytes = 0;
2461 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
2462 size * 2, &emu->fx8010.etram_pages) < 0)
2464 memset(emu->fx8010.etram_pages.area, 0, size * 2);
2465 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2466 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2467 spin_lock_irq(&emu->emu_lock);
2468 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2469 spin_unlock_irq(&emu->emu_lock);
2475 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2480 static void copy_string(char *dst, char *src, char *null, int idx)
2483 sprintf(dst, "%s %02X", null, idx);
2488 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2489 struct snd_emu10k1_fx8010_info *info)
2491 char **fxbus, **extin, **extout;
2492 unsigned short fxbus_mask, extin_mask, extout_mask;
2495 info->internal_tram_size = emu->fx8010.itram_size;
2496 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2498 extin = emu->audigy ? audigy_ins : creative_ins;
2499 extout = emu->audigy ? audigy_outs : creative_outs;
2500 fxbus_mask = emu->fx8010.fxbus_mask;
2501 extin_mask = emu->fx8010.extin_mask;
2502 extout_mask = emu->fx8010.extout_mask;
2503 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2504 copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
2505 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2506 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2508 for (res = 16; res < 32; res++, extout++)
2509 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2510 info->gpr_controls = emu->fx8010.gpr_count;
2513 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2515 struct snd_emu10k1 *emu = hw->private_data;
2516 struct snd_emu10k1_fx8010_info *info;
2517 struct snd_emu10k1_fx8010_code *icode;
2518 struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2520 void __user *argp = (void __user *)arg;
2524 case SNDRV_EMU10K1_IOCTL_PVERSION:
2525 emu->support_tlv = 1;
2526 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2527 case SNDRV_EMU10K1_IOCTL_INFO:
2528 info = kzalloc(sizeof(*info), GFP_KERNEL);
2531 snd_emu10k1_fx8010_info(emu, info);
2532 if (copy_to_user(argp, info, sizeof(*info))) {
2538 case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2539 if (!capable(CAP_SYS_ADMIN))
2542 icode = memdup_user(argp, sizeof(*icode));
2544 return PTR_ERR(icode);
2545 res = snd_emu10k1_icode_poke(emu, icode);
2548 case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2549 icode = memdup_user(argp, sizeof(*icode));
2551 return PTR_ERR(icode);
2552 res = snd_emu10k1_icode_peek(emu, icode);
2553 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2559 case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2560 ipcm = memdup_user(argp, sizeof(*ipcm));
2562 return PTR_ERR(ipcm);
2563 res = snd_emu10k1_ipcm_poke(emu, ipcm);
2566 case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2567 ipcm = memdup_user(argp, sizeof(*ipcm));
2569 return PTR_ERR(ipcm);
2570 res = snd_emu10k1_ipcm_peek(emu, ipcm);
2571 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2577 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2578 if (!capable(CAP_SYS_ADMIN))
2580 if (get_user(addr, (unsigned int __user *)argp))
2582 mutex_lock(&emu->fx8010.lock);
2583 res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2584 mutex_unlock(&emu->fx8010.lock);
2586 case SNDRV_EMU10K1_IOCTL_STOP:
2587 if (!capable(CAP_SYS_ADMIN))
2590 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2592 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2594 case SNDRV_EMU10K1_IOCTL_CONTINUE:
2595 if (!capable(CAP_SYS_ADMIN))
2598 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2600 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2602 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2603 if (!capable(CAP_SYS_ADMIN))
2606 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2608 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2611 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2613 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2615 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2616 if (!capable(CAP_SYS_ADMIN))
2618 if (get_user(addr, (unsigned int __user *)argp))
2623 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
2625 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
2628 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
2630 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
2632 case SNDRV_EMU10K1_IOCTL_DBG_READ:
2634 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2636 addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2637 if (put_user(addr, (unsigned int __user *)argp))
2644 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2649 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2651 struct snd_hwdep *hw;
2654 if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
2656 strcpy(hw->name, "EMU10K1 (FX8010)");
2657 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2658 hw->ops.open = snd_emu10k1_fx8010_open;
2659 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2660 hw->ops.release = snd_emu10k1_fx8010_release;
2661 hw->private_data = emu;
2665 #ifdef CONFIG_PM_SLEEP
2666 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2670 len = emu->audigy ? 0x200 : 0x100;
2671 emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
2672 if (! emu->saved_gpr)
2674 len = emu->audigy ? 0x100 : 0xa0;
2675 emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
2676 emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
2677 if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2679 len = emu->audigy ? 2 * 1024 : 2 * 512;
2680 emu->saved_icode = vmalloc(len * 4);
2681 if (! emu->saved_icode)
2686 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2688 kfree(emu->saved_gpr);
2689 kfree(emu->tram_val_saved);
2690 kfree(emu->tram_addr_saved);
2691 vfree(emu->saved_icode);
2695 * save/restore GPR, TRAM and codes
2697 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2701 len = emu->audigy ? 0x200 : 0x100;
2702 for (i = 0; i < len; i++)
2703 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2705 len = emu->audigy ? 0x100 : 0xa0;
2706 for (i = 0; i < len; i++) {
2707 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2708 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2710 emu->tram_addr_saved[i] >>= 12;
2711 emu->tram_addr_saved[i] |=
2712 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2716 len = emu->audigy ? 2 * 1024 : 2 * 512;
2717 for (i = 0; i < len; i++)
2718 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2721 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2726 if (emu->fx8010.etram_pages.bytes > 0) {
2727 unsigned size, size_reg = 0;
2728 size = emu->fx8010.etram_pages.bytes / 2;
2729 size = (size - 1) >> 13;
2734 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2735 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2736 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2737 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2741 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2743 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2745 len = emu->audigy ? 0x200 : 0x100;
2746 for (i = 0; i < len; i++)
2747 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2749 len = emu->audigy ? 0x100 : 0xa0;
2750 for (i = 0; i < len; i++) {
2751 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2752 emu->tram_val_saved[i]);
2754 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2755 emu->tram_addr_saved[i]);
2757 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2758 emu->tram_addr_saved[i] << 12);
2759 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2760 emu->tram_addr_saved[i] >> 20);
2764 len = emu->audigy ? 2 * 1024 : 2 * 512;
2765 for (i = 0; i < len; i++)
2766 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2768 /* start FX processor when the DSP code is updated */
2770 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2772 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);