sound/pci/emu10k1/emu10k1_main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   4  *                   Creative Labs, Inc.
   5  *  Routines for control of EMU10K1 chips
   6  *
   7  *  Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
   8  *      Added support for Audigy 2 Value.
   9  *      Added EMU 1010 support.
  10  *      General bug fixes and enhancements.
  11  *
  12  *  BUGS:
  13  *    --
  14  *
  15  *  TODO:
  16  *    --
  17  */
  18
  19 #include <linux/sched.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/iommu.h>
  25 #include <linux/pci.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/mutex.h>
  29
  30
  31 #include <sound/core.h>
  32 #include <sound/emu10k1.h>
  33 #include <linux/firmware.h>
  34 #include "p16v.h"
  35 #include "tina2.h"
  36 #include "p17v.h"
  37
  38
  39 #define HANA_FILENAME "/*(DEBLOBBED)*/"
  40 #define DOCK_FILENAME "/*(DEBLOBBED)*/"
  41 #define EMU1010B_FILENAME "/*(DEBLOBBED)*/"
  42 #define MICRO_DOCK_FILENAME "/*(DEBLOBBED)*/"
  43 #define EMU0404_FILENAME "/*(DEBLOBBED)*/"
  44 #define EMU1010_NOTEBOOK_FILENAME "/*(DEBLOBBED)*/"
  45
  46 /*(DEBLOBBED)*/
  47
  48
  49 /*************************************************************************
  50  * EMU10K1 init / done
  51  *************************************************************************/
  52
  53 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
  54 {
  55         snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
  56         snd_emu10k1_ptr_write(emu, IP, ch, 0);
  57         snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
  58         snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
  59         snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
  60         snd_emu10k1_ptr_write(emu, CPF, ch, 0);
  61         snd_emu10k1_ptr_write(emu, CCR, ch, 0);
  62
  63         snd_emu10k1_ptr_write(emu, PSST, ch, 0);
  64         snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
  65         snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
  66         snd_emu10k1_ptr_write(emu, Z1, ch, 0);
  67         snd_emu10k1_ptr_write(emu, Z2, ch, 0);
  68         snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
  69
  70         snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
  71         snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
  72         snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
  73         snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
  74         snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
  75         snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24);    /* 1 Hz */
  76         snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24);    /* 1 Hz */
  77         snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
  78
  79         /*** these are last so OFF prevents writing ***/
  80         snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
  81         snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
  82         snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
  83         snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
  84         snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
  85
  86         /* Audigy extra stuffs */
  87         if (emu->audigy) {
  88                 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
  89                 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
  90                 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
  91                 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
  92                 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
  93                 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
  94                 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
  95         }
  96 }
  97
  98 static unsigned int spi_dac_init[] = {
  99                 0x00ff,
 100                 0x02ff,
 101                 0x0400,
 102                 0x0520,
 103                 0x0600,
 104                 0x08ff,
 105                 0x0aff,
 106                 0x0cff,
 107                 0x0eff,
 108                 0x10ff,
 109                 0x1200,
 110                 0x1400,
 111                 0x1480,
 112                 0x1800,
 113                 0x1aff,
 114                 0x1cff,
 115                 0x1e00,
 116                 0x0530,
 117                 0x0602,
 118                 0x0622,
 119                 0x1400,
 120 };
 121
 122 static unsigned int i2c_adc_init[][2] = {
 123         { 0x17, 0x00 }, /* Reset */
 124         { 0x07, 0x00 }, /* Timeout */
 125         { 0x0b, 0x22 },  /* Interface control */
 126         { 0x0c, 0x22 },  /* Master mode control */
 127         { 0x0d, 0x08 },  /* Powerdown control */
 128         { 0x0e, 0xcf },  /* Attenuation Left  0x01 = -103dB, 0xff = 24dB */
 129         { 0x0f, 0xcf },  /* Attenuation Right 0.5dB steps */
 130         { 0x10, 0x7b },  /* ALC Control 1 */
 131         { 0x11, 0x00 },  /* ALC Control 2 */
 132         { 0x12, 0x32 },  /* ALC Control 3 */
 133         { 0x13, 0x00 },  /* Noise gate control */
 134         { 0x14, 0xa6 },  /* Limiter control */
 135         { 0x15, ADC_MUX_2 },  /* ADC Mixer control. Mic for A2ZS Notebook */
 136 };
 137
 138 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
 139 {
 140         unsigned int silent_page;
 141         int ch;
 142         u32 tmp;
 143
 144         /* disable audio and lock cache */
 145         outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
 146                 HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
 147
 148         /* reset recording buffers */
 149         snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
 150         snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
 151         snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
 152         snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
 153         snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
 154         snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
 155
 156         /* disable channel interrupt */
 157         outl(0, emu->port + INTE);
 158         snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
 159         snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
 160         snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
 161         snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
 162
 163         if (emu->audigy) {
 164                 /* set SPDIF bypass mode */
 165                 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
 166                 /* enable rear left + rear right AC97 slots */
 167                 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
 168                                       AC97SLOT_REAR_LEFT);
 169         }
 170
 171         /* init envelope engine */
 172         for (ch = 0; ch < NUM_G; ch++)
 173                 snd_emu10k1_voice_init(emu, ch);
 174
 175         snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
 176         snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
 177         snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
 178
 179         if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
 180                 /* Hacks for Alice3 to work independent of haP16V driver */
 181                 /* Setup SRCMulti_I2S SamplingRate */
 182                 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
 183                 tmp &= 0xfffff1ff;
 184                 tmp |= (0x2<<9);
 185                 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
 186
 187                 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
 188                 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
 189                 /* Setup SRCMulti Input Audio Enable */
 190                 /* Use 0xFFFFFFFF to enable P16V sounds. */
 191                 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
 192
 193                 /* Enabled Phased (8-channel) P16V playback */
 194                 outl(0x0201, emu->port + HCFG2);
 195                 /* Set playback routing. */
 196                 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
 197         }
 198         if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
 199                 /* Hacks for Alice3 to work independent of haP16V driver */
 200                 dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
 201                 /* Setup SRCMulti_I2S SamplingRate */
 202                 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
 203                 tmp &= 0xfffff1ff;
 204                 tmp |= (0x2<<9);
 205                 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
 206
 207                 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
 208                 outl(0x600000, emu->port + 0x20);
 209                 outl(0x14, emu->port + 0x24);
 210
 211                 /* Setup SRCMulti Input Audio Enable */
 212                 outl(0x7b0000, emu->port + 0x20);
 213                 outl(0xFF000000, emu->port + 0x24);
 214
 215                 /* Setup SPDIF Out Audio Enable */
 216                 /* The Audigy 2 Value has a separate SPDIF out,
 217                  * so no need for a mixer switch
 218                  */
 219                 outl(0x7a0000, emu->port + 0x20);
 220                 outl(0xFF000000, emu->port + 0x24);
 221                 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
 222                 outl(tmp, emu->port + A_IOCFG);
 223         }
 224         if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
 225                 int size, n;
 226
 227                 size = ARRAY_SIZE(spi_dac_init);
 228                 for (n = 0; n < size; n++)
 229                         snd_emu10k1_spi_write(emu, spi_dac_init[n]);
 230
 231                 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
 232                 /* Enable GPIOs
 233                  * GPIO0: Unknown
 234                  * GPIO1: Speakers-enabled.
 235                  * GPIO2: Unknown
 236                  * GPIO3: Unknown
 237                  * GPIO4: IEC958 Output on.
 238                  * GPIO5: Unknown
 239                  * GPIO6: Unknown
 240                  * GPIO7: Unknown
 241                  */
 242                 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
 243         }
 244         if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
 245                 int size, n;
 246
 247                 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
 248                 tmp = inl(emu->port + A_IOCFG);
 249                 outl(tmp | 0x4, emu->port + A_IOCFG);  /* Set bit 2 for mic input */
 250                 tmp = inl(emu->port + A_IOCFG);
 251                 size = ARRAY_SIZE(i2c_adc_init);
 252                 for (n = 0; n < size; n++)
 253                         snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
 254                 for (n = 0; n < 4; n++) {
 255                         emu->i2c_capture_volume[n][0] = 0xcf;
 256                         emu->i2c_capture_volume[n][1] = 0xcf;
 257                 }
 258         }
 259
 260
 261         snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
 262         snd_emu10k1_ptr_write(emu, TCB, 0, 0);  /* taken from original driver */
 263         snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
 264
 265         silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
 266         for (ch = 0; ch < NUM_G; ch++) {
 267                 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
 268                 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
 269         }
 270
 271         if (emu->card_capabilities->emu_model) {
 272                 outl(HCFG_AUTOMUTE_ASYNC |
 273                         HCFG_EMU32_SLAVE |
 274                         HCFG_AUDIOENABLE, emu->port + HCFG);
 275         /*
 276          *  Hokay, setup HCFG
 277          *   Mute Disable Audio = 0
 278          *   Lock Tank Memory = 1
 279          *   Lock Sound Memory = 0
 280          *   Auto Mute = 1
 281          */
 282         } else if (emu->audigy) {
 283                 if (emu->revision == 4) /* audigy2 */
 284                         outl(HCFG_AUDIOENABLE |
 285                              HCFG_AC3ENABLE_CDSPDIF |
 286                              HCFG_AC3ENABLE_GPSPDIF |
 287                              HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
 288                 else
 289                         outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
 290         /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
 291          * e.g. card_capabilities->joystick */
 292         } else if (emu->model == 0x20 ||
 293             emu->model == 0xc400 ||
 294             (emu->model == 0x21 && emu->revision < 6))
 295                 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
 296         else
 297                 /* With on-chip joystick */
 298                 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
 299
 300         if (enable_ir) {        /* enable IR for SB Live */
 301                 if (emu->card_capabilities->emu_model) {
 302                         ;  /* Disable all access to A_IOCFG for the emu1010 */
 303                 } else if (emu->card_capabilities->i2c_adc) {
 304                         ;  /* Disable A_IOCFG for Audigy 2 ZS Notebook */
 305                 } else if (emu->audigy) {
 306                         unsigned int reg = inl(emu->port + A_IOCFG);
 307                         outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
 308                         udelay(500);
 309                         outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
 310                         udelay(100);
 311                         outl(reg, emu->port + A_IOCFG);
 312                 } else {
 313                         unsigned int reg = inl(emu->port + HCFG);
 314                         outl(reg | HCFG_GPOUT2, emu->port + HCFG);
 315                         udelay(500);
 316                         outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
 317                         udelay(100);
 318                         outl(reg, emu->port + HCFG);
 319                 }
 320         }
 321
 322         if (emu->card_capabilities->emu_model) {
 323                 ;  /* Disable all access to A_IOCFG for the emu1010 */
 324         } else if (emu->card_capabilities->i2c_adc) {
 325                 ;  /* Disable A_IOCFG for Audigy 2 ZS Notebook */
 326         } else if (emu->audigy) {       /* enable analog output */
 327                 unsigned int reg = inl(emu->port + A_IOCFG);
 328                 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
 329         }
 330
 331         if (emu->address_mode == 0) {
 332                 /* use 16M in 4G */
 333                 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG);
 334         }
 335
 336         return 0;
 337 }
 338
 339 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
 340 {
 341         /*
 342          *  Enable the audio bit
 343          */
 344         outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
 345
 346         /* Enable analog/digital outs on audigy */
 347         if (emu->card_capabilities->emu_model) {
 348                 ;  /* Disable all access to A_IOCFG for the emu1010 */
 349         } else if (emu->card_capabilities->i2c_adc) {
 350                 ;  /* Disable A_IOCFG for Audigy 2 ZS Notebook */
 351         } else if (emu->audigy) {
 352                 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
 353
 354                 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
 355                         /* Unmute Analog now.  Set GPO6 to 1 for Apollo.
 356                          * This has to be done after init ALice3 I2SOut beyond 48KHz.
 357                          * So, sequence is important. */
 358                         outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
 359                 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
 360                         /* Unmute Analog now. */
 361                         outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
 362                 } else {
 363                         /* Disable routing from AC97 line out to Front speakers */
 364                         outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
 365                 }
 366         }
 367
 368 #if 0
 369         {
 370         unsigned int tmp;
 371         /* FIXME: the following routine disables LiveDrive-II !! */
 372         /* TOSLink detection */
 373         emu->tos_link = 0;
 374         tmp = inl(emu->port + HCFG);
 375         if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
 376                 outl(tmp|0x800, emu->port + HCFG);
 377                 udelay(50);
 378                 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
 379                         emu->tos_link = 1;
 380                         outl(tmp, emu->port + HCFG);
 381                 }
 382         }
 383         }
 384 #endif
 385
 386         snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
 387 }
 388
 389 int snd_emu10k1_done(struct snd_emu10k1 *emu)
 390 {
 391         int ch;
 392
 393         outl(0, emu->port + INTE);
 394
 395         /*
 396          *  Shutdown the chip
 397          */
 398         for (ch = 0; ch < NUM_G; ch++)
 399                 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
 400         for (ch = 0; ch < NUM_G; ch++) {
 401                 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
 402                 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
 403                 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
 404                 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
 405         }
 406
 407         /* reset recording buffers */
 408         snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
 409         snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
 410         snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
 411         snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
 412         snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
 413         snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
 414         snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
 415         snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
 416         snd_emu10k1_ptr_write(emu, TCB, 0, 0);
 417         if (emu->audigy)
 418                 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
 419         else
 420                 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
 421
 422         /* disable channel interrupt */
 423         snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
 424         snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
 425         snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
 426         snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
 427
 428         /* disable audio and lock cache */
 429         outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
 430         snd_emu10k1_ptr_write(emu, PTB, 0, 0);
 431
 432         return 0;
 433 }
 434
 435 /*************************************************************************
 436  * ECARD functional implementation
 437  *************************************************************************/
 438
 439 /* In A1 Silicon, these bits are in the HC register */
 440 #define HOOKN_BIT               (1L << 12)
 441 #define HANDN_BIT               (1L << 11)
 442 #define PULSEN_BIT              (1L << 10)
 443
 444 #define EC_GDI1                 (1 << 13)
 445 #define EC_GDI0                 (1 << 14)
 446
 447 #define EC_NUM_CONTROL_BITS     20
 448
 449 #define EC_AC3_DATA_SELN        0x0001L
 450 #define EC_EE_DATA_SEL          0x0002L
 451 #define EC_EE_CNTRL_SELN        0x0004L
 452 #define EC_EECLK                0x0008L
 453 #define EC_EECS                 0x0010L
 454 #define EC_EESDO                0x0020L
 455 #define EC_TRIM_CSN             0x0040L
 456 #define EC_TRIM_SCLK            0x0080L
 457 #define EC_TRIM_SDATA           0x0100L
 458 #define EC_TRIM_MUTEN           0x0200L
 459 #define EC_ADCCAL               0x0400L
 460 #define EC_ADCRSTN              0x0800L
 461 #define EC_DACCAL               0x1000L
 462 #define EC_DACMUTEN             0x2000L
 463 #define EC_LEDN                 0x4000L
 464
 465 #define EC_SPDIF0_SEL_SHIFT     15
 466 #define EC_SPDIF1_SEL_SHIFT     17
 467 #define EC_SPDIF0_SEL_MASK      (0x3L << EC_SPDIF0_SEL_SHIFT)
 468 #define EC_SPDIF1_SEL_MASK      (0x7L << EC_SPDIF1_SEL_SHIFT)
 469 #define EC_SPDIF0_SELECT(_x)    (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
 470 #define EC_SPDIF1_SELECT(_x)    (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
 471 #define EC_CURRENT_PROM_VERSION 0x01    /* Self-explanatory.  This should
 472                                          * be incremented any time the EEPROM's
 473                                          * format is changed.  */
 474
 475 #define EC_EEPROM_SIZE          0x40    /* ECARD EEPROM has 64 16-bit words */
 476
 477 /* Addresses for special values stored in to EEPROM */
 478 #define EC_PROM_VERSION_ADDR    0x20    /* Address of the current prom version */
 479 #define EC_BOARDREV0_ADDR       0x21    /* LSW of board rev */
 480 #define EC_BOARDREV1_ADDR       0x22    /* MSW of board rev */
 481
 482 #define EC_LAST_PROMFILE_ADDR   0x2f
 483
 484 #define EC_SERIALNUM_ADDR       0x30    /* First word of serial number.  The
 485                                          * can be up to 30 characters in length
 486                                          * and is stored as a NULL-terminated
 487                                          * ASCII string.  Any unused bytes must be
 488                                          * filled with zeros */
 489 #define EC_CHECKSUM_ADDR        0x3f    /* Location at which checksum is stored */
 490
 491
 492 /* Most of this stuff is pretty self-evident.  According to the hardware
 493  * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
 494  * offset problem.  Weird.
 495  */
 496 #define EC_RAW_RUN_MODE         (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
 497                                  EC_TRIM_CSN)
 498
 499
 500 #define EC_DEFAULT_ADC_GAIN     0xC4C4
 501 #define EC_DEFAULT_SPDIF0_SEL   0x0
 502 #define EC_DEFAULT_SPDIF1_SEL   0x4
 503
 504 /**************************************************************************
 505  * @func Clock bits into the Ecard's control latch.  The Ecard uses a
 506  *  control latch will is loaded bit-serially by toggling the Modem control
 507  *  lines from function 2 on the E8010.  This function hides these details
 508  *  and presents the illusion that we are actually writing to a distinct
 509  *  register.
 510  */
 511
 512 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value)
 513 {
 514         unsigned short count;
 515         unsigned int data;
 516         unsigned long hc_port;
 517         unsigned int hc_value;
 518
 519         hc_port = emu->port + HCFG;
 520         hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
 521         outl(hc_value, hc_port);
 522
 523         for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
 524
 525                 /* Set up the value */
 526                 data = ((value & 0x1) ? PULSEN_BIT : 0);
 527                 value >>= 1;
 528
 529                 outl(hc_value | data, hc_port);
 530
 531                 /* Clock the shift register */
 532                 outl(hc_value | data | HANDN_BIT, hc_port);
 533                 outl(hc_value | data, hc_port);
 534         }
 535
 536         /* Latch the bits */
 537         outl(hc_value | HOOKN_BIT, hc_port);
 538         outl(hc_value, hc_port);
 539 }
 540
 541 /**************************************************************************
 542  * @func Set the gain of the ECARD's CS3310 Trim/gain controller.  The
 543  * trim value consists of a 16bit value which is composed of two
 544  * 8 bit gain/trim values, one for the left channel and one for the
 545  * right channel.  The following table maps from the Gain/Attenuation
 546  * value in decibels into the corresponding bit pattern for a single
 547  * channel.
 548  */
 549
 550 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu,
 551                                          unsigned short gain)
 552 {
 553         unsigned int bit;
 554
 555         /* Enable writing to the TRIM registers */
 556         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
 557
 558         /* Do it again to insure that we meet hold time requirements */
 559         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
 560
 561         for (bit = (1 << 15); bit; bit >>= 1) {
 562                 unsigned int value;
 563
 564                 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
 565
 566                 if (gain & bit)
 567                         value |= EC_TRIM_SDATA;
 568
 569                 /* Clock the bit */
 570                 snd_emu10k1_ecard_write(emu, value);
 571                 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
 572                 snd_emu10k1_ecard_write(emu, value);
 573         }
 574
 575         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
 576 }
 577
 578 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu)
 579 {
 580         unsigned int hc_value;
 581
 582         /* Set up the initial settings */
 583         emu->ecard_ctrl = EC_RAW_RUN_MODE |
 584                           EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
 585                           EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
 586
 587         /* Step 0: Set the codec type in the hardware control register
 588          * and enable audio output */
 589         hc_value = inl(emu->port + HCFG);
 590         outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
 591         inl(emu->port + HCFG);
 592
 593         /* Step 1: Turn off the led and deassert TRIM_CS */
 594         snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
 595
 596         /* Step 2: Calibrate the ADC and DAC */
 597         snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
 598
 599         /* Step 3: Wait for awhile;   XXX We can't get away with this
 600          * under a real operating system; we'll need to block and wait that
 601          * way. */
 602         snd_emu10k1_wait(emu, 48000);
 603
 604         /* Step 4: Switch off the DAC and ADC calibration.  Note
 605          * That ADC_CAL is actually an inverted signal, so we assert
 606          * it here to stop calibration.  */
 607         snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
 608
 609         /* Step 4: Switch into run mode */
 610         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
 611
 612         /* Step 5: Set the analog input gain */
 613         snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
 614
 615         return 0;
 616 }
 617
 618 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu)
 619 {
 620         unsigned long special_port;
 621         unsigned int value;
 622
 623         /* Special initialisation routine
 624          * before the rest of the IO-Ports become active.
 625          */
 626         special_port = emu->port + 0x38;
 627         value = inl(special_port);
 628         outl(0x00d00000, special_port);
 629         value = inl(special_port);
 630         outl(0x00d00001, special_port);
 631         value = inl(special_port);
 632         outl(0x00d0005f, special_port);
 633         value = inl(special_port);
 634         outl(0x00d0007f, special_port);
 635         value = inl(special_port);
 636         outl(0x0090007f, special_port);
 637         value = inl(special_port);
 638
 639         snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
 640         /* Delay to give time for ADC chip to switch on. It needs 113ms */
 641         msleep(200);
 642         return 0;
 643 }
 644
 645 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
 646                                      const struct firmware *fw_entry)
 647 {
 648         int n, i;
 649         int reg;
 650         int value;
 651         unsigned int write_post;
 652         unsigned long flags;
 653
 654         if (!fw_entry)
 655                 return -EIO;
 656
 657         /* The FPGA is a Xilinx Spartan IIE XC2S50E */
 658         /* GPIO7 -> FPGA PGMN
 659          * GPIO6 -> FPGA CCLK
 660          * GPIO5 -> FPGA DIN
 661          * FPGA CONFIG OFF -> FPGA PGMN
 662          */
 663         spin_lock_irqsave(&emu->emu_lock, flags);
 664         outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
 665         write_post = inl(emu->port + A_IOCFG);
 666         udelay(100);
 667         outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
 668         write_post = inl(emu->port + A_IOCFG);
 669         udelay(100); /* Allow FPGA memory to clean */
 670         for (n = 0; n < fw_entry->size; n++) {
 671                 value = fw_entry->data[n];
 672                 for (i = 0; i < 8; i++) {
 673                         reg = 0x80;
 674                         if (value & 0x1)
 675                                 reg = reg | 0x20;
 676                         value = value >> 1;
 677                         outl(reg, emu->port + A_IOCFG);
 678                         write_post = inl(emu->port + A_IOCFG);
 679                         outl(reg | 0x40, emu->port + A_IOCFG);
 680                         write_post = inl(emu->port + A_IOCFG);
 681                 }
 682         }
 683         /* After programming, set GPIO bit 4 high again. */
 684         outl(0x10, emu->port + A_IOCFG);
 685         write_post = inl(emu->port + A_IOCFG);
 686         spin_unlock_irqrestore(&emu->emu_lock, flags);
 687
 688         return 0;
 689 }
 690
 691 /* firmware file names, per model, init-fw and dock-fw (optional) */
 692 static const char * const firmware_names[5][2] = {
 693         [EMU_MODEL_EMU1010] = {
 694                 HANA_FILENAME, DOCK_FILENAME
 695         },
 696         [EMU_MODEL_EMU1010B] = {
 697                 EMU1010B_FILENAME, MICRO_DOCK_FILENAME
 698         },
 699         [EMU_MODEL_EMU1616] = {
 700                 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME
 701         },
 702         [EMU_MODEL_EMU0404] = {
 703                 EMU0404_FILENAME, NULL
 704         },
 705 };
 706
 707 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock,
 708                                      const struct firmware **fw)
 709 {
 710         const char *filename;
 711         int err;
 712
 713         if (!*fw) {
 714                 filename = firmware_names[emu->card_capabilities->emu_model][dock];
 715                 if (!filename)
 716                         return 0;
 717                 err = reject_firmware(fw, filename, &emu->pci->dev);
 718                 if (err)
 719                         return err;
 720         }
 721
 722         return snd_emu1010_load_firmware_entry(emu, *fw);
 723 }
 724
 725 static void emu1010_firmware_work(struct work_struct *work)
 726 {
 727         struct snd_emu10k1 *emu;
 728         u32 tmp, tmp2, reg;
 729         int err;
 730
 731         emu = container_of(work, struct snd_emu10k1,
 732                            emu1010.firmware_work.work);
 733         if (emu->card->shutdown)
 734                 return;
 735 #ifdef CONFIG_PM_SLEEP
 736         if (emu->suspend)
 737                 return;
 738 #endif
 739         snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */
 740         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg); /* OPTIONS: Which cards are attached to the EMU */
 741         if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {
 742                 /* Audio Dock attached */
 743                 /* Return to Audio Dock programming mode */
 744                 dev_info(emu->card->dev,
 745                          "emu1010: Loading Audio Dock Firmware\n");
 746                 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
 747                                        EMU_HANA_FPGA_CONFIG_AUDIODOCK);
 748                 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw);
 749                 if (err < 0)
 750                         goto next;
 751
 752                 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
 753                 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp);
 754                 dev_info(emu->card->dev,
 755                          "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp);
 756                 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
 757                 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp);
 758                 dev_info(emu->card->dev,
 759                          "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp);
 760                 if ((tmp & 0x1f) != 0x15) {
 761                         /* FPGA failed to be programmed */
 762                         dev_info(emu->card->dev,
 763                                  "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n",
 764                                  tmp);
 765                         goto next;
 766                 }
 767                 dev_info(emu->card->dev,
 768                          "emu1010: Audio Dock Firmware loaded\n");
 769                 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp);
 770                 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2);
 771                 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2);
 772                 /* Sync clocking between 1010 and Dock */
 773                 /* Allow DLL to settle */
 774                 msleep(10);
 775                 /* Unmute all. Default is muted after a firmware load */
 776                 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
 777         } else if (!reg && emu->emu1010.last_reg) {
 778                 /* Audio Dock removed */
 779                 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
 780                 /* Unmute all */
 781                 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
 782         }
 783
 784  next:
 785         emu->emu1010.last_reg = reg;
 786         if (!emu->card->shutdown)
 787                 schedule_delayed_work(&emu->emu1010.firmware_work,
 788                                       msecs_to_jiffies(1000));
 789 }
 790
 791 /*
 792  * EMU-1010 - details found out from this driver, official MS Win drivers,
 793  * testing the card:
 794  *
 795  * Audigy2 (aka Alice2):
 796  * ---------------------
 797  *      * communication over PCI
 798  *      * conversion of 32-bit data coming over EMU32 links from HANA FPGA
 799  *        to 2 x 16-bit, using internal DSP instructions
 800  *      * slave mode, clock supplied by HANA
 801  *      * linked to HANA using:
 802  *              32 x 32-bit serial EMU32 output channels
 803  *              16 x EMU32 input channels
 804  *              (?) x I2S I/O channels (?)
 805  *
 806  * FPGA (aka HANA):
 807  * ---------------
 808  *      * provides all (?) physical inputs and outputs of the card
 809  *              (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
 810  *      * provides clock signal for the card and Alice2
 811  *      * two crystals - for 44.1kHz and 48kHz multiples
 812  *      * provides internal routing of signal sources to signal destinations
 813  *      * inputs/outputs to Alice2 - see above
 814  *
 815  * Current status of the driver:
 816  * ----------------------------
 817  *      * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
 818  *      * PCM device nb. 2:
 819  *              16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
 820  *              16 x 32-bit capture - snd_emu10k1_capture_efx_ops
 821  */
 822 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
 823 {
 824         unsigned int i;
 825         u32 tmp, tmp2, reg;
 826         int err;
 827
 828         dev_info(emu->card->dev, "emu1010: Special config.\n");
 829         /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
 830          * Lock Sound Memory Cache, Lock Tank Memory Cache,
 831          * Mute all codecs.
 832          */
 833         outl(0x0005a00c, emu->port + HCFG);
 834         /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
 835          * Lock Tank Memory Cache,
 836          * Mute all codecs.
 837          */
 838         outl(0x0005a004, emu->port + HCFG);
 839         /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
 840          * Mute all codecs.
 841          */
 842         outl(0x0005a000, emu->port + HCFG);
 843         /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
 844          * Mute all codecs.
 845          */
 846         outl(0x0005a000, emu->port + HCFG);
 847
 848         /* Disable 48Volt power to Audio Dock */
 849         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
 850
 851         /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
 852         snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
 853         dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg);
 854         if ((reg & 0x3f) == 0x15) {
 855                 /* FPGA netlist already present so clear it */
 856                 /* Return to programming mode */
 857
 858                 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
 859         }
 860         snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
 861         dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
 862         if ((reg & 0x3f) == 0x15) {
 863                 /* FPGA failed to return to programming mode */
 864                 dev_info(emu->card->dev,
 865                          "emu1010: FPGA failed to return to programming mode\n");
 866                 return -ENODEV;
 867         }
 868         dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg);
 869
 870         err = snd_emu1010_load_firmware(emu, 0, &emu->firmware);
 871         if (err < 0) {
 872                 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n");
 873                 return err;
 874         }
 875
 876         /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
 877         snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg);
 878         if ((reg & 0x3f) != 0x15) {
 879                 /* FPGA failed to be programmed */
 880                 dev_info(emu->card->dev,
 881                          "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n",
 882                          reg);
 883                 return -ENODEV;
 884         }
 885
 886         dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n");
 887         snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp);
 888         snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2);
 889         dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2);
 890         /* Enable 48Volt power to Audio Dock */
 891         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON);
 892
 893         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
 894         dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
 895         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
 896         dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
 897         snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);
 898         /* Optical -> ADAT I/O  */
 899         /* 0 : SPDIF
 900          * 1 : ADAT
 901          */
 902         emu->emu1010.optical_in = 1; /* IN_ADAT */
 903         emu->emu1010.optical_out = 1; /* IN_ADAT */
 904         tmp = 0;
 905         tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
 906                 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
 907         snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
 908         snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);
 909         /* Set no attenuation on Audio Dock pads. */
 910         snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
 911         emu->emu1010.adc_pads = 0x00;
 912         snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
 913         /* Unmute Audio dock DACs, Headphone source DAC-4. */
 914         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
 915         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
 916         snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp);
 917         /* DAC PADs. */
 918         snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
 919         emu->emu1010.dac_pads = 0x0f;
 920         snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
 921         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
 922         snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
 923         /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
 924         snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
 925         /* MIDI routing */
 926         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
 927         /* Unknown. */
 928         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
 929         /* IRQ Enable: All on */
 930         /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
 931         /* IRQ Enable: All off */
 932         snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
 933
 934         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg);
 935         dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg);
 936         /* Default WCLK set to 48kHz. */
 937         snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
 938         /* Word Clock source, Internal 48kHz x1 */
 939         snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
 940         /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
 941         /* Audio Dock LEDs. */
 942         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
 943
 944 #if 0
 945         /* For 96kHz */
 946         snd_emu1010_fpga_link_dst_src_write(emu,
 947                 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
 948         snd_emu1010_fpga_link_dst_src_write(emu,
 949                 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
 950         snd_emu1010_fpga_link_dst_src_write(emu,
 951                 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
 952         snd_emu1010_fpga_link_dst_src_write(emu,
 953                 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
 954 #endif
 955 #if 0
 956         /* For 192kHz */
 957         snd_emu1010_fpga_link_dst_src_write(emu,
 958                 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
 959         snd_emu1010_fpga_link_dst_src_write(emu,
 960                 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
 961         snd_emu1010_fpga_link_dst_src_write(emu,
 962                 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
 963         snd_emu1010_fpga_link_dst_src_write(emu,
 964                 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
 965         snd_emu1010_fpga_link_dst_src_write(emu,
 966                 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
 967         snd_emu1010_fpga_link_dst_src_write(emu,
 968                 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
 969         snd_emu1010_fpga_link_dst_src_write(emu,
 970                 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
 971         snd_emu1010_fpga_link_dst_src_write(emu,
 972                 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
 973 #endif
 974 #if 1
 975         /* For 48kHz */
 976         snd_emu1010_fpga_link_dst_src_write(emu,
 977                 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
 978         snd_emu1010_fpga_link_dst_src_write(emu,
 979                 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
 980         snd_emu1010_fpga_link_dst_src_write(emu,
 981                 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
 982         snd_emu1010_fpga_link_dst_src_write(emu,
 983                 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
 984         snd_emu1010_fpga_link_dst_src_write(emu,
 985                 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
 986         snd_emu1010_fpga_link_dst_src_write(emu,
 987                 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
 988         snd_emu1010_fpga_link_dst_src_write(emu,
 989                 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
 990         snd_emu1010_fpga_link_dst_src_write(emu,
 991                 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
 992         /* Pavel Hofman - setting defaults for 8 more capture channels
 993          * Defaults only, users will set their own values anyways, let's
 994          * just copy/paste.
 995          */
 996
 997         snd_emu1010_fpga_link_dst_src_write(emu,
 998                 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
 999         snd_emu1010_fpga_link_dst_src_write(emu,
1000                 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
1001         snd_emu1010_fpga_link_dst_src_write(emu,
1002                 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
1003         snd_emu1010_fpga_link_dst_src_write(emu,
1004                 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
1005         snd_emu1010_fpga_link_dst_src_write(emu,
1006                 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
1007         snd_emu1010_fpga_link_dst_src_write(emu,
1008                 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
1009         snd_emu1010_fpga_link_dst_src_write(emu,
1010                 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
1011         snd_emu1010_fpga_link_dst_src_write(emu,
1012                 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
1013 #endif
1014 #if 0
1015         /* Original */
1016         snd_emu1010_fpga_link_dst_src_write(emu,
1017                 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
1018         snd_emu1010_fpga_link_dst_src_write(emu,
1019                 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
1020         snd_emu1010_fpga_link_dst_src_write(emu,
1021                 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
1022         snd_emu1010_fpga_link_dst_src_write(emu,
1023                 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
1024         snd_emu1010_fpga_link_dst_src_write(emu,
1025                 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
1026         snd_emu1010_fpga_link_dst_src_write(emu,
1027                 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
1028         snd_emu1010_fpga_link_dst_src_write(emu,
1029                 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
1030         snd_emu1010_fpga_link_dst_src_write(emu,
1031                 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
1032         snd_emu1010_fpga_link_dst_src_write(emu,
1033                 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
1034         snd_emu1010_fpga_link_dst_src_write(emu,
1035                 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
1036         snd_emu1010_fpga_link_dst_src_write(emu,
1037                 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
1038         snd_emu1010_fpga_link_dst_src_write(emu,
1039                 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
1040 #endif
1041         for (i = 0; i < 0x20; i++) {
1042                 /* AudioDock Elink <- Silence */
1043                 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE);
1044         }
1045         for (i = 0; i < 4; i++) {
1046                 /* Hana SPDIF Out <- Silence */
1047                 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE);
1048         }
1049         for (i = 0; i < 7; i++) {
1050                 /* Hamoa DAC <- Silence */
1051                 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE);
1052         }
1053         for (i = 0; i < 7; i++) {
1054                 /* Hana ADAT Out <- Silence */
1055                 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
1056         }
1057         snd_emu1010_fpga_link_dst_src_write(emu,
1058                 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
1059         snd_emu1010_fpga_link_dst_src_write(emu,
1060                 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
1061         snd_emu1010_fpga_link_dst_src_write(emu,
1062                 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
1063         snd_emu1010_fpga_link_dst_src_write(emu,
1064                 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
1065         snd_emu1010_fpga_link_dst_src_write(emu,
1066                 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
1067         snd_emu1010_fpga_link_dst_src_write(emu,
1068                 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
1069         snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
1070
1071         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1072
1073         /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1074          * Lock Sound Memory Cache, Lock Tank Memory Cache,
1075          * Mute all codecs.
1076          */
1077         outl(0x0000a000, emu->port + HCFG);
1078         /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1079          * Lock Sound Memory Cache, Lock Tank Memory Cache,
1080          * Un-Mute all codecs.
1081          */
1082         outl(0x0000a001, emu->port + HCFG);
1083
1084         /* Initial boot complete. Now patches */
1085
1086         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1087         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1088         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1089         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1090         snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1091         snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
1092         snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif  (or 0x11 for aes/ebu) */
1093
1094 #if 0
1095         snd_emu1010_fpga_link_dst_src_write(emu,
1096                 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
1097         snd_emu1010_fpga_link_dst_src_write(emu,
1098                 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
1099         snd_emu1010_fpga_link_dst_src_write(emu,
1100                 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
1101         snd_emu1010_fpga_link_dst_src_write(emu,
1102                 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
1103 #endif
1104         /* Default outputs */
1105         if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
1106                 /* 1616(M) cardbus default outputs */
1107                 /* ALICE2 bus 0xa0 */
1108                 snd_emu1010_fpga_link_dst_src_write(emu,
1109                         EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1110                 emu->emu1010.output_source[0] = 17;
1111                 snd_emu1010_fpga_link_dst_src_write(emu,
1112                         EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1113                 emu->emu1010.output_source[1] = 18;
1114                 snd_emu1010_fpga_link_dst_src_write(emu,
1115                         EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1116                 emu->emu1010.output_source[2] = 19;
1117                 snd_emu1010_fpga_link_dst_src_write(emu,
1118                         EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1119                 emu->emu1010.output_source[3] = 20;
1120                 snd_emu1010_fpga_link_dst_src_write(emu,
1121                         EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1122                 emu->emu1010.output_source[4] = 21;
1123                 snd_emu1010_fpga_link_dst_src_write(emu,
1124                         EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1125                 emu->emu1010.output_source[5] = 22;
1126                 /* ALICE2 bus 0xa0 */
1127                 snd_emu1010_fpga_link_dst_src_write(emu,
1128                         EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0);
1129                 emu->emu1010.output_source[16] = 17;
1130                 snd_emu1010_fpga_link_dst_src_write(emu,
1131                         EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1);
1132                 emu->emu1010.output_source[17] = 18;
1133         } else {
1134                 /* ALICE2 bus 0xa0 */
1135                 snd_emu1010_fpga_link_dst_src_write(emu,
1136                         EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1137                 emu->emu1010.output_source[0] = 21;
1138                 snd_emu1010_fpga_link_dst_src_write(emu,
1139                         EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1140                 emu->emu1010.output_source[1] = 22;
1141                 snd_emu1010_fpga_link_dst_src_write(emu,
1142                         EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1143                 emu->emu1010.output_source[2] = 23;
1144                 snd_emu1010_fpga_link_dst_src_write(emu,
1145                         EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1146                 emu->emu1010.output_source[3] = 24;
1147                 snd_emu1010_fpga_link_dst_src_write(emu,
1148                         EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1149                 emu->emu1010.output_source[4] = 25;
1150                 snd_emu1010_fpga_link_dst_src_write(emu,
1151                         EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1152                 emu->emu1010.output_source[5] = 26;
1153                 snd_emu1010_fpga_link_dst_src_write(emu,
1154                         EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
1155                 emu->emu1010.output_source[6] = 27;
1156                 snd_emu1010_fpga_link_dst_src_write(emu,
1157                         EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
1158                 emu->emu1010.output_source[7] = 28;
1159                 /* ALICE2 bus 0xa0 */
1160                 snd_emu1010_fpga_link_dst_src_write(emu,
1161                         EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1162                 emu->emu1010.output_source[8] = 21;
1163                 snd_emu1010_fpga_link_dst_src_write(emu,
1164                         EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1165                 emu->emu1010.output_source[9] = 22;
1166                 /* ALICE2 bus 0xa0 */
1167                 snd_emu1010_fpga_link_dst_src_write(emu,
1168                         EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1169                 emu->emu1010.output_source[10] = 21;
1170                 snd_emu1010_fpga_link_dst_src_write(emu,
1171                         EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1172                 emu->emu1010.output_source[11] = 22;
1173                 /* ALICE2 bus 0xa0 */
1174                 snd_emu1010_fpga_link_dst_src_write(emu,
1175                         EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1176                 emu->emu1010.output_source[12] = 21;
1177                 snd_emu1010_fpga_link_dst_src_write(emu,
1178                         EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1179                 emu->emu1010.output_source[13] = 22;
1180                 /* ALICE2 bus 0xa0 */
1181                 snd_emu1010_fpga_link_dst_src_write(emu,
1182                         EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1183                 emu->emu1010.output_source[14] = 21;
1184                 snd_emu1010_fpga_link_dst_src_write(emu,
1185                         EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1186                 emu->emu1010.output_source[15] = 22;
1187                 /* ALICE2 bus 0xa0 */
1188                 snd_emu1010_fpga_link_dst_src_write(emu,
1189                         EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0);
1190                 emu->emu1010.output_source[16] = 21;
1191                 snd_emu1010_fpga_link_dst_src_write(emu,
1192                         EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
1193                 emu->emu1010.output_source[17] = 22;
1194                 snd_emu1010_fpga_link_dst_src_write(emu,
1195                         EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
1196                 emu->emu1010.output_source[18] = 23;
1197                 snd_emu1010_fpga_link_dst_src_write(emu,
1198                         EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
1199                 emu->emu1010.output_source[19] = 24;
1200                 snd_emu1010_fpga_link_dst_src_write(emu,
1201                         EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
1202                 emu->emu1010.output_source[20] = 25;
1203                 snd_emu1010_fpga_link_dst_src_write(emu,
1204                         EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1205                 emu->emu1010.output_source[21] = 26;
1206                 snd_emu1010_fpga_link_dst_src_write(emu,
1207                         EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1208                 emu->emu1010.output_source[22] = 27;
1209                 snd_emu1010_fpga_link_dst_src_write(emu,
1210                         EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1211                 emu->emu1010.output_source[23] = 28;
1212         }
1213         /* TEMP: Select SPDIF in/out */
1214         /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */
1215
1216         /* TEMP: Select 48kHz SPDIF out */
1217         snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1218         snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1219         /* Word Clock source, Internal 48kHz x1 */
1220         snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
1221         /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
1222         emu->emu1010.internal_clock = 1; /* 48000 */
1223         snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */
1224         snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1225         /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */
1226         /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */
1227         /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */
1228
1229         return 0;
1230 }
1231 /*
1232  *  Create the EMU10K1 instance
1233  */
1234
1235 #ifdef CONFIG_PM_SLEEP
1236 static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1237 static void free_pm_buffer(struct snd_emu10k1 *emu);
1238 #endif
1239
1240 static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1241 {
1242         if (emu->port) {        /* avoid access to already used hardware */
1243                 snd_emu10k1_fx8010_tram_setup(emu, 0);
1244                 snd_emu10k1_done(emu);
1245                 snd_emu10k1_free_efx(emu);
1246         }
1247         if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) {
1248                 /* Disable 48Volt power to Audio Dock */
1249                 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
1250         }
1251         cancel_delayed_work_sync(&emu->emu1010.firmware_work);
1252         release_firmware(emu->firmware);
1253         release_firmware(emu->dock_fw);
1254         if (emu->irq >= 0)
1255                 free_irq(emu->irq, emu);
1256         snd_util_memhdr_free(emu->memhdr);
1257         if (emu->silent_page.area)
1258                 snd_dma_free_pages(&emu->silent_page);
1259         if (emu->ptb_pages.area)
1260                 snd_dma_free_pages(&emu->ptb_pages);
1261         vfree(emu->page_ptr_table);
1262         vfree(emu->page_addr_table);
1263 #ifdef CONFIG_PM_SLEEP
1264         free_pm_buffer(emu);
1265 #endif
1266         if (emu->port)
1267                 pci_release_regions(emu->pci);
1268         if (emu->card_capabilities->ca0151_chip) /* P16V */
1269                 snd_p16v_free(emu);
1270         pci_disable_device(emu->pci);
1271         kfree(emu);
1272         return 0;
1273 }
1274
1275 static int snd_emu10k1_dev_free(struct snd_device *device)
1276 {
1277         struct snd_emu10k1 *emu = device->device_data;
1278         return snd_emu10k1_free(emu);
1279 }
1280
1281 static struct snd_emu_chip_details emu_chip_details[] = {
1282         /* Audigy 5/Rx SB1550 */
1283         /* Tested by michael@gernoth.net 28 Mar 2015 */
1284         /* DSP: CA10300-IAT LF
1285          * DAC: Cirrus Logic CS4382-KQZ
1286          * ADC: Philips 1361T
1287          * AC97: Sigmatel STAC9750
1288          * CA0151: None
1289          */
1290         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102,
1291          .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]",
1292          .id = "Audigy2",
1293          .emu10k2_chip = 1,
1294          .ca0108_chip = 1,
1295          .spk71 = 1,
1296          .adc_1361t = 1,  /* 24 bit capture instead of 16bit */
1297          .ac97_chip = 1},
1298         /* Audigy4 (Not PRO) SB0610 */
1299         /* Tested by James@superbug.co.uk 4th April 2006 */
1300         /* A_IOCFG bits
1301          * Output
1302          * 0: ?
1303          * 1: ?
1304          * 2: ?
1305          * 3: 0 - Digital Out, 1 - Line in
1306          * 4: ?
1307          * 5: ?
1308          * 6: ?
1309          * 7: ?
1310          * Input
1311          * 8: ?
1312          * 9: ?
1313          * A: Green jack sense (Front)
1314          * B: ?
1315          * C: Black jack sense (Rear/Side Right)
1316          * D: Yellow jack sense (Center/LFE/Side Left)
1317          * E: ?
1318          * F: ?
1319          *
1320          * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1321          * 0 - Digital Out
1322          * 1 - Line in
1323          */
1324         /* Mic input not tested.
1325          * Analog CD input not tested
1326          * Digital Out not tested.
1327          * Line in working.
1328          * Audio output 5.1 working. Side outputs not working.
1329          */
1330         /* DSP: CA10300-IAT LF
1331          * DAC: Cirrus Logic CS4382-KQZ
1332          * ADC: Philips 1361T
1333          * AC97: Sigmatel STAC9750
1334          * CA0151: None
1335          */
1336         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1337          .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]",
1338          .id = "Audigy2",
1339          .emu10k2_chip = 1,
1340          .ca0108_chip = 1,
1341          .spk71 = 1,
1342          .adc_1361t = 1,  /* 24 bit capture instead of 16bit */
1343          .ac97_chip = 1} ,
1344         /* Audigy 2 Value AC3 out does not work yet.
1345          * Need to find out how to turn off interpolators.
1346          */
1347         /* Tested by James@superbug.co.uk 3rd July 2005 */
1348         /* DSP: CA0108-IAT
1349          * DAC: CS4382-KQ
1350          * ADC: Philips 1361T
1351          * AC97: STAC9750
1352          * CA0151: None
1353          */
1354         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1355          .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
1356          .id = "Audigy2",
1357          .emu10k2_chip = 1,
1358          .ca0108_chip = 1,
1359          .spk71 = 1,
1360          .ac97_chip = 1} ,
1361         /* Audigy 2 ZS Notebook Cardbus card.*/
1362         /* Tested by James@superbug.co.uk 6th November 2006 */
1363         /* Audio output 7.1/Headphones working.
1364          * Digital output working. (AC3 not checked, only PCM)
1365          * Audio Mic/Line inputs working.
1366          * Digital input not tested.
1367          */
1368         /* DSP: Tina2
1369          * DAC: Wolfson WM8768/WM8568
1370          * ADC: Wolfson WM8775
1371          * AC97: None
1372          * CA0151: None
1373          */
1374         /* Tested by James@superbug.co.uk 4th April 2006 */
1375         /* A_IOCFG bits
1376          * Output
1377          * 0: Not Used
1378          * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
1379          * 2: Analog input 0 = line in, 1 = mic in
1380          * 3: Not Used
1381          * 4: Digital output 0 = off, 1 = on.
1382          * 5: Not Used
1383          * 6: Not Used
1384          * 7: Not Used
1385          * Input
1386          *      All bits 1 (0x3fxx) means nothing plugged in.
1387          * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
1388          * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
1389          * C-D: 2 = Front/Rear/etc, 3 = nothing.
1390          * E-F: Always 0
1391          *
1392          */
1393         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1394          .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1395          .id = "Audigy2",
1396          .emu10k2_chip = 1,
1397          .ca0108_chip = 1,
1398          .ca_cardbus_chip = 1,
1399          .spi_dac = 1,
1400          .i2c_adc = 1,
1401          .spk71 = 1} ,
1402         /* Tested by James@superbug.co.uk 4th Nov 2007. */
1403         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
1404          .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
1405          .id = "EMU1010",
1406          .emu10k2_chip = 1,
1407          .ca0108_chip = 1,
1408          .ca_cardbus_chip = 1,
1409          .spk71 = 1 ,
1410          .emu_model = EMU_MODEL_EMU1616},
1411         /* Tested by James@superbug.co.uk 4th Nov 2007. */
1412         /* This is MAEM8960, 0202 is MAEM 8980 */
1413         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
1414          .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
1415          .id = "EMU1010",
1416          .emu10k2_chip = 1,
1417          .ca0108_chip = 1,
1418          .spk71 = 1,
1419          .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
1420         /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
1421         /* This is MAEM8986, 0202 is MAEM8980 */
1422         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
1423          .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
1424          .id = "EMU1010",
1425          .emu10k2_chip = 1,
1426          .ca0108_chip = 1,
1427          .spk71 = 1,
1428          .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
1429         /* Tested by James@superbug.co.uk 8th July 2005. */
1430         /* This is MAEM8810, 0202 is MAEM8820 */
1431         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
1432          .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
1433          .id = "EMU1010",
1434          .emu10k2_chip = 1,
1435          .ca0102_chip = 1,
1436          .spk71 = 1,
1437          .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
1438         /* EMU0404b */
1439         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
1440          .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
1441          .id = "EMU0404",
1442          .emu10k2_chip = 1,
1443          .ca0108_chip = 1,
1444          .spk71 = 1,
1445          .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
1446         /* Tested by James@superbug.co.uk 20-3-2007. */
1447         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
1448          .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
1449          .id = "EMU0404",
1450          .emu10k2_chip = 1,
1451          .ca0102_chip = 1,
1452          .spk71 = 1,
1453          .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
1454         /* EMU0404 PCIe */
1455         {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
1456          .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
1457          .id = "EMU0404",
1458          .emu10k2_chip = 1,
1459          .ca0108_chip = 1,
1460          .spk71 = 1,
1461          .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
1462         /* Note that all E-mu cards require kernel 2.6 or newer. */
1463         {.vendor = 0x1102, .device = 0x0008,
1464          .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
1465          .id = "Audigy2",
1466          .emu10k2_chip = 1,
1467          .ca0108_chip = 1,
1468          .ac97_chip = 1} ,
1469         /* Tested by James@superbug.co.uk 3rd July 2005 */
1470         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1471          .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]",
1472          .id = "Audigy2",
1473          .emu10k2_chip = 1,
1474          .ca0102_chip = 1,
1475          .ca0151_chip = 1,
1476          .spk71 = 1,
1477          .spdif_bug = 1,
1478          .ac97_chip = 1} ,
1479         /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
1480         /* The 0x20061102 does have SB0350 written on it
1481          * Just like 0x20021102
1482          */
1483         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
1484          .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]",
1485          .id = "Audigy2",
1486          .emu10k2_chip = 1,
1487          .ca0102_chip = 1,
1488          .ca0151_chip = 1,
1489          .spk71 = 1,
1490          .spdif_bug = 1,
1491          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1492          .ac97_chip = 1} ,
1493         /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by
1494            Creative's Windows driver */
1495         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102,
1496          .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]",
1497          .id = "Audigy2",
1498          .emu10k2_chip = 1,
1499          .ca0102_chip = 1,
1500          .ca0151_chip = 1,
1501          .spk71 = 1,
1502          .spdif_bug = 1,
1503          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1504          .ac97_chip = 1} ,
1505         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1506          .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]",
1507          .id = "Audigy2",
1508          .emu10k2_chip = 1,
1509          .ca0102_chip = 1,
1510          .ca0151_chip = 1,
1511          .spk71 = 1,
1512          .spdif_bug = 1,
1513          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1514          .ac97_chip = 1} ,
1515         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1516          .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]",
1517          .id = "Audigy2",
1518          .emu10k2_chip = 1,
1519          .ca0102_chip = 1,
1520          .ca0151_chip = 1,
1521          .spk71 = 1,
1522          .spdif_bug = 1,
1523          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1524          .ac97_chip = 1} ,
1525         /* Audigy 2 */
1526         /* Tested by James@superbug.co.uk 3rd July 2005 */
1527         /* DSP: CA0102-IAT
1528          * DAC: CS4382-KQ
1529          * ADC: Philips 1361T
1530          * AC97: STAC9721
1531          * CA0151: Yes
1532          */
1533         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1534          .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]",
1535          .id = "Audigy2",
1536          .emu10k2_chip = 1,
1537          .ca0102_chip = 1,
1538          .ca0151_chip = 1,
1539          .spk71 = 1,
1540          .spdif_bug = 1,
1541          .adc_1361t = 1,  /* 24 bit capture instead of 16bit */
1542          .ac97_chip = 1} ,
1543         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1544          .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
1545          .id = "Audigy2",
1546          .emu10k2_chip = 1,
1547          .ca0102_chip = 1,
1548          .ca0151_chip = 1,
1549          .spk71 = 1,
1550          .spdif_bug = 1} ,
1551         /* Dell OEM/Creative Labs Audigy 2 ZS */
1552         /* See ALSA bug#1365 */
1553         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1554          .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]",
1555          .id = "Audigy2",
1556          .emu10k2_chip = 1,
1557          .ca0102_chip = 1,
1558          .ca0151_chip = 1,
1559          .spk71 = 1,
1560          .spdif_bug = 1,
1561          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1562          .ac97_chip = 1} ,
1563         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1564          .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
1565          .id = "Audigy2",
1566          .emu10k2_chip = 1,
1567          .ca0102_chip = 1,
1568          .ca0151_chip = 1,
1569          .spk71 = 1,
1570          .spdif_bug = 1,
1571          .invert_shared_spdif = 1,      /* digital/analog switch swapped */
1572          .adc_1361t = 1,  /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1573          .ac97_chip = 1} ,
1574         {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1575          .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]",
1576          .id = "Audigy2",
1577          .emu10k2_chip = 1,
1578          .ca0102_chip = 1,
1579          .ca0151_chip = 1,
1580          .spdif_bug = 1,
1581          .ac97_chip = 1} ,
1582         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1583          .driver = "Audigy", .name = "SB Audigy 1 [SB0092]",
1584          .id = "Audigy",
1585          .emu10k2_chip = 1,
1586          .ca0102_chip = 1,
1587          .ac97_chip = 1} ,
1588         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1589          .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]",
1590          .id = "Audigy",
1591          .emu10k2_chip = 1,
1592          .ca0102_chip = 1,
1593          .spdif_bug = 1,
1594          .ac97_chip = 1} ,
1595         {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1596          .driver = "Audigy", .name = "SB Audigy 1 [SB0090]",
1597          .id = "Audigy",
1598          .emu10k2_chip = 1,
1599          .ca0102_chip = 1,
1600          .ac97_chip = 1} ,
1601         {.vendor = 0x1102, .device = 0x0004,
1602          .driver = "Audigy", .name = "Audigy 1 [Unknown]",
1603          .id = "Audigy",
1604          .emu10k2_chip = 1,
1605          .ca0102_chip = 1,
1606          .ac97_chip = 1} ,
1607         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1608          .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1609          .id = "Live",
1610          .emu10k1_chip = 1,
1611          .ac97_chip = 1,
1612          .sblive51 = 1} ,
1613         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102,
1614          .driver = "EMU10K1", .name = "SB Live! [SB0105]",
1615          .id = "Live",
1616          .emu10k1_chip = 1,
1617          .ac97_chip = 1,
1618          .sblive51 = 1} ,
1619         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102,
1620          .driver = "EMU10K1", .name = "SB Live! Value [SB0103]",
1621          .id = "Live",
1622          .emu10k1_chip = 1,
1623          .ac97_chip = 1,
1624          .sblive51 = 1} ,
1625         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1626          .driver = "EMU10K1", .name = "SB Live! Value [SB0101]",
1627          .id = "Live",
1628          .emu10k1_chip = 1,
1629          .ac97_chip = 1,
1630          .sblive51 = 1} ,
1631         /* Tested by ALSA bug#1680 26th December 2005 */
1632         /* note: It really has SB0220 written on the card, */
1633         /* but it's SB0228 according to kx.inf */
1634         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1635          .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]",
1636          .id = "Live",
1637          .emu10k1_chip = 1,
1638          .ac97_chip = 1,
1639          .sblive51 = 1} ,
1640         /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1641         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1642          .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1643          .id = "Live",
1644          .emu10k1_chip = 1,
1645          .ac97_chip = 1,
1646          .sblive51 = 1} ,
1647         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1648          .driver = "EMU10K1", .name = "SB Live! 5.1",
1649          .id = "Live",
1650          .emu10k1_chip = 1,
1651          .ac97_chip = 1,
1652          .sblive51 = 1} ,
1653         /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
1654         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
1655          .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]",
1656          .id = "Live",
1657          .emu10k1_chip = 1,
1658          .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1659                           * share the same IDs!
1660                           */
1661          .sblive51 = 1} ,
1662         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1663          .driver = "EMU10K1", .name = "SB Live! Value [CT4850]",
1664          .id = "Live",
1665          .emu10k1_chip = 1,
1666          .ac97_chip = 1,
1667          .sblive51 = 1} ,
1668         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1669          .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
1670          .id = "Live",
1671          .emu10k1_chip = 1,
1672          .ac97_chip = 1} ,
1673         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1674          .driver = "EMU10K1", .name = "SB Live! Value [CT4871]",
1675          .id = "Live",
1676          .emu10k1_chip = 1,
1677          .ac97_chip = 1,
1678          .sblive51 = 1} ,
1679         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1680          .driver = "EMU10K1", .name = "SB Live! Value [CT4831]",
1681          .id = "Live",
1682          .emu10k1_chip = 1,
1683          .ac97_chip = 1,
1684          .sblive51 = 1} ,
1685         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1686          .driver = "EMU10K1", .name = "SB Live! Value [CT4870]",
1687          .id = "Live",
1688          .emu10k1_chip = 1,
1689          .ac97_chip = 1,
1690          .sblive51 = 1} ,
1691         /* Tested by James@superbug.co.uk 3rd July 2005 */
1692         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1693          .driver = "EMU10K1", .name = "SB Live! Value [CT4832]",
1694          .id = "Live",
1695          .emu10k1_chip = 1,
1696          .ac97_chip = 1,
1697          .sblive51 = 1} ,
1698         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1699          .driver = "EMU10K1", .name = "SB Live! Value [CT4830]",
1700          .id = "Live",
1701          .emu10k1_chip = 1,
1702          .ac97_chip = 1,
1703          .sblive51 = 1} ,
1704         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1705          .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
1706          .id = "Live",
1707          .emu10k1_chip = 1,
1708          .ac97_chip = 1,
1709          .sblive51 = 1} ,
1710         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1711          .driver = "EMU10K1", .name = "SB Live! Value [CT4780]",
1712          .id = "Live",
1713          .emu10k1_chip = 1,
1714          .ac97_chip = 1,
1715          .sblive51 = 1} ,
1716         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1717          .driver = "EMU10K1", .name = "E-mu APS [PC545]",
1718          .id = "APS",
1719          .emu10k1_chip = 1,
1720          .ecard = 1} ,
1721         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1722          .driver = "EMU10K1", .name = "SB Live! [CT4620]",
1723          .id = "Live",
1724          .emu10k1_chip = 1,
1725          .ac97_chip = 1,
1726          .sblive51 = 1} ,
1727         {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1728          .driver = "EMU10K1", .name = "SB Live! Value [CT4670]",
1729          .id = "Live",
1730          .emu10k1_chip = 1,
1731          .ac97_chip = 1,
1732          .sblive51 = 1} ,
1733         {.vendor = 0x1102, .device = 0x0002,
1734          .driver = "EMU10K1", .name = "SB Live! [Unknown]",
1735          .id = "Live",
1736          .emu10k1_chip = 1,
1737          .ac97_chip = 1,
1738          .sblive51 = 1} ,
1739         { } /* terminator */
1740 };
1741
1742 /*
1743  * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too)
1744  * has a problem that from time to time it likes to do few DMA reads a bit
1745  * beyond its normal allocation and gets very confused if these reads get
1746  * blocked by a IOMMU.
1747  *
1748  * This behaviour has been observed for the first (reserved) page
1749  * (for which it happens multiple times at every playback), often for various
1750  * synth pages and sometimes for PCM playback buffers and the page table
1751  * memory itself.
1752  *
1753  * As a workaround let's widen these DMA allocations by an extra page if we
1754  * detect that the device is behind a non-passthrough IOMMU.
1755  */
1756 static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu)
1757 {
1758         struct iommu_domain *domain;
1759
1760         emu->iommu_workaround = false;
1761
1762         if (!iommu_present(emu->card->dev->bus))
1763                 return;
1764
1765         domain = iommu_get_domain_for_dev(emu->card->dev);
1766         if (domain && domain->type == IOMMU_DOMAIN_IDENTITY)
1767                 return;
1768
1769         dev_notice(emu->card->dev,
1770                    "non-passthrough IOMMU detected, widening DMA allocations");
1771         emu->iommu_workaround = true;
1772 }
1773
1774 int snd_emu10k1_create(struct snd_card *card,
1775                        struct pci_dev *pci,
1776                        unsigned short extin_mask,
1777                        unsigned short extout_mask,
1778                        long max_cache_bytes,
1779                        int enable_ir,
1780                        uint subsystem,
1781                        struct snd_emu10k1 **remu)
1782 {
1783         struct snd_emu10k1 *emu;
1784         int idx, err;
1785         int is_audigy;
1786         size_t page_table_size;
1787         unsigned int silent_page;
1788         const struct snd_emu_chip_details *c;
1789         static struct snd_device_ops ops = {
1790                 .dev_free =     snd_emu10k1_dev_free,
1791         };
1792
1793         *remu = NULL;
1794
1795         /* enable PCI device */
1796         err = pci_enable_device(pci);
1797         if (err < 0)
1798                 return err;
1799
1800         emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1801         if (emu == NULL) {
1802                 pci_disable_device(pci);
1803                 return -ENOMEM;
1804         }
1805         emu->card = card;
1806         spin_lock_init(&emu->reg_lock);
1807         spin_lock_init(&emu->emu_lock);
1808         spin_lock_init(&emu->spi_lock);
1809         spin_lock_init(&emu->i2c_lock);
1810         spin_lock_init(&emu->voice_lock);
1811         spin_lock_init(&emu->synth_lock);
1812         spin_lock_init(&emu->memblk_lock);
1813         mutex_init(&emu->fx8010.lock);
1814         INIT_LIST_HEAD(&emu->mapped_link_head);
1815         INIT_LIST_HEAD(&emu->mapped_order_link_head);
1816         emu->pci = pci;
1817         emu->irq = -1;
1818         emu->synth = NULL;
1819         emu->get_synth_voice = NULL;
1820         INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);
1821         /* read revision & serial */
1822         emu->revision = pci->revision;
1823         pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1824         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1825         dev_dbg(card->dev,
1826                 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n",
1827                 pci->vendor, pci->device, emu->serial, emu->model);
1828
1829         for (c = emu_chip_details; c->vendor; c++) {
1830                 if (c->vendor == pci->vendor && c->device == pci->device) {
1831                         if (subsystem) {
1832                                 if (c->subsystem && (c->subsystem == subsystem))
1833                                         break;
1834                                 else
1835                                         continue;
1836                         } else {
1837                                 if (c->subsystem && (c->subsystem != emu->serial))
1838                                         continue;
1839                                 if (c->revision && c->revision != emu->revision)
1840                                         continue;
1841                         }
1842                         break;
1843                 }
1844         }
1845         if (c->vendor == 0) {
1846                 dev_err(card->dev, "emu10k1: Card not recognised\n");
1847                 kfree(emu);
1848                 pci_disable_device(pci);
1849                 return -ENOENT;
1850         }
1851         emu->card_capabilities = c;
1852         if (c->subsystem && !subsystem)
1853                 dev_dbg(card->dev, "Sound card name = %s\n", c->name);
1854         else if (subsystem)
1855                 dev_dbg(card->dev, "Sound card name = %s, "
1856                         "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. "
1857                         "Forced to subsystem = 0x%x\n", c->name,
1858                         pci->vendor, pci->device, emu->serial, c->subsystem);
1859         else
1860                 dev_dbg(card->dev, "Sound card name = %s, "
1861                         "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n",
1862                         c->name, pci->vendor, pci->device,
1863                         emu->serial);
1864
1865         if (!*card->id && c->id)
1866                 strlcpy(card->id, c->id, sizeof(card->id));
1867
1868         is_audigy = emu->audigy = c->emu10k2_chip;
1869
1870         snd_emu10k1_detect_iommu(emu);
1871
1872         /* set addressing mode */
1873         emu->address_mode = is_audigy ? 0 : 1;
1874         /* set the DMA transfer mask */
1875         emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK;
1876         if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) {
1877                 dev_err(card->dev,
1878                         "architecture does not support PCI busmaster DMA with mask 0x%lx\n",
1879                         emu->dma_mask);
1880                 kfree(emu);
1881                 pci_disable_device(pci);
1882                 return -ENXIO;
1883         }
1884         if (is_audigy)
1885                 emu->gpr_base = A_FXGPREGBASE;
1886         else
1887                 emu->gpr_base = FXGPREGBASE;
1888
1889         err = pci_request_regions(pci, "EMU10K1");
1890         if (err < 0) {
1891                 kfree(emu);
1892                 pci_disable_device(pci);
1893                 return err;
1894         }
1895         emu->port = pci_resource_start(pci, 0);
1896
1897         emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1898
1899         page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 :
1900                                          MAXPAGES0);
1901         if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size,
1902                                                 &emu->ptb_pages) < 0) {
1903                 err = -ENOMEM;
1904                 goto error;
1905         }
1906         dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n",
1907                 (unsigned long)emu->ptb_pages.addr,
1908                 (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes));
1909
1910         emu->page_ptr_table = vmalloc(array_size(sizeof(void *),
1911                                                  emu->max_cache_pages));
1912         emu->page_addr_table = vmalloc(array_size(sizeof(unsigned long),
1913                                                   emu->max_cache_pages));
1914         if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
1915                 err = -ENOMEM;
1916                 goto error;
1917         }
1918
1919         if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE,
1920                                                 &emu->silent_page) < 0) {
1921                 err = -ENOMEM;
1922                 goto error;
1923         }
1924         dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n",
1925                 (unsigned long)emu->silent_page.addr,
1926                 (unsigned long)(emu->silent_page.addr +
1927                                 emu->silent_page.bytes));
1928
1929         emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1930         if (emu->memhdr == NULL) {
1931                 err = -ENOMEM;
1932                 goto error;
1933         }
1934         emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1935                 sizeof(struct snd_util_memblk);
1936
1937         pci_set_master(pci);
1938
1939         emu->fx8010.fxbus_mask = 0x303f;
1940         if (extin_mask == 0)
1941                 extin_mask = 0x3fcf;
1942         if (extout_mask == 0)
1943                 extout_mask = 0x7fff;
1944         emu->fx8010.extin_mask = extin_mask;
1945         emu->fx8010.extout_mask = extout_mask;
1946         emu->enable_ir = enable_ir;
1947
1948         if (emu->card_capabilities->ca_cardbus_chip) {
1949                 err = snd_emu10k1_cardbus_init(emu);
1950                 if (err < 0)
1951                         goto error;
1952         }
1953         if (emu->card_capabilities->ecard) {
1954                 err = snd_emu10k1_ecard_init(emu);
1955                 if (err < 0)
1956                         goto error;
1957         } else if (emu->card_capabilities->emu_model) {
1958                 err = snd_emu10k1_emu1010_init(emu);
1959                 if (err < 0) {
1960                         snd_emu10k1_free(emu);
1961                         return err;
1962                 }
1963         } else {
1964                 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1965                         does not support this, it shouldn't do any harm */
1966                 snd_emu10k1_ptr_write(emu, AC97SLOT, 0,
1967                                         AC97SLOT_CNTR|AC97SLOT_LFE);
1968         }
1969
1970         /* initialize TRAM setup */
1971         emu->fx8010.itram_size = (16 * 1024)/2;
1972         emu->fx8010.etram_pages.area = NULL;
1973         emu->fx8010.etram_pages.bytes = 0;
1974
1975         /* irq handler must be registered after I/O ports are activated */
1976         if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
1977                         KBUILD_MODNAME, emu)) {
1978                 err = -EBUSY;
1979                 goto error;
1980         }
1981         emu->irq = pci->irq;
1982
1983         /*
1984          *  Init to 0x02109204 :
1985          *  Clock accuracy    = 0     (1000ppm)
1986          *  Sample Rate       = 2     (48kHz)
1987          *  Audio Channel     = 1     (Left of 2)
1988          *  Source Number     = 0     (Unspecified)
1989          *  Generation Status = 1     (Original for Cat Code 12)
1990          *  Cat Code          = 12    (Digital Signal Mixer)
1991          *  Mode              = 0     (Mode 0)
1992          *  Emphasis          = 0     (None)
1993          *  CP                = 1     (Copyright unasserted)
1994          *  AN                = 0     (Audio data)
1995          *  P                 = 0     (Consumer)
1996          */
1997         emu->spdif_bits[0] = emu->spdif_bits[1] =
1998                 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1999                 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
2000                 SPCS_GENERATIONSTATUS | 0x00001200 |
2001                 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
2002
2003         /* Clear silent pages and set up pointers */
2004         memset(emu->silent_page.area, 0, emu->silent_page.bytes);
2005         silent_page = emu->silent_page.addr << emu->address_mode;
2006         for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++)
2007                 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
2008
2009         /* set up voice indices */
2010         for (idx = 0; idx < NUM_G; idx++) {
2011                 emu->voices[idx].emu = emu;
2012                 emu->voices[idx].number = idx;
2013         }
2014
2015         err = snd_emu10k1_init(emu, enable_ir, 0);
2016         if (err < 0)
2017                 goto error;
2018 #ifdef CONFIG_PM_SLEEP
2019         err = alloc_pm_buffer(emu);
2020         if (err < 0)
2021                 goto error;
2022 #endif
2023
2024         /*  Initialize the effect engine */
2025         err = snd_emu10k1_init_efx(emu);
2026         if (err < 0)
2027                 goto error;
2028         snd_emu10k1_audio_enable(emu);
2029
2030         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops);
2031         if (err < 0)
2032                 goto error;
2033
2034 #ifdef CONFIG_SND_PROC_FS
2035         snd_emu10k1_proc_init(emu);
2036 #endif
2037
2038         *remu = emu;
2039         return 0;
2040
2041  error:
2042         snd_emu10k1_free(emu);
2043         return err;
2044 }
2045
2046 #ifdef CONFIG_PM_SLEEP
2047 static unsigned char saved_regs[] = {
2048         CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
2049         FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
2050         ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
2051         TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
2052         MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
2053         SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
2054         0xff /* end */
2055 };
2056 static unsigned char saved_regs_audigy[] = {
2057         A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
2058         A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
2059         0xff /* end */
2060 };
2061
2062 static int alloc_pm_buffer(struct snd_emu10k1 *emu)
2063 {
2064         int size;
2065
2066         size = ARRAY_SIZE(saved_regs);
2067         if (emu->audigy)
2068                 size += ARRAY_SIZE(saved_regs_audigy);
2069         emu->saved_ptr = vmalloc(array3_size(4, NUM_G, size));
2070         if (!emu->saved_ptr)
2071                 return -ENOMEM;
2072         if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
2073                 return -ENOMEM;
2074         if (emu->card_capabilities->ca0151_chip &&
2075             snd_p16v_alloc_pm_buffer(emu) < 0)
2076                 return -ENOMEM;
2077         return 0;
2078 }
2079
2080 static void free_pm_buffer(struct snd_emu10k1 *emu)
2081 {
2082         vfree(emu->saved_ptr);
2083         snd_emu10k1_efx_free_pm_buffer(emu);
2084         if (emu->card_capabilities->ca0151_chip)
2085                 snd_p16v_free_pm_buffer(emu);
2086 }
2087
2088 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
2089 {
2090         int i;
2091         unsigned char *reg;
2092         unsigned int *val;
2093
2094         val = emu->saved_ptr;
2095         for (reg = saved_regs; *reg != 0xff; reg++)
2096                 for (i = 0; i < NUM_G; i++, val++)
2097                         *val = snd_emu10k1_ptr_read(emu, *reg, i);
2098         if (emu->audigy) {
2099                 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2100                         for (i = 0; i < NUM_G; i++, val++)
2101                                 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2102         }
2103         if (emu->audigy)
2104                 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
2105         emu->saved_hcfg = inl(emu->port + HCFG);
2106 }
2107
2108 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
2109 {
2110         if (emu->card_capabilities->ca_cardbus_chip)
2111                 snd_emu10k1_cardbus_init(emu);
2112         if (emu->card_capabilities->ecard)
2113                 snd_emu10k1_ecard_init(emu);
2114         else if (emu->card_capabilities->emu_model)
2115                 snd_emu10k1_emu1010_init(emu);
2116         else
2117                 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
2118         snd_emu10k1_init(emu, emu->enable_ir, 1);
2119 }
2120
2121 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
2122 {
2123         int i;
2124         unsigned char *reg;
2125         unsigned int *val;
2126
2127         snd_emu10k1_audio_enable(emu);
2128
2129         /* resore for spdif */
2130         if (emu->audigy)
2131                 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
2132         outl(emu->saved_hcfg, emu->port + HCFG);
2133
2134         val = emu->saved_ptr;
2135         for (reg = saved_regs; *reg != 0xff; reg++)
2136                 for (i = 0; i < NUM_G; i++, val++)
2137                         snd_emu10k1_ptr_write(emu, *reg, i, *val);
2138         if (emu->audigy) {
2139                 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2140                         for (i = 0; i < NUM_G; i++, val++)
2141                                 snd_emu10k1_ptr_write(emu, *reg, i, *val);
2142         }
2143 }
2144 #endif