2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Routines for control of EMU10K1 chips
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added support for Audigy 2 Value.
8 * Added EMU 1010 support.
9 * General bug fixes and enhancements.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include <linux/sched.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/mutex.h>
45 #include <sound/core.h>
46 #include <sound/emu10k1.h>
47 #include <linux/firmware.h>
53 #define HANA_FILENAME "/*(DEBLOBBED)*/"
54 #define DOCK_FILENAME "/*(DEBLOBBED)*/"
55 #define EMU1010B_FILENAME "/*(DEBLOBBED)*/"
56 #define MICRO_DOCK_FILENAME "/*(DEBLOBBED)*/"
57 #define EMU0404_FILENAME "/*(DEBLOBBED)*/"
58 #define EMU1010_NOTEBOOK_FILENAME "/*(DEBLOBBED)*/"
63 /*************************************************************************
65 *************************************************************************/
67 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
69 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
70 snd_emu10k1_ptr_write(emu, IP, ch, 0);
71 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
72 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
73 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
74 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
75 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
77 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
78 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
79 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
80 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
81 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
82 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
84 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
85 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
86 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
87 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
88 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
89 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
90 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
91 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
93 /*** these are last so OFF prevents writing ***/
94 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
95 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
96 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
97 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
98 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
100 /* Audigy extra stuffs */
102 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
103 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
104 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
105 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
106 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
107 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
108 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
112 static unsigned int spi_dac_init[] = {
136 static unsigned int i2c_adc_init[][2] = {
137 { 0x17, 0x00 }, /* Reset */
138 { 0x07, 0x00 }, /* Timeout */
139 { 0x0b, 0x22 }, /* Interface control */
140 { 0x0c, 0x22 }, /* Master mode control */
141 { 0x0d, 0x08 }, /* Powerdown control */
142 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
143 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
144 { 0x10, 0x7b }, /* ALC Control 1 */
145 { 0x11, 0x00 }, /* ALC Control 2 */
146 { 0x12, 0x32 }, /* ALC Control 3 */
147 { 0x13, 0x00 }, /* Noise gate control */
148 { 0x14, 0xa6 }, /* Limiter control */
149 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */
152 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
154 unsigned int silent_page;
158 /* disable audio and lock cache */
159 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
160 HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
162 /* reset recording buffers */
163 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
164 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
165 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
166 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
167 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
168 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
170 /* disable channel interrupt */
171 outl(0, emu->port + INTE);
172 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
173 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
174 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
175 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
178 /* set SPDIF bypass mode */
179 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
180 /* enable rear left + rear right AC97 slots */
181 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
185 /* init envelope engine */
186 for (ch = 0; ch < NUM_G; ch++)
187 snd_emu10k1_voice_init(emu, ch);
189 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
190 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
191 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
193 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
194 /* Hacks for Alice3 to work independent of haP16V driver */
195 /* Setup SRCMulti_I2S SamplingRate */
196 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
199 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
201 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
202 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
203 /* Setup SRCMulti Input Audio Enable */
204 /* Use 0xFFFFFFFF to enable P16V sounds. */
205 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
207 /* Enabled Phased (8-channel) P16V playback */
208 outl(0x0201, emu->port + HCFG2);
209 /* Set playback routing. */
210 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
212 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
213 /* Hacks for Alice3 to work independent of haP16V driver */
214 dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
215 /* Setup SRCMulti_I2S SamplingRate */
216 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
219 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
221 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
222 outl(0x600000, emu->port + 0x20);
223 outl(0x14, emu->port + 0x24);
225 /* Setup SRCMulti Input Audio Enable */
226 outl(0x7b0000, emu->port + 0x20);
227 outl(0xFF000000, emu->port + 0x24);
229 /* Setup SPDIF Out Audio Enable */
230 /* The Audigy 2 Value has a separate SPDIF out,
231 * so no need for a mixer switch
233 outl(0x7a0000, emu->port + 0x20);
234 outl(0xFF000000, emu->port + 0x24);
235 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
236 outl(tmp, emu->port + A_IOCFG);
238 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
241 size = ARRAY_SIZE(spi_dac_init);
242 for (n = 0; n < size; n++)
243 snd_emu10k1_spi_write(emu, spi_dac_init[n]);
245 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
248 * GPIO1: Speakers-enabled.
251 * GPIO4: IEC958 Output on.
256 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
258 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
261 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
262 tmp = inl(emu->port + A_IOCFG);
263 outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
264 tmp = inl(emu->port + A_IOCFG);
265 size = ARRAY_SIZE(i2c_adc_init);
266 for (n = 0; n < size; n++)
267 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
268 for (n = 0; n < 4; n++) {
269 emu->i2c_capture_volume[n][0] = 0xcf;
270 emu->i2c_capture_volume[n][1] = 0xcf;
275 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
276 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
277 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
279 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
280 for (ch = 0; ch < NUM_G; ch++) {
281 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
282 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
285 if (emu->card_capabilities->emu_model) {
286 outl(HCFG_AUTOMUTE_ASYNC |
288 HCFG_AUDIOENABLE, emu->port + HCFG);
291 * Mute Disable Audio = 0
292 * Lock Tank Memory = 1
293 * Lock Sound Memory = 0
296 } else if (emu->audigy) {
297 if (emu->revision == 4) /* audigy2 */
298 outl(HCFG_AUDIOENABLE |
299 HCFG_AC3ENABLE_CDSPDIF |
300 HCFG_AC3ENABLE_GPSPDIF |
301 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
303 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
304 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
305 * e.g. card_capabilities->joystick */
306 } else if (emu->model == 0x20 ||
307 emu->model == 0xc400 ||
308 (emu->model == 0x21 && emu->revision < 6))
309 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
311 /* With on-chip joystick */
312 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
314 if (enable_ir) { /* enable IR for SB Live */
315 if (emu->card_capabilities->emu_model) {
316 ; /* Disable all access to A_IOCFG for the emu1010 */
317 } else if (emu->card_capabilities->i2c_adc) {
318 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
319 } else if (emu->audigy) {
320 unsigned int reg = inl(emu->port + A_IOCFG);
321 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
323 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
325 outl(reg, emu->port + A_IOCFG);
327 unsigned int reg = inl(emu->port + HCFG);
328 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
330 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
332 outl(reg, emu->port + HCFG);
336 if (emu->card_capabilities->emu_model) {
337 ; /* Disable all access to A_IOCFG for the emu1010 */
338 } else if (emu->card_capabilities->i2c_adc) {
339 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
340 } else if (emu->audigy) { /* enable analog output */
341 unsigned int reg = inl(emu->port + A_IOCFG);
342 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
345 if (emu->address_mode == 0) {
347 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG);
353 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
356 * Enable the audio bit
358 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
360 /* Enable analog/digital outs on audigy */
361 if (emu->card_capabilities->emu_model) {
362 ; /* Disable all access to A_IOCFG for the emu1010 */
363 } else if (emu->card_capabilities->i2c_adc) {
364 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
365 } else if (emu->audigy) {
366 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
368 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
369 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
370 * This has to be done after init ALice3 I2SOut beyond 48KHz.
371 * So, sequence is important. */
372 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
373 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
374 /* Unmute Analog now. */
375 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
377 /* Disable routing from AC97 line out to Front speakers */
378 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
385 /* FIXME: the following routine disables LiveDrive-II !! */
386 /* TOSLink detection */
388 tmp = inl(emu->port + HCFG);
389 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
390 outl(tmp|0x800, emu->port + HCFG);
392 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
394 outl(tmp, emu->port + HCFG);
400 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
403 int snd_emu10k1_done(struct snd_emu10k1 *emu)
407 outl(0, emu->port + INTE);
412 for (ch = 0; ch < NUM_G; ch++)
413 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
414 for (ch = 0; ch < NUM_G; ch++) {
415 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
416 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
417 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
418 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
421 /* reset recording buffers */
422 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
423 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
424 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
425 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
426 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
427 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
428 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
429 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
430 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
432 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
434 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
436 /* disable channel interrupt */
437 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
438 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
439 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
440 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
442 /* disable audio and lock cache */
443 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
444 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
449 /*************************************************************************
450 * ECARD functional implementation
451 *************************************************************************/
453 /* In A1 Silicon, these bits are in the HC register */
454 #define HOOKN_BIT (1L << 12)
455 #define HANDN_BIT (1L << 11)
456 #define PULSEN_BIT (1L << 10)
458 #define EC_GDI1 (1 << 13)
459 #define EC_GDI0 (1 << 14)
461 #define EC_NUM_CONTROL_BITS 20
463 #define EC_AC3_DATA_SELN 0x0001L
464 #define EC_EE_DATA_SEL 0x0002L
465 #define EC_EE_CNTRL_SELN 0x0004L
466 #define EC_EECLK 0x0008L
467 #define EC_EECS 0x0010L
468 #define EC_EESDO 0x0020L
469 #define EC_TRIM_CSN 0x0040L
470 #define EC_TRIM_SCLK 0x0080L
471 #define EC_TRIM_SDATA 0x0100L
472 #define EC_TRIM_MUTEN 0x0200L
473 #define EC_ADCCAL 0x0400L
474 #define EC_ADCRSTN 0x0800L
475 #define EC_DACCAL 0x1000L
476 #define EC_DACMUTEN 0x2000L
477 #define EC_LEDN 0x4000L
479 #define EC_SPDIF0_SEL_SHIFT 15
480 #define EC_SPDIF1_SEL_SHIFT 17
481 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
482 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
483 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
484 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
485 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
486 * be incremented any time the EEPROM's
487 * format is changed. */
489 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
491 /* Addresses for special values stored in to EEPROM */
492 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
493 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
494 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
496 #define EC_LAST_PROMFILE_ADDR 0x2f
498 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
499 * can be up to 30 characters in length
500 * and is stored as a NULL-terminated
501 * ASCII string. Any unused bytes must be
502 * filled with zeros */
503 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
506 /* Most of this stuff is pretty self-evident. According to the hardware
507 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
508 * offset problem. Weird.
510 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
514 #define EC_DEFAULT_ADC_GAIN 0xC4C4
515 #define EC_DEFAULT_SPDIF0_SEL 0x0
516 #define EC_DEFAULT_SPDIF1_SEL 0x4
518 /**************************************************************************
519 * @func Clock bits into the Ecard's control latch. The Ecard uses a
520 * control latch will is loaded bit-serially by toggling the Modem control
521 * lines from function 2 on the E8010. This function hides these details
522 * and presents the illusion that we are actually writing to a distinct
526 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value)
528 unsigned short count;
530 unsigned long hc_port;
531 unsigned int hc_value;
533 hc_port = emu->port + HCFG;
534 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
535 outl(hc_value, hc_port);
537 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
539 /* Set up the value */
540 data = ((value & 0x1) ? PULSEN_BIT : 0);
543 outl(hc_value | data, hc_port);
545 /* Clock the shift register */
546 outl(hc_value | data | HANDN_BIT, hc_port);
547 outl(hc_value | data, hc_port);
551 outl(hc_value | HOOKN_BIT, hc_port);
552 outl(hc_value, hc_port);
555 /**************************************************************************
556 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
557 * trim value consists of a 16bit value which is composed of two
558 * 8 bit gain/trim values, one for the left channel and one for the
559 * right channel. The following table maps from the Gain/Attenuation
560 * value in decibels into the corresponding bit pattern for a single
564 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu,
569 /* Enable writing to the TRIM registers */
570 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
572 /* Do it again to insure that we meet hold time requirements */
573 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
575 for (bit = (1 << 15); bit; bit >>= 1) {
578 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
581 value |= EC_TRIM_SDATA;
584 snd_emu10k1_ecard_write(emu, value);
585 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
586 snd_emu10k1_ecard_write(emu, value);
589 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
592 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu)
594 unsigned int hc_value;
596 /* Set up the initial settings */
597 emu->ecard_ctrl = EC_RAW_RUN_MODE |
598 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
599 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
601 /* Step 0: Set the codec type in the hardware control register
602 * and enable audio output */
603 hc_value = inl(emu->port + HCFG);
604 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
605 inl(emu->port + HCFG);
607 /* Step 1: Turn off the led and deassert TRIM_CS */
608 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
610 /* Step 2: Calibrate the ADC and DAC */
611 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
613 /* Step 3: Wait for awhile; XXX We can't get away with this
614 * under a real operating system; we'll need to block and wait that
616 snd_emu10k1_wait(emu, 48000);
618 /* Step 4: Switch off the DAC and ADC calibration. Note
619 * That ADC_CAL is actually an inverted signal, so we assert
620 * it here to stop calibration. */
621 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
623 /* Step 4: Switch into run mode */
624 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
626 /* Step 5: Set the analog input gain */
627 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
632 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu)
634 unsigned long special_port;
637 /* Special initialisation routine
638 * before the rest of the IO-Ports become active.
640 special_port = emu->port + 0x38;
641 value = inl(special_port);
642 outl(0x00d00000, special_port);
643 value = inl(special_port);
644 outl(0x00d00001, special_port);
645 value = inl(special_port);
646 outl(0x00d0005f, special_port);
647 value = inl(special_port);
648 outl(0x00d0007f, special_port);
649 value = inl(special_port);
650 outl(0x0090007f, special_port);
651 value = inl(special_port);
653 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
654 /* Delay to give time for ADC chip to switch on. It needs 113ms */
659 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
660 const struct firmware *fw_entry)
665 unsigned int write_post;
671 /* The FPGA is a Xilinx Spartan IIE XC2S50E */
672 /* GPIO7 -> FPGA PGMN
675 * FPGA CONFIG OFF -> FPGA PGMN
677 spin_lock_irqsave(&emu->emu_lock, flags);
678 outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
679 write_post = inl(emu->port + A_IOCFG);
681 outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
682 write_post = inl(emu->port + A_IOCFG);
683 udelay(100); /* Allow FPGA memory to clean */
684 for (n = 0; n < fw_entry->size; n++) {
685 value = fw_entry->data[n];
686 for (i = 0; i < 8; i++) {
691 outl(reg, emu->port + A_IOCFG);
692 write_post = inl(emu->port + A_IOCFG);
693 outl(reg | 0x40, emu->port + A_IOCFG);
694 write_post = inl(emu->port + A_IOCFG);
697 /* After programming, set GPIO bit 4 high again. */
698 outl(0x10, emu->port + A_IOCFG);
699 write_post = inl(emu->port + A_IOCFG);
700 spin_unlock_irqrestore(&emu->emu_lock, flags);
705 /* firmware file names, per model, init-fw and dock-fw (optional) */
706 static const char * const firmware_names[5][2] = {
707 [EMU_MODEL_EMU1010] = {
708 HANA_FILENAME, DOCK_FILENAME
710 [EMU_MODEL_EMU1010B] = {
711 EMU1010B_FILENAME, MICRO_DOCK_FILENAME
713 [EMU_MODEL_EMU1616] = {
714 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME
716 [EMU_MODEL_EMU0404] = {
717 EMU0404_FILENAME, NULL
721 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock,
722 const struct firmware **fw)
724 const char *filename;
728 filename = firmware_names[emu->card_capabilities->emu_model][dock];
731 err = reject_firmware(fw, filename, &emu->pci->dev);
736 return snd_emu1010_load_firmware_entry(emu, *fw);
739 static void emu1010_firmware_work(struct work_struct *work)
741 struct snd_emu10k1 *emu;
745 emu = container_of(work, struct snd_emu10k1,
746 emu1010.firmware_work.work);
747 if (emu->card->shutdown)
749 #ifdef CONFIG_PM_SLEEP
753 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */
754 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */
755 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {
756 /* Audio Dock attached */
757 /* Return to Audio Dock programming mode */
758 dev_info(emu->card->dev,
759 "emu1010: Loading Audio Dock Firmware\n");
760 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
761 EMU_HANA_FPGA_CONFIG_AUDIODOCK);
762 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw);
766 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
767 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp);
768 dev_info(emu->card->dev,
769 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp);
770 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
771 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp);
772 dev_info(emu->card->dev,
773 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp);
774 if ((tmp & 0x1f) != 0x15) {
775 /* FPGA failed to be programmed */
776 dev_info(emu->card->dev,
777 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n",
781 dev_info(emu->card->dev,
782 "emu1010: Audio Dock Firmware loaded\n");
783 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp);
784 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2);
785 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2);
786 /* Sync clocking between 1010 and Dock */
787 /* Allow DLL to settle */
789 /* Unmute all. Default is muted after a firmware load */
790 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
791 } else if (!reg && emu->emu1010.last_reg) {
792 /* Audio Dock removed */
793 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
795 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
799 emu->emu1010.last_reg = reg;
800 if (!emu->card->shutdown)
801 schedule_delayed_work(&emu->emu1010.firmware_work,
802 msecs_to_jiffies(1000));
806 * EMU-1010 - details found out from this driver, official MS Win drivers,
809 * Audigy2 (aka Alice2):
810 * ---------------------
811 * * communication over PCI
812 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
813 * to 2 x 16-bit, using internal DSP instructions
814 * * slave mode, clock supplied by HANA
815 * * linked to HANA using:
816 * 32 x 32-bit serial EMU32 output channels
817 * 16 x EMU32 input channels
818 * (?) x I2S I/O channels (?)
822 * * provides all (?) physical inputs and outputs of the card
823 * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
824 * * provides clock signal for the card and Alice2
825 * * two crystals - for 44.1kHz and 48kHz multiples
826 * * provides internal routing of signal sources to signal destinations
827 * * inputs/outputs to Alice2 - see above
829 * Current status of the driver:
830 * ----------------------------
831 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
832 * * PCM device nb. 2:
833 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
834 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops
836 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
842 dev_info(emu->card->dev, "emu1010: Special config.\n");
843 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
844 * Lock Sound Memory Cache, Lock Tank Memory Cache,
847 outl(0x0005a00c, emu->port + HCFG);
848 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
849 * Lock Tank Memory Cache,
852 outl(0x0005a004, emu->port + HCFG);
853 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
856 outl(0x0005a000, emu->port + HCFG);
857 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
860 outl(0x0005a000, emu->port + HCFG);
862 /* Disable 48Volt power to Audio Dock */
863 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
865 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
866 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
867 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg);
868 if ((reg & 0x3f) == 0x15) {
869 /* FPGA netlist already present so clear it */
870 /* Return to programming mode */
872 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
874 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
875 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
876 if ((reg & 0x3f) == 0x15) {
877 /* FPGA failed to return to programming mode */
878 dev_info(emu->card->dev,
879 "emu1010: FPGA failed to return to programming mode\n");
882 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg);
884 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware);
886 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n");
890 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
891 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
892 if ((reg & 0x3f) != 0x15) {
893 /* FPGA failed to be programmed */
894 dev_info(emu->card->dev,
895 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n",
900 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n");
901 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp);
902 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2);
903 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2);
904 /* Enable 48Volt power to Audio Dock */
905 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON);
907 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
908 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
909 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
910 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
911 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);
912 /* Optical -> ADAT I/O */
916 emu->emu1010.optical_in = 1; /* IN_ADAT */
917 emu->emu1010.optical_out = 1; /* IN_ADAT */
919 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
920 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
921 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
922 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);
923 /* Set no attenuation on Audio Dock pads. */
924 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
925 emu->emu1010.adc_pads = 0x00;
926 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
927 /* Unmute Audio dock DACs, Headphone source DAC-4. */
928 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
929 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
930 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp);
932 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
933 emu->emu1010.dac_pads = 0x0f;
934 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
935 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
936 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
937 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
938 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
940 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
942 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
943 /* IRQ Enable: All on */
944 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
945 /* IRQ Enable: All off */
946 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
948 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
949 dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg);
950 /* Default WCLK set to 48kHz. */
951 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
952 /* Word Clock source, Internal 48kHz x1 */
953 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
954 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
955 /* Audio Dock LEDs. */
956 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
960 snd_emu1010_fpga_link_dst_src_write(emu,
961 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
962 snd_emu1010_fpga_link_dst_src_write(emu,
963 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
964 snd_emu1010_fpga_link_dst_src_write(emu,
965 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
966 snd_emu1010_fpga_link_dst_src_write(emu,
967 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
971 snd_emu1010_fpga_link_dst_src_write(emu,
972 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
973 snd_emu1010_fpga_link_dst_src_write(emu,
974 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
975 snd_emu1010_fpga_link_dst_src_write(emu,
976 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
977 snd_emu1010_fpga_link_dst_src_write(emu,
978 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
979 snd_emu1010_fpga_link_dst_src_write(emu,
980 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
981 snd_emu1010_fpga_link_dst_src_write(emu,
982 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
983 snd_emu1010_fpga_link_dst_src_write(emu,
984 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
985 snd_emu1010_fpga_link_dst_src_write(emu,
986 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
990 snd_emu1010_fpga_link_dst_src_write(emu,
991 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
992 snd_emu1010_fpga_link_dst_src_write(emu,
993 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
994 snd_emu1010_fpga_link_dst_src_write(emu,
995 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
996 snd_emu1010_fpga_link_dst_src_write(emu,
997 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
998 snd_emu1010_fpga_link_dst_src_write(emu,
999 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
1000 snd_emu1010_fpga_link_dst_src_write(emu,
1001 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
1002 snd_emu1010_fpga_link_dst_src_write(emu,
1003 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
1004 snd_emu1010_fpga_link_dst_src_write(emu,
1005 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
1006 /* Pavel Hofman - setting defaults for 8 more capture channels
1007 * Defaults only, users will set their own values anyways, let's
1011 snd_emu1010_fpga_link_dst_src_write(emu,
1012 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
1013 snd_emu1010_fpga_link_dst_src_write(emu,
1014 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
1015 snd_emu1010_fpga_link_dst_src_write(emu,
1016 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
1017 snd_emu1010_fpga_link_dst_src_write(emu,
1018 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
1019 snd_emu1010_fpga_link_dst_src_write(emu,
1020 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
1021 snd_emu1010_fpga_link_dst_src_write(emu,
1022 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
1023 snd_emu1010_fpga_link_dst_src_write(emu,
1024 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
1025 snd_emu1010_fpga_link_dst_src_write(emu,
1026 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
1030 snd_emu1010_fpga_link_dst_src_write(emu,
1031 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
1032 snd_emu1010_fpga_link_dst_src_write(emu,
1033 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
1034 snd_emu1010_fpga_link_dst_src_write(emu,
1035 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
1036 snd_emu1010_fpga_link_dst_src_write(emu,
1037 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
1038 snd_emu1010_fpga_link_dst_src_write(emu,
1039 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
1040 snd_emu1010_fpga_link_dst_src_write(emu,
1041 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
1042 snd_emu1010_fpga_link_dst_src_write(emu,
1043 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
1044 snd_emu1010_fpga_link_dst_src_write(emu,
1045 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
1046 snd_emu1010_fpga_link_dst_src_write(emu,
1047 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
1048 snd_emu1010_fpga_link_dst_src_write(emu,
1049 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
1050 snd_emu1010_fpga_link_dst_src_write(emu,
1051 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
1052 snd_emu1010_fpga_link_dst_src_write(emu,
1053 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
1055 for (i = 0; i < 0x20; i++) {
1056 /* AudioDock Elink <- Silence */
1057 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE);
1059 for (i = 0; i < 4; i++) {
1060 /* Hana SPDIF Out <- Silence */
1061 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE);
1063 for (i = 0; i < 7; i++) {
1064 /* Hamoa DAC <- Silence */
1065 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE);
1067 for (i = 0; i < 7; i++) {
1068 /* Hana ADAT Out <- Silence */
1069 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
1071 snd_emu1010_fpga_link_dst_src_write(emu,
1072 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
1073 snd_emu1010_fpga_link_dst_src_write(emu,
1074 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
1075 snd_emu1010_fpga_link_dst_src_write(emu,
1076 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
1077 snd_emu1010_fpga_link_dst_src_write(emu,
1078 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
1079 snd_emu1010_fpga_link_dst_src_write(emu,
1080 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
1081 snd_emu1010_fpga_link_dst_src_write(emu,
1082 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
1083 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
1085 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1087 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1088 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1091 outl(0x0000a000, emu->port + HCFG);
1092 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1093 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1094 * Un-Mute all codecs.
1096 outl(0x0000a001, emu->port + HCFG);
1098 /* Initial boot complete. Now patches */
1100 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1101 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1102 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1103 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1104 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1105 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
1106 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
1109 snd_emu1010_fpga_link_dst_src_write(emu,
1110 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
1111 snd_emu1010_fpga_link_dst_src_write(emu,
1112 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
1113 snd_emu1010_fpga_link_dst_src_write(emu,
1114 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
1115 snd_emu1010_fpga_link_dst_src_write(emu,
1116 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
1118 /* Default outputs */
1119 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
1120 /* 1616(M) cardbus default outputs */
1121 /* ALICE2 bus 0xa0 */
1122 snd_emu1010_fpga_link_dst_src_write(emu,
1123 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1124 emu->emu1010.output_source[0] = 17;
1125 snd_emu1010_fpga_link_dst_src_write(emu,
1126 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1127 emu->emu1010.output_source[1] = 18;
1128 snd_emu1010_fpga_link_dst_src_write(emu,
1129 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1130 emu->emu1010.output_source[2] = 19;
1131 snd_emu1010_fpga_link_dst_src_write(emu,
1132 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1133 emu->emu1010.output_source[3] = 20;
1134 snd_emu1010_fpga_link_dst_src_write(emu,
1135 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1136 emu->emu1010.output_source[4] = 21;
1137 snd_emu1010_fpga_link_dst_src_write(emu,
1138 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1139 emu->emu1010.output_source[5] = 22;
1140 /* ALICE2 bus 0xa0 */
1141 snd_emu1010_fpga_link_dst_src_write(emu,
1142 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0);
1143 emu->emu1010.output_source[16] = 17;
1144 snd_emu1010_fpga_link_dst_src_write(emu,
1145 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1);
1146 emu->emu1010.output_source[17] = 18;
1148 /* ALICE2 bus 0xa0 */
1149 snd_emu1010_fpga_link_dst_src_write(emu,
1150 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1151 emu->emu1010.output_source[0] = 21;
1152 snd_emu1010_fpga_link_dst_src_write(emu,
1153 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1154 emu->emu1010.output_source[1] = 22;
1155 snd_emu1010_fpga_link_dst_src_write(emu,
1156 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1157 emu->emu1010.output_source[2] = 23;
1158 snd_emu1010_fpga_link_dst_src_write(emu,
1159 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1160 emu->emu1010.output_source[3] = 24;
1161 snd_emu1010_fpga_link_dst_src_write(emu,
1162 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1163 emu->emu1010.output_source[4] = 25;
1164 snd_emu1010_fpga_link_dst_src_write(emu,
1165 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1166 emu->emu1010.output_source[5] = 26;
1167 snd_emu1010_fpga_link_dst_src_write(emu,
1168 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
1169 emu->emu1010.output_source[6] = 27;
1170 snd_emu1010_fpga_link_dst_src_write(emu,
1171 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
1172 emu->emu1010.output_source[7] = 28;
1173 /* ALICE2 bus 0xa0 */
1174 snd_emu1010_fpga_link_dst_src_write(emu,
1175 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1176 emu->emu1010.output_source[8] = 21;
1177 snd_emu1010_fpga_link_dst_src_write(emu,
1178 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1179 emu->emu1010.output_source[9] = 22;
1180 /* ALICE2 bus 0xa0 */
1181 snd_emu1010_fpga_link_dst_src_write(emu,
1182 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1183 emu->emu1010.output_source[10] = 21;
1184 snd_emu1010_fpga_link_dst_src_write(emu,
1185 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1186 emu->emu1010.output_source[11] = 22;
1187 /* ALICE2 bus 0xa0 */
1188 snd_emu1010_fpga_link_dst_src_write(emu,
1189 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1190 emu->emu1010.output_source[12] = 21;
1191 snd_emu1010_fpga_link_dst_src_write(emu,
1192 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1193 emu->emu1010.output_source[13] = 22;
1194 /* ALICE2 bus 0xa0 */
1195 snd_emu1010_fpga_link_dst_src_write(emu,
1196 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1197 emu->emu1010.output_source[14] = 21;
1198 snd_emu1010_fpga_link_dst_src_write(emu,
1199 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1200 emu->emu1010.output_source[15] = 22;
1201 /* ALICE2 bus 0xa0 */
1202 snd_emu1010_fpga_link_dst_src_write(emu,
1203 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0);
1204 emu->emu1010.output_source[16] = 21;
1205 snd_emu1010_fpga_link_dst_src_write(emu,
1206 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
1207 emu->emu1010.output_source[17] = 22;
1208 snd_emu1010_fpga_link_dst_src_write(emu,
1209 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
1210 emu->emu1010.output_source[18] = 23;
1211 snd_emu1010_fpga_link_dst_src_write(emu,
1212 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
1213 emu->emu1010.output_source[19] = 24;
1214 snd_emu1010_fpga_link_dst_src_write(emu,
1215 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
1216 emu->emu1010.output_source[20] = 25;
1217 snd_emu1010_fpga_link_dst_src_write(emu,
1218 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1219 emu->emu1010.output_source[21] = 26;
1220 snd_emu1010_fpga_link_dst_src_write(emu,
1221 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1222 emu->emu1010.output_source[22] = 27;
1223 snd_emu1010_fpga_link_dst_src_write(emu,
1224 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1225 emu->emu1010.output_source[23] = 28;
1227 /* TEMP: Select SPDIF in/out */
1228 /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */
1230 /* TEMP: Select 48kHz SPDIF out */
1231 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1232 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1233 /* Word Clock source, Internal 48kHz x1 */
1234 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
1235 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
1236 emu->emu1010.internal_clock = 1; /* 48000 */
1237 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */
1238 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1239 /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */
1240 /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */
1241 /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */
1246 * Create the EMU10K1 instance
1249 #ifdef CONFIG_PM_SLEEP
1250 static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1251 static void free_pm_buffer(struct snd_emu10k1 *emu);
1254 static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1256 if (emu->port) { /* avoid access to already used hardware */
1257 snd_emu10k1_fx8010_tram_setup(emu, 0);
1258 snd_emu10k1_done(emu);
1259 snd_emu10k1_free_efx(emu);
1261 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) {
1262 /* Disable 48Volt power to Audio Dock */
1263 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
1265 cancel_delayed_work_sync(&emu->emu1010.firmware_work);
1266 release_firmware(emu->firmware);
1267 release_firmware(emu->dock_fw);
1269 free_irq(emu->irq, emu);
1270 /* remove reserved page */
1271 if (emu->reserved_page) {
1272 snd_emu10k1_synth_free(emu,
1273 (struct snd_util_memblk *)emu->reserved_page);
1274 emu->reserved_page = NULL;
1276 snd_util_memhdr_free(emu->memhdr);
1277 if (emu->silent_page.area)
1278 snd_dma_free_pages(&emu->silent_page);
1279 if (emu->ptb_pages.area)
1280 snd_dma_free_pages(&emu->ptb_pages);
1281 vfree(emu->page_ptr_table);
1282 vfree(emu->page_addr_table);
1283 #ifdef CONFIG_PM_SLEEP
1284 free_pm_buffer(emu);
1287 pci_release_regions(emu->pci);
1288 if (emu->card_capabilities->ca0151_chip) /* P16V */
1290 pci_disable_device(emu->pci);
1295 static int snd_emu10k1_dev_free(struct snd_device *device)
1297 struct snd_emu10k1 *emu = device->device_data;
1298 return snd_emu10k1_free(emu);
1301 static struct snd_emu_chip_details emu_chip_details[] = {
1302 /* Audigy 5/Rx SB1550 */
1303 /* Tested by michael@gernoth.net 28 Mar 2015 */
1304 /* DSP: CA10300-IAT LF
1305 * DAC: Cirrus Logic CS4382-KQZ
1306 * ADC: Philips 1361T
1307 * AC97: Sigmatel STAC9750
1310 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102,
1311 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]",
1316 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1318 /* Audigy4 (Not PRO) SB0610 */
1319 /* Tested by James@superbug.co.uk 4th April 2006 */
1325 * 3: 0 - Digital Out, 1 - Line in
1333 * A: Green jack sense (Front)
1335 * C: Black jack sense (Rear/Side Right)
1336 * D: Yellow jack sense (Center/LFE/Side Left)
1340 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1344 /* Mic input not tested.
1345 * Analog CD input not tested
1346 * Digital Out not tested.
1348 * Audio output 5.1 working. Side outputs not working.
1350 /* DSP: CA10300-IAT LF
1351 * DAC: Cirrus Logic CS4382-KQZ
1352 * ADC: Philips 1361T
1353 * AC97: Sigmatel STAC9750
1356 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1357 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]",
1362 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1364 /* Audigy 2 Value AC3 out does not work yet.
1365 * Need to find out how to turn off interpolators.
1367 /* Tested by James@superbug.co.uk 3rd July 2005 */
1370 * ADC: Philips 1361T
1374 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1375 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
1381 /* Audigy 2 ZS Notebook Cardbus card.*/
1382 /* Tested by James@superbug.co.uk 6th November 2006 */
1383 /* Audio output 7.1/Headphones working.
1384 * Digital output working. (AC3 not checked, only PCM)
1385 * Audio Mic/Line inputs working.
1386 * Digital input not tested.
1389 * DAC: Wolfson WM8768/WM8568
1390 * ADC: Wolfson WM8775
1394 /* Tested by James@superbug.co.uk 4th April 2006 */
1398 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
1399 * 2: Analog input 0 = line in, 1 = mic in
1401 * 4: Digital output 0 = off, 1 = on.
1406 * All bits 1 (0x3fxx) means nothing plugged in.
1407 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
1408 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
1409 * C-D: 2 = Front/Rear/etc, 3 = nothing.
1413 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1414 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1418 .ca_cardbus_chip = 1,
1422 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1423 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
1424 .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
1428 .ca_cardbus_chip = 1,
1430 .emu_model = EMU_MODEL_EMU1616},
1431 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1432 /* This is MAEM8960, 0202 is MAEM 8980 */
1433 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
1434 .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
1439 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
1440 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
1441 /* This is MAEM8986, 0202 is MAEM8980 */
1442 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
1443 .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
1448 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
1449 /* Tested by James@superbug.co.uk 8th July 2005. */
1450 /* This is MAEM8810, 0202 is MAEM8820 */
1451 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
1452 .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
1457 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
1459 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
1460 .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
1465 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
1466 /* Tested by James@superbug.co.uk 20-3-2007. */
1467 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
1468 .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
1473 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
1475 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
1476 .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
1481 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
1482 /* Note that all E-mu cards require kernel 2.6 or newer. */
1483 {.vendor = 0x1102, .device = 0x0008,
1484 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
1489 /* Tested by James@superbug.co.uk 3rd July 2005 */
1490 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1491 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]",
1499 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
1500 /* The 0x20061102 does have SB0350 written on it
1501 * Just like 0x20021102
1503 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
1504 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]",
1511 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1513 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by
1514 Creative's Windows driver */
1515 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102,
1516 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]",
1523 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1525 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1526 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]",
1533 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1535 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1536 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]",
1543 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1546 /* Tested by James@superbug.co.uk 3rd July 2005 */
1549 * ADC: Philips 1361T
1553 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1554 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]",
1561 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1563 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1564 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
1571 /* Dell OEM/Creative Labs Audigy 2 ZS */
1572 /* See ALSA bug#1365 */
1573 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1574 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]",
1581 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1583 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1584 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
1591 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1592 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1594 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1595 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]",
1602 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1603 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]",
1608 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1609 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]",
1615 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1616 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]",
1621 {.vendor = 0x1102, .device = 0x0004,
1622 .driver = "Audigy", .name = "Audigy 1 [Unknown]",
1627 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1628 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1633 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102,
1634 .driver = "EMU10K1", .name = "SB Live! [SB0105]",
1639 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102,
1640 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]",
1645 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1646 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]",
1651 /* Tested by ALSA bug#1680 26th December 2005 */
1652 /* note: It really has SB0220 written on the card, */
1653 /* but it's SB0228 according to kx.inf */
1654 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1655 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]",
1660 /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1661 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1662 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1667 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1668 .driver = "EMU10K1", .name = "SB Live! 5.1",
1673 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
1674 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
1675 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]",
1678 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1679 * share the same IDs!
1682 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1683 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]",
1688 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1689 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
1693 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1694 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]",
1699 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1700 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]",
1705 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1706 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]",
1711 /* Tested by James@superbug.co.uk 3rd July 2005 */
1712 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1713 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]",
1718 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1719 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]",
1724 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1725 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
1730 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1731 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]",
1736 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1737 .driver = "EMU10K1", .name = "E-mu APS [PC545]",
1741 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1742 .driver = "EMU10K1", .name = "SB Live! [CT4620]",
1747 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1748 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]",
1753 {.vendor = 0x1102, .device = 0x0002,
1754 .driver = "EMU10K1", .name = "SB Live! [Unknown]",
1759 { } /* terminator */
1762 int snd_emu10k1_create(struct snd_card *card,
1763 struct pci_dev *pci,
1764 unsigned short extin_mask,
1765 unsigned short extout_mask,
1766 long max_cache_bytes,
1769 struct snd_emu10k1 **remu)
1771 struct snd_emu10k1 *emu;
1774 unsigned int silent_page;
1775 const struct snd_emu_chip_details *c;
1776 static struct snd_device_ops ops = {
1777 .dev_free = snd_emu10k1_dev_free,
1782 /* enable PCI device */
1783 err = pci_enable_device(pci);
1787 emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1789 pci_disable_device(pci);
1793 spin_lock_init(&emu->reg_lock);
1794 spin_lock_init(&emu->emu_lock);
1795 spin_lock_init(&emu->spi_lock);
1796 spin_lock_init(&emu->i2c_lock);
1797 spin_lock_init(&emu->voice_lock);
1798 spin_lock_init(&emu->synth_lock);
1799 spin_lock_init(&emu->memblk_lock);
1800 mutex_init(&emu->fx8010.lock);
1801 INIT_LIST_HEAD(&emu->mapped_link_head);
1802 INIT_LIST_HEAD(&emu->mapped_order_link_head);
1806 emu->get_synth_voice = NULL;
1807 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);
1808 /* read revision & serial */
1809 emu->revision = pci->revision;
1810 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1811 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1813 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n",
1814 pci->vendor, pci->device, emu->serial, emu->model);
1816 for (c = emu_chip_details; c->vendor; c++) {
1817 if (c->vendor == pci->vendor && c->device == pci->device) {
1819 if (c->subsystem && (c->subsystem == subsystem))
1824 if (c->subsystem && (c->subsystem != emu->serial))
1826 if (c->revision && c->revision != emu->revision)
1832 if (c->vendor == 0) {
1833 dev_err(card->dev, "emu10k1: Card not recognised\n");
1835 pci_disable_device(pci);
1838 emu->card_capabilities = c;
1839 if (c->subsystem && !subsystem)
1840 dev_dbg(card->dev, "Sound card name = %s\n", c->name);
1842 dev_dbg(card->dev, "Sound card name = %s, "
1843 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. "
1844 "Forced to subsystem = 0x%x\n", c->name,
1845 pci->vendor, pci->device, emu->serial, c->subsystem);
1847 dev_dbg(card->dev, "Sound card name = %s, "
1848 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n",
1849 c->name, pci->vendor, pci->device,
1852 if (!*card->id && c->id) {
1854 strlcpy(card->id, c->id, sizeof(card->id));
1856 for (i = 0; i < snd_ecards_limit; i++) {
1857 if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
1860 if (i >= snd_ecards_limit)
1863 if (n >= SNDRV_CARDS)
1865 snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
1869 is_audigy = emu->audigy = c->emu10k2_chip;
1871 /* set addressing mode */
1872 emu->address_mode = is_audigy ? 0 : 1;
1873 /* set the DMA transfer mask */
1874 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK;
1875 if (dma_set_mask(&pci->dev, emu->dma_mask) < 0 ||
1876 dma_set_coherent_mask(&pci->dev, emu->dma_mask) < 0) {
1878 "architecture does not support PCI busmaster DMA with mask 0x%lx\n",
1881 pci_disable_device(pci);
1885 emu->gpr_base = A_FXGPREGBASE;
1887 emu->gpr_base = FXGPREGBASE;
1889 err = pci_request_regions(pci, "EMU10K1");
1892 pci_disable_device(pci);
1895 emu->port = pci_resource_start(pci, 0);
1897 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1898 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1899 (emu->address_mode ? 32 : 16) * 1024, &emu->ptb_pages) < 0) {
1904 emu->page_ptr_table = vmalloc(emu->max_cache_pages * sizeof(void *));
1905 emu->page_addr_table = vmalloc(emu->max_cache_pages *
1906 sizeof(unsigned long));
1907 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
1912 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1913 EMUPAGESIZE, &emu->silent_page) < 0) {
1917 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1918 if (emu->memhdr == NULL) {
1922 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1923 sizeof(struct snd_util_memblk);
1925 pci_set_master(pci);
1927 emu->fx8010.fxbus_mask = 0x303f;
1928 if (extin_mask == 0)
1929 extin_mask = 0x3fcf;
1930 if (extout_mask == 0)
1931 extout_mask = 0x7fff;
1932 emu->fx8010.extin_mask = extin_mask;
1933 emu->fx8010.extout_mask = extout_mask;
1934 emu->enable_ir = enable_ir;
1936 if (emu->card_capabilities->ca_cardbus_chip) {
1937 err = snd_emu10k1_cardbus_init(emu);
1941 if (emu->card_capabilities->ecard) {
1942 err = snd_emu10k1_ecard_init(emu);
1945 } else if (emu->card_capabilities->emu_model) {
1946 err = snd_emu10k1_emu1010_init(emu);
1948 snd_emu10k1_free(emu);
1952 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1953 does not support this, it shouldn't do any harm */
1954 snd_emu10k1_ptr_write(emu, AC97SLOT, 0,
1955 AC97SLOT_CNTR|AC97SLOT_LFE);
1958 /* initialize TRAM setup */
1959 emu->fx8010.itram_size = (16 * 1024)/2;
1960 emu->fx8010.etram_pages.area = NULL;
1961 emu->fx8010.etram_pages.bytes = 0;
1963 /* irq handler must be registered after I/O ports are activated */
1964 if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
1965 KBUILD_MODNAME, emu)) {
1969 emu->irq = pci->irq;
1972 * Init to 0x02109204 :
1973 * Clock accuracy = 0 (1000ppm)
1974 * Sample Rate = 2 (48kHz)
1975 * Audio Channel = 1 (Left of 2)
1976 * Source Number = 0 (Unspecified)
1977 * Generation Status = 1 (Original for Cat Code 12)
1978 * Cat Code = 12 (Digital Signal Mixer)
1980 * Emphasis = 0 (None)
1981 * CP = 1 (Copyright unasserted)
1982 * AN = 0 (Audio data)
1985 emu->spdif_bits[0] = emu->spdif_bits[1] =
1986 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1987 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1988 SPCS_GENERATIONSTATUS | 0x00001200 |
1989 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1991 emu->reserved_page = (struct snd_emu10k1_memblk *)
1992 snd_emu10k1_synth_alloc(emu, 4096);
1993 if (emu->reserved_page)
1994 emu->reserved_page->map_locked = 1;
1996 /* Clear silent pages and set up pointers */
1997 memset(emu->silent_page.area, 0, PAGE_SIZE);
1998 silent_page = emu->silent_page.addr << emu->address_mode;
1999 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++)
2000 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
2002 /* set up voice indices */
2003 for (idx = 0; idx < NUM_G; idx++) {
2004 emu->voices[idx].emu = emu;
2005 emu->voices[idx].number = idx;
2008 err = snd_emu10k1_init(emu, enable_ir, 0);
2011 #ifdef CONFIG_PM_SLEEP
2012 err = alloc_pm_buffer(emu);
2017 /* Initialize the effect engine */
2018 err = snd_emu10k1_init_efx(emu);
2021 snd_emu10k1_audio_enable(emu);
2023 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops);
2027 #ifdef CONFIG_SND_PROC_FS
2028 snd_emu10k1_proc_init(emu);
2035 snd_emu10k1_free(emu);
2039 #ifdef CONFIG_PM_SLEEP
2040 static unsigned char saved_regs[] = {
2041 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
2042 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
2043 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
2044 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
2045 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
2046 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
2049 static unsigned char saved_regs_audigy[] = {
2050 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
2051 A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
2055 static int alloc_pm_buffer(struct snd_emu10k1 *emu)
2059 size = ARRAY_SIZE(saved_regs);
2061 size += ARRAY_SIZE(saved_regs_audigy);
2062 emu->saved_ptr = vmalloc(4 * NUM_G * size);
2063 if (!emu->saved_ptr)
2065 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
2067 if (emu->card_capabilities->ca0151_chip &&
2068 snd_p16v_alloc_pm_buffer(emu) < 0)
2073 static void free_pm_buffer(struct snd_emu10k1 *emu)
2075 vfree(emu->saved_ptr);
2076 snd_emu10k1_efx_free_pm_buffer(emu);
2077 if (emu->card_capabilities->ca0151_chip)
2078 snd_p16v_free_pm_buffer(emu);
2081 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
2087 val = emu->saved_ptr;
2088 for (reg = saved_regs; *reg != 0xff; reg++)
2089 for (i = 0; i < NUM_G; i++, val++)
2090 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2092 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2093 for (i = 0; i < NUM_G; i++, val++)
2094 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2097 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
2098 emu->saved_hcfg = inl(emu->port + HCFG);
2101 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
2103 if (emu->card_capabilities->ca_cardbus_chip)
2104 snd_emu10k1_cardbus_init(emu);
2105 if (emu->card_capabilities->ecard)
2106 snd_emu10k1_ecard_init(emu);
2107 else if (emu->card_capabilities->emu_model)
2108 snd_emu10k1_emu1010_init(emu);
2110 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
2111 snd_emu10k1_init(emu, emu->enable_ir, 1);
2114 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
2120 snd_emu10k1_audio_enable(emu);
2122 /* resore for spdif */
2124 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
2125 outl(emu->saved_hcfg, emu->port + HCFG);
2127 val = emu->saved_ptr;
2128 for (reg = saved_regs; *reg != 0xff; reg++)
2129 for (i = 0; i < NUM_G; i++, val++)
2130 snd_emu10k1_ptr_write(emu, *reg, i, *val);
2132 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2133 for (i = 0; i < NUM_G; i++, val++)
2134 snd_emu10k1_ptr_write(emu, *reg, i, *val);