1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
8 * This file contains the implementation of hardware access methord for 20k1.
14 #include <linux/types.h>
15 #include <linux/slab.h>
16 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/spinlock.h>
20 #include <linux/kernel.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
24 #include "ct20k1reg.h"
28 spinlock_t reg_20k1_lock;
29 spinlock_t reg_pci_lock;
32 static u32 hw_read_20kx(struct hw *hw, u32 reg);
33 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
34 static u32 hw_read_pci(struct hw *hw, u32 reg);
35 static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
38 * Type definition block.
39 * The layout of control structures can be directly applied on 20k2 chip.
43 * SRC control block definitions.
46 /* SRC resource control block */
47 #define SRCCTL_STATE 0x00000007
48 #define SRCCTL_BM 0x00000008
49 #define SRCCTL_RSR 0x00000030
50 #define SRCCTL_SF 0x000001C0
51 #define SRCCTL_WR 0x00000200
52 #define SRCCTL_PM 0x00000400
53 #define SRCCTL_ROM 0x00001800
54 #define SRCCTL_VO 0x00002000
55 #define SRCCTL_ST 0x00004000
56 #define SRCCTL_IE 0x00008000
57 #define SRCCTL_ILSZ 0x000F0000
58 #define SRCCTL_BP 0x00100000
60 #define SRCCCR_CISZ 0x000007FF
61 #define SRCCCR_CWA 0x001FF800
62 #define SRCCCR_D 0x00200000
63 #define SRCCCR_RS 0x01C00000
64 #define SRCCCR_NAL 0x3E000000
65 #define SRCCCR_RA 0xC0000000
67 #define SRCCA_CA 0x03FFFFFF
68 #define SRCCA_RS 0x1C000000
69 #define SRCCA_NAL 0xE0000000
71 #define SRCSA_SA 0x03FFFFFF
73 #define SRCLA_LA 0x03FFFFFF
75 /* Mixer Parameter Ring ram Low and Hight register.
76 * Fixed-point value in 8.24 format for parameter channel */
77 #define MPRLH_PITCH 0xFFFFFFFF
79 /* SRC resource register dirty flags */
88 u16 czbfs:1; /* Clear Z-Buffers */
94 struct src_rsc_ctrl_blk {
101 union src_dirty dirty;
104 /* SRC manager control block */
105 union src_mgr_dirty {
121 struct src_mgr_ctrl_blk {
124 union src_mgr_dirty dirty;
127 /* SRCIMP manager control block */
128 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000
137 /* SRCIMP manager register dirty flags */
138 union srcimp_mgr_dirty {
146 struct srcimp_mgr_ctrl_blk {
147 struct srcimap srcimap;
148 union srcimp_mgr_dirty dirty;
152 * Function implementation block.
155 static int src_get_rsc_ctrl_blk(void **rblk)
157 struct src_rsc_ctrl_blk *blk;
160 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
169 static int src_put_rsc_ctrl_blk(void *blk)
176 static int src_set_state(void *blk, unsigned int state)
178 struct src_rsc_ctrl_blk *ctl = blk;
180 set_field(&ctl->ctl, SRCCTL_STATE, state);
181 ctl->dirty.bf.ctl = 1;
185 static int src_set_bm(void *blk, unsigned int bm)
187 struct src_rsc_ctrl_blk *ctl = blk;
189 set_field(&ctl->ctl, SRCCTL_BM, bm);
190 ctl->dirty.bf.ctl = 1;
194 static int src_set_rsr(void *blk, unsigned int rsr)
196 struct src_rsc_ctrl_blk *ctl = blk;
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
199 ctl->dirty.bf.ctl = 1;
203 static int src_set_sf(void *blk, unsigned int sf)
205 struct src_rsc_ctrl_blk *ctl = blk;
207 set_field(&ctl->ctl, SRCCTL_SF, sf);
208 ctl->dirty.bf.ctl = 1;
212 static int src_set_wr(void *blk, unsigned int wr)
214 struct src_rsc_ctrl_blk *ctl = blk;
216 set_field(&ctl->ctl, SRCCTL_WR, wr);
217 ctl->dirty.bf.ctl = 1;
221 static int src_set_pm(void *blk, unsigned int pm)
223 struct src_rsc_ctrl_blk *ctl = blk;
225 set_field(&ctl->ctl, SRCCTL_PM, pm);
226 ctl->dirty.bf.ctl = 1;
230 static int src_set_rom(void *blk, unsigned int rom)
232 struct src_rsc_ctrl_blk *ctl = blk;
234 set_field(&ctl->ctl, SRCCTL_ROM, rom);
235 ctl->dirty.bf.ctl = 1;
239 static int src_set_vo(void *blk, unsigned int vo)
241 struct src_rsc_ctrl_blk *ctl = blk;
243 set_field(&ctl->ctl, SRCCTL_VO, vo);
244 ctl->dirty.bf.ctl = 1;
248 static int src_set_st(void *blk, unsigned int st)
250 struct src_rsc_ctrl_blk *ctl = blk;
252 set_field(&ctl->ctl, SRCCTL_ST, st);
253 ctl->dirty.bf.ctl = 1;
257 static int src_set_ie(void *blk, unsigned int ie)
259 struct src_rsc_ctrl_blk *ctl = blk;
261 set_field(&ctl->ctl, SRCCTL_IE, ie);
262 ctl->dirty.bf.ctl = 1;
266 static int src_set_ilsz(void *blk, unsigned int ilsz)
268 struct src_rsc_ctrl_blk *ctl = blk;
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
271 ctl->dirty.bf.ctl = 1;
275 static int src_set_bp(void *blk, unsigned int bp)
277 struct src_rsc_ctrl_blk *ctl = blk;
279 set_field(&ctl->ctl, SRCCTL_BP, bp);
280 ctl->dirty.bf.ctl = 1;
284 static int src_set_cisz(void *blk, unsigned int cisz)
286 struct src_rsc_ctrl_blk *ctl = blk;
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
289 ctl->dirty.bf.ccr = 1;
293 static int src_set_ca(void *blk, unsigned int ca)
295 struct src_rsc_ctrl_blk *ctl = blk;
297 set_field(&ctl->ca, SRCCA_CA, ca);
298 ctl->dirty.bf.ca = 1;
302 static int src_set_sa(void *blk, unsigned int sa)
304 struct src_rsc_ctrl_blk *ctl = blk;
306 set_field(&ctl->sa, SRCSA_SA, sa);
307 ctl->dirty.bf.sa = 1;
311 static int src_set_la(void *blk, unsigned int la)
313 struct src_rsc_ctrl_blk *ctl = blk;
315 set_field(&ctl->la, SRCLA_LA, la);
316 ctl->dirty.bf.la = 1;
320 static int src_set_pitch(void *blk, unsigned int pitch)
322 struct src_rsc_ctrl_blk *ctl = blk;
324 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
325 ctl->dirty.bf.mpr = 1;
329 static int src_set_clear_zbufs(void *blk, unsigned int clear)
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
335 static int src_set_dirty(void *blk, unsigned int flags)
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
341 static int src_set_dirty_all(void *blk)
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
347 #define AR_SLOT_SIZE 4096
348 #define AR_SLOT_BLOCK_SIZE 16
349 #define AR_PTS_PITCH 6
350 #define AR_PARAM_SRC_OFFSET 0x60
352 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
354 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
359 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
361 struct src_rsc_ctrl_blk *ctl = blk;
364 if (ctl->dirty.bf.czbfs) {
365 /* Clear Z-Buffer registers */
366 for (i = 0; i < 8; i++)
367 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
369 for (i = 0; i < 4; i++)
370 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
372 for (i = 0; i < 8; i++)
373 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
375 ctl->dirty.bf.czbfs = 0;
377 if (ctl->dirty.bf.mpr) {
378 /* Take the parameter mixer resource in the same group as that
379 * the idx src is in for simplicity. Unlike src, all conjugate
380 * parameter mixer resources must be programmed for
381 * corresponding conjugate src resources. */
382 unsigned int pm_idx = src_param_pitch_mixer(idx);
383 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
384 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
385 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
386 ctl->dirty.bf.mpr = 0;
388 if (ctl->dirty.bf.sa) {
389 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
390 ctl->dirty.bf.sa = 0;
392 if (ctl->dirty.bf.la) {
393 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
394 ctl->dirty.bf.la = 0;
396 if (ctl->dirty.bf.ca) {
397 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
398 ctl->dirty.bf.ca = 0;
401 /* Write srccf register */
402 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
404 if (ctl->dirty.bf.ccr) {
405 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
406 ctl->dirty.bf.ccr = 0;
408 if (ctl->dirty.bf.ctl) {
409 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
410 ctl->dirty.bf.ctl = 0;
416 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
418 struct src_rsc_ctrl_blk *ctl = blk;
420 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
421 ctl->dirty.bf.ca = 0;
423 return get_field(ctl->ca, SRCCA_CA);
426 static unsigned int src_get_dirty(void *blk)
428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
431 static unsigned int src_dirty_conj_mask(void)
436 static int src_mgr_enbs_src(void *blk, unsigned int idx)
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
444 static int src_mgr_enb_src(void *blk, unsigned int idx)
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
451 static int src_mgr_dsb_src(void *blk, unsigned int idx)
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 static int src_mgr_commit_write(struct hw *hw, void *blk)
460 struct src_mgr_ctrl_blk *ctl = blk;
464 if (ctl->dirty.bf.enbsa) {
466 ret = hw_read_20kx(hw, SRCENBSTAT);
468 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
469 ctl->dirty.bf.enbsa = 0;
471 for (i = 0; i < 8; i++) {
472 if ((ctl->dirty.data & (0x1 << i))) {
473 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
474 ctl->dirty.data &= ~(0x1 << i);
481 static int src_mgr_get_ctrl_blk(void **rblk)
483 struct src_mgr_ctrl_blk *blk;
486 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
495 static int src_mgr_put_ctrl_blk(void *blk)
502 static int srcimp_mgr_get_ctrl_blk(void **rblk)
504 struct srcimp_mgr_ctrl_blk *blk;
507 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
516 static int srcimp_mgr_put_ctrl_blk(void *blk)
523 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
525 struct srcimp_mgr_ctrl_blk *ctl = blk;
527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
528 ctl->dirty.bf.srcimap = 1;
532 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
534 struct srcimp_mgr_ctrl_blk *ctl = blk;
536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
537 ctl->dirty.bf.srcimap = 1;
541 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
543 struct srcimp_mgr_ctrl_blk *ctl = blk;
545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
546 ctl->dirty.bf.srcimap = 1;
550 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
552 struct srcimp_mgr_ctrl_blk *ctl = blk;
554 ctl->srcimap.idx = addr;
555 ctl->dirty.bf.srcimap = 1;
559 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
561 struct srcimp_mgr_ctrl_blk *ctl = blk;
563 if (ctl->dirty.bf.srcimap) {
564 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
565 ctl->srcimap.srcaim);
566 ctl->dirty.bf.srcimap = 0;
573 * AMIXER control block definitions.
576 #define AMOPLO_M 0x00000003
577 #define AMOPLO_X 0x0003FFF0
578 #define AMOPLO_Y 0xFFFC0000
580 #define AMOPHI_SADR 0x000000FF
581 #define AMOPHI_SE 0x80000000
583 /* AMIXER resource register dirty flags */
593 /* AMIXER resource control block */
594 struct amixer_rsc_ctrl_blk {
597 union amixer_dirty dirty;
600 static int amixer_set_mode(void *blk, unsigned int mode)
602 struct amixer_rsc_ctrl_blk *ctl = blk;
604 set_field(&ctl->amoplo, AMOPLO_M, mode);
605 ctl->dirty.bf.amoplo = 1;
609 static int amixer_set_iv(void *blk, unsigned int iv)
611 /* 20k1 amixer does not have this field */
615 static int amixer_set_x(void *blk, unsigned int x)
617 struct amixer_rsc_ctrl_blk *ctl = blk;
619 set_field(&ctl->amoplo, AMOPLO_X, x);
620 ctl->dirty.bf.amoplo = 1;
624 static int amixer_set_y(void *blk, unsigned int y)
626 struct amixer_rsc_ctrl_blk *ctl = blk;
628 set_field(&ctl->amoplo, AMOPLO_Y, y);
629 ctl->dirty.bf.amoplo = 1;
633 static int amixer_set_sadr(void *blk, unsigned int sadr)
635 struct amixer_rsc_ctrl_blk *ctl = blk;
637 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
638 ctl->dirty.bf.amophi = 1;
642 static int amixer_set_se(void *blk, unsigned int se)
644 struct amixer_rsc_ctrl_blk *ctl = blk;
646 set_field(&ctl->amophi, AMOPHI_SE, se);
647 ctl->dirty.bf.amophi = 1;
651 static int amixer_set_dirty(void *blk, unsigned int flags)
653 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
657 static int amixer_set_dirty_all(void *blk)
659 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
663 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
665 struct amixer_rsc_ctrl_blk *ctl = blk;
667 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
668 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
669 ctl->dirty.bf.amoplo = 0;
670 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
671 ctl->dirty.bf.amophi = 0;
677 static int amixer_get_y(void *blk)
679 struct amixer_rsc_ctrl_blk *ctl = blk;
681 return get_field(ctl->amoplo, AMOPLO_Y);
684 static unsigned int amixer_get_dirty(void *blk)
686 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
689 static int amixer_rsc_get_ctrl_blk(void **rblk)
691 struct amixer_rsc_ctrl_blk *blk;
694 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
703 static int amixer_rsc_put_ctrl_blk(void *blk)
710 static int amixer_mgr_get_ctrl_blk(void **rblk)
712 /*amixer_mgr_ctrl_blk_t *blk;*/
715 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
724 static int amixer_mgr_put_ctrl_blk(void *blk)
726 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
732 * DAIO control block definitions.
735 /* Receiver Sample Rate Tracker Control register */
736 #define SRTCTL_SRCR 0x000000FF
737 #define SRTCTL_SRCL 0x0000FF00
738 #define SRTCTL_RSR 0x00030000
739 #define SRTCTL_DRAT 0x000C0000
740 #define SRTCTL_RLE 0x10000000
741 #define SRTCTL_RLP 0x20000000
742 #define SRTCTL_EC 0x40000000
743 #define SRTCTL_ET 0x80000000
745 /* DAIO Receiver register dirty flags */
754 /* DAIO Receiver control block */
755 struct dai_ctrl_blk {
757 union dai_dirty dirty;
760 /* S/PDIF Transmitter register dirty flags */
769 /* S/PDIF Transmitter control block */
770 struct dao_ctrl_blk {
771 unsigned int spos; /* S/PDIF Output Channel Status Register */
772 union dao_dirty dirty;
775 /* Audio Input Mapper RAM */
776 #define AIM_ARC 0x00000FFF
777 #define AIM_NXT 0x007F0000
784 /* I2S Transmitter/Receiver Control register */
785 #define I2SCTL_EA 0x00000004
786 #define I2SCTL_EI 0x00000010
788 /* S/PDIF Transmitter Control register */
789 #define SPOCTL_OE 0x00000001
790 #define SPOCTL_OS 0x0000000E
791 #define SPOCTL_RIV 0x00000010
792 #define SPOCTL_LIV 0x00000020
793 #define SPOCTL_SR 0x000000C0
795 /* S/PDIF Receiver Control register */
796 #define SPICTL_EN 0x00000001
797 #define SPICTL_I24 0x00000002
798 #define SPICTL_IB 0x00000004
799 #define SPICTL_SM 0x00000008
800 #define SPICTL_VM 0x00000010
802 /* DAIO manager register dirty flags */
803 union daio_mgr_dirty {
815 /* DAIO manager control block */
816 struct daio_mgr_ctrl_blk {
820 struct daoimap daoimap;
821 union daio_mgr_dirty dirty;
824 static int dai_srt_set_srcr(void *blk, unsigned int src)
826 struct dai_ctrl_blk *ctl = blk;
828 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
829 ctl->dirty.bf.srtctl = 1;
833 static int dai_srt_set_srcl(void *blk, unsigned int src)
835 struct dai_ctrl_blk *ctl = blk;
837 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
838 ctl->dirty.bf.srtctl = 1;
842 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
844 struct dai_ctrl_blk *ctl = blk;
846 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
847 ctl->dirty.bf.srtctl = 1;
851 static int dai_srt_set_drat(void *blk, unsigned int drat)
853 struct dai_ctrl_blk *ctl = blk;
855 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
856 ctl->dirty.bf.srtctl = 1;
860 static int dai_srt_set_ec(void *blk, unsigned int ec)
862 struct dai_ctrl_blk *ctl = blk;
864 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
865 ctl->dirty.bf.srtctl = 1;
869 static int dai_srt_set_et(void *blk, unsigned int et)
871 struct dai_ctrl_blk *ctl = blk;
873 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
874 ctl->dirty.bf.srtctl = 1;
878 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
880 struct dai_ctrl_blk *ctl = blk;
882 if (ctl->dirty.bf.srtctl) {
885 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
888 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
890 ctl->dirty.bf.srtctl = 0;
896 static int dai_get_ctrl_blk(void **rblk)
898 struct dai_ctrl_blk *blk;
901 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
910 static int dai_put_ctrl_blk(void *blk)
917 static int dao_set_spos(void *blk, unsigned int spos)
919 ((struct dao_ctrl_blk *)blk)->spos = spos;
920 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
924 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
926 struct dao_ctrl_blk *ctl = blk;
928 if (ctl->dirty.bf.spos) {
931 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
933 ctl->dirty.bf.spos = 0;
939 static int dao_get_spos(void *blk, unsigned int *spos)
941 *spos = ((struct dao_ctrl_blk *)blk)->spos;
945 static int dao_get_ctrl_blk(void **rblk)
947 struct dao_ctrl_blk *blk;
950 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
959 static int dao_put_ctrl_blk(void *blk)
966 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
968 struct daio_mgr_ctrl_blk *ctl = blk;
972 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
973 ctl->dirty.bf.spictl |= (0x1 << idx);
977 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
978 ctl->dirty.bf.i2sictl |= (0x1 << idx);
983 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
985 struct daio_mgr_ctrl_blk *ctl = blk;
989 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
990 ctl->dirty.bf.spictl |= (0x1 << idx);
994 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
995 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1000 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1002 struct daio_mgr_ctrl_blk *ctl = blk;
1006 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1007 ctl->dirty.bf.spoctl |= (0x1 << idx);
1011 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1012 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1017 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1019 struct daio_mgr_ctrl_blk *ctl = blk;
1023 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1024 ctl->dirty.bf.spoctl |= (0x1 << idx);
1028 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1029 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1034 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1036 struct daio_mgr_ctrl_blk *ctl = blk;
1040 switch ((conf & 0x7)) {
1042 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1045 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1048 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1051 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1056 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1057 (conf >> 4) & 0x1); /* Non-audio */
1058 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1059 (conf >> 4) & 0x1); /* Non-audio */
1060 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1061 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1063 ctl->dirty.bf.spoctl |= (0x1 << idx);
1071 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1073 struct daio_mgr_ctrl_blk *ctl = blk;
1075 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1076 ctl->dirty.bf.daoimap = 1;
1080 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1082 struct daio_mgr_ctrl_blk *ctl = blk;
1084 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1085 ctl->dirty.bf.daoimap = 1;
1089 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1091 struct daio_mgr_ctrl_blk *ctl = blk;
1093 ctl->daoimap.idx = addr;
1094 ctl->dirty.bf.daoimap = 1;
1098 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1100 struct daio_mgr_ctrl_blk *ctl = blk;
1103 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1104 for (i = 0; i < 4; i++) {
1105 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1106 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1108 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1109 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1111 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1114 if (ctl->dirty.bf.spoctl) {
1115 for (i = 0; i < 4; i++) {
1116 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1117 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1119 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1122 if (ctl->dirty.bf.spictl) {
1123 for (i = 0; i < 4; i++) {
1124 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1125 ctl->dirty.bf.spictl &= ~(0x1 << i);
1127 hw_write_20kx(hw, SPICTL, ctl->spictl);
1130 if (ctl->dirty.bf.daoimap) {
1131 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1133 ctl->dirty.bf.daoimap = 0;
1139 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1141 struct daio_mgr_ctrl_blk *blk;
1144 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1148 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1149 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1150 blk->spictl = hw_read_20kx(hw, SPICTL);
1157 static int daio_mgr_put_ctrl_blk(void *blk)
1164 /* Timer interrupt */
1165 static int set_timer_irq(struct hw *hw, int enable)
1167 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1171 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1174 ticks |= TIMR_IE | TIMR_IP;
1175 hw_write_20kx(hw, TIMR, ticks);
1179 static unsigned int get_wc(struct hw *hw)
1181 return hw_read_20kx(hw, WC);
1184 /* Card hardware initialization block */
1186 unsigned int msr; /* master sample rate in rsrs */
1190 unsigned int msr; /* master sample rate in rsrs */
1191 unsigned char input; /* the input source of ADC */
1192 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1196 unsigned int msr; /* master sample rate in rsrs */
1200 unsigned long vm_pgt_phys;
1203 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1208 /* Read I2S CTL. Keep original value. */
1209 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1210 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1211 /* Program I2S with proper master sample rate and enable
1212 * the correct I2S channel. */
1213 i2sorg &= 0xfffffffc;
1215 /* Enable S/PDIF-out-A in fixed 24-bit data
1216 * format and default to 48kHz. */
1217 /* Disable all before doing any changes. */
1218 hw_write_20kx(hw, SPOCTL, 0x0);
1221 switch (info->msr) {
1224 spdorg |= (0x0 << 6);
1228 spdorg |= (0x1 << 6);
1232 spdorg |= (0x2 << 6);
1239 hw_write_20kx(hw, I2SCTL, i2sorg);
1240 hw_write_20kx(hw, SPOCTL, spdorg);
1242 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1243 /* Disable all before doing any changes. */
1244 hw_write_20kx(hw, SPICTL, 0x0);
1246 spdorg = 0x0a0a0a0a;
1247 hw_write_20kx(hw, SPICTL, spdorg);
1253 /* TRANSPORT operations */
1254 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1257 u32 ptp_phys_low, ptp_phys_high;
1259 /* Set up device page table */
1260 if ((~0UL) == info->vm_pgt_phys) {
1261 dev_err(hw->card->dev,
1262 "Wrong device page table page address!\n");
1266 trnctl = 0x13; /* 32-bit, 4k-size page */
1267 ptp_phys_low = (u32)info->vm_pgt_phys;
1268 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1269 if (sizeof(void *) == 8) /* 64bit address */
1271 #if 0 /* Only 4k h/w pages for simplicitiy */
1272 #if PAGE_SIZE == 8192
1276 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1277 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1278 hw_write_20kx(hw, TRNCTL, trnctl);
1279 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
1284 /* Card initialization */
1285 #define GCTL_EAC 0x00000001
1286 #define GCTL_EAI 0x00000002
1287 #define GCTL_BEP 0x00000004
1288 #define GCTL_BES 0x00000008
1289 #define GCTL_DSP 0x00000010
1290 #define GCTL_DBP 0x00000020
1291 #define GCTL_ABP 0x00000040
1292 #define GCTL_TBP 0x00000080
1293 #define GCTL_SBP 0x00000100
1294 #define GCTL_FBP 0x00000200
1295 #define GCTL_XA 0x00000400
1296 #define GCTL_ET 0x00000800
1297 #define GCTL_PR 0x00001000
1298 #define GCTL_MRL 0x00002000
1299 #define GCTL_SDE 0x00004000
1300 #define GCTL_SDI 0x00008000
1301 #define GCTL_SM 0x00010000
1302 #define GCTL_SR 0x00020000
1303 #define GCTL_SD 0x00040000
1304 #define GCTL_SE 0x00080000
1305 #define GCTL_AID 0x00100000
1307 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1309 unsigned int pllctl;
1312 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1313 for (i = 0; i < 3; i++) {
1314 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1317 hw_write_20kx(hw, PLLCTL, pllctl);
1321 dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
1328 static int hw_auto_init(struct hw *hw)
1333 gctl = hw_read_20kx(hw, GCTL);
1334 set_field(&gctl, GCTL_EAI, 0);
1335 hw_write_20kx(hw, GCTL, gctl);
1336 set_field(&gctl, GCTL_EAI, 1);
1337 hw_write_20kx(hw, GCTL, gctl);
1339 for (i = 0; i < 400000; i++) {
1340 gctl = hw_read_20kx(hw, GCTL);
1341 if (get_field(gctl, GCTL_AID))
1344 if (!get_field(gctl, GCTL_AID)) {
1345 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1352 static int i2c_unlock(struct hw *hw)
1354 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1357 hw_write_pci(hw, 0xcc, 0x8c);
1358 hw_write_pci(hw, 0xcc, 0x0e);
1359 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1362 hw_write_pci(hw, 0xcc, 0xee);
1363 hw_write_pci(hw, 0xcc, 0xaa);
1364 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1370 static void i2c_lock(struct hw *hw)
1372 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1373 hw_write_pci(hw, 0xcc, 0x00);
1376 static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1381 ret = hw_read_pci(hw, 0xEC);
1382 } while (!(ret & 0x800000));
1383 hw_write_pci(hw, 0xE0, device);
1384 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1387 /* DAC operations */
1389 static int hw_reset_dac(struct hw *hw)
1399 ret = hw_read_pci(hw, 0xEC);
1400 } while (!(ret & 0x800000));
1401 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1403 /* To be effective, need to reset the DAC twice. */
1404 for (i = 0; i < 2; i++) {
1407 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1409 hw_write_20kx(hw, GPIO, gpioorg);
1411 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1414 i2c_write(hw, 0x00180080, 0x01, 0x80);
1415 i2c_write(hw, 0x00180080, 0x02, 0x10);
1422 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1428 if (hw->model == CTSB055X) {
1429 /* SB055x, unmute outputs */
1430 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1431 gpioorg &= 0xffbf; /* set GPIO6 to low */
1432 gpioorg |= 2; /* set GPIO1 to high */
1433 hw_write_20kx(hw, GPIO, gpioorg);
1438 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1440 hw_write_20kx(hw, GPIO, gpioorg);
1447 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1449 ret = hw_read_pci(hw, 0xEC);
1450 } while (!(ret & 0x800000));
1452 switch (info->msr) {
1467 i2c_write(hw, 0x00180080, 0x06, data);
1468 i2c_write(hw, 0x00180080, 0x09, data);
1469 i2c_write(hw, 0x00180080, 0x0c, data);
1470 i2c_write(hw, 0x00180080, 0x0f, data);
1474 /* unmute outputs */
1475 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1476 gpioorg = gpioorg | 0x40;
1477 hw_write_20kx(hw, GPIO, gpioorg);
1482 /* ADC operations */
1484 static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1489 static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1493 data = hw_read_20kx(hw, GPIO);
1496 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1499 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1501 case ADC_NONE: /* Digital I/O */
1502 data = (!(data & (0x1<<8)));
1510 static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1514 data = hw_read_20kx(hw, GPIO);
1517 data = (data & (0x1 << 7)) ? 1 : 0;
1520 data = (data & (0x1 << 7)) ? 0 : 1;
1528 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1530 switch (hw->model) {
1532 return is_adc_input_selected_SB055x(hw, type);
1534 return is_adc_input_selected_hendrix(hw, type);
1536 return is_adc_input_selected_hendrix(hw, type);
1538 return is_adc_input_selected_SBx(hw, type);
1543 adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1548 * check and set the following GPIO bits accordingly
1551 * Mic_Pwr_on = GPIO7
1552 * Digital_IO_Sel = GPIO8
1554 * Aux/MicLine_Sw = GPIO12
1556 data = hw_read_20kx(hw, GPIO);
1560 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1561 data |= boost ? (0x1<<2) : 0;
1567 data |= (0x1<<8) | (0x1<<12);
1570 data |= (0x1<<12); /* set to digital */
1576 hw_write_20kx(hw, GPIO, data);
1583 adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1593 ret = hw_read_pci(hw, 0xEC);
1594 } while (!(ret & 0x800000)); /* i2c ready poll */
1595 /* set i2c access mode as Direct Control */
1596 hw_write_pci(hw, 0xEC, 0x05);
1598 data = hw_read_20kx(hw, GPIO);
1601 data |= ((0x1 << 7) | (0x1 << 8));
1602 i2c_data = 0x1; /* Mic-in */
1605 data &= ~(0x1 << 7);
1607 i2c_data = 0x2; /* Line-in */
1610 data &= ~(0x1 << 8);
1611 i2c_data = 0x0; /* set to Digital */
1617 hw_write_20kx(hw, GPIO, data);
1618 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1620 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1621 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1623 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1624 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1633 adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1643 ret = hw_read_pci(hw, 0xEC);
1644 } while (!(ret & 0x800000)); /* i2c ready poll */
1645 /* set i2c access mode as Direct Control */
1646 hw_write_pci(hw, 0xEC, 0x05);
1648 data = hw_read_20kx(hw, GPIO);
1652 i2c_data = 0x1; /* Mic-in */
1655 data &= ~(0x1 << 7);
1656 i2c_data = 0x2; /* Line-in */
1662 hw_write_20kx(hw, GPIO, data);
1663 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1665 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1666 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1668 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1669 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1677 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1679 int state = type == ADC_MICIN;
1681 switch (hw->model) {
1683 return adc_input_select_SB055x(hw, type, state);
1685 return adc_input_select_hendrix(hw, type, state);
1687 return adc_input_select_hendrix(hw, type, state);
1689 return adc_input_select_SBx(hw, type, state);
1693 static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1695 return adc_input_select_SB055x(hw, input, mic20db);
1698 static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1705 input_source = 0x100; /* default to analog */
1709 input_source = 0x180; /* set GPIO7 to select Mic */
1722 input_source = 0x0; /* set to Digital */
1733 ret = hw_read_pci(hw, 0xEC);
1734 } while (!(ret & 0x800000)); /* i2c ready poll */
1735 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1737 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1738 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1739 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1740 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1743 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1744 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1746 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1747 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1750 if (!(hw_read_20kx(hw, ID0) & 0x100))
1751 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1755 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1757 gpioorg |= input_source;
1758 hw_write_20kx(hw, GPIO, gpioorg);
1763 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1765 if (hw->model == CTSB055X)
1766 return adc_init_SB055x(hw, info->input, info->mic20db);
1768 return adc_init_SBx(hw, info->input, info->mic20db);
1771 static struct capabilities hw_capabilities(struct hw *hw)
1773 struct capabilities cap;
1775 /* SB073x and Vista compatible cards have no digit IO switch */
1776 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
1777 cap.dedicated_mic = 0;
1778 cap.output_switch = 0;
1779 cap.mic_source_switch = 0;
1784 #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1786 #define UAA_CFG_PWRSTATUS 0x44
1787 #define UAA_CFG_SPACE_FLAG 0xA0
1788 #define UAA_CORE_CHANGE 0x3FFC
1789 static int uaa_to_xfi(struct pci_dev *pci)
1791 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1792 unsigned int cmd, irq, cl_size, l_timer, pwr;
1793 unsigned int is_uaa;
1794 unsigned int data[4] = {0};
1795 unsigned int io_base;
1796 void __iomem *mem_base;
1798 const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1799 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1800 const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1801 const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1802 const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1803 const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1804 const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1806 /* By default, Hendrix card UAA Bar0 should be using memory... */
1807 io_base = pci_resource_start(pci, 0);
1808 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1812 /* Read current mode from Mode Change Register */
1813 for (i = 0; i < 4; i++)
1814 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1816 /* Determine current mode... */
1817 if (data[0] == CTLA) {
1818 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1819 && data[3] == CTLA) || (data[1] == CTLA
1820 && data[2] == CTLZ && data[3] == CTLL));
1821 } else if (data[0] == CTLZ) {
1822 is_uaa = (data[1] == CTLL
1823 && data[2] == CTLA && data[3] == CTLA);
1824 } else if (data[0] == CTLL) {
1825 is_uaa = (data[1] == CTLA
1826 && data[2] == CTLA && data[3] == CTLZ);
1832 /* Not in UAA mode currently. Return directly. */
1837 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1838 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1839 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1840 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1843 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1844 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1845 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1846 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1847 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1849 /* Set up X-Fi core PCI configuration space. */
1850 /* Switch to X-Fi config space with BAR0 exposed. */
1851 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1852 /* Copy UAA's BAR5 into X-Fi BAR0 */
1853 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1854 /* Switch to X-Fi config space without BAR0 exposed. */
1855 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1856 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1859 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1860 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1861 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1862 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1863 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1864 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1866 /* Switch to X-Fi mode */
1867 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1868 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1869 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1870 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1877 static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1879 struct hw *hw = dev_id;
1880 unsigned int status;
1882 status = hw_read_20kx(hw, GIP);
1886 if (hw->irq_callback)
1887 hw->irq_callback(hw->irq_callback_data, status);
1889 hw_write_20kx(hw, GIP, status);
1893 static int hw_card_start(struct hw *hw)
1896 struct pci_dev *pci = hw->pci;
1897 const unsigned int dma_bits = BITS_PER_LONG;
1899 err = pci_enable_device(pci);
1903 /* Set DMA transfer mask */
1904 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1905 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1907 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1908 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1912 err = pci_request_regions(pci, "XFi");
1916 if (hw->model == CTUAA)
1917 hw->io_base = pci_resource_start(pci, 5);
1919 hw->io_base = pci_resource_start(pci, 0);
1923 /* Switch to X-Fi mode from UAA mode if neeeded */
1924 if (hw->model == CTUAA) {
1925 err = uaa_to_xfi(pci);
1932 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1933 KBUILD_MODNAME, hw);
1935 dev_err(hw->card->dev,
1936 "XFi: Cannot get irq %d\n", pci->irq);
1940 hw->card->sync_irq = hw->irq;
1943 pci_set_master(pci);
1948 pci_release_regions(pci);
1951 pci_disable_device(pci);
1955 static int hw_card_stop(struct hw *hw)
1959 /* disable transport bus master and queueing of request */
1960 hw_write_20kx(hw, TRNCTL, 0x00);
1963 data = hw_read_20kx(hw, PLLCTL);
1964 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
1969 static int hw_card_shutdown(struct hw *hw)
1972 free_irq(hw->irq, hw);
1975 iounmap(hw->mem_base);
1976 hw->mem_base = NULL;
1979 pci_release_regions(hw->pci);
1983 pci_disable_device(hw->pci);
1988 static int hw_card_init(struct hw *hw, struct card_conf *info)
1993 struct dac_conf dac_info = {0};
1994 struct adc_conf adc_info = {0};
1995 struct daio_conf daio_info = {0};
1996 struct trn_conf trn_info = {0};
1998 /* Get PCI io port base address and do Hendrix switch if needed. */
1999 err = hw_card_start(hw);
2004 err = hw_pll_init(hw, info->rsr);
2008 /* kick off auto-init */
2009 err = hw_auto_init(hw);
2013 /* Enable audio ring */
2014 gctl = hw_read_20kx(hw, GCTL);
2015 set_field(&gctl, GCTL_EAC, 1);
2016 set_field(&gctl, GCTL_DBP, 1);
2017 set_field(&gctl, GCTL_TBP, 1);
2018 set_field(&gctl, GCTL_FBP, 1);
2019 set_field(&gctl, GCTL_ET, 1);
2020 hw_write_20kx(hw, GCTL, gctl);
2023 /* Reset all global pending interrupts */
2024 hw_write_20kx(hw, GIE, 0);
2025 /* Reset all SRC pending interrupts */
2026 hw_write_20kx(hw, SRCIP, 0);
2029 /* Detect the card ID and configure GPIO accordingly. */
2030 switch (hw->model) {
2032 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2035 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2038 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2041 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2045 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2046 err = hw_trn_init(hw, &trn_info);
2050 daio_info.msr = info->msr;
2051 err = hw_daio_init(hw, &daio_info);
2055 dac_info.msr = info->msr;
2056 err = hw_dac_init(hw, &dac_info);
2060 adc_info.msr = info->msr;
2061 adc_info.input = ADC_LINEIN;
2062 adc_info.mic20db = 0;
2063 err = hw_adc_init(hw, &adc_info);
2067 data = hw_read_20kx(hw, SRCMCTL);
2068 data |= 0x1; /* Enables input from the audio ring */
2069 hw_write_20kx(hw, SRCMCTL, data);
2074 #ifdef CONFIG_PM_SLEEP
2075 static int hw_suspend(struct hw *hw)
2077 struct pci_dev *pci = hw->pci;
2081 if (hw->model == CTUAA) {
2082 /* Switch to UAA config space. */
2083 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
2089 static int hw_resume(struct hw *hw, struct card_conf *info)
2091 /* Re-initialize card hardware. */
2092 return hw_card_init(hw, info);
2096 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2099 unsigned long flags;
2102 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2103 outl(reg, hw->io_base + 0x0);
2104 value = inl(hw->io_base + 0x4);
2105 spin_unlock_irqrestore(
2106 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2111 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2113 unsigned long flags;
2116 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2117 outl(reg, hw->io_base + 0x0);
2118 outl(data, hw->io_base + 0x4);
2119 spin_unlock_irqrestore(
2120 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2124 static u32 hw_read_pci(struct hw *hw, u32 reg)
2127 unsigned long flags;
2130 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2131 outl(reg, hw->io_base + 0x10);
2132 value = inl(hw->io_base + 0x14);
2133 spin_unlock_irqrestore(
2134 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2139 static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2141 unsigned long flags;
2144 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2145 outl(reg, hw->io_base + 0x10);
2146 outl(data, hw->io_base + 0x14);
2147 spin_unlock_irqrestore(
2148 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2151 static const struct hw ct20k1_preset = {
2154 .card_init = hw_card_init,
2155 .card_stop = hw_card_stop,
2156 .pll_init = hw_pll_init,
2157 .is_adc_source_selected = hw_is_adc_input_selected,
2158 .select_adc_source = hw_adc_input_select,
2159 .capabilities = hw_capabilities,
2160 #ifdef CONFIG_PM_SLEEP
2161 .suspend = hw_suspend,
2162 .resume = hw_resume,
2165 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2166 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2167 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2168 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2169 .src_set_state = src_set_state,
2170 .src_set_bm = src_set_bm,
2171 .src_set_rsr = src_set_rsr,
2172 .src_set_sf = src_set_sf,
2173 .src_set_wr = src_set_wr,
2174 .src_set_pm = src_set_pm,
2175 .src_set_rom = src_set_rom,
2176 .src_set_vo = src_set_vo,
2177 .src_set_st = src_set_st,
2178 .src_set_ie = src_set_ie,
2179 .src_set_ilsz = src_set_ilsz,
2180 .src_set_bp = src_set_bp,
2181 .src_set_cisz = src_set_cisz,
2182 .src_set_ca = src_set_ca,
2183 .src_set_sa = src_set_sa,
2184 .src_set_la = src_set_la,
2185 .src_set_pitch = src_set_pitch,
2186 .src_set_dirty = src_set_dirty,
2187 .src_set_clear_zbufs = src_set_clear_zbufs,
2188 .src_set_dirty_all = src_set_dirty_all,
2189 .src_commit_write = src_commit_write,
2190 .src_get_ca = src_get_ca,
2191 .src_get_dirty = src_get_dirty,
2192 .src_dirty_conj_mask = src_dirty_conj_mask,
2193 .src_mgr_enbs_src = src_mgr_enbs_src,
2194 .src_mgr_enb_src = src_mgr_enb_src,
2195 .src_mgr_dsb_src = src_mgr_dsb_src,
2196 .src_mgr_commit_write = src_mgr_commit_write,
2198 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2199 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2200 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2201 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2202 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2203 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2204 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2206 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2207 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2208 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2209 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2210 .amixer_set_mode = amixer_set_mode,
2211 .amixer_set_iv = amixer_set_iv,
2212 .amixer_set_x = amixer_set_x,
2213 .amixer_set_y = amixer_set_y,
2214 .amixer_set_sadr = amixer_set_sadr,
2215 .amixer_set_se = amixer_set_se,
2216 .amixer_set_dirty = amixer_set_dirty,
2217 .amixer_set_dirty_all = amixer_set_dirty_all,
2218 .amixer_commit_write = amixer_commit_write,
2219 .amixer_get_y = amixer_get_y,
2220 .amixer_get_dirty = amixer_get_dirty,
2222 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2223 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2224 .dai_srt_set_srco = dai_srt_set_srcr,
2225 .dai_srt_set_srcm = dai_srt_set_srcl,
2226 .dai_srt_set_rsr = dai_srt_set_rsr,
2227 .dai_srt_set_drat = dai_srt_set_drat,
2228 .dai_srt_set_ec = dai_srt_set_ec,
2229 .dai_srt_set_et = dai_srt_set_et,
2230 .dai_commit_write = dai_commit_write,
2232 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2233 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2234 .dao_set_spos = dao_set_spos,
2235 .dao_commit_write = dao_commit_write,
2236 .dao_get_spos = dao_get_spos,
2238 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2239 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2240 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2241 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2242 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2243 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2244 .daio_mgr_dao_init = daio_mgr_dao_init,
2245 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2246 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2247 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2248 .daio_mgr_commit_write = daio_mgr_commit_write,
2250 .set_timer_irq = set_timer_irq,
2251 .set_timer_tick = set_timer_tick,
2255 int create_20k1_hw_obj(struct hw **rhw)
2257 struct hw20k1 *hw20k1;
2260 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2264 spin_lock_init(&hw20k1->reg_20k1_lock);
2265 spin_lock_init(&hw20k1->reg_pci_lock);
2267 hw20k1->hw = ct20k1_preset;
2274 int destroy_20k1_hw_obj(struct hw *hw)
2277 hw_card_shutdown(hw);
2279 kfree(container_of(hw, struct hw20k1, hw));