2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
5 * Routines for control of Cirrus Logic CS461x chips
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer control.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #include <linux/delay.h>
49 #include <linux/pci.h>
51 #include <linux/init.h>
52 #include <linux/interrupt.h>
53 #include <linux/slab.h>
54 #include <linux/gameport.h>
55 #include <linux/mutex.h>
56 #include <linux/export.h>
57 #include <linux/module.h>
58 #include <linux/firmware.h>
59 #include <linux/vmalloc.h>
62 #include <sound/core.h>
63 #include <sound/control.h>
64 #include <sound/info.h>
65 #include <sound/pcm.h>
66 #include <sound/pcm_params.h>
69 #include "cs46xx_lib.h"
72 static void amp_voyetra(struct snd_cs46xx *chip, int change);
74 #ifdef CONFIG_SND_CS46XX_NEW_DSP
75 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
76 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
77 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
78 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
79 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
80 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
83 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
84 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
85 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
86 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
88 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
93 unsigned short result,tmp;
96 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
97 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
100 chip->active_ctrl(chip, 1);
102 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
103 offset = CS46XX_SECONDARY_CODEC_OFFSET;
106 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
107 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
108 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
109 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
110 * 5. if DCV not cleared, break and return error
111 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
114 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
116 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
117 if ((tmp & ACCTL_VFRM) == 0) {
118 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
119 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
121 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
122 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
127 * Setup the AC97 control registers on the CS461x to send the
128 * appropriate command to the AC97 to perform the read.
129 * ACCAD = Command Address Register = 46Ch
130 * ACCDA = Command Data Register = 470h
131 * ACCTL = Control Register = 460h
132 * set DCV - will clear when process completed
133 * set CRW - Read command
134 * set VFRM - valid frame enabled
135 * set ESYN - ASYNC generation enabled
136 * set RSTN - ARST# inactive, AC97 codec not reset
139 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
140 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
141 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
142 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
143 ACCTL_VFRM | ACCTL_ESYN |
145 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
146 ACCTL_VFRM | ACCTL_ESYN |
149 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
150 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
155 * Wait for the read to occur.
157 for (count = 0; count < 1000; count++) {
159 * First, we want to wait for a short time.
163 * Now, check to see if the read has completed.
164 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
166 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
170 dev_err(chip->card->dev,
171 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
177 * Wait for the valid status bit to go active.
179 for (count = 0; count < 100; count++) {
181 * Read the AC97 status register.
182 * ACSTS = Status Register = 464h
183 * VSTS - Valid Status
185 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
190 dev_err(chip->card->dev,
191 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
198 * Read the data returned from the AC97 register.
199 * ACSDA = Status Data Register = 474h
202 dev_dbg(chip->card->dev,
203 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
204 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
205 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
208 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
209 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
211 chip->active_ctrl(chip, -1);
215 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
218 struct snd_cs46xx *chip = ac97->private_data;
220 int codec_index = ac97->num;
222 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
223 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
226 val = snd_cs46xx_codec_read(chip, reg, codec_index);
232 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
239 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
240 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
243 chip->active_ctrl(chip, 1);
246 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
247 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
248 * 3. Write ACCTL = Control Register = 460h for initiating the write
249 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
250 * 5. if DCV not cleared, break and return error
254 * Setup the AC97 control registers on the CS461x to send the
255 * appropriate command to the AC97 to perform the read.
256 * ACCAD = Command Address Register = 46Ch
257 * ACCDA = Command Data Register = 470h
258 * ACCTL = Control Register = 460h
259 * set DCV - will clear when process completed
260 * reset CRW - Write command
261 * set VFRM - valid frame enabled
262 * set ESYN - ASYNC generation enabled
263 * set RSTN - ARST# inactive, AC97 codec not reset
265 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
266 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
267 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
269 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
270 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
271 ACCTL_ESYN | ACCTL_RSTN);
272 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
273 ACCTL_ESYN | ACCTL_RSTN);
275 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
276 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
279 for (count = 0; count < 4000; count++) {
281 * First, we want to wait for a short time.
285 * Now, check to see if the write has completed.
286 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
288 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
292 dev_err(chip->card->dev,
293 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
294 codec_index, reg, val);
296 chip->active_ctrl(chip, -1);
299 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
303 struct snd_cs46xx *chip = ac97->private_data;
304 int codec_index = ac97->num;
306 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
307 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
310 snd_cs46xx_codec_write(chip, reg, val, codec_index);
315 * Chip initialization
318 int snd_cs46xx_download(struct snd_cs46xx *chip,
320 unsigned long offset,
324 unsigned int bank = offset >> 16;
325 offset = offset & 0xffff;
327 if (snd_BUG_ON((offset & 3) || (len & 3)))
329 dst = chip->region.idx[bank+1].remap_addr + offset;
332 /* writel already converts 32-bit value to right endianess */
340 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
342 #ifdef __LITTLE_ENDIAN
343 memcpy(dst, src, len);
346 const __le32 *_src = src;
349 *_dst++ = le32_to_cpu(*_src++);
353 #ifdef CONFIG_SND_CS46XX_NEW_DSP
355 static const char *module_names[CS46XX_DSP_MODULES] = {
356 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
361 static void free_module_desc(struct dsp_module_desc *module)
365 kfree(module->module_name);
366 kfree(module->symbol_table.symbols);
367 if (module->segments) {
369 for (i = 0; i < module->nsegments; i++)
370 kfree(module->segments[i].data);
371 kfree(module->segments);
376 /* firmware binary format:
380 * char symbol_name[DSP_MAX_SYMBOL_NAME];
382 * } symbols[nsymbols];
389 * } segments[nsegments];
392 static int load_firmware(struct snd_cs46xx *chip,
393 struct dsp_module_desc **module_ret,
397 unsigned int nums, fwlen, fwsize;
399 struct dsp_module_desc *module = NULL;
400 const struct firmware *fw;
403 sprintf(fw_path, "cs46xx/%s", fw_name);
404 err = reject_firmware(&fw, fw_path, &chip->pci->dev);
407 fwsize = fw->size / 4;
414 module = kzalloc(sizeof(*module), GFP_KERNEL);
417 module->module_name = kstrdup(fw_name, GFP_KERNEL);
418 if (!module->module_name)
422 fwdat = (const __le32 *)fw->data;
423 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
426 module->symbol_table.symbols =
427 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
428 if (!module->symbol_table.symbols)
430 for (i = 0; i < nums; i++) {
431 struct dsp_symbol_entry *entry =
432 &module->symbol_table.symbols[i];
433 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
435 entry->address = le32_to_cpu(fwdat[fwlen++]);
436 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
437 fwlen += DSP_MAX_SYMBOL_NAME / 4;
438 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
443 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
447 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
448 if (!module->segments)
450 for (i = 0; i < nums; i++) {
451 struct dsp_segment_desc *entry = &module->segments[i];
452 if (fwlen + 3 > fwsize)
454 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
455 entry->offset = le32_to_cpu(fwdat[fwlen++]);
456 entry->size = le32_to_cpu(fwdat[fwlen++]);
457 if (fwlen + entry->size > fwsize)
459 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
462 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
463 fwlen += entry->size;
466 *module_ret = module;
467 release_firmware(fw);
473 free_module_desc(module);
474 release_firmware(fw);
478 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
479 unsigned long offset,
483 unsigned int bank = offset >> 16;
484 offset = offset & 0xffff;
486 if (snd_BUG_ON((offset & 3) || (len & 3)))
488 dst = chip->region.idx[bank+1].remap_addr + offset;
491 /* writel already converts 32-bit value to right endianess */
499 #else /* old DSP image */
505 } memory[BA1_MEMORY_COUNT];
506 u32 map[BA1_DWORD_SIZE];
511 static int load_firmware(struct snd_cs46xx *chip)
513 const struct firmware *fw;
516 err = reject_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
519 if (fw->size != sizeof(*chip->ba1)) {
524 chip->ba1 = vmalloc(sizeof(*chip->ba1));
530 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
534 for (i = 0; i < BA1_MEMORY_COUNT; i++)
535 size += chip->ba1->memory[i].size;
536 if (size > BA1_DWORD_SIZE * 4)
540 release_firmware(fw);
544 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
547 unsigned int offset = 0;
548 struct ba1_struct *ba1 = chip->ba1;
550 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
551 err = snd_cs46xx_download(chip,
553 ba1->memory[idx].offset,
554 ba1->memory[idx].size);
557 offset += ba1->memory[idx].size >> 2;
561 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
567 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
572 * Write the reset bit of the SP control register.
574 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
577 * Write the control register.
579 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
582 * Clear the trap registers.
584 for (idx = 0; idx < 8; idx++) {
585 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
586 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
588 snd_cs46xx_poke(chip, BA1_DREG, 0);
591 * Set the frame timer to reflect the number of cycles per frame.
593 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
596 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
600 * Make sure the previous FIFO write operation has completed.
602 for(i = 0; i < 50; i++){
603 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
605 if( !(status & SERBST_WBSY) )
608 mdelay(retry_timeout);
611 if(status & SERBST_WBSY) {
612 dev_err(chip->card->dev,
613 "failure waiting for FIFO command to complete\n");
620 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
622 int idx, powerdown = 0;
626 * See if the devices are powered down. If so, we must power them up first
627 * or they will not respond.
629 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
630 if (!(tmp & CLKCR1_SWCE)) {
631 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
636 * We want to clear out the serial port FIFOs so we don't end up playing
637 * whatever random garbage happens to be in them. We fill the sample FIFOS
638 * with zero (silence).
640 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
643 * Fill all 256 sample FIFO locations.
645 for (idx = 0; idx < 0xFF; idx++) {
647 * Make sure the previous FIFO write operation has completed.
649 if (cs46xx_wait_for_fifo(chip,1)) {
650 dev_dbg(chip->card->dev,
651 "failed waiting for FIFO at addr (%02X)\n",
655 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
660 * Write the serial port FIFO index.
662 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
664 * Tell the serial port to load the new value into the FIFO location.
666 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
669 * Now, if we powered up the devices, then power them back down again.
670 * This is kinda ugly, but should never happen.
673 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
676 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
681 * Set the frame timer to reflect the number of cycles per frame.
683 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
685 * Turn on the run, run at frame, and DMA enable bits in the local copy of
686 * the SP control register.
688 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
690 * Wait until the run at frame bit resets itself in the SP control
693 for (cnt = 0; cnt < 25; cnt++) {
695 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
699 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
700 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
703 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
706 * Turn off the run, run at frame, and DMA enable bits in the local copy of
707 * the SP control register.
709 snd_cs46xx_poke(chip, BA1_SPCR, 0);
713 * Sample rate routines
716 #define GOF_PER_SEC 200
718 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
721 unsigned int tmp1, tmp2;
722 unsigned int phiIncr;
723 unsigned int correctionPerGOF, correctionPerSec;
726 * Compute the values used to drive the actual sample rate conversion.
727 * The following formulas are being computed, using inline assembly
728 * since we need to use 64 bit arithmetic to compute the values:
730 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
731 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
733 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
734 * GOF_PER_SEC * correctionPerGOF
738 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
739 * correctionPerGOF:correctionPerSec =
740 * dividend:remainder(ulOther / GOF_PER_SEC)
743 phiIncr = tmp1 / 48000;
744 tmp1 -= phiIncr * 48000;
749 tmp1 -= tmp2 * 48000;
750 correctionPerGOF = tmp1 / GOF_PER_SEC;
751 tmp1 -= correctionPerGOF * GOF_PER_SEC;
752 correctionPerSec = tmp1;
755 * Fill in the SampleRateConverter control block.
757 spin_lock_irqsave(&chip->reg_lock, flags);
758 snd_cs46xx_poke(chip, BA1_PSRC,
759 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
760 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
761 spin_unlock_irqrestore(&chip->reg_lock, flags);
764 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
767 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
768 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
769 unsigned int frameGroupLength, cnt;
772 * We can only decimate by up to a factor of 1/9th the hardware rate.
773 * Correct the value if an attempt is made to stray outside that limit.
775 if ((rate * 9) < 48000)
779 * We can not capture at a rate greater than the Input Rate (48000).
780 * Return an error if an attempt is made to stray outside that limit.
786 * Compute the values used to drive the actual sample rate conversion.
787 * The following formulas are being computed, using inline assembly
788 * since we need to use 64 bit arithmetic to compute the values:
790 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
791 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
794 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
795 * GOF_PER_SEC * correctionPerGOF
796 * initialDelay = ceil((24 * Fs,in) / Fs,out)
800 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
801 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
802 * correctionPerGOF:correctionPerSec =
803 * dividend:remainder(ulOther / GOF_PER_SEC)
804 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
808 coeffIncr = tmp1 / 48000;
809 tmp1 -= coeffIncr * 48000;
812 coeffIncr += tmp1 / 48000;
813 coeffIncr ^= 0xFFFFFFFF;
816 phiIncr = tmp1 / rate;
817 tmp1 -= phiIncr * rate;
823 correctionPerGOF = tmp1 / GOF_PER_SEC;
824 tmp1 -= correctionPerGOF * GOF_PER_SEC;
825 correctionPerSec = tmp1;
826 initialDelay = ((48000 * 24) + rate - 1) / rate;
829 * Fill in the VariDecimate control block.
831 spin_lock_irqsave(&chip->reg_lock, flags);
832 snd_cs46xx_poke(chip, BA1_CSRC,
833 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
834 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
835 snd_cs46xx_poke(chip, BA1_CD,
836 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
837 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
838 spin_unlock_irqrestore(&chip->reg_lock, flags);
841 * Figure out the frame group length for the write back task. Basically,
842 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
843 * the output sample rate.
845 frameGroupLength = 1;
846 for (cnt = 2; cnt <= 64; cnt *= 2) {
847 if (((rate / cnt) * cnt) != rate)
848 frameGroupLength *= 2;
850 if (((rate / 3) * 3) != rate) {
851 frameGroupLength *= 3;
853 for (cnt = 5; cnt <= 125; cnt *= 5) {
854 if (((rate / cnt) * cnt) != rate)
855 frameGroupLength *= 5;
859 * Fill in the WriteBack control block.
861 spin_lock_irqsave(&chip->reg_lock, flags);
862 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
863 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
864 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
865 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
866 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
867 spin_unlock_irqrestore(&chip->reg_lock, flags);
874 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
875 struct snd_pcm_indirect *rec, size_t bytes)
877 struct snd_pcm_runtime *runtime = substream->runtime;
878 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
879 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
882 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
886 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
887 snd_cs46xx_pb_trans_copy);
890 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
891 struct snd_pcm_indirect *rec, size_t bytes)
893 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
894 struct snd_pcm_runtime *runtime = substream->runtime;
895 memcpy(runtime->dma_area + rec->sw_data,
896 chip->capt.hw_buf.area + rec->hw_data, bytes);
899 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
901 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
902 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
903 snd_cs46xx_cp_trans_copy);
906 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
908 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
910 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
912 if (snd_BUG_ON(!cpcm->pcm_channel))
915 #ifdef CONFIG_SND_CS46XX_NEW_DSP
916 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
918 ptr = snd_cs46xx_peek(chip, BA1_PBA);
920 ptr -= cpcm->hw_buf.addr;
921 return ptr >> cpcm->shift;
924 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
926 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
928 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
930 #ifdef CONFIG_SND_CS46XX_NEW_DSP
931 if (snd_BUG_ON(!cpcm->pcm_channel))
933 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
935 ptr = snd_cs46xx_peek(chip, BA1_PBA);
937 ptr -= cpcm->hw_buf.addr;
938 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
941 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
943 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
944 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
945 return ptr >> chip->capt.shift;
948 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
950 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
951 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
952 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
955 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
958 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
959 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
962 #ifdef CONFIG_SND_CS46XX_NEW_DSP
963 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
964 if (! cpcm->pcm_channel) {
969 case SNDRV_PCM_TRIGGER_START:
970 case SNDRV_PCM_TRIGGER_RESUME:
971 #ifdef CONFIG_SND_CS46XX_NEW_DSP
972 /* magic value to unmute PCM stream playback volume */
973 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
974 SCBVolumeCtrl) << 2, 0x80008000);
976 if (cpcm->pcm_channel->unlinked)
977 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
979 if (substream->runtime->periods != CS46XX_FRAGS)
980 snd_cs46xx_playback_transfer(substream);
982 spin_lock(&chip->reg_lock);
983 if (substream->runtime->periods != CS46XX_FRAGS)
984 snd_cs46xx_playback_transfer(substream);
986 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
988 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
990 spin_unlock(&chip->reg_lock);
993 case SNDRV_PCM_TRIGGER_STOP:
994 case SNDRV_PCM_TRIGGER_SUSPEND:
995 #ifdef CONFIG_SND_CS46XX_NEW_DSP
996 /* magic mute channel */
997 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
998 SCBVolumeCtrl) << 2, 0xffffffff);
1000 if (!cpcm->pcm_channel->unlinked)
1001 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
1003 spin_lock(&chip->reg_lock);
1005 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
1007 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1009 spin_unlock(&chip->reg_lock);
1020 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1023 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1027 spin_lock(&chip->reg_lock);
1029 case SNDRV_PCM_TRIGGER_START:
1030 case SNDRV_PCM_TRIGGER_RESUME:
1031 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1033 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1035 case SNDRV_PCM_TRIGGER_STOP:
1036 case SNDRV_PCM_TRIGGER_SUSPEND:
1037 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1039 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1045 spin_unlock(&chip->reg_lock);
1050 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1051 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1055 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1056 if ( cpcm->pcm_channel == NULL) {
1057 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1058 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1059 if (cpcm->pcm_channel == NULL) {
1060 dev_err(chip->card->dev,
1061 "failed to create virtual PCM channel\n");
1064 cpcm->pcm_channel->sample_rate = sample_rate;
1066 /* if sample rate is changed */
1067 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1068 int unlinked = cpcm->pcm_channel->unlinked;
1069 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1071 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1073 cpcm->pcm_channel_id)) == NULL) {
1074 dev_err(chip->card->dev,
1075 "failed to re-create virtual PCM channel\n");
1079 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1080 cpcm->pcm_channel->sample_rate = sample_rate;
1088 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1089 struct snd_pcm_hw_params *hw_params)
1091 struct snd_pcm_runtime *runtime = substream->runtime;
1092 struct snd_cs46xx_pcm *cpcm;
1094 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1095 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1096 int sample_rate = params_rate(hw_params);
1097 int period_size = params_period_bytes(hw_params);
1099 cpcm = runtime->private_data;
1101 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1102 if (snd_BUG_ON(!sample_rate))
1105 mutex_lock(&chip->spos_mutex);
1107 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1108 mutex_unlock(&chip->spos_mutex);
1112 snd_BUG_ON(!cpcm->pcm_channel);
1113 if (!cpcm->pcm_channel) {
1114 mutex_unlock(&chip->spos_mutex);
1119 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1120 mutex_unlock(&chip->spos_mutex);
1124 dev_dbg(chip->card->dev,
1125 "period_size (%d), periods (%d) buffer_size(%d)\n",
1126 period_size, params_periods(hw_params),
1127 params_buffer_bytes(hw_params));
1130 if (params_periods(hw_params) == CS46XX_FRAGS) {
1131 if (runtime->dma_area != cpcm->hw_buf.area)
1132 snd_pcm_lib_free_pages(substream);
1133 runtime->dma_area = cpcm->hw_buf.area;
1134 runtime->dma_addr = cpcm->hw_buf.addr;
1135 runtime->dma_bytes = cpcm->hw_buf.bytes;
1138 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1139 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1140 substream->ops = &snd_cs46xx_playback_ops;
1141 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1142 substream->ops = &snd_cs46xx_playback_rear_ops;
1143 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1144 substream->ops = &snd_cs46xx_playback_clfe_ops;
1145 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1146 substream->ops = &snd_cs46xx_playback_iec958_ops;
1151 substream->ops = &snd_cs46xx_playback_ops;
1155 if (runtime->dma_area == cpcm->hw_buf.area) {
1156 runtime->dma_area = NULL;
1157 runtime->dma_addr = 0;
1158 runtime->dma_bytes = 0;
1160 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1161 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1162 mutex_unlock(&chip->spos_mutex);
1167 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1168 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1169 substream->ops = &snd_cs46xx_playback_indirect_ops;
1170 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1171 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1172 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1173 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1174 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1175 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1180 substream->ops = &snd_cs46xx_playback_indirect_ops;
1185 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1186 mutex_unlock(&chip->spos_mutex);
1192 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1194 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1195 struct snd_pcm_runtime *runtime = substream->runtime;
1196 struct snd_cs46xx_pcm *cpcm;
1198 cpcm = runtime->private_data;
1200 /* if play_back open fails, then this function
1201 is called and cpcm can actually be NULL here */
1202 if (!cpcm) return -ENXIO;
1204 if (runtime->dma_area != cpcm->hw_buf.area)
1205 snd_pcm_lib_free_pages(substream);
1207 runtime->dma_area = NULL;
1208 runtime->dma_addr = 0;
1209 runtime->dma_bytes = 0;
1214 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1218 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1219 struct snd_pcm_runtime *runtime = substream->runtime;
1220 struct snd_cs46xx_pcm *cpcm;
1222 cpcm = runtime->private_data;
1224 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1225 if (snd_BUG_ON(!cpcm->pcm_channel))
1228 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1229 pfie &= ~0x0000f03f;
1232 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1233 pfie &= ~0x0000f03f;
1237 /* if to convert from stereo to mono */
1238 if (runtime->channels == 1) {
1242 /* if to convert from 8 bit to 16 bit */
1243 if (snd_pcm_format_width(runtime->format) == 8) {
1247 /* if to convert to unsigned */
1248 if (snd_pcm_format_unsigned(runtime->format))
1251 /* Never convert byte order when sample stream is 8 bit */
1252 if (snd_pcm_format_width(runtime->format) != 8) {
1253 /* convert from big endian to little endian */
1254 if (snd_pcm_format_big_endian(runtime->format))
1258 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1259 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1260 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1262 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1264 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1266 tmp |= (4 << cpcm->shift) - 1;
1267 /* playback transaction count register */
1268 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1270 /* playback format && interrupt enable */
1271 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1273 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1274 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1276 tmp |= (4 << cpcm->shift) - 1;
1277 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1278 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1279 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1285 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1286 struct snd_pcm_hw_params *hw_params)
1288 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1289 struct snd_pcm_runtime *runtime = substream->runtime;
1292 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1293 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1295 if (runtime->periods == CS46XX_FRAGS) {
1296 if (runtime->dma_area != chip->capt.hw_buf.area)
1297 snd_pcm_lib_free_pages(substream);
1298 runtime->dma_area = chip->capt.hw_buf.area;
1299 runtime->dma_addr = chip->capt.hw_buf.addr;
1300 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1301 substream->ops = &snd_cs46xx_capture_ops;
1303 if (runtime->dma_area == chip->capt.hw_buf.area) {
1304 runtime->dma_area = NULL;
1305 runtime->dma_addr = 0;
1306 runtime->dma_bytes = 0;
1308 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1310 substream->ops = &snd_cs46xx_capture_indirect_ops;
1316 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1318 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1319 struct snd_pcm_runtime *runtime = substream->runtime;
1321 if (runtime->dma_area != chip->capt.hw_buf.area)
1322 snd_pcm_lib_free_pages(substream);
1323 runtime->dma_area = NULL;
1324 runtime->dma_addr = 0;
1325 runtime->dma_bytes = 0;
1330 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1332 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1333 struct snd_pcm_runtime *runtime = substream->runtime;
1335 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1336 chip->capt.shift = 2;
1337 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1338 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1339 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1340 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1345 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1347 struct snd_cs46xx *chip = dev_id;
1349 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1350 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1353 struct snd_cs46xx_pcm *cpcm = NULL;
1357 * Read the Interrupt Status Register to clear the interrupt
1359 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1360 if ((status1 & 0x7fffffff) == 0) {
1361 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1365 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1366 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1368 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1370 if ( status1 & (1 << i) ) {
1371 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1372 if (chip->capt.substream)
1373 snd_pcm_period_elapsed(chip->capt.substream);
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1384 if ( status2 & (1 << (i - 16))) {
1385 if (ins->pcm_channels[i].active &&
1386 ins->pcm_channels[i].private_data &&
1387 !ins->pcm_channels[i].unlinked) {
1388 cpcm = ins->pcm_channels[i].private_data;
1389 snd_pcm_period_elapsed(cpcm->substream);
1397 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1398 if (chip->playback_pcm->substream)
1399 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1401 if ((status1 & HISR_VC1) && chip->pcm) {
1402 if (chip->capt.substream)
1403 snd_pcm_period_elapsed(chip->capt.substream);
1407 if ((status1 & HISR_MIDI) && chip->rmidi) {
1410 spin_lock(&chip->reg_lock);
1411 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1412 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1413 if ((chip->midcr & MIDCR_RIE) == 0)
1415 snd_rawmidi_receive(chip->midi_input, &c, 1);
1417 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1418 if ((chip->midcr & MIDCR_TIE) == 0)
1420 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1421 chip->midcr &= ~MIDCR_TIE;
1422 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1425 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1427 spin_unlock(&chip->reg_lock);
1430 * EOI to the PCI part....reenables interrupts
1432 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1437 static const struct snd_pcm_hardware snd_cs46xx_playback =
1439 .info = (SNDRV_PCM_INFO_MMAP |
1440 SNDRV_PCM_INFO_INTERLEAVED |
1441 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1442 /*SNDRV_PCM_INFO_RESUME*/),
1443 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1444 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1445 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1446 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1451 .buffer_bytes_max = (256 * 1024),
1452 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1453 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1454 .periods_min = CS46XX_FRAGS,
1455 .periods_max = 1024,
1459 static const struct snd_pcm_hardware snd_cs46xx_capture =
1461 .info = (SNDRV_PCM_INFO_MMAP |
1462 SNDRV_PCM_INFO_INTERLEAVED |
1463 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1464 /*SNDRV_PCM_INFO_RESUME*/),
1465 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1466 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1471 .buffer_bytes_max = (256 * 1024),
1472 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1473 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1474 .periods_min = CS46XX_FRAGS,
1475 .periods_max = 1024,
1479 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1481 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1483 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1484 .count = ARRAY_SIZE(period_sizes),
1485 .list = period_sizes,
1491 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1493 kfree(runtime->private_data);
1496 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1498 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1499 struct snd_cs46xx_pcm * cpcm;
1500 struct snd_pcm_runtime *runtime = substream->runtime;
1502 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1505 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1506 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1511 runtime->hw = snd_cs46xx_playback;
1512 runtime->private_data = cpcm;
1513 runtime->private_free = snd_cs46xx_pcm_free_substream;
1515 cpcm->substream = substream;
1516 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1517 mutex_lock(&chip->spos_mutex);
1518 cpcm->pcm_channel = NULL;
1519 cpcm->pcm_channel_id = pcm_channel_id;
1522 snd_pcm_hw_constraint_list(runtime, 0,
1523 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1524 &hw_constraints_period_sizes);
1526 mutex_unlock(&chip->spos_mutex);
1528 chip->playback_pcm = cpcm; /* HACK */
1531 if (chip->accept_valid)
1532 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1533 chip->active_ctrl(chip, 1);
1538 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1540 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1541 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1544 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1545 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1547 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1548 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1551 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1553 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1554 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1557 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1559 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1561 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1563 mutex_lock(&chip->spos_mutex);
1564 cs46xx_iec958_pre_open (chip);
1565 mutex_unlock(&chip->spos_mutex);
1567 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1570 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1572 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1575 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1577 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1579 err = snd_cs46xx_playback_close(substream);
1581 mutex_lock(&chip->spos_mutex);
1582 cs46xx_iec958_post_close (chip);
1583 mutex_unlock(&chip->spos_mutex);
1589 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1591 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1593 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1594 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1596 chip->capt.substream = substream;
1597 substream->runtime->hw = snd_cs46xx_capture;
1599 if (chip->accept_valid)
1600 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1602 chip->active_ctrl(chip, 1);
1604 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1605 snd_pcm_hw_constraint_list(substream->runtime, 0,
1606 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1607 &hw_constraints_period_sizes);
1612 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1614 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1615 struct snd_pcm_runtime *runtime = substream->runtime;
1616 struct snd_cs46xx_pcm * cpcm;
1618 cpcm = runtime->private_data;
1620 /* when playback_open fails, then cpcm can be NULL */
1621 if (!cpcm) return -ENXIO;
1623 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1624 mutex_lock(&chip->spos_mutex);
1625 if (cpcm->pcm_channel) {
1626 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1627 cpcm->pcm_channel = NULL;
1629 mutex_unlock(&chip->spos_mutex);
1631 chip->playback_pcm = NULL;
1634 cpcm->substream = NULL;
1635 snd_dma_free_pages(&cpcm->hw_buf);
1636 chip->active_ctrl(chip, -1);
1641 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1643 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1645 chip->capt.substream = NULL;
1646 snd_dma_free_pages(&chip->capt.hw_buf);
1647 chip->active_ctrl(chip, -1);
1652 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1653 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1654 .open = snd_cs46xx_playback_open_rear,
1655 .close = snd_cs46xx_playback_close,
1656 .ioctl = snd_pcm_lib_ioctl,
1657 .hw_params = snd_cs46xx_playback_hw_params,
1658 .hw_free = snd_cs46xx_playback_hw_free,
1659 .prepare = snd_cs46xx_playback_prepare,
1660 .trigger = snd_cs46xx_playback_trigger,
1661 .pointer = snd_cs46xx_playback_direct_pointer,
1664 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1665 .open = snd_cs46xx_playback_open_rear,
1666 .close = snd_cs46xx_playback_close,
1667 .ioctl = snd_pcm_lib_ioctl,
1668 .hw_params = snd_cs46xx_playback_hw_params,
1669 .hw_free = snd_cs46xx_playback_hw_free,
1670 .prepare = snd_cs46xx_playback_prepare,
1671 .trigger = snd_cs46xx_playback_trigger,
1672 .pointer = snd_cs46xx_playback_indirect_pointer,
1673 .ack = snd_cs46xx_playback_transfer,
1676 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1677 .open = snd_cs46xx_playback_open_clfe,
1678 .close = snd_cs46xx_playback_close,
1679 .ioctl = snd_pcm_lib_ioctl,
1680 .hw_params = snd_cs46xx_playback_hw_params,
1681 .hw_free = snd_cs46xx_playback_hw_free,
1682 .prepare = snd_cs46xx_playback_prepare,
1683 .trigger = snd_cs46xx_playback_trigger,
1684 .pointer = snd_cs46xx_playback_direct_pointer,
1687 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1688 .open = snd_cs46xx_playback_open_clfe,
1689 .close = snd_cs46xx_playback_close,
1690 .ioctl = snd_pcm_lib_ioctl,
1691 .hw_params = snd_cs46xx_playback_hw_params,
1692 .hw_free = snd_cs46xx_playback_hw_free,
1693 .prepare = snd_cs46xx_playback_prepare,
1694 .trigger = snd_cs46xx_playback_trigger,
1695 .pointer = snd_cs46xx_playback_indirect_pointer,
1696 .ack = snd_cs46xx_playback_transfer,
1699 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1700 .open = snd_cs46xx_playback_open_iec958,
1701 .close = snd_cs46xx_playback_close_iec958,
1702 .ioctl = snd_pcm_lib_ioctl,
1703 .hw_params = snd_cs46xx_playback_hw_params,
1704 .hw_free = snd_cs46xx_playback_hw_free,
1705 .prepare = snd_cs46xx_playback_prepare,
1706 .trigger = snd_cs46xx_playback_trigger,
1707 .pointer = snd_cs46xx_playback_direct_pointer,
1710 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1711 .open = snd_cs46xx_playback_open_iec958,
1712 .close = snd_cs46xx_playback_close_iec958,
1713 .ioctl = snd_pcm_lib_ioctl,
1714 .hw_params = snd_cs46xx_playback_hw_params,
1715 .hw_free = snd_cs46xx_playback_hw_free,
1716 .prepare = snd_cs46xx_playback_prepare,
1717 .trigger = snd_cs46xx_playback_trigger,
1718 .pointer = snd_cs46xx_playback_indirect_pointer,
1719 .ack = snd_cs46xx_playback_transfer,
1724 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1725 .open = snd_cs46xx_playback_open,
1726 .close = snd_cs46xx_playback_close,
1727 .ioctl = snd_pcm_lib_ioctl,
1728 .hw_params = snd_cs46xx_playback_hw_params,
1729 .hw_free = snd_cs46xx_playback_hw_free,
1730 .prepare = snd_cs46xx_playback_prepare,
1731 .trigger = snd_cs46xx_playback_trigger,
1732 .pointer = snd_cs46xx_playback_direct_pointer,
1735 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1736 .open = snd_cs46xx_playback_open,
1737 .close = snd_cs46xx_playback_close,
1738 .ioctl = snd_pcm_lib_ioctl,
1739 .hw_params = snd_cs46xx_playback_hw_params,
1740 .hw_free = snd_cs46xx_playback_hw_free,
1741 .prepare = snd_cs46xx_playback_prepare,
1742 .trigger = snd_cs46xx_playback_trigger,
1743 .pointer = snd_cs46xx_playback_indirect_pointer,
1744 .ack = snd_cs46xx_playback_transfer,
1747 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1748 .open = snd_cs46xx_capture_open,
1749 .close = snd_cs46xx_capture_close,
1750 .ioctl = snd_pcm_lib_ioctl,
1751 .hw_params = snd_cs46xx_capture_hw_params,
1752 .hw_free = snd_cs46xx_capture_hw_free,
1753 .prepare = snd_cs46xx_capture_prepare,
1754 .trigger = snd_cs46xx_capture_trigger,
1755 .pointer = snd_cs46xx_capture_direct_pointer,
1758 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1759 .open = snd_cs46xx_capture_open,
1760 .close = snd_cs46xx_capture_close,
1761 .ioctl = snd_pcm_lib_ioctl,
1762 .hw_params = snd_cs46xx_capture_hw_params,
1763 .hw_free = snd_cs46xx_capture_hw_free,
1764 .prepare = snd_cs46xx_capture_prepare,
1765 .trigger = snd_cs46xx_capture_trigger,
1766 .pointer = snd_cs46xx_capture_indirect_pointer,
1767 .ack = snd_cs46xx_capture_transfer,
1770 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1771 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1773 #define MAX_PLAYBACK_CHANNELS 1
1776 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1778 struct snd_pcm *pcm;
1781 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1784 pcm->private_data = chip;
1786 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1787 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1790 pcm->info_flags = 0;
1791 strcpy(pcm->name, "CS46xx");
1794 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1795 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1801 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1802 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1804 struct snd_pcm *pcm;
1807 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1810 pcm->private_data = chip;
1812 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1815 pcm->info_flags = 0;
1816 strcpy(pcm->name, "CS46xx - Rear");
1817 chip->pcm_rear = pcm;
1819 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1820 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1825 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1827 struct snd_pcm *pcm;
1830 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1833 pcm->private_data = chip;
1835 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1838 pcm->info_flags = 0;
1839 strcpy(pcm->name, "CS46xx - Center LFE");
1840 chip->pcm_center_lfe = pcm;
1842 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1843 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1848 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1850 struct snd_pcm *pcm;
1853 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1856 pcm->private_data = chip;
1858 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1861 pcm->info_flags = 0;
1862 strcpy(pcm->name, "CS46xx - IEC958");
1863 chip->pcm_iec958 = pcm;
1865 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1866 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1875 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1877 struct snd_cs46xx *chip = bus->private_data;
1879 chip->ac97_bus = NULL;
1882 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1884 struct snd_cs46xx *chip = ac97->private_data;
1886 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1887 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1890 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1891 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1892 chip->eapd_switch = NULL;
1895 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1898 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1899 struct snd_ctl_elem_info *uinfo)
1901 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1903 uinfo->value.integer.min = 0;
1904 uinfo->value.integer.max = 0x7fff;
1908 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1910 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1911 int reg = kcontrol->private_value;
1912 unsigned int val = snd_cs46xx_peek(chip, reg);
1913 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1914 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1918 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1920 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1921 int reg = kcontrol->private_value;
1922 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1923 (0xffff - ucontrol->value.integer.value[1]));
1924 unsigned int old = snd_cs46xx_peek(chip, reg);
1925 int change = (old != val);
1928 snd_cs46xx_poke(chip, reg, val);
1934 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1936 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1938 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1940 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1941 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1946 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1948 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1951 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1952 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1953 cs46xx_dsp_set_dac_volume(chip,
1954 ucontrol->value.integer.value[0],
1955 ucontrol->value.integer.value[1]);
1963 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1965 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1967 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1968 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1972 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1974 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1977 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1978 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1979 cs46xx_dsp_set_iec958_volume (chip,
1980 ucontrol->value.integer.value[0],
1981 ucontrol->value.integer.value[1]);
1989 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1991 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1992 struct snd_ctl_elem_value *ucontrol)
1994 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1995 int reg = kcontrol->private_value;
1997 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1998 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2000 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
2005 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
2006 struct snd_ctl_elem_value *ucontrol)
2008 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2011 switch (kcontrol->private_value) {
2012 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2013 mutex_lock(&chip->spos_mutex);
2014 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2015 if (ucontrol->value.integer.value[0] && !change)
2016 cs46xx_dsp_enable_spdif_out(chip);
2017 else if (change && !ucontrol->value.integer.value[0])
2018 cs46xx_dsp_disable_spdif_out(chip);
2020 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2021 mutex_unlock(&chip->spos_mutex);
2023 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2024 change = chip->dsp_spos_instance->spdif_status_in;
2025 if (ucontrol->value.integer.value[0] && !change) {
2026 cs46xx_dsp_enable_spdif_in(chip);
2027 /* restore volume */
2029 else if (change && !ucontrol->value.integer.value[0])
2030 cs46xx_dsp_disable_spdif_in(chip);
2032 res = (change != chip->dsp_spos_instance->spdif_status_in);
2036 snd_BUG(); /* should never happen ... */
2042 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2043 struct snd_ctl_elem_value *ucontrol)
2045 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2046 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2048 if (ins->adc_input != NULL)
2049 ucontrol->value.integer.value[0] = 1;
2051 ucontrol->value.integer.value[0] = 0;
2056 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2057 struct snd_ctl_elem_value *ucontrol)
2059 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2060 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2063 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2064 cs46xx_dsp_enable_adc_capture(chip);
2066 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2067 cs46xx_dsp_disable_adc_capture(chip);
2073 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2074 struct snd_ctl_elem_value *ucontrol)
2076 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2077 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2079 if (ins->pcm_input != NULL)
2080 ucontrol->value.integer.value[0] = 1;
2082 ucontrol->value.integer.value[0] = 0;
2088 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2089 struct snd_ctl_elem_value *ucontrol)
2091 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2092 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2095 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2096 cs46xx_dsp_enable_pcm_capture(chip);
2098 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2099 cs46xx_dsp_disable_pcm_capture(chip);
2106 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2107 struct snd_ctl_elem_value *ucontrol)
2109 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2111 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2113 if (val1 & EGPIODR_GPOE0)
2114 ucontrol->value.integer.value[0] = 1;
2116 ucontrol->value.integer.value[0] = 0;
2122 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2124 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2125 struct snd_ctl_elem_value *ucontrol)
2127 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2128 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2129 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2131 if (ucontrol->value.integer.value[0]) {
2132 /* optical is default */
2133 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2134 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2135 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2136 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2139 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2140 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2143 /* checking diff from the EGPIO direction register
2145 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2149 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2151 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2156 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2157 struct snd_ctl_elem_value *ucontrol)
2159 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2160 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2162 mutex_lock(&chip->spos_mutex);
2163 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2164 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2165 ucontrol->value.iec958.status[2] = 0;
2166 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2167 mutex_unlock(&chip->spos_mutex);
2172 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2173 struct snd_ctl_elem_value *ucontrol)
2175 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2176 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2180 mutex_lock(&chip->spos_mutex);
2181 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2182 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2183 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2184 /* left and right validity bit */
2185 (1 << 13) | (1 << 12);
2188 change = (unsigned int)ins->spdif_csuv_default != val;
2189 ins->spdif_csuv_default = val;
2191 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2192 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2194 mutex_unlock(&chip->spos_mutex);
2199 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2200 struct snd_ctl_elem_value *ucontrol)
2202 ucontrol->value.iec958.status[0] = 0xff;
2203 ucontrol->value.iec958.status[1] = 0xff;
2204 ucontrol->value.iec958.status[2] = 0x00;
2205 ucontrol->value.iec958.status[3] = 0xff;
2209 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2210 struct snd_ctl_elem_value *ucontrol)
2212 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2213 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2215 mutex_lock(&chip->spos_mutex);
2216 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2217 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2218 ucontrol->value.iec958.status[2] = 0;
2219 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2220 mutex_unlock(&chip->spos_mutex);
2225 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2226 struct snd_ctl_elem_value *ucontrol)
2228 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2229 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2233 mutex_lock(&chip->spos_mutex);
2234 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2235 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2236 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2237 /* left and right validity bit */
2238 (1 << 13) | (1 << 12);
2241 change = ins->spdif_csuv_stream != val;
2242 ins->spdif_csuv_stream = val;
2244 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2245 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2247 mutex_unlock(&chip->spos_mutex);
2252 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2255 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2258 .name = "DAC Volume",
2259 .info = snd_cs46xx_vol_info,
2260 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2261 .get = snd_cs46xx_vol_get,
2262 .put = snd_cs46xx_vol_put,
2263 .private_value = BA1_PVOL,
2265 .get = snd_cs46xx_vol_dac_get,
2266 .put = snd_cs46xx_vol_dac_put,
2271 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2272 .name = "ADC Volume",
2273 .info = snd_cs46xx_vol_info,
2274 .get = snd_cs46xx_vol_get,
2275 .put = snd_cs46xx_vol_put,
2276 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2277 .private_value = BA1_CVOL,
2279 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2282 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = "ADC Capture Switch",
2286 .info = snd_mixer_boolean_info,
2287 .get = snd_cs46xx_adc_capture_get,
2288 .put = snd_cs46xx_adc_capture_put
2291 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2292 .name = "DAC Capture Switch",
2293 .info = snd_mixer_boolean_info,
2294 .get = snd_cs46xx_pcm_capture_get,
2295 .put = snd_cs46xx_pcm_capture_put
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2300 .info = snd_mixer_boolean_info,
2301 .get = snd_cs46xx_iec958_get,
2302 .put = snd_cs46xx_iec958_put,
2303 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2307 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2308 .info = snd_mixer_boolean_info,
2309 .get = snd_cs46xx_iec958_get,
2310 .put = snd_cs46xx_iec958_put,
2311 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2314 /* Input IEC958 volume does not work for the moment. (Benny) */
2316 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2317 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2318 .info = snd_cs46xx_vol_info,
2319 .get = snd_cs46xx_vol_iec958_get,
2320 .put = snd_cs46xx_vol_iec958_put,
2321 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2325 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2326 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2327 .info = snd_cs46xx_spdif_info,
2328 .get = snd_cs46xx_spdif_default_get,
2329 .put = snd_cs46xx_spdif_default_put,
2332 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2333 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2334 .info = snd_cs46xx_spdif_info,
2335 .get = snd_cs46xx_spdif_mask_get,
2336 .access = SNDRV_CTL_ELEM_ACCESS_READ
2339 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2340 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2341 .info = snd_cs46xx_spdif_info,
2342 .get = snd_cs46xx_spdif_stream_get,
2343 .put = snd_cs46xx_spdif_stream_put
2349 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2350 /* set primary cs4294 codec into Extended Audio Mode */
2351 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2352 struct snd_ctl_elem_value *ucontrol)
2354 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2356 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2357 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2361 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2362 struct snd_ctl_elem_value *ucontrol)
2364 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2365 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2366 AC97_CSR_ACMODE, 0x200,
2367 ucontrol->value.integer.value[0] ? 0 : 0x200);
2370 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2371 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2372 .name = "Duplicate Front",
2373 .info = snd_mixer_boolean_info,
2374 .get = snd_cs46xx_front_dup_get,
2375 .put = snd_cs46xx_front_dup_put,
2379 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2380 /* Only available on the Hercules Game Theater XP soundcard */
2381 static struct snd_kcontrol_new snd_hercules_controls[] = {
2383 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2384 .name = "Optical/Coaxial SPDIF Input Switch",
2385 .info = snd_mixer_boolean_info,
2386 .get = snd_herc_spdif_select_get,
2387 .put = snd_herc_spdif_select_put,
2392 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2394 unsigned long end_time;
2397 /* reset to defaults */
2398 snd_ac97_write(ac97, AC97_RESET, 0);
2400 /* set the desired CODEC mode */
2401 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2402 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2403 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2404 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2405 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2406 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2408 snd_BUG(); /* should never happen ... */
2413 /* it's necessary to wait awhile until registers are accessible after RESET */
2414 /* because the PCM or MASTER volume registers can be modified, */
2415 /* the REC_GAIN register is used for tests */
2416 end_time = jiffies + HZ;
2418 unsigned short ext_mid;
2420 /* use preliminary reads to settle the communication */
2421 snd_ac97_read(ac97, AC97_RESET);
2422 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2423 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2425 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2426 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2429 /* test if we can write to the record gain volume register */
2430 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2431 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2435 } while (time_after_eq(end_time, jiffies));
2437 dev_err(ac97->bus->card->dev,
2438 "CS46xx secondary codec doesn't respond!\n");
2442 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2445 struct snd_ac97_template ac97;
2447 memset(&ac97, 0, sizeof(ac97));
2448 ac97.private_data = chip;
2449 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2451 if (chip->amplifier_ctrl == amp_voyetra)
2452 ac97.scaps = AC97_SCAP_INV_EAPD;
2454 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2455 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2457 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2458 dev_dbg(chip->card->dev,
2459 "secondary codec not present\n");
2464 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2465 for (idx = 0; idx < 100; ++idx) {
2466 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2467 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2472 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2476 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2478 struct snd_card *card = chip->card;
2479 struct snd_ctl_elem_id id;
2482 static struct snd_ac97_bus_ops ops = {
2483 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2484 .reset = snd_cs46xx_codec_reset,
2486 .write = snd_cs46xx_ac97_write,
2487 .read = snd_cs46xx_ac97_read,
2490 /* detect primary codec */
2491 chip->nr_ac97_codecs = 0;
2492 dev_dbg(chip->card->dev, "detecting primary codec\n");
2493 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2495 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2497 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2499 chip->nr_ac97_codecs = 1;
2501 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2502 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2503 /* try detect a secondary codec */
2504 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2505 chip->nr_ac97_codecs = 2;
2506 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2508 /* add cs4630 mixer controls */
2509 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2510 struct snd_kcontrol *kctl;
2511 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2512 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2513 kctl->id.device = spdif_device;
2514 if ((err = snd_ctl_add(card, kctl)) < 0)
2518 /* get EAPD mixer switch (for voyetra hack) */
2519 memset(&id, 0, sizeof(id));
2520 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2521 strcpy(id.name, "External Amplifier");
2522 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2524 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2525 if (chip->nr_ac97_codecs == 1) {
2526 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2527 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2528 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2531 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2532 AC97_CSR_ACMODE, 0x200);
2535 /* do soundcard specific mixer setup */
2536 if (chip->mixer_init) {
2537 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2538 chip->mixer_init(chip);
2542 /* turn on amplifier */
2543 chip->amplifier_ctrl(chip, 1);
2552 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2554 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2556 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2559 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2561 struct snd_cs46xx *chip = substream->rmidi->private_data;
2563 chip->active_ctrl(chip, 1);
2564 spin_lock_irq(&chip->reg_lock);
2565 chip->uartm |= CS46XX_MODE_INPUT;
2566 chip->midcr |= MIDCR_RXE;
2567 chip->midi_input = substream;
2568 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2569 snd_cs46xx_midi_reset(chip);
2571 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2573 spin_unlock_irq(&chip->reg_lock);
2577 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2579 struct snd_cs46xx *chip = substream->rmidi->private_data;
2581 spin_lock_irq(&chip->reg_lock);
2582 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2583 chip->midi_input = NULL;
2584 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2585 snd_cs46xx_midi_reset(chip);
2587 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2589 chip->uartm &= ~CS46XX_MODE_INPUT;
2590 spin_unlock_irq(&chip->reg_lock);
2591 chip->active_ctrl(chip, -1);
2595 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2597 struct snd_cs46xx *chip = substream->rmidi->private_data;
2599 chip->active_ctrl(chip, 1);
2601 spin_lock_irq(&chip->reg_lock);
2602 chip->uartm |= CS46XX_MODE_OUTPUT;
2603 chip->midcr |= MIDCR_TXE;
2604 chip->midi_output = substream;
2605 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2606 snd_cs46xx_midi_reset(chip);
2608 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2610 spin_unlock_irq(&chip->reg_lock);
2614 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2616 struct snd_cs46xx *chip = substream->rmidi->private_data;
2618 spin_lock_irq(&chip->reg_lock);
2619 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2620 chip->midi_output = NULL;
2621 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2622 snd_cs46xx_midi_reset(chip);
2624 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2626 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2627 spin_unlock_irq(&chip->reg_lock);
2628 chip->active_ctrl(chip, -1);
2632 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2634 unsigned long flags;
2635 struct snd_cs46xx *chip = substream->rmidi->private_data;
2637 spin_lock_irqsave(&chip->reg_lock, flags);
2639 if ((chip->midcr & MIDCR_RIE) == 0) {
2640 chip->midcr |= MIDCR_RIE;
2641 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2644 if (chip->midcr & MIDCR_RIE) {
2645 chip->midcr &= ~MIDCR_RIE;
2646 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2649 spin_unlock_irqrestore(&chip->reg_lock, flags);
2652 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2654 unsigned long flags;
2655 struct snd_cs46xx *chip = substream->rmidi->private_data;
2658 spin_lock_irqsave(&chip->reg_lock, flags);
2660 if ((chip->midcr & MIDCR_TIE) == 0) {
2661 chip->midcr |= MIDCR_TIE;
2662 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2663 while ((chip->midcr & MIDCR_TIE) &&
2664 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2665 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2666 chip->midcr &= ~MIDCR_TIE;
2668 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2671 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2674 if (chip->midcr & MIDCR_TIE) {
2675 chip->midcr &= ~MIDCR_TIE;
2676 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2679 spin_unlock_irqrestore(&chip->reg_lock, flags);
2682 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2684 .open = snd_cs46xx_midi_output_open,
2685 .close = snd_cs46xx_midi_output_close,
2686 .trigger = snd_cs46xx_midi_output_trigger,
2689 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2691 .open = snd_cs46xx_midi_input_open,
2692 .close = snd_cs46xx_midi_input_close,
2693 .trigger = snd_cs46xx_midi_input_trigger,
2696 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2698 struct snd_rawmidi *rmidi;
2701 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2703 strcpy(rmidi->name, "CS46XX");
2704 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2705 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2706 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2707 rmidi->private_data = chip;
2708 chip->rmidi = rmidi;
2714 * gameport interface
2717 #if IS_REACHABLE(CONFIG_GAMEPORT)
2719 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2721 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2723 if (snd_BUG_ON(!chip))
2725 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2728 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2730 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2732 if (snd_BUG_ON(!chip))
2734 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2737 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2739 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2740 unsigned js1, js2, jst;
2742 if (snd_BUG_ON(!chip))
2745 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2746 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2747 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2749 *buttons = (~jst >> 4) & 0x0F;
2751 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2752 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2753 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2754 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2756 for(jst=0;jst<4;++jst)
2757 if(axes[jst]==0xFFFF) axes[jst] = -1;
2761 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2764 case GAMEPORT_MODE_COOKED:
2766 case GAMEPORT_MODE_RAW:
2774 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2776 struct gameport *gp;
2778 chip->gameport = gp = gameport_allocate_port();
2780 dev_err(chip->card->dev,
2781 "cannot allocate memory for gameport\n");
2785 gameport_set_name(gp, "CS46xx Gameport");
2786 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2787 gameport_set_dev_parent(gp, &chip->pci->dev);
2788 gameport_set_port_data(gp, chip);
2790 gp->open = snd_cs46xx_gameport_open;
2791 gp->read = snd_cs46xx_gameport_read;
2792 gp->trigger = snd_cs46xx_gameport_trigger;
2793 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2795 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2796 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2798 gameport_register_port(gp);
2803 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2805 if (chip->gameport) {
2806 gameport_unregister_port(chip->gameport);
2807 chip->gameport = NULL;
2811 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2812 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2813 #endif /* CONFIG_GAMEPORT */
2815 #ifdef CONFIG_SND_PROC_FS
2820 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2821 void *file_private_data,
2822 struct file *file, char __user *buf,
2823 size_t count, loff_t pos)
2825 struct snd_cs46xx_region *region = entry->private_data;
2827 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2832 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2833 .read = snd_cs46xx_io_read,
2836 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2838 struct snd_info_entry *entry;
2841 for (idx = 0; idx < 5; idx++) {
2842 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2843 if (! snd_card_proc_new(card, region->name, &entry)) {
2844 entry->content = SNDRV_INFO_CONTENT_DATA;
2845 entry->private_data = chip;
2846 entry->c.ops = &snd_cs46xx_proc_io_ops;
2847 entry->size = region->size;
2848 entry->mode = S_IFREG | 0400;
2851 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2852 cs46xx_dsp_proc_init(card, chip);
2857 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2859 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2860 cs46xx_dsp_proc_done(chip);
2864 #else /* !CONFIG_SND_PROC_FS */
2865 #define snd_cs46xx_proc_init(card, chip)
2866 #define snd_cs46xx_proc_done(chip)
2872 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2876 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2879 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2881 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2884 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2887 * Stop playback DMA.
2889 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2890 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2895 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2896 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2899 * Reset the processor.
2901 snd_cs46xx_reset(chip);
2903 snd_cs46xx_proc_stop(chip);
2906 * Power down the PLL.
2908 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2911 * Turn off the Processor by turning off the software clock enable flag in
2912 * the clock control register.
2914 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2915 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2919 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2923 if (snd_BUG_ON(!chip))
2926 if (chip->active_ctrl)
2927 chip->active_ctrl(chip, 1);
2929 snd_cs46xx_remove_gameport(chip);
2931 if (chip->amplifier_ctrl)
2932 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2934 snd_cs46xx_proc_done(chip);
2936 if (chip->region.idx[0].resource)
2937 snd_cs46xx_hw_stop(chip);
2940 free_irq(chip->irq, chip);
2942 if (chip->active_ctrl)
2943 chip->active_ctrl(chip, -chip->amplifier);
2945 for (idx = 0; idx < 5; idx++) {
2946 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2948 iounmap(region->remap_addr);
2949 release_and_free_resource(region->resource);
2952 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2953 if (chip->dsp_spos_instance) {
2954 cs46xx_dsp_spos_destroy(chip);
2955 chip->dsp_spos_instance = NULL;
2957 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2958 free_module_desc(chip->modules[idx]);
2963 #ifdef CONFIG_PM_SLEEP
2964 kfree(chip->saved_regs);
2967 pci_disable_device(chip->pci);
2972 static int snd_cs46xx_dev_free(struct snd_device *device)
2974 struct snd_cs46xx *chip = device->device_data;
2975 return snd_cs46xx_free(chip);
2981 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2986 * First, blast the clock control register to zero so that the PLL starts
2987 * out in a known state, and blast the master serial port control register
2988 * to zero so that the serial ports also start out in a known state.
2990 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2991 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2994 * If we are in AC97 mode, then we must set the part to a host controlled
2995 * AC-link. Otherwise, we won't be able to bring up the link.
2997 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2998 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2999 SERACC_TWO_CODECS); /* 2.00 dual codecs */
3000 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3002 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3006 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3007 * spec) and then drive it high. This is done for non AC97 modes since
3008 * there might be logic external to the CS461x that uses the ARST# line
3011 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3012 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3013 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3016 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3017 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3018 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3022 * The first thing we do here is to enable sync generation. As soon
3023 * as we start receiving bit clock, we'll start producing the SYNC
3026 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3027 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3028 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3032 * Now wait for a short while to allow the AC97 part to start
3033 * generating bit clock (so we don't try to start the PLL without an
3039 * Set the serial port timing configuration, so that
3040 * the clock control circuit gets its clock from the correct place.
3042 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3045 * Write the selected clock control setup to the hardware. Do not turn on
3046 * SWCE yet (if requested), so that the devices clocked by the output of
3047 * PLL are not clocked until the PLL is stable.
3049 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3050 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3051 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3056 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3059 * Wait until the PLL has stabilized.
3064 * Turn on clocking of the core so that we can setup the serial ports.
3066 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3069 * Enable FIFO Host Bypass
3071 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3074 * Fill the serial port FIFOs with silence.
3076 snd_cs46xx_clear_serial_FIFOs(chip);
3079 * Set the serial port FIFO pointer to the first sample in the FIFO.
3081 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3084 * Write the serial port configuration to the part. The master
3085 * enable bit is not set until all other values have been written.
3087 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3088 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3089 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3092 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3093 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3094 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3095 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3096 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3097 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3104 * Wait for the codec ready signal from the AC97 codec.
3107 while (timeout-- > 0) {
3109 * Read the AC97 status register to see if we've seen a CODEC READY
3110 * signal from the AC97 codec.
3112 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3118 dev_err(chip->card->dev,
3119 "create - never read codec ready from AC'97\n");
3120 dev_err(chip->card->dev,
3121 "it is not probably bug, try to use CS4236 driver\n");
3124 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3127 for (count = 0; count < 150; count++) {
3128 /* First, we want to wait for a short time. */
3131 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3136 * Make sure CODEC is READY.
3138 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3139 dev_dbg(chip->card->dev,
3140 "never read card ready from secondary AC'97\n");
3145 * Assert the vaid frame signal so that we can start sending commands
3146 * to the AC97 codec.
3148 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3149 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3150 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3155 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3156 * the codec is pumping ADC data across the AC-link.
3159 while (timeout-- > 0) {
3161 * Read the input slot valid register and see if input slots 3 and
3164 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3169 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3170 dev_err(chip->card->dev,
3171 "create - never read ISV3 & ISV4 from AC'97\n");
3174 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3175 Reloading the driver may help, if there's other soundcards
3176 with the same problem I would like to know. (Benny) */
3178 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3179 dev_err(chip->card->dev,
3180 "Try reloading the ALSA driver, if you find something\n");
3181 dev_err(chip->card->dev,
3182 "broken or not working on your soundcard upon\n");
3183 dev_err(chip->card->dev,
3184 "this message please report to alsa-devel@alsa-project.org\n");
3191 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3192 * commense the transfer of digital audio data to the AC97 codec.
3195 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3199 * Power down the DAC and ADC. We will power them up (if) when we need
3202 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3205 * Turn off the Processor by turning off the software clock enable flag in
3206 * the clock control register.
3208 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3209 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3215 * start and load DSP
3218 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3222 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3224 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3226 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3228 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3231 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3234 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3237 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3243 * Reset the processor.
3245 snd_cs46xx_reset(chip);
3247 * Download the image to the processor.
3249 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3250 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3251 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3253 dev_err(chip->card->dev, "firmware load error [%s]\n",
3257 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3259 dev_err(chip->card->dev, "image download error [%s]\n",
3265 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3268 err = load_firmware(chip);
3273 err = snd_cs46xx_download_image(chip);
3275 dev_err(chip->card->dev, "image download error\n");
3280 * Stop playback DMA.
3282 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3283 chip->play_ctl = tmp & 0xffff0000;
3284 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3290 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3291 chip->capt.ctl = tmp & 0x0000ffff;
3292 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3296 snd_cs46xx_set_play_sample_rate(chip, 8000);
3297 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3299 snd_cs46xx_proc_start(chip);
3301 cs46xx_enable_stream_irqs(chip);
3303 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3304 /* set the attenuation to 0dB */
3305 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3306 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3314 * AMP control - null AMP
3317 static void amp_none(struct snd_cs46xx *chip, int change)
3321 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3322 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3325 u32 idx, valid_slots,tmp,powerdown = 0;
3326 u16 modem_power,pin_config,logic_type;
3328 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3331 * See if the devices are powered down. If so, we must power them up first
3332 * or they will not respond.
3334 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3336 if (!(tmp & CLKCR1_SWCE)) {
3337 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3342 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3345 if(chip->nr_ac97_codecs != 2) {
3346 dev_err(chip->card->dev,
3347 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3351 modem_power = snd_cs46xx_codec_read (chip,
3352 AC97_EXTENDED_MSTATUS,
3353 CS46XX_SECONDARY_CODEC_INDEX);
3354 modem_power &=0xFEFF;
3356 snd_cs46xx_codec_write(chip,
3357 AC97_EXTENDED_MSTATUS, modem_power,
3358 CS46XX_SECONDARY_CODEC_INDEX);
3361 * Set GPIO pin's 7 and 8 so that they are configured for output.
3363 pin_config = snd_cs46xx_codec_read (chip,
3365 CS46XX_SECONDARY_CODEC_INDEX);
3368 snd_cs46xx_codec_write(chip,
3369 AC97_GPIO_CFG, pin_config,
3370 CS46XX_SECONDARY_CODEC_INDEX);
3373 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3376 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3377 CS46XX_SECONDARY_CODEC_INDEX);
3380 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3381 CS46XX_SECONDARY_CODEC_INDEX);
3383 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3384 valid_slots |= 0x200;
3385 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3387 if ( cs46xx_wait_for_fifo(chip,1) ) {
3388 dev_dbg(chip->card->dev, "FIFO is busy\n");
3394 * Fill slots 12 with the correct value for the GPIO pins.
3396 for(idx = 0x90; idx <= 0x9F; idx++) {
3398 * Initialize the fifo so that bits 7 and 8 are on.
3400 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3401 * the left. 0x1800 corresponds to bits 7 and 8.
3403 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3406 * Wait for command to complete
3408 if ( cs46xx_wait_for_fifo(chip,200) ) {
3409 dev_dbg(chip->card->dev,
3410 "failed waiting for FIFO at addr (%02X)\n",
3417 * Write the serial port FIFO index.
3419 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3422 * Tell the serial port to load the new value into the FIFO location.
3424 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3427 /* wait for last command to complete */
3428 cs46xx_wait_for_fifo(chip,200);
3431 * Now, if we powered up the devices, then power them back down again.
3432 * This is kinda ugly, but should never happen.
3435 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3445 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3447 /* Manage the EAPD bit on the Crystal 4297
3448 and the Analog AD1885 */
3450 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3451 int old = chip->amplifier;
3455 chip->amplifier += change;
3456 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3457 CS46XX_PRIMARY_CODEC_INDEX);
3459 if (chip->amplifier) {
3460 /* Turn the EAPD amp on */
3463 /* Turn the EAPD amp off */
3467 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3468 CS46XX_PRIMARY_CODEC_INDEX);
3469 if (chip->eapd_switch)
3470 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3471 &chip->eapd_switch->id);
3474 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3475 if (chip->amplifier && !old) {
3476 voyetra_setup_eapd_slot(chip);
3481 static void hercules_init(struct snd_cs46xx *chip)
3483 /* default: AMP off, and SPDIF input optical */
3484 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3485 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3490 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3492 static void amp_hercules(struct snd_cs46xx *chip, int change)
3494 int old = chip->amplifier;
3495 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3496 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3498 chip->amplifier += change;
3499 if (chip->amplifier && !old) {
3500 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3502 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3503 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3504 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3505 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3506 } else if (old && !chip->amplifier) {
3507 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3508 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3509 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3513 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3515 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3517 /* Enable SPDIF out */
3518 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3519 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3522 static void hercules_mixer_init (struct snd_cs46xx *chip)
3524 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3527 struct snd_card *card = chip->card;
3530 /* set EGPIO to default */
3531 hercules_init(chip);
3533 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3535 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3536 if (chip->in_suspend)
3539 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3540 struct snd_kcontrol *kctl;
3542 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3543 if ((err = snd_ctl_add(card, kctl)) < 0) {
3545 "failed to initialize Hercules mixer (%d)\n",
3559 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3561 chip->amplifier += change;
3563 if (chip->amplifier) {
3564 /* Switch the GPIO pins 7 and 8 to open drain */
3565 snd_cs46xx_codec_write(chip, 0x4C,
3566 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3567 snd_cs46xx_codec_write(chip, 0x4E,
3568 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3569 /* Now wake the AMP (this might be backwards) */
3570 snd_cs46xx_codec_write(chip, 0x54,
3571 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3573 snd_cs46xx_codec_write(chip, 0x54,
3574 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3581 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3582 * whenever we need to beat on the chip.
3584 * The original idea and code for this hack comes from David Kaiser at
3585 * Linuxcare. Perhaps one day Crystal will document their chips well
3586 * enough to make them useful.
3589 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3593 if (!chip->acpi_port)
3596 chip->amplifier += change;
3598 /* Read ACPI port */
3599 nval = control = inw(chip->acpi_port + 0x10);
3601 /* Flip CLKRUN off while running */
3602 if (! chip->amplifier)
3606 if (nval != control)
3607 outw(nval, chip->acpi_port + 0x10);
3612 * detect intel piix4
3614 static void clkrun_init(struct snd_cs46xx *chip)
3616 struct pci_dev *pdev;
3619 chip->acpi_port = 0;
3621 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3622 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3624 return; /* Not a thinkpad thats for sure */
3626 /* Find the control port */
3627 pci_read_config_byte(pdev, 0x41, &pp);
3628 chip->acpi_port = pp << 8;
3642 void (*init)(struct snd_cs46xx *);
3643 void (*amp)(struct snd_cs46xx *, int);
3644 void (*active)(struct snd_cs46xx *, int);
3645 void (*mixer_init)(struct snd_cs46xx *);
3648 static struct cs_card_type cards[] = {
3652 .name = "Genius Soundmaker 128 value",
3653 /* nothing special */
3660 .mixer_init = voyetra_mixer_init,
3665 .name = "Mitac MI6020/21",
3668 /* Hercules Game Theatre XP */
3670 .vendor = 0x14af, /* Guillemot Corporation */
3672 .name = "Hercules Game Theatre XP",
3673 .amp = amp_hercules,
3674 .mixer_init = hercules_mixer_init,
3679 .name = "Hercules Game Theatre XP",
3680 .amp = amp_hercules,
3681 .mixer_init = hercules_mixer_init,
3686 .name = "Hercules Game Theatre XP",
3687 .amp = amp_hercules,
3688 .mixer_init = hercules_mixer_init,
3694 .name = "Hercules Game Theatre XP",
3695 .amp = amp_hercules,
3696 .mixer_init = hercules_mixer_init,
3701 .name = "Hercules Game Theatre XP",
3702 .amp = amp_hercules,
3703 .mixer_init = hercules_mixer_init,
3708 .name = "Hercules Game Theatre XP",
3709 .amp = amp_hercules,
3710 .mixer_init = hercules_mixer_init,
3712 /* Herculess Fortissimo */
3716 .name = "Hercules Gamesurround Fortissimo II",
3721 .name = "Hercules Gamesurround Fortissimo III 7.1",
3727 .name = "Terratec DMX XFire 1024",
3732 .name = "Terratec SiXPack 5.1",
3734 /* Not sure if the 570 needs the clkrun hack */
3736 .vendor = PCI_VENDOR_ID_IBM,
3738 .name = "Thinkpad 570",
3739 .init = clkrun_init,
3740 .active = clkrun_hack,
3743 .vendor = PCI_VENDOR_ID_IBM,
3745 .name = "Thinkpad 600X/A20/T20",
3746 .init = clkrun_init,
3747 .active = clkrun_hack,
3750 .vendor = PCI_VENDOR_ID_IBM,
3752 .name = "Thinkpad 600E (unsupported)",
3761 #ifdef CONFIG_PM_SLEEP
3762 static unsigned int saved_regs[] = {
3770 static int snd_cs46xx_suspend(struct device *dev)
3772 struct snd_card *card = dev_get_drvdata(dev);
3773 struct snd_cs46xx *chip = card->private_data;
3776 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3777 chip->in_suspend = 1;
3778 snd_pcm_suspend_all(chip->pcm);
3779 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3780 snd_pcm_suspend_all(chip->pcm_rear);
3781 snd_pcm_suspend_all(chip->pcm_center_lfe);
3782 snd_pcm_suspend_all(chip->pcm_iec958);
3784 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3785 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3787 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3788 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3790 /* save some registers */
3791 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3792 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3794 amp_saved = chip->amplifier;
3796 chip->amplifier_ctrl(chip, -chip->amplifier);
3797 snd_cs46xx_hw_stop(chip);
3798 /* disable CLKRUN */
3799 chip->active_ctrl(chip, -chip->amplifier);
3800 chip->amplifier = amp_saved; /* restore the status */
3804 static int snd_cs46xx_resume(struct device *dev)
3806 struct snd_card *card = dev_get_drvdata(dev);
3807 struct snd_cs46xx *chip = card->private_data;
3809 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3814 amp_saved = chip->amplifier;
3815 chip->amplifier = 0;
3816 chip->active_ctrl(chip, 1); /* force to on */
3818 snd_cs46xx_chip_init(chip);
3820 snd_cs46xx_reset(chip);
3821 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3822 cs46xx_dsp_resume(chip);
3823 /* restore some registers */
3824 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3825 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3827 snd_cs46xx_download_image(chip);
3831 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3832 chip->ac97_general_purpose);
3833 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3834 chip->ac97_powerdown);
3836 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3837 chip->ac97_powerdown);
3841 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3842 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3847 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3848 chip->capt.ctl = tmp & 0x0000ffff;
3849 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3853 /* reset playback/capture */
3854 snd_cs46xx_set_play_sample_rate(chip, 8000);
3855 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3856 snd_cs46xx_proc_start(chip);
3858 cs46xx_enable_stream_irqs(chip);
3861 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3863 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3864 chip->amplifier = amp_saved;
3865 chip->in_suspend = 0;
3866 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3870 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3871 #endif /* CONFIG_PM_SLEEP */
3877 int snd_cs46xx_create(struct snd_card *card,
3878 struct pci_dev *pci,
3879 int external_amp, int thinkpad,
3880 struct snd_cs46xx **rchip)
3882 struct snd_cs46xx *chip;
3884 struct snd_cs46xx_region *region;
3885 struct cs_card_type *cp;
3886 u16 ss_card, ss_vendor;
3887 static struct snd_device_ops ops = {
3888 .dev_free = snd_cs46xx_dev_free,
3893 /* enable PCI device */
3894 if ((err = pci_enable_device(pci)) < 0)
3897 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3899 pci_disable_device(pci);
3902 spin_lock_init(&chip->reg_lock);
3903 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3904 mutex_init(&chip->spos_mutex);
3909 chip->ba0_addr = pci_resource_start(pci, 0);
3910 chip->ba1_addr = pci_resource_start(pci, 1);
3911 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3912 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3913 dev_err(chip->card->dev,
3914 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3915 chip->ba0_addr, chip->ba1_addr);
3916 snd_cs46xx_free(chip);
3920 region = &chip->region.name.ba0;
3921 strcpy(region->name, "CS46xx_BA0");
3922 region->base = chip->ba0_addr;
3923 region->size = CS46XX_BA0_SIZE;
3925 region = &chip->region.name.data0;
3926 strcpy(region->name, "CS46xx_BA1_data0");
3927 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3928 region->size = CS46XX_BA1_DATA0_SIZE;
3930 region = &chip->region.name.data1;
3931 strcpy(region->name, "CS46xx_BA1_data1");
3932 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3933 region->size = CS46XX_BA1_DATA1_SIZE;
3935 region = &chip->region.name.pmem;
3936 strcpy(region->name, "CS46xx_BA1_pmem");
3937 region->base = chip->ba1_addr + BA1_SP_PMEM;
3938 region->size = CS46XX_BA1_PRG_SIZE;
3940 region = &chip->region.name.reg;
3941 strcpy(region->name, "CS46xx_BA1_reg");
3942 region->base = chip->ba1_addr + BA1_SP_REG;
3943 region->size = CS46XX_BA1_REG_SIZE;
3945 /* set up amp and clkrun hack */
3946 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3947 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3949 for (cp = &cards[0]; cp->name; cp++) {
3950 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3951 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3954 chip->amplifier_ctrl = cp->amp;
3955 chip->active_ctrl = cp->active;
3956 chip->mixer_init = cp->mixer_init;
3965 dev_info(chip->card->dev,
3966 "Crystal EAPD support forced on.\n");
3967 chip->amplifier_ctrl = amp_voyetra;
3971 dev_info(chip->card->dev,
3972 "Activating CLKRUN hack for Thinkpad.\n");
3973 chip->active_ctrl = clkrun_hack;
3977 if (chip->amplifier_ctrl == NULL)
3978 chip->amplifier_ctrl = amp_none;
3979 if (chip->active_ctrl == NULL)
3980 chip->active_ctrl = amp_none;
3982 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3984 pci_set_master(pci);
3986 for (idx = 0; idx < 5; idx++) {
3987 region = &chip->region.idx[idx];
3988 if ((region->resource = request_mem_region(region->base, region->size,
3989 region->name)) == NULL) {
3990 dev_err(chip->card->dev,
3991 "unable to request memory region 0x%lx-0x%lx\n",
3992 region->base, region->base + region->size - 1);
3993 snd_cs46xx_free(chip);
3996 region->remap_addr = ioremap_nocache(region->base, region->size);
3997 if (region->remap_addr == NULL) {
3998 dev_err(chip->card->dev,
3999 "%s ioremap problem\n", region->name);
4000 snd_cs46xx_free(chip);
4005 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
4006 KBUILD_MODNAME, chip)) {
4007 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
4008 snd_cs46xx_free(chip);
4011 chip->irq = pci->irq;
4013 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4014 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4015 if (chip->dsp_spos_instance == NULL) {
4016 snd_cs46xx_free(chip);
4021 err = snd_cs46xx_chip_init(chip);
4023 snd_cs46xx_free(chip);
4027 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4028 snd_cs46xx_free(chip);
4032 snd_cs46xx_proc_init(card, chip);
4034 #ifdef CONFIG_PM_SLEEP
4035 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4036 sizeof(*chip->saved_regs),
4038 if (!chip->saved_regs) {
4039 snd_cs46xx_free(chip);
4044 chip->active_ctrl(chip, -1); /* disable CLKRUN */