1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
6 * Routines for control of Cirrus Logic CS461x chips
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
55 #include "cs46xx_lib.h"
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short result,tmp;
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
86 chip->active_ctrl(chip, 1);
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 * Wait for the read to occur.
143 for (count = 0; count < 1000; count++) {
145 * First, we want to wait for a short time.
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
163 * Wait for the valid status bit to go active.
165 for (count = 0; count < 100; count++) {
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
204 struct snd_cs46xx *chip = ac97->private_data;
206 int codec_index = ac97->num;
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
229 chip->active_ctrl(chip, 1);
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
265 for (count = 0; count < 4000; count++) {
267 * First, we want to wait for a short time.
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
282 chip->active_ctrl(chip, -1);
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
306 unsigned long offset,
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
315 dst = chip->region.idx[bank+1].remap_addr + offset;
318 /* writel already converts 32-bit value to right endianess */
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
332 const __le32 *_src = src;
335 *_dst++ = le32_to_cpu(*_src++);
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
347 static void free_module_desc(struct dsp_module_desc *module)
351 kfree(module->module_name);
352 kfree(module->symbol_table.symbols);
353 if (module->segments) {
355 for (i = 0; i < module->nsegments; i++)
356 kfree(module->segments[i].data);
357 kfree(module->segments);
362 /* firmware binary format:
366 * char symbol_name[DSP_MAX_SYMBOL_NAME];
368 * } symbols[nsymbols];
375 * } segments[nsegments];
378 static int load_firmware(struct snd_cs46xx *chip,
379 struct dsp_module_desc **module_ret,
383 unsigned int nums, fwlen, fwsize;
385 struct dsp_module_desc *module = NULL;
386 const struct firmware *fw;
389 sprintf(fw_path, "cs46xx/%s", fw_name);
390 err = reject_firmware(&fw, fw_path, &chip->pci->dev);
393 fwsize = fw->size / 4;
400 module = kzalloc(sizeof(*module), GFP_KERNEL);
403 module->module_name = kstrdup(fw_name, GFP_KERNEL);
404 if (!module->module_name)
408 fwdat = (const __le32 *)fw->data;
409 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
412 module->symbol_table.symbols =
413 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
414 if (!module->symbol_table.symbols)
416 for (i = 0; i < nums; i++) {
417 struct dsp_symbol_entry *entry =
418 &module->symbol_table.symbols[i];
419 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
421 entry->address = le32_to_cpu(fwdat[fwlen++]);
422 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
423 fwlen += DSP_MAX_SYMBOL_NAME / 4;
424 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
433 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
434 if (!module->segments)
436 for (i = 0; i < nums; i++) {
437 struct dsp_segment_desc *entry = &module->segments[i];
438 if (fwlen + 3 > fwsize)
440 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
441 entry->offset = le32_to_cpu(fwdat[fwlen++]);
442 entry->size = le32_to_cpu(fwdat[fwlen++]);
443 if (fwlen + entry->size > fwsize)
445 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
448 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
449 fwlen += entry->size;
452 *module_ret = module;
453 release_firmware(fw);
459 free_module_desc(module);
460 release_firmware(fw);
464 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
465 unsigned long offset,
469 unsigned int bank = offset >> 16;
470 offset = offset & 0xffff;
472 if (snd_BUG_ON((offset & 3) || (len & 3)))
474 dst = chip->region.idx[bank+1].remap_addr + offset;
477 /* writel already converts 32-bit value to right endianess */
485 #else /* old DSP image */
491 } memory[BA1_MEMORY_COUNT];
492 u32 map[BA1_DWORD_SIZE];
497 static int load_firmware(struct snd_cs46xx *chip)
499 const struct firmware *fw;
502 err = reject_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
505 if (fw->size != sizeof(*chip->ba1)) {
510 chip->ba1 = vmalloc(sizeof(*chip->ba1));
516 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
520 for (i = 0; i < BA1_MEMORY_COUNT; i++)
521 size += chip->ba1->memory[i].size;
522 if (size > BA1_DWORD_SIZE * 4)
526 release_firmware(fw);
530 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
533 unsigned int offset = 0;
534 struct ba1_struct *ba1 = chip->ba1;
536 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
537 err = snd_cs46xx_download(chip,
539 ba1->memory[idx].offset,
540 ba1->memory[idx].size);
543 offset += ba1->memory[idx].size >> 2;
547 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
553 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
558 * Write the reset bit of the SP control register.
560 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
563 * Write the control register.
565 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
568 * Clear the trap registers.
570 for (idx = 0; idx < 8; idx++) {
571 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
572 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
574 snd_cs46xx_poke(chip, BA1_DREG, 0);
577 * Set the frame timer to reflect the number of cycles per frame.
579 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
582 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
586 * Make sure the previous FIFO write operation has completed.
588 for(i = 0; i < 50; i++){
589 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
591 if( !(status & SERBST_WBSY) )
594 mdelay(retry_timeout);
597 if(status & SERBST_WBSY) {
598 dev_err(chip->card->dev,
599 "failure waiting for FIFO command to complete\n");
606 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
608 int idx, powerdown = 0;
612 * See if the devices are powered down. If so, we must power them up first
613 * or they will not respond.
615 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
616 if (!(tmp & CLKCR1_SWCE)) {
617 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 * We want to clear out the serial port FIFOs so we don't end up playing
623 * whatever random garbage happens to be in them. We fill the sample FIFOS
624 * with zero (silence).
626 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
629 * Fill all 256 sample FIFO locations.
631 for (idx = 0; idx < 0xFF; idx++) {
633 * Make sure the previous FIFO write operation has completed.
635 if (cs46xx_wait_for_fifo(chip,1)) {
636 dev_dbg(chip->card->dev,
637 "failed waiting for FIFO at addr (%02X)\n",
641 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646 * Write the serial port FIFO index.
648 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
650 * Tell the serial port to load the new value into the FIFO location.
652 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
655 * Now, if we powered up the devices, then power them back down again.
656 * This is kinda ugly, but should never happen.
659 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
662 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
667 * Set the frame timer to reflect the number of cycles per frame.
669 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
671 * Turn on the run, run at frame, and DMA enable bits in the local copy of
672 * the SP control register.
674 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
676 * Wait until the run at frame bit resets itself in the SP control
679 for (cnt = 0; cnt < 25; cnt++) {
681 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
685 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
686 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
689 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
692 * Turn off the run, run at frame, and DMA enable bits in the local copy of
693 * the SP control register.
695 snd_cs46xx_poke(chip, BA1_SPCR, 0);
699 * Sample rate routines
702 #define GOF_PER_SEC 200
704 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
707 unsigned int tmp1, tmp2;
708 unsigned int phiIncr;
709 unsigned int correctionPerGOF, correctionPerSec;
712 * Compute the values used to drive the actual sample rate conversion.
713 * The following formulas are being computed, using inline assembly
714 * since we need to use 64 bit arithmetic to compute the values:
716 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
717 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
719 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
720 * GOF_PER_SEC * correctionPerGOF
724 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
725 * correctionPerGOF:correctionPerSec =
726 * dividend:remainder(ulOther / GOF_PER_SEC)
729 phiIncr = tmp1 / 48000;
730 tmp1 -= phiIncr * 48000;
735 tmp1 -= tmp2 * 48000;
736 correctionPerGOF = tmp1 / GOF_PER_SEC;
737 tmp1 -= correctionPerGOF * GOF_PER_SEC;
738 correctionPerSec = tmp1;
741 * Fill in the SampleRateConverter control block.
743 spin_lock_irqsave(&chip->reg_lock, flags);
744 snd_cs46xx_poke(chip, BA1_PSRC,
745 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
746 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
747 spin_unlock_irqrestore(&chip->reg_lock, flags);
750 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
753 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
754 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
755 unsigned int frameGroupLength, cnt;
758 * We can only decimate by up to a factor of 1/9th the hardware rate.
759 * Correct the value if an attempt is made to stray outside that limit.
761 if ((rate * 9) < 48000)
765 * We can not capture at a rate greater than the Input Rate (48000).
766 * Return an error if an attempt is made to stray outside that limit.
772 * Compute the values used to drive the actual sample rate conversion.
773 * The following formulas are being computed, using inline assembly
774 * since we need to use 64 bit arithmetic to compute the values:
776 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
777 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
778 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
780 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
781 * GOF_PER_SEC * correctionPerGOF
782 * initialDelay = ceil((24 * Fs,in) / Fs,out)
786 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
787 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
788 * correctionPerGOF:correctionPerSec =
789 * dividend:remainder(ulOther / GOF_PER_SEC)
790 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
794 coeffIncr = tmp1 / 48000;
795 tmp1 -= coeffIncr * 48000;
798 coeffIncr += tmp1 / 48000;
799 coeffIncr ^= 0xFFFFFFFF;
802 phiIncr = tmp1 / rate;
803 tmp1 -= phiIncr * rate;
809 correctionPerGOF = tmp1 / GOF_PER_SEC;
810 tmp1 -= correctionPerGOF * GOF_PER_SEC;
811 correctionPerSec = tmp1;
812 initialDelay = DIV_ROUND_UP(48000 * 24, rate);
815 * Fill in the VariDecimate control block.
817 spin_lock_irqsave(&chip->reg_lock, flags);
818 snd_cs46xx_poke(chip, BA1_CSRC,
819 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
820 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
821 snd_cs46xx_poke(chip, BA1_CD,
822 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
823 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
824 spin_unlock_irqrestore(&chip->reg_lock, flags);
827 * Figure out the frame group length for the write back task. Basically,
828 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
829 * the output sample rate.
831 frameGroupLength = 1;
832 for (cnt = 2; cnt <= 64; cnt *= 2) {
833 if (((rate / cnt) * cnt) != rate)
834 frameGroupLength *= 2;
836 if (((rate / 3) * 3) != rate) {
837 frameGroupLength *= 3;
839 for (cnt = 5; cnt <= 125; cnt *= 5) {
840 if (((rate / cnt) * cnt) != rate)
841 frameGroupLength *= 5;
845 * Fill in the WriteBack control block.
847 spin_lock_irqsave(&chip->reg_lock, flags);
848 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
849 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
850 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
851 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
852 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
853 spin_unlock_irqrestore(&chip->reg_lock, flags);
860 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
861 struct snd_pcm_indirect *rec, size_t bytes)
863 struct snd_pcm_runtime *runtime = substream->runtime;
864 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
865 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
868 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
870 struct snd_pcm_runtime *runtime = substream->runtime;
871 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
872 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
873 snd_cs46xx_pb_trans_copy);
876 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
877 struct snd_pcm_indirect *rec, size_t bytes)
879 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
880 struct snd_pcm_runtime *runtime = substream->runtime;
881 memcpy(runtime->dma_area + rec->sw_data,
882 chip->capt.hw_buf.area + rec->hw_data, bytes);
885 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
887 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
888 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
889 snd_cs46xx_cp_trans_copy);
892 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
894 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
896 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
898 if (snd_BUG_ON(!cpcm->pcm_channel))
901 #ifdef CONFIG_SND_CS46XX_NEW_DSP
902 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
904 ptr = snd_cs46xx_peek(chip, BA1_PBA);
906 ptr -= cpcm->hw_buf.addr;
907 return ptr >> cpcm->shift;
910 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
912 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
914 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
916 #ifdef CONFIG_SND_CS46XX_NEW_DSP
917 if (snd_BUG_ON(!cpcm->pcm_channel))
919 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
921 ptr = snd_cs46xx_peek(chip, BA1_PBA);
923 ptr -= cpcm->hw_buf.addr;
924 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
927 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
929 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
930 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
931 return ptr >> chip->capt.shift;
934 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
936 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
937 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
938 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
941 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
944 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
945 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
949 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
950 if (! cpcm->pcm_channel) {
955 case SNDRV_PCM_TRIGGER_START:
956 case SNDRV_PCM_TRIGGER_RESUME:
957 #ifdef CONFIG_SND_CS46XX_NEW_DSP
958 /* magic value to unmute PCM stream playback volume */
959 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
960 SCBVolumeCtrl) << 2, 0x80008000);
962 if (cpcm->pcm_channel->unlinked)
963 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
965 if (substream->runtime->periods != CS46XX_FRAGS)
966 snd_cs46xx_playback_transfer(substream);
968 spin_lock(&chip->reg_lock);
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
972 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
974 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
976 spin_unlock(&chip->reg_lock);
979 case SNDRV_PCM_TRIGGER_STOP:
980 case SNDRV_PCM_TRIGGER_SUSPEND:
981 #ifdef CONFIG_SND_CS46XX_NEW_DSP
982 /* magic mute channel */
983 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
984 SCBVolumeCtrl) << 2, 0xffffffff);
986 if (!cpcm->pcm_channel->unlinked)
987 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
989 spin_lock(&chip->reg_lock);
991 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
993 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
995 spin_unlock(&chip->reg_lock);
1006 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1009 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1013 spin_lock(&chip->reg_lock);
1015 case SNDRV_PCM_TRIGGER_START:
1016 case SNDRV_PCM_TRIGGER_RESUME:
1017 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1019 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1021 case SNDRV_PCM_TRIGGER_STOP:
1022 case SNDRV_PCM_TRIGGER_SUSPEND:
1023 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1025 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1031 spin_unlock(&chip->reg_lock);
1036 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1037 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1041 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1042 if ( cpcm->pcm_channel == NULL) {
1043 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1044 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1045 if (cpcm->pcm_channel == NULL) {
1046 dev_err(chip->card->dev,
1047 "failed to create virtual PCM channel\n");
1050 cpcm->pcm_channel->sample_rate = sample_rate;
1052 /* if sample rate is changed */
1053 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1054 int unlinked = cpcm->pcm_channel->unlinked;
1055 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1057 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1059 cpcm->pcm_channel_id);
1060 if (!cpcm->pcm_channel) {
1061 dev_err(chip->card->dev,
1062 "failed to re-create virtual PCM channel\n");
1066 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1067 cpcm->pcm_channel->sample_rate = sample_rate;
1075 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1076 struct snd_pcm_hw_params *hw_params)
1078 struct snd_pcm_runtime *runtime = substream->runtime;
1079 struct snd_cs46xx_pcm *cpcm;
1081 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1082 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1083 int sample_rate = params_rate(hw_params);
1084 int period_size = params_period_bytes(hw_params);
1086 cpcm = runtime->private_data;
1088 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1089 if (snd_BUG_ON(!sample_rate))
1092 mutex_lock(&chip->spos_mutex);
1094 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1095 mutex_unlock(&chip->spos_mutex);
1099 snd_BUG_ON(!cpcm->pcm_channel);
1100 if (!cpcm->pcm_channel) {
1101 mutex_unlock(&chip->spos_mutex);
1106 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1107 mutex_unlock(&chip->spos_mutex);
1111 dev_dbg(chip->card->dev,
1112 "period_size (%d), periods (%d) buffer_size(%d)\n",
1113 period_size, params_periods(hw_params),
1114 params_buffer_bytes(hw_params));
1117 if (params_periods(hw_params) == CS46XX_FRAGS) {
1118 if (runtime->dma_area != cpcm->hw_buf.area)
1119 snd_pcm_lib_free_pages(substream);
1120 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf);
1123 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1124 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1125 substream->ops = &snd_cs46xx_playback_ops;
1126 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1127 substream->ops = &snd_cs46xx_playback_rear_ops;
1128 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1129 substream->ops = &snd_cs46xx_playback_clfe_ops;
1130 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1131 substream->ops = &snd_cs46xx_playback_iec958_ops;
1136 substream->ops = &snd_cs46xx_playback_ops;
1140 if (runtime->dma_area == cpcm->hw_buf.area)
1141 snd_pcm_set_runtime_buffer(substream, NULL);
1142 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1145 mutex_unlock(&chip->spos_mutex);
1150 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1151 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1152 substream->ops = &snd_cs46xx_playback_indirect_ops;
1153 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1154 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1155 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1156 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1157 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1158 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1163 substream->ops = &snd_cs46xx_playback_indirect_ops;
1168 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1169 mutex_unlock(&chip->spos_mutex);
1175 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1177 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1178 struct snd_pcm_runtime *runtime = substream->runtime;
1179 struct snd_cs46xx_pcm *cpcm;
1181 cpcm = runtime->private_data;
1183 /* if play_back open fails, then this function
1184 is called and cpcm can actually be NULL here */
1185 if (!cpcm) return -ENXIO;
1187 if (runtime->dma_area != cpcm->hw_buf.area)
1188 snd_pcm_lib_free_pages(substream);
1190 snd_pcm_set_runtime_buffer(substream, NULL);
1195 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1199 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1200 struct snd_pcm_runtime *runtime = substream->runtime;
1201 struct snd_cs46xx_pcm *cpcm;
1203 cpcm = runtime->private_data;
1205 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1206 if (snd_BUG_ON(!cpcm->pcm_channel))
1209 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1210 pfie &= ~0x0000f03f;
1213 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1214 pfie &= ~0x0000f03f;
1218 /* if to convert from stereo to mono */
1219 if (runtime->channels == 1) {
1223 /* if to convert from 8 bit to 16 bit */
1224 if (snd_pcm_format_width(runtime->format) == 8) {
1228 /* if to convert to unsigned */
1229 if (snd_pcm_format_unsigned(runtime->format))
1232 /* Never convert byte order when sample stream is 8 bit */
1233 if (snd_pcm_format_width(runtime->format) != 8) {
1234 /* convert from big endian to little endian */
1235 if (snd_pcm_format_big_endian(runtime->format))
1239 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1240 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1241 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1243 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1245 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1247 tmp |= (4 << cpcm->shift) - 1;
1248 /* playback transaction count register */
1249 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1251 /* playback format && interrupt enable */
1252 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1254 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1255 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1257 tmp |= (4 << cpcm->shift) - 1;
1258 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1259 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1260 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1266 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1267 struct snd_pcm_hw_params *hw_params)
1269 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1270 struct snd_pcm_runtime *runtime = substream->runtime;
1273 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1274 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1276 if (runtime->periods == CS46XX_FRAGS) {
1277 if (runtime->dma_area != chip->capt.hw_buf.area)
1278 snd_pcm_lib_free_pages(substream);
1279 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1280 substream->ops = &snd_cs46xx_capture_ops;
1282 if (runtime->dma_area == chip->capt.hw_buf.area)
1283 snd_pcm_set_runtime_buffer(substream, NULL);
1284 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1287 substream->ops = &snd_cs46xx_capture_indirect_ops;
1293 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1295 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1296 struct snd_pcm_runtime *runtime = substream->runtime;
1298 if (runtime->dma_area != chip->capt.hw_buf.area)
1299 snd_pcm_lib_free_pages(substream);
1300 snd_pcm_set_runtime_buffer(substream, NULL);
1305 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1307 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1308 struct snd_pcm_runtime *runtime = substream->runtime;
1310 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1311 chip->capt.shift = 2;
1312 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1313 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1314 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1315 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1320 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1322 struct snd_cs46xx *chip = dev_id;
1324 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1325 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1328 struct snd_cs46xx_pcm *cpcm = NULL;
1332 * Read the Interrupt Status Register to clear the interrupt
1334 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1335 if ((status1 & 0x7fffffff) == 0) {
1336 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1340 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1341 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1343 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1345 if ( status1 & (1 << i) ) {
1346 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1347 if (chip->capt.substream)
1348 snd_pcm_period_elapsed(chip->capt.substream);
1350 if (ins->pcm_channels[i].active &&
1351 ins->pcm_channels[i].private_data &&
1352 !ins->pcm_channels[i].unlinked) {
1353 cpcm = ins->pcm_channels[i].private_data;
1354 snd_pcm_period_elapsed(cpcm->substream);
1359 if ( status2 & (1 << (i - 16))) {
1360 if (ins->pcm_channels[i].active &&
1361 ins->pcm_channels[i].private_data &&
1362 !ins->pcm_channels[i].unlinked) {
1363 cpcm = ins->pcm_channels[i].private_data;
1364 snd_pcm_period_elapsed(cpcm->substream);
1372 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1373 if (chip->playback_pcm->substream)
1374 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1376 if ((status1 & HISR_VC1) && chip->pcm) {
1377 if (chip->capt.substream)
1378 snd_pcm_period_elapsed(chip->capt.substream);
1382 if ((status1 & HISR_MIDI) && chip->rmidi) {
1385 spin_lock(&chip->reg_lock);
1386 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1387 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1388 if ((chip->midcr & MIDCR_RIE) == 0)
1390 snd_rawmidi_receive(chip->midi_input, &c, 1);
1392 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1393 if ((chip->midcr & MIDCR_TIE) == 0)
1395 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1396 chip->midcr &= ~MIDCR_TIE;
1397 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1400 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1402 spin_unlock(&chip->reg_lock);
1405 * EOI to the PCI part....reenables interrupts
1407 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1412 static const struct snd_pcm_hardware snd_cs46xx_playback =
1414 .info = (SNDRV_PCM_INFO_MMAP |
1415 SNDRV_PCM_INFO_INTERLEAVED |
1416 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1417 /*SNDRV_PCM_INFO_RESUME*/ |
1418 SNDRV_PCM_INFO_SYNC_APPLPTR),
1419 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1420 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1421 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1422 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1427 .buffer_bytes_max = (256 * 1024),
1428 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1429 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1430 .periods_min = CS46XX_FRAGS,
1431 .periods_max = 1024,
1435 static const struct snd_pcm_hardware snd_cs46xx_capture =
1437 .info = (SNDRV_PCM_INFO_MMAP |
1438 SNDRV_PCM_INFO_INTERLEAVED |
1439 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1440 /*SNDRV_PCM_INFO_RESUME*/ |
1441 SNDRV_PCM_INFO_SYNC_APPLPTR),
1442 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1443 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1448 .buffer_bytes_max = (256 * 1024),
1449 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1450 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1451 .periods_min = CS46XX_FRAGS,
1452 .periods_max = 1024,
1456 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1458 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1460 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1461 .count = ARRAY_SIZE(period_sizes),
1462 .list = period_sizes,
1468 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1470 kfree(runtime->private_data);
1473 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1475 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1476 struct snd_cs46xx_pcm * cpcm;
1477 struct snd_pcm_runtime *runtime = substream->runtime;
1479 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1482 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1483 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1488 runtime->hw = snd_cs46xx_playback;
1489 runtime->private_data = cpcm;
1490 runtime->private_free = snd_cs46xx_pcm_free_substream;
1492 cpcm->substream = substream;
1493 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1494 mutex_lock(&chip->spos_mutex);
1495 cpcm->pcm_channel = NULL;
1496 cpcm->pcm_channel_id = pcm_channel_id;
1499 snd_pcm_hw_constraint_list(runtime, 0,
1500 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1501 &hw_constraints_period_sizes);
1503 mutex_unlock(&chip->spos_mutex);
1505 chip->playback_pcm = cpcm; /* HACK */
1508 if (chip->accept_valid)
1509 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1510 chip->active_ctrl(chip, 1);
1515 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1517 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1518 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1521 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1522 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1524 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1525 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1528 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1530 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1531 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1534 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1536 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1538 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1540 mutex_lock(&chip->spos_mutex);
1541 cs46xx_iec958_pre_open (chip);
1542 mutex_unlock(&chip->spos_mutex);
1544 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1547 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1549 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1552 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1554 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1556 err = snd_cs46xx_playback_close(substream);
1558 mutex_lock(&chip->spos_mutex);
1559 cs46xx_iec958_post_close (chip);
1560 mutex_unlock(&chip->spos_mutex);
1566 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1568 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1570 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1571 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1573 chip->capt.substream = substream;
1574 substream->runtime->hw = snd_cs46xx_capture;
1576 if (chip->accept_valid)
1577 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1579 chip->active_ctrl(chip, 1);
1581 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1582 snd_pcm_hw_constraint_list(substream->runtime, 0,
1583 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1584 &hw_constraints_period_sizes);
1589 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1591 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1592 struct snd_pcm_runtime *runtime = substream->runtime;
1593 struct snd_cs46xx_pcm * cpcm;
1595 cpcm = runtime->private_data;
1597 /* when playback_open fails, then cpcm can be NULL */
1598 if (!cpcm) return -ENXIO;
1600 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1601 mutex_lock(&chip->spos_mutex);
1602 if (cpcm->pcm_channel) {
1603 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1604 cpcm->pcm_channel = NULL;
1606 mutex_unlock(&chip->spos_mutex);
1608 chip->playback_pcm = NULL;
1611 cpcm->substream = NULL;
1612 snd_dma_free_pages(&cpcm->hw_buf);
1613 chip->active_ctrl(chip, -1);
1618 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1620 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1622 chip->capt.substream = NULL;
1623 snd_dma_free_pages(&chip->capt.hw_buf);
1624 chip->active_ctrl(chip, -1);
1629 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1630 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1631 .open = snd_cs46xx_playback_open_rear,
1632 .close = snd_cs46xx_playback_close,
1633 .hw_params = snd_cs46xx_playback_hw_params,
1634 .hw_free = snd_cs46xx_playback_hw_free,
1635 .prepare = snd_cs46xx_playback_prepare,
1636 .trigger = snd_cs46xx_playback_trigger,
1637 .pointer = snd_cs46xx_playback_direct_pointer,
1640 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1641 .open = snd_cs46xx_playback_open_rear,
1642 .close = snd_cs46xx_playback_close,
1643 .hw_params = snd_cs46xx_playback_hw_params,
1644 .hw_free = snd_cs46xx_playback_hw_free,
1645 .prepare = snd_cs46xx_playback_prepare,
1646 .trigger = snd_cs46xx_playback_trigger,
1647 .pointer = snd_cs46xx_playback_indirect_pointer,
1648 .ack = snd_cs46xx_playback_transfer,
1651 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1652 .open = snd_cs46xx_playback_open_clfe,
1653 .close = snd_cs46xx_playback_close,
1654 .hw_params = snd_cs46xx_playback_hw_params,
1655 .hw_free = snd_cs46xx_playback_hw_free,
1656 .prepare = snd_cs46xx_playback_prepare,
1657 .trigger = snd_cs46xx_playback_trigger,
1658 .pointer = snd_cs46xx_playback_direct_pointer,
1661 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1662 .open = snd_cs46xx_playback_open_clfe,
1663 .close = snd_cs46xx_playback_close,
1664 .hw_params = snd_cs46xx_playback_hw_params,
1665 .hw_free = snd_cs46xx_playback_hw_free,
1666 .prepare = snd_cs46xx_playback_prepare,
1667 .trigger = snd_cs46xx_playback_trigger,
1668 .pointer = snd_cs46xx_playback_indirect_pointer,
1669 .ack = snd_cs46xx_playback_transfer,
1672 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1673 .open = snd_cs46xx_playback_open_iec958,
1674 .close = snd_cs46xx_playback_close_iec958,
1675 .hw_params = snd_cs46xx_playback_hw_params,
1676 .hw_free = snd_cs46xx_playback_hw_free,
1677 .prepare = snd_cs46xx_playback_prepare,
1678 .trigger = snd_cs46xx_playback_trigger,
1679 .pointer = snd_cs46xx_playback_direct_pointer,
1682 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1683 .open = snd_cs46xx_playback_open_iec958,
1684 .close = snd_cs46xx_playback_close_iec958,
1685 .hw_params = snd_cs46xx_playback_hw_params,
1686 .hw_free = snd_cs46xx_playback_hw_free,
1687 .prepare = snd_cs46xx_playback_prepare,
1688 .trigger = snd_cs46xx_playback_trigger,
1689 .pointer = snd_cs46xx_playback_indirect_pointer,
1690 .ack = snd_cs46xx_playback_transfer,
1695 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1696 .open = snd_cs46xx_playback_open,
1697 .close = snd_cs46xx_playback_close,
1698 .hw_params = snd_cs46xx_playback_hw_params,
1699 .hw_free = snd_cs46xx_playback_hw_free,
1700 .prepare = snd_cs46xx_playback_prepare,
1701 .trigger = snd_cs46xx_playback_trigger,
1702 .pointer = snd_cs46xx_playback_direct_pointer,
1705 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1706 .open = snd_cs46xx_playback_open,
1707 .close = snd_cs46xx_playback_close,
1708 .hw_params = snd_cs46xx_playback_hw_params,
1709 .hw_free = snd_cs46xx_playback_hw_free,
1710 .prepare = snd_cs46xx_playback_prepare,
1711 .trigger = snd_cs46xx_playback_trigger,
1712 .pointer = snd_cs46xx_playback_indirect_pointer,
1713 .ack = snd_cs46xx_playback_transfer,
1716 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1717 .open = snd_cs46xx_capture_open,
1718 .close = snd_cs46xx_capture_close,
1719 .hw_params = snd_cs46xx_capture_hw_params,
1720 .hw_free = snd_cs46xx_capture_hw_free,
1721 .prepare = snd_cs46xx_capture_prepare,
1722 .trigger = snd_cs46xx_capture_trigger,
1723 .pointer = snd_cs46xx_capture_direct_pointer,
1726 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1727 .open = snd_cs46xx_capture_open,
1728 .close = snd_cs46xx_capture_close,
1729 .hw_params = snd_cs46xx_capture_hw_params,
1730 .hw_free = snd_cs46xx_capture_hw_free,
1731 .prepare = snd_cs46xx_capture_prepare,
1732 .trigger = snd_cs46xx_capture_trigger,
1733 .pointer = snd_cs46xx_capture_indirect_pointer,
1734 .ack = snd_cs46xx_capture_transfer,
1737 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1738 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1740 #define MAX_PLAYBACK_CHANNELS 1
1743 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1745 struct snd_pcm *pcm;
1748 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1752 pcm->private_data = chip;
1754 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1755 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1758 pcm->info_flags = 0;
1759 strcpy(pcm->name, "CS46xx");
1762 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1770 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1771 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1773 struct snd_pcm *pcm;
1776 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1780 pcm->private_data = chip;
1782 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1785 pcm->info_flags = 0;
1786 strcpy(pcm->name, "CS46xx - Rear");
1787 chip->pcm_rear = pcm;
1789 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1796 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1798 struct snd_pcm *pcm;
1801 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1805 pcm->private_data = chip;
1807 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1810 pcm->info_flags = 0;
1811 strcpy(pcm->name, "CS46xx - Center LFE");
1812 chip->pcm_center_lfe = pcm;
1814 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1821 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1823 struct snd_pcm *pcm;
1826 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1830 pcm->private_data = chip;
1832 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1835 pcm->info_flags = 0;
1836 strcpy(pcm->name, "CS46xx - IEC958");
1837 chip->pcm_iec958 = pcm;
1839 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1850 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1852 struct snd_cs46xx *chip = ac97->private_data;
1854 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1855 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1858 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1859 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1860 chip->eapd_switch = NULL;
1863 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1866 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1867 struct snd_ctl_elem_info *uinfo)
1869 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1871 uinfo->value.integer.min = 0;
1872 uinfo->value.integer.max = 0x7fff;
1876 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1878 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1879 int reg = kcontrol->private_value;
1880 unsigned int val = snd_cs46xx_peek(chip, reg);
1881 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1882 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1886 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1888 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1889 int reg = kcontrol->private_value;
1890 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1891 (0xffff - ucontrol->value.integer.value[1]));
1892 unsigned int old = snd_cs46xx_peek(chip, reg);
1893 int change = (old != val);
1896 snd_cs46xx_poke(chip, reg, val);
1902 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1904 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1908 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1909 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1914 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1916 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1919 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1920 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1921 cs46xx_dsp_set_dac_volume(chip,
1922 ucontrol->value.integer.value[0],
1923 ucontrol->value.integer.value[1]);
1931 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1933 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1935 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1936 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1940 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1942 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1945 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1946 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1947 cs46xx_dsp_set_iec958_volume (chip,
1948 ucontrol->value.integer.value[0],
1949 ucontrol->value.integer.value[1]);
1957 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1959 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_value *ucontrol)
1962 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1963 int reg = kcontrol->private_value;
1965 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1966 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1968 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1973 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1974 struct snd_ctl_elem_value *ucontrol)
1976 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1979 switch (kcontrol->private_value) {
1980 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1981 mutex_lock(&chip->spos_mutex);
1982 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1983 if (ucontrol->value.integer.value[0] && !change)
1984 cs46xx_dsp_enable_spdif_out(chip);
1985 else if (change && !ucontrol->value.integer.value[0])
1986 cs46xx_dsp_disable_spdif_out(chip);
1988 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1989 mutex_unlock(&chip->spos_mutex);
1991 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1992 change = chip->dsp_spos_instance->spdif_status_in;
1993 if (ucontrol->value.integer.value[0] && !change) {
1994 cs46xx_dsp_enable_spdif_in(chip);
1995 /* restore volume */
1997 else if (change && !ucontrol->value.integer.value[0])
1998 cs46xx_dsp_disable_spdif_in(chip);
2000 res = (change != chip->dsp_spos_instance->spdif_status_in);
2004 snd_BUG(); /* should never happen ... */
2010 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
2013 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2014 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2016 if (ins->adc_input != NULL)
2017 ucontrol->value.integer.value[0] = 1;
2019 ucontrol->value.integer.value[0] = 0;
2024 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2025 struct snd_ctl_elem_value *ucontrol)
2027 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2028 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2031 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2032 cs46xx_dsp_enable_adc_capture(chip);
2034 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2035 cs46xx_dsp_disable_adc_capture(chip);
2041 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2042 struct snd_ctl_elem_value *ucontrol)
2044 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2045 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2047 if (ins->pcm_input != NULL)
2048 ucontrol->value.integer.value[0] = 1;
2050 ucontrol->value.integer.value[0] = 0;
2056 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2057 struct snd_ctl_elem_value *ucontrol)
2059 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2060 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2063 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2064 cs46xx_dsp_enable_pcm_capture(chip);
2066 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2067 cs46xx_dsp_disable_pcm_capture(chip);
2074 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2075 struct snd_ctl_elem_value *ucontrol)
2077 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2079 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2081 if (val1 & EGPIODR_GPOE0)
2082 ucontrol->value.integer.value[0] = 1;
2084 ucontrol->value.integer.value[0] = 0;
2090 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2092 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2093 struct snd_ctl_elem_value *ucontrol)
2095 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2096 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2097 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2099 if (ucontrol->value.integer.value[0]) {
2100 /* optical is default */
2101 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2102 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2103 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2104 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2107 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2108 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2111 /* checking diff from the EGPIO direction register
2113 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2117 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2119 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2124 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2125 struct snd_ctl_elem_value *ucontrol)
2127 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2128 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2130 mutex_lock(&chip->spos_mutex);
2131 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2132 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2133 ucontrol->value.iec958.status[2] = 0;
2134 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2135 mutex_unlock(&chip->spos_mutex);
2140 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2141 struct snd_ctl_elem_value *ucontrol)
2143 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2144 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2148 mutex_lock(&chip->spos_mutex);
2149 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2150 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2151 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2152 /* left and right validity bit */
2153 (1 << 13) | (1 << 12);
2156 change = (unsigned int)ins->spdif_csuv_default != val;
2157 ins->spdif_csuv_default = val;
2159 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2160 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2162 mutex_unlock(&chip->spos_mutex);
2167 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2168 struct snd_ctl_elem_value *ucontrol)
2170 ucontrol->value.iec958.status[0] = 0xff;
2171 ucontrol->value.iec958.status[1] = 0xff;
2172 ucontrol->value.iec958.status[2] = 0x00;
2173 ucontrol->value.iec958.status[3] = 0xff;
2177 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2178 struct snd_ctl_elem_value *ucontrol)
2180 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2181 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2183 mutex_lock(&chip->spos_mutex);
2184 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2185 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2186 ucontrol->value.iec958.status[2] = 0;
2187 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2188 mutex_unlock(&chip->spos_mutex);
2193 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2194 struct snd_ctl_elem_value *ucontrol)
2196 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2197 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2201 mutex_lock(&chip->spos_mutex);
2202 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2203 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2204 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2205 /* left and right validity bit */
2206 (1 << 13) | (1 << 12);
2209 change = ins->spdif_csuv_stream != val;
2210 ins->spdif_csuv_stream = val;
2212 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2213 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2215 mutex_unlock(&chip->spos_mutex);
2220 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2223 static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2225 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2226 .name = "DAC Volume",
2227 .info = snd_cs46xx_vol_info,
2228 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2229 .get = snd_cs46xx_vol_get,
2230 .put = snd_cs46xx_vol_put,
2231 .private_value = BA1_PVOL,
2233 .get = snd_cs46xx_vol_dac_get,
2234 .put = snd_cs46xx_vol_dac_put,
2239 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2240 .name = "ADC Volume",
2241 .info = snd_cs46xx_vol_info,
2242 .get = snd_cs46xx_vol_get,
2243 .put = snd_cs46xx_vol_put,
2244 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2245 .private_value = BA1_CVOL,
2247 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2250 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2252 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2253 .name = "ADC Capture Switch",
2254 .info = snd_mixer_boolean_info,
2255 .get = snd_cs46xx_adc_capture_get,
2256 .put = snd_cs46xx_adc_capture_put
2259 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2260 .name = "DAC Capture Switch",
2261 .info = snd_mixer_boolean_info,
2262 .get = snd_cs46xx_pcm_capture_get,
2263 .put = snd_cs46xx_pcm_capture_put
2266 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2267 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2268 .info = snd_mixer_boolean_info,
2269 .get = snd_cs46xx_iec958_get,
2270 .put = snd_cs46xx_iec958_put,
2271 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2274 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2275 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2276 .info = snd_mixer_boolean_info,
2277 .get = snd_cs46xx_iec958_get,
2278 .put = snd_cs46xx_iec958_put,
2279 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2282 /* Input IEC958 volume does not work for the moment. (Benny) */
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2286 .info = snd_cs46xx_vol_info,
2287 .get = snd_cs46xx_vol_iec958_get,
2288 .put = snd_cs46xx_vol_iec958_put,
2289 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2293 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2294 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2295 .info = snd_cs46xx_spdif_info,
2296 .get = snd_cs46xx_spdif_default_get,
2297 .put = snd_cs46xx_spdif_default_put,
2300 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2301 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2302 .info = snd_cs46xx_spdif_info,
2303 .get = snd_cs46xx_spdif_mask_get,
2304 .access = SNDRV_CTL_ELEM_ACCESS_READ
2307 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2308 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2309 .info = snd_cs46xx_spdif_info,
2310 .get = snd_cs46xx_spdif_stream_get,
2311 .put = snd_cs46xx_spdif_stream_put
2317 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2318 /* set primary cs4294 codec into Extended Audio Mode */
2319 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2320 struct snd_ctl_elem_value *ucontrol)
2322 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2324 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2325 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2329 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2330 struct snd_ctl_elem_value *ucontrol)
2332 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2333 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2334 AC97_CSR_ACMODE, 0x200,
2335 ucontrol->value.integer.value[0] ? 0 : 0x200);
2338 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2339 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2340 .name = "Duplicate Front",
2341 .info = snd_mixer_boolean_info,
2342 .get = snd_cs46xx_front_dup_get,
2343 .put = snd_cs46xx_front_dup_put,
2347 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2348 /* Only available on the Hercules Game Theater XP soundcard */
2349 static const struct snd_kcontrol_new snd_hercules_controls[] = {
2351 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2352 .name = "Optical/Coaxial SPDIF Input Switch",
2353 .info = snd_mixer_boolean_info,
2354 .get = snd_herc_spdif_select_get,
2355 .put = snd_herc_spdif_select_put,
2360 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2362 unsigned long end_time;
2365 /* reset to defaults */
2366 snd_ac97_write(ac97, AC97_RESET, 0);
2368 /* set the desired CODEC mode */
2369 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2370 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2371 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2372 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2373 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2374 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2376 snd_BUG(); /* should never happen ... */
2381 /* it's necessary to wait awhile until registers are accessible after RESET */
2382 /* because the PCM or MASTER volume registers can be modified, */
2383 /* the REC_GAIN register is used for tests */
2384 end_time = jiffies + HZ;
2386 unsigned short ext_mid;
2388 /* use preliminary reads to settle the communication */
2389 snd_ac97_read(ac97, AC97_RESET);
2390 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2391 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2393 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2394 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2397 /* test if we can write to the record gain volume register */
2398 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2399 err = snd_ac97_read(ac97, AC97_REC_GAIN);
2404 } while (time_after_eq(end_time, jiffies));
2406 dev_err(ac97->bus->card->dev,
2407 "CS46xx secondary codec doesn't respond!\n");
2411 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2414 struct snd_ac97_template ac97;
2416 memset(&ac97, 0, sizeof(ac97));
2417 ac97.private_data = chip;
2418 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2420 if (chip->amplifier_ctrl == amp_voyetra)
2421 ac97.scaps = AC97_SCAP_INV_EAPD;
2423 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2424 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2426 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2427 dev_dbg(chip->card->dev,
2428 "secondary codec not present\n");
2433 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2434 for (idx = 0; idx < 100; ++idx) {
2435 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2436 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2441 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2445 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2447 struct snd_card *card = chip->card;
2448 struct snd_ctl_elem_id id;
2451 static const struct snd_ac97_bus_ops ops = {
2452 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2453 .reset = snd_cs46xx_codec_reset,
2455 .write = snd_cs46xx_ac97_write,
2456 .read = snd_cs46xx_ac97_read,
2459 /* detect primary codec */
2460 chip->nr_ac97_codecs = 0;
2461 dev_dbg(chip->card->dev, "detecting primary codec\n");
2462 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2466 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2468 chip->nr_ac97_codecs = 1;
2470 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2471 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2472 /* try detect a secondary codec */
2473 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2474 chip->nr_ac97_codecs = 2;
2475 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2477 /* add cs4630 mixer controls */
2478 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2479 struct snd_kcontrol *kctl;
2480 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2481 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2482 kctl->id.device = spdif_device;
2483 err = snd_ctl_add(card, kctl);
2488 /* get EAPD mixer switch (for voyetra hack) */
2489 memset(&id, 0, sizeof(id));
2490 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2491 strcpy(id.name, "External Amplifier");
2492 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2494 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2495 if (chip->nr_ac97_codecs == 1) {
2496 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2497 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2498 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2501 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2502 AC97_CSR_ACMODE, 0x200);
2505 /* do soundcard specific mixer setup */
2506 if (chip->mixer_init) {
2507 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2508 chip->mixer_init(chip);
2512 /* turn on amplifier */
2513 chip->amplifier_ctrl(chip, 1);
2522 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2524 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2526 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2529 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2531 struct snd_cs46xx *chip = substream->rmidi->private_data;
2533 chip->active_ctrl(chip, 1);
2534 spin_lock_irq(&chip->reg_lock);
2535 chip->uartm |= CS46XX_MODE_INPUT;
2536 chip->midcr |= MIDCR_RXE;
2537 chip->midi_input = substream;
2538 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2539 snd_cs46xx_midi_reset(chip);
2541 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2543 spin_unlock_irq(&chip->reg_lock);
2547 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2549 struct snd_cs46xx *chip = substream->rmidi->private_data;
2551 spin_lock_irq(&chip->reg_lock);
2552 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2553 chip->midi_input = NULL;
2554 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2555 snd_cs46xx_midi_reset(chip);
2557 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2559 chip->uartm &= ~CS46XX_MODE_INPUT;
2560 spin_unlock_irq(&chip->reg_lock);
2561 chip->active_ctrl(chip, -1);
2565 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2567 struct snd_cs46xx *chip = substream->rmidi->private_data;
2569 chip->active_ctrl(chip, 1);
2571 spin_lock_irq(&chip->reg_lock);
2572 chip->uartm |= CS46XX_MODE_OUTPUT;
2573 chip->midcr |= MIDCR_TXE;
2574 chip->midi_output = substream;
2575 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2576 snd_cs46xx_midi_reset(chip);
2578 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2580 spin_unlock_irq(&chip->reg_lock);
2584 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2586 struct snd_cs46xx *chip = substream->rmidi->private_data;
2588 spin_lock_irq(&chip->reg_lock);
2589 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2590 chip->midi_output = NULL;
2591 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2592 snd_cs46xx_midi_reset(chip);
2594 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2596 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2597 spin_unlock_irq(&chip->reg_lock);
2598 chip->active_ctrl(chip, -1);
2602 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2604 unsigned long flags;
2605 struct snd_cs46xx *chip = substream->rmidi->private_data;
2607 spin_lock_irqsave(&chip->reg_lock, flags);
2609 if ((chip->midcr & MIDCR_RIE) == 0) {
2610 chip->midcr |= MIDCR_RIE;
2611 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2614 if (chip->midcr & MIDCR_RIE) {
2615 chip->midcr &= ~MIDCR_RIE;
2616 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2619 spin_unlock_irqrestore(&chip->reg_lock, flags);
2622 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2624 unsigned long flags;
2625 struct snd_cs46xx *chip = substream->rmidi->private_data;
2628 spin_lock_irqsave(&chip->reg_lock, flags);
2630 if ((chip->midcr & MIDCR_TIE) == 0) {
2631 chip->midcr |= MIDCR_TIE;
2632 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2633 while ((chip->midcr & MIDCR_TIE) &&
2634 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2635 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2636 chip->midcr &= ~MIDCR_TIE;
2638 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2641 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2644 if (chip->midcr & MIDCR_TIE) {
2645 chip->midcr &= ~MIDCR_TIE;
2646 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2649 spin_unlock_irqrestore(&chip->reg_lock, flags);
2652 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2654 .open = snd_cs46xx_midi_output_open,
2655 .close = snd_cs46xx_midi_output_close,
2656 .trigger = snd_cs46xx_midi_output_trigger,
2659 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2661 .open = snd_cs46xx_midi_input_open,
2662 .close = snd_cs46xx_midi_input_close,
2663 .trigger = snd_cs46xx_midi_input_trigger,
2666 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2668 struct snd_rawmidi *rmidi;
2671 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2674 strcpy(rmidi->name, "CS46XX");
2675 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2676 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2677 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2678 rmidi->private_data = chip;
2679 chip->rmidi = rmidi;
2685 * gameport interface
2688 #if IS_REACHABLE(CONFIG_GAMEPORT)
2690 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2692 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2694 if (snd_BUG_ON(!chip))
2696 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2699 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2701 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2703 if (snd_BUG_ON(!chip))
2705 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2708 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2710 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2711 unsigned js1, js2, jst;
2713 if (snd_BUG_ON(!chip))
2716 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2717 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2718 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2720 *buttons = (~jst >> 4) & 0x0F;
2722 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2723 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2724 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2725 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2727 for(jst=0;jst<4;++jst)
2728 if(axes[jst]==0xFFFF) axes[jst] = -1;
2732 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2735 case GAMEPORT_MODE_COOKED:
2737 case GAMEPORT_MODE_RAW:
2745 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2747 struct gameport *gp;
2749 chip->gameport = gp = gameport_allocate_port();
2751 dev_err(chip->card->dev,
2752 "cannot allocate memory for gameport\n");
2756 gameport_set_name(gp, "CS46xx Gameport");
2757 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2758 gameport_set_dev_parent(gp, &chip->pci->dev);
2759 gameport_set_port_data(gp, chip);
2761 gp->open = snd_cs46xx_gameport_open;
2762 gp->read = snd_cs46xx_gameport_read;
2763 gp->trigger = snd_cs46xx_gameport_trigger;
2764 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2766 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2767 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2769 gameport_register_port(gp);
2774 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2776 if (chip->gameport) {
2777 gameport_unregister_port(chip->gameport);
2778 chip->gameport = NULL;
2782 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2783 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2784 #endif /* CONFIG_GAMEPORT */
2786 #ifdef CONFIG_SND_PROC_FS
2791 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2792 void *file_private_data,
2793 struct file *file, char __user *buf,
2794 size_t count, loff_t pos)
2796 struct snd_cs46xx_region *region = entry->private_data;
2798 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2803 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2804 .read = snd_cs46xx_io_read,
2807 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2809 struct snd_info_entry *entry;
2812 for (idx = 0; idx < 5; idx++) {
2813 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2814 if (! snd_card_proc_new(card, region->name, &entry)) {
2815 entry->content = SNDRV_INFO_CONTENT_DATA;
2816 entry->private_data = chip;
2817 entry->c.ops = &snd_cs46xx_proc_io_ops;
2818 entry->size = region->size;
2819 entry->mode = S_IFREG | 0400;
2822 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2823 cs46xx_dsp_proc_init(card, chip);
2828 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2830 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2831 cs46xx_dsp_proc_done(chip);
2835 #else /* !CONFIG_SND_PROC_FS */
2836 #define snd_cs46xx_proc_init(card, chip)
2837 #define snd_cs46xx_proc_done(chip)
2843 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2847 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2850 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2852 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2855 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2858 * Stop playback DMA.
2860 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2861 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2866 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2867 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2870 * Reset the processor.
2872 snd_cs46xx_reset(chip);
2874 snd_cs46xx_proc_stop(chip);
2877 * Power down the PLL.
2879 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2882 * Turn off the Processor by turning off the software clock enable flag in
2883 * the clock control register.
2885 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2886 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2890 static void snd_cs46xx_free(struct snd_card *card)
2892 struct snd_cs46xx *chip = card->private_data;
2893 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2897 if (chip->active_ctrl)
2898 chip->active_ctrl(chip, 1);
2900 snd_cs46xx_remove_gameport(chip);
2902 if (chip->amplifier_ctrl)
2903 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2905 snd_cs46xx_proc_done(chip);
2907 snd_cs46xx_hw_stop(chip);
2909 if (chip->active_ctrl)
2910 chip->active_ctrl(chip, -chip->amplifier);
2912 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2913 if (chip->dsp_spos_instance) {
2914 cs46xx_dsp_spos_destroy(chip);
2915 chip->dsp_spos_instance = NULL;
2917 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2918 free_module_desc(chip->modules[idx]);
2927 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2932 * First, blast the clock control register to zero so that the PLL starts
2933 * out in a known state, and blast the master serial port control register
2934 * to zero so that the serial ports also start out in a known state.
2936 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2937 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2940 * If we are in AC97 mode, then we must set the part to a host controlled
2941 * AC-link. Otherwise, we won't be able to bring up the link.
2943 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2944 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2945 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2946 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2948 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2952 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2953 * spec) and then drive it high. This is done for non AC97 modes since
2954 * there might be logic external to the CS461x that uses the ARST# line
2957 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2958 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2959 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2962 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2963 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2964 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2968 * The first thing we do here is to enable sync generation. As soon
2969 * as we start receiving bit clock, we'll start producing the SYNC
2972 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2974 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2978 * Now wait for a short while to allow the AC97 part to start
2979 * generating bit clock (so we don't try to start the PLL without an
2985 * Set the serial port timing configuration, so that
2986 * the clock control circuit gets its clock from the correct place.
2988 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2991 * Write the selected clock control setup to the hardware. Do not turn on
2992 * SWCE yet (if requested), so that the devices clocked by the output of
2993 * PLL are not clocked until the PLL is stable.
2995 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2996 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2997 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3002 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3005 * Wait until the PLL has stabilized.
3010 * Turn on clocking of the core so that we can setup the serial ports.
3012 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3015 * Enable FIFO Host Bypass
3017 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3020 * Fill the serial port FIFOs with silence.
3022 snd_cs46xx_clear_serial_FIFOs(chip);
3025 * Set the serial port FIFO pointer to the first sample in the FIFO.
3027 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3030 * Write the serial port configuration to the part. The master
3031 * enable bit is not set until all other values have been written.
3033 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3034 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3035 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3038 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3039 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3040 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3041 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3042 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3043 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3050 * Wait for the codec ready signal from the AC97 codec.
3053 while (timeout-- > 0) {
3055 * Read the AC97 status register to see if we've seen a CODEC READY
3056 * signal from the AC97 codec.
3058 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3064 dev_err(chip->card->dev,
3065 "create - never read codec ready from AC'97\n");
3066 dev_err(chip->card->dev,
3067 "it is not probably bug, try to use CS4236 driver\n");
3070 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3073 for (count = 0; count < 150; count++) {
3074 /* First, we want to wait for a short time. */
3077 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3082 * Make sure CODEC is READY.
3084 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3085 dev_dbg(chip->card->dev,
3086 "never read card ready from secondary AC'97\n");
3091 * Assert the vaid frame signal so that we can start sending commands
3092 * to the AC97 codec.
3094 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3095 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3096 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3101 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3102 * the codec is pumping ADC data across the AC-link.
3105 while (timeout-- > 0) {
3107 * Read the input slot valid register and see if input slots 3 and
3110 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3115 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3116 dev_err(chip->card->dev,
3117 "create - never read ISV3 & ISV4 from AC'97\n");
3120 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3121 Reloading the driver may help, if there's other soundcards
3122 with the same problem I would like to know. (Benny) */
3124 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3125 dev_err(chip->card->dev,
3126 "Try reloading the ALSA driver, if you find something\n");
3127 dev_err(chip->card->dev,
3128 "broken or not working on your soundcard upon\n");
3129 dev_err(chip->card->dev,
3130 "this message please report to alsa-devel@alsa-project.org\n");
3137 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3138 * commense the transfer of digital audio data to the AC97 codec.
3141 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3145 * Power down the DAC and ADC. We will power them up (if) when we need
3148 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3151 * Turn off the Processor by turning off the software clock enable flag in
3152 * the clock control register.
3154 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3155 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3161 * start and load DSP
3164 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3168 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3170 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3172 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3174 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3177 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3180 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3183 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3189 * Reset the processor.
3191 snd_cs46xx_reset(chip);
3193 * Download the image to the processor.
3195 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3196 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3197 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3199 dev_err(chip->card->dev, "firmware load error [%s]\n",
3203 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3205 dev_err(chip->card->dev, "image download error [%s]\n",
3211 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3214 err = load_firmware(chip);
3219 err = snd_cs46xx_download_image(chip);
3221 dev_err(chip->card->dev, "image download error\n");
3226 * Stop playback DMA.
3228 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3229 chip->play_ctl = tmp & 0xffff0000;
3230 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3236 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3237 chip->capt.ctl = tmp & 0x0000ffff;
3238 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3242 snd_cs46xx_set_play_sample_rate(chip, 8000);
3243 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3245 snd_cs46xx_proc_start(chip);
3247 cs46xx_enable_stream_irqs(chip);
3249 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3250 /* set the attenuation to 0dB */
3251 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3252 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3260 * AMP control - null AMP
3263 static void amp_none(struct snd_cs46xx *chip, int change)
3267 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3268 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3271 u32 idx, valid_slots,tmp,powerdown = 0;
3272 u16 modem_power,pin_config,logic_type;
3274 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3277 * See if the devices are powered down. If so, we must power them up first
3278 * or they will not respond.
3280 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3282 if (!(tmp & CLKCR1_SWCE)) {
3283 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3288 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3291 if(chip->nr_ac97_codecs != 2) {
3292 dev_err(chip->card->dev,
3293 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3297 modem_power = snd_cs46xx_codec_read (chip,
3298 AC97_EXTENDED_MSTATUS,
3299 CS46XX_SECONDARY_CODEC_INDEX);
3300 modem_power &=0xFEFF;
3302 snd_cs46xx_codec_write(chip,
3303 AC97_EXTENDED_MSTATUS, modem_power,
3304 CS46XX_SECONDARY_CODEC_INDEX);
3307 * Set GPIO pin's 7 and 8 so that they are configured for output.
3309 pin_config = snd_cs46xx_codec_read (chip,
3311 CS46XX_SECONDARY_CODEC_INDEX);
3314 snd_cs46xx_codec_write(chip,
3315 AC97_GPIO_CFG, pin_config,
3316 CS46XX_SECONDARY_CODEC_INDEX);
3319 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3322 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3323 CS46XX_SECONDARY_CODEC_INDEX);
3326 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3327 CS46XX_SECONDARY_CODEC_INDEX);
3329 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3330 valid_slots |= 0x200;
3331 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3333 if ( cs46xx_wait_for_fifo(chip,1) ) {
3334 dev_dbg(chip->card->dev, "FIFO is busy\n");
3340 * Fill slots 12 with the correct value for the GPIO pins.
3342 for(idx = 0x90; idx <= 0x9F; idx++) {
3344 * Initialize the fifo so that bits 7 and 8 are on.
3346 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3347 * the left. 0x1800 corresponds to bits 7 and 8.
3349 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3352 * Wait for command to complete
3354 if ( cs46xx_wait_for_fifo(chip,200) ) {
3355 dev_dbg(chip->card->dev,
3356 "failed waiting for FIFO at addr (%02X)\n",
3363 * Write the serial port FIFO index.
3365 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3368 * Tell the serial port to load the new value into the FIFO location.
3370 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3373 /* wait for last command to complete */
3374 cs46xx_wait_for_fifo(chip,200);
3377 * Now, if we powered up the devices, then power them back down again.
3378 * This is kinda ugly, but should never happen.
3381 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3391 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3393 /* Manage the EAPD bit on the Crystal 4297
3394 and the Analog AD1885 */
3396 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3397 int old = chip->amplifier;
3401 chip->amplifier += change;
3402 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3403 CS46XX_PRIMARY_CODEC_INDEX);
3405 if (chip->amplifier) {
3406 /* Turn the EAPD amp on */
3409 /* Turn the EAPD amp off */
3413 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3414 CS46XX_PRIMARY_CODEC_INDEX);
3415 if (chip->eapd_switch)
3416 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3417 &chip->eapd_switch->id);
3420 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3421 if (chip->amplifier && !old) {
3422 voyetra_setup_eapd_slot(chip);
3427 static void hercules_init(struct snd_cs46xx *chip)
3429 /* default: AMP off, and SPDIF input optical */
3430 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3431 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3436 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3438 static void amp_hercules(struct snd_cs46xx *chip, int change)
3440 int old = chip->amplifier;
3441 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3442 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3444 chip->amplifier += change;
3445 if (chip->amplifier && !old) {
3446 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3448 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3449 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3450 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3451 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3452 } else if (old && !chip->amplifier) {
3453 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3454 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3455 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3459 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3461 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3463 /* Enable SPDIF out */
3464 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3465 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3468 static void hercules_mixer_init (struct snd_cs46xx *chip)
3470 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3473 struct snd_card *card = chip->card;
3476 /* set EGPIO to default */
3477 hercules_init(chip);
3479 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3481 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3482 if (chip->in_suspend)
3485 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3486 struct snd_kcontrol *kctl;
3488 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3489 err = snd_ctl_add(card, kctl);
3492 "failed to initialize Hercules mixer (%d)\n",
3506 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3508 chip->amplifier += change;
3510 if (chip->amplifier) {
3511 /* Switch the GPIO pins 7 and 8 to open drain */
3512 snd_cs46xx_codec_write(chip, 0x4C,
3513 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3514 snd_cs46xx_codec_write(chip, 0x4E,
3515 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3516 /* Now wake the AMP (this might be backwards) */
3517 snd_cs46xx_codec_write(chip, 0x54,
3518 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3520 snd_cs46xx_codec_write(chip, 0x54,
3521 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3528 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3529 * whenever we need to beat on the chip.
3531 * The original idea and code for this hack comes from David Kaiser at
3532 * Linuxcare. Perhaps one day Crystal will document their chips well
3533 * enough to make them useful.
3536 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3540 if (!chip->acpi_port)
3543 chip->amplifier += change;
3545 /* Read ACPI port */
3546 nval = control = inw(chip->acpi_port + 0x10);
3548 /* Flip CLKRUN off while running */
3549 if (! chip->amplifier)
3553 if (nval != control)
3554 outw(nval, chip->acpi_port + 0x10);
3559 * detect intel piix4
3561 static void clkrun_init(struct snd_cs46xx *chip)
3563 struct pci_dev *pdev;
3566 chip->acpi_port = 0;
3568 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3569 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3571 return; /* Not a thinkpad thats for sure */
3573 /* Find the control port */
3574 pci_read_config_byte(pdev, 0x41, &pp);
3575 chip->acpi_port = pp << 8;
3589 void (*init)(struct snd_cs46xx *);
3590 void (*amp)(struct snd_cs46xx *, int);
3591 void (*active)(struct snd_cs46xx *, int);
3592 void (*mixer_init)(struct snd_cs46xx *);
3595 static struct cs_card_type cards[] = {
3599 .name = "Genius Soundmaker 128 value",
3600 /* nothing special */
3607 .mixer_init = voyetra_mixer_init,
3612 .name = "Mitac MI6020/21",
3615 /* Hercules Game Theatre XP */
3617 .vendor = 0x14af, /* Guillemot Corporation */
3619 .name = "Hercules Game Theatre XP",
3620 .amp = amp_hercules,
3621 .mixer_init = hercules_mixer_init,
3626 .name = "Hercules Game Theatre XP",
3627 .amp = amp_hercules,
3628 .mixer_init = hercules_mixer_init,
3633 .name = "Hercules Game Theatre XP",
3634 .amp = amp_hercules,
3635 .mixer_init = hercules_mixer_init,
3641 .name = "Hercules Game Theatre XP",
3642 .amp = amp_hercules,
3643 .mixer_init = hercules_mixer_init,
3648 .name = "Hercules Game Theatre XP",
3649 .amp = amp_hercules,
3650 .mixer_init = hercules_mixer_init,
3655 .name = "Hercules Game Theatre XP",
3656 .amp = amp_hercules,
3657 .mixer_init = hercules_mixer_init,
3659 /* Herculess Fortissimo */
3663 .name = "Hercules Gamesurround Fortissimo II",
3668 .name = "Hercules Gamesurround Fortissimo III 7.1",
3674 .name = "Terratec DMX XFire 1024",
3679 .name = "Terratec SiXPack 5.1",
3681 /* Not sure if the 570 needs the clkrun hack */
3683 .vendor = PCI_VENDOR_ID_IBM,
3685 .name = "Thinkpad 570",
3686 .init = clkrun_init,
3687 .active = clkrun_hack,
3690 .vendor = PCI_VENDOR_ID_IBM,
3692 .name = "Thinkpad 600X/A20/T20",
3693 .init = clkrun_init,
3694 .active = clkrun_hack,
3697 .vendor = PCI_VENDOR_ID_IBM,
3699 .name = "Thinkpad 600E (unsupported)",
3708 #ifdef CONFIG_PM_SLEEP
3709 static const unsigned int saved_regs[] = {
3717 static int snd_cs46xx_suspend(struct device *dev)
3719 struct snd_card *card = dev_get_drvdata(dev);
3720 struct snd_cs46xx *chip = card->private_data;
3723 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3724 chip->in_suspend = 1;
3725 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3726 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3728 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3729 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3731 /* save some registers */
3732 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3733 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3735 amp_saved = chip->amplifier;
3737 chip->amplifier_ctrl(chip, -chip->amplifier);
3738 snd_cs46xx_hw_stop(chip);
3739 /* disable CLKRUN */
3740 chip->active_ctrl(chip, -chip->amplifier);
3741 chip->amplifier = amp_saved; /* restore the status */
3745 static int snd_cs46xx_resume(struct device *dev)
3747 struct snd_card *card = dev_get_drvdata(dev);
3748 struct snd_cs46xx *chip = card->private_data;
3750 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3755 amp_saved = chip->amplifier;
3756 chip->amplifier = 0;
3757 chip->active_ctrl(chip, 1); /* force to on */
3759 snd_cs46xx_chip_init(chip);
3761 snd_cs46xx_reset(chip);
3762 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3763 cs46xx_dsp_resume(chip);
3764 /* restore some registers */
3765 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3766 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3768 snd_cs46xx_download_image(chip);
3772 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3773 chip->ac97_general_purpose);
3774 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3775 chip->ac97_powerdown);
3777 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3778 chip->ac97_powerdown);
3782 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3783 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3788 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3789 chip->capt.ctl = tmp & 0x0000ffff;
3790 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3794 /* reset playback/capture */
3795 snd_cs46xx_set_play_sample_rate(chip, 8000);
3796 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3797 snd_cs46xx_proc_start(chip);
3799 cs46xx_enable_stream_irqs(chip);
3802 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3804 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3805 chip->amplifier = amp_saved;
3806 chip->in_suspend = 0;
3807 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3811 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3812 #endif /* CONFIG_PM_SLEEP */
3818 int snd_cs46xx_create(struct snd_card *card,
3819 struct pci_dev *pci,
3820 int external_amp, int thinkpad)
3822 struct snd_cs46xx *chip = card->private_data;
3824 struct snd_cs46xx_region *region;
3825 struct cs_card_type *cp;
3826 u16 ss_card, ss_vendor;
3828 /* enable PCI device */
3829 err = pcim_enable_device(pci);
3833 spin_lock_init(&chip->reg_lock);
3834 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3835 mutex_init(&chip->spos_mutex);
3841 err = pci_request_regions(pci, "CS46xx");
3844 chip->ba0_addr = pci_resource_start(pci, 0);
3845 chip->ba1_addr = pci_resource_start(pci, 1);
3846 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3847 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3848 dev_err(chip->card->dev,
3849 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3850 chip->ba0_addr, chip->ba1_addr);
3854 region = &chip->region.name.ba0;
3855 strcpy(region->name, "CS46xx_BA0");
3856 region->base = chip->ba0_addr;
3857 region->size = CS46XX_BA0_SIZE;
3859 region = &chip->region.name.data0;
3860 strcpy(region->name, "CS46xx_BA1_data0");
3861 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3862 region->size = CS46XX_BA1_DATA0_SIZE;
3864 region = &chip->region.name.data1;
3865 strcpy(region->name, "CS46xx_BA1_data1");
3866 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3867 region->size = CS46XX_BA1_DATA1_SIZE;
3869 region = &chip->region.name.pmem;
3870 strcpy(region->name, "CS46xx_BA1_pmem");
3871 region->base = chip->ba1_addr + BA1_SP_PMEM;
3872 region->size = CS46XX_BA1_PRG_SIZE;
3874 region = &chip->region.name.reg;
3875 strcpy(region->name, "CS46xx_BA1_reg");
3876 region->base = chip->ba1_addr + BA1_SP_REG;
3877 region->size = CS46XX_BA1_REG_SIZE;
3879 /* set up amp and clkrun hack */
3880 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3881 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3883 for (cp = &cards[0]; cp->name; cp++) {
3884 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3885 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3888 chip->amplifier_ctrl = cp->amp;
3889 chip->active_ctrl = cp->active;
3890 chip->mixer_init = cp->mixer_init;
3899 dev_info(chip->card->dev,
3900 "Crystal EAPD support forced on.\n");
3901 chip->amplifier_ctrl = amp_voyetra;
3905 dev_info(chip->card->dev,
3906 "Activating CLKRUN hack for Thinkpad.\n");
3907 chip->active_ctrl = clkrun_hack;
3911 if (chip->amplifier_ctrl == NULL)
3912 chip->amplifier_ctrl = amp_none;
3913 if (chip->active_ctrl == NULL)
3914 chip->active_ctrl = amp_none;
3916 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3918 pci_set_master(pci);
3920 for (idx = 0; idx < 5; idx++) {
3921 region = &chip->region.idx[idx];
3922 region->remap_addr = devm_ioremap(&pci->dev, region->base,
3924 if (region->remap_addr == NULL) {
3925 dev_err(chip->card->dev,
3926 "%s ioremap problem\n", region->name);
3931 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt,
3932 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3933 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3936 chip->irq = pci->irq;
3937 card->sync_irq = chip->irq;
3938 card->private_free = snd_cs46xx_free;
3940 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3941 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3942 if (!chip->dsp_spos_instance)
3946 err = snd_cs46xx_chip_init(chip);
3950 snd_cs46xx_proc_init(card, chip);
3952 #ifdef CONFIG_PM_SLEEP
3953 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3954 ARRAY_SIZE(saved_regs),
3955 sizeof(*chip->saved_regs),
3957 if (!chip->saved_regs)
3961 chip->active_ctrl(chip, -1); /* disable CLKRUN */