sound/pci/cs46xx/cs46xx_lib.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   4  *                   Abramo Bagnara <abramo@alsa-project.org>
   5  *                   Cirrus Logic, Inc.
   6  *  Routines for control of Cirrus Logic CS461x chips
   7  *
   8  *  KNOWN BUGS:
   9  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
  10  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  11  *      are swapped. To get around this problem when it happens, mute and unmute
  12  *      the SPDIF input mixer control.
  13  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  14  *      off on inadecuate moments which causes distorcions on sound.
  15  *
  16  *  TODO:
  17  *    - Secondary CODEC on some soundcards
  18  *    - SPDIF input support for other sample rates then 48khz
  19  *    - Posibility to mix the SPDIF output with analog sources.
  20  *    - PCM channels for Center and LFE on secondary codec
  21  *
  22  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  23  *        is default configuration), no SPDIF, no secondary codec, no
  24  *        multi channel PCM.  But known to work.
  25  *
  26  *  FINALLY: A credit to the developers Tom and Jordan
  27  *           at Cirrus for have helping me out with the DSP, however we
  28  *           still don't have sufficient documentation and technical
  29  *           references to be able to implement all fancy feutures
  30  *           supported by the cs46xx DSP's.
  31  *           Benny <benny@hostmobility.com>
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/pci.h>
  36 #include <linux/pm.h>
  37 #include <linux/init.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/slab.h>
  40 #include <linux/gameport.h>
  41 #include <linux/mutex.h>
  42 #include <linux/export.h>
  43 #include <linux/module.h>
  44 #include <linux/firmware.h>
  45 #include <linux/vmalloc.h>
  46 #include <linux/io.h>
  47
  48 #include <sound/core.h>
  49 #include <sound/control.h>
  50 #include <sound/info.h>
  51 #include <sound/pcm.h>
  52 #include <sound/pcm_params.h>
  53 #include "cs46xx.h"
  54
  55 #include "cs46xx_lib.h"
  56 #include "dsp_spos.h"
  57
  58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
  59
  60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
  61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  67 #endif
  68
  69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
  70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
  72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  73
  74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  75                                             unsigned short reg,
  76                                             int codec_index)
  77 {
  78         int count;
  79         unsigned short result,tmp;
  80         u32 offset = 0;
  81
  82         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
  83                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
  84                 return 0xffff;
  85
  86         chip->active_ctrl(chip, 1);
  87
  88         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  89                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
  90
  91         /*
  92          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  93          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
  94          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
  95          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  96          *  5. if DCV not cleared, break and return error
  97          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
  98          */
  99
 100         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 101
 102         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 103         if ((tmp & ACCTL_VFRM) == 0) {
 104                 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
 105                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 106                 msleep(50);
 107                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 108                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 109
 110         }
 111
 112         /*
 113          *  Setup the AC97 control registers on the CS461x to send the
 114          *  appropriate command to the AC97 to perform the read.
 115          *  ACCAD = Command Address Register = 46Ch
 116          *  ACCDA = Command Data Register = 470h
 117          *  ACCTL = Control Register = 460h
 118          *  set DCV - will clear when process completed
 119          *  set CRW - Read command
 120          *  set VFRM - valid frame enabled
 121          *  set ESYN - ASYNC generation enabled
 122          *  set RSTN - ARST# inactive, AC97 codec not reset
 123          */
 124
 125         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 126         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 127         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 128                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 129                                    ACCTL_VFRM | ACCTL_ESYN |
 130                                    ACCTL_RSTN);
 131                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 132                                    ACCTL_VFRM | ACCTL_ESYN |
 133                                    ACCTL_RSTN);
 134         } else {
 135                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 136                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 137                                    ACCTL_RSTN);
 138         }
 139
 140         /*
 141          *  Wait for the read to occur.
 142          */
 143         for (count = 0; count < 1000; count++) {
 144                 /*
 145                  *  First, we want to wait for a short time.
 146                  */
 147                 udelay(10);
 148                 /*
 149                  *  Now, check to see if the read has completed.
 150                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 151                  */
 152                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 153                         goto ok1;
 154         }
 155
 156         dev_err(chip->card->dev,
 157                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 158         result = 0xffff;
 159         goto end;
 160
 161  ok1:
 162         /*
 163          *  Wait for the valid status bit to go active.
 164          */
 165         for (count = 0; count < 100; count++) {
 166                 /*
 167                  *  Read the AC97 status register.
 168                  *  ACSTS = Status Register = 464h
 169                  *  VSTS - Valid Status
 170                  */
 171                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 172                         goto ok2;
 173                 udelay(10);
 174         }
 175
 176         dev_err(chip->card->dev,
 177                 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
 178                 codec_index, reg);
 179         result = 0xffff;
 180         goto end;
 181
 182  ok2:
 183         /*
 184          *  Read the data returned from the AC97 register.
 185          *  ACSDA = Status Data Register = 474h
 186          */
 187 #if 0
 188         dev_dbg(chip->card->dev,
 189                 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 190                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 191                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 192 #endif
 193
 194         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 195         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 196  end:
 197         chip->active_ctrl(chip, -1);
 198         return result;
 199 }
 200
 201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
 202                                             unsigned short reg)
 203 {
 204         struct snd_cs46xx *chip = ac97->private_data;
 205         unsigned short val;
 206         int codec_index = ac97->num;
 207
 208         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 209                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 210                 return 0xffff;
 211
 212         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 213
 214         return val;
 215 }
 216
 217
 218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
 219                                    unsigned short reg,
 220                                    unsigned short val,
 221                                    int codec_index)
 222 {
 223         int count;
 224
 225         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 226                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 227                 return;
 228
 229         chip->active_ctrl(chip, 1);
 230
 231         /*
 232          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 233          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 234          *  3. Write ACCTL = Control Register = 460h for initiating the write
 235          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 236          *  5. if DCV not cleared, break and return error
 237          */
 238
 239         /*
 240          *  Setup the AC97 control registers on the CS461x to send the
 241          *  appropriate command to the AC97 to perform the read.
 242          *  ACCAD = Command Address Register = 46Ch
 243          *  ACCDA = Command Data Register = 470h
 244          *  ACCTL = Control Register = 460h
 245          *  set DCV - will clear when process completed
 246          *  reset CRW - Write command
 247          *  set VFRM - valid frame enabled
 248          *  set ESYN - ASYNC generation enabled
 249          *  set RSTN - ARST# inactive, AC97 codec not reset
 250          */
 251         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 252         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 253         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 254
 255         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 256                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 257                                    ACCTL_ESYN | ACCTL_RSTN);
 258                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 259                                    ACCTL_ESYN | ACCTL_RSTN);
 260         } else {
 261                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 262                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 263         }
 264
 265         for (count = 0; count < 4000; count++) {
 266                 /*
 267                  *  First, we want to wait for a short time.
 268                  */
 269                 udelay(10);
 270                 /*
 271                  *  Now, check to see if the write has completed.
 272                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 273                  */
 274                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 275                         goto end;
 276                 }
 277         }
 278         dev_err(chip->card->dev,
 279                 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
 280                 codec_index, reg, val);
 281  end:
 282         chip->active_ctrl(chip, -1);
 283 }
 284
 285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
 286                                    unsigned short reg,
 287                                    unsigned short val)
 288 {
 289         struct snd_cs46xx *chip = ac97->private_data;
 290         int codec_index = ac97->num;
 291
 292         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 293                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 294                 return;
 295
 296         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 297 }
 298
 299
 300 /*
 301  *  Chip initialization
 302  */
 303
 304 int snd_cs46xx_download(struct snd_cs46xx *chip,
 305                         u32 *src,
 306                         unsigned long offset,
 307                         unsigned long len)
 308 {
 309         void __iomem *dst;
 310         unsigned int bank = offset >> 16;
 311         offset = offset & 0xffff;
 312
 313         if (snd_BUG_ON((offset & 3) || (len & 3)))
 314                 return -EINVAL;
 315         dst = chip->region.idx[bank+1].remap_addr + offset;
 316         len /= sizeof(u32);
 317
 318         /* writel already converts 32-bit value to right endianess */
 319         while (len-- > 0) {
 320                 writel(*src++, dst);
 321                 dst += sizeof(u32);
 322         }
 323         return 0;
 324 }
 325
 326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
 327 {
 328 #ifdef __LITTLE_ENDIAN
 329         memcpy(dst, src, len);
 330 #else
 331         u32 *_dst = dst;
 332         const __le32 *_src = src;
 333         len /= 4;
 334         while (len-- > 0)
 335                 *_dst++ = le32_to_cpu(*_src++);
 336 #endif
 337 }
 338
 339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 340
 341 static const char *module_names[CS46XX_DSP_MODULES] = {
 342         "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
 343 };
 344
 345 /*(DEBLOBBED)*/
 346
 347 static void free_module_desc(struct dsp_module_desc *module)
 348 {
 349         if (!module)
 350                 return;
 351         kfree(module->module_name);
 352         kfree(module->symbol_table.symbols);
 353         if (module->segments) {
 354                 int i;
 355                 for (i = 0; i < module->nsegments; i++)
 356                         kfree(module->segments[i].data);
 357                 kfree(module->segments);
 358         }
 359         kfree(module);
 360 }
 361
 362 /* firmware binary format:
 363  * le32 nsymbols;
 364  * struct {
 365  *      le32 address;
 366  *      char symbol_name[DSP_MAX_SYMBOL_NAME];
 367  *      le32 symbol_type;
 368  * } symbols[nsymbols];
 369  * le32 nsegments;
 370  * struct {
 371  *      le32 segment_type;
 372  *      le32 offset;
 373  *      le32 size;
 374  *      le32 data[size];
 375  * } segments[nsegments];
 376  */
 377
 378 static int load_firmware(struct snd_cs46xx *chip,
 379                          struct dsp_module_desc **module_ret,
 380                          const char *fw_name)
 381 {
 382         int i, err;
 383         unsigned int nums, fwlen, fwsize;
 384         const __le32 *fwdat;
 385         struct dsp_module_desc *module = NULL;
 386         const struct firmware *fw;
 387         char fw_path[32];
 388
 389         sprintf(fw_path, "cs46xx/%s", fw_name);
 390         err = reject_firmware(&fw, fw_path, &chip->pci->dev);
 391         if (err < 0)
 392                 return err;
 393         fwsize = fw->size / 4;
 394         if (fwsize < 2) {
 395                 err = -EINVAL;
 396                 goto error;
 397         }
 398
 399         err = -ENOMEM;
 400         module = kzalloc(sizeof(*module), GFP_KERNEL);
 401         if (!module)
 402                 goto error;
 403         module->module_name = kstrdup(fw_name, GFP_KERNEL);
 404         if (!module->module_name)
 405                 goto error;
 406
 407         fwlen = 0;
 408         fwdat = (const __le32 *)fw->data;
 409         nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
 410         if (nums >= 40)
 411                 goto error_inval;
 412         module->symbol_table.symbols =
 413                 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
 414         if (!module->symbol_table.symbols)
 415                 goto error;
 416         for (i = 0; i < nums; i++) {
 417                 struct dsp_symbol_entry *entry =
 418                         &module->symbol_table.symbols[i];
 419                 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
 420                         goto error_inval;
 421                 entry->address = le32_to_cpu(fwdat[fwlen++]);
 422                 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
 423                 fwlen += DSP_MAX_SYMBOL_NAME / 4;
 424                 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
 425         }
 426
 427         if (fwlen >= fwsize)
 428                 goto error_inval;
 429         nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
 430         if (nums > 10)
 431                 goto error_inval;
 432         module->segments =
 433                 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
 434         if (!module->segments)
 435                 goto error;
 436         for (i = 0; i < nums; i++) {
 437                 struct dsp_segment_desc *entry = &module->segments[i];
 438                 if (fwlen + 3 > fwsize)
 439                         goto error_inval;
 440                 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
 441                 entry->offset = le32_to_cpu(fwdat[fwlen++]);
 442                 entry->size = le32_to_cpu(fwdat[fwlen++]);
 443                 if (fwlen + entry->size > fwsize)
 444                         goto error_inval;
 445                 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
 446                 if (!entry->data)
 447                         goto error;
 448                 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
 449                 fwlen += entry->size;
 450         }
 451
 452         *module_ret = module;
 453         release_firmware(fw);
 454         return 0;
 455
 456  error_inval:
 457         err = -EINVAL;
 458  error:
 459         free_module_desc(module);
 460         release_firmware(fw);
 461         return err;
 462 }
 463
 464 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
 465                          unsigned long offset,
 466                          unsigned long len)
 467 {
 468         void __iomem *dst;
 469         unsigned int bank = offset >> 16;
 470         offset = offset & 0xffff;
 471
 472         if (snd_BUG_ON((offset & 3) || (len & 3)))
 473                 return -EINVAL;
 474         dst = chip->region.idx[bank+1].remap_addr + offset;
 475         len /= sizeof(u32);
 476
 477         /* writel already converts 32-bit value to right endianess */
 478         while (len-- > 0) {
 479                 writel(0, dst);
 480                 dst += sizeof(u32);
 481         }
 482         return 0;
 483 }
 484
 485 #else /* old DSP image */
 486
 487 struct ba1_struct {
 488         struct {
 489                 u32 offset;
 490                 u32 size;
 491         } memory[BA1_MEMORY_COUNT];
 492         u32 map[BA1_DWORD_SIZE];
 493 };
 494
 495 /*(DEBLOBBED)*/
 496
 497 static int load_firmware(struct snd_cs46xx *chip)
 498 {
 499         const struct firmware *fw;
 500         int i, size, err;
 501
 502         err = reject_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
 503         if (err < 0)
 504                 return err;
 505         if (fw->size != sizeof(*chip->ba1)) {
 506                 err = -EINVAL;
 507                 goto error;
 508         }
 509
 510         chip->ba1 = vmalloc(sizeof(*chip->ba1));
 511         if (!chip->ba1) {
 512                 err = -ENOMEM;
 513                 goto error;
 514         }
 515
 516         memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
 517
 518         /* sanity check */
 519         size = 0;
 520         for (i = 0; i < BA1_MEMORY_COUNT; i++)
 521                 size += chip->ba1->memory[i].size;
 522         if (size > BA1_DWORD_SIZE * 4)
 523                 err = -EINVAL;
 524
 525  error:
 526         release_firmware(fw);
 527         return err;
 528 }
 529
 530 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
 531 {
 532         int idx, err;
 533         unsigned int offset = 0;
 534         struct ba1_struct *ba1 = chip->ba1;
 535
 536         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 537                 err = snd_cs46xx_download(chip,
 538                                           &ba1->map[offset],
 539                                           ba1->memory[idx].offset,
 540                                           ba1->memory[idx].size);
 541                 if (err < 0)
 542                         return err;
 543                 offset += ba1->memory[idx].size >> 2;
 544         }
 545         return 0;
 546 }
 547 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 548
 549 /*
 550  *  Chip reset
 551  */
 552
 553 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
 554 {
 555         int idx;
 556
 557         /*
 558          *  Write the reset bit of the SP control register.
 559          */
 560         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 561
 562         /*
 563          *  Write the control register.
 564          */
 565         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 566
 567         /*
 568          *  Clear the trap registers.
 569          */
 570         for (idx = 0; idx < 8; idx++) {
 571                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 572                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 573         }
 574         snd_cs46xx_poke(chip, BA1_DREG, 0);
 575
 576         /*
 577          *  Set the frame timer to reflect the number of cycles per frame.
 578          */
 579         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 580 }
 581
 582 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
 583 {
 584         u32 i, status = 0;
 585         /*
 586          * Make sure the previous FIFO write operation has completed.
 587          */
 588         for(i = 0; i < 50; i++){
 589                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 590
 591                 if( !(status & SERBST_WBSY) )
 592                         break;
 593
 594                 mdelay(retry_timeout);
 595         }
 596
 597         if(status & SERBST_WBSY) {
 598                 dev_err(chip->card->dev,
 599                         "failure waiting for FIFO command to complete\n");
 600                 return -EINVAL;
 601         }
 602
 603         return 0;
 604 }
 605
 606 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
 607 {
 608         int idx, powerdown = 0;
 609         unsigned int tmp;
 610
 611         /*
 612          *  See if the devices are powered down.  If so, we must power them up first
 613          *  or they will not respond.
 614          */
 615         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 616         if (!(tmp & CLKCR1_SWCE)) {
 617                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 618                 powerdown = 1;
 619         }
 620
 621         /*
 622          *  We want to clear out the serial port FIFOs so we don't end up playing
 623          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 624          *  with zero (silence).
 625          */
 626         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 627
 628         /*
 629          *  Fill all 256 sample FIFO locations.
 630          */
 631         for (idx = 0; idx < 0xFF; idx++) {
 632                 /*
 633                  *  Make sure the previous FIFO write operation has completed.
 634                  */
 635                 if (cs46xx_wait_for_fifo(chip,1)) {
 636                         dev_dbg(chip->card->dev,
 637                                 "failed waiting for FIFO at addr (%02X)\n",
 638                                 idx);
 639
 640                         if (powerdown)
 641                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 642
 643                         break;
 644                 }
 645                 /*
 646                  *  Write the serial port FIFO index.
 647                  */
 648                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 649                 /*
 650                  *  Tell the serial port to load the new value into the FIFO location.
 651                  */
 652                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 653         }
 654         /*
 655          *  Now, if we powered up the devices, then power them back down again.
 656          *  This is kinda ugly, but should never happen.
 657          */
 658         if (powerdown)
 659                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 660 }
 661
 662 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
 663 {
 664         int cnt;
 665
 666         /*
 667          *  Set the frame timer to reflect the number of cycles per frame.
 668          */
 669         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 670         /*
 671          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 672          *  the SP control register.
 673          */
 674         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 675         /*
 676          *  Wait until the run at frame bit resets itself in the SP control
 677          *  register.
 678          */
 679         for (cnt = 0; cnt < 25; cnt++) {
 680                 udelay(50);
 681                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 682                         break;
 683         }
 684
 685         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 686                 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
 687 }
 688
 689 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
 690 {
 691         /*
 692          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 693          *  the SP control register.
 694          */
 695         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 696 }
 697
 698 /*
 699  *  Sample rate routines
 700  */
 701
 702 #define GOF_PER_SEC 200
 703
 704 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 705 {
 706         unsigned long flags;
 707         unsigned int tmp1, tmp2;
 708         unsigned int phiIncr;
 709         unsigned int correctionPerGOF, correctionPerSec;
 710
 711         /*
 712          *  Compute the values used to drive the actual sample rate conversion.
 713          *  The following formulas are being computed, using inline assembly
 714          *  since we need to use 64 bit arithmetic to compute the values:
 715          *
 716          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 717          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 718          *                                   GOF_PER_SEC)
 719          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 720          *                       GOF_PER_SEC * correctionPerGOF
 721          *
 722          *  i.e.
 723          *
 724          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 725          *  correctionPerGOF:correctionPerSec =
 726          *      dividend:remainder(ulOther / GOF_PER_SEC)
 727          */
 728         tmp1 = rate << 16;
 729         phiIncr = tmp1 / 48000;
 730         tmp1 -= phiIncr * 48000;
 731         tmp1 <<= 10;
 732         phiIncr <<= 10;
 733         tmp2 = tmp1 / 48000;
 734         phiIncr += tmp2;
 735         tmp1 -= tmp2 * 48000;
 736         correctionPerGOF = tmp1 / GOF_PER_SEC;
 737         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 738         correctionPerSec = tmp1;
 739
 740         /*
 741          *  Fill in the SampleRateConverter control block.
 742          */
 743         spin_lock_irqsave(&chip->reg_lock, flags);
 744         snd_cs46xx_poke(chip, BA1_PSRC,
 745           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 746         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 747         spin_unlock_irqrestore(&chip->reg_lock, flags);
 748 }
 749
 750 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 751 {
 752         unsigned long flags;
 753         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 754         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 755         unsigned int frameGroupLength, cnt;
 756
 757         /*
 758          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 759          *  Correct the value if an attempt is made to stray outside that limit.
 760          */
 761         if ((rate * 9) < 48000)
 762                 rate = 48000 / 9;
 763
 764         /*
 765          *  We can not capture at a rate greater than the Input Rate (48000).
 766          *  Return an error if an attempt is made to stray outside that limit.
 767          */
 768         if (rate > 48000)
 769                 rate = 48000;
 770
 771         /*
 772          *  Compute the values used to drive the actual sample rate conversion.
 773          *  The following formulas are being computed, using inline assembly
 774          *  since we need to use 64 bit arithmetic to compute the values:
 775          *
 776          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 777          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 778          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 779          *                                GOF_PER_SEC)
 780          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 781          *                          GOF_PER_SEC * correctionPerGOF
 782          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 783          *
 784          * i.e.
 785          *
 786          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 787          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 788          *     correctionPerGOF:correctionPerSec =
 789          *          dividend:remainder(ulOther / GOF_PER_SEC)
 790          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 791          */
 792
 793         tmp1 = rate << 16;
 794         coeffIncr = tmp1 / 48000;
 795         tmp1 -= coeffIncr * 48000;
 796         tmp1 <<= 7;
 797         coeffIncr <<= 7;
 798         coeffIncr += tmp1 / 48000;
 799         coeffIncr ^= 0xFFFFFFFF;
 800         coeffIncr++;
 801         tmp1 = 48000 << 16;
 802         phiIncr = tmp1 / rate;
 803         tmp1 -= phiIncr * rate;
 804         tmp1 <<= 10;
 805         phiIncr <<= 10;
 806         tmp2 = tmp1 / rate;
 807         phiIncr += tmp2;
 808         tmp1 -= tmp2 * rate;
 809         correctionPerGOF = tmp1 / GOF_PER_SEC;
 810         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 811         correctionPerSec = tmp1;
 812         initialDelay = DIV_ROUND_UP(48000 * 24, rate);
 813
 814         /*
 815          *  Fill in the VariDecimate control block.
 816          */
 817         spin_lock_irqsave(&chip->reg_lock, flags);
 818         snd_cs46xx_poke(chip, BA1_CSRC,
 819                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 820         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 821         snd_cs46xx_poke(chip, BA1_CD,
 822                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 823         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 824         spin_unlock_irqrestore(&chip->reg_lock, flags);
 825
 826         /*
 827          *  Figure out the frame group length for the write back task.  Basically,
 828          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 829          *  the output sample rate.
 830          */
 831         frameGroupLength = 1;
 832         for (cnt = 2; cnt <= 64; cnt *= 2) {
 833                 if (((rate / cnt) * cnt) != rate)
 834                         frameGroupLength *= 2;
 835         }
 836         if (((rate / 3) * 3) != rate) {
 837                 frameGroupLength *= 3;
 838         }
 839         for (cnt = 5; cnt <= 125; cnt *= 5) {
 840                 if (((rate / cnt) * cnt) != rate)
 841                         frameGroupLength *= 5;
 842         }
 843
 844         /*
 845          * Fill in the WriteBack control block.
 846          */
 847         spin_lock_irqsave(&chip->reg_lock, flags);
 848         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 849         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 850         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 851         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 852         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 853         spin_unlock_irqrestore(&chip->reg_lock, flags);
 854 }
 855
 856 /*
 857  *  PCM part
 858  */
 859
 860 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
 861                                      struct snd_pcm_indirect *rec, size_t bytes)
 862 {
 863         struct snd_pcm_runtime *runtime = substream->runtime;
 864         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 865         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 866 }
 867
 868 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
 869 {
 870         struct snd_pcm_runtime *runtime = substream->runtime;
 871         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 872         return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
 873                                                   snd_cs46xx_pb_trans_copy);
 874 }
 875
 876 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
 877                                      struct snd_pcm_indirect *rec, size_t bytes)
 878 {
 879         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 880         struct snd_pcm_runtime *runtime = substream->runtime;
 881         memcpy(runtime->dma_area + rec->sw_data,
 882                chip->capt.hw_buf.area + rec->hw_data, bytes);
 883 }
 884
 885 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
 886 {
 887         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 888         return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
 889                                                  snd_cs46xx_cp_trans_copy);
 890 }
 891
 892 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
 893 {
 894         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 895         size_t ptr;
 896         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 897
 898         if (snd_BUG_ON(!cpcm->pcm_channel))
 899                 return -ENXIO;
 900
 901 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 902         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 903 #else
 904         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 905 #endif
 906         ptr -= cpcm->hw_buf.addr;
 907         return ptr >> cpcm->shift;
 908 }
 909
 910 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
 911 {
 912         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 913         size_t ptr;
 914         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 915
 916 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 917         if (snd_BUG_ON(!cpcm->pcm_channel))
 918                 return -ENXIO;
 919         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 920 #else
 921         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 922 #endif
 923         ptr -= cpcm->hw_buf.addr;
 924         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 925 }
 926
 927 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
 928 {
 929         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 930         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 931         return ptr >> chip->capt.shift;
 932 }
 933
 934 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
 935 {
 936         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 937         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 938         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 939 }
 940
 941 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
 942                                        int cmd)
 943 {
 944         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 945         /*struct snd_pcm_runtime *runtime = substream->runtime;*/
 946         int result = 0;
 947
 948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 949         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 950         if (! cpcm->pcm_channel) {
 951                 return -ENXIO;
 952         }
 953 #endif
 954         switch (cmd) {
 955         case SNDRV_PCM_TRIGGER_START:
 956         case SNDRV_PCM_TRIGGER_RESUME:
 957 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 958                 /* magic value to unmute PCM stream  playback volume */
 959                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 960                                        SCBVolumeCtrl) << 2, 0x80008000);
 961
 962                 if (cpcm->pcm_channel->unlinked)
 963                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 964
 965                 if (substream->runtime->periods != CS46XX_FRAGS)
 966                         snd_cs46xx_playback_transfer(substream);
 967 #else
 968                 spin_lock(&chip->reg_lock);
 969                 if (substream->runtime->periods != CS46XX_FRAGS)
 970                         snd_cs46xx_playback_transfer(substream);
 971                 { unsigned int tmp;
 972                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 973                 tmp &= 0x0000ffff;
 974                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 975                 }
 976                 spin_unlock(&chip->reg_lock);
 977 #endif
 978                 break;
 979         case SNDRV_PCM_TRIGGER_STOP:
 980         case SNDRV_PCM_TRIGGER_SUSPEND:
 981 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 982                 /* magic mute channel */
 983                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 984                                        SCBVolumeCtrl) << 2, 0xffffffff);
 985
 986                 if (!cpcm->pcm_channel->unlinked)
 987                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 988 #else
 989                 spin_lock(&chip->reg_lock);
 990                 { unsigned int tmp;
 991                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 992                 tmp &= 0x0000ffff;
 993                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 994                 }
 995                 spin_unlock(&chip->reg_lock);
 996 #endif
 997                 break;
 998         default:
 999                 result = -EINVAL;
1000                 break;
1001         }
1002
1003         return result;
1004 }
1005
1006 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1007                                       int cmd)
1008 {
1009         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1010         unsigned int tmp;
1011         int result = 0;
1012
1013         spin_lock(&chip->reg_lock);
1014         switch (cmd) {
1015         case SNDRV_PCM_TRIGGER_START:
1016         case SNDRV_PCM_TRIGGER_RESUME:
1017                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1018                 tmp &= 0xffff0000;
1019                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1020                 break;
1021         case SNDRV_PCM_TRIGGER_STOP:
1022         case SNDRV_PCM_TRIGGER_SUSPEND:
1023                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1024                 tmp &= 0xffff0000;
1025                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1026                 break;
1027         default:
1028                 result = -EINVAL;
1029                 break;
1030         }
1031         spin_unlock(&chip->reg_lock);
1032
1033         return result;
1034 }
1035
1036 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1037 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1038                                        int sample_rate)
1039 {
1040
1041         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1042         if ( cpcm->pcm_channel == NULL) {
1043                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1044                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1045                 if (cpcm->pcm_channel == NULL) {
1046                         dev_err(chip->card->dev,
1047                                 "failed to create virtual PCM channel\n");
1048                         return -ENOMEM;
1049                 }
1050                 cpcm->pcm_channel->sample_rate = sample_rate;
1051         } else
1052         /* if sample rate is changed */
1053         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1054                 int unlinked = cpcm->pcm_channel->unlinked;
1055                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1056
1057                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1058                                                                   cpcm->hw_buf.addr,
1059                                                                   cpcm->pcm_channel_id);
1060                 if (!cpcm->pcm_channel) {
1061                         dev_err(chip->card->dev,
1062                                 "failed to re-create virtual PCM channel\n");
1063                         return -ENOMEM;
1064                 }
1065
1066                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1067                 cpcm->pcm_channel->sample_rate = sample_rate;
1068         }
1069
1070         return 0;
1071 }
1072 #endif
1073
1074
1075 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1076                                          struct snd_pcm_hw_params *hw_params)
1077 {
1078         struct snd_pcm_runtime *runtime = substream->runtime;
1079         struct snd_cs46xx_pcm *cpcm;
1080         int err;
1081 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1082         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1083         int sample_rate = params_rate(hw_params);
1084         int period_size = params_period_bytes(hw_params);
1085 #endif
1086         cpcm = runtime->private_data;
1087
1088 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1089         if (snd_BUG_ON(!sample_rate))
1090                 return -ENXIO;
1091
1092         mutex_lock(&chip->spos_mutex);
1093
1094         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1095                 mutex_unlock(&chip->spos_mutex);
1096                 return -ENXIO;
1097         }
1098
1099         snd_BUG_ON(!cpcm->pcm_channel);
1100         if (!cpcm->pcm_channel) {
1101                 mutex_unlock(&chip->spos_mutex);
1102                 return -ENXIO;
1103         }
1104
1105
1106         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1107                  mutex_unlock(&chip->spos_mutex);
1108                  return -EINVAL;
1109          }
1110
1111         dev_dbg(chip->card->dev,
1112                 "period_size (%d), periods (%d) buffer_size(%d)\n",
1113                      period_size, params_periods(hw_params),
1114                      params_buffer_bytes(hw_params));
1115 #endif
1116
1117         if (params_periods(hw_params) == CS46XX_FRAGS) {
1118                 if (runtime->dma_area != cpcm->hw_buf.area)
1119                         snd_pcm_lib_free_pages(substream);
1120                 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf);
1121
1122
1123 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1124                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1125                         substream->ops = &snd_cs46xx_playback_ops;
1126                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1127                         substream->ops = &snd_cs46xx_playback_rear_ops;
1128                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1129                         substream->ops = &snd_cs46xx_playback_clfe_ops;
1130                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1131                         substream->ops = &snd_cs46xx_playback_iec958_ops;
1132                 } else {
1133                         snd_BUG();
1134                 }
1135 #else
1136                 substream->ops = &snd_cs46xx_playback_ops;
1137 #endif
1138
1139         } else {
1140                 if (runtime->dma_area == cpcm->hw_buf.area)
1141                         snd_pcm_set_runtime_buffer(substream, NULL);
1142                 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1143                 if (err < 0) {
1144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1145                         mutex_unlock(&chip->spos_mutex);
1146 #endif
1147                         return err;
1148                 }
1149
1150 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1151                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1152                         substream->ops = &snd_cs46xx_playback_indirect_ops;
1153                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1154                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1155                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1156                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1157                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1158                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1159                 } else {
1160                         snd_BUG();
1161                 }
1162 #else
1163                 substream->ops = &snd_cs46xx_playback_indirect_ops;
1164 #endif
1165
1166         }
1167
1168 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1169         mutex_unlock(&chip->spos_mutex);
1170 #endif
1171
1172         return 0;
1173 }
1174
1175 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1176 {
1177         /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1178         struct snd_pcm_runtime *runtime = substream->runtime;
1179         struct snd_cs46xx_pcm *cpcm;
1180
1181         cpcm = runtime->private_data;
1182
1183         /* if play_back open fails, then this function
1184            is called and cpcm can actually be NULL here */
1185         if (!cpcm) return -ENXIO;
1186
1187         if (runtime->dma_area != cpcm->hw_buf.area)
1188                 snd_pcm_lib_free_pages(substream);
1189
1190         snd_pcm_set_runtime_buffer(substream, NULL);
1191
1192         return 0;
1193 }
1194
1195 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1196 {
1197         unsigned int tmp;
1198         unsigned int pfie;
1199         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1200         struct snd_pcm_runtime *runtime = substream->runtime;
1201         struct snd_cs46xx_pcm *cpcm;
1202
1203         cpcm = runtime->private_data;
1204
1205 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1206         if (snd_BUG_ON(!cpcm->pcm_channel))
1207                 return -ENXIO;
1208
1209         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1210         pfie &= ~0x0000f03f;
1211 #else
1212         /* old dsp */
1213         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1214         pfie &= ~0x0000f03f;
1215 #endif
1216
1217         cpcm->shift = 2;
1218         /* if to convert from stereo to mono */
1219         if (runtime->channels == 1) {
1220                 cpcm->shift--;
1221                 pfie |= 0x00002000;
1222         }
1223         /* if to convert from 8 bit to 16 bit */
1224         if (snd_pcm_format_width(runtime->format) == 8) {
1225                 cpcm->shift--;
1226                 pfie |= 0x00001000;
1227         }
1228         /* if to convert to unsigned */
1229         if (snd_pcm_format_unsigned(runtime->format))
1230                 pfie |= 0x00008000;
1231
1232         /* Never convert byte order when sample stream is 8 bit */
1233         if (snd_pcm_format_width(runtime->format) != 8) {
1234                 /* convert from big endian to little endian */
1235                 if (snd_pcm_format_big_endian(runtime->format))
1236                         pfie |= 0x00004000;
1237         }
1238
1239         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1240         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1241         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1242
1243 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1244
1245         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1246         tmp &= ~0x000003ff;
1247         tmp |= (4 << cpcm->shift) - 1;
1248         /* playback transaction count register */
1249         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1250
1251         /* playback format && interrupt enable */
1252         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1253 #else
1254         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1255         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1256         tmp &= ~0x000003ff;
1257         tmp |= (4 << cpcm->shift) - 1;
1258         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1259         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1260         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1261 #endif
1262
1263         return 0;
1264 }
1265
1266 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1267                                         struct snd_pcm_hw_params *hw_params)
1268 {
1269         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1270         struct snd_pcm_runtime *runtime = substream->runtime;
1271         int err;
1272
1273 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1274         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1275 #endif
1276         if (runtime->periods == CS46XX_FRAGS) {
1277                 if (runtime->dma_area != chip->capt.hw_buf.area)
1278                         snd_pcm_lib_free_pages(substream);
1279                 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1280                 substream->ops = &snd_cs46xx_capture_ops;
1281         } else {
1282                 if (runtime->dma_area == chip->capt.hw_buf.area)
1283                         snd_pcm_set_runtime_buffer(substream, NULL);
1284                 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1285                 if (err < 0)
1286                         return err;
1287                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1294 {
1295         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1296         struct snd_pcm_runtime *runtime = substream->runtime;
1297
1298         if (runtime->dma_area != chip->capt.hw_buf.area)
1299                 snd_pcm_lib_free_pages(substream);
1300         snd_pcm_set_runtime_buffer(substream, NULL);
1301
1302         return 0;
1303 }
1304
1305 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1306 {
1307         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1308         struct snd_pcm_runtime *runtime = substream->runtime;
1309
1310         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1311         chip->capt.shift = 2;
1312         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1313         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1314         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1315         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1316
1317         return 0;
1318 }
1319
1320 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1321 {
1322         struct snd_cs46xx *chip = dev_id;
1323         u32 status1;
1324 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1325         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1326         u32 status2;
1327         int i;
1328         struct snd_cs46xx_pcm *cpcm = NULL;
1329 #endif
1330
1331         /*
1332          *  Read the Interrupt Status Register to clear the interrupt
1333          */
1334         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1335         if ((status1 & 0x7fffffff) == 0) {
1336                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1337                 return IRQ_NONE;
1338         }
1339
1340 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1341         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1342
1343         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1344                 if (i <= 15) {
1345                         if ( status1 & (1 << i) ) {
1346                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1347                                         if (chip->capt.substream)
1348                                                 snd_pcm_period_elapsed(chip->capt.substream);
1349                                 } else {
1350                                         if (ins->pcm_channels[i].active &&
1351                                             ins->pcm_channels[i].private_data &&
1352                                             !ins->pcm_channels[i].unlinked) {
1353                                                 cpcm = ins->pcm_channels[i].private_data;
1354                                                 snd_pcm_period_elapsed(cpcm->substream);
1355                                         }
1356                                 }
1357                         }
1358                 } else {
1359                         if ( status2 & (1 << (i - 16))) {
1360                                 if (ins->pcm_channels[i].active &&
1361                                     ins->pcm_channels[i].private_data &&
1362                                     !ins->pcm_channels[i].unlinked) {
1363                                         cpcm = ins->pcm_channels[i].private_data;
1364                                         snd_pcm_period_elapsed(cpcm->substream);
1365                                 }
1366                         }
1367                 }
1368         }
1369
1370 #else
1371         /* old dsp */
1372         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1373                 if (chip->playback_pcm->substream)
1374                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1375         }
1376         if ((status1 & HISR_VC1) && chip->pcm) {
1377                 if (chip->capt.substream)
1378                         snd_pcm_period_elapsed(chip->capt.substream);
1379         }
1380 #endif
1381
1382         if ((status1 & HISR_MIDI) && chip->rmidi) {
1383                 unsigned char c;
1384
1385                 spin_lock(&chip->reg_lock);
1386                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1387                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1388                         if ((chip->midcr & MIDCR_RIE) == 0)
1389                                 continue;
1390                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1391                 }
1392                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1393                         if ((chip->midcr & MIDCR_TIE) == 0)
1394                                 break;
1395                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1396                                 chip->midcr &= ~MIDCR_TIE;
1397                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1398                                 break;
1399                         }
1400                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1401                 }
1402                 spin_unlock(&chip->reg_lock);
1403         }
1404         /*
1405          *  EOI to the PCI part....reenables interrupts
1406          */
1407         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1408
1409         return IRQ_HANDLED;
1410 }
1411
1412 static const struct snd_pcm_hardware snd_cs46xx_playback =
1413 {
1414         .info =                 (SNDRV_PCM_INFO_MMAP |
1415                                  SNDRV_PCM_INFO_INTERLEAVED |
1416                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1417                                  /*SNDRV_PCM_INFO_RESUME*/ |
1418                                  SNDRV_PCM_INFO_SYNC_APPLPTR),
1419         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1420                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1421                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1422         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1423         .rate_min =             5500,
1424         .rate_max =             48000,
1425         .channels_min =         1,
1426         .channels_max =         2,
1427         .buffer_bytes_max =     (256 * 1024),
1428         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1429         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1430         .periods_min =          CS46XX_FRAGS,
1431         .periods_max =          1024,
1432         .fifo_size =            0,
1433 };
1434
1435 static const struct snd_pcm_hardware snd_cs46xx_capture =
1436 {
1437         .info =                 (SNDRV_PCM_INFO_MMAP |
1438                                  SNDRV_PCM_INFO_INTERLEAVED |
1439                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1440                                  /*SNDRV_PCM_INFO_RESUME*/ |
1441                                  SNDRV_PCM_INFO_SYNC_APPLPTR),
1442         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1443         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1444         .rate_min =             5500,
1445         .rate_max =             48000,
1446         .channels_min =         2,
1447         .channels_max =         2,
1448         .buffer_bytes_max =     (256 * 1024),
1449         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1450         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1451         .periods_min =          CS46XX_FRAGS,
1452         .periods_max =          1024,
1453         .fifo_size =            0,
1454 };
1455
1456 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1457
1458 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1459
1460 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1461         .count = ARRAY_SIZE(period_sizes),
1462         .list = period_sizes,
1463         .mask = 0
1464 };
1465
1466 #endif
1467
1468 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1469 {
1470         kfree(runtime->private_data);
1471 }
1472
1473 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1474 {
1475         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1476         struct snd_cs46xx_pcm * cpcm;
1477         struct snd_pcm_runtime *runtime = substream->runtime;
1478
1479         cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1480         if (cpcm == NULL)
1481                 return -ENOMEM;
1482         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1483                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1484                 kfree(cpcm);
1485                 return -ENOMEM;
1486         }
1487
1488         runtime->hw = snd_cs46xx_playback;
1489         runtime->private_data = cpcm;
1490         runtime->private_free = snd_cs46xx_pcm_free_substream;
1491
1492         cpcm->substream = substream;
1493 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1494         mutex_lock(&chip->spos_mutex);
1495         cpcm->pcm_channel = NULL;
1496         cpcm->pcm_channel_id = pcm_channel_id;
1497
1498
1499         snd_pcm_hw_constraint_list(runtime, 0,
1500                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1501                                    &hw_constraints_period_sizes);
1502
1503         mutex_unlock(&chip->spos_mutex);
1504 #else
1505         chip->playback_pcm = cpcm; /* HACK */
1506 #endif
1507
1508         if (chip->accept_valid)
1509                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1510         chip->active_ctrl(chip, 1);
1511
1512         return 0;
1513 }
1514
1515 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1516 {
1517         dev_dbg(substream->pcm->card->dev, "open front channel\n");
1518         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1519 }
1520
1521 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1522 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1523 {
1524         dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1525         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1526 }
1527
1528 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1529 {
1530         dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1531         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1532 }
1533
1534 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1535 {
1536         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1537
1538         dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1539
1540         mutex_lock(&chip->spos_mutex);
1541         cs46xx_iec958_pre_open (chip);
1542         mutex_unlock(&chip->spos_mutex);
1543
1544         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1545 }
1546
1547 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1548
1549 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1550 {
1551         int err;
1552         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1553
1554         dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1555
1556         err = snd_cs46xx_playback_close(substream);
1557
1558         mutex_lock(&chip->spos_mutex);
1559         cs46xx_iec958_post_close (chip);
1560         mutex_unlock(&chip->spos_mutex);
1561
1562         return err;
1563 }
1564 #endif
1565
1566 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1567 {
1568         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1569
1570         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1571                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1572                 return -ENOMEM;
1573         chip->capt.substream = substream;
1574         substream->runtime->hw = snd_cs46xx_capture;
1575
1576         if (chip->accept_valid)
1577                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1578
1579         chip->active_ctrl(chip, 1);
1580
1581 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1582         snd_pcm_hw_constraint_list(substream->runtime, 0,
1583                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1584                                    &hw_constraints_period_sizes);
1585 #endif
1586         return 0;
1587 }
1588
1589 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1590 {
1591         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1592         struct snd_pcm_runtime *runtime = substream->runtime;
1593         struct snd_cs46xx_pcm * cpcm;
1594
1595         cpcm = runtime->private_data;
1596
1597         /* when playback_open fails, then cpcm can be NULL */
1598         if (!cpcm) return -ENXIO;
1599
1600 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1601         mutex_lock(&chip->spos_mutex);
1602         if (cpcm->pcm_channel) {
1603                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1604                 cpcm->pcm_channel = NULL;
1605         }
1606         mutex_unlock(&chip->spos_mutex);
1607 #else
1608         chip->playback_pcm = NULL;
1609 #endif
1610
1611         cpcm->substream = NULL;
1612         snd_dma_free_pages(&cpcm->hw_buf);
1613         chip->active_ctrl(chip, -1);
1614
1615         return 0;
1616 }
1617
1618 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1619 {
1620         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1621
1622         chip->capt.substream = NULL;
1623         snd_dma_free_pages(&chip->capt.hw_buf);
1624         chip->active_ctrl(chip, -1);
1625
1626         return 0;
1627 }
1628
1629 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1630 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1631         .open =                 snd_cs46xx_playback_open_rear,
1632         .close =                snd_cs46xx_playback_close,
1633         .hw_params =            snd_cs46xx_playback_hw_params,
1634         .hw_free =              snd_cs46xx_playback_hw_free,
1635         .prepare =              snd_cs46xx_playback_prepare,
1636         .trigger =              snd_cs46xx_playback_trigger,
1637         .pointer =              snd_cs46xx_playback_direct_pointer,
1638 };
1639
1640 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1641         .open =                 snd_cs46xx_playback_open_rear,
1642         .close =                snd_cs46xx_playback_close,
1643         .hw_params =            snd_cs46xx_playback_hw_params,
1644         .hw_free =              snd_cs46xx_playback_hw_free,
1645         .prepare =              snd_cs46xx_playback_prepare,
1646         .trigger =              snd_cs46xx_playback_trigger,
1647         .pointer =              snd_cs46xx_playback_indirect_pointer,
1648         .ack =                  snd_cs46xx_playback_transfer,
1649 };
1650
1651 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1652         .open =                 snd_cs46xx_playback_open_clfe,
1653         .close =                snd_cs46xx_playback_close,
1654         .hw_params =            snd_cs46xx_playback_hw_params,
1655         .hw_free =              snd_cs46xx_playback_hw_free,
1656         .prepare =              snd_cs46xx_playback_prepare,
1657         .trigger =              snd_cs46xx_playback_trigger,
1658         .pointer =              snd_cs46xx_playback_direct_pointer,
1659 };
1660
1661 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1662         .open =                 snd_cs46xx_playback_open_clfe,
1663         .close =                snd_cs46xx_playback_close,
1664         .hw_params =            snd_cs46xx_playback_hw_params,
1665         .hw_free =              snd_cs46xx_playback_hw_free,
1666         .prepare =              snd_cs46xx_playback_prepare,
1667         .trigger =              snd_cs46xx_playback_trigger,
1668         .pointer =              snd_cs46xx_playback_indirect_pointer,
1669         .ack =                  snd_cs46xx_playback_transfer,
1670 };
1671
1672 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1673         .open =                 snd_cs46xx_playback_open_iec958,
1674         .close =                snd_cs46xx_playback_close_iec958,
1675         .hw_params =            snd_cs46xx_playback_hw_params,
1676         .hw_free =              snd_cs46xx_playback_hw_free,
1677         .prepare =              snd_cs46xx_playback_prepare,
1678         .trigger =              snd_cs46xx_playback_trigger,
1679         .pointer =              snd_cs46xx_playback_direct_pointer,
1680 };
1681
1682 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1683         .open =                 snd_cs46xx_playback_open_iec958,
1684         .close =                snd_cs46xx_playback_close_iec958,
1685         .hw_params =            snd_cs46xx_playback_hw_params,
1686         .hw_free =              snd_cs46xx_playback_hw_free,
1687         .prepare =              snd_cs46xx_playback_prepare,
1688         .trigger =              snd_cs46xx_playback_trigger,
1689         .pointer =              snd_cs46xx_playback_indirect_pointer,
1690         .ack =                  snd_cs46xx_playback_transfer,
1691 };
1692
1693 #endif
1694
1695 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1696         .open =                 snd_cs46xx_playback_open,
1697         .close =                snd_cs46xx_playback_close,
1698         .hw_params =            snd_cs46xx_playback_hw_params,
1699         .hw_free =              snd_cs46xx_playback_hw_free,
1700         .prepare =              snd_cs46xx_playback_prepare,
1701         .trigger =              snd_cs46xx_playback_trigger,
1702         .pointer =              snd_cs46xx_playback_direct_pointer,
1703 };
1704
1705 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1706         .open =                 snd_cs46xx_playback_open,
1707         .close =                snd_cs46xx_playback_close,
1708         .hw_params =            snd_cs46xx_playback_hw_params,
1709         .hw_free =              snd_cs46xx_playback_hw_free,
1710         .prepare =              snd_cs46xx_playback_prepare,
1711         .trigger =              snd_cs46xx_playback_trigger,
1712         .pointer =              snd_cs46xx_playback_indirect_pointer,
1713         .ack =                  snd_cs46xx_playback_transfer,
1714 };
1715
1716 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1717         .open =                 snd_cs46xx_capture_open,
1718         .close =                snd_cs46xx_capture_close,
1719         .hw_params =            snd_cs46xx_capture_hw_params,
1720         .hw_free =              snd_cs46xx_capture_hw_free,
1721         .prepare =              snd_cs46xx_capture_prepare,
1722         .trigger =              snd_cs46xx_capture_trigger,
1723         .pointer =              snd_cs46xx_capture_direct_pointer,
1724 };
1725
1726 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1727         .open =                 snd_cs46xx_capture_open,
1728         .close =                snd_cs46xx_capture_close,
1729         .hw_params =            snd_cs46xx_capture_hw_params,
1730         .hw_free =              snd_cs46xx_capture_hw_free,
1731         .prepare =              snd_cs46xx_capture_prepare,
1732         .trigger =              snd_cs46xx_capture_trigger,
1733         .pointer =              snd_cs46xx_capture_indirect_pointer,
1734         .ack =                  snd_cs46xx_capture_transfer,
1735 };
1736
1737 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1738 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1739 #else
1740 #define MAX_PLAYBACK_CHANNELS   1
1741 #endif
1742
1743 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1744 {
1745         struct snd_pcm *pcm;
1746         int err;
1747
1748         err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1749         if (err < 0)
1750                 return err;
1751
1752         pcm->private_data = chip;
1753
1754         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1755         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1756
1757         /* global setup */
1758         pcm->info_flags = 0;
1759         strcpy(pcm->name, "CS46xx");
1760         chip->pcm = pcm;
1761
1762         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1763                                               &chip->pci->dev,
1764                                               64*1024, 256*1024);
1765
1766         return 0;
1767 }
1768
1769
1770 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1771 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1772 {
1773         struct snd_pcm *pcm;
1774         int err;
1775
1776         err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1777         if (err < 0)
1778                 return err;
1779
1780         pcm->private_data = chip;
1781
1782         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1783
1784         /* global setup */
1785         pcm->info_flags = 0;
1786         strcpy(pcm->name, "CS46xx - Rear");
1787         chip->pcm_rear = pcm;
1788
1789         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1790                                               &chip->pci->dev,
1791                                               64*1024, 256*1024);
1792
1793         return 0;
1794 }
1795
1796 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1797 {
1798         struct snd_pcm *pcm;
1799         int err;
1800
1801         err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1802         if (err < 0)
1803                 return err;
1804
1805         pcm->private_data = chip;
1806
1807         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1808
1809         /* global setup */
1810         pcm->info_flags = 0;
1811         strcpy(pcm->name, "CS46xx - Center LFE");
1812         chip->pcm_center_lfe = pcm;
1813
1814         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1815                                               &chip->pci->dev,
1816                                               64*1024, 256*1024);
1817
1818         return 0;
1819 }
1820
1821 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1822 {
1823         struct snd_pcm *pcm;
1824         int err;
1825
1826         err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1827         if (err < 0)
1828                 return err;
1829
1830         pcm->private_data = chip;
1831
1832         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1833
1834         /* global setup */
1835         pcm->info_flags = 0;
1836         strcpy(pcm->name, "CS46xx - IEC958");
1837         chip->pcm_iec958 = pcm;
1838
1839         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1840                                               &chip->pci->dev,
1841                                               64*1024, 256*1024);
1842
1843         return 0;
1844 }
1845 #endif
1846
1847 /*
1848  *  Mixer routines
1849  */
1850 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1851 {
1852         struct snd_cs46xx *chip = ac97->private_data;
1853
1854         if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1855                        ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1856                 return;
1857
1858         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1859                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1860                 chip->eapd_switch = NULL;
1861         }
1862         else
1863                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1864 }
1865
1866 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1867                                struct snd_ctl_elem_info *uinfo)
1868 {
1869         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1870         uinfo->count = 2;
1871         uinfo->value.integer.min = 0;
1872         uinfo->value.integer.max = 0x7fff;
1873         return 0;
1874 }
1875
1876 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1877 {
1878         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1879         int reg = kcontrol->private_value;
1880         unsigned int val = snd_cs46xx_peek(chip, reg);
1881         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1882         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1883         return 0;
1884 }
1885
1886 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1887 {
1888         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1889         int reg = kcontrol->private_value;
1890         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1891                             (0xffff - ucontrol->value.integer.value[1]));
1892         unsigned int old = snd_cs46xx_peek(chip, reg);
1893         int change = (old != val);
1894
1895         if (change) {
1896                 snd_cs46xx_poke(chip, reg, val);
1897         }
1898
1899         return change;
1900 }
1901
1902 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1903
1904 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1905 {
1906         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1907
1908         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1909         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1910
1911         return 0;
1912 }
1913
1914 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1915 {
1916         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1917         int change = 0;
1918
1919         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1920             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1921                 cs46xx_dsp_set_dac_volume(chip,
1922                                           ucontrol->value.integer.value[0],
1923                                           ucontrol->value.integer.value[1]);
1924                 change = 1;
1925         }
1926
1927         return change;
1928 }
1929
1930 #if 0
1931 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1932 {
1933         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1934
1935         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1936         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1937         return 0;
1938 }
1939
1940 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1941 {
1942         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1943         int change = 0;
1944
1945         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1946             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1947                 cs46xx_dsp_set_iec958_volume (chip,
1948                                               ucontrol->value.integer.value[0],
1949                                               ucontrol->value.integer.value[1]);
1950                 change = 1;
1951         }
1952
1953         return change;
1954 }
1955 #endif
1956
1957 #define snd_mixer_boolean_info          snd_ctl_boolean_mono_info
1958
1959 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1960                                  struct snd_ctl_elem_value *ucontrol)
1961 {
1962         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1963         int reg = kcontrol->private_value;
1964
1965         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1966                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1967         else
1968                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1969
1970         return 0;
1971 }
1972
1973 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1974                                   struct snd_ctl_elem_value *ucontrol)
1975 {
1976         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1977         int change, res;
1978
1979         switch (kcontrol->private_value) {
1980         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1981                 mutex_lock(&chip->spos_mutex);
1982                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1983                 if (ucontrol->value.integer.value[0] && !change)
1984                         cs46xx_dsp_enable_spdif_out(chip);
1985                 else if (change && !ucontrol->value.integer.value[0])
1986                         cs46xx_dsp_disable_spdif_out(chip);
1987
1988                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1989                 mutex_unlock(&chip->spos_mutex);
1990                 break;
1991         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1992                 change = chip->dsp_spos_instance->spdif_status_in;
1993                 if (ucontrol->value.integer.value[0] && !change) {
1994                         cs46xx_dsp_enable_spdif_in(chip);
1995                         /* restore volume */
1996                 }
1997                 else if (change && !ucontrol->value.integer.value[0])
1998                         cs46xx_dsp_disable_spdif_in(chip);
1999
2000                 res = (change != chip->dsp_spos_instance->spdif_status_in);
2001                 break;
2002         default:
2003                 res = -EINVAL;
2004                 snd_BUG(); /* should never happen ... */
2005         }
2006
2007         return res;
2008 }
2009
2010 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2011                                       struct snd_ctl_elem_value *ucontrol)
2012 {
2013         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2014         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2015
2016         if (ins->adc_input != NULL)
2017                 ucontrol->value.integer.value[0] = 1;
2018         else
2019                 ucontrol->value.integer.value[0] = 0;
2020
2021         return 0;
2022 }
2023
2024 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2025                                       struct snd_ctl_elem_value *ucontrol)
2026 {
2027         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2028         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2029         int change = 0;
2030
2031         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2032                 cs46xx_dsp_enable_adc_capture(chip);
2033                 change = 1;
2034         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2035                 cs46xx_dsp_disable_adc_capture(chip);
2036                 change = 1;
2037         }
2038         return change;
2039 }
2040
2041 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2042                                       struct snd_ctl_elem_value *ucontrol)
2043 {
2044         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2045         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2046
2047         if (ins->pcm_input != NULL)
2048                 ucontrol->value.integer.value[0] = 1;
2049         else
2050                 ucontrol->value.integer.value[0] = 0;
2051
2052         return 0;
2053 }
2054
2055
2056 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2057                                       struct snd_ctl_elem_value *ucontrol)
2058 {
2059         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2060         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2061         int change = 0;
2062
2063         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2064                 cs46xx_dsp_enable_pcm_capture(chip);
2065                 change = 1;
2066         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2067                 cs46xx_dsp_disable_pcm_capture(chip);
2068                 change = 1;
2069         }
2070
2071         return change;
2072 }
2073
2074 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2075                                      struct snd_ctl_elem_value *ucontrol)
2076 {
2077         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2078
2079         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2080
2081         if (val1 & EGPIODR_GPOE0)
2082                 ucontrol->value.integer.value[0] = 1;
2083         else
2084                 ucontrol->value.integer.value[0] = 0;
2085
2086         return 0;
2087 }
2088
2089 /*
2090  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2091  */
2092 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2093                                        struct snd_ctl_elem_value *ucontrol)
2094 {
2095         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2096         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2097         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2098
2099         if (ucontrol->value.integer.value[0]) {
2100                 /* optical is default */
2101                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2102                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2103                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2104                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2105         } else {
2106                 /* coaxial */
2107                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2108                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2109         }
2110
2111         /* checking diff from the EGPIO direction register
2112            should be enough */
2113         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2114 }
2115
2116
2117 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2118 {
2119         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2120         uinfo->count = 1;
2121         return 0;
2122 }
2123
2124 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2125                                         struct snd_ctl_elem_value *ucontrol)
2126 {
2127         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2128         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2129
2130         mutex_lock(&chip->spos_mutex);
2131         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2132         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2133         ucontrol->value.iec958.status[2] = 0;
2134         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2135         mutex_unlock(&chip->spos_mutex);
2136
2137         return 0;
2138 }
2139
2140 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2141                                         struct snd_ctl_elem_value *ucontrol)
2142 {
2143         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2144         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2145         unsigned int val;
2146         int change;
2147
2148         mutex_lock(&chip->spos_mutex);
2149         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2150                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2151                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2152                 /* left and right validity bit */
2153                 (1 << 13) | (1 << 12);
2154
2155
2156         change = (unsigned int)ins->spdif_csuv_default != val;
2157         ins->spdif_csuv_default = val;
2158
2159         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2160                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2161
2162         mutex_unlock(&chip->spos_mutex);
2163
2164         return change;
2165 }
2166
2167 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2168                                      struct snd_ctl_elem_value *ucontrol)
2169 {
2170         ucontrol->value.iec958.status[0] = 0xff;
2171         ucontrol->value.iec958.status[1] = 0xff;
2172         ucontrol->value.iec958.status[2] = 0x00;
2173         ucontrol->value.iec958.status[3] = 0xff;
2174         return 0;
2175 }
2176
2177 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2178                                          struct snd_ctl_elem_value *ucontrol)
2179 {
2180         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2181         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2182
2183         mutex_lock(&chip->spos_mutex);
2184         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2185         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2186         ucontrol->value.iec958.status[2] = 0;
2187         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2188         mutex_unlock(&chip->spos_mutex);
2189
2190         return 0;
2191 }
2192
2193 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2194                                         struct snd_ctl_elem_value *ucontrol)
2195 {
2196         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2197         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2198         unsigned int val;
2199         int change;
2200
2201         mutex_lock(&chip->spos_mutex);
2202         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2203                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2204                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2205                 /* left and right validity bit */
2206                 (1 << 13) | (1 << 12);
2207
2208
2209         change = ins->spdif_csuv_stream != val;
2210         ins->spdif_csuv_stream = val;
2211
2212         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2213                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2214
2215         mutex_unlock(&chip->spos_mutex);
2216
2217         return change;
2218 }
2219
2220 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2221
2222
2223 static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2224 {
2225         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2226         .name = "DAC Volume",
2227         .info = snd_cs46xx_vol_info,
2228 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2229         .get = snd_cs46xx_vol_get,
2230         .put = snd_cs46xx_vol_put,
2231         .private_value = BA1_PVOL,
2232 #else
2233         .get = snd_cs46xx_vol_dac_get,
2234         .put = snd_cs46xx_vol_dac_put,
2235 #endif
2236 },
2237
2238 {
2239         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2240         .name = "ADC Volume",
2241         .info = snd_cs46xx_vol_info,
2242         .get = snd_cs46xx_vol_get,
2243         .put = snd_cs46xx_vol_put,
2244 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2245         .private_value = BA1_CVOL,
2246 #else
2247         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2248 #endif
2249 },
2250 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2251 {
2252         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2253         .name = "ADC Capture Switch",
2254         .info = snd_mixer_boolean_info,
2255         .get = snd_cs46xx_adc_capture_get,
2256         .put = snd_cs46xx_adc_capture_put
2257 },
2258 {
2259         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2260         .name = "DAC Capture Switch",
2261         .info = snd_mixer_boolean_info,
2262         .get = snd_cs46xx_pcm_capture_get,
2263         .put = snd_cs46xx_pcm_capture_put
2264 },
2265 {
2266         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2267         .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2268         .info = snd_mixer_boolean_info,
2269         .get = snd_cs46xx_iec958_get,
2270         .put = snd_cs46xx_iec958_put,
2271         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2272 },
2273 {
2274         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2275         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2276         .info = snd_mixer_boolean_info,
2277         .get = snd_cs46xx_iec958_get,
2278         .put = snd_cs46xx_iec958_put,
2279         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2280 },
2281 #if 0
2282 /* Input IEC958 volume does not work for the moment. (Benny) */
2283 {
2284         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2286         .info = snd_cs46xx_vol_info,
2287         .get = snd_cs46xx_vol_iec958_get,
2288         .put = snd_cs46xx_vol_iec958_put,
2289         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2290 },
2291 #endif
2292 {
2293         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2294         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2295         .info =  snd_cs46xx_spdif_info,
2296         .get =   snd_cs46xx_spdif_default_get,
2297         .put =   snd_cs46xx_spdif_default_put,
2298 },
2299 {
2300         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2301         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2302         .info =  snd_cs46xx_spdif_info,
2303         .get =   snd_cs46xx_spdif_mask_get,
2304         .access = SNDRV_CTL_ELEM_ACCESS_READ
2305 },
2306 {
2307         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2308         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2309         .info =  snd_cs46xx_spdif_info,
2310         .get =   snd_cs46xx_spdif_stream_get,
2311         .put =   snd_cs46xx_spdif_stream_put
2312 },
2313
2314 #endif
2315 };
2316
2317 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2318 /* set primary cs4294 codec into Extended Audio Mode */
2319 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2320                                     struct snd_ctl_elem_value *ucontrol)
2321 {
2322         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2323         unsigned short val;
2324         val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2325         ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2326         return 0;
2327 }
2328
2329 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2330                                     struct snd_ctl_elem_value *ucontrol)
2331 {
2332         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2333         return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2334                                     AC97_CSR_ACMODE, 0x200,
2335                                     ucontrol->value.integer.value[0] ? 0 : 0x200);
2336 }
2337
2338 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2339         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2340         .name = "Duplicate Front",
2341         .info = snd_mixer_boolean_info,
2342         .get = snd_cs46xx_front_dup_get,
2343         .put = snd_cs46xx_front_dup_put,
2344 };
2345 #endif
2346
2347 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2348 /* Only available on the Hercules Game Theater XP soundcard */
2349 static const struct snd_kcontrol_new snd_hercules_controls[] = {
2350 {
2351         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2352         .name = "Optical/Coaxial SPDIF Input Switch",
2353         .info = snd_mixer_boolean_info,
2354         .get = snd_herc_spdif_select_get,
2355         .put = snd_herc_spdif_select_put,
2356 },
2357 };
2358
2359
2360 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2361 {
2362         unsigned long end_time;
2363         int err;
2364
2365         /* reset to defaults */
2366         snd_ac97_write(ac97, AC97_RESET, 0);
2367
2368         /* set the desired CODEC mode */
2369         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2370                 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2371                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2372         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2373                 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2374                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2375         } else {
2376                 snd_BUG(); /* should never happen ... */
2377         }
2378
2379         udelay(50);
2380
2381         /* it's necessary to wait awhile until registers are accessible after RESET */
2382         /* because the PCM or MASTER volume registers can be modified, */
2383         /* the REC_GAIN register is used for tests */
2384         end_time = jiffies + HZ;
2385         do {
2386                 unsigned short ext_mid;
2387
2388                 /* use preliminary reads to settle the communication */
2389                 snd_ac97_read(ac97, AC97_RESET);
2390                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2391                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2392                 /* modem? */
2393                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2394                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2395                         return;
2396
2397                 /* test if we can write to the record gain volume register */
2398                 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2399                 err = snd_ac97_read(ac97, AC97_REC_GAIN);
2400                 if (err == 0x8a05)
2401                         return;
2402
2403                 msleep(10);
2404         } while (time_after_eq(end_time, jiffies));
2405
2406         dev_err(ac97->bus->card->dev,
2407                 "CS46xx secondary codec doesn't respond!\n");
2408 }
2409 #endif
2410
2411 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2412 {
2413         int idx, err;
2414         struct snd_ac97_template ac97;
2415
2416         memset(&ac97, 0, sizeof(ac97));
2417         ac97.private_data = chip;
2418         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2419         ac97.num = codec;
2420         if (chip->amplifier_ctrl == amp_voyetra)
2421                 ac97.scaps = AC97_SCAP_INV_EAPD;
2422
2423         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2424                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2425                 udelay(10);
2426                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2427                         dev_dbg(chip->card->dev,
2428                                 "secondary codec not present\n");
2429                         return -ENXIO;
2430                 }
2431         }
2432
2433         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2434         for (idx = 0; idx < 100; ++idx) {
2435                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2436                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2437                         return err;
2438                 }
2439                 msleep(10);
2440         }
2441         dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2442         return -ENXIO;
2443 }
2444
2445 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2446 {
2447         struct snd_card *card = chip->card;
2448         struct snd_ctl_elem_id id;
2449         int err;
2450         unsigned int idx;
2451         static const struct snd_ac97_bus_ops ops = {
2452 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2453                 .reset = snd_cs46xx_codec_reset,
2454 #endif
2455                 .write = snd_cs46xx_ac97_write,
2456                 .read = snd_cs46xx_ac97_read,
2457         };
2458
2459         /* detect primary codec */
2460         chip->nr_ac97_codecs = 0;
2461         dev_dbg(chip->card->dev, "detecting primary codec\n");
2462         err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2463         if (err < 0)
2464                 return err;
2465
2466         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2467                 return -ENXIO;
2468         chip->nr_ac97_codecs = 1;
2469
2470 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2471         dev_dbg(chip->card->dev, "detecting secondary codec\n");
2472         /* try detect a secondary codec */
2473         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2474                 chip->nr_ac97_codecs = 2;
2475 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2476
2477         /* add cs4630 mixer controls */
2478         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2479                 struct snd_kcontrol *kctl;
2480                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2481                 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2482                         kctl->id.device = spdif_device;
2483                 err = snd_ctl_add(card, kctl);
2484                 if (err < 0)
2485                         return err;
2486         }
2487
2488         /* get EAPD mixer switch (for voyetra hack) */
2489         memset(&id, 0, sizeof(id));
2490         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2491         strcpy(id.name, "External Amplifier");
2492         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2493
2494 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2495         if (chip->nr_ac97_codecs == 1) {
2496                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2497                 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2498                         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2499                         if (err < 0)
2500                                 return err;
2501                         snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2502                                              AC97_CSR_ACMODE, 0x200);
2503                 }
2504         }
2505         /* do soundcard specific mixer setup */
2506         if (chip->mixer_init) {
2507                 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2508                 chip->mixer_init(chip);
2509         }
2510 #endif
2511
2512         /* turn on amplifier */
2513         chip->amplifier_ctrl(chip, 1);
2514
2515         return 0;
2516 }
2517
2518 /*
2519  *  RawMIDI interface
2520  */
2521
2522 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2523 {
2524         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2525         udelay(100);
2526         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2527 }
2528
2529 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2530 {
2531         struct snd_cs46xx *chip = substream->rmidi->private_data;
2532
2533         chip->active_ctrl(chip, 1);
2534         spin_lock_irq(&chip->reg_lock);
2535         chip->uartm |= CS46XX_MODE_INPUT;
2536         chip->midcr |= MIDCR_RXE;
2537         chip->midi_input = substream;
2538         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2539                 snd_cs46xx_midi_reset(chip);
2540         } else {
2541                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2542         }
2543         spin_unlock_irq(&chip->reg_lock);
2544         return 0;
2545 }
2546
2547 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2548 {
2549         struct snd_cs46xx *chip = substream->rmidi->private_data;
2550
2551         spin_lock_irq(&chip->reg_lock);
2552         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2553         chip->midi_input = NULL;
2554         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2555                 snd_cs46xx_midi_reset(chip);
2556         } else {
2557                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2558         }
2559         chip->uartm &= ~CS46XX_MODE_INPUT;
2560         spin_unlock_irq(&chip->reg_lock);
2561         chip->active_ctrl(chip, -1);
2562         return 0;
2563 }
2564
2565 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2566 {
2567         struct snd_cs46xx *chip = substream->rmidi->private_data;
2568
2569         chip->active_ctrl(chip, 1);
2570
2571         spin_lock_irq(&chip->reg_lock);
2572         chip->uartm |= CS46XX_MODE_OUTPUT;
2573         chip->midcr |= MIDCR_TXE;
2574         chip->midi_output = substream;
2575         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2576                 snd_cs46xx_midi_reset(chip);
2577         } else {
2578                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2579         }
2580         spin_unlock_irq(&chip->reg_lock);
2581         return 0;
2582 }
2583
2584 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2585 {
2586         struct snd_cs46xx *chip = substream->rmidi->private_data;
2587
2588         spin_lock_irq(&chip->reg_lock);
2589         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2590         chip->midi_output = NULL;
2591         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2592                 snd_cs46xx_midi_reset(chip);
2593         } else {
2594                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2595         }
2596         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2597         spin_unlock_irq(&chip->reg_lock);
2598         chip->active_ctrl(chip, -1);
2599         return 0;
2600 }
2601
2602 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2603 {
2604         unsigned long flags;
2605         struct snd_cs46xx *chip = substream->rmidi->private_data;
2606
2607         spin_lock_irqsave(&chip->reg_lock, flags);
2608         if (up) {
2609                 if ((chip->midcr & MIDCR_RIE) == 0) {
2610                         chip->midcr |= MIDCR_RIE;
2611                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2612                 }
2613         } else {
2614                 if (chip->midcr & MIDCR_RIE) {
2615                         chip->midcr &= ~MIDCR_RIE;
2616                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2617                 }
2618         }
2619         spin_unlock_irqrestore(&chip->reg_lock, flags);
2620 }
2621
2622 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2623 {
2624         unsigned long flags;
2625         struct snd_cs46xx *chip = substream->rmidi->private_data;
2626         unsigned char byte;
2627
2628         spin_lock_irqsave(&chip->reg_lock, flags);
2629         if (up) {
2630                 if ((chip->midcr & MIDCR_TIE) == 0) {
2631                         chip->midcr |= MIDCR_TIE;
2632                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2633                         while ((chip->midcr & MIDCR_TIE) &&
2634                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2635                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2636                                         chip->midcr &= ~MIDCR_TIE;
2637                                 } else {
2638                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2639                                 }
2640                         }
2641                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2642                 }
2643         } else {
2644                 if (chip->midcr & MIDCR_TIE) {
2645                         chip->midcr &= ~MIDCR_TIE;
2646                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2647                 }
2648         }
2649         spin_unlock_irqrestore(&chip->reg_lock, flags);
2650 }
2651
2652 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2653 {
2654         .open =         snd_cs46xx_midi_output_open,
2655         .close =        snd_cs46xx_midi_output_close,
2656         .trigger =      snd_cs46xx_midi_output_trigger,
2657 };
2658
2659 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2660 {
2661         .open =         snd_cs46xx_midi_input_open,
2662         .close =        snd_cs46xx_midi_input_close,
2663         .trigger =      snd_cs46xx_midi_input_trigger,
2664 };
2665
2666 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2667 {
2668         struct snd_rawmidi *rmidi;
2669         int err;
2670
2671         err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2672         if (err < 0)
2673                 return err;
2674         strcpy(rmidi->name, "CS46XX");
2675         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2676         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2677         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2678         rmidi->private_data = chip;
2679         chip->rmidi = rmidi;
2680         return 0;
2681 }
2682
2683
2684 /*
2685  * gameport interface
2686  */
2687
2688 #if IS_REACHABLE(CONFIG_GAMEPORT)
2689
2690 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2691 {
2692         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2693
2694         if (snd_BUG_ON(!chip))
2695                 return;
2696         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2697 }
2698
2699 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2700 {
2701         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2702
2703         if (snd_BUG_ON(!chip))
2704                 return 0;
2705         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2706 }
2707
2708 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2709 {
2710         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2711         unsigned js1, js2, jst;
2712
2713         if (snd_BUG_ON(!chip))
2714                 return 0;
2715
2716         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2717         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2718         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2719
2720         *buttons = (~jst >> 4) & 0x0F;
2721
2722         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2723         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2724         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2725         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2726
2727         for(jst=0;jst<4;++jst)
2728                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2729         return 0;
2730 }
2731
2732 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2733 {
2734         switch (mode) {
2735         case GAMEPORT_MODE_COOKED:
2736                 return 0;
2737         case GAMEPORT_MODE_RAW:
2738                 return 0;
2739         default:
2740                 return -1;
2741         }
2742         return 0;
2743 }
2744
2745 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2746 {
2747         struct gameport *gp;
2748
2749         chip->gameport = gp = gameport_allocate_port();
2750         if (!gp) {
2751                 dev_err(chip->card->dev,
2752                         "cannot allocate memory for gameport\n");
2753                 return -ENOMEM;
2754         }
2755
2756         gameport_set_name(gp, "CS46xx Gameport");
2757         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2758         gameport_set_dev_parent(gp, &chip->pci->dev);
2759         gameport_set_port_data(gp, chip);
2760
2761         gp->open = snd_cs46xx_gameport_open;
2762         gp->read = snd_cs46xx_gameport_read;
2763         gp->trigger = snd_cs46xx_gameport_trigger;
2764         gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2765
2766         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2767         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2768
2769         gameport_register_port(gp);
2770
2771         return 0;
2772 }
2773
2774 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2775 {
2776         if (chip->gameport) {
2777                 gameport_unregister_port(chip->gameport);
2778                 chip->gameport = NULL;
2779         }
2780 }
2781 #else
2782 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2783 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2784 #endif /* CONFIG_GAMEPORT */
2785
2786 #ifdef CONFIG_SND_PROC_FS
2787 /*
2788  *  proc interface
2789  */
2790
2791 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2792                                   void *file_private_data,
2793                                   struct file *file, char __user *buf,
2794                                   size_t count, loff_t pos)
2795 {
2796         struct snd_cs46xx_region *region = entry->private_data;
2797
2798         if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2799                 return -EFAULT;
2800         return count;
2801 }
2802
2803 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2804         .read = snd_cs46xx_io_read,
2805 };
2806
2807 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2808 {
2809         struct snd_info_entry *entry;
2810         int idx;
2811
2812         for (idx = 0; idx < 5; idx++) {
2813                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2814                 if (! snd_card_proc_new(card, region->name, &entry)) {
2815                         entry->content = SNDRV_INFO_CONTENT_DATA;
2816                         entry->private_data = chip;
2817                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2818                         entry->size = region->size;
2819                         entry->mode = S_IFREG | 0400;
2820                 }
2821         }
2822 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2823         cs46xx_dsp_proc_init(card, chip);
2824 #endif
2825         return 0;
2826 }
2827
2828 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2829 {
2830 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2831         cs46xx_dsp_proc_done(chip);
2832 #endif
2833         return 0;
2834 }
2835 #else /* !CONFIG_SND_PROC_FS */
2836 #define snd_cs46xx_proc_init(card, chip)
2837 #define snd_cs46xx_proc_done(chip)
2838 #endif
2839
2840 /*
2841  * stop the h/w
2842  */
2843 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2844 {
2845         unsigned int tmp;
2846
2847         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2848         tmp &= ~0x0000f03f;
2849         tmp |=  0x00000010;
2850         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2851
2852         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2853         tmp &= ~0x0000003f;
2854         tmp |=  0x00000011;
2855         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2856
2857         /*
2858          *  Stop playback DMA.
2859          */
2860         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2861         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2862
2863         /*
2864          *  Stop capture DMA.
2865          */
2866         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2867         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2868
2869         /*
2870          *  Reset the processor.
2871          */
2872         snd_cs46xx_reset(chip);
2873
2874         snd_cs46xx_proc_stop(chip);
2875
2876         /*
2877          *  Power down the PLL.
2878          */
2879         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2880
2881         /*
2882          *  Turn off the Processor by turning off the software clock enable flag in
2883          *  the clock control register.
2884          */
2885         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2886         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2887 }
2888
2889
2890 static void snd_cs46xx_free(struct snd_card *card)
2891 {
2892         struct snd_cs46xx *chip = card->private_data;
2893 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2894         int idx;
2895 #endif
2896
2897         if (chip->active_ctrl)
2898                 chip->active_ctrl(chip, 1);
2899
2900         snd_cs46xx_remove_gameport(chip);
2901
2902         if (chip->amplifier_ctrl)
2903                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2904
2905         snd_cs46xx_proc_done(chip);
2906
2907         snd_cs46xx_hw_stop(chip);
2908
2909         if (chip->active_ctrl)
2910                 chip->active_ctrl(chip, -chip->amplifier);
2911
2912 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2913         if (chip->dsp_spos_instance) {
2914                 cs46xx_dsp_spos_destroy(chip);
2915                 chip->dsp_spos_instance = NULL;
2916         }
2917         for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2918                 free_module_desc(chip->modules[idx]);
2919 #else
2920         vfree(chip->ba1);
2921 #endif
2922 }
2923
2924 /*
2925  *  initialize chip
2926  */
2927 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2928 {
2929         int timeout;
2930
2931         /*
2932          *  First, blast the clock control register to zero so that the PLL starts
2933          *  out in a known state, and blast the master serial port control register
2934          *  to zero so that the serial ports also start out in a known state.
2935          */
2936         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2937         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2938
2939         /*
2940          *  If we are in AC97 mode, then we must set the part to a host controlled
2941          *  AC-link.  Otherwise, we won't be able to bring up the link.
2942          */
2943 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2944         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2945                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2946         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2947 #else
2948         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2949 #endif
2950
2951         /*
2952          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2953          *  spec) and then drive it high.  This is done for non AC97 modes since
2954          *  there might be logic external to the CS461x that uses the ARST# line
2955          *  for a reset.
2956          */
2957         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2958 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2959         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2960 #endif
2961         udelay(50);
2962         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2963 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2964         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2965 #endif
2966
2967         /*
2968          *  The first thing we do here is to enable sync generation.  As soon
2969          *  as we start receiving bit clock, we'll start producing the SYNC
2970          *  signal.
2971          */
2972         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2974         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2975 #endif
2976
2977         /*
2978          *  Now wait for a short while to allow the AC97 part to start
2979          *  generating bit clock (so we don't try to start the PLL without an
2980          *  input clock).
2981          */
2982         mdelay(10);
2983
2984         /*
2985          *  Set the serial port timing configuration, so that
2986          *  the clock control circuit gets its clock from the correct place.
2987          */
2988         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2989
2990         /*
2991          *  Write the selected clock control setup to the hardware.  Do not turn on
2992          *  SWCE yet (if requested), so that the devices clocked by the output of
2993          *  PLL are not clocked until the PLL is stable.
2994          */
2995         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2996         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2997         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2998
2999         /*
3000          *  Power up the PLL.
3001          */
3002         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3003
3004         /*
3005          *  Wait until the PLL has stabilized.
3006          */
3007         msleep(100);
3008
3009         /*
3010          *  Turn on clocking of the core so that we can setup the serial ports.
3011          */
3012         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3013
3014         /*
3015          * Enable FIFO  Host Bypass
3016          */
3017         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3018
3019         /*
3020          *  Fill the serial port FIFOs with silence.
3021          */
3022         snd_cs46xx_clear_serial_FIFOs(chip);
3023
3024         /*
3025          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3026          */
3027         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3028
3029         /*
3030          *  Write the serial port configuration to the part.  The master
3031          *  enable bit is not set until all other values have been written.
3032          */
3033         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3034         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3035         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3036
3037
3038 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3039         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3040         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3041         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3042         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3043         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3044 #endif
3045
3046         mdelay(5);
3047
3048
3049         /*
3050          * Wait for the codec ready signal from the AC97 codec.
3051          */
3052         timeout = 150;
3053         while (timeout-- > 0) {
3054                 /*
3055                  *  Read the AC97 status register to see if we've seen a CODEC READY
3056                  *  signal from the AC97 codec.
3057                  */
3058                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3059                         goto ok1;
3060                 msleep(10);
3061         }
3062
3063
3064         dev_err(chip->card->dev,
3065                 "create - never read codec ready from AC'97\n");
3066         dev_err(chip->card->dev,
3067                 "it is not probably bug, try to use CS4236 driver\n");
3068         return -EIO;
3069  ok1:
3070 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3071         {
3072                 int count;
3073                 for (count = 0; count < 150; count++) {
3074                         /* First, we want to wait for a short time. */
3075                         udelay(25);
3076
3077                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3078                                 break;
3079                 }
3080
3081                 /*
3082                  *  Make sure CODEC is READY.
3083                  */
3084                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3085                         dev_dbg(chip->card->dev,
3086                                 "never read card ready from secondary AC'97\n");
3087         }
3088 #endif
3089
3090         /*
3091          *  Assert the vaid frame signal so that we can start sending commands
3092          *  to the AC97 codec.
3093          */
3094         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3095 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3096         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3097 #endif
3098
3099
3100         /*
3101          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3102          *  the codec is pumping ADC data across the AC-link.
3103          */
3104         timeout = 150;
3105         while (timeout-- > 0) {
3106                 /*
3107                  *  Read the input slot valid register and see if input slots 3 and
3108                  *  4 are valid yet.
3109                  */
3110                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3111                         goto ok2;
3112                 msleep(10);
3113         }
3114
3115 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3116         dev_err(chip->card->dev,
3117                 "create - never read ISV3 & ISV4 from AC'97\n");
3118         return -EIO;
3119 #else
3120         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3121            Reloading the driver may help, if there's other soundcards
3122            with the same problem I would like to know. (Benny) */
3123
3124         dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3125         dev_err(chip->card->dev,
3126                 "Try reloading the ALSA driver, if you find something\n");
3127         dev_err(chip->card->dev,
3128                 "broken or not working on your soundcard upon\n");
3129         dev_err(chip->card->dev,
3130                 "this message please report to alsa-devel@alsa-project.org\n");
3131
3132         return -EIO;
3133 #endif
3134  ok2:
3135
3136         /*
3137          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3138          *  commense the transfer of digital audio data to the AC97 codec.
3139          */
3140
3141         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3142
3143
3144         /*
3145          *  Power down the DAC and ADC.  We will power them up (if) when we need
3146          *  them.
3147          */
3148         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3149
3150         /*
3151          *  Turn off the Processor by turning off the software clock enable flag in
3152          *  the clock control register.
3153          */
3154         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3155         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3156
3157         return 0;
3158 }
3159
3160 /*
3161  *  start and load DSP
3162  */
3163
3164 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3165 {
3166         unsigned int tmp;
3167
3168         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3169
3170         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3171         tmp &= ~0x0000f03f;
3172         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3173
3174         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3175         tmp &= ~0x0000003f;
3176         tmp |=  0x00000001;
3177         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3178 }
3179
3180 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3181 {
3182         unsigned int tmp;
3183 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3184         int i;
3185 #endif
3186         int err;
3187
3188         /*
3189          *  Reset the processor.
3190          */
3191         snd_cs46xx_reset(chip);
3192         /*
3193          *  Download the image to the processor.
3194          */
3195 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3196         for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3197                 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3198                 if (err < 0) {
3199                         dev_err(chip->card->dev, "firmware load error [%s]\n",
3200                                    module_names[i]);
3201                         return err;
3202                 }
3203                 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3204                 if (err < 0) {
3205                         dev_err(chip->card->dev, "image download error [%s]\n",
3206                                    module_names[i]);
3207                         return err;
3208                 }
3209         }
3210
3211         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3212                 return -EIO;
3213 #else
3214         err = load_firmware(chip);
3215         if (err < 0)
3216                 return err;
3217
3218         /* old image */
3219         err = snd_cs46xx_download_image(chip);
3220         if (err < 0) {
3221                 dev_err(chip->card->dev, "image download error\n");
3222                 return err;
3223         }
3224
3225         /*
3226          *  Stop playback DMA.
3227          */
3228         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3229         chip->play_ctl = tmp & 0xffff0000;
3230         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3231 #endif
3232
3233         /*
3234          *  Stop capture DMA.
3235          */
3236         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3237         chip->capt.ctl = tmp & 0x0000ffff;
3238         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3239
3240         mdelay(5);
3241
3242         snd_cs46xx_set_play_sample_rate(chip, 8000);
3243         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3244
3245         snd_cs46xx_proc_start(chip);
3246
3247         cs46xx_enable_stream_irqs(chip);
3248
3249 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3250         /* set the attenuation to 0dB */
3251         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3252         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3253 #endif
3254
3255         return 0;
3256 }
3257
3258
3259 /*
3260  *      AMP control - null AMP
3261  */
3262
3263 static void amp_none(struct snd_cs46xx *chip, int change)
3264 {
3265 }
3266
3267 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3268 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3269 {
3270
3271         u32 idx, valid_slots,tmp,powerdown = 0;
3272         u16 modem_power,pin_config,logic_type;
3273
3274         dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3275
3276         /*
3277          *  See if the devices are powered down.  If so, we must power them up first
3278          *  or they will not respond.
3279          */
3280         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3281
3282         if (!(tmp & CLKCR1_SWCE)) {
3283                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3284                 powerdown = 1;
3285         }
3286
3287         /*
3288          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3289          * stuff.
3290          */
3291         if(chip->nr_ac97_codecs != 2) {
3292                 dev_err(chip->card->dev,
3293                         "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3294                 return -EINVAL;
3295         }
3296
3297         modem_power = snd_cs46xx_codec_read (chip,
3298                                              AC97_EXTENDED_MSTATUS,
3299                                              CS46XX_SECONDARY_CODEC_INDEX);
3300         modem_power &=0xFEFF;
3301
3302         snd_cs46xx_codec_write(chip,
3303                                AC97_EXTENDED_MSTATUS, modem_power,
3304                                CS46XX_SECONDARY_CODEC_INDEX);
3305
3306         /*
3307          * Set GPIO pin's 7 and 8 so that they are configured for output.
3308          */
3309         pin_config = snd_cs46xx_codec_read (chip,
3310                                             AC97_GPIO_CFG,
3311                                             CS46XX_SECONDARY_CODEC_INDEX);
3312         pin_config &=0x27F;
3313
3314         snd_cs46xx_codec_write(chip,
3315                                AC97_GPIO_CFG, pin_config,
3316                                CS46XX_SECONDARY_CODEC_INDEX);
3317
3318         /*
3319          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3320          */
3321
3322         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3323                                            CS46XX_SECONDARY_CODEC_INDEX);
3324         logic_type &=0x27F;
3325
3326         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3327                                 CS46XX_SECONDARY_CODEC_INDEX);
3328
3329         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3330         valid_slots |= 0x200;
3331         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3332
3333         if ( cs46xx_wait_for_fifo(chip,1) ) {
3334                 dev_dbg(chip->card->dev, "FIFO is busy\n");
3335
3336           return -EINVAL;
3337         }
3338
3339         /*
3340          * Fill slots 12 with the correct value for the GPIO pins.
3341          */
3342         for(idx = 0x90; idx <= 0x9F; idx++) {
3343                 /*
3344                  * Initialize the fifo so that bits 7 and 8 are on.
3345                  *
3346                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3347                  * the left.  0x1800 corresponds to bits 7 and 8.
3348                  */
3349                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3350
3351                 /*
3352                  * Wait for command to complete
3353                  */
3354                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3355                         dev_dbg(chip->card->dev,
3356                                 "failed waiting for FIFO at addr (%02X)\n",
3357                                 idx);
3358
3359                         return -EINVAL;
3360                 }
3361
3362                 /*
3363                  * Write the serial port FIFO index.
3364                  */
3365                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3366
3367                 /*
3368                  * Tell the serial port to load the new value into the FIFO location.
3369                  */
3370                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3371         }
3372
3373         /* wait for last command to complete */
3374         cs46xx_wait_for_fifo(chip,200);
3375
3376         /*
3377          *  Now, if we powered up the devices, then power them back down again.
3378          *  This is kinda ugly, but should never happen.
3379          */
3380         if (powerdown)
3381                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3382
3383         return 0;
3384 }
3385 #endif
3386
3387 /*
3388  *      Crystal EAPD mode
3389  */
3390
3391 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3392 {
3393         /* Manage the EAPD bit on the Crystal 4297
3394            and the Analog AD1885 */
3395
3396 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3397         int old = chip->amplifier;
3398 #endif
3399         int oval, val;
3400
3401         chip->amplifier += change;
3402         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3403                                      CS46XX_PRIMARY_CODEC_INDEX);
3404         val = oval;
3405         if (chip->amplifier) {
3406                 /* Turn the EAPD amp on */
3407                 val |= 0x8000;
3408         } else {
3409                 /* Turn the EAPD amp off */
3410                 val &= ~0x8000;
3411         }
3412         if (val != oval) {
3413                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3414                                        CS46XX_PRIMARY_CODEC_INDEX);
3415                 if (chip->eapd_switch)
3416                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3417                                        &chip->eapd_switch->id);
3418         }
3419
3420 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3421         if (chip->amplifier && !old) {
3422                 voyetra_setup_eapd_slot(chip);
3423         }
3424 #endif
3425 }
3426
3427 static void hercules_init(struct snd_cs46xx *chip)
3428 {
3429         /* default: AMP off, and SPDIF input optical */
3430         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3431         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3432 }
3433
3434
3435 /*
3436  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3437  */
3438 static void amp_hercules(struct snd_cs46xx *chip, int change)
3439 {
3440         int old = chip->amplifier;
3441         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3442         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3443
3444         chip->amplifier += change;
3445         if (chip->amplifier && !old) {
3446                 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3447
3448                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3449                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3450                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3451                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3452         } else if (old && !chip->amplifier) {
3453                 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3454                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3455                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3456         }
3457 }
3458
3459 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3460 {
3461         dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3462
3463         /* Enable SPDIF out */
3464         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3465         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3466 }
3467
3468 static void hercules_mixer_init (struct snd_cs46xx *chip)
3469 {
3470 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3471         unsigned int idx;
3472         int err;
3473         struct snd_card *card = chip->card;
3474 #endif
3475
3476         /* set EGPIO to default */
3477         hercules_init(chip);
3478
3479         dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3480
3481 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3482         if (chip->in_suspend)
3483                 return;
3484
3485         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3486                 struct snd_kcontrol *kctl;
3487
3488                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3489                 err = snd_ctl_add(card, kctl);
3490                 if (err < 0) {
3491                         dev_err(card->dev,
3492                                 "failed to initialize Hercules mixer (%d)\n",
3493                                 err);
3494                         break;
3495                 }
3496         }
3497 #endif
3498 }
3499
3500
3501 #if 0
3502 /*
3503  *      Untested
3504  */
3505
3506 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3507 {
3508         chip->amplifier += change;
3509
3510         if (chip->amplifier) {
3511                 /* Switch the GPIO pins 7 and 8 to open drain */
3512                 snd_cs46xx_codec_write(chip, 0x4C,
3513                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3514                 snd_cs46xx_codec_write(chip, 0x4E,
3515                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3516                 /* Now wake the AMP (this might be backwards) */
3517                 snd_cs46xx_codec_write(chip, 0x54,
3518                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3519         } else {
3520                 snd_cs46xx_codec_write(chip, 0x54,
3521                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3522         }
3523 }
3524 #endif
3525
3526
3527 /*
3528  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3529  *      whenever we need to beat on the chip.
3530  *
3531  *      The original idea and code for this hack comes from David Kaiser at
3532  *      Linuxcare. Perhaps one day Crystal will document their chips well
3533  *      enough to make them useful.
3534  */
3535
3536 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3537 {
3538         u16 control, nval;
3539
3540         if (!chip->acpi_port)
3541                 return;
3542
3543         chip->amplifier += change;
3544
3545         /* Read ACPI port */
3546         nval = control = inw(chip->acpi_port + 0x10);
3547
3548         /* Flip CLKRUN off while running */
3549         if (! chip->amplifier)
3550                 nval |= 0x2000;
3551         else
3552                 nval &= ~0x2000;
3553         if (nval != control)
3554                 outw(nval, chip->acpi_port + 0x10);
3555 }
3556
3557
3558 /*
3559  * detect intel piix4
3560  */
3561 static void clkrun_init(struct snd_cs46xx *chip)
3562 {
3563         struct pci_dev *pdev;
3564         u8 pp;
3565
3566         chip->acpi_port = 0;
3567
3568         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3569                 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3570         if (pdev == NULL)
3571                 return;         /* Not a thinkpad thats for sure */
3572
3573         /* Find the control port */
3574         pci_read_config_byte(pdev, 0x41, &pp);
3575         chip->acpi_port = pp << 8;
3576         pci_dev_put(pdev);
3577 }
3578
3579
3580 /*
3581  * Card subid table
3582  */
3583
3584 struct cs_card_type
3585 {
3586         u16 vendor;
3587         u16 id;
3588         char *name;
3589         void (*init)(struct snd_cs46xx *);
3590         void (*amp)(struct snd_cs46xx *, int);
3591         void (*active)(struct snd_cs46xx *, int);
3592         void (*mixer_init)(struct snd_cs46xx *);
3593 };
3594
3595 static struct cs_card_type cards[] = {
3596         {
3597                 .vendor = 0x1489,
3598                 .id = 0x7001,
3599                 .name = "Genius Soundmaker 128 value",
3600                 /* nothing special */
3601         },
3602         {
3603                 .vendor = 0x5053,
3604                 .id = 0x3357,
3605                 .name = "Voyetra",
3606                 .amp = amp_voyetra,
3607                 .mixer_init = voyetra_mixer_init,
3608         },
3609         {
3610                 .vendor = 0x1071,
3611                 .id = 0x6003,
3612                 .name = "Mitac MI6020/21",
3613                 .amp = amp_voyetra,
3614         },
3615         /* Hercules Game Theatre XP */
3616         {
3617                 .vendor = 0x14af, /* Guillemot Corporation */
3618                 .id = 0x0050,
3619                 .name = "Hercules Game Theatre XP",
3620                 .amp = amp_hercules,
3621                 .mixer_init = hercules_mixer_init,
3622         },
3623         {
3624                 .vendor = 0x1681,
3625                 .id = 0x0050,
3626                 .name = "Hercules Game Theatre XP",
3627                 .amp = amp_hercules,
3628                 .mixer_init = hercules_mixer_init,
3629         },
3630         {
3631                 .vendor = 0x1681,
3632                 .id = 0x0051,
3633                 .name = "Hercules Game Theatre XP",
3634                 .amp = amp_hercules,
3635                 .mixer_init = hercules_mixer_init,
3636
3637         },
3638         {
3639                 .vendor = 0x1681,
3640                 .id = 0x0052,
3641                 .name = "Hercules Game Theatre XP",
3642                 .amp = amp_hercules,
3643                 .mixer_init = hercules_mixer_init,
3644         },
3645         {
3646                 .vendor = 0x1681,
3647                 .id = 0x0053,
3648                 .name = "Hercules Game Theatre XP",
3649                 .amp = amp_hercules,
3650                 .mixer_init = hercules_mixer_init,
3651         },
3652         {
3653                 .vendor = 0x1681,
3654                 .id = 0x0054,
3655                 .name = "Hercules Game Theatre XP",
3656                 .amp = amp_hercules,
3657                 .mixer_init = hercules_mixer_init,
3658         },
3659         /* Herculess Fortissimo */
3660         {
3661                 .vendor = 0x1681,
3662                 .id = 0xa010,
3663                 .name = "Hercules Gamesurround Fortissimo II",
3664         },
3665         {
3666                 .vendor = 0x1681,
3667                 .id = 0xa011,
3668                 .name = "Hercules Gamesurround Fortissimo III 7.1",
3669         },
3670         /* Teratec */
3671         {
3672                 .vendor = 0x153b,
3673                 .id = 0x112e,
3674                 .name = "Terratec DMX XFire 1024",
3675         },
3676         {
3677                 .vendor = 0x153b,
3678                 .id = 0x1136,
3679                 .name = "Terratec SiXPack 5.1",
3680         },
3681         /* Not sure if the 570 needs the clkrun hack */
3682         {
3683                 .vendor = PCI_VENDOR_ID_IBM,
3684                 .id = 0x0132,
3685                 .name = "Thinkpad 570",
3686                 .init = clkrun_init,
3687                 .active = clkrun_hack,
3688         },
3689         {
3690                 .vendor = PCI_VENDOR_ID_IBM,
3691                 .id = 0x0153,
3692                 .name = "Thinkpad 600X/A20/T20",
3693                 .init = clkrun_init,
3694                 .active = clkrun_hack,
3695         },
3696         {
3697                 .vendor = PCI_VENDOR_ID_IBM,
3698                 .id = 0x1010,
3699                 .name = "Thinkpad 600E (unsupported)",
3700         },
3701         {} /* terminator */
3702 };
3703
3704
3705 /*
3706  * APM support
3707  */
3708 #ifdef CONFIG_PM_SLEEP
3709 static const unsigned int saved_regs[] = {
3710         BA0_ACOSV,
3711         /*BA0_ASER_FADDR,*/
3712         BA0_ASER_MASTER,
3713         BA1_PVOL,
3714         BA1_CVOL,
3715 };
3716
3717 static int snd_cs46xx_suspend(struct device *dev)
3718 {
3719         struct snd_card *card = dev_get_drvdata(dev);
3720         struct snd_cs46xx *chip = card->private_data;
3721         int i, amp_saved;
3722
3723         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3724         chip->in_suspend = 1;
3725         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3726         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3727
3728         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3729         snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3730
3731         /* save some registers */
3732         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3733                 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3734
3735         amp_saved = chip->amplifier;
3736         /* turn off amp */
3737         chip->amplifier_ctrl(chip, -chip->amplifier);
3738         snd_cs46xx_hw_stop(chip);
3739         /* disable CLKRUN */
3740         chip->active_ctrl(chip, -chip->amplifier);
3741         chip->amplifier = amp_saved; /* restore the status */
3742         return 0;
3743 }
3744
3745 static int snd_cs46xx_resume(struct device *dev)
3746 {
3747         struct snd_card *card = dev_get_drvdata(dev);
3748         struct snd_cs46xx *chip = card->private_data;
3749         int amp_saved;
3750 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3751         int i;
3752 #endif
3753         unsigned int tmp;
3754
3755         amp_saved = chip->amplifier;
3756         chip->amplifier = 0;
3757         chip->active_ctrl(chip, 1); /* force to on */
3758
3759         snd_cs46xx_chip_init(chip);
3760
3761         snd_cs46xx_reset(chip);
3762 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3763         cs46xx_dsp_resume(chip);
3764         /* restore some registers */
3765         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3766                 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3767 #else
3768         snd_cs46xx_download_image(chip);
3769 #endif
3770
3771 #if 0
3772         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3773                                chip->ac97_general_purpose);
3774         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3775                                chip->ac97_powerdown);
3776         mdelay(10);
3777         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3778                                chip->ac97_powerdown);
3779         mdelay(5);
3780 #endif
3781
3782         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3783         snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3784
3785         /*
3786          *  Stop capture DMA.
3787          */
3788         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3789         chip->capt.ctl = tmp & 0x0000ffff;
3790         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3791
3792         mdelay(5);
3793
3794         /* reset playback/capture */
3795         snd_cs46xx_set_play_sample_rate(chip, 8000);
3796         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3797         snd_cs46xx_proc_start(chip);
3798
3799         cs46xx_enable_stream_irqs(chip);
3800
3801         if (amp_saved)
3802                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3803         else
3804                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3805         chip->amplifier = amp_saved;
3806         chip->in_suspend = 0;
3807         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3808         return 0;
3809 }
3810
3811 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3812 #endif /* CONFIG_PM_SLEEP */
3813
3814
3815 /*
3816  */
3817
3818 int snd_cs46xx_create(struct snd_card *card,
3819                       struct pci_dev *pci,
3820                       int external_amp, int thinkpad)
3821 {
3822         struct snd_cs46xx *chip = card->private_data;
3823         int err, idx;
3824         struct snd_cs46xx_region *region;
3825         struct cs_card_type *cp;
3826         u16 ss_card, ss_vendor;
3827
3828         /* enable PCI device */
3829         err = pcim_enable_device(pci);
3830         if (err < 0)
3831                 return err;
3832
3833         spin_lock_init(&chip->reg_lock);
3834 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3835         mutex_init(&chip->spos_mutex);
3836 #endif
3837         chip->card = card;
3838         chip->pci = pci;
3839         chip->irq = -1;
3840
3841         err = pci_request_regions(pci, "CS46xx");
3842         if (err < 0)
3843                 return err;
3844         chip->ba0_addr = pci_resource_start(pci, 0);
3845         chip->ba1_addr = pci_resource_start(pci, 1);
3846         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3847             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3848                 dev_err(chip->card->dev,
3849                         "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3850                            chip->ba0_addr, chip->ba1_addr);
3851                 return -ENOMEM;
3852         }
3853
3854         region = &chip->region.name.ba0;
3855         strcpy(region->name, "CS46xx_BA0");
3856         region->base = chip->ba0_addr;
3857         region->size = CS46XX_BA0_SIZE;
3858
3859         region = &chip->region.name.data0;
3860         strcpy(region->name, "CS46xx_BA1_data0");
3861         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3862         region->size = CS46XX_BA1_DATA0_SIZE;
3863
3864         region = &chip->region.name.data1;
3865         strcpy(region->name, "CS46xx_BA1_data1");
3866         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3867         region->size = CS46XX_BA1_DATA1_SIZE;
3868
3869         region = &chip->region.name.pmem;
3870         strcpy(region->name, "CS46xx_BA1_pmem");
3871         region->base = chip->ba1_addr + BA1_SP_PMEM;
3872         region->size = CS46XX_BA1_PRG_SIZE;
3873
3874         region = &chip->region.name.reg;
3875         strcpy(region->name, "CS46xx_BA1_reg");
3876         region->base = chip->ba1_addr + BA1_SP_REG;
3877         region->size = CS46XX_BA1_REG_SIZE;
3878
3879         /* set up amp and clkrun hack */
3880         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3881         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3882
3883         for (cp = &cards[0]; cp->name; cp++) {
3884                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3885                         dev_dbg(chip->card->dev, "hack for %s enabled\n",
3886                                 cp->name);
3887
3888                         chip->amplifier_ctrl = cp->amp;
3889                         chip->active_ctrl = cp->active;
3890                         chip->mixer_init = cp->mixer_init;
3891
3892                         if (cp->init)
3893                                 cp->init(chip);
3894                         break;
3895                 }
3896         }
3897
3898         if (external_amp) {
3899                 dev_info(chip->card->dev,
3900                          "Crystal EAPD support forced on.\n");
3901                 chip->amplifier_ctrl = amp_voyetra;
3902         }
3903
3904         if (thinkpad) {
3905                 dev_info(chip->card->dev,
3906                          "Activating CLKRUN hack for Thinkpad.\n");
3907                 chip->active_ctrl = clkrun_hack;
3908                 clkrun_init(chip);
3909         }
3910
3911         if (chip->amplifier_ctrl == NULL)
3912                 chip->amplifier_ctrl = amp_none;
3913         if (chip->active_ctrl == NULL)
3914                 chip->active_ctrl = amp_none;
3915
3916         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3917
3918         pci_set_master(pci);
3919
3920         for (idx = 0; idx < 5; idx++) {
3921                 region = &chip->region.idx[idx];
3922                 region->remap_addr = devm_ioremap(&pci->dev, region->base,
3923                                                   region->size);
3924                 if (region->remap_addr == NULL) {
3925                         dev_err(chip->card->dev,
3926                                 "%s ioremap problem\n", region->name);
3927                         return -ENOMEM;
3928                 }
3929         }
3930
3931         if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt,
3932                              IRQF_SHARED, KBUILD_MODNAME, chip)) {
3933                 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3934                 return -EBUSY;
3935         }
3936         chip->irq = pci->irq;
3937         card->sync_irq = chip->irq;
3938         card->private_free = snd_cs46xx_free;
3939
3940 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3941         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3942         if (!chip->dsp_spos_instance)
3943                 return -ENOMEM;
3944 #endif
3945
3946         err = snd_cs46xx_chip_init(chip);
3947         if (err < 0)
3948                 return err;
3949
3950         snd_cs46xx_proc_init(card, chip);
3951
3952 #ifdef CONFIG_PM_SLEEP
3953         chip->saved_regs = devm_kmalloc_array(&pci->dev,
3954                                               ARRAY_SIZE(saved_regs),
3955                                               sizeof(*chip->saved_regs),
3956                                               GFP_KERNEL);
3957         if (!chip->saved_regs)
3958                 return -ENOMEM;
3959 #endif
3960
3961         chip->active_ctrl(chip, -1); /* disable CLKRUN */
3962         return 0;
3963 }