1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
6 * Routines for control of Cirrus Logic CS461x chips
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
55 #include "cs46xx_lib.h"
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short result,tmp;
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
86 chip->active_ctrl(chip, 1);
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 * Wait for the read to occur.
143 for (count = 0; count < 1000; count++) {
145 * First, we want to wait for a short time.
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
163 * Wait for the valid status bit to go active.
165 for (count = 0; count < 100; count++) {
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
204 struct snd_cs46xx *chip = ac97->private_data;
206 int codec_index = ac97->num;
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
229 chip->active_ctrl(chip, 1);
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
265 for (count = 0; count < 4000; count++) {
267 * First, we want to wait for a short time.
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
282 chip->active_ctrl(chip, -1);
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
306 unsigned long offset,
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
315 dst = chip->region.idx[bank+1].remap_addr + offset;
318 /* writel already converts 32-bit value to right endianess */
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
332 const __le32 *_src = src;
335 *_dst++ = le32_to_cpu(*_src++);
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
347 static void free_module_desc(struct dsp_module_desc *module)
351 kfree(module->module_name);
352 kfree(module->symbol_table.symbols);
353 if (module->segments) {
355 for (i = 0; i < module->nsegments; i++)
356 kfree(module->segments[i].data);
357 kfree(module->segments);
362 /* firmware binary format:
366 * char symbol_name[DSP_MAX_SYMBOL_NAME];
368 * } symbols[nsymbols];
375 * } segments[nsegments];
378 static int load_firmware(struct snd_cs46xx *chip,
379 struct dsp_module_desc **module_ret,
383 unsigned int nums, fwlen, fwsize;
385 struct dsp_module_desc *module = NULL;
386 const struct firmware *fw;
389 sprintf(fw_path, "cs46xx/%s", fw_name);
390 err = reject_firmware(&fw, fw_path, &chip->pci->dev);
393 fwsize = fw->size / 4;
400 module = kzalloc(sizeof(*module), GFP_KERNEL);
403 module->module_name = kstrdup(fw_name, GFP_KERNEL);
404 if (!module->module_name)
408 fwdat = (const __le32 *)fw->data;
409 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
412 module->symbol_table.symbols =
413 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
414 if (!module->symbol_table.symbols)
416 for (i = 0; i < nums; i++) {
417 struct dsp_symbol_entry *entry =
418 &module->symbol_table.symbols[i];
419 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
421 entry->address = le32_to_cpu(fwdat[fwlen++]);
422 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
423 fwlen += DSP_MAX_SYMBOL_NAME / 4;
424 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
433 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
434 if (!module->segments)
436 for (i = 0; i < nums; i++) {
437 struct dsp_segment_desc *entry = &module->segments[i];
438 if (fwlen + 3 > fwsize)
440 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
441 entry->offset = le32_to_cpu(fwdat[fwlen++]);
442 entry->size = le32_to_cpu(fwdat[fwlen++]);
443 if (fwlen + entry->size > fwsize)
445 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
448 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
449 fwlen += entry->size;
452 *module_ret = module;
453 release_firmware(fw);
459 free_module_desc(module);
460 release_firmware(fw);
464 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
465 unsigned long offset,
469 unsigned int bank = offset >> 16;
470 offset = offset & 0xffff;
472 if (snd_BUG_ON((offset & 3) || (len & 3)))
474 dst = chip->region.idx[bank+1].remap_addr + offset;
477 /* writel already converts 32-bit value to right endianess */
485 #else /* old DSP image */
491 } memory[BA1_MEMORY_COUNT];
492 u32 map[BA1_DWORD_SIZE];
497 static int load_firmware(struct snd_cs46xx *chip)
499 const struct firmware *fw;
502 err = reject_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
505 if (fw->size != sizeof(*chip->ba1)) {
510 chip->ba1 = vmalloc(sizeof(*chip->ba1));
516 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
520 for (i = 0; i < BA1_MEMORY_COUNT; i++)
521 size += chip->ba1->memory[i].size;
522 if (size > BA1_DWORD_SIZE * 4)
526 release_firmware(fw);
530 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
533 unsigned int offset = 0;
534 struct ba1_struct *ba1 = chip->ba1;
536 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
537 err = snd_cs46xx_download(chip,
539 ba1->memory[idx].offset,
540 ba1->memory[idx].size);
543 offset += ba1->memory[idx].size >> 2;
547 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
553 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
558 * Write the reset bit of the SP control register.
560 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
563 * Write the control register.
565 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
568 * Clear the trap registers.
570 for (idx = 0; idx < 8; idx++) {
571 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
572 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
574 snd_cs46xx_poke(chip, BA1_DREG, 0);
577 * Set the frame timer to reflect the number of cycles per frame.
579 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
582 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
586 * Make sure the previous FIFO write operation has completed.
588 for(i = 0; i < 50; i++){
589 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
591 if( !(status & SERBST_WBSY) )
594 mdelay(retry_timeout);
597 if(status & SERBST_WBSY) {
598 dev_err(chip->card->dev,
599 "failure waiting for FIFO command to complete\n");
606 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
608 int idx, powerdown = 0;
612 * See if the devices are powered down. If so, we must power them up first
613 * or they will not respond.
615 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
616 if (!(tmp & CLKCR1_SWCE)) {
617 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 * We want to clear out the serial port FIFOs so we don't end up playing
623 * whatever random garbage happens to be in them. We fill the sample FIFOS
624 * with zero (silence).
626 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
629 * Fill all 256 sample FIFO locations.
631 for (idx = 0; idx < 0xFF; idx++) {
633 * Make sure the previous FIFO write operation has completed.
635 if (cs46xx_wait_for_fifo(chip,1)) {
636 dev_dbg(chip->card->dev,
637 "failed waiting for FIFO at addr (%02X)\n",
641 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646 * Write the serial port FIFO index.
648 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
650 * Tell the serial port to load the new value into the FIFO location.
652 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
655 * Now, if we powered up the devices, then power them back down again.
656 * This is kinda ugly, but should never happen.
659 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
662 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
667 * Set the frame timer to reflect the number of cycles per frame.
669 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
671 * Turn on the run, run at frame, and DMA enable bits in the local copy of
672 * the SP control register.
674 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
676 * Wait until the run at frame bit resets itself in the SP control
679 for (cnt = 0; cnt < 25; cnt++) {
681 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
685 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
686 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
689 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
692 * Turn off the run, run at frame, and DMA enable bits in the local copy of
693 * the SP control register.
695 snd_cs46xx_poke(chip, BA1_SPCR, 0);
699 * Sample rate routines
702 #define GOF_PER_SEC 200
704 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
707 unsigned int tmp1, tmp2;
708 unsigned int phiIncr;
709 unsigned int correctionPerGOF, correctionPerSec;
712 * Compute the values used to drive the actual sample rate conversion.
713 * The following formulas are being computed, using inline assembly
714 * since we need to use 64 bit arithmetic to compute the values:
716 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
717 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
719 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
720 * GOF_PER_SEC * correctionPerGOF
724 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
725 * correctionPerGOF:correctionPerSec =
726 * dividend:remainder(ulOther / GOF_PER_SEC)
729 phiIncr = tmp1 / 48000;
730 tmp1 -= phiIncr * 48000;
735 tmp1 -= tmp2 * 48000;
736 correctionPerGOF = tmp1 / GOF_PER_SEC;
737 tmp1 -= correctionPerGOF * GOF_PER_SEC;
738 correctionPerSec = tmp1;
741 * Fill in the SampleRateConverter control block.
743 spin_lock_irqsave(&chip->reg_lock, flags);
744 snd_cs46xx_poke(chip, BA1_PSRC,
745 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
746 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
747 spin_unlock_irqrestore(&chip->reg_lock, flags);
750 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
753 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
754 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
755 unsigned int frameGroupLength, cnt;
758 * We can only decimate by up to a factor of 1/9th the hardware rate.
759 * Correct the value if an attempt is made to stray outside that limit.
761 if ((rate * 9) < 48000)
765 * We can not capture at a rate greater than the Input Rate (48000).
766 * Return an error if an attempt is made to stray outside that limit.
772 * Compute the values used to drive the actual sample rate conversion.
773 * The following formulas are being computed, using inline assembly
774 * since we need to use 64 bit arithmetic to compute the values:
776 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
777 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
778 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
780 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
781 * GOF_PER_SEC * correctionPerGOF
782 * initialDelay = ceil((24 * Fs,in) / Fs,out)
786 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
787 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
788 * correctionPerGOF:correctionPerSec =
789 * dividend:remainder(ulOther / GOF_PER_SEC)
790 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
794 coeffIncr = tmp1 / 48000;
795 tmp1 -= coeffIncr * 48000;
798 coeffIncr += tmp1 / 48000;
799 coeffIncr ^= 0xFFFFFFFF;
802 phiIncr = tmp1 / rate;
803 tmp1 -= phiIncr * rate;
809 correctionPerGOF = tmp1 / GOF_PER_SEC;
810 tmp1 -= correctionPerGOF * GOF_PER_SEC;
811 correctionPerSec = tmp1;
812 initialDelay = ((48000 * 24) + rate - 1) / rate;
815 * Fill in the VariDecimate control block.
817 spin_lock_irqsave(&chip->reg_lock, flags);
818 snd_cs46xx_poke(chip, BA1_CSRC,
819 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
820 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
821 snd_cs46xx_poke(chip, BA1_CD,
822 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
823 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
824 spin_unlock_irqrestore(&chip->reg_lock, flags);
827 * Figure out the frame group length for the write back task. Basically,
828 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
829 * the output sample rate.
831 frameGroupLength = 1;
832 for (cnt = 2; cnt <= 64; cnt *= 2) {
833 if (((rate / cnt) * cnt) != rate)
834 frameGroupLength *= 2;
836 if (((rate / 3) * 3) != rate) {
837 frameGroupLength *= 3;
839 for (cnt = 5; cnt <= 125; cnt *= 5) {
840 if (((rate / cnt) * cnt) != rate)
841 frameGroupLength *= 5;
845 * Fill in the WriteBack control block.
847 spin_lock_irqsave(&chip->reg_lock, flags);
848 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
849 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
850 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
851 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
852 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
853 spin_unlock_irqrestore(&chip->reg_lock, flags);
860 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
861 struct snd_pcm_indirect *rec, size_t bytes)
863 struct snd_pcm_runtime *runtime = substream->runtime;
864 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
865 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
868 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
870 struct snd_pcm_runtime *runtime = substream->runtime;
871 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
872 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
873 snd_cs46xx_pb_trans_copy);
876 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
877 struct snd_pcm_indirect *rec, size_t bytes)
879 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
880 struct snd_pcm_runtime *runtime = substream->runtime;
881 memcpy(runtime->dma_area + rec->sw_data,
882 chip->capt.hw_buf.area + rec->hw_data, bytes);
885 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
887 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
888 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
889 snd_cs46xx_cp_trans_copy);
892 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
894 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
896 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
898 if (snd_BUG_ON(!cpcm->pcm_channel))
901 #ifdef CONFIG_SND_CS46XX_NEW_DSP
902 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
904 ptr = snd_cs46xx_peek(chip, BA1_PBA);
906 ptr -= cpcm->hw_buf.addr;
907 return ptr >> cpcm->shift;
910 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
912 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
914 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
916 #ifdef CONFIG_SND_CS46XX_NEW_DSP
917 if (snd_BUG_ON(!cpcm->pcm_channel))
919 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
921 ptr = snd_cs46xx_peek(chip, BA1_PBA);
923 ptr -= cpcm->hw_buf.addr;
924 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
927 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
929 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
930 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
931 return ptr >> chip->capt.shift;
934 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
936 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
937 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
938 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
941 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
944 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
945 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
949 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
950 if (! cpcm->pcm_channel) {
955 case SNDRV_PCM_TRIGGER_START:
956 case SNDRV_PCM_TRIGGER_RESUME:
957 #ifdef CONFIG_SND_CS46XX_NEW_DSP
958 /* magic value to unmute PCM stream playback volume */
959 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
960 SCBVolumeCtrl) << 2, 0x80008000);
962 if (cpcm->pcm_channel->unlinked)
963 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
965 if (substream->runtime->periods != CS46XX_FRAGS)
966 snd_cs46xx_playback_transfer(substream);
968 spin_lock(&chip->reg_lock);
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
972 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
974 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
976 spin_unlock(&chip->reg_lock);
979 case SNDRV_PCM_TRIGGER_STOP:
980 case SNDRV_PCM_TRIGGER_SUSPEND:
981 #ifdef CONFIG_SND_CS46XX_NEW_DSP
982 /* magic mute channel */
983 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
984 SCBVolumeCtrl) << 2, 0xffffffff);
986 if (!cpcm->pcm_channel->unlinked)
987 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
989 spin_lock(&chip->reg_lock);
991 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
993 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
995 spin_unlock(&chip->reg_lock);
1006 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1009 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1013 spin_lock(&chip->reg_lock);
1015 case SNDRV_PCM_TRIGGER_START:
1016 case SNDRV_PCM_TRIGGER_RESUME:
1017 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1019 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1021 case SNDRV_PCM_TRIGGER_STOP:
1022 case SNDRV_PCM_TRIGGER_SUSPEND:
1023 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1025 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1031 spin_unlock(&chip->reg_lock);
1036 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1037 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1041 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1042 if ( cpcm->pcm_channel == NULL) {
1043 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1044 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1045 if (cpcm->pcm_channel == NULL) {
1046 dev_err(chip->card->dev,
1047 "failed to create virtual PCM channel\n");
1050 cpcm->pcm_channel->sample_rate = sample_rate;
1052 /* if sample rate is changed */
1053 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1054 int unlinked = cpcm->pcm_channel->unlinked;
1055 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1057 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1059 cpcm->pcm_channel_id)) == NULL) {
1060 dev_err(chip->card->dev,
1061 "failed to re-create virtual PCM channel\n");
1065 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1066 cpcm->pcm_channel->sample_rate = sample_rate;
1074 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1075 struct snd_pcm_hw_params *hw_params)
1077 struct snd_pcm_runtime *runtime = substream->runtime;
1078 struct snd_cs46xx_pcm *cpcm;
1080 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1081 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1082 int sample_rate = params_rate(hw_params);
1083 int period_size = params_period_bytes(hw_params);
1085 cpcm = runtime->private_data;
1087 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1088 if (snd_BUG_ON(!sample_rate))
1091 mutex_lock(&chip->spos_mutex);
1093 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1094 mutex_unlock(&chip->spos_mutex);
1098 snd_BUG_ON(!cpcm->pcm_channel);
1099 if (!cpcm->pcm_channel) {
1100 mutex_unlock(&chip->spos_mutex);
1105 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1106 mutex_unlock(&chip->spos_mutex);
1110 dev_dbg(chip->card->dev,
1111 "period_size (%d), periods (%d) buffer_size(%d)\n",
1112 period_size, params_periods(hw_params),
1113 params_buffer_bytes(hw_params));
1116 if (params_periods(hw_params) == CS46XX_FRAGS) {
1117 if (runtime->dma_area != cpcm->hw_buf.area)
1118 snd_pcm_lib_free_pages(substream);
1119 runtime->dma_area = cpcm->hw_buf.area;
1120 runtime->dma_addr = cpcm->hw_buf.addr;
1121 runtime->dma_bytes = cpcm->hw_buf.bytes;
1124 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1125 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1126 substream->ops = &snd_cs46xx_playback_ops;
1127 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1128 substream->ops = &snd_cs46xx_playback_rear_ops;
1129 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_clfe_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_iec958_ops;
1137 substream->ops = &snd_cs46xx_playback_ops;
1141 if (runtime->dma_area == cpcm->hw_buf.area) {
1142 runtime->dma_area = NULL;
1143 runtime->dma_addr = 0;
1144 runtime->dma_bytes = 0;
1146 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1147 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1148 mutex_unlock(&chip->spos_mutex);
1153 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1154 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1155 substream->ops = &snd_cs46xx_playback_indirect_ops;
1156 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1157 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1158 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1166 substream->ops = &snd_cs46xx_playback_indirect_ops;
1171 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1172 mutex_unlock(&chip->spos_mutex);
1178 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1180 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1181 struct snd_pcm_runtime *runtime = substream->runtime;
1182 struct snd_cs46xx_pcm *cpcm;
1184 cpcm = runtime->private_data;
1186 /* if play_back open fails, then this function
1187 is called and cpcm can actually be NULL here */
1188 if (!cpcm) return -ENXIO;
1190 if (runtime->dma_area != cpcm->hw_buf.area)
1191 snd_pcm_lib_free_pages(substream);
1193 runtime->dma_area = NULL;
1194 runtime->dma_addr = 0;
1195 runtime->dma_bytes = 0;
1200 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1204 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1205 struct snd_pcm_runtime *runtime = substream->runtime;
1206 struct snd_cs46xx_pcm *cpcm;
1208 cpcm = runtime->private_data;
1210 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1211 if (snd_BUG_ON(!cpcm->pcm_channel))
1214 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1215 pfie &= ~0x0000f03f;
1218 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1219 pfie &= ~0x0000f03f;
1223 /* if to convert from stereo to mono */
1224 if (runtime->channels == 1) {
1228 /* if to convert from 8 bit to 16 bit */
1229 if (snd_pcm_format_width(runtime->format) == 8) {
1233 /* if to convert to unsigned */
1234 if (snd_pcm_format_unsigned(runtime->format))
1237 /* Never convert byte order when sample stream is 8 bit */
1238 if (snd_pcm_format_width(runtime->format) != 8) {
1239 /* convert from big endian to little endian */
1240 if (snd_pcm_format_big_endian(runtime->format))
1244 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1245 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1246 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1248 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1250 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1252 tmp |= (4 << cpcm->shift) - 1;
1253 /* playback transaction count register */
1254 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1256 /* playback format && interrupt enable */
1257 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1259 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1260 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1262 tmp |= (4 << cpcm->shift) - 1;
1263 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1264 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1265 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1271 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1272 struct snd_pcm_hw_params *hw_params)
1274 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1275 struct snd_pcm_runtime *runtime = substream->runtime;
1278 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1279 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1281 if (runtime->periods == CS46XX_FRAGS) {
1282 if (runtime->dma_area != chip->capt.hw_buf.area)
1283 snd_pcm_lib_free_pages(substream);
1284 runtime->dma_area = chip->capt.hw_buf.area;
1285 runtime->dma_addr = chip->capt.hw_buf.addr;
1286 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1287 substream->ops = &snd_cs46xx_capture_ops;
1289 if (runtime->dma_area == chip->capt.hw_buf.area) {
1290 runtime->dma_area = NULL;
1291 runtime->dma_addr = 0;
1292 runtime->dma_bytes = 0;
1294 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1296 substream->ops = &snd_cs46xx_capture_indirect_ops;
1302 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1304 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1305 struct snd_pcm_runtime *runtime = substream->runtime;
1307 if (runtime->dma_area != chip->capt.hw_buf.area)
1308 snd_pcm_lib_free_pages(substream);
1309 runtime->dma_area = NULL;
1310 runtime->dma_addr = 0;
1311 runtime->dma_bytes = 0;
1316 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1318 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1319 struct snd_pcm_runtime *runtime = substream->runtime;
1321 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1322 chip->capt.shift = 2;
1323 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1324 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1325 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1326 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1331 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1333 struct snd_cs46xx *chip = dev_id;
1335 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1336 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1339 struct snd_cs46xx_pcm *cpcm = NULL;
1343 * Read the Interrupt Status Register to clear the interrupt
1345 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1346 if ((status1 & 0x7fffffff) == 0) {
1347 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1351 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1352 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1354 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1356 if ( status1 & (1 << i) ) {
1357 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1358 if (chip->capt.substream)
1359 snd_pcm_period_elapsed(chip->capt.substream);
1361 if (ins->pcm_channels[i].active &&
1362 ins->pcm_channels[i].private_data &&
1363 !ins->pcm_channels[i].unlinked) {
1364 cpcm = ins->pcm_channels[i].private_data;
1365 snd_pcm_period_elapsed(cpcm->substream);
1370 if ( status2 & (1 << (i - 16))) {
1371 if (ins->pcm_channels[i].active &&
1372 ins->pcm_channels[i].private_data &&
1373 !ins->pcm_channels[i].unlinked) {
1374 cpcm = ins->pcm_channels[i].private_data;
1375 snd_pcm_period_elapsed(cpcm->substream);
1383 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1384 if (chip->playback_pcm->substream)
1385 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1387 if ((status1 & HISR_VC1) && chip->pcm) {
1388 if (chip->capt.substream)
1389 snd_pcm_period_elapsed(chip->capt.substream);
1393 if ((status1 & HISR_MIDI) && chip->rmidi) {
1396 spin_lock(&chip->reg_lock);
1397 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1398 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1399 if ((chip->midcr & MIDCR_RIE) == 0)
1401 snd_rawmidi_receive(chip->midi_input, &c, 1);
1403 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1404 if ((chip->midcr & MIDCR_TIE) == 0)
1406 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1407 chip->midcr &= ~MIDCR_TIE;
1408 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1411 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1413 spin_unlock(&chip->reg_lock);
1416 * EOI to the PCI part....reenables interrupts
1418 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1423 static const struct snd_pcm_hardware snd_cs46xx_playback =
1425 .info = (SNDRV_PCM_INFO_MMAP |
1426 SNDRV_PCM_INFO_INTERLEAVED |
1427 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1428 /*SNDRV_PCM_INFO_RESUME*/ |
1429 SNDRV_PCM_INFO_SYNC_APPLPTR),
1430 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1431 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1432 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1433 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1438 .buffer_bytes_max = (256 * 1024),
1439 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1440 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1441 .periods_min = CS46XX_FRAGS,
1442 .periods_max = 1024,
1446 static const struct snd_pcm_hardware snd_cs46xx_capture =
1448 .info = (SNDRV_PCM_INFO_MMAP |
1449 SNDRV_PCM_INFO_INTERLEAVED |
1450 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1451 /*SNDRV_PCM_INFO_RESUME*/ |
1452 SNDRV_PCM_INFO_SYNC_APPLPTR),
1453 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1454 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1459 .buffer_bytes_max = (256 * 1024),
1460 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1461 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1462 .periods_min = CS46XX_FRAGS,
1463 .periods_max = 1024,
1467 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1469 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1471 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1472 .count = ARRAY_SIZE(period_sizes),
1473 .list = period_sizes,
1479 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1481 kfree(runtime->private_data);
1484 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1486 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1487 struct snd_cs46xx_pcm * cpcm;
1488 struct snd_pcm_runtime *runtime = substream->runtime;
1490 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1493 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1494 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1499 runtime->hw = snd_cs46xx_playback;
1500 runtime->private_data = cpcm;
1501 runtime->private_free = snd_cs46xx_pcm_free_substream;
1503 cpcm->substream = substream;
1504 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1505 mutex_lock(&chip->spos_mutex);
1506 cpcm->pcm_channel = NULL;
1507 cpcm->pcm_channel_id = pcm_channel_id;
1510 snd_pcm_hw_constraint_list(runtime, 0,
1511 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1512 &hw_constraints_period_sizes);
1514 mutex_unlock(&chip->spos_mutex);
1516 chip->playback_pcm = cpcm; /* HACK */
1519 if (chip->accept_valid)
1520 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1521 chip->active_ctrl(chip, 1);
1526 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1528 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1529 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1532 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1533 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1535 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1536 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1539 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1541 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1542 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1545 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1547 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1549 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1551 mutex_lock(&chip->spos_mutex);
1552 cs46xx_iec958_pre_open (chip);
1553 mutex_unlock(&chip->spos_mutex);
1555 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1558 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1560 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1563 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1565 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1567 err = snd_cs46xx_playback_close(substream);
1569 mutex_lock(&chip->spos_mutex);
1570 cs46xx_iec958_post_close (chip);
1571 mutex_unlock(&chip->spos_mutex);
1577 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1579 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1581 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1582 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1584 chip->capt.substream = substream;
1585 substream->runtime->hw = snd_cs46xx_capture;
1587 if (chip->accept_valid)
1588 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1590 chip->active_ctrl(chip, 1);
1592 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1593 snd_pcm_hw_constraint_list(substream->runtime, 0,
1594 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1595 &hw_constraints_period_sizes);
1600 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1602 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1603 struct snd_pcm_runtime *runtime = substream->runtime;
1604 struct snd_cs46xx_pcm * cpcm;
1606 cpcm = runtime->private_data;
1608 /* when playback_open fails, then cpcm can be NULL */
1609 if (!cpcm) return -ENXIO;
1611 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1612 mutex_lock(&chip->spos_mutex);
1613 if (cpcm->pcm_channel) {
1614 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1615 cpcm->pcm_channel = NULL;
1617 mutex_unlock(&chip->spos_mutex);
1619 chip->playback_pcm = NULL;
1622 cpcm->substream = NULL;
1623 snd_dma_free_pages(&cpcm->hw_buf);
1624 chip->active_ctrl(chip, -1);
1629 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1631 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1633 chip->capt.substream = NULL;
1634 snd_dma_free_pages(&chip->capt.hw_buf);
1635 chip->active_ctrl(chip, -1);
1640 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1641 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1642 .open = snd_cs46xx_playback_open_rear,
1643 .close = snd_cs46xx_playback_close,
1644 .ioctl = snd_pcm_lib_ioctl,
1645 .hw_params = snd_cs46xx_playback_hw_params,
1646 .hw_free = snd_cs46xx_playback_hw_free,
1647 .prepare = snd_cs46xx_playback_prepare,
1648 .trigger = snd_cs46xx_playback_trigger,
1649 .pointer = snd_cs46xx_playback_direct_pointer,
1652 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1653 .open = snd_cs46xx_playback_open_rear,
1654 .close = snd_cs46xx_playback_close,
1655 .ioctl = snd_pcm_lib_ioctl,
1656 .hw_params = snd_cs46xx_playback_hw_params,
1657 .hw_free = snd_cs46xx_playback_hw_free,
1658 .prepare = snd_cs46xx_playback_prepare,
1659 .trigger = snd_cs46xx_playback_trigger,
1660 .pointer = snd_cs46xx_playback_indirect_pointer,
1661 .ack = snd_cs46xx_playback_transfer,
1664 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1665 .open = snd_cs46xx_playback_open_clfe,
1666 .close = snd_cs46xx_playback_close,
1667 .ioctl = snd_pcm_lib_ioctl,
1668 .hw_params = snd_cs46xx_playback_hw_params,
1669 .hw_free = snd_cs46xx_playback_hw_free,
1670 .prepare = snd_cs46xx_playback_prepare,
1671 .trigger = snd_cs46xx_playback_trigger,
1672 .pointer = snd_cs46xx_playback_direct_pointer,
1675 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1676 .open = snd_cs46xx_playback_open_clfe,
1677 .close = snd_cs46xx_playback_close,
1678 .ioctl = snd_pcm_lib_ioctl,
1679 .hw_params = snd_cs46xx_playback_hw_params,
1680 .hw_free = snd_cs46xx_playback_hw_free,
1681 .prepare = snd_cs46xx_playback_prepare,
1682 .trigger = snd_cs46xx_playback_trigger,
1683 .pointer = snd_cs46xx_playback_indirect_pointer,
1684 .ack = snd_cs46xx_playback_transfer,
1687 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1688 .open = snd_cs46xx_playback_open_iec958,
1689 .close = snd_cs46xx_playback_close_iec958,
1690 .ioctl = snd_pcm_lib_ioctl,
1691 .hw_params = snd_cs46xx_playback_hw_params,
1692 .hw_free = snd_cs46xx_playback_hw_free,
1693 .prepare = snd_cs46xx_playback_prepare,
1694 .trigger = snd_cs46xx_playback_trigger,
1695 .pointer = snd_cs46xx_playback_direct_pointer,
1698 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1699 .open = snd_cs46xx_playback_open_iec958,
1700 .close = snd_cs46xx_playback_close_iec958,
1701 .ioctl = snd_pcm_lib_ioctl,
1702 .hw_params = snd_cs46xx_playback_hw_params,
1703 .hw_free = snd_cs46xx_playback_hw_free,
1704 .prepare = snd_cs46xx_playback_prepare,
1705 .trigger = snd_cs46xx_playback_trigger,
1706 .pointer = snd_cs46xx_playback_indirect_pointer,
1707 .ack = snd_cs46xx_playback_transfer,
1712 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1713 .open = snd_cs46xx_playback_open,
1714 .close = snd_cs46xx_playback_close,
1715 .ioctl = snd_pcm_lib_ioctl,
1716 .hw_params = snd_cs46xx_playback_hw_params,
1717 .hw_free = snd_cs46xx_playback_hw_free,
1718 .prepare = snd_cs46xx_playback_prepare,
1719 .trigger = snd_cs46xx_playback_trigger,
1720 .pointer = snd_cs46xx_playback_direct_pointer,
1723 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1724 .open = snd_cs46xx_playback_open,
1725 .close = snd_cs46xx_playback_close,
1726 .ioctl = snd_pcm_lib_ioctl,
1727 .hw_params = snd_cs46xx_playback_hw_params,
1728 .hw_free = snd_cs46xx_playback_hw_free,
1729 .prepare = snd_cs46xx_playback_prepare,
1730 .trigger = snd_cs46xx_playback_trigger,
1731 .pointer = snd_cs46xx_playback_indirect_pointer,
1732 .ack = snd_cs46xx_playback_transfer,
1735 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1736 .open = snd_cs46xx_capture_open,
1737 .close = snd_cs46xx_capture_close,
1738 .ioctl = snd_pcm_lib_ioctl,
1739 .hw_params = snd_cs46xx_capture_hw_params,
1740 .hw_free = snd_cs46xx_capture_hw_free,
1741 .prepare = snd_cs46xx_capture_prepare,
1742 .trigger = snd_cs46xx_capture_trigger,
1743 .pointer = snd_cs46xx_capture_direct_pointer,
1746 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1747 .open = snd_cs46xx_capture_open,
1748 .close = snd_cs46xx_capture_close,
1749 .ioctl = snd_pcm_lib_ioctl,
1750 .hw_params = snd_cs46xx_capture_hw_params,
1751 .hw_free = snd_cs46xx_capture_hw_free,
1752 .prepare = snd_cs46xx_capture_prepare,
1753 .trigger = snd_cs46xx_capture_trigger,
1754 .pointer = snd_cs46xx_capture_indirect_pointer,
1755 .ack = snd_cs46xx_capture_transfer,
1758 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1759 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1761 #define MAX_PLAYBACK_CHANNELS 1
1764 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1766 struct snd_pcm *pcm;
1769 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1772 pcm->private_data = chip;
1774 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1775 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1778 pcm->info_flags = 0;
1779 strcpy(pcm->name, "CS46xx");
1782 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1783 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1789 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1790 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1792 struct snd_pcm *pcm;
1795 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1798 pcm->private_data = chip;
1800 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1803 pcm->info_flags = 0;
1804 strcpy(pcm->name, "CS46xx - Rear");
1805 chip->pcm_rear = pcm;
1807 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1808 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1813 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1815 struct snd_pcm *pcm;
1818 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1821 pcm->private_data = chip;
1823 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1826 pcm->info_flags = 0;
1827 strcpy(pcm->name, "CS46xx - Center LFE");
1828 chip->pcm_center_lfe = pcm;
1830 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1831 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1836 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1838 struct snd_pcm *pcm;
1841 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1844 pcm->private_data = chip;
1846 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1849 pcm->info_flags = 0;
1850 strcpy(pcm->name, "CS46xx - IEC958");
1851 chip->pcm_iec958 = pcm;
1853 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1854 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1863 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1865 struct snd_cs46xx *chip = bus->private_data;
1867 chip->ac97_bus = NULL;
1870 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1872 struct snd_cs46xx *chip = ac97->private_data;
1874 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1875 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1878 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1879 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1880 chip->eapd_switch = NULL;
1883 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1886 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1887 struct snd_ctl_elem_info *uinfo)
1889 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1891 uinfo->value.integer.min = 0;
1892 uinfo->value.integer.max = 0x7fff;
1896 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1898 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1899 int reg = kcontrol->private_value;
1900 unsigned int val = snd_cs46xx_peek(chip, reg);
1901 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1902 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1906 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1908 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1909 int reg = kcontrol->private_value;
1910 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1911 (0xffff - ucontrol->value.integer.value[1]));
1912 unsigned int old = snd_cs46xx_peek(chip, reg);
1913 int change = (old != val);
1916 snd_cs46xx_poke(chip, reg, val);
1922 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1924 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1926 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1928 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1929 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1934 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1936 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1939 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1940 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1941 cs46xx_dsp_set_dac_volume(chip,
1942 ucontrol->value.integer.value[0],
1943 ucontrol->value.integer.value[1]);
1951 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1953 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1955 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1956 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1960 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1962 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1965 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1966 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1967 cs46xx_dsp_set_iec958_volume (chip,
1968 ucontrol->value.integer.value[0],
1969 ucontrol->value.integer.value[1]);
1977 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1979 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *ucontrol)
1982 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1983 int reg = kcontrol->private_value;
1985 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1986 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1988 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1993 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1994 struct snd_ctl_elem_value *ucontrol)
1996 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1999 switch (kcontrol->private_value) {
2000 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2001 mutex_lock(&chip->spos_mutex);
2002 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2003 if (ucontrol->value.integer.value[0] && !change)
2004 cs46xx_dsp_enable_spdif_out(chip);
2005 else if (change && !ucontrol->value.integer.value[0])
2006 cs46xx_dsp_disable_spdif_out(chip);
2008 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2009 mutex_unlock(&chip->spos_mutex);
2011 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2012 change = chip->dsp_spos_instance->spdif_status_in;
2013 if (ucontrol->value.integer.value[0] && !change) {
2014 cs46xx_dsp_enable_spdif_in(chip);
2015 /* restore volume */
2017 else if (change && !ucontrol->value.integer.value[0])
2018 cs46xx_dsp_disable_spdif_in(chip);
2020 res = (change != chip->dsp_spos_instance->spdif_status_in);
2024 snd_BUG(); /* should never happen ... */
2030 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2031 struct snd_ctl_elem_value *ucontrol)
2033 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2034 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2036 if (ins->adc_input != NULL)
2037 ucontrol->value.integer.value[0] = 1;
2039 ucontrol->value.integer.value[0] = 0;
2044 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2045 struct snd_ctl_elem_value *ucontrol)
2047 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2048 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2051 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2052 cs46xx_dsp_enable_adc_capture(chip);
2054 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2055 cs46xx_dsp_disable_adc_capture(chip);
2061 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2062 struct snd_ctl_elem_value *ucontrol)
2064 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2065 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2067 if (ins->pcm_input != NULL)
2068 ucontrol->value.integer.value[0] = 1;
2070 ucontrol->value.integer.value[0] = 0;
2076 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2077 struct snd_ctl_elem_value *ucontrol)
2079 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2080 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2083 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2084 cs46xx_dsp_enable_pcm_capture(chip);
2086 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2087 cs46xx_dsp_disable_pcm_capture(chip);
2094 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2095 struct snd_ctl_elem_value *ucontrol)
2097 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2099 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2101 if (val1 & EGPIODR_GPOE0)
2102 ucontrol->value.integer.value[0] = 1;
2104 ucontrol->value.integer.value[0] = 0;
2110 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2112 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2113 struct snd_ctl_elem_value *ucontrol)
2115 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2116 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2117 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2119 if (ucontrol->value.integer.value[0]) {
2120 /* optical is default */
2121 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2122 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2123 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2124 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2127 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2128 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2131 /* checking diff from the EGPIO direction register
2133 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2137 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2139 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2144 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2145 struct snd_ctl_elem_value *ucontrol)
2147 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2148 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2150 mutex_lock(&chip->spos_mutex);
2151 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2152 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2153 ucontrol->value.iec958.status[2] = 0;
2154 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2155 mutex_unlock(&chip->spos_mutex);
2160 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2161 struct snd_ctl_elem_value *ucontrol)
2163 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2164 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2168 mutex_lock(&chip->spos_mutex);
2169 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2170 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2171 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2172 /* left and right validity bit */
2173 (1 << 13) | (1 << 12);
2176 change = (unsigned int)ins->spdif_csuv_default != val;
2177 ins->spdif_csuv_default = val;
2179 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2180 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2182 mutex_unlock(&chip->spos_mutex);
2187 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2188 struct snd_ctl_elem_value *ucontrol)
2190 ucontrol->value.iec958.status[0] = 0xff;
2191 ucontrol->value.iec958.status[1] = 0xff;
2192 ucontrol->value.iec958.status[2] = 0x00;
2193 ucontrol->value.iec958.status[3] = 0xff;
2197 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2198 struct snd_ctl_elem_value *ucontrol)
2200 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2201 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2203 mutex_lock(&chip->spos_mutex);
2204 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2205 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2206 ucontrol->value.iec958.status[2] = 0;
2207 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2208 mutex_unlock(&chip->spos_mutex);
2213 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2214 struct snd_ctl_elem_value *ucontrol)
2216 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2217 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2221 mutex_lock(&chip->spos_mutex);
2222 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2223 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2224 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2225 /* left and right validity bit */
2226 (1 << 13) | (1 << 12);
2229 change = ins->spdif_csuv_stream != val;
2230 ins->spdif_csuv_stream = val;
2232 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2233 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2235 mutex_unlock(&chip->spos_mutex);
2240 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2243 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2245 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2246 .name = "DAC Volume",
2247 .info = snd_cs46xx_vol_info,
2248 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2249 .get = snd_cs46xx_vol_get,
2250 .put = snd_cs46xx_vol_put,
2251 .private_value = BA1_PVOL,
2253 .get = snd_cs46xx_vol_dac_get,
2254 .put = snd_cs46xx_vol_dac_put,
2259 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2260 .name = "ADC Volume",
2261 .info = snd_cs46xx_vol_info,
2262 .get = snd_cs46xx_vol_get,
2263 .put = snd_cs46xx_vol_put,
2264 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2265 .private_value = BA1_CVOL,
2267 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2270 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2272 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2273 .name = "ADC Capture Switch",
2274 .info = snd_mixer_boolean_info,
2275 .get = snd_cs46xx_adc_capture_get,
2276 .put = snd_cs46xx_adc_capture_put
2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2280 .name = "DAC Capture Switch",
2281 .info = snd_mixer_boolean_info,
2282 .get = snd_cs46xx_pcm_capture_get,
2283 .put = snd_cs46xx_pcm_capture_put
2286 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2287 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2288 .info = snd_mixer_boolean_info,
2289 .get = snd_cs46xx_iec958_get,
2290 .put = snd_cs46xx_iec958_put,
2291 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2294 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2295 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2296 .info = snd_mixer_boolean_info,
2297 .get = snd_cs46xx_iec958_get,
2298 .put = snd_cs46xx_iec958_put,
2299 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2302 /* Input IEC958 volume does not work for the moment. (Benny) */
2304 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2305 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2306 .info = snd_cs46xx_vol_info,
2307 .get = snd_cs46xx_vol_iec958_get,
2308 .put = snd_cs46xx_vol_iec958_put,
2309 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2313 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2314 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2315 .info = snd_cs46xx_spdif_info,
2316 .get = snd_cs46xx_spdif_default_get,
2317 .put = snd_cs46xx_spdif_default_put,
2320 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2321 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2322 .info = snd_cs46xx_spdif_info,
2323 .get = snd_cs46xx_spdif_mask_get,
2324 .access = SNDRV_CTL_ELEM_ACCESS_READ
2327 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2328 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2329 .info = snd_cs46xx_spdif_info,
2330 .get = snd_cs46xx_spdif_stream_get,
2331 .put = snd_cs46xx_spdif_stream_put
2337 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2338 /* set primary cs4294 codec into Extended Audio Mode */
2339 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2340 struct snd_ctl_elem_value *ucontrol)
2342 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2344 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2345 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2349 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2350 struct snd_ctl_elem_value *ucontrol)
2352 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2353 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2354 AC97_CSR_ACMODE, 0x200,
2355 ucontrol->value.integer.value[0] ? 0 : 0x200);
2358 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2359 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2360 .name = "Duplicate Front",
2361 .info = snd_mixer_boolean_info,
2362 .get = snd_cs46xx_front_dup_get,
2363 .put = snd_cs46xx_front_dup_put,
2367 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2368 /* Only available on the Hercules Game Theater XP soundcard */
2369 static struct snd_kcontrol_new snd_hercules_controls[] = {
2371 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2372 .name = "Optical/Coaxial SPDIF Input Switch",
2373 .info = snd_mixer_boolean_info,
2374 .get = snd_herc_spdif_select_get,
2375 .put = snd_herc_spdif_select_put,
2380 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2382 unsigned long end_time;
2385 /* reset to defaults */
2386 snd_ac97_write(ac97, AC97_RESET, 0);
2388 /* set the desired CODEC mode */
2389 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2390 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2391 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2392 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2393 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2394 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2396 snd_BUG(); /* should never happen ... */
2401 /* it's necessary to wait awhile until registers are accessible after RESET */
2402 /* because the PCM or MASTER volume registers can be modified, */
2403 /* the REC_GAIN register is used for tests */
2404 end_time = jiffies + HZ;
2406 unsigned short ext_mid;
2408 /* use preliminary reads to settle the communication */
2409 snd_ac97_read(ac97, AC97_RESET);
2410 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2411 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2413 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2414 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2417 /* test if we can write to the record gain volume register */
2418 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2419 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2423 } while (time_after_eq(end_time, jiffies));
2425 dev_err(ac97->bus->card->dev,
2426 "CS46xx secondary codec doesn't respond!\n");
2430 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2433 struct snd_ac97_template ac97;
2435 memset(&ac97, 0, sizeof(ac97));
2436 ac97.private_data = chip;
2437 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2439 if (chip->amplifier_ctrl == amp_voyetra)
2440 ac97.scaps = AC97_SCAP_INV_EAPD;
2442 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2443 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2445 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2446 dev_dbg(chip->card->dev,
2447 "secondary codec not present\n");
2452 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2453 for (idx = 0; idx < 100; ++idx) {
2454 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2455 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2460 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2464 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2466 struct snd_card *card = chip->card;
2467 struct snd_ctl_elem_id id;
2470 static struct snd_ac97_bus_ops ops = {
2471 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2472 .reset = snd_cs46xx_codec_reset,
2474 .write = snd_cs46xx_ac97_write,
2475 .read = snd_cs46xx_ac97_read,
2478 /* detect primary codec */
2479 chip->nr_ac97_codecs = 0;
2480 dev_dbg(chip->card->dev, "detecting primary codec\n");
2481 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2483 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2485 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2487 chip->nr_ac97_codecs = 1;
2489 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2490 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2491 /* try detect a secondary codec */
2492 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2493 chip->nr_ac97_codecs = 2;
2494 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2496 /* add cs4630 mixer controls */
2497 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2498 struct snd_kcontrol *kctl;
2499 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2500 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2501 kctl->id.device = spdif_device;
2502 if ((err = snd_ctl_add(card, kctl)) < 0)
2506 /* get EAPD mixer switch (for voyetra hack) */
2507 memset(&id, 0, sizeof(id));
2508 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2509 strcpy(id.name, "External Amplifier");
2510 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2512 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2513 if (chip->nr_ac97_codecs == 1) {
2514 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2515 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2516 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2519 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2520 AC97_CSR_ACMODE, 0x200);
2523 /* do soundcard specific mixer setup */
2524 if (chip->mixer_init) {
2525 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2526 chip->mixer_init(chip);
2530 /* turn on amplifier */
2531 chip->amplifier_ctrl(chip, 1);
2540 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2544 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2547 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2549 struct snd_cs46xx *chip = substream->rmidi->private_data;
2551 chip->active_ctrl(chip, 1);
2552 spin_lock_irq(&chip->reg_lock);
2553 chip->uartm |= CS46XX_MODE_INPUT;
2554 chip->midcr |= MIDCR_RXE;
2555 chip->midi_input = substream;
2556 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2557 snd_cs46xx_midi_reset(chip);
2559 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2561 spin_unlock_irq(&chip->reg_lock);
2565 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2567 struct snd_cs46xx *chip = substream->rmidi->private_data;
2569 spin_lock_irq(&chip->reg_lock);
2570 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2571 chip->midi_input = NULL;
2572 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2573 snd_cs46xx_midi_reset(chip);
2575 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2577 chip->uartm &= ~CS46XX_MODE_INPUT;
2578 spin_unlock_irq(&chip->reg_lock);
2579 chip->active_ctrl(chip, -1);
2583 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2585 struct snd_cs46xx *chip = substream->rmidi->private_data;
2587 chip->active_ctrl(chip, 1);
2589 spin_lock_irq(&chip->reg_lock);
2590 chip->uartm |= CS46XX_MODE_OUTPUT;
2591 chip->midcr |= MIDCR_TXE;
2592 chip->midi_output = substream;
2593 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2594 snd_cs46xx_midi_reset(chip);
2596 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2598 spin_unlock_irq(&chip->reg_lock);
2602 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2604 struct snd_cs46xx *chip = substream->rmidi->private_data;
2606 spin_lock_irq(&chip->reg_lock);
2607 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2608 chip->midi_output = NULL;
2609 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2610 snd_cs46xx_midi_reset(chip);
2612 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2614 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2615 spin_unlock_irq(&chip->reg_lock);
2616 chip->active_ctrl(chip, -1);
2620 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2622 unsigned long flags;
2623 struct snd_cs46xx *chip = substream->rmidi->private_data;
2625 spin_lock_irqsave(&chip->reg_lock, flags);
2627 if ((chip->midcr & MIDCR_RIE) == 0) {
2628 chip->midcr |= MIDCR_RIE;
2629 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2632 if (chip->midcr & MIDCR_RIE) {
2633 chip->midcr &= ~MIDCR_RIE;
2634 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2637 spin_unlock_irqrestore(&chip->reg_lock, flags);
2640 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2642 unsigned long flags;
2643 struct snd_cs46xx *chip = substream->rmidi->private_data;
2646 spin_lock_irqsave(&chip->reg_lock, flags);
2648 if ((chip->midcr & MIDCR_TIE) == 0) {
2649 chip->midcr |= MIDCR_TIE;
2650 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2651 while ((chip->midcr & MIDCR_TIE) &&
2652 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2653 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2654 chip->midcr &= ~MIDCR_TIE;
2656 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2659 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2662 if (chip->midcr & MIDCR_TIE) {
2663 chip->midcr &= ~MIDCR_TIE;
2664 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2667 spin_unlock_irqrestore(&chip->reg_lock, flags);
2670 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2672 .open = snd_cs46xx_midi_output_open,
2673 .close = snd_cs46xx_midi_output_close,
2674 .trigger = snd_cs46xx_midi_output_trigger,
2677 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2679 .open = snd_cs46xx_midi_input_open,
2680 .close = snd_cs46xx_midi_input_close,
2681 .trigger = snd_cs46xx_midi_input_trigger,
2684 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2686 struct snd_rawmidi *rmidi;
2689 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2691 strcpy(rmidi->name, "CS46XX");
2692 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2693 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2694 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2695 rmidi->private_data = chip;
2696 chip->rmidi = rmidi;
2702 * gameport interface
2705 #if IS_REACHABLE(CONFIG_GAMEPORT)
2707 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2709 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2711 if (snd_BUG_ON(!chip))
2713 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2716 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2718 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2720 if (snd_BUG_ON(!chip))
2722 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2725 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2727 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2728 unsigned js1, js2, jst;
2730 if (snd_BUG_ON(!chip))
2733 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2734 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2735 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2737 *buttons = (~jst >> 4) & 0x0F;
2739 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2740 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2741 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2742 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2744 for(jst=0;jst<4;++jst)
2745 if(axes[jst]==0xFFFF) axes[jst] = -1;
2749 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2752 case GAMEPORT_MODE_COOKED:
2754 case GAMEPORT_MODE_RAW:
2762 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2764 struct gameport *gp;
2766 chip->gameport = gp = gameport_allocate_port();
2768 dev_err(chip->card->dev,
2769 "cannot allocate memory for gameport\n");
2773 gameport_set_name(gp, "CS46xx Gameport");
2774 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2775 gameport_set_dev_parent(gp, &chip->pci->dev);
2776 gameport_set_port_data(gp, chip);
2778 gp->open = snd_cs46xx_gameport_open;
2779 gp->read = snd_cs46xx_gameport_read;
2780 gp->trigger = snd_cs46xx_gameport_trigger;
2781 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2783 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2784 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2786 gameport_register_port(gp);
2791 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2793 if (chip->gameport) {
2794 gameport_unregister_port(chip->gameport);
2795 chip->gameport = NULL;
2799 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2800 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2801 #endif /* CONFIG_GAMEPORT */
2803 #ifdef CONFIG_SND_PROC_FS
2808 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2809 void *file_private_data,
2810 struct file *file, char __user *buf,
2811 size_t count, loff_t pos)
2813 struct snd_cs46xx_region *region = entry->private_data;
2815 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2820 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2821 .read = snd_cs46xx_io_read,
2824 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2826 struct snd_info_entry *entry;
2829 for (idx = 0; idx < 5; idx++) {
2830 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2831 if (! snd_card_proc_new(card, region->name, &entry)) {
2832 entry->content = SNDRV_INFO_CONTENT_DATA;
2833 entry->private_data = chip;
2834 entry->c.ops = &snd_cs46xx_proc_io_ops;
2835 entry->size = region->size;
2836 entry->mode = S_IFREG | 0400;
2839 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2840 cs46xx_dsp_proc_init(card, chip);
2845 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2847 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2848 cs46xx_dsp_proc_done(chip);
2852 #else /* !CONFIG_SND_PROC_FS */
2853 #define snd_cs46xx_proc_init(card, chip)
2854 #define snd_cs46xx_proc_done(chip)
2860 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2864 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2867 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2869 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2872 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2875 * Stop playback DMA.
2877 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2878 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2883 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2884 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2887 * Reset the processor.
2889 snd_cs46xx_reset(chip);
2891 snd_cs46xx_proc_stop(chip);
2894 * Power down the PLL.
2896 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2899 * Turn off the Processor by turning off the software clock enable flag in
2900 * the clock control register.
2902 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2903 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2907 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2911 if (snd_BUG_ON(!chip))
2914 if (chip->active_ctrl)
2915 chip->active_ctrl(chip, 1);
2917 snd_cs46xx_remove_gameport(chip);
2919 if (chip->amplifier_ctrl)
2920 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2922 snd_cs46xx_proc_done(chip);
2924 if (chip->region.idx[0].resource)
2925 snd_cs46xx_hw_stop(chip);
2928 free_irq(chip->irq, chip);
2930 if (chip->active_ctrl)
2931 chip->active_ctrl(chip, -chip->amplifier);
2933 for (idx = 0; idx < 5; idx++) {
2934 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2936 iounmap(region->remap_addr);
2937 release_and_free_resource(region->resource);
2940 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2941 if (chip->dsp_spos_instance) {
2942 cs46xx_dsp_spos_destroy(chip);
2943 chip->dsp_spos_instance = NULL;
2945 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2946 free_module_desc(chip->modules[idx]);
2951 #ifdef CONFIG_PM_SLEEP
2952 kfree(chip->saved_regs);
2955 pci_disable_device(chip->pci);
2960 static int snd_cs46xx_dev_free(struct snd_device *device)
2962 struct snd_cs46xx *chip = device->device_data;
2963 return snd_cs46xx_free(chip);
2969 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2974 * First, blast the clock control register to zero so that the PLL starts
2975 * out in a known state, and blast the master serial port control register
2976 * to zero so that the serial ports also start out in a known state.
2978 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2979 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2982 * If we are in AC97 mode, then we must set the part to a host controlled
2983 * AC-link. Otherwise, we won't be able to bring up the link.
2985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2986 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2987 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2988 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2990 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2994 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2995 * spec) and then drive it high. This is done for non AC97 modes since
2996 * there might be logic external to the CS461x that uses the ARST# line
2999 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3000 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3001 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3004 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3005 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3006 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3010 * The first thing we do here is to enable sync generation. As soon
3011 * as we start receiving bit clock, we'll start producing the SYNC
3014 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3015 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3016 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3020 * Now wait for a short while to allow the AC97 part to start
3021 * generating bit clock (so we don't try to start the PLL without an
3027 * Set the serial port timing configuration, so that
3028 * the clock control circuit gets its clock from the correct place.
3030 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3033 * Write the selected clock control setup to the hardware. Do not turn on
3034 * SWCE yet (if requested), so that the devices clocked by the output of
3035 * PLL are not clocked until the PLL is stable.
3037 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3038 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3039 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3044 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3047 * Wait until the PLL has stabilized.
3052 * Turn on clocking of the core so that we can setup the serial ports.
3054 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3057 * Enable FIFO Host Bypass
3059 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3062 * Fill the serial port FIFOs with silence.
3064 snd_cs46xx_clear_serial_FIFOs(chip);
3067 * Set the serial port FIFO pointer to the first sample in the FIFO.
3069 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3072 * Write the serial port configuration to the part. The master
3073 * enable bit is not set until all other values have been written.
3075 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3076 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3077 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3080 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3081 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3082 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3083 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3084 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3085 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3092 * Wait for the codec ready signal from the AC97 codec.
3095 while (timeout-- > 0) {
3097 * Read the AC97 status register to see if we've seen a CODEC READY
3098 * signal from the AC97 codec.
3100 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3106 dev_err(chip->card->dev,
3107 "create - never read codec ready from AC'97\n");
3108 dev_err(chip->card->dev,
3109 "it is not probably bug, try to use CS4236 driver\n");
3112 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3115 for (count = 0; count < 150; count++) {
3116 /* First, we want to wait for a short time. */
3119 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3124 * Make sure CODEC is READY.
3126 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3127 dev_dbg(chip->card->dev,
3128 "never read card ready from secondary AC'97\n");
3133 * Assert the vaid frame signal so that we can start sending commands
3134 * to the AC97 codec.
3136 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3137 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3138 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3143 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3144 * the codec is pumping ADC data across the AC-link.
3147 while (timeout-- > 0) {
3149 * Read the input slot valid register and see if input slots 3 and
3152 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3157 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3158 dev_err(chip->card->dev,
3159 "create - never read ISV3 & ISV4 from AC'97\n");
3162 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3163 Reloading the driver may help, if there's other soundcards
3164 with the same problem I would like to know. (Benny) */
3166 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3167 dev_err(chip->card->dev,
3168 "Try reloading the ALSA driver, if you find something\n");
3169 dev_err(chip->card->dev,
3170 "broken or not working on your soundcard upon\n");
3171 dev_err(chip->card->dev,
3172 "this message please report to alsa-devel@alsa-project.org\n");
3179 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3180 * commense the transfer of digital audio data to the AC97 codec.
3183 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3187 * Power down the DAC and ADC. We will power them up (if) when we need
3190 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3193 * Turn off the Processor by turning off the software clock enable flag in
3194 * the clock control register.
3196 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3197 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3203 * start and load DSP
3206 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3210 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3212 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3214 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3216 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3219 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3222 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3225 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3231 * Reset the processor.
3233 snd_cs46xx_reset(chip);
3235 * Download the image to the processor.
3237 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3238 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3239 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3241 dev_err(chip->card->dev, "firmware load error [%s]\n",
3245 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3247 dev_err(chip->card->dev, "image download error [%s]\n",
3253 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3256 err = load_firmware(chip);
3261 err = snd_cs46xx_download_image(chip);
3263 dev_err(chip->card->dev, "image download error\n");
3268 * Stop playback DMA.
3270 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3271 chip->play_ctl = tmp & 0xffff0000;
3272 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3278 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3279 chip->capt.ctl = tmp & 0x0000ffff;
3280 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3284 snd_cs46xx_set_play_sample_rate(chip, 8000);
3285 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3287 snd_cs46xx_proc_start(chip);
3289 cs46xx_enable_stream_irqs(chip);
3291 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3292 /* set the attenuation to 0dB */
3293 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3294 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3302 * AMP control - null AMP
3305 static void amp_none(struct snd_cs46xx *chip, int change)
3309 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3310 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3313 u32 idx, valid_slots,tmp,powerdown = 0;
3314 u16 modem_power,pin_config,logic_type;
3316 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3319 * See if the devices are powered down. If so, we must power them up first
3320 * or they will not respond.
3322 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3324 if (!(tmp & CLKCR1_SWCE)) {
3325 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3330 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3333 if(chip->nr_ac97_codecs != 2) {
3334 dev_err(chip->card->dev,
3335 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3339 modem_power = snd_cs46xx_codec_read (chip,
3340 AC97_EXTENDED_MSTATUS,
3341 CS46XX_SECONDARY_CODEC_INDEX);
3342 modem_power &=0xFEFF;
3344 snd_cs46xx_codec_write(chip,
3345 AC97_EXTENDED_MSTATUS, modem_power,
3346 CS46XX_SECONDARY_CODEC_INDEX);
3349 * Set GPIO pin's 7 and 8 so that they are configured for output.
3351 pin_config = snd_cs46xx_codec_read (chip,
3353 CS46XX_SECONDARY_CODEC_INDEX);
3356 snd_cs46xx_codec_write(chip,
3357 AC97_GPIO_CFG, pin_config,
3358 CS46XX_SECONDARY_CODEC_INDEX);
3361 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3364 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3365 CS46XX_SECONDARY_CODEC_INDEX);
3368 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3369 CS46XX_SECONDARY_CODEC_INDEX);
3371 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3372 valid_slots |= 0x200;
3373 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3375 if ( cs46xx_wait_for_fifo(chip,1) ) {
3376 dev_dbg(chip->card->dev, "FIFO is busy\n");
3382 * Fill slots 12 with the correct value for the GPIO pins.
3384 for(idx = 0x90; idx <= 0x9F; idx++) {
3386 * Initialize the fifo so that bits 7 and 8 are on.
3388 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3389 * the left. 0x1800 corresponds to bits 7 and 8.
3391 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3394 * Wait for command to complete
3396 if ( cs46xx_wait_for_fifo(chip,200) ) {
3397 dev_dbg(chip->card->dev,
3398 "failed waiting for FIFO at addr (%02X)\n",
3405 * Write the serial port FIFO index.
3407 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3410 * Tell the serial port to load the new value into the FIFO location.
3412 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3415 /* wait for last command to complete */
3416 cs46xx_wait_for_fifo(chip,200);
3419 * Now, if we powered up the devices, then power them back down again.
3420 * This is kinda ugly, but should never happen.
3423 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3433 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3435 /* Manage the EAPD bit on the Crystal 4297
3436 and the Analog AD1885 */
3438 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3439 int old = chip->amplifier;
3443 chip->amplifier += change;
3444 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3445 CS46XX_PRIMARY_CODEC_INDEX);
3447 if (chip->amplifier) {
3448 /* Turn the EAPD amp on */
3451 /* Turn the EAPD amp off */
3455 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3456 CS46XX_PRIMARY_CODEC_INDEX);
3457 if (chip->eapd_switch)
3458 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3459 &chip->eapd_switch->id);
3462 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3463 if (chip->amplifier && !old) {
3464 voyetra_setup_eapd_slot(chip);
3469 static void hercules_init(struct snd_cs46xx *chip)
3471 /* default: AMP off, and SPDIF input optical */
3472 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3473 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3478 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3480 static void amp_hercules(struct snd_cs46xx *chip, int change)
3482 int old = chip->amplifier;
3483 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3484 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3486 chip->amplifier += change;
3487 if (chip->amplifier && !old) {
3488 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3490 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3491 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3492 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3493 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3494 } else if (old && !chip->amplifier) {
3495 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3496 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3497 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3501 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3503 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3505 /* Enable SPDIF out */
3506 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3507 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3510 static void hercules_mixer_init (struct snd_cs46xx *chip)
3512 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3515 struct snd_card *card = chip->card;
3518 /* set EGPIO to default */
3519 hercules_init(chip);
3521 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3523 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3524 if (chip->in_suspend)
3527 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3528 struct snd_kcontrol *kctl;
3530 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3531 if ((err = snd_ctl_add(card, kctl)) < 0) {
3533 "failed to initialize Hercules mixer (%d)\n",
3547 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3549 chip->amplifier += change;
3551 if (chip->amplifier) {
3552 /* Switch the GPIO pins 7 and 8 to open drain */
3553 snd_cs46xx_codec_write(chip, 0x4C,
3554 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3555 snd_cs46xx_codec_write(chip, 0x4E,
3556 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3557 /* Now wake the AMP (this might be backwards) */
3558 snd_cs46xx_codec_write(chip, 0x54,
3559 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3561 snd_cs46xx_codec_write(chip, 0x54,
3562 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3569 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3570 * whenever we need to beat on the chip.
3572 * The original idea and code for this hack comes from David Kaiser at
3573 * Linuxcare. Perhaps one day Crystal will document their chips well
3574 * enough to make them useful.
3577 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3581 if (!chip->acpi_port)
3584 chip->amplifier += change;
3586 /* Read ACPI port */
3587 nval = control = inw(chip->acpi_port + 0x10);
3589 /* Flip CLKRUN off while running */
3590 if (! chip->amplifier)
3594 if (nval != control)
3595 outw(nval, chip->acpi_port + 0x10);
3600 * detect intel piix4
3602 static void clkrun_init(struct snd_cs46xx *chip)
3604 struct pci_dev *pdev;
3607 chip->acpi_port = 0;
3609 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3610 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3612 return; /* Not a thinkpad thats for sure */
3614 /* Find the control port */
3615 pci_read_config_byte(pdev, 0x41, &pp);
3616 chip->acpi_port = pp << 8;
3630 void (*init)(struct snd_cs46xx *);
3631 void (*amp)(struct snd_cs46xx *, int);
3632 void (*active)(struct snd_cs46xx *, int);
3633 void (*mixer_init)(struct snd_cs46xx *);
3636 static struct cs_card_type cards[] = {
3640 .name = "Genius Soundmaker 128 value",
3641 /* nothing special */
3648 .mixer_init = voyetra_mixer_init,
3653 .name = "Mitac MI6020/21",
3656 /* Hercules Game Theatre XP */
3658 .vendor = 0x14af, /* Guillemot Corporation */
3660 .name = "Hercules Game Theatre XP",
3661 .amp = amp_hercules,
3662 .mixer_init = hercules_mixer_init,
3667 .name = "Hercules Game Theatre XP",
3668 .amp = amp_hercules,
3669 .mixer_init = hercules_mixer_init,
3674 .name = "Hercules Game Theatre XP",
3675 .amp = amp_hercules,
3676 .mixer_init = hercules_mixer_init,
3682 .name = "Hercules Game Theatre XP",
3683 .amp = amp_hercules,
3684 .mixer_init = hercules_mixer_init,
3689 .name = "Hercules Game Theatre XP",
3690 .amp = amp_hercules,
3691 .mixer_init = hercules_mixer_init,
3696 .name = "Hercules Game Theatre XP",
3697 .amp = amp_hercules,
3698 .mixer_init = hercules_mixer_init,
3700 /* Herculess Fortissimo */
3704 .name = "Hercules Gamesurround Fortissimo II",
3709 .name = "Hercules Gamesurround Fortissimo III 7.1",
3715 .name = "Terratec DMX XFire 1024",
3720 .name = "Terratec SiXPack 5.1",
3722 /* Not sure if the 570 needs the clkrun hack */
3724 .vendor = PCI_VENDOR_ID_IBM,
3726 .name = "Thinkpad 570",
3727 .init = clkrun_init,
3728 .active = clkrun_hack,
3731 .vendor = PCI_VENDOR_ID_IBM,
3733 .name = "Thinkpad 600X/A20/T20",
3734 .init = clkrun_init,
3735 .active = clkrun_hack,
3738 .vendor = PCI_VENDOR_ID_IBM,
3740 .name = "Thinkpad 600E (unsupported)",
3749 #ifdef CONFIG_PM_SLEEP
3750 static unsigned int saved_regs[] = {
3758 static int snd_cs46xx_suspend(struct device *dev)
3760 struct snd_card *card = dev_get_drvdata(dev);
3761 struct snd_cs46xx *chip = card->private_data;
3764 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3765 chip->in_suspend = 1;
3766 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3767 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3769 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3770 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3772 /* save some registers */
3773 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3774 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3776 amp_saved = chip->amplifier;
3778 chip->amplifier_ctrl(chip, -chip->amplifier);
3779 snd_cs46xx_hw_stop(chip);
3780 /* disable CLKRUN */
3781 chip->active_ctrl(chip, -chip->amplifier);
3782 chip->amplifier = amp_saved; /* restore the status */
3786 static int snd_cs46xx_resume(struct device *dev)
3788 struct snd_card *card = dev_get_drvdata(dev);
3789 struct snd_cs46xx *chip = card->private_data;
3791 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3796 amp_saved = chip->amplifier;
3797 chip->amplifier = 0;
3798 chip->active_ctrl(chip, 1); /* force to on */
3800 snd_cs46xx_chip_init(chip);
3802 snd_cs46xx_reset(chip);
3803 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3804 cs46xx_dsp_resume(chip);
3805 /* restore some registers */
3806 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3807 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3809 snd_cs46xx_download_image(chip);
3813 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3814 chip->ac97_general_purpose);
3815 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3816 chip->ac97_powerdown);
3818 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3819 chip->ac97_powerdown);
3823 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3824 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3829 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3830 chip->capt.ctl = tmp & 0x0000ffff;
3831 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3835 /* reset playback/capture */
3836 snd_cs46xx_set_play_sample_rate(chip, 8000);
3837 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3838 snd_cs46xx_proc_start(chip);
3840 cs46xx_enable_stream_irqs(chip);
3843 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3845 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3846 chip->amplifier = amp_saved;
3847 chip->in_suspend = 0;
3848 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3852 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3853 #endif /* CONFIG_PM_SLEEP */
3859 int snd_cs46xx_create(struct snd_card *card,
3860 struct pci_dev *pci,
3861 int external_amp, int thinkpad,
3862 struct snd_cs46xx **rchip)
3864 struct snd_cs46xx *chip;
3866 struct snd_cs46xx_region *region;
3867 struct cs_card_type *cp;
3868 u16 ss_card, ss_vendor;
3869 static struct snd_device_ops ops = {
3870 .dev_free = snd_cs46xx_dev_free,
3875 /* enable PCI device */
3876 if ((err = pci_enable_device(pci)) < 0)
3879 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3881 pci_disable_device(pci);
3884 spin_lock_init(&chip->reg_lock);
3885 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3886 mutex_init(&chip->spos_mutex);
3891 chip->ba0_addr = pci_resource_start(pci, 0);
3892 chip->ba1_addr = pci_resource_start(pci, 1);
3893 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3894 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3895 dev_err(chip->card->dev,
3896 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3897 chip->ba0_addr, chip->ba1_addr);
3898 snd_cs46xx_free(chip);
3902 region = &chip->region.name.ba0;
3903 strcpy(region->name, "CS46xx_BA0");
3904 region->base = chip->ba0_addr;
3905 region->size = CS46XX_BA0_SIZE;
3907 region = &chip->region.name.data0;
3908 strcpy(region->name, "CS46xx_BA1_data0");
3909 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3910 region->size = CS46XX_BA1_DATA0_SIZE;
3912 region = &chip->region.name.data1;
3913 strcpy(region->name, "CS46xx_BA1_data1");
3914 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3915 region->size = CS46XX_BA1_DATA1_SIZE;
3917 region = &chip->region.name.pmem;
3918 strcpy(region->name, "CS46xx_BA1_pmem");
3919 region->base = chip->ba1_addr + BA1_SP_PMEM;
3920 region->size = CS46XX_BA1_PRG_SIZE;
3922 region = &chip->region.name.reg;
3923 strcpy(region->name, "CS46xx_BA1_reg");
3924 region->base = chip->ba1_addr + BA1_SP_REG;
3925 region->size = CS46XX_BA1_REG_SIZE;
3927 /* set up amp and clkrun hack */
3928 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3929 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3931 for (cp = &cards[0]; cp->name; cp++) {
3932 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3933 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3936 chip->amplifier_ctrl = cp->amp;
3937 chip->active_ctrl = cp->active;
3938 chip->mixer_init = cp->mixer_init;
3947 dev_info(chip->card->dev,
3948 "Crystal EAPD support forced on.\n");
3949 chip->amplifier_ctrl = amp_voyetra;
3953 dev_info(chip->card->dev,
3954 "Activating CLKRUN hack for Thinkpad.\n");
3955 chip->active_ctrl = clkrun_hack;
3959 if (chip->amplifier_ctrl == NULL)
3960 chip->amplifier_ctrl = amp_none;
3961 if (chip->active_ctrl == NULL)
3962 chip->active_ctrl = amp_none;
3964 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3966 pci_set_master(pci);
3968 for (idx = 0; idx < 5; idx++) {
3969 region = &chip->region.idx[idx];
3970 if ((region->resource = request_mem_region(region->base, region->size,
3971 region->name)) == NULL) {
3972 dev_err(chip->card->dev,
3973 "unable to request memory region 0x%lx-0x%lx\n",
3974 region->base, region->base + region->size - 1);
3975 snd_cs46xx_free(chip);
3978 region->remap_addr = ioremap_nocache(region->base, region->size);
3979 if (region->remap_addr == NULL) {
3980 dev_err(chip->card->dev,
3981 "%s ioremap problem\n", region->name);
3982 snd_cs46xx_free(chip);
3987 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3988 KBUILD_MODNAME, chip)) {
3989 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3990 snd_cs46xx_free(chip);
3993 chip->irq = pci->irq;
3995 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3996 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3997 if (chip->dsp_spos_instance == NULL) {
3998 snd_cs46xx_free(chip);
4003 err = snd_cs46xx_chip_init(chip);
4005 snd_cs46xx_free(chip);
4009 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4010 snd_cs46xx_free(chip);
4014 snd_cs46xx_proc_init(card, chip);
4016 #ifdef CONFIG_PM_SLEEP
4017 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4018 sizeof(*chip->saved_regs),
4020 if (!chip->saved_regs) {
4021 snd_cs46xx_free(chip);
4026 chip->active_ctrl(chip, -1); /* disable CLKRUN */