2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
49 "{C-Media,CMI8338B}}");
51 #if IS_REACHABLE(CONFIG_GAMEPORT)
52 #define SUPPORT_JOYSTICK 1
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
60 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
83 * CM8x38 registers definition
86 #define CM_REG_FUNCTRL0 0x00
87 #define CM_RST_CH1 0x00080000
88 #define CM_RST_CH0 0x00040000
89 #define CM_CHEN1 0x00020000 /* ch1: enable */
90 #define CM_CHEN0 0x00010000 /* ch0: enable */
91 #define CM_PAUSE1 0x00000008 /* ch1: pause */
92 #define CM_PAUSE0 0x00000004 /* ch0: pause */
93 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
94 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96 #define CM_REG_FUNCTRL1 0x04
97 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
98 #define CM_DSFC_SHIFT 13
99 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
100 #define CM_ASFC_SHIFT 10
101 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
102 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
103 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
104 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
105 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
106 #define CM_BREQ 0x00000010 /* bus master enabled */
107 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
108 #define CM_UART_EN 0x00000004 /* legacy UART */
109 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
110 #define CM_ZVPORT 0x00000001 /* ZVPORT */
112 #define CM_REG_CHFORMAT 0x08
114 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
115 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
116 #define CM_CHB3D 0x20000000 /* 4 channels */
118 #define CM_CHIP_MASK1 0x1f000000
119 #define CM_CHIP_037 0x01000000
120 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
121 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
122 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
123 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
124 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
125 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
126 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
128 #define CM_ADCBITLEN_MASK 0x0000C000
129 #define CM_ADCBITLEN_16 0x00000000
130 #define CM_ADCBITLEN_15 0x00004000
131 #define CM_ADCBITLEN_14 0x00008000
132 #define CM_ADCBITLEN_13 0x0000C000
134 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
135 #define CM_ADCDACLEN_060 0x00000000
136 #define CM_ADCDACLEN_066 0x00001000
137 #define CM_ADCDACLEN_130 0x00002000
138 #define CM_ADCDACLEN_280 0x00003000
140 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
141 #define CM_ADCDLEN_ORIGINAL 0x00000000
142 #define CM_ADCDLEN_EXTRA 0x00001000
143 #define CM_ADCDLEN_24K 0x00002000
144 #define CM_ADCDLEN_WEIGHT 0x00003000
146 #define CM_CH1_SRATE_176K 0x00000800
147 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
148 #define CM_CH1_SRATE_88K 0x00000400
149 #define CM_CH0_SRATE_176K 0x00000200
150 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
151 #define CM_CH0_SRATE_88K 0x00000100
152 #define CM_CH0_SRATE_128K 0x00000300
153 #define CM_CH0_SRATE_MASK 0x00000300
155 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
156 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
157 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
158 #define CM_SPDLOCKED 0x00000010
160 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
161 #define CM_CH1FMT_SHIFT 2
162 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
163 #define CM_CH0FMT_SHIFT 0
165 #define CM_REG_INT_HLDCLR 0x0C
166 #define CM_CHIP_MASK2 0xff000000
167 #define CM_CHIP_8768 0x20000000
168 #define CM_CHIP_055 0x08000000
169 #define CM_CHIP_039 0x04000000
170 #define CM_CHIP_039_6CH 0x01000000
171 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
172 #define CM_TDMA_INT_EN 0x00040000
173 #define CM_CH1_INT_EN 0x00020000
174 #define CM_CH0_INT_EN 0x00010000
176 #define CM_REG_INT_STATUS 0x10
177 #define CM_INTR 0x80000000
178 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
179 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
180 #define CM_UARTINT 0x00010000
181 #define CM_LTDMAINT 0x00008000
182 #define CM_HTDMAINT 0x00004000
183 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
184 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
185 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
186 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
187 #define CM_CH1BUSY 0x00000008
188 #define CM_CH0BUSY 0x00000004
189 #define CM_CHINT1 0x00000002
190 #define CM_CHINT0 0x00000001
192 #define CM_REG_LEGACY_CTRL 0x14
193 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
194 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
195 #define CM_VMPU_330 0x00000000
196 #define CM_VMPU_320 0x20000000
197 #define CM_VMPU_310 0x40000000
198 #define CM_VMPU_300 0x60000000
199 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
200 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
201 #define CM_VSBSEL_220 0x00000000
202 #define CM_VSBSEL_240 0x04000000
203 #define CM_VSBSEL_260 0x08000000
204 #define CM_VSBSEL_280 0x0C000000
205 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
206 #define CM_FMSEL_388 0x00000000
207 #define CM_FMSEL_3C8 0x01000000
208 #define CM_FMSEL_3E0 0x02000000
209 #define CM_FMSEL_3E8 0x03000000
210 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
211 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
212 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
213 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
214 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
215 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
216 #define CM_C_EECS 0x00040000
217 #define CM_C_EEDI46 0x00020000
218 #define CM_C_EECK46 0x00010000
219 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
220 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
221 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
222 #define CM_EXBASEN 0x00001000 /* external bass input enable */
224 #define CM_REG_MISC_CTRL 0x18
225 #define CM_PWD 0x80000000 /* power down */
226 #define CM_RESET 0x40000000
227 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
228 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
229 #define CM_TXVX 0x08000000 /* model 037? */
230 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
231 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
232 #define CM_SPDIF48K 0x01000000 /* write */
233 #define CM_SPATUS48K 0x01000000 /* read */
234 #define CM_ENDBDAC 0x00800000 /* enable double dac */
235 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
236 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
237 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
238 #define CM_FM_EN 0x00080000 /* enable legacy FM */
239 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
240 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
241 #define CM_VIDWPDSB 0x00010000 /* model 037? */
242 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
243 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
244 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
245 #define CM_VIDWPPRT 0x00002000 /* model 037? */
246 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
247 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
248 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
249 #define CM_ENCENTER 0x00000080
250 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
251 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
252 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255 #define CM_UPDDMA_2048 0x00000000
256 #define CM_UPDDMA_1024 0x00000004
257 #define CM_UPDDMA_512 0x00000008
258 #define CM_UPDDMA_256 0x0000000C
259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
263 #define CM_REG_TDMA_POSITION 0x1C
264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
268 #define CM_REG_MIXER0 0x20
269 #define CM_REG_SBVR 0x20 /* write: sb16 version */
270 #define CM_REG_DEV 0x20 /* read: hardware device version */
272 #define CM_REG_MIXER21 0x21
273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
276 #define CM_X_SB16 0x01 /* SB16 compatible */
278 #define CM_REG_SB16_DATA 0x22
279 #define CM_REG_SB16_ADDR 0x23
281 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
286 #define CM_REG_MIXER1 0x24
287 #define CM_FMMUTE 0x80 /* mute FM */
288 #define CM_FMMUTE_SHIFT 7
289 #define CM_WSMUTE 0x40 /* mute PCM */
290 #define CM_WSMUTE_SHIFT 6
291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292 #define CM_REAR2LIN_SHIFT 5
293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
294 #define CM_REAR2FRONT_SHIFT 4
295 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296 #define CM_WAVEINL_SHIFT 3
297 #define CM_WAVEINR 0x04 /* digical wave rec. right */
298 #define CM_WAVEINR_SHIFT 2
299 #define CM_X3DEN 0x02 /* 3D surround enable */
300 #define CM_X3DEN_SHIFT 1
301 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302 #define CM_CDPLAY_SHIFT 0
304 #define CM_REG_MIXER2 0x25
305 #define CM_RAUXREN 0x80 /* AUX right capture */
306 #define CM_RAUXREN_SHIFT 7
307 #define CM_RAUXLEN 0x40 /* AUX left capture */
308 #define CM_RAUXLEN_SHIFT 6
309 #define CM_VAUXRM 0x20 /* AUX right mute */
310 #define CM_VAUXRM_SHIFT 5
311 #define CM_VAUXLM 0x10 /* AUX left mute */
312 #define CM_VAUXLM_SHIFT 4
313 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314 #define CM_VADMIC_SHIFT 1
315 #define CM_MICGAINZ 0x01 /* mic boost */
316 #define CM_MICGAINZ_SHIFT 0
318 #define CM_REG_AUX_VOL 0x26
319 #define CM_VAUXL_MASK 0xf0
320 #define CM_VAUXR_MASK 0x0f
322 #define CM_REG_MISC 0x27
323 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
324 #define CM_XGPO1 0x20
325 // #define CM_XGPBIO 0x04
326 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
327 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
328 #define CM_SPDVALID 0x02 /* spdif input valid check */
329 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
331 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
333 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
334 * or identical with AC97 codec?
336 #define CM_REG_EXTERN_CODEC CM_REG_AC97
339 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
341 #define CM_REG_MPU_PCI 0x40
344 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
346 #define CM_REG_FM_PCI 0x50
349 * access from SB-mixer port
351 #define CM_REG_EXTENT_IND 0xf0
352 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
353 #define CM_VPHONE_SHIFT 5
354 #define CM_VPHOM 0x10 /* Phone mute control */
355 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
356 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
357 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
358 #define CM_VADMIC3 0x01 /* Mic record boost */
361 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
362 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
365 #define CM_REG_PLL 0xf8
370 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
371 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
372 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
373 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375 #define CM_REG_EXT_MISC 0x90
376 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
377 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
378 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
379 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
380 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
381 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
382 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
383 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
388 #define CM_EXTENT_CODEC 0x100
389 #define CM_EXTENT_MIDI 0x2
390 #define CM_EXTENT_SYNTH 0x4
394 * channels for playback / capture
400 * flags to check device open/close
402 #define CM_OPEN_NONE 0
403 #define CM_OPEN_CH_MASK 0x01
404 #define CM_OPEN_DAC 0x10
405 #define CM_OPEN_ADC 0x20
406 #define CM_OPEN_SPDIF 0x40
407 #define CM_OPEN_MCHAN 0x80
408 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
409 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
411 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
412 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
413 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
417 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
418 #define CM_PLAYBACK_SPDF CM_SPDF_1
419 #define CM_CAPTURE_SPDF CM_SPDF_0
421 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
422 #define CM_PLAYBACK_SPDF CM_SPDF_0
423 #define CM_CAPTURE_SPDF CM_SPDF_1
432 struct snd_pcm_substream *substream;
433 u8 running; /* dac/adc running? */
434 u8 fmt; /* format bits */
437 unsigned int dma_size; /* in frames */
439 unsigned int ch; /* channel (0/1) */
440 unsigned int offset; /* physical address of the buffer */
443 /* mixer elements toggled/resumed during ac3 playback */
444 struct cmipci_mixer_auto_switches {
445 const char *name; /* switch to toggle */
446 int toggle_on; /* value to change when ac3 mode */
448 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
449 {"PCM Playback Switch", 0},
450 {"IEC958 Output Switch", 1},
451 {"IEC958 Mix Analog", 0},
452 // {"IEC958 Out To DAC", 1}, // no longer used
455 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
458 struct snd_card *card;
461 unsigned int device; /* device ID */
464 unsigned long iobase;
465 unsigned int ctrl; /* FUNCTRL0 current value */
467 struct snd_pcm *pcm; /* DAC/ADC PCM */
468 struct snd_pcm *pcm2; /* 2nd DAC */
469 struct snd_pcm *pcm_spdif; /* SPDIF */
473 unsigned int can_ac3_sw: 1;
474 unsigned int can_ac3_hw: 1;
475 unsigned int can_multi_ch: 1;
476 unsigned int can_96k: 1; /* samplerate above 48k */
477 unsigned int do_soft_ac3: 1;
479 unsigned int spdif_playback_avail: 1; /* spdif ready? */
480 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
481 int spdif_counter; /* for software AC3 */
483 unsigned int dig_status;
484 unsigned int dig_pcm_status;
486 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
488 int opened[2]; /* open mode */
489 struct mutex open_mutex;
491 unsigned int mixer_insensitive: 1;
492 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
493 int mixer_res_status[CM_SAVED_MIXERS];
495 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
498 struct snd_rawmidi *rmidi;
500 #ifdef SUPPORT_JOYSTICK
501 struct gameport *gameport;
506 #ifdef CONFIG_PM_SLEEP
507 unsigned int saved_regs[0x20];
508 unsigned char saved_mixers[0x20];
513 /* read/write operations for dword register */
514 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
516 outl(data, cm->iobase + cmd);
519 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
521 return inl(cm->iobase + cmd);
524 /* read/write operations for word register */
525 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
527 outw(data, cm->iobase + cmd);
530 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
532 return inw(cm->iobase + cmd);
535 /* read/write operations for byte register */
536 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
538 outb(data, cm->iobase + cmd);
541 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
543 return inb(cm->iobase + cmd);
546 /* bit operations for dword register */
547 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
549 unsigned int val, oval;
550 val = oval = inl(cm->iobase + cmd);
554 outl(val, cm->iobase + cmd);
558 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
560 unsigned int val, oval;
561 val = oval = inl(cm->iobase + cmd);
565 outl(val, cm->iobase + cmd);
569 /* bit operations for byte register */
570 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
572 unsigned char val, oval;
573 val = oval = inb(cm->iobase + cmd);
577 outb(val, cm->iobase + cmd);
581 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
583 unsigned char val, oval;
584 val = oval = inb(cm->iobase + cmd);
588 outb(val, cm->iobase + cmd);
598 * calculate frequency
601 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
603 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
607 for (i = 0; i < ARRAY_SIZE(rates); i++) {
608 if (rates[i] == rate)
615 #ifdef USE_VAR48KRATE
617 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
618 * does it this way .. maybe not. Never get any information from C-Media about
619 * that <werner@suse.de>.
621 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
623 unsigned int delta, tolerance;
626 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
631 tolerance = rate*CM_TOLERANCE_RATE;
633 for (xn = (1+2); xn < (0x1f+2); xn++) {
634 for (xm = (1+2); xm < (0xff+2); xm++) {
635 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
643 * If we found one, remember this,
644 * and try to find a closer one
646 if (delta < tolerance) {
658 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
659 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
660 * at the register CM_REG_FUNCTRL1 (0x04).
661 * Problem: other ways are also possible (any information about that?)
663 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
665 unsigned int reg = CM_REG_PLL + slot;
667 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
668 * for DSFC/ASFC (000 up to 111).
671 /* FIXME: Init (Do we've to set an other register first before programming?) */
673 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
674 snd_cmipci_write_b(cm, reg, rate>>8);
675 snd_cmipci_write_b(cm, reg, rate&0xff);
677 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
679 #endif /* USE_VAR48KRATE */
681 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
682 struct snd_pcm_hw_params *hw_params)
684 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
687 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *hw_params)
690 struct cmipci *cm = snd_pcm_substream_chip(substream);
691 if (params_channels(hw_params) > 2) {
692 mutex_lock(&cm->open_mutex);
693 if (cm->opened[CM_CH_PLAY]) {
694 mutex_unlock(&cm->open_mutex);
697 /* reserve the channel A */
698 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
699 mutex_unlock(&cm->open_mutex);
701 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
704 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
706 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
707 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
712 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
714 return snd_pcm_lib_free_pages(substream);
721 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
722 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
727 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
732 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
738 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
741 if (!cm->can_multi_ch || !rec->ch)
743 if (rec->fmt != 0x03) /* stereo 16bit only */
747 if (cm->can_multi_ch) {
748 spin_lock_irq(&cm->reg_lock);
750 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
751 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
753 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
754 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
757 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
759 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
762 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
764 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
765 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
768 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
770 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
771 spin_unlock_irq(&cm->reg_lock);
778 * prepare playback/capture channel
779 * channel to be used must have been set in rec->ch.
781 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
782 struct snd_pcm_substream *substream)
784 unsigned int reg, freq, freq_ext, val;
785 unsigned int period_size;
786 struct snd_pcm_runtime *runtime = substream->runtime;
790 if (snd_pcm_format_width(runtime->format) >= 16) {
792 if (snd_pcm_format_width(runtime->format) > 16)
793 rec->shift++; /* 24/32bit */
795 if (runtime->channels > 1)
797 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
798 dev_dbg(cm->card->dev, "cannot set dac channels\n");
802 rec->offset = runtime->dma_addr;
803 /* buffer and period sizes in frame */
804 rec->dma_size = runtime->buffer_size << rec->shift;
805 period_size = runtime->period_size << rec->shift;
806 if (runtime->channels > 2) {
808 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
809 period_size = (period_size * runtime->channels) / 2;
812 spin_lock_irq(&cm->reg_lock);
814 /* set buffer address */
815 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
816 snd_cmipci_write(cm, reg, rec->offset);
817 /* program sample counts */
818 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
819 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
820 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
822 /* set adc/dac flag */
823 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
828 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
829 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
831 /* set sample rate */
834 if (runtime->rate > 48000)
835 switch (runtime->rate) {
836 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
837 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
838 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
839 default: snd_BUG(); break;
842 freq = snd_cmipci_rate_freq(runtime->rate);
843 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
845 val &= ~CM_DSFC_MASK;
846 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
848 val &= ~CM_ASFC_MASK;
849 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
851 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
852 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
855 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
857 val &= ~CM_CH1FMT_MASK;
858 val |= rec->fmt << CM_CH1FMT_SHIFT;
860 val &= ~CM_CH0FMT_MASK;
861 val |= rec->fmt << CM_CH0FMT_SHIFT;
864 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
865 val |= freq_ext << (rec->ch * 2);
867 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
868 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
870 if (!rec->is_dac && cm->chip_version) {
871 if (runtime->rate > 44100)
872 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
874 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
878 spin_unlock_irq(&cm->reg_lock);
886 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
889 unsigned int inthld, chen, reset, pause;
892 inthld = CM_CH0_INT_EN << rec->ch;
893 chen = CM_CHEN0 << rec->ch;
894 reset = CM_RST_CH0 << rec->ch;
895 pause = CM_PAUSE0 << rec->ch;
897 spin_lock(&cm->reg_lock);
899 case SNDRV_PCM_TRIGGER_START:
902 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
905 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
906 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
908 case SNDRV_PCM_TRIGGER_STOP:
910 /* disable interrupt */
911 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
914 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
916 rec->needs_silencing = rec->is_dac;
918 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
919 case SNDRV_PCM_TRIGGER_SUSPEND:
921 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
923 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
924 case SNDRV_PCM_TRIGGER_RESUME:
926 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
932 spin_unlock(&cm->reg_lock);
937 * return the current pointer
939 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
940 struct snd_pcm_substream *substream)
943 unsigned int reg, rem, tries;
947 #if 1 // this seems better..
948 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
949 for (tries = 0; tries < 3; tries++) {
950 rem = snd_cmipci_read_w(cm, reg);
951 if (rem < rec->dma_size)
954 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
955 return SNDRV_PCM_POS_XRUN;
957 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
959 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
960 ptr = snd_cmipci_read(cm, reg) - rec->offset;
961 ptr = bytes_to_frames(substream->runtime, ptr);
963 if (substream->runtime->channels > 2)
964 ptr = (ptr * 2) / substream->runtime->channels;
972 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
975 struct cmipci *cm = snd_pcm_substream_chip(substream);
976 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
979 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
981 struct cmipci *cm = snd_pcm_substream_chip(substream);
982 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
991 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
994 struct cmipci *cm = snd_pcm_substream_chip(substream);
995 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
998 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
1000 struct cmipci *cm = snd_pcm_substream_chip(substream);
1001 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1006 * hw preparation for spdif
1009 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_info *uinfo)
1012 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1017 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1018 struct snd_ctl_elem_value *ucontrol)
1020 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1023 spin_lock_irq(&chip->reg_lock);
1024 for (i = 0; i < 4; i++)
1025 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1026 spin_unlock_irq(&chip->reg_lock);
1030 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1031 struct snd_ctl_elem_value *ucontrol)
1033 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1038 spin_lock_irq(&chip->reg_lock);
1039 for (i = 0; i < 4; i++)
1040 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1041 change = val != chip->dig_status;
1042 chip->dig_status = val;
1043 spin_unlock_irq(&chip->reg_lock);
1047 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1049 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1050 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1051 .info = snd_cmipci_spdif_default_info,
1052 .get = snd_cmipci_spdif_default_get,
1053 .put = snd_cmipci_spdif_default_put
1056 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1057 struct snd_ctl_elem_info *uinfo)
1059 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1064 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1065 struct snd_ctl_elem_value *ucontrol)
1067 ucontrol->value.iec958.status[0] = 0xff;
1068 ucontrol->value.iec958.status[1] = 0xff;
1069 ucontrol->value.iec958.status[2] = 0xff;
1070 ucontrol->value.iec958.status[3] = 0xff;
1074 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1076 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1077 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1078 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1079 .info = snd_cmipci_spdif_mask_info,
1080 .get = snd_cmipci_spdif_mask_get,
1083 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1084 struct snd_ctl_elem_info *uinfo)
1086 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1091 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1092 struct snd_ctl_elem_value *ucontrol)
1094 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1097 spin_lock_irq(&chip->reg_lock);
1098 for (i = 0; i < 4; i++)
1099 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1100 spin_unlock_irq(&chip->reg_lock);
1104 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1105 struct snd_ctl_elem_value *ucontrol)
1107 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1112 spin_lock_irq(&chip->reg_lock);
1113 for (i = 0; i < 4; i++)
1114 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1115 change = val != chip->dig_pcm_status;
1116 chip->dig_pcm_status = val;
1117 spin_unlock_irq(&chip->reg_lock);
1121 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1123 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1124 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1125 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1126 .info = snd_cmipci_spdif_stream_info,
1127 .get = snd_cmipci_spdif_stream_get,
1128 .put = snd_cmipci_spdif_stream_put
1134 /* save mixer setting and mute for AC3 playback */
1135 static int save_mixer_state(struct cmipci *cm)
1137 if (! cm->mixer_insensitive) {
1138 struct snd_ctl_elem_value *val;
1141 val = kmalloc(sizeof(*val), GFP_KERNEL);
1144 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1145 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1148 memset(val, 0, sizeof(*val));
1150 cm->mixer_res_status[i] = val->value.integer.value[0];
1151 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1152 event = SNDRV_CTL_EVENT_MASK_INFO;
1153 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1154 ctl->put(ctl, val); /* toggle */
1155 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1157 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1158 snd_ctl_notify(cm->card, event, &ctl->id);
1162 cm->mixer_insensitive = 1;
1168 /* restore the previously saved mixer status */
1169 static void restore_mixer_state(struct cmipci *cm)
1171 if (cm->mixer_insensitive) {
1172 struct snd_ctl_elem_value *val;
1175 val = kmalloc(sizeof(*val), GFP_KERNEL);
1178 cm->mixer_insensitive = 0; /* at first clear this;
1179 otherwise the changes will be ignored */
1180 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1181 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1185 memset(val, 0, sizeof(*val));
1186 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1188 event = SNDRV_CTL_EVENT_MASK_INFO;
1189 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1190 val->value.integer.value[0] = cm->mixer_res_status[i];
1192 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1194 snd_ctl_notify(cm->card, event, &ctl->id);
1201 /* spinlock held! */
1202 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1206 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1208 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1210 if (cm->can_ac3_hw) {
1211 /* SPD24SEL for 037, 0x02 */
1212 /* SPD24SEL for 039, 0x20, but cannot be set */
1213 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215 } else { /* can_ac3_sw */
1216 /* SPD32SEL for 037 & 039, 0x20 */
1217 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1218 /* set 176K sample rate to fix 033 HW bug */
1219 if (cm->chip_version == 33) {
1220 if (rate >= 48000) {
1221 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1223 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1229 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1230 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1232 if (cm->can_ac3_hw) {
1233 /* chip model >= 37 */
1234 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1235 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1236 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1238 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1239 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1242 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1243 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1244 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1249 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1253 rate = subs->runtime->rate;
1256 if ((err = save_mixer_state(cm)) < 0)
1259 spin_lock_irq(&cm->reg_lock);
1260 cm->spdif_playback_avail = up;
1262 /* they are controlled via "IEC958 Output Switch" */
1263 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1264 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1265 if (cm->spdif_playback_enabled)
1266 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1267 setup_ac3(cm, subs, do_ac3, rate);
1269 if (rate == 48000 || rate == 96000)
1270 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1272 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1274 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1276 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1278 /* they are controlled via "IEC958 Output Switch" */
1279 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1280 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1281 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1282 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1283 setup_ac3(cm, subs, 0, 0);
1285 spin_unlock_irq(&cm->reg_lock);
1294 /* playback - enable spdif only on the certain condition */
1295 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1297 struct cmipci *cm = snd_pcm_substream_chip(substream);
1298 int rate = substream->runtime->rate;
1299 int err, do_spdif, do_ac3 = 0;
1301 do_spdif = (rate >= 44100 && rate <= 96000 &&
1302 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1303 substream->runtime->channels == 2);
1304 if (do_spdif && cm->can_ac3_hw)
1305 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1306 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1308 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1311 /* playback (via device #2) - enable spdif always */
1312 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1314 struct cmipci *cm = snd_pcm_substream_chip(substream);
1318 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1320 do_ac3 = 1; /* doesn't matter */
1321 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1323 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1327 * Apparently, the samples last played on channel A stay in some buffer, even
1328 * after the channel is reset, and get added to the data for the rear DACs when
1329 * playing a multichannel stream on channel B. This is likely to generate
1330 * wraparounds and thus distortions.
1331 * To avoid this, we play at least one zero sample after the actual stream has
1334 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1336 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1337 unsigned int reg, val;
1339 if (rec->needs_silencing && runtime && runtime->dma_area) {
1340 /* set up a small silence buffer */
1341 memset(runtime->dma_area, 0, PAGE_SIZE);
1342 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1343 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1344 snd_cmipci_write(cm, reg, val);
1346 /* configure for 16 bits, 2 channels, 8 kHz */
1347 if (runtime->channels > 2)
1348 set_dac_channels(cm, rec, 2);
1349 spin_lock_irq(&cm->reg_lock);
1350 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1351 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1352 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1353 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1354 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1355 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1356 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1358 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1359 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1361 /* start stream (we don't need interrupts) */
1362 cm->ctrl |= CM_CHEN0 << rec->ch;
1363 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1364 spin_unlock_irq(&cm->reg_lock);
1368 /* stop and reset stream */
1369 spin_lock_irq(&cm->reg_lock);
1370 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1371 val = CM_RST_CH0 << rec->ch;
1372 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1373 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1374 spin_unlock_irq(&cm->reg_lock);
1376 rec->needs_silencing = 0;
1380 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1382 struct cmipci *cm = snd_pcm_substream_chip(substream);
1383 setup_spdif_playback(cm, substream, 0, 0);
1384 restore_mixer_state(cm);
1385 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1386 return snd_cmipci_hw_free(substream);
1389 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1391 struct cmipci *cm = snd_pcm_substream_chip(substream);
1392 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1393 return snd_cmipci_hw_free(substream);
1397 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1399 struct cmipci *cm = snd_pcm_substream_chip(substream);
1400 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1403 /* capture with spdif (via device #2) */
1404 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1406 struct cmipci *cm = snd_pcm_substream_chip(substream);
1408 spin_lock_irq(&cm->reg_lock);
1409 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1411 if (substream->runtime->rate > 48000)
1412 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1414 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1416 if (snd_pcm_format_width(substream->runtime->format) > 16)
1417 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1419 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1421 spin_unlock_irq(&cm->reg_lock);
1423 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1426 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1428 struct cmipci *cm = snd_pcm_substream_chip(subs);
1430 spin_lock_irq(&cm->reg_lock);
1431 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1432 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1433 spin_unlock_irq(&cm->reg_lock);
1435 return snd_cmipci_hw_free(subs);
1442 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1444 struct cmipci *cm = dev_id;
1445 unsigned int status, mask = 0;
1447 /* fastpath out, to ease interrupt sharing */
1448 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1449 if (!(status & CM_INTR))
1452 /* acknowledge interrupt */
1453 spin_lock(&cm->reg_lock);
1454 if (status & CM_CHINT0)
1455 mask |= CM_CH0_INT_EN;
1456 if (status & CM_CHINT1)
1457 mask |= CM_CH1_INT_EN;
1458 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1459 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1460 spin_unlock(&cm->reg_lock);
1462 if (cm->rmidi && (status & CM_UARTINT))
1463 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1466 if ((status & CM_CHINT0) && cm->channel[0].running)
1467 snd_pcm_period_elapsed(cm->channel[0].substream);
1468 if ((status & CM_CHINT1) && cm->channel[1].running)
1469 snd_pcm_period_elapsed(cm->channel[1].substream);
1478 /* playback on channel A */
1479 static const struct snd_pcm_hardware snd_cmipci_playback =
1481 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1482 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1483 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1484 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1485 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1490 .buffer_bytes_max = (128*1024),
1491 .period_bytes_min = 64,
1492 .period_bytes_max = (128*1024),
1494 .periods_max = 1024,
1498 /* capture on channel B */
1499 static const struct snd_pcm_hardware snd_cmipci_capture =
1501 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1502 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1503 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1504 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1505 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1510 .buffer_bytes_max = (128*1024),
1511 .period_bytes_min = 64,
1512 .period_bytes_max = (128*1024),
1514 .periods_max = 1024,
1518 /* playback on channel B - stereo 16bit only? */
1519 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1521 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1522 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1523 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1524 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1525 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1530 .buffer_bytes_max = (128*1024),
1531 .period_bytes_min = 64,
1532 .period_bytes_max = (128*1024),
1534 .periods_max = 1024,
1538 /* spdif playback on channel A */
1539 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1541 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1542 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1543 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1544 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1545 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1550 .buffer_bytes_max = (128*1024),
1551 .period_bytes_min = 64,
1552 .period_bytes_max = (128*1024),
1554 .periods_max = 1024,
1558 /* spdif playback on channel A (32bit, IEC958 subframes) */
1559 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1561 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1562 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1563 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1564 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1565 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1570 .buffer_bytes_max = (128*1024),
1571 .period_bytes_min = 64,
1572 .period_bytes_max = (128*1024),
1574 .periods_max = 1024,
1578 /* spdif capture on channel B */
1579 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1581 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1582 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1583 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1584 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1585 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1586 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1591 .buffer_bytes_max = (128*1024),
1592 .period_bytes_min = 64,
1593 .period_bytes_max = (128*1024),
1595 .periods_max = 1024,
1599 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1600 32000, 44100, 48000, 88200, 96000, 128000 };
1601 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1602 .count = ARRAY_SIZE(rate_constraints),
1603 .list = rate_constraints,
1608 * check device open/close
1610 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1612 int ch = mode & CM_OPEN_CH_MASK;
1614 /* FIXME: a file should wait until the device becomes free
1615 * when it's opened on blocking mode. however, since the current
1616 * pcm framework doesn't pass file pointer before actually opened,
1617 * we can't know whether blocking mode or not in open callback..
1619 mutex_lock(&cm->open_mutex);
1620 if (cm->opened[ch]) {
1621 mutex_unlock(&cm->open_mutex);
1624 cm->opened[ch] = mode;
1625 cm->channel[ch].substream = subs;
1626 if (! (mode & CM_OPEN_DAC)) {
1627 /* disable dual DAC mode */
1628 cm->channel[ch].is_dac = 0;
1629 spin_lock_irq(&cm->reg_lock);
1630 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1631 spin_unlock_irq(&cm->reg_lock);
1633 mutex_unlock(&cm->open_mutex);
1637 static void close_device_check(struct cmipci *cm, int mode)
1639 int ch = mode & CM_OPEN_CH_MASK;
1641 mutex_lock(&cm->open_mutex);
1642 if (cm->opened[ch] == mode) {
1643 if (cm->channel[ch].substream) {
1644 snd_cmipci_ch_reset(cm, ch);
1645 cm->channel[ch].running = 0;
1646 cm->channel[ch].substream = NULL;
1649 if (! cm->channel[ch].is_dac) {
1650 /* enable dual DAC mode again */
1651 cm->channel[ch].is_dac = 1;
1652 spin_lock_irq(&cm->reg_lock);
1653 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1654 spin_unlock_irq(&cm->reg_lock);
1657 mutex_unlock(&cm->open_mutex);
1663 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1665 struct cmipci *cm = snd_pcm_substream_chip(substream);
1666 struct snd_pcm_runtime *runtime = substream->runtime;
1669 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1671 runtime->hw = snd_cmipci_playback;
1672 if (cm->chip_version == 68) {
1673 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1674 SNDRV_PCM_RATE_96000;
1675 runtime->hw.rate_max = 96000;
1676 } else if (cm->chip_version == 55) {
1677 err = snd_pcm_hw_constraint_list(runtime, 0,
1678 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1681 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1682 runtime->hw.rate_max = 128000;
1684 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1685 cm->dig_pcm_status = cm->dig_status;
1689 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1691 struct cmipci *cm = snd_pcm_substream_chip(substream);
1692 struct snd_pcm_runtime *runtime = substream->runtime;
1695 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1697 runtime->hw = snd_cmipci_capture;
1698 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1699 runtime->hw.rate_min = 41000;
1700 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1701 } else if (cm->chip_version == 55) {
1702 err = snd_pcm_hw_constraint_list(runtime, 0,
1703 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1706 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1707 runtime->hw.rate_max = 128000;
1709 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1713 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1715 struct cmipci *cm = snd_pcm_substream_chip(substream);
1716 struct snd_pcm_runtime *runtime = substream->runtime;
1719 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1721 runtime->hw = snd_cmipci_playback2;
1722 mutex_lock(&cm->open_mutex);
1723 if (! cm->opened[CM_CH_PLAY]) {
1724 if (cm->can_multi_ch) {
1725 runtime->hw.channels_max = cm->max_channels;
1726 if (cm->max_channels == 4)
1727 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1728 else if (cm->max_channels == 6)
1729 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1730 else if (cm->max_channels == 8)
1731 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1734 mutex_unlock(&cm->open_mutex);
1735 if (cm->chip_version == 68) {
1736 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1737 SNDRV_PCM_RATE_96000;
1738 runtime->hw.rate_max = 96000;
1739 } else if (cm->chip_version == 55) {
1740 err = snd_pcm_hw_constraint_list(runtime, 0,
1741 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1744 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1745 runtime->hw.rate_max = 128000;
1747 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1751 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1753 struct cmipci *cm = snd_pcm_substream_chip(substream);
1754 struct snd_pcm_runtime *runtime = substream->runtime;
1757 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1759 if (cm->can_ac3_hw) {
1760 runtime->hw = snd_cmipci_playback_spdif;
1761 if (cm->chip_version >= 37) {
1762 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1763 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1766 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1767 SNDRV_PCM_RATE_96000;
1768 runtime->hw.rate_max = 96000;
1771 runtime->hw = snd_cmipci_playback_iec958_subframe;
1773 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1774 cm->dig_pcm_status = cm->dig_status;
1778 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1780 struct cmipci *cm = snd_pcm_substream_chip(substream);
1781 struct snd_pcm_runtime *runtime = substream->runtime;
1784 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1786 runtime->hw = snd_cmipci_capture_spdif;
1787 if (cm->can_96k && !(cm->chip_version == 68)) {
1788 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1789 SNDRV_PCM_RATE_96000;
1790 runtime->hw.rate_max = 96000;
1792 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1800 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1802 struct cmipci *cm = snd_pcm_substream_chip(substream);
1803 close_device_check(cm, CM_OPEN_PLAYBACK);
1807 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1809 struct cmipci *cm = snd_pcm_substream_chip(substream);
1810 close_device_check(cm, CM_OPEN_CAPTURE);
1814 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1816 struct cmipci *cm = snd_pcm_substream_chip(substream);
1817 close_device_check(cm, CM_OPEN_PLAYBACK2);
1818 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1822 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1824 struct cmipci *cm = snd_pcm_substream_chip(substream);
1825 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1829 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1831 struct cmipci *cm = snd_pcm_substream_chip(substream);
1832 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1840 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1841 .open = snd_cmipci_playback_open,
1842 .close = snd_cmipci_playback_close,
1843 .ioctl = snd_pcm_lib_ioctl,
1844 .hw_params = snd_cmipci_hw_params,
1845 .hw_free = snd_cmipci_playback_hw_free,
1846 .prepare = snd_cmipci_playback_prepare,
1847 .trigger = snd_cmipci_playback_trigger,
1848 .pointer = snd_cmipci_playback_pointer,
1851 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1852 .open = snd_cmipci_capture_open,
1853 .close = snd_cmipci_capture_close,
1854 .ioctl = snd_pcm_lib_ioctl,
1855 .hw_params = snd_cmipci_hw_params,
1856 .hw_free = snd_cmipci_hw_free,
1857 .prepare = snd_cmipci_capture_prepare,
1858 .trigger = snd_cmipci_capture_trigger,
1859 .pointer = snd_cmipci_capture_pointer,
1862 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1863 .open = snd_cmipci_playback2_open,
1864 .close = snd_cmipci_playback2_close,
1865 .ioctl = snd_pcm_lib_ioctl,
1866 .hw_params = snd_cmipci_playback2_hw_params,
1867 .hw_free = snd_cmipci_playback2_hw_free,
1868 .prepare = snd_cmipci_capture_prepare, /* channel B */
1869 .trigger = snd_cmipci_capture_trigger, /* channel B */
1870 .pointer = snd_cmipci_capture_pointer, /* channel B */
1873 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1874 .open = snd_cmipci_playback_spdif_open,
1875 .close = snd_cmipci_playback_spdif_close,
1876 .ioctl = snd_pcm_lib_ioctl,
1877 .hw_params = snd_cmipci_hw_params,
1878 .hw_free = snd_cmipci_playback_hw_free,
1879 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1880 .trigger = snd_cmipci_playback_trigger,
1881 .pointer = snd_cmipci_playback_pointer,
1884 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1885 .open = snd_cmipci_capture_spdif_open,
1886 .close = snd_cmipci_capture_spdif_close,
1887 .ioctl = snd_pcm_lib_ioctl,
1888 .hw_params = snd_cmipci_hw_params,
1889 .hw_free = snd_cmipci_capture_spdif_hw_free,
1890 .prepare = snd_cmipci_capture_spdif_prepare,
1891 .trigger = snd_cmipci_capture_trigger,
1892 .pointer = snd_cmipci_capture_pointer,
1899 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1901 struct snd_pcm *pcm;
1904 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1908 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1909 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1911 pcm->private_data = cm;
1912 pcm->info_flags = 0;
1913 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1916 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1917 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1922 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1924 struct snd_pcm *pcm;
1927 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1931 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1933 pcm->private_data = cm;
1934 pcm->info_flags = 0;
1935 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1938 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1939 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1944 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1946 struct snd_pcm *pcm;
1949 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1953 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1954 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1956 pcm->private_data = cm;
1957 pcm->info_flags = 0;
1958 strcpy(pcm->name, "C-Media PCI IEC958");
1959 cm->pcm_spdif = pcm;
1961 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1962 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1964 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1965 snd_pcm_alt_chmaps, cm->max_channels, 0,
1975 * - CM8338/8738 has a compatible mixer interface with SB16, but
1976 * lack of some elements like tone control, i/o gain and AGC.
1977 * - Access to native registers:
1979 * - Output mute switches
1982 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1984 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1985 outb(data, s->iobase + CM_REG_SB16_DATA);
1988 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1992 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1993 v = inb(s->iobase + CM_REG_SB16_DATA);
1998 * general mixer element
2000 struct cmipci_sb_reg {
2001 unsigned int left_reg, right_reg;
2002 unsigned int left_shift, right_shift;
2004 unsigned int invert: 1;
2005 unsigned int stereo: 1;
2008 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
2009 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
2011 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2012 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2013 .info = snd_cmipci_info_volume, \
2014 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2015 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2018 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2019 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2020 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2021 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2023 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2025 r->left_reg = val & 0xff;
2026 r->right_reg = (val >> 8) & 0xff;
2027 r->left_shift = (val >> 16) & 0x07;
2028 r->right_shift = (val >> 19) & 0x07;
2029 r->invert = (val >> 22) & 1;
2030 r->stereo = (val >> 23) & 1;
2031 r->mask = (val >> 24) & 0xff;
2034 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2035 struct snd_ctl_elem_info *uinfo)
2037 struct cmipci_sb_reg reg;
2039 cmipci_sb_reg_decode(®, kcontrol->private_value);
2040 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2041 uinfo->count = reg.stereo + 1;
2042 uinfo->value.integer.min = 0;
2043 uinfo->value.integer.max = reg.mask;
2047 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2048 struct snd_ctl_elem_value *ucontrol)
2050 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2051 struct cmipci_sb_reg reg;
2054 cmipci_sb_reg_decode(®, kcontrol->private_value);
2055 spin_lock_irq(&cm->reg_lock);
2056 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2058 val = reg.mask - val;
2059 ucontrol->value.integer.value[0] = val;
2061 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2063 val = reg.mask - val;
2064 ucontrol->value.integer.value[1] = val;
2066 spin_unlock_irq(&cm->reg_lock);
2070 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2071 struct snd_ctl_elem_value *ucontrol)
2073 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2074 struct cmipci_sb_reg reg;
2076 int left, right, oleft, oright;
2078 cmipci_sb_reg_decode(®, kcontrol->private_value);
2079 left = ucontrol->value.integer.value[0] & reg.mask;
2081 left = reg.mask - left;
2082 left <<= reg.left_shift;
2084 right = ucontrol->value.integer.value[1] & reg.mask;
2086 right = reg.mask - right;
2087 right <<= reg.right_shift;
2090 spin_lock_irq(&cm->reg_lock);
2091 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2092 left |= oleft & ~(reg.mask << reg.left_shift);
2093 change = left != oleft;
2095 if (reg.left_reg != reg.right_reg) {
2096 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2097 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2100 right |= oright & ~(reg.mask << reg.right_shift);
2101 change |= right != oright;
2102 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2104 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2105 spin_unlock_irq(&cm->reg_lock);
2110 * input route (left,right) -> (left,right)
2112 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2113 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2114 .info = snd_cmipci_info_input_sw, \
2115 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2116 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2119 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2120 struct snd_ctl_elem_info *uinfo)
2122 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2124 uinfo->value.integer.min = 0;
2125 uinfo->value.integer.max = 1;
2129 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_value *ucontrol)
2132 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2133 struct cmipci_sb_reg reg;
2136 cmipci_sb_reg_decode(®, kcontrol->private_value);
2137 spin_lock_irq(&cm->reg_lock);
2138 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2139 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2140 spin_unlock_irq(&cm->reg_lock);
2141 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2142 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2143 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2144 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2148 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
2151 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2152 struct cmipci_sb_reg reg;
2154 int val1, val2, oval1, oval2;
2156 cmipci_sb_reg_decode(®, kcontrol->private_value);
2157 spin_lock_irq(&cm->reg_lock);
2158 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2159 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2160 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2161 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2162 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2163 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2164 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2165 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2166 change = val1 != oval1 || val2 != oval2;
2167 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2168 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2169 spin_unlock_irq(&cm->reg_lock);
2174 * native mixer switches/volumes
2177 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2178 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2179 .info = snd_cmipci_info_native_mixer, \
2180 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2181 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2184 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2185 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2186 .info = snd_cmipci_info_native_mixer, \
2187 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2188 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2191 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2192 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2193 .info = snd_cmipci_info_native_mixer, \
2194 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2195 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2198 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2199 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2200 .info = snd_cmipci_info_native_mixer, \
2201 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2202 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2205 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_info *uinfo)
2208 struct cmipci_sb_reg reg;
2210 cmipci_sb_reg_decode(®, kcontrol->private_value);
2211 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2212 uinfo->count = reg.stereo + 1;
2213 uinfo->value.integer.min = 0;
2214 uinfo->value.integer.max = reg.mask;
2219 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2220 struct snd_ctl_elem_value *ucontrol)
2222 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2223 struct cmipci_sb_reg reg;
2224 unsigned char oreg, val;
2226 cmipci_sb_reg_decode(®, kcontrol->private_value);
2227 spin_lock_irq(&cm->reg_lock);
2228 oreg = inb(cm->iobase + reg.left_reg);
2229 val = (oreg >> reg.left_shift) & reg.mask;
2231 val = reg.mask - val;
2232 ucontrol->value.integer.value[0] = val;
2234 val = (oreg >> reg.right_shift) & reg.mask;
2236 val = reg.mask - val;
2237 ucontrol->value.integer.value[1] = val;
2239 spin_unlock_irq(&cm->reg_lock);
2243 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2246 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2247 struct cmipci_sb_reg reg;
2248 unsigned char oreg, nreg, val;
2250 cmipci_sb_reg_decode(®, kcontrol->private_value);
2251 spin_lock_irq(&cm->reg_lock);
2252 oreg = inb(cm->iobase + reg.left_reg);
2253 val = ucontrol->value.integer.value[0] & reg.mask;
2255 val = reg.mask - val;
2256 nreg = oreg & ~(reg.mask << reg.left_shift);
2257 nreg |= (val << reg.left_shift);
2259 val = ucontrol->value.integer.value[1] & reg.mask;
2261 val = reg.mask - val;
2262 nreg &= ~(reg.mask << reg.right_shift);
2263 nreg |= (val << reg.right_shift);
2265 outb(nreg, cm->iobase + reg.left_reg);
2266 spin_unlock_irq(&cm->reg_lock);
2267 return (nreg != oreg);
2271 * special case - check mixer sensitivity
2273 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_value *ucontrol)
2276 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2277 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2280 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2281 struct snd_ctl_elem_value *ucontrol)
2283 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2284 if (cm->mixer_insensitive) {
2288 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2292 static struct snd_kcontrol_new snd_cmipci_mixers[] = {
2293 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2294 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2295 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2296 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2297 { /* switch with sensitivity */
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = "PCM Playback Switch",
2300 .info = snd_cmipci_info_native_mixer,
2301 .get = snd_cmipci_get_native_mixer_sensitive,
2302 .put = snd_cmipci_put_native_mixer_sensitive,
2303 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2305 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2306 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2307 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2308 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2309 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2310 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2311 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2312 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2313 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2314 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2315 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2316 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2317 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2318 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2319 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2320 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2321 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2322 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2323 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2324 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2325 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2326 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2327 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2334 struct cmipci_switch_args {
2335 int reg; /* register index */
2336 unsigned int mask; /* mask bits */
2337 unsigned int mask_on; /* mask bits to turn on */
2338 unsigned int is_byte: 1; /* byte access? */
2339 unsigned int ac3_sensitive: 1; /* access forbidden during
2340 * non-audio operation?
2344 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2346 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2347 struct snd_ctl_elem_value *ucontrol,
2348 struct cmipci_switch_args *args)
2351 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2353 spin_lock_irq(&cm->reg_lock);
2354 if (args->ac3_sensitive && cm->mixer_insensitive) {
2355 ucontrol->value.integer.value[0] = 0;
2356 spin_unlock_irq(&cm->reg_lock);
2360 val = inb(cm->iobase + args->reg);
2362 val = snd_cmipci_read(cm, args->reg);
2363 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2364 spin_unlock_irq(&cm->reg_lock);
2368 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2369 struct snd_ctl_elem_value *ucontrol)
2371 struct cmipci_switch_args *args;
2372 args = (struct cmipci_switch_args *)kcontrol->private_value;
2373 if (snd_BUG_ON(!args))
2375 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2378 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2379 struct snd_ctl_elem_value *ucontrol,
2380 struct cmipci_switch_args *args)
2384 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2386 spin_lock_irq(&cm->reg_lock);
2387 if (args->ac3_sensitive && cm->mixer_insensitive) {
2389 spin_unlock_irq(&cm->reg_lock);
2393 val = inb(cm->iobase + args->reg);
2395 val = snd_cmipci_read(cm, args->reg);
2396 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2397 args->mask_on : (args->mask & ~args->mask_on));
2400 if (ucontrol->value.integer.value[0])
2401 val |= args->mask_on;
2403 val |= (args->mask & ~args->mask_on);
2405 outb((unsigned char)val, cm->iobase + args->reg);
2407 snd_cmipci_write(cm, args->reg, val);
2409 spin_unlock_irq(&cm->reg_lock);
2413 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2414 struct snd_ctl_elem_value *ucontrol)
2416 struct cmipci_switch_args *args;
2417 args = (struct cmipci_switch_args *)kcontrol->private_value;
2418 if (snd_BUG_ON(!args))
2420 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2423 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2424 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2427 .mask_on = xmask_on, \
2428 .is_byte = xis_byte, \
2429 .ac3_sensitive = xac3, \
2432 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2433 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2435 #if 0 /* these will be controlled in pcm device */
2436 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2437 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2439 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2440 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2441 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2442 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2443 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2444 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2445 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2446 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2447 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2448 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2449 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2450 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2451 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2452 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2454 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2456 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2458 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2459 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2460 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2461 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2462 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2464 #define DEFINE_SWITCH(sname, stype, sarg) \
2467 .info = snd_cmipci_uswitch_info, \
2468 .get = snd_cmipci_uswitch_get, \
2469 .put = snd_cmipci_uswitch_put, \
2470 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2473 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2474 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2478 * callbacks for spdif output switch
2479 * needs toggle two registers..
2481 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2482 struct snd_ctl_elem_value *ucontrol)
2485 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2486 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2490 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2491 struct snd_ctl_elem_value *ucontrol)
2493 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2495 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2496 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2498 if (ucontrol->value.integer.value[0]) {
2499 if (chip->spdif_playback_avail)
2500 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2502 if (chip->spdif_playback_avail)
2503 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2506 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2511 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2512 struct snd_ctl_elem_info *uinfo)
2514 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2515 static const char *const texts[3] = {
2516 "Line-In", "Rear Output", "Bass Output"
2519 return snd_ctl_enum_info(uinfo, 1,
2520 cm->chip_version >= 39 ? 3 : 2, texts);
2523 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2526 if (cm->chip_version >= 39) {
2527 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2528 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2531 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2532 if (val & CM_REAR2LIN)
2537 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2538 struct snd_ctl_elem_value *ucontrol)
2540 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2542 spin_lock_irq(&cm->reg_lock);
2543 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2544 spin_unlock_irq(&cm->reg_lock);
2548 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2549 struct snd_ctl_elem_value *ucontrol)
2551 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2554 spin_lock_irq(&cm->reg_lock);
2555 if (ucontrol->value.enumerated.item[0] == 2)
2556 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2558 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2559 if (ucontrol->value.enumerated.item[0] == 1)
2560 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2562 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2563 spin_unlock_irq(&cm->reg_lock);
2567 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2568 struct snd_ctl_elem_info *uinfo)
2570 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2572 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2575 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2576 struct snd_ctl_elem_value *ucontrol)
2578 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2579 /* same bit as spdi_phase */
2580 spin_lock_irq(&cm->reg_lock);
2581 ucontrol->value.enumerated.item[0] =
2582 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2583 spin_unlock_irq(&cm->reg_lock);
2587 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2588 struct snd_ctl_elem_value *ucontrol)
2590 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2593 spin_lock_irq(&cm->reg_lock);
2594 if (ucontrol->value.enumerated.item[0])
2595 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2597 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2598 spin_unlock_irq(&cm->reg_lock);
2602 /* both for CM8338/8738 */
2603 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2604 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2606 .name = "Line-In Mode",
2607 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2608 .info = snd_cmipci_line_in_mode_info,
2609 .get = snd_cmipci_line_in_mode_get,
2610 .put = snd_cmipci_line_in_mode_put,
2614 /* for non-multichannel chips */
2615 static struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2616 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2618 /* only for CM8738 */
2619 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2620 #if 0 /* controlled in pcm device */
2621 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2622 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2623 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2625 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2626 { .name = "IEC958 Output Switch",
2627 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2628 .info = snd_cmipci_uswitch_info,
2629 .get = snd_cmipci_spdout_enable_get,
2630 .put = snd_cmipci_spdout_enable_put,
2632 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2633 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2634 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2635 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2636 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2637 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2640 /* only for model 033/037 */
2641 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2642 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2643 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2644 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2647 /* only for model 039 or later */
2648 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2649 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2650 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2652 .name = "Mic-In Mode",
2653 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2654 .info = snd_cmipci_mic_in_mode_info,
2655 .get = snd_cmipci_mic_in_mode_get,
2656 .put = snd_cmipci_mic_in_mode_put,
2660 /* card control switches */
2661 static struct snd_kcontrol_new snd_cmipci_modem_switch =
2662 DEFINE_CARD_SWITCH("Modem", modem);
2665 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2667 struct snd_card *card;
2668 struct snd_kcontrol_new *sw;
2669 struct snd_kcontrol *kctl;
2673 if (snd_BUG_ON(!cm || !cm->card))
2678 strcpy(card->mixername, "CMedia PCI");
2680 spin_lock_irq(&cm->reg_lock);
2681 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2682 spin_unlock_irq(&cm->reg_lock);
2684 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2685 if (cm->chip_version == 68) { // 8768 has no PCM volume
2686 if (!strcmp(snd_cmipci_mixers[idx].name,
2687 "PCM Playback Volume"))
2690 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2694 /* mixer switches */
2695 sw = snd_cmipci_mixer_switches;
2696 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2697 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2701 if (! cm->can_multi_ch) {
2702 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2706 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2707 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2708 sw = snd_cmipci_8738_mixer_switches;
2709 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2710 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2714 if (cm->can_ac3_hw) {
2715 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2717 kctl->id.device = pcm_spdif_device;
2718 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2720 kctl->id.device = pcm_spdif_device;
2721 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2723 kctl->id.device = pcm_spdif_device;
2725 if (cm->chip_version <= 37) {
2726 sw = snd_cmipci_old_mixer_switches;
2727 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2728 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2734 if (cm->chip_version >= 39) {
2735 sw = snd_cmipci_extra_mixer_switches;
2736 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2737 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2745 * newer chips don't have the register bits to force modem link
2746 * detection; the bit that was FLINKON now mutes CH1
2748 if (cm->chip_version < 39) {
2749 err = snd_ctl_add(cm->card,
2750 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2755 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2756 struct snd_ctl_elem_id elem_id;
2757 struct snd_kcontrol *ctl;
2758 memset(&elem_id, 0, sizeof(elem_id));
2759 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2760 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2761 ctl = snd_ctl_find_id(cm->card, &elem_id);
2763 cm->mixer_res_ctl[idx] = ctl;
2774 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2775 struct snd_info_buffer *buffer)
2777 struct cmipci *cm = entry->private_data;
2780 snd_iprintf(buffer, "%s\n", cm->card->longname);
2781 for (i = 0; i < 0x94; i++) {
2784 v = inb(cm->iobase + i);
2786 snd_iprintf(buffer, "\n%02x:", i);
2787 snd_iprintf(buffer, " %02x", v);
2789 snd_iprintf(buffer, "\n");
2792 static void snd_cmipci_proc_init(struct cmipci *cm)
2794 struct snd_info_entry *entry;
2796 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2797 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2800 static const struct pci_device_id snd_cmipci_ids[] = {
2801 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2802 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2803 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2804 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2805 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2811 * check chip version and capabilities
2812 * driver name is modified according to the chip model
2814 static void query_chip(struct cmipci *cm)
2816 unsigned int detect;
2818 /* check reg 0Ch, bit 24-31 */
2819 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2821 /* check reg 08h, bit 24-28 */
2822 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2825 cm->chip_version = 33;
2826 if (cm->do_soft_ac3)
2832 cm->chip_version = 37;
2836 cm->chip_version = 39;
2840 cm->max_channels = 2;
2842 if (detect & CM_CHIP_039) {
2843 cm->chip_version = 39;
2844 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2845 cm->max_channels = 6;
2847 cm->max_channels = 4;
2848 } else if (detect & CM_CHIP_8768) {
2849 cm->chip_version = 68;
2850 cm->max_channels = 8;
2853 cm->chip_version = 55;
2854 cm->max_channels = 6;
2858 cm->can_multi_ch = 1;
2862 #ifdef SUPPORT_JOYSTICK
2863 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2865 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2866 struct gameport *gp;
2867 struct resource *r = NULL;
2870 if (joystick_port[dev] == 0)
2873 if (joystick_port[dev] == 1) { /* auto-detect */
2874 for (i = 0; ports[i]; i++) {
2876 r = request_region(io_port, 1, "CMIPCI gameport");
2881 io_port = joystick_port[dev];
2882 r = request_region(io_port, 1, "CMIPCI gameport");
2886 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2890 cm->gameport = gp = gameport_allocate_port();
2892 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2893 release_and_free_resource(r);
2896 gameport_set_name(gp, "C-Media Gameport");
2897 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2898 gameport_set_dev_parent(gp, &cm->pci->dev);
2900 gameport_set_port_data(gp, r);
2902 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2904 gameport_register_port(cm->gameport);
2909 static void snd_cmipci_free_gameport(struct cmipci *cm)
2912 struct resource *r = gameport_get_port_data(cm->gameport);
2914 gameport_unregister_port(cm->gameport);
2915 cm->gameport = NULL;
2917 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2918 release_and_free_resource(r);
2922 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2923 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2926 static int snd_cmipci_free(struct cmipci *cm)
2929 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2930 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2931 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2932 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2933 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2934 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2935 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2938 snd_cmipci_mixer_write(cm, 0, 0);
2940 free_irq(cm->irq, cm);
2943 snd_cmipci_free_gameport(cm);
2944 pci_release_regions(cm->pci);
2945 pci_disable_device(cm->pci);
2950 static int snd_cmipci_dev_free(struct snd_device *device)
2952 struct cmipci *cm = device->device_data;
2953 return snd_cmipci_free(cm);
2956 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2960 struct snd_opl3 *opl3;
2966 if (cm->chip_version >= 39) {
2967 /* first try FM regs in PCI port range */
2968 iosynth = cm->iobase + CM_REG_FM_PCI;
2969 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2970 OPL3_HW_OPL3, 1, &opl3);
2975 /* then try legacy ports */
2976 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2979 case 0x3E8: val |= CM_FMSEL_3E8; break;
2980 case 0x3E0: val |= CM_FMSEL_3E0; break;
2981 case 0x3C8: val |= CM_FMSEL_3C8; break;
2982 case 0x388: val |= CM_FMSEL_388; break;
2986 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2988 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2990 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2991 OPL3_HW_OPL3, 0, &opl3) < 0) {
2992 dev_err(cm->card->dev,
2993 "no OPL device at %#lx, skipping...\n",
2998 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2999 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
3005 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3006 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3010 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3011 int dev, struct cmipci **rcmipci)
3015 static struct snd_device_ops ops = {
3016 .dev_free = snd_cmipci_dev_free,
3020 int integrated_midi = 0;
3022 int pcm_index, pcm_spdif_index;
3023 static const struct pci_device_id intel_82437vx[] = {
3024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3030 if ((err = pci_enable_device(pci)) < 0)
3033 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3035 pci_disable_device(pci);
3039 spin_lock_init(&cm->reg_lock);
3040 mutex_init(&cm->open_mutex);
3041 cm->device = pci->device;
3045 cm->channel[0].ch = 0;
3046 cm->channel[1].ch = 1;
3047 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3049 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3051 pci_disable_device(pci);
3054 cm->iobase = pci_resource_start(pci, 0);
3056 if (request_irq(pci->irq, snd_cmipci_interrupt,
3057 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3058 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3059 snd_cmipci_free(cm);
3064 pci_set_master(cm->pci);
3067 * check chip version, max channels and capabilities
3070 cm->chip_version = 0;
3071 cm->max_channels = 2;
3072 cm->do_soft_ac3 = soft_ac3[dev];
3074 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3075 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3077 /* added -MCx suffix for chip supporting multi-channels */
3078 if (cm->can_multi_ch)
3079 sprintf(cm->card->driver + strlen(cm->card->driver),
3080 "-MC%d", cm->max_channels);
3081 else if (cm->can_ac3_sw)
3082 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3084 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3085 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3088 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3090 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3093 /* initialize codec registers */
3094 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3095 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3096 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3097 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3098 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3099 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3100 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3102 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3103 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3105 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3107 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3109 if (cm->chip_version) {
3110 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3111 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3113 /* Set Bus Master Request */
3114 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3116 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3117 switch (pci->device) {
3118 case PCI_DEVICE_ID_CMEDIA_CM8738:
3119 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3120 if (!pci_dev_present(intel_82437vx))
3121 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3127 if (cm->chip_version < 68) {
3128 val = pci->device < 0x110 ? 8338 : 8738;
3130 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3138 switch ((pci->subsystem_vendor << 16) |
3139 pci->subsystem_device) {
3154 sprintf(card->shortname, "C-Media CMI%d", val);
3155 if (cm->chip_version < 68)
3156 sprintf(modelstr, " (model %d)", cm->chip_version);
3159 sprintf(card->longname, "%s%s at %#lx, irq %i",
3160 card->shortname, modelstr, cm->iobase, cm->irq);
3162 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3163 snd_cmipci_free(cm);
3167 if (cm->chip_version >= 39) {
3168 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3169 if (val != 0x00 && val != 0xff) {
3170 iomidi = cm->iobase + CM_REG_MPU_PCI;
3171 integrated_midi = 1;
3174 if (!integrated_midi) {
3176 iomidi = mpu_port[dev];
3178 case 0x320: val = CM_VMPU_320; break;
3179 case 0x310: val = CM_VMPU_310; break;
3180 case 0x300: val = CM_VMPU_300; break;
3181 case 0x330: val = CM_VMPU_330; break;
3186 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3188 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3189 if (inb(iomidi + 1) == 0xff) {
3190 dev_err(cm->card->dev,
3191 "cannot enable MPU-401 port at %#lx\n",
3193 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3200 if (cm->chip_version < 68) {
3201 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3207 snd_cmipci_mixer_write(cm, 0, 0);
3209 snd_cmipci_proc_init(cm);
3211 /* create pcm devices */
3212 pcm_index = pcm_spdif_index = 0;
3213 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3216 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3219 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3220 pcm_spdif_index = pcm_index;
3221 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3225 /* create mixer interface & switches */
3226 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3230 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3233 MPU401_INFO_INTEGRATED : 0) |
3234 MPU401_INFO_IRQ_HOOK,
3235 -1, &cm->rmidi)) < 0) {
3236 dev_err(cm->card->dev,
3237 "no UART401 device at 0x%lx\n", iomidi);
3241 #ifdef USE_VAR48KRATE
3242 for (val = 0; val < ARRAY_SIZE(rates); val++)
3243 snd_cmipci_set_pll(cm, rates[val], val);
3246 * (Re-)Enable external switch spdo_48k
3248 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3249 #endif /* USE_VAR48KRATE */
3251 if (snd_cmipci_create_gameport(cm, dev) < 0)
3252 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3261 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3263 static int snd_cmipci_probe(struct pci_dev *pci,
3264 const struct pci_device_id *pci_id)
3267 struct snd_card *card;
3271 if (dev >= SNDRV_CARDS)
3273 if (! enable[dev]) {
3278 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3283 switch (pci->device) {
3284 case PCI_DEVICE_ID_CMEDIA_CM8738:
3285 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3286 strcpy(card->driver, "CMI8738");
3288 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3289 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3290 strcpy(card->driver, "CMI8338");
3293 strcpy(card->driver, "CMIPCI");
3297 err = snd_cmipci_create(card, pci, dev, &cm);
3301 card->private_data = cm;
3303 err = snd_card_register(card);
3307 pci_set_drvdata(pci, card);
3312 snd_card_free(card);
3316 static void snd_cmipci_remove(struct pci_dev *pci)
3318 snd_card_free(pci_get_drvdata(pci));
3322 #ifdef CONFIG_PM_SLEEP
3326 static unsigned char saved_regs[] = {
3327 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3328 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3329 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3330 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3331 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3334 static unsigned char saved_mixers[] = {
3335 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3336 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3337 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3338 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3339 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3340 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3341 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3342 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3345 static int snd_cmipci_suspend(struct device *dev)
3347 struct snd_card *card = dev_get_drvdata(dev);
3348 struct cmipci *cm = card->private_data;
3351 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3353 snd_pcm_suspend_all(cm->pcm);
3354 snd_pcm_suspend_all(cm->pcm2);
3355 snd_pcm_suspend_all(cm->pcm_spdif);
3357 /* save registers */
3358 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3359 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3360 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3361 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3364 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3368 static int snd_cmipci_resume(struct device *dev)
3370 struct snd_card *card = dev_get_drvdata(dev);
3371 struct cmipci *cm = card->private_data;
3374 /* reset / initialize to a sane state */
3375 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3376 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3377 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3378 snd_cmipci_mixer_write(cm, 0, 0);
3380 /* restore registers */
3381 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3382 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3383 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3384 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3386 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3390 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3391 #define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3393 #define SND_CMIPCI_PM_OPS NULL
3394 #endif /* CONFIG_PM_SLEEP */
3396 static struct pci_driver cmipci_driver = {
3397 .name = KBUILD_MODNAME,
3398 .id_table = snd_cmipci_ids,
3399 .probe = snd_cmipci_probe,
3400 .remove = snd_cmipci_remove,
3402 .pm = SND_CMIPCI_PM_OPS,
3406 module_pci_driver(cmipci_driver);